diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml index 6a67375..4f85ede 100644 --- a/.github/workflows/check.yml +++ b/.github/workflows/check.yml @@ -9,12 +9,12 @@ jobs: strategy: matrix: mcu: [bcm2835, bcm2837, bcm2711] - rust-version: [1.61.0, 1.62.1, 1.63.0, 1.64.0, 1.65.0, 1.66.1, 1.67.1, 1.68.0] + rust-version: [1.65.0, 1.66.1, 1.67.1, 1.68.2, 1.69.0, 1.70.0, 1.71.1, 1.72.1, 1.73.0] runs-on: ubuntu-latest steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 - name: Install Rust run: rustup default ${{ matrix.rust-version }} diff --git a/crates/bcm2711-lpa/Cargo.toml b/crates/bcm2711-lpa/Cargo.toml index 9c22170..90b37bb 100644 --- a/crates/bcm2711-lpa/Cargo.toml +++ b/crates/bcm2711-lpa/Cargo.toml @@ -1,9 +1,9 @@ [package] name = "bcm2711-lpa" -version = "0.1.0" +version = "0.2.0" authors = ["Po-Yi Tsai "] edition = "2021" -rust-version = "1.61.0" +rust-version = "1.65.0" description = "Peripheral access crate for BCM2711 found in the Raspberry Pi 4." repository = "https://github.com/abt8601/raspi-pacs" license = "Unlicense" diff --git a/crates/bcm2711-lpa/src/aux.rs b/crates/bcm2711-lpa/src/aux.rs index 5380cb2..e9cf956 100644 --- a/crates/bcm2711-lpa/src/aux.rs +++ b/crates/bcm2711-lpa/src/aux.rs @@ -1,16 +1,19 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Interrupt status"] pub irq: IRQ, #[doc = "0x04 - Enable sub-peripherals"] pub enables: ENABLES, } -#[doc = "IRQ (rw) register accessor: an alias for `Reg`"] +#[doc = "IRQ (rw) register accessor: Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq`] +module"] pub type IRQ = crate::Reg; #[doc = "Interrupt status"] pub mod irq; -#[doc = "ENABLES (rw) register accessor: an alias for `Reg`"] +#[doc = "ENABLES (rw) register accessor: Enable sub-peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enables::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enables::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enables`] +module"] pub type ENABLES = crate::Reg; #[doc = "Enable sub-peripherals"] pub mod enables; diff --git a/crates/bcm2711-lpa/src/aux/enables.rs b/crates/bcm2711-lpa/src/aux/enables.rs index eb9fc6d..c84adb4 100644 --- a/crates/bcm2711-lpa/src/aux/enables.rs +++ b/crates/bcm2711-lpa/src/aux/enables.rs @@ -1,51 +1,19 @@ #[doc = "Register `ENABLES` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ENABLES` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UART_1` reader - UART1 enabled"] -pub type UART_1_R = crate::BitReader; +pub type UART_1_R = crate::BitReader; #[doc = "Field `UART_1` writer - UART1 enabled"] -pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +pub type UART_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_1` reader - SPI1 enabled"] -pub type SPI_1_R = crate::BitReader; +pub type SPI_1_R = crate::BitReader; #[doc = "Field `SPI_1` writer - SPI1 enabled"] -pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +pub type SPI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_2` reader - SPI2 enabled"] -pub type SPI_2_R = crate::BitReader; +pub type SPI_2_R = crate::BitReader; #[doc = "Field `SPI_2` writer - SPI2 enabled"] -pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +pub type SPI_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - UART1 enabled"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { SPI_2_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLES") + .field("spi_2", &format_args!("{}", self.spi_2().bit())) + .field("spi_1", &format_args!("{}", self.spi_1().bit())) + .field("uart_1", &format_args!("{}", self.uart_1().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - UART1 enabled"] #[inline(always)] #[must_use] - pub fn uart_1(&mut self) -> UART_1_W<0> { + pub fn uart_1(&mut self) -> UART_1_W { UART_1_W::new(self) } #[doc = "Bit 1 - SPI1 enabled"] #[inline(always)] #[must_use] - pub fn spi_1(&mut self) -> SPI_1_W<1> { + pub fn spi_1(&mut self) -> SPI_1_W { SPI_1_W::new(self) } #[doc = "Bit 2 - SPI2 enabled"] #[inline(always)] #[must_use] - pub fn spi_2(&mut self) -> SPI_2_W<2> { + pub fn spi_2(&mut self) -> SPI_2_W { SPI_2_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable sub-peripherals\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enables](index.html) module"] +#[doc = "Enable sub-peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enables::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enables::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLES_SPEC; impl crate::RegisterSpec for ENABLES_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enables::R](R) reader structure"] -impl crate::Readable for ENABLES_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [enables::W](W) writer structure"] +#[doc = "`read()` method returns [`enables::R`](R) reader structure"] +impl crate::Readable for ENABLES_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enables::W`](W) writer structure"] impl crate::Writable for ENABLES_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/aux/irq.rs b/crates/bcm2711-lpa/src/aux/irq.rs index a59c319..785d02a 100644 --- a/crates/bcm2711-lpa/src/aux/irq.rs +++ b/crates/bcm2711-lpa/src/aux/irq.rs @@ -1,51 +1,19 @@ #[doc = "Register `IRQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UART_1` reader - UART1 interrupt active"] -pub type UART_1_R = crate::BitReader; +pub type UART_1_R = crate::BitReader; #[doc = "Field `UART_1` writer - UART1 interrupt active"] -pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +pub type UART_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_1` reader - SPI1 interrupt active"] -pub type SPI_1_R = crate::BitReader; +pub type SPI_1_R = crate::BitReader; #[doc = "Field `SPI_1` writer - SPI1 interrupt active"] -pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +pub type SPI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_2` reader - SPI2 interrupt active"] -pub type SPI_2_R = crate::BitReader; +pub type SPI_2_R = crate::BitReader; #[doc = "Field `SPI_2` writer - SPI2 interrupt active"] -pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +pub type SPI_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - UART1 interrupt active"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { SPI_2_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IRQ") + .field("spi_2", &format_args!("{}", self.spi_2().bit())) + .field("spi_1", &format_args!("{}", self.spi_1().bit())) + .field("uart_1", &format_args!("{}", self.uart_1().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - UART1 interrupt active"] #[inline(always)] #[must_use] - pub fn uart_1(&mut self) -> UART_1_W<0> { + pub fn uart_1(&mut self) -> UART_1_W { UART_1_W::new(self) } #[doc = "Bit 1 - SPI1 interrupt active"] #[inline(always)] #[must_use] - pub fn spi_1(&mut self) -> SPI_1_W<1> { + pub fn spi_1(&mut self) -> SPI_1_W { SPI_1_W::new(self) } #[doc = "Bit 2 - SPI2 interrupt active"] #[inline(always)] #[must_use] - pub fn spi_2(&mut self) -> SPI_2_W<2> { + pub fn spi_2(&mut self) -> SPI_2_W { SPI_2_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq](index.html) module"] +#[doc = "Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRQ_SPEC; impl crate::RegisterSpec for IRQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irq::R](R) reader structure"] -impl crate::Readable for IRQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irq::W](W) writer structure"] +#[doc = "`read()` method returns [`irq::R`](R) reader structure"] +impl crate::Readable for IRQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq::W`](W) writer structure"] impl crate::Writable for IRQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/bsc0.rs b/crates/bcm2711-lpa/src/bsc0.rs index 8ccfb52..0d1c120 100644 --- a/crates/bcm2711-lpa/src/bsc0.rs +++ b/crates/bcm2711-lpa/src/bsc0.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control"] pub c: C, @@ -18,35 +19,43 @@ pub struct RegisterBlock { #[doc = "0x1c - Clock stretch timeout (broken on 283x)"] pub clkt: CLKT, } -#[doc = "C (rw) register accessor: an alias for `Reg`"] +#[doc = "C (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c`] +module"] pub type C = crate::Reg; #[doc = "Control"] pub mod c; -#[doc = "S (rw) register accessor: an alias for `Reg`"] +#[doc = "S (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s`] +module"] pub type S = crate::Reg; #[doc = "Status"] pub mod s; -#[doc = "DLEN (rw) register accessor: an alias for `Reg`"] +#[doc = "DLEN (rw) register accessor: Data length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlen`] +module"] pub type DLEN = crate::Reg; #[doc = "Data length"] pub mod dlen; -#[doc = "A (rw) register accessor: an alias for `Reg`"] +#[doc = "A (rw) register accessor: Slave address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a`] +module"] pub type A = crate::Reg; #[doc = "Slave address"] pub mod a; -#[doc = "FIFO (rw) register accessor: an alias for `Reg`"] +#[doc = "FIFO (rw) register accessor: Data FIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`] +module"] pub type FIFO = crate::Reg; #[doc = "Data FIFO"] pub mod fifo; -#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV (rw) register accessor: Clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div`] +module"] pub type DIV = crate::Reg; #[doc = "Clock divider"] pub mod div; -#[doc = "DEL (rw) register accessor: an alias for `Reg`"] +#[doc = "DEL (rw) register accessor: Data delay (Values must be under CDIV / 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`del::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`del::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@del`] +module"] pub type DEL = crate::Reg; #[doc = "Data delay (Values must be under CDIV / 2)"] pub mod del; -#[doc = "CLKT (rw) register accessor: an alias for `Reg`"] +#[doc = "CLKT (rw) register accessor: Clock stretch timeout (broken on 283x)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkt`] +module"] pub type CLKT = crate::Reg; #[doc = "Clock stretch timeout (broken on 283x)"] pub mod clkt; diff --git a/crates/bcm2711-lpa/src/bsc0/a.rs b/crates/bcm2711-lpa/src/bsc0/a.rs index d98d147..e9669f3 100644 --- a/crates/bcm2711-lpa/src/bsc0/a.rs +++ b/crates/bcm2711-lpa/src/bsc0/a.rs @@ -1,43 +1,11 @@ #[doc = "Register `A` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `A` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDR` reader - Slave address"] -pub type ADDR_R = crate::FieldReader; +pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - Slave address"] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, A_SPEC, u8, u8, 7, O>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; impl R { #[doc = "Bits 0:6 - Slave address"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { ADDR_R::new((self.bits & 0x7f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A") + .field("addr", &format_args!("{}", self.addr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - Slave address"] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<0> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Slave address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [a](index.html) module"] +#[doc = "Slave address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct A_SPEC; impl crate::RegisterSpec for A_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [a::R](R) reader structure"] -impl crate::Readable for A_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [a::W](W) writer structure"] +#[doc = "`read()` method returns [`a::R`](R) reader structure"] +impl crate::Readable for A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a::W`](W) writer structure"] impl crate::Writable for A_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/bsc0/c.rs b/crates/bcm2711-lpa/src/bsc0/c.rs index f62d48d..85f86f7 100644 --- a/crates/bcm2711-lpa/src/bsc0/c.rs +++ b/crates/bcm2711-lpa/src/bsc0/c.rs @@ -1,67 +1,35 @@ #[doc = "Register `C` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `READ` reader - Transfer is read"] -pub type READ_R = crate::BitReader; +pub type READ_R = crate::BitReader; #[doc = "Field `READ` writer - Transfer is read"] -pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLEAR` reader - Clear the FIFO"] -pub type CLEAR_R = crate::FieldReader; +pub type CLEAR_R = crate::FieldReader; #[doc = "Field `CLEAR` writer - Clear the FIFO"] -pub type CLEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, C_SPEC, u8, u8, 2, O>; +pub type CLEAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `ST` reader - Start transfer"] -pub type ST_R = crate::BitReader; +pub type ST_R = crate::BitReader; #[doc = "Field `ST` writer - Start transfer"] -pub type ST_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTD` reader - Interrupt on done"] -pub type INTD_R = crate::BitReader; +pub type INTD_R = crate::BitReader; #[doc = "Field `INTD` writer - Interrupt on done"] -pub type INTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type INTD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTT` reader - Interrupt on TX"] -pub type INTT_R = crate::BitReader; +pub type INTT_R = crate::BitReader; #[doc = "Field `INTT` writer - Interrupt on TX"] -pub type INTT_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type INTT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTR` reader - Interrupt on RX"] -pub type INTR_R = crate::BitReader; +pub type INTR_R = crate::BitReader; #[doc = "Field `INTR` writer - Interrupt on RX"] -pub type INTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type INTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2CEN` reader - I2C Enable"] -pub type I2CEN_R = crate::BitReader; +pub type I2CEN_R = crate::BitReader; #[doc = "Field `I2CEN` writer - I2C Enable"] -pub type I2CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type I2CEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer is read"] #[inline(always)] @@ -99,68 +67,87 @@ impl R { I2CEN_R::new(((self.bits >> 15) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("C") + .field("i2cen", &format_args!("{}", self.i2cen().bit())) + .field("intr", &format_args!("{}", self.intr().bit())) + .field("intt", &format_args!("{}", self.intt().bit())) + .field("intd", &format_args!("{}", self.intd().bit())) + .field("st", &format_args!("{}", self.st().bit())) + .field("clear", &format_args!("{}", self.clear().bits())) + .field("read", &format_args!("{}", self.read().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer is read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W<0> { + pub fn read(&mut self) -> READ_W { READ_W::new(self) } #[doc = "Bits 4:5 - Clear the FIFO"] #[inline(always)] #[must_use] - pub fn clear(&mut self) -> CLEAR_W<4> { + pub fn clear(&mut self) -> CLEAR_W { CLEAR_W::new(self) } #[doc = "Bit 7 - Start transfer"] #[inline(always)] #[must_use] - pub fn st(&mut self) -> ST_W<7> { + pub fn st(&mut self) -> ST_W { ST_W::new(self) } #[doc = "Bit 8 - Interrupt on done"] #[inline(always)] #[must_use] - pub fn intd(&mut self) -> INTD_W<8> { + pub fn intd(&mut self) -> INTD_W { INTD_W::new(self) } #[doc = "Bit 9 - Interrupt on TX"] #[inline(always)] #[must_use] - pub fn intt(&mut self) -> INTT_W<9> { + pub fn intt(&mut self) -> INTT_W { INTT_W::new(self) } #[doc = "Bit 10 - Interrupt on RX"] #[inline(always)] #[must_use] - pub fn intr(&mut self) -> INTR_W<10> { + pub fn intr(&mut self) -> INTR_W { INTR_W::new(self) } #[doc = "Bit 15 - I2C Enable"] #[inline(always)] #[must_use] - pub fn i2cen(&mut self) -> I2CEN_W<15> { + pub fn i2cen(&mut self) -> I2CEN_W { I2CEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C_SPEC; impl crate::RegisterSpec for C_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c::R](R) reader structure"] -impl crate::Readable for C_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c::W](W) writer structure"] +#[doc = "`read()` method returns [`c::R`](R) reader structure"] +impl crate::Readable for C_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c::W`](W) writer structure"] impl crate::Writable for C_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/bsc0/clkt.rs b/crates/bcm2711-lpa/src/bsc0/clkt.rs index 15bc5c4..103f923 100644 --- a/crates/bcm2711-lpa/src/bsc0/clkt.rs +++ b/crates/bcm2711-lpa/src/bsc0/clkt.rs @@ -1,43 +1,11 @@ #[doc = "Register `CLKT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLKT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TOUT` reader - Number of SCL clock cycles to wait"] -pub type TOUT_R = crate::FieldReader; +pub type TOUT_R = crate::FieldReader; #[doc = "Field `TOUT` writer - Number of SCL clock cycles to wait"] -pub type TOUT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKT_SPEC, u16, u16, 16, O>; +pub type TOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { TOUT_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLKT") + .field("tout", &format_args!("{}", self.tout().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"] #[inline(always)] #[must_use] - pub fn tout(&mut self) -> TOUT_W<0> { + pub fn tout(&mut self) -> TOUT_W { TOUT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock stretch timeout (broken on 283x)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkt](index.html) module"] +#[doc = "Clock stretch timeout (broken on 283x)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKT_SPEC; impl crate::RegisterSpec for CLKT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clkt::R](R) reader structure"] -impl crate::Readable for CLKT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clkt::W](W) writer structure"] +#[doc = "`read()` method returns [`clkt::R`](R) reader structure"] +impl crate::Readable for CLKT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clkt::W`](W) writer structure"] impl crate::Writable for CLKT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/bsc0/del.rs b/crates/bcm2711-lpa/src/bsc0/del.rs index c39336b..4c0e876 100644 --- a/crates/bcm2711-lpa/src/bsc0/del.rs +++ b/crates/bcm2711-lpa/src/bsc0/del.rs @@ -1,47 +1,15 @@ #[doc = "Register `DEL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `REDL` reader - Delay before reading after a rising edge"] -pub type REDL_R = crate::FieldReader; +pub type REDL_R = crate::FieldReader; #[doc = "Field `REDL` writer - Delay before reading after a rising edge"] -pub type REDL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEL_SPEC, u16, u16, 16, O>; +pub type REDL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `FEDL` reader - Delay before reading after a falling edge"] -pub type FEDL_R = crate::FieldReader; +pub type FEDL_R = crate::FieldReader; #[doc = "Field `FEDL` writer - Delay before reading after a falling edge"] -pub type FEDL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEL_SPEC, u16, u16, 16, O>; +pub type FEDL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Delay before reading after a rising edge"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { FEDL_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEL") + .field("fedl", &format_args!("{}", self.fedl().bits())) + .field("redl", &format_args!("{}", self.redl().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Delay before reading after a rising edge"] #[inline(always)] #[must_use] - pub fn redl(&mut self) -> REDL_W<0> { + pub fn redl(&mut self) -> REDL_W { REDL_W::new(self) } #[doc = "Bits 16:31 - Delay before reading after a falling edge"] #[inline(always)] #[must_use] - pub fn fedl(&mut self) -> FEDL_W<16> { + pub fn fedl(&mut self) -> FEDL_W { FEDL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data delay (Values must be under CDIV / 2)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [del](index.html) module"] +#[doc = "Data delay (Values must be under CDIV / 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`del::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`del::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEL_SPEC; impl crate::RegisterSpec for DEL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [del::R](R) reader structure"] -impl crate::Readable for DEL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [del::W](W) writer structure"] +#[doc = "`read()` method returns [`del::R`](R) reader structure"] +impl crate::Readable for DEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`del::W`](W) writer structure"] impl crate::Writable for DEL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/bsc0/div.rs b/crates/bcm2711-lpa/src/bsc0/div.rs index ce0aa5a..9ffd801 100644 --- a/crates/bcm2711-lpa/src/bsc0/div.rs +++ b/crates/bcm2711-lpa/src/bsc0/div.rs @@ -1,43 +1,11 @@ #[doc = "Register `DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CDIV` reader - Divide the source clock"] -pub type CDIV_R = crate::FieldReader; +pub type CDIV_R = crate::FieldReader; #[doc = "Field `CDIV` writer - Divide the source clock"] -pub type CDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 16, O>; +pub type CDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Divide the source clock"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { CDIV_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIV") + .field("cdiv", &format_args!("{}", self.cdiv().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Divide the source clock"] #[inline(always)] #[must_use] - pub fn cdiv(&mut self) -> CDIV_W<0> { + pub fn cdiv(&mut self) -> CDIV_W { CDIV_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](index.html) module"] +#[doc = "Clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SPEC; impl crate::RegisterSpec for DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div::R](R) reader structure"] -impl crate::Readable for DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +#[doc = "`read()` method returns [`div::R`](R) reader structure"] +impl crate::Readable for DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] impl crate::Writable for DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/bsc0/dlen.rs b/crates/bcm2711-lpa/src/bsc0/dlen.rs index 25e2771..5c7bb83 100644 --- a/crates/bcm2711-lpa/src/bsc0/dlen.rs +++ b/crates/bcm2711-lpa/src/bsc0/dlen.rs @@ -1,43 +1,11 @@ #[doc = "Register `DLEN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DLEN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DLEN` reader - Data length"] -pub type DLEN_R = crate::FieldReader; +pub type DLEN_R = crate::FieldReader; #[doc = "Field `DLEN` writer - Data length"] -pub type DLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLEN_SPEC, u16, u16, 16, O>; +pub type DLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Data length"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DLEN_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DLEN") + .field("dlen", &format_args!("{}", self.dlen().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Data length"] #[inline(always)] #[must_use] - pub fn dlen(&mut self) -> DLEN_W<0> { + pub fn dlen(&mut self) -> DLEN_W { DLEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlen](index.html) module"] +#[doc = "Data length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DLEN_SPEC; impl crate::RegisterSpec for DLEN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dlen::R](R) reader structure"] -impl crate::Readable for DLEN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dlen::W](W) writer structure"] +#[doc = "`read()` method returns [`dlen::R`](R) reader structure"] +impl crate::Readable for DLEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dlen::W`](W) writer structure"] impl crate::Writable for DLEN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/bsc0/fifo.rs b/crates/bcm2711-lpa/src/bsc0/fifo.rs index f85912b..0536908 100644 --- a/crates/bcm2711-lpa/src/bsc0/fifo.rs +++ b/crates/bcm2711-lpa/src/bsc0/fifo.rs @@ -1,43 +1,11 @@ #[doc = "Register `FIFO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FIFO` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - Access the FIFO"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - Access the FIFO"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u8, u8, 8, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Access the FIFO"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new((self.bits & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Access the FIFO"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data FIFO\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"] +#[doc = "Data FIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_SPEC; impl crate::RegisterSpec for FIFO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fifo::R](R) reader structure"] -impl crate::Readable for FIFO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"] +#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] +impl crate::Readable for FIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"] impl crate::Writable for FIFO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/bsc0/s.rs b/crates/bcm2711-lpa/src/bsc0/s.rs index 45f365b..56cb006 100644 --- a/crates/bcm2711-lpa/src/bsc0/s.rs +++ b/crates/bcm2711-lpa/src/bsc0/s.rs @@ -1,65 +1,33 @@ #[doc = "Register `S` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `S` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TA` reader - Transfer active"] -pub type TA_R = crate::BitReader; +pub type TA_R = crate::BitReader; #[doc = "Field `DONE` reader - Transfer done"] -pub type DONE_R = crate::BitReader; +pub type DONE_R = crate::BitReader; #[doc = "Field `DONE` writer - Transfer done"] -pub type DONE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +pub type DONE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TXW` reader - FIFO needs to be written"] -pub type TXW_R = crate::BitReader; +pub type TXW_R = crate::BitReader; #[doc = "Field `RXR` reader - FIFO needs to be read"] -pub type RXR_R = crate::BitReader; +pub type RXR_R = crate::BitReader; #[doc = "Field `TXD` reader - FIFO has space for at least one byte"] -pub type TXD_R = crate::BitReader; +pub type TXD_R = crate::BitReader; #[doc = "Field `RXD` reader - FIFO contains at least one byte"] -pub type RXD_R = crate::BitReader; +pub type RXD_R = crate::BitReader; #[doc = "Field `TXE` reader - FIFO is empty. Nothing to transmit"] -pub type TXE_R = crate::BitReader; +pub type TXE_R = crate::BitReader; #[doc = "Field `RXF` reader - FIFO is full. Can't receive anything else"] -pub type RXF_R = crate::BitReader; +pub type RXF_R = crate::BitReader; #[doc = "Field `ERR` reader - Error: No ack"] -pub type ERR_R = crate::BitReader; +pub type ERR_R = crate::BitReader; #[doc = "Field `ERR` writer - Error: No ack"] -pub type ERR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +pub type ERR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLKT` reader - Clock stretch timeout"] -pub type CLKT_R = crate::BitReader; +pub type CLKT_R = crate::BitReader; #[doc = "Field `CLKT` writer - Clock stretch timeout"] -pub type CLKT_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +pub type CLKT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer active"] #[inline(always)] @@ -112,44 +80,66 @@ impl R { CLKT_R::new(((self.bits >> 9) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("S") + .field("clkt", &format_args!("{}", self.clkt().bit())) + .field("err", &format_args!("{}", self.err().bit())) + .field("rxf", &format_args!("{}", self.rxf().bit())) + .field("txe", &format_args!("{}", self.txe().bit())) + .field("rxd", &format_args!("{}", self.rxd().bit())) + .field("txd", &format_args!("{}", self.txd().bit())) + .field("rxr", &format_args!("{}", self.rxr().bit())) + .field("txw", &format_args!("{}", self.txw().bit())) + .field("done", &format_args!("{}", self.done().bit())) + .field("ta", &format_args!("{}", self.ta().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Transfer done"] #[inline(always)] #[must_use] - pub fn done(&mut self) -> DONE_W<1> { + pub fn done(&mut self) -> DONE_W { DONE_W::new(self) } #[doc = "Bit 8 - Error: No ack"] #[inline(always)] #[must_use] - pub fn err(&mut self) -> ERR_W<8> { + pub fn err(&mut self) -> ERR_W { ERR_W::new(self) } #[doc = "Bit 9 - Clock stretch timeout"] #[inline(always)] #[must_use] - pub fn clkt(&mut self) -> CLKT_W<9> { + pub fn clkt(&mut self) -> CLKT_W { CLKT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s](index.html) module"] +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct S_SPEC; impl crate::RegisterSpec for S_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [s::R](R) reader structure"] -impl crate::Readable for S_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [s::W](W) writer structure"] +#[doc = "`read()` method returns [`s::R`](R) reader structure"] +impl crate::Readable for S_SPEC {} +#[doc = "`write(|w| ..)` method takes [`s::W`](W) writer structure"] impl crate::Writable for S_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0302; } diff --git a/crates/bcm2711-lpa/src/cm_pcm.rs b/crates/bcm2711-lpa/src/cm_pcm.rs index 0c60fcd..855e1b0 100644 --- a/crates/bcm2711-lpa/src/cm_pcm.rs +++ b/crates/bcm2711-lpa/src/cm_pcm.rs @@ -1,16 +1,19 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control / Status"] pub cs: CS, #[doc = "0x04 - Clock divisor"] pub div: DIV, } -#[doc = "CS (rw) register accessor: an alias for `Reg`"] +#[doc = "CS (rw) register accessor: Control / Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cs`] +module"] pub type CS = crate::Reg; #[doc = "Control / Status"] pub mod cs; -#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV (rw) register accessor: Clock divisor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div`] +module"] pub type DIV = crate::Reg; #[doc = "Clock divisor"] pub mod div; diff --git a/crates/bcm2711-lpa/src/cm_pcm/cs.rs b/crates/bcm2711-lpa/src/cm_pcm/cs.rs index 67ddd60..036729f 100644 --- a/crates/bcm2711-lpa/src/cm_pcm/cs.rs +++ b/crates/bcm2711-lpa/src/cm_pcm/cs.rs @@ -1,41 +1,9 @@ #[doc = "Register `CS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SRC` reader - Clock source"] -pub type SRC_R = crate::FieldReader; +pub type SRC_R = crate::FieldReader; #[doc = "Clock source\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -61,10 +29,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for SRC_A { + type Ux = u8; +} impl SRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 1 => Some(SRC_A::XOSC), 2 => Some(SRC_A::TEST0), @@ -76,99 +47,103 @@ impl SRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `XOSC`"] + #[doc = "`1`"] #[inline(always)] pub fn is_xosc(&self) -> bool { *self == SRC_A::XOSC } - #[doc = "Checks if the value of the field is `TEST0`"] + #[doc = "`10`"] #[inline(always)] pub fn is_test0(&self) -> bool { *self == SRC_A::TEST0 } - #[doc = "Checks if the value of the field is `TEST1`"] + #[doc = "`11`"] #[inline(always)] pub fn is_test1(&self) -> bool { *self == SRC_A::TEST1 } - #[doc = "Checks if the value of the field is `PLLA`"] + #[doc = "`100`"] #[inline(always)] pub fn is_plla(&self) -> bool { *self == SRC_A::PLLA } - #[doc = "Checks if the value of the field is `PLLB`"] + #[doc = "`101`"] #[inline(always)] pub fn is_pllb(&self) -> bool { *self == SRC_A::PLLB } - #[doc = "Checks if the value of the field is `PLLC`"] + #[doc = "`110`"] #[inline(always)] pub fn is_pllc(&self) -> bool { *self == SRC_A::PLLC } - #[doc = "Checks if the value of the field is `HDMI`"] + #[doc = "`111`"] #[inline(always)] pub fn is_hdmi(&self) -> bool { *self == SRC_A::HDMI } } #[doc = "Field `SRC` writer - Clock source"] -pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, SRC_A, 4, O>; -impl<'a, const O: u8> SRC_W<'a, O> { +pub type SRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, SRC_A>; +impl<'a, REG, const O: u8> SRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1`"] #[inline(always)] - pub fn xosc(self) -> &'a mut W { + pub fn xosc(self) -> &'a mut crate::W { self.variant(SRC_A::XOSC) } #[doc = "`10`"] #[inline(always)] - pub fn test0(self) -> &'a mut W { + pub fn test0(self) -> &'a mut crate::W { self.variant(SRC_A::TEST0) } #[doc = "`11`"] #[inline(always)] - pub fn test1(self) -> &'a mut W { + pub fn test1(self) -> &'a mut crate::W { self.variant(SRC_A::TEST1) } #[doc = "`100`"] #[inline(always)] - pub fn plla(self) -> &'a mut W { + pub fn plla(self) -> &'a mut crate::W { self.variant(SRC_A::PLLA) } #[doc = "`101`"] #[inline(always)] - pub fn pllb(self) -> &'a mut W { + pub fn pllb(self) -> &'a mut crate::W { self.variant(SRC_A::PLLB) } #[doc = "`110`"] #[inline(always)] - pub fn pllc(self) -> &'a mut W { + pub fn pllc(self) -> &'a mut crate::W { self.variant(SRC_A::PLLC) } #[doc = "`111`"] #[inline(always)] - pub fn hdmi(self) -> &'a mut W { + pub fn hdmi(self) -> &'a mut crate::W { self.variant(SRC_A::HDMI) } } #[doc = "Field `ENAB` reader - Enable the clock generator. (Switch SRC first.)"] -pub type ENAB_R = crate::BitReader; +pub type ENAB_R = crate::BitReader; #[doc = "Field `ENAB` writer - Enable the clock generator. (Switch SRC first.)"] -pub type ENAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type ENAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `KILL` reader - Stop and reset the generator"] -pub type KILL_R = crate::BitReader; +pub type KILL_R = crate::BitReader; #[doc = "Field `KILL` writer - Stop and reset the generator"] -pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type KILL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUSY` reader - Indicates the clock generator is running"] -pub type BUSY_R = crate::BitReader; +pub type BUSY_R = crate::BitReader; #[doc = "Field `FLIP` reader - Generate an edge on output. (For testing)"] -pub type FLIP_R = crate::BitReader; +pub type FLIP_R = crate::BitReader; #[doc = "Field `FLIP` writer - Generate an edge on output. (For testing)"] -pub type FLIP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type FLIP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MASH` reader - MASH control, stage count"] -pub type MASH_R = crate::FieldReader; +pub type MASH_R = crate::FieldReader; #[doc = "Field `MASH` writer - MASH control, stage count"] -pub type MASH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, u8, 2, O>; +pub type MASH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Password. Always 0x5a\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -182,12 +157,19 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for PASSWD_AW { + type Ux = u8; +} #[doc = "Field `PASSWD` writer - Password. Always 0x5a"] -pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, PASSWD_AW, 8, O>; -impl<'a, const O: u8> PASSWD_W<'a, O> { +pub type PASSWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, PASSWD_AW>; +impl<'a, REG, const O: u8> PASSWD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1011010`"] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(PASSWD_AW::PASSWD) } } @@ -223,62 +205,80 @@ impl R { MASH_R::new(((self.bits >> 9) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CS") + .field("mash", &format_args!("{}", self.mash().bits())) + .field("flip", &format_args!("{}", self.flip().bit())) + .field("busy", &format_args!("{}", self.busy().bit())) + .field("kill", &format_args!("{}", self.kill().bit())) + .field("enab", &format_args!("{}", self.enab().bit())) + .field("src", &format_args!("{}", self.src().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:3 - Clock source"] #[inline(always)] #[must_use] - pub fn src(&mut self) -> SRC_W<0> { + pub fn src(&mut self) -> SRC_W { SRC_W::new(self) } #[doc = "Bit 4 - Enable the clock generator. (Switch SRC first.)"] #[inline(always)] #[must_use] - pub fn enab(&mut self) -> ENAB_W<4> { + pub fn enab(&mut self) -> ENAB_W { ENAB_W::new(self) } #[doc = "Bit 5 - Stop and reset the generator"] #[inline(always)] #[must_use] - pub fn kill(&mut self) -> KILL_W<5> { + pub fn kill(&mut self) -> KILL_W { KILL_W::new(self) } #[doc = "Bit 8 - Generate an edge on output. (For testing)"] #[inline(always)] #[must_use] - pub fn flip(&mut self) -> FLIP_W<8> { + pub fn flip(&mut self) -> FLIP_W { FLIP_W::new(self) } #[doc = "Bits 9:10 - MASH control, stage count"] #[inline(always)] #[must_use] - pub fn mash(&mut self) -> MASH_W<9> { + pub fn mash(&mut self) -> MASH_W { MASH_W::new(self) } #[doc = "Bits 24:31 - Password. Always 0x5a"] #[inline(always)] #[must_use] - pub fn passwd(&mut self) -> PASSWD_W<24> { + pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control / Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +#[doc = "Control / Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CS_SPEC; impl crate::RegisterSpec for CS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cs::R](R) reader structure"] -impl crate::Readable for CS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/cm_pcm/div.rs b/crates/bcm2711-lpa/src/cm_pcm/div.rs index a0c99f8..825974e 100644 --- a/crates/bcm2711-lpa/src/cm_pcm/div.rs +++ b/crates/bcm2711-lpa/src/cm_pcm/div.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DIVF` reader - Fractional part of divisor"] -pub type DIVF_R = crate::FieldReader; +pub type DIVF_R = crate::FieldReader; #[doc = "Field `DIVF` writer - Fractional part of divisor"] -pub type DIVF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 12, O>; +pub type DIVF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; #[doc = "Field `DIVI` reader - Integer part of divisor"] -pub type DIVI_R = crate::FieldReader; +pub type DIVI_R = crate::FieldReader; #[doc = "Field `DIVI` writer - Integer part of divisor"] -pub type DIVI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 12, O>; +pub type DIVI_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; #[doc = "Password. Always 0x5a\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -55,12 +23,19 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for PASSWD_AW { + type Ux = u8; +} #[doc = "Field `PASSWD` writer - Password. Always 0x5a"] -pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u8, PASSWD_AW, 8, O>; -impl<'a, const O: u8> PASSWD_W<'a, O> { +pub type PASSWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, PASSWD_AW>; +impl<'a, REG, const O: u8> PASSWD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1011010`"] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(PASSWD_AW::PASSWD) } } @@ -76,44 +51,58 @@ impl R { DIVI_R::new(((self.bits >> 12) & 0x0fff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIV") + .field("divi", &format_args!("{}", self.divi().bits())) + .field("divf", &format_args!("{}", self.divf().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:11 - Fractional part of divisor"] #[inline(always)] #[must_use] - pub fn divf(&mut self) -> DIVF_W<0> { + pub fn divf(&mut self) -> DIVF_W { DIVF_W::new(self) } #[doc = "Bits 12:23 - Integer part of divisor"] #[inline(always)] #[must_use] - pub fn divi(&mut self) -> DIVI_W<12> { + pub fn divi(&mut self) -> DIVI_W { DIVI_W::new(self) } #[doc = "Bits 24:31 - Password. Always 0x5a"] #[inline(always)] #[must_use] - pub fn passwd(&mut self) -> PASSWD_W<24> { + pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](index.html) module"] +#[doc = "Clock divisor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SPEC; impl crate::RegisterSpec for DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div::R](R) reader structure"] -impl crate::Readable for DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +#[doc = "`read()` method returns [`div::R`](R) reader structure"] +impl crate::Readable for DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] impl crate::Writable for DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc.rs b/crates/bcm2711-lpa/src/emmc.rs index e4be2cf..597a27a 100644 --- a/crates/bcm2711-lpa/src/emmc.rs +++ b/crates/bcm2711-lpa/src/emmc.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Argument for ACMD23 command"] pub arg2: ARG2, @@ -59,107 +60,133 @@ pub struct RegisterBlock { #[doc = "0xfc - Version information and slot interrupt status"] pub slotisr_ver: SLOTISR_VER, } -#[doc = "ARG2 (rw) register accessor: an alias for `Reg`"] +#[doc = "ARG2 (rw) register accessor: Argument for ACMD23 command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arg2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arg2`] +module"] pub type ARG2 = crate::Reg; #[doc = "Argument for ACMD23 command"] pub mod arg2; -#[doc = "BLKSIZECNT (rw) register accessor: an alias for `Reg`"] +#[doc = "BLKSIZECNT (rw) register accessor: Numer and size in bytes for data block to be transferred\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blksizecnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blksizecnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blksizecnt`] +module"] pub type BLKSIZECNT = crate::Reg; #[doc = "Numer and size in bytes for data block to be transferred"] pub mod blksizecnt; -#[doc = "ARG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "ARG1 (rw) register accessor: Argument for everything but ACMD23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arg1`] +module"] pub type ARG1 = crate::Reg; #[doc = "Argument for everything but ACMD23"] pub mod arg1; -#[doc = "CMDTM (rw) register accessor: an alias for `Reg`"] +#[doc = "CMDTM (rw) register accessor: Issue commands to the card\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdtm::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdtm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdtm`] +module"] pub type CMDTM = crate::Reg; #[doc = "Issue commands to the card"] pub mod cmdtm; -#[doc = "RESP0 (rw) register accessor: an alias for `Reg`"] +#[doc = "RESP0 (rw) register accessor: Status bits of the response\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp0`] +module"] pub type RESP0 = crate::Reg; #[doc = "Status bits of the response"] pub mod resp0; -#[doc = "RESP1 (rw) register accessor: an alias for `Reg`"] +#[doc = "RESP1 (rw) register accessor: Bits 63:32 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp1`] +module"] pub type RESP1 = crate::Reg; #[doc = "Bits 63:32 of CMD2 and CMD10 responses"] pub mod resp1; -#[doc = "RESP2 (rw) register accessor: an alias for `Reg`"] +#[doc = "RESP2 (rw) register accessor: Bits 95:64 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp2`] +module"] pub type RESP2 = crate::Reg; #[doc = "Bits 95:64 of CMD2 and CMD10 responses"] pub mod resp2; -#[doc = "RESP3 (rw) register accessor: an alias for `Reg`"] +#[doc = "RESP3 (rw) register accessor: Bits 127:96 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp3`] +module"] pub type RESP3 = crate::Reg; #[doc = "Bits 127:96 of CMD2 and CMD10 responses"] pub mod resp3; -#[doc = "DATA (rw) register accessor: an alias for `Reg`"] +#[doc = "DATA (rw) register accessor: Data to/from the card\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] +module"] pub type DATA = crate::Reg; #[doc = "Data to/from the card"] pub mod data; -#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +#[doc = "STATUS (rw) register accessor: Status info for debugging\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] +module"] pub type STATUS = crate::Reg; #[doc = "Status info for debugging"] pub mod status; -#[doc = "CONTROL0 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONTROL0 (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control0`] +module"] pub type CONTROL0 = crate::Reg; #[doc = "Control"] pub mod control0; -#[doc = "CONTROL1 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONTROL1 (rw) register accessor: Configure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control1`] +module"] pub type CONTROL1 = crate::Reg; #[doc = "Configure"] pub mod control1; -#[doc = "INTERRUPT (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERRUPT (rw) register accessor: Interrupt flags\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrupt`] +module"] pub type INTERRUPT = crate::Reg; #[doc = "Interrupt flags"] pub mod interrupt; -#[doc = "IRPT_MASK (rw) register accessor: an alias for `Reg`"] +#[doc = "IRPT_MASK (rw) register accessor: Mask interrupts that change in INTERRUPT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irpt_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irpt_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irpt_mask`] +module"] pub type IRPT_MASK = crate::Reg; #[doc = "Mask interrupts that change in INTERRUPT"] pub mod irpt_mask; -#[doc = "IRPT_EN (rw) register accessor: an alias for `Reg`"] +#[doc = "IRPT_EN (rw) register accessor: Enable interrupt to core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irpt_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irpt_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irpt_en`] +module"] pub type IRPT_EN = crate::Reg; #[doc = "Enable interrupt to core"] pub mod irpt_en; -#[doc = "CONTROL2 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONTROL2 (rw) register accessor: Control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control2`] +module"] pub type CONTROL2 = crate::Reg; #[doc = "Control 2"] pub mod control2; -#[doc = "FORCE_IRPT (rw) register accessor: an alias for `Reg`"] +#[doc = "FORCE_IRPT (rw) register accessor: Force an interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`force_irpt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`force_irpt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@force_irpt`] +module"] pub type FORCE_IRPT = crate::Reg; #[doc = "Force an interrupt"] pub mod force_irpt; -#[doc = "BOOT_TIMEOUT (rw) register accessor: an alias for `Reg`"] +#[doc = "BOOT_TIMEOUT (rw) register accessor: Number of SD clock cycles to wait for boot\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`boot_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`boot_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@boot_timeout`] +module"] pub type BOOT_TIMEOUT = crate::Reg; #[doc = "Number of SD clock cycles to wait for boot"] pub mod boot_timeout; -#[doc = "DBG_SEL (rw) register accessor: an alias for `Reg`"] +#[doc = "DBG_SEL (rw) register accessor: What submodules are accessed by the debug bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbg_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbg_sel`] +module"] pub type DBG_SEL = crate::Reg; #[doc = "What submodules are accessed by the debug bus"] pub mod dbg_sel; -#[doc = "EXRDFIFO_CFG (rw) register accessor: an alias for `Reg`"] +#[doc = "EXRDFIFO_CFG (rw) register accessor: Fine tune DMA request generation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exrdfifo_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrdfifo_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exrdfifo_cfg`] +module"] pub type EXRDFIFO_CFG = crate::Reg; #[doc = "Fine tune DMA request generation"] pub mod exrdfifo_cfg; -#[doc = "EXRDFIFO_EN (rw) register accessor: an alias for `Reg`"] +#[doc = "EXRDFIFO_EN (rw) register accessor: Enable the extension data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exrdfifo_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrdfifo_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exrdfifo_en`] +module"] pub type EXRDFIFO_EN = crate::Reg; #[doc = "Enable the extension data register"] pub mod exrdfifo_en; -#[doc = "TUNE_STEP (rw) register accessor: an alias for `Reg`"] +#[doc = "TUNE_STEP (rw) register accessor: Sample clock delay step duration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_step::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_step::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tune_step`] +module"] pub type TUNE_STEP = crate::Reg; #[doc = "Sample clock delay step duration"] pub mod tune_step; -#[doc = "TUNE_STEPS_STD (rw) register accessor: an alias for `Reg`"] +#[doc = "TUNE_STEPS_STD (rw) register accessor: Sample clock delay step count for SDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_steps_std::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_steps_std::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tune_steps_std`] +module"] pub type TUNE_STEPS_STD = crate::Reg; #[doc = "Sample clock delay step count for SDR"] pub mod tune_steps_std; -#[doc = "TUNE_STEPS_DDR (rw) register accessor: an alias for `Reg`"] +#[doc = "TUNE_STEPS_DDR (rw) register accessor: Sample clock delay step count for DDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_steps_ddr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_steps_ddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tune_steps_ddr`] +module"] pub type TUNE_STEPS_DDR = crate::Reg; #[doc = "Sample clock delay step count for DDR"] pub mod tune_steps_ddr; -#[doc = "SPI_INT_SPT (rw) register accessor: an alias for `Reg`"] +#[doc = "SPI_INT_SPT (rw) register accessor: Interrupts in SPI mode depend on CS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_int_spt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_int_spt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_int_spt`] +module"] pub type SPI_INT_SPT = crate::Reg; #[doc = "Interrupts in SPI mode depend on CS"] pub mod spi_int_spt; -#[doc = "SLOTISR_VER (rw) register accessor: an alias for `Reg`"] +#[doc = "SLOTISR_VER (rw) register accessor: Version information and slot interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slotisr_ver::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slotisr_ver::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slotisr_ver`] +module"] pub type SLOTISR_VER = crate::Reg; #[doc = "Version information and slot interrupt status"] pub mod slotisr_ver; diff --git a/crates/bcm2711-lpa/src/emmc/arg1.rs b/crates/bcm2711-lpa/src/emmc/arg1.rs index 4a25300..491f890 100644 --- a/crates/bcm2711-lpa/src/emmc/arg1.rs +++ b/crates/bcm2711-lpa/src/emmc/arg1.rs @@ -1,59 +1,38 @@ #[doc = "Register `ARG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ARG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Argument for everything but ACMD23\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arg1](index.html) module"] +#[doc = "Argument for everything but ACMD23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ARG1_SPEC; impl crate::RegisterSpec for ARG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [arg1::R](R) reader structure"] -impl crate::Readable for ARG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [arg1::W](W) writer structure"] +#[doc = "`read()` method returns [`arg1::R`](R) reader structure"] +impl crate::Readable for ARG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`arg1::W`](W) writer structure"] impl crate::Writable for ARG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/arg2.rs b/crates/bcm2711-lpa/src/emmc/arg2.rs index b295b35..90678c2 100644 --- a/crates/bcm2711-lpa/src/emmc/arg2.rs +++ b/crates/bcm2711-lpa/src/emmc/arg2.rs @@ -1,59 +1,38 @@ #[doc = "Register `ARG2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ARG2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Argument for ACMD23 command\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arg2](index.html) module"] +#[doc = "Argument for ACMD23 command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arg2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ARG2_SPEC; impl crate::RegisterSpec for ARG2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [arg2::R](R) reader structure"] -impl crate::Readable for ARG2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [arg2::W](W) writer structure"] +#[doc = "`read()` method returns [`arg2::R`](R) reader structure"] +impl crate::Readable for ARG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`arg2::W`](W) writer structure"] impl crate::Writable for ARG2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/blksizecnt.rs b/crates/bcm2711-lpa/src/emmc/blksizecnt.rs index f3dabd8..c6eec15 100644 --- a/crates/bcm2711-lpa/src/emmc/blksizecnt.rs +++ b/crates/bcm2711-lpa/src/emmc/blksizecnt.rs @@ -1,47 +1,15 @@ #[doc = "Register `BLKSIZECNT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BLKSIZECNT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BLKSIZE` reader - Block size in bytes"] -pub type BLKSIZE_R = crate::FieldReader; +pub type BLKSIZE_R = crate::FieldReader; #[doc = "Field `BLKSIZE` writer - Block size in bytes"] -pub type BLKSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BLKSIZECNT_SPEC, u16, u16, 10, O>; +pub type BLKSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `BLKCNT` reader - Number of blocks to be transferred"] -pub type BLKCNT_R = crate::FieldReader; +pub type BLKCNT_R = crate::FieldReader; #[doc = "Field `BLKCNT` writer - Number of blocks to be transferred"] -pub type BLKCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BLKSIZECNT_SPEC, u16, u16, 16, O>; +pub type BLKCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:9 - Block size in bytes"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { BLKCNT_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLKSIZECNT") + .field("blkcnt", &format_args!("{}", self.blkcnt().bits())) + .field("blksize", &format_args!("{}", self.blksize().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:9 - Block size in bytes"] #[inline(always)] #[must_use] - pub fn blksize(&mut self) -> BLKSIZE_W<0> { + pub fn blksize(&mut self) -> BLKSIZE_W { BLKSIZE_W::new(self) } #[doc = "Bits 16:31 - Number of blocks to be transferred"] #[inline(always)] #[must_use] - pub fn blkcnt(&mut self) -> BLKCNT_W<16> { + pub fn blkcnt(&mut self) -> BLKCNT_W { BLKCNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Numer and size in bytes for data block to be transferred\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [blksizecnt](index.html) module"] +#[doc = "Numer and size in bytes for data block to be transferred\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blksizecnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blksizecnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BLKSIZECNT_SPEC; impl crate::RegisterSpec for BLKSIZECNT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [blksizecnt::R](R) reader structure"] -impl crate::Readable for BLKSIZECNT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [blksizecnt::W](W) writer structure"] +#[doc = "`read()` method returns [`blksizecnt::R`](R) reader structure"] +impl crate::Readable for BLKSIZECNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blksizecnt::W`](W) writer structure"] impl crate::Writable for BLKSIZECNT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/boot_timeout.rs b/crates/bcm2711-lpa/src/emmc/boot_timeout.rs index 5a9943a..41d8ff1 100644 --- a/crates/bcm2711-lpa/src/emmc/boot_timeout.rs +++ b/crates/bcm2711-lpa/src/emmc/boot_timeout.rs @@ -1,59 +1,38 @@ #[doc = "Register `BOOT_TIMEOUT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BOOT_TIMEOUT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Number of SD clock cycles to wait for boot\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [boot_timeout](index.html) module"] +#[doc = "Number of SD clock cycles to wait for boot\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`boot_timeout::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`boot_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BOOT_TIMEOUT_SPEC; impl crate::RegisterSpec for BOOT_TIMEOUT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [boot_timeout::R](R) reader structure"] -impl crate::Readable for BOOT_TIMEOUT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [boot_timeout::W](W) writer structure"] +#[doc = "`read()` method returns [`boot_timeout::R`](R) reader structure"] +impl crate::Readable for BOOT_TIMEOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot_timeout::W`](W) writer structure"] impl crate::Writable for BOOT_TIMEOUT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/cmdtm.rs b/crates/bcm2711-lpa/src/emmc/cmdtm.rs index e30a873..6ff28c8 100644 --- a/crates/bcm2711-lpa/src/emmc/cmdtm.rs +++ b/crates/bcm2711-lpa/src/emmc/cmdtm.rs @@ -1,45 +1,13 @@ #[doc = "Register `CMDTM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CMDTM` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TM_BLKCNT_EN` reader - Enable block counter"] -pub type TM_BLKCNT_EN_R = crate::BitReader; +pub type TM_BLKCNT_EN_R = crate::BitReader; #[doc = "Field `TM_BLKCNT_EN` writer - Enable block counter"] -pub type TM_BLKCNT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +pub type TM_BLKCNT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TM_AUTO_CMD_EN` reader - Command after completion"] -pub type TM_AUTO_CMD_EN_R = crate::FieldReader; +pub type TM_AUTO_CMD_EN_R = crate::FieldReader; #[doc = "Command after completion\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -57,10 +25,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for TM_AUTO_CMD_EN_A { + type Ux = u8; +} impl TM_AUTO_CMD_EN_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(TM_AUTO_CMD_EN_A::NONE), 1 => Some(TM_AUTO_CMD_EN_A::CMD12), @@ -68,39 +39,43 @@ impl TM_AUTO_CMD_EN_R { _ => None, } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_none(&self) -> bool { *self == TM_AUTO_CMD_EN_A::NONE } - #[doc = "Checks if the value of the field is `CMD12`"] + #[doc = "`1`"] #[inline(always)] pub fn is_cmd12(&self) -> bool { *self == TM_AUTO_CMD_EN_A::CMD12 } - #[doc = "Checks if the value of the field is `CMD23`"] + #[doc = "`10`"] #[inline(always)] pub fn is_cmd23(&self) -> bool { *self == TM_AUTO_CMD_EN_A::CMD23 } } #[doc = "Field `TM_AUTO_CMD_EN` writer - Command after completion"] -pub type TM_AUTO_CMD_EN_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, CMDTM_SPEC, u8, TM_AUTO_CMD_EN_A, 2, O>; -impl<'a, const O: u8> TM_AUTO_CMD_EN_W<'a, O> { +pub type TM_AUTO_CMD_EN_W<'a, REG, const O: u8> = + crate::FieldWriter<'a, REG, 2, O, TM_AUTO_CMD_EN_A>; +impl<'a, REG, const O: u8> TM_AUTO_CMD_EN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(TM_AUTO_CMD_EN_A::NONE) } #[doc = "`1`"] #[inline(always)] - pub fn cmd12(self) -> &'a mut W { + pub fn cmd12(self) -> &'a mut crate::W { self.variant(TM_AUTO_CMD_EN_A::CMD12) } #[doc = "`10`"] #[inline(always)] - pub fn cmd23(self) -> &'a mut W { + pub fn cmd23(self) -> &'a mut crate::W { self.variant(TM_AUTO_CMD_EN_A::CMD23) } } @@ -123,34 +98,37 @@ impl From for bool { impl TM_DAT_DIR_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TM_DAT_DIR_A { + pub const fn variant(&self) -> TM_DAT_DIR_A { match self.bits { false => TM_DAT_DIR_A::HOST_TO_CARD, true => TM_DAT_DIR_A::CARD_TO_HOST, } } - #[doc = "Checks if the value of the field is `HOST_TO_CARD`"] + #[doc = "`0`"] #[inline(always)] pub fn is_host_to_card(&self) -> bool { *self == TM_DAT_DIR_A::HOST_TO_CARD } - #[doc = "Checks if the value of the field is `CARD_TO_HOST`"] + #[doc = "`1`"] #[inline(always)] pub fn is_card_to_host(&self) -> bool { *self == TM_DAT_DIR_A::CARD_TO_HOST } } #[doc = "Field `TM_DAT_DIR` writer - Direction of data transfer"] -pub type TM_DAT_DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, TM_DAT_DIR_A, O>; -impl<'a, const O: u8> TM_DAT_DIR_W<'a, O> { +pub type TM_DAT_DIR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TM_DAT_DIR_A>; +impl<'a, REG, const O: u8> TM_DAT_DIR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn host_to_card(self) -> &'a mut W { + pub fn host_to_card(self) -> &'a mut crate::W { self.variant(TM_DAT_DIR_A::HOST_TO_CARD) } #[doc = "`1`"] #[inline(always)] - pub fn card_to_host(self) -> &'a mut W { + pub fn card_to_host(self) -> &'a mut crate::W { self.variant(TM_DAT_DIR_A::CARD_TO_HOST) } } @@ -173,40 +151,42 @@ impl From for bool { impl TM_MULTI_BLOCK_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TM_MULTI_BLOCK_A { + pub const fn variant(&self) -> TM_MULTI_BLOCK_A { match self.bits { false => TM_MULTI_BLOCK_A::SINGLE, true => TM_MULTI_BLOCK_A::MULTIPLE, } } - #[doc = "Checks if the value of the field is `SINGLE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_single(&self) -> bool { *self == TM_MULTI_BLOCK_A::SINGLE } - #[doc = "Checks if the value of the field is `MULTIPLE`"] + #[doc = "`1`"] #[inline(always)] pub fn is_multiple(&self) -> bool { *self == TM_MULTI_BLOCK_A::MULTIPLE } } #[doc = "Field `TM_MULTI_BLOCK` writer - Type of data transfer"] -pub type TM_MULTI_BLOCK_W<'a, const O: u8> = - crate::BitWriter<'a, u32, CMDTM_SPEC, TM_MULTI_BLOCK_A, O>; -impl<'a, const O: u8> TM_MULTI_BLOCK_W<'a, O> { +pub type TM_MULTI_BLOCK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TM_MULTI_BLOCK_A>; +impl<'a, REG, const O: u8> TM_MULTI_BLOCK_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn single(self) -> &'a mut W { + pub fn single(self) -> &'a mut crate::W { self.variant(TM_MULTI_BLOCK_A::SINGLE) } #[doc = "`1`"] #[inline(always)] - pub fn multiple(self) -> &'a mut W { + pub fn multiple(self) -> &'a mut crate::W { self.variant(TM_MULTI_BLOCK_A::MULTIPLE) } } #[doc = "Field `CMD_RSPNS_TYPE` reader - Type of expected response"] -pub type CMD_RSPNS_TYPE_R = crate::FieldReader; +pub type CMD_RSPNS_TYPE_R = crate::FieldReader; #[doc = "Type of expected response\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -226,10 +206,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for RESPONSE_A { + type Ux = u8; +} impl CMD_RSPNS_TYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RESPONSE_A { + pub const fn variant(&self) -> RESPONSE_A { match self.bits { 0 => RESPONSE_A::NONE, 1 => RESPONSE_A::_136BITS, @@ -238,66 +221,69 @@ impl CMD_RSPNS_TYPE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_none(&self) -> bool { *self == RESPONSE_A::NONE } - #[doc = "Checks if the value of the field is `_136BITS`"] + #[doc = "`1`"] #[inline(always)] pub fn is_136bits(&self) -> bool { *self == RESPONSE_A::_136BITS } - #[doc = "Checks if the value of the field is `_48BITS`"] + #[doc = "`10`"] #[inline(always)] pub fn is_48bits(&self) -> bool { *self == RESPONSE_A::_48BITS } - #[doc = "Checks if the value of the field is `_48BITS_USING_BUSY`"] + #[doc = "`11`"] #[inline(always)] pub fn is_48bits_using_busy(&self) -> bool { *self == RESPONSE_A::_48BITS_USING_BUSY } } #[doc = "Field `CMD_RSPNS_TYPE` writer - Type of expected response"] -pub type CMD_RSPNS_TYPE_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, CMDTM_SPEC, u8, RESPONSE_A, 2, O>; -impl<'a, const O: u8> CMD_RSPNS_TYPE_W<'a, O> { +pub type CMD_RSPNS_TYPE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, RESPONSE_A>; +impl<'a, REG, const O: u8> CMD_RSPNS_TYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(RESPONSE_A::NONE) } #[doc = "`1`"] #[inline(always)] - pub fn _136bits(self) -> &'a mut W { + pub fn _136bits(self) -> &'a mut crate::W { self.variant(RESPONSE_A::_136BITS) } #[doc = "`10`"] #[inline(always)] - pub fn _48bits(self) -> &'a mut W { + pub fn _48bits(self) -> &'a mut crate::W { self.variant(RESPONSE_A::_48BITS) } #[doc = "`11`"] #[inline(always)] - pub fn _48bits_using_busy(self) -> &'a mut W { + pub fn _48bits_using_busy(self) -> &'a mut crate::W { self.variant(RESPONSE_A::_48BITS_USING_BUSY) } } #[doc = "Field `CMD_CRCCHK_EN` reader - Check the responses CRC"] -pub type CMD_CRCCHK_EN_R = crate::BitReader; +pub type CMD_CRCCHK_EN_R = crate::BitReader; #[doc = "Field `CMD_CRCCHK_EN` writer - Check the responses CRC"] -pub type CMD_CRCCHK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +pub type CMD_CRCCHK_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMD_IXCHK_EN` reader - Check that the response has the same command index"] -pub type CMD_IXCHK_EN_R = crate::BitReader; +pub type CMD_IXCHK_EN_R = crate::BitReader; #[doc = "Field `CMD_IXCHK_EN` writer - Check that the response has the same command index"] -pub type CMD_IXCHK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +pub type CMD_IXCHK_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMD_ISDATA` reader - Command involves data"] -pub type CMD_ISDATA_R = crate::BitReader; +pub type CMD_ISDATA_R = crate::BitReader; #[doc = "Field `CMD_ISDATA` writer - Command involves data"] -pub type CMD_ISDATA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +pub type CMD_ISDATA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMD_TYPE` reader - Type of command to be issued"] -pub type CMD_TYPE_R = crate::FieldReader; +pub type CMD_TYPE_R = crate::FieldReader; #[doc = "Type of command to be issued\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -317,10 +303,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for CMD_TYPE_A { + type Ux = u8; +} impl CMD_TYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> CMD_TYPE_A { + pub const fn variant(&self) -> CMD_TYPE_A { match self.bits { 0 => CMD_TYPE_A::NORMAL, 1 => CMD_TYPE_A::SUSPEND, @@ -329,56 +318,59 @@ impl CMD_TYPE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "`0`"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == CMD_TYPE_A::NORMAL } - #[doc = "Checks if the value of the field is `SUSPEND`"] + #[doc = "`1`"] #[inline(always)] pub fn is_suspend(&self) -> bool { *self == CMD_TYPE_A::SUSPEND } - #[doc = "Checks if the value of the field is `RESUME`"] + #[doc = "`10`"] #[inline(always)] pub fn is_resume(&self) -> bool { *self == CMD_TYPE_A::RESUME } - #[doc = "Checks if the value of the field is `ABORT`"] + #[doc = "`11`"] #[inline(always)] pub fn is_abort(&self) -> bool { *self == CMD_TYPE_A::ABORT } } #[doc = "Field `CMD_TYPE` writer - Type of command to be issued"] -pub type CMD_TYPE_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, CMDTM_SPEC, u8, CMD_TYPE_A, 2, O>; -impl<'a, const O: u8> CMD_TYPE_W<'a, O> { +pub type CMD_TYPE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, CMD_TYPE_A>; +impl<'a, REG, const O: u8> CMD_TYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(CMD_TYPE_A::NORMAL) } #[doc = "`1`"] #[inline(always)] - pub fn suspend(self) -> &'a mut W { + pub fn suspend(self) -> &'a mut crate::W { self.variant(CMD_TYPE_A::SUSPEND) } #[doc = "`10`"] #[inline(always)] - pub fn resume(self) -> &'a mut W { + pub fn resume(self) -> &'a mut crate::W { self.variant(CMD_TYPE_A::RESUME) } #[doc = "`11`"] #[inline(always)] - pub fn abort(self) -> &'a mut W { + pub fn abort(self) -> &'a mut crate::W { self.variant(CMD_TYPE_A::ABORT) } } #[doc = "Field `CMD_INDEX` reader - Command index to be issued"] -pub type CMD_INDEX_R = crate::FieldReader; +pub type CMD_INDEX_R = crate::FieldReader; #[doc = "Field `CMD_INDEX` writer - Command index to be issued"] -pub type CMD_INDEX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMDTM_SPEC, u8, u8, 6, O>; +pub type CMD_INDEX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bit 1 - Enable block counter"] #[inline(always)] @@ -431,86 +423,126 @@ impl R { CMD_INDEX_R::new(((self.bits >> 24) & 0x3f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CMDTM") + .field("cmd_index", &format_args!("{}", self.cmd_index().bits())) + .field("cmd_type", &format_args!("{}", self.cmd_type().bits())) + .field("cmd_isdata", &format_args!("{}", self.cmd_isdata().bit())) + .field( + "cmd_ixchk_en", + &format_args!("{}", self.cmd_ixchk_en().bit()), + ) + .field( + "cmd_crcchk_en", + &format_args!("{}", self.cmd_crcchk_en().bit()), + ) + .field( + "cmd_rspns_type", + &format_args!("{}", self.cmd_rspns_type().bits()), + ) + .field( + "tm_multi_block", + &format_args!("{}", self.tm_multi_block().bit()), + ) + .field("tm_dat_dir", &format_args!("{}", self.tm_dat_dir().bit())) + .field( + "tm_auto_cmd_en", + &format_args!("{}", self.tm_auto_cmd_en().bits()), + ) + .field( + "tm_blkcnt_en", + &format_args!("{}", self.tm_blkcnt_en().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Enable block counter"] #[inline(always)] #[must_use] - pub fn tm_blkcnt_en(&mut self) -> TM_BLKCNT_EN_W<1> { + pub fn tm_blkcnt_en(&mut self) -> TM_BLKCNT_EN_W { TM_BLKCNT_EN_W::new(self) } #[doc = "Bits 2:3 - Command after completion"] #[inline(always)] #[must_use] - pub fn tm_auto_cmd_en(&mut self) -> TM_AUTO_CMD_EN_W<2> { + pub fn tm_auto_cmd_en(&mut self) -> TM_AUTO_CMD_EN_W { TM_AUTO_CMD_EN_W::new(self) } #[doc = "Bit 4 - Direction of data transfer"] #[inline(always)] #[must_use] - pub fn tm_dat_dir(&mut self) -> TM_DAT_DIR_W<4> { + pub fn tm_dat_dir(&mut self) -> TM_DAT_DIR_W { TM_DAT_DIR_W::new(self) } #[doc = "Bit 5 - Type of data transfer"] #[inline(always)] #[must_use] - pub fn tm_multi_block(&mut self) -> TM_MULTI_BLOCK_W<5> { + pub fn tm_multi_block(&mut self) -> TM_MULTI_BLOCK_W { TM_MULTI_BLOCK_W::new(self) } #[doc = "Bits 16:17 - Type of expected response"] #[inline(always)] #[must_use] - pub fn cmd_rspns_type(&mut self) -> CMD_RSPNS_TYPE_W<16> { + pub fn cmd_rspns_type(&mut self) -> CMD_RSPNS_TYPE_W { CMD_RSPNS_TYPE_W::new(self) } #[doc = "Bit 19 - Check the responses CRC"] #[inline(always)] #[must_use] - pub fn cmd_crcchk_en(&mut self) -> CMD_CRCCHK_EN_W<19> { + pub fn cmd_crcchk_en(&mut self) -> CMD_CRCCHK_EN_W { CMD_CRCCHK_EN_W::new(self) } #[doc = "Bit 20 - Check that the response has the same command index"] #[inline(always)] #[must_use] - pub fn cmd_ixchk_en(&mut self) -> CMD_IXCHK_EN_W<20> { + pub fn cmd_ixchk_en(&mut self) -> CMD_IXCHK_EN_W { CMD_IXCHK_EN_W::new(self) } #[doc = "Bit 21 - Command involves data"] #[inline(always)] #[must_use] - pub fn cmd_isdata(&mut self) -> CMD_ISDATA_W<21> { + pub fn cmd_isdata(&mut self) -> CMD_ISDATA_W { CMD_ISDATA_W::new(self) } #[doc = "Bits 22:23 - Type of command to be issued"] #[inline(always)] #[must_use] - pub fn cmd_type(&mut self) -> CMD_TYPE_W<22> { + pub fn cmd_type(&mut self) -> CMD_TYPE_W { CMD_TYPE_W::new(self) } #[doc = "Bits 24:29 - Command index to be issued"] #[inline(always)] #[must_use] - pub fn cmd_index(&mut self) -> CMD_INDEX_W<24> { + pub fn cmd_index(&mut self) -> CMD_INDEX_W { CMD_INDEX_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Issue commands to the card\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmdtm](index.html) module"] +#[doc = "Issue commands to the card\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdtm::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdtm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMDTM_SPEC; impl crate::RegisterSpec for CMDTM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cmdtm::R](R) reader structure"] -impl crate::Readable for CMDTM_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cmdtm::W](W) writer structure"] +#[doc = "`read()` method returns [`cmdtm::R`](R) reader structure"] +impl crate::Readable for CMDTM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmdtm::W`](W) writer structure"] impl crate::Writable for CMDTM_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/control0.rs b/crates/bcm2711-lpa/src/emmc/control0.rs index 948b94b..47fb08f 100644 --- a/crates/bcm2711-lpa/src/emmc/control0.rs +++ b/crates/bcm2711-lpa/src/emmc/control0.rs @@ -1,79 +1,47 @@ #[doc = "Register `CONTROL0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONTROL0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HCTL_DWIDTH` reader - Use 4 data lines"] -pub type HCTL_DWIDTH_R = crate::BitReader; +pub type HCTL_DWIDTH_R = crate::BitReader; #[doc = "Field `HCTL_DWIDTH` writer - Use 4 data lines"] -pub type HCTL_DWIDTH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type HCTL_DWIDTH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HCTL_HS_EN` reader - Enable high speed mode"] -pub type HCTL_HS_EN_R = crate::BitReader; +pub type HCTL_HS_EN_R = crate::BitReader; #[doc = "Field `HCTL_HS_EN` writer - Enable high speed mode"] -pub type HCTL_HS_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type HCTL_HS_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HCTL_8BIT` reader - Use 8 data lines"] -pub type HCTL_8BIT_R = crate::BitReader; +pub type HCTL_8BIT_R = crate::BitReader; #[doc = "Field `HCTL_8BIT` writer - Use 8 data lines"] -pub type HCTL_8BIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type HCTL_8BIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAP_STOP` reader - Stop the current transaction at the next block gap"] -pub type GAP_STOP_R = crate::BitReader; +pub type GAP_STOP_R = crate::BitReader; #[doc = "Field `GAP_STOP` writer - Stop the current transaction at the next block gap"] -pub type GAP_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type GAP_STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAP_RESTART` reader - Restart a transaction stopped by GAP_STOP"] -pub type GAP_RESTART_R = crate::BitReader; +pub type GAP_RESTART_R = crate::BitReader; #[doc = "Field `GAP_RESTART` writer - Restart a transaction stopped by GAP_STOP"] -pub type GAP_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type GAP_RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READWAIT_EN` reader - Use DAT2 read/wait protocol"] -pub type READWAIT_EN_R = crate::BitReader; +pub type READWAIT_EN_R = crate::BitReader; #[doc = "Field `READWAIT_EN` writer - Use DAT2 read/wait protocol"] -pub type READWAIT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type READWAIT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAP_IEN` reader - Enable interrupt on block gap"] -pub type GAP_IEN_R = crate::BitReader; +pub type GAP_IEN_R = crate::BitReader; #[doc = "Field `GAP_IEN` writer - Enable interrupt on block gap"] -pub type GAP_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type GAP_IEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_MODE` reader - Enable SPI mode"] -pub type SPI_MODE_R = crate::BitReader; +pub type SPI_MODE_R = crate::BitReader; #[doc = "Field `SPI_MODE` writer - Enable SPI mode"] -pub type SPI_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type SPI_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOT_EN` reader - Boot mode enabled"] -pub type BOOT_EN_R = crate::BitReader; +pub type BOOT_EN_R = crate::BitReader; #[doc = "Field `BOOT_EN` writer - Boot mode enabled"] -pub type BOOT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type BOOT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ALT_BOOT_EN` reader - Enable alternate boot mode"] -pub type ALT_BOOT_EN_R = crate::BitReader; +pub type ALT_BOOT_EN_R = crate::BitReader; #[doc = "Field `ALT_BOOT_EN` writer - Enable alternate boot mode"] -pub type ALT_BOOT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type ALT_BOOT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - Use 4 data lines"] #[inline(always)] @@ -126,86 +94,108 @@ impl R { ALT_BOOT_EN_R::new(((self.bits >> 22) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONTROL0") + .field("alt_boot_en", &format_args!("{}", self.alt_boot_en().bit())) + .field("boot_en", &format_args!("{}", self.boot_en().bit())) + .field("spi_mode", &format_args!("{}", self.spi_mode().bit())) + .field("gap_ien", &format_args!("{}", self.gap_ien().bit())) + .field("readwait_en", &format_args!("{}", self.readwait_en().bit())) + .field("gap_restart", &format_args!("{}", self.gap_restart().bit())) + .field("gap_stop", &format_args!("{}", self.gap_stop().bit())) + .field("hctl_8bit", &format_args!("{}", self.hctl_8bit().bit())) + .field("hctl_hs_en", &format_args!("{}", self.hctl_hs_en().bit())) + .field("hctl_dwidth", &format_args!("{}", self.hctl_dwidth().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Use 4 data lines"] #[inline(always)] #[must_use] - pub fn hctl_dwidth(&mut self) -> HCTL_DWIDTH_W<1> { + pub fn hctl_dwidth(&mut self) -> HCTL_DWIDTH_W { HCTL_DWIDTH_W::new(self) } #[doc = "Bit 2 - Enable high speed mode"] #[inline(always)] #[must_use] - pub fn hctl_hs_en(&mut self) -> HCTL_HS_EN_W<2> { + pub fn hctl_hs_en(&mut self) -> HCTL_HS_EN_W { HCTL_HS_EN_W::new(self) } #[doc = "Bit 5 - Use 8 data lines"] #[inline(always)] #[must_use] - pub fn hctl_8bit(&mut self) -> HCTL_8BIT_W<5> { + pub fn hctl_8bit(&mut self) -> HCTL_8BIT_W { HCTL_8BIT_W::new(self) } #[doc = "Bit 16 - Stop the current transaction at the next block gap"] #[inline(always)] #[must_use] - pub fn gap_stop(&mut self) -> GAP_STOP_W<16> { + pub fn gap_stop(&mut self) -> GAP_STOP_W { GAP_STOP_W::new(self) } #[doc = "Bit 17 - Restart a transaction stopped by GAP_STOP"] #[inline(always)] #[must_use] - pub fn gap_restart(&mut self) -> GAP_RESTART_W<17> { + pub fn gap_restart(&mut self) -> GAP_RESTART_W { GAP_RESTART_W::new(self) } #[doc = "Bit 18 - Use DAT2 read/wait protocol"] #[inline(always)] #[must_use] - pub fn readwait_en(&mut self) -> READWAIT_EN_W<18> { + pub fn readwait_en(&mut self) -> READWAIT_EN_W { READWAIT_EN_W::new(self) } #[doc = "Bit 19 - Enable interrupt on block gap"] #[inline(always)] #[must_use] - pub fn gap_ien(&mut self) -> GAP_IEN_W<19> { + pub fn gap_ien(&mut self) -> GAP_IEN_W { GAP_IEN_W::new(self) } #[doc = "Bit 20 - Enable SPI mode"] #[inline(always)] #[must_use] - pub fn spi_mode(&mut self) -> SPI_MODE_W<20> { + pub fn spi_mode(&mut self) -> SPI_MODE_W { SPI_MODE_W::new(self) } #[doc = "Bit 21 - Boot mode enabled"] #[inline(always)] #[must_use] - pub fn boot_en(&mut self) -> BOOT_EN_W<21> { + pub fn boot_en(&mut self) -> BOOT_EN_W { BOOT_EN_W::new(self) } #[doc = "Bit 22 - Enable alternate boot mode"] #[inline(always)] #[must_use] - pub fn alt_boot_en(&mut self) -> ALT_BOOT_EN_W<22> { + pub fn alt_boot_en(&mut self) -> ALT_BOOT_EN_W { ALT_BOOT_EN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control0](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONTROL0_SPEC; impl crate::RegisterSpec for CONTROL0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [control0::R](R) reader structure"] -impl crate::Readable for CONTROL0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [control0::W](W) writer structure"] +#[doc = "`read()` method returns [`control0::R`](R) reader structure"] +impl crate::Readable for CONTROL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`control0::W`](W) writer structure"] impl crate::Writable for CONTROL0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/control1.rs b/crates/bcm2711-lpa/src/emmc/control1.rs index 1dc7cb3..40a8765 100644 --- a/crates/bcm2711-lpa/src/emmc/control1.rs +++ b/crates/bcm2711-lpa/src/emmc/control1.rs @@ -1,49 +1,17 @@ #[doc = "Register `CONTROL1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONTROL1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLK_INTLEN` reader - Enable internal clock"] -pub type CLK_INTLEN_R = crate::BitReader; +pub type CLK_INTLEN_R = crate::BitReader; #[doc = "Field `CLK_INTLEN` writer - Enable internal clock"] -pub type CLK_INTLEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type CLK_INTLEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLK_STABLE` reader - SD Clock stable"] -pub type CLK_STABLE_R = crate::BitReader; +pub type CLK_STABLE_R = crate::BitReader; #[doc = "Field `CLK_EN` reader - SD Clock enable"] -pub type CLK_EN_R = crate::BitReader; +pub type CLK_EN_R = crate::BitReader; #[doc = "Field `CLK_EN` writer - SD Clock enable"] -pub type CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type CLK_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLK_GENSEL` reader - Mode of clock generation"] pub type CLK_GENSEL_R = crate::BitReader; #[doc = "Mode of clock generation\n\nValue on reset: 0"] @@ -63,61 +31,64 @@ impl From for bool { impl CLK_GENSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> CLK_GENSEL_A { + pub const fn variant(&self) -> CLK_GENSEL_A { match self.bits { false => CLK_GENSEL_A::DIVIDED, true => CLK_GENSEL_A::PROGRAMMABLE, } } - #[doc = "Checks if the value of the field is `DIVIDED`"] + #[doc = "`0`"] #[inline(always)] pub fn is_divided(&self) -> bool { *self == CLK_GENSEL_A::DIVIDED } - #[doc = "Checks if the value of the field is `PROGRAMMABLE`"] + #[doc = "`1`"] #[inline(always)] pub fn is_programmable(&self) -> bool { *self == CLK_GENSEL_A::PROGRAMMABLE } } #[doc = "Field `CLK_GENSEL` writer - Mode of clock generation"] -pub type CLK_GENSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, CLK_GENSEL_A, O>; -impl<'a, const O: u8> CLK_GENSEL_W<'a, O> { +pub type CLK_GENSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CLK_GENSEL_A>; +impl<'a, REG, const O: u8> CLK_GENSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn divided(self) -> &'a mut W { + pub fn divided(self) -> &'a mut crate::W { self.variant(CLK_GENSEL_A::DIVIDED) } #[doc = "`1`"] #[inline(always)] - pub fn programmable(self) -> &'a mut W { + pub fn programmable(self) -> &'a mut crate::W { self.variant(CLK_GENSEL_A::PROGRAMMABLE) } } #[doc = "Field `CLK_FREQ_MS2` reader - Clock base divider MSBs"] -pub type CLK_FREQ_MS2_R = crate::FieldReader; +pub type CLK_FREQ_MS2_R = crate::FieldReader; #[doc = "Field `CLK_FREQ_MS2` writer - Clock base divider MSBs"] -pub type CLK_FREQ_MS2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 2, O>; +pub type CLK_FREQ_MS2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `CLK_FREQ8` reader - Clock base divider LSB"] -pub type CLK_FREQ8_R = crate::FieldReader; +pub type CLK_FREQ8_R = crate::FieldReader; #[doc = "Field `CLK_FREQ8` writer - Clock base divider LSB"] -pub type CLK_FREQ8_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 8, O>; +pub type CLK_FREQ8_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DATA_TOUNIT` reader - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] -pub type DATA_TOUNIT_R = crate::FieldReader; +pub type DATA_TOUNIT_R = crate::FieldReader; #[doc = "Field `DATA_TOUNIT` writer - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] -pub type DATA_TOUNIT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 4, O>; +pub type DATA_TOUNIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `SRST_HC` reader - Reset the complete host circuit"] -pub type SRST_HC_R = crate::BitReader; +pub type SRST_HC_R = crate::BitReader; #[doc = "Field `SRST_HC` writer - Reset the complete host circuit"] -pub type SRST_HC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type SRST_HC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRST_CMD` reader - Reset the command handling circuit"] -pub type SRST_CMD_R = crate::BitReader; +pub type SRST_CMD_R = crate::BitReader; #[doc = "Field `SRST_CMD` writer - Reset the command handling circuit"] -pub type SRST_CMD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type SRST_CMD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRST_DATA` reader - Reset the data handling circuit"] -pub type SRST_DATA_R = crate::BitReader; +pub type SRST_DATA_R = crate::BitReader; #[doc = "Field `SRST_DATA` writer - Reset the data handling circuit"] -pub type SRST_DATA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type SRST_DATA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable internal clock"] #[inline(always)] @@ -170,80 +141,108 @@ impl R { SRST_DATA_R::new(((self.bits >> 26) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONTROL1") + .field("srst_data", &format_args!("{}", self.srst_data().bit())) + .field("srst_cmd", &format_args!("{}", self.srst_cmd().bit())) + .field("srst_hc", &format_args!("{}", self.srst_hc().bit())) + .field( + "data_tounit", + &format_args!("{}", self.data_tounit().bits()), + ) + .field("clk_freq8", &format_args!("{}", self.clk_freq8().bits())) + .field( + "clk_freq_ms2", + &format_args!("{}", self.clk_freq_ms2().bits()), + ) + .field("clk_gensel", &format_args!("{}", self.clk_gensel().bit())) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .field("clk_stable", &format_args!("{}", self.clk_stable().bit())) + .field("clk_intlen", &format_args!("{}", self.clk_intlen().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable internal clock"] #[inline(always)] #[must_use] - pub fn clk_intlen(&mut self) -> CLK_INTLEN_W<0> { + pub fn clk_intlen(&mut self) -> CLK_INTLEN_W { CLK_INTLEN_W::new(self) } #[doc = "Bit 2 - SD Clock enable"] #[inline(always)] #[must_use] - pub fn clk_en(&mut self) -> CLK_EN_W<2> { + pub fn clk_en(&mut self) -> CLK_EN_W { CLK_EN_W::new(self) } #[doc = "Bit 5 - Mode of clock generation"] #[inline(always)] #[must_use] - pub fn clk_gensel(&mut self) -> CLK_GENSEL_W<5> { + pub fn clk_gensel(&mut self) -> CLK_GENSEL_W { CLK_GENSEL_W::new(self) } #[doc = "Bits 6:7 - Clock base divider MSBs"] #[inline(always)] #[must_use] - pub fn clk_freq_ms2(&mut self) -> CLK_FREQ_MS2_W<6> { + pub fn clk_freq_ms2(&mut self) -> CLK_FREQ_MS2_W { CLK_FREQ_MS2_W::new(self) } #[doc = "Bits 8:15 - Clock base divider LSB"] #[inline(always)] #[must_use] - pub fn clk_freq8(&mut self) -> CLK_FREQ8_W<8> { + pub fn clk_freq8(&mut self) -> CLK_FREQ8_W { CLK_FREQ8_W::new(self) } #[doc = "Bits 16:19 - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] #[inline(always)] #[must_use] - pub fn data_tounit(&mut self) -> DATA_TOUNIT_W<16> { + pub fn data_tounit(&mut self) -> DATA_TOUNIT_W { DATA_TOUNIT_W::new(self) } #[doc = "Bit 24 - Reset the complete host circuit"] #[inline(always)] #[must_use] - pub fn srst_hc(&mut self) -> SRST_HC_W<24> { + pub fn srst_hc(&mut self) -> SRST_HC_W { SRST_HC_W::new(self) } #[doc = "Bit 25 - Reset the command handling circuit"] #[inline(always)] #[must_use] - pub fn srst_cmd(&mut self) -> SRST_CMD_W<25> { + pub fn srst_cmd(&mut self) -> SRST_CMD_W { SRST_CMD_W::new(self) } #[doc = "Bit 26 - Reset the data handling circuit"] #[inline(always)] #[must_use] - pub fn srst_data(&mut self) -> SRST_DATA_W<26> { + pub fn srst_data(&mut self) -> SRST_DATA_W { SRST_DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Configure\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control1](index.html) module"] +#[doc = "Configure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONTROL1_SPEC; impl crate::RegisterSpec for CONTROL1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [control1::R](R) reader structure"] -impl crate::Readable for CONTROL1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [control1::W](W) writer structure"] +#[doc = "`read()` method returns [`control1::R`](R) reader structure"] +impl crate::Readable for CONTROL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`control1::W`](W) writer structure"] impl crate::Writable for CONTROL1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/control2.rs b/crates/bcm2711-lpa/src/emmc/control2.rs index 1bc9076..bb052fc 100644 --- a/crates/bcm2711-lpa/src/emmc/control2.rs +++ b/crates/bcm2711-lpa/src/emmc/control2.rs @@ -1,53 +1,21 @@ #[doc = "Register `CONTROL2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONTROL2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ACNOX_ERR` reader - Auto command not executed due to an error"] -pub type ACNOX_ERR_R = crate::BitReader; +pub type ACNOX_ERR_R = crate::BitReader; #[doc = "Field `ACTO_ERR` reader - Auto command timeout"] -pub type ACTO_ERR_R = crate::BitReader; +pub type ACTO_ERR_R = crate::BitReader; #[doc = "Field `ACCRC_ERR` reader - Command CRC error during auto command"] -pub type ACCRC_ERR_R = crate::BitReader; +pub type ACCRC_ERR_R = crate::BitReader; #[doc = "Field `ACEND_ERR` reader - End bit is not 1 during auto command"] -pub type ACEND_ERR_R = crate::BitReader; +pub type ACEND_ERR_R = crate::BitReader; #[doc = "Field `ACBAD_ERR` reader - Command index error during auto command"] -pub type ACBAD_ERR_R = crate::BitReader; +pub type ACBAD_ERR_R = crate::BitReader; #[doc = "Field `NOTC12_ERR` reader - Error during auto CMD12"] -pub type NOTC12_ERR_R = crate::BitReader; +pub type NOTC12_ERR_R = crate::BitReader; #[doc = "Field `UHSMODE` reader - Select the speed of the SD card"] -pub type UHSMODE_R = crate::FieldReader; +pub type UHSMODE_R = crate::FieldReader; #[doc = "Select the speed of the SD card\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -69,10 +37,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for UHSMODE_A { + type Ux = u8; +} impl UHSMODE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(UHSMODE_A::SDR12), 1 => Some(UHSMODE_A::SDR25), @@ -82,70 +53,73 @@ impl UHSMODE_R { _ => None, } } - #[doc = "Checks if the value of the field is `SDR12`"] + #[doc = "`0`"] #[inline(always)] pub fn is_sdr12(&self) -> bool { *self == UHSMODE_A::SDR12 } - #[doc = "Checks if the value of the field is `SDR25`"] + #[doc = "`1`"] #[inline(always)] pub fn is_sdr25(&self) -> bool { *self == UHSMODE_A::SDR25 } - #[doc = "Checks if the value of the field is `SDR50`"] + #[doc = "`10`"] #[inline(always)] pub fn is_sdr50(&self) -> bool { *self == UHSMODE_A::SDR50 } - #[doc = "Checks if the value of the field is `SDR104`"] + #[doc = "`11`"] #[inline(always)] pub fn is_sdr104(&self) -> bool { *self == UHSMODE_A::SDR104 } - #[doc = "Checks if the value of the field is `DDR50`"] + #[doc = "`100`"] #[inline(always)] pub fn is_ddr50(&self) -> bool { *self == UHSMODE_A::DDR50 } } #[doc = "Field `UHSMODE` writer - Select the speed of the SD card"] -pub type UHSMODE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, CONTROL2_SPEC, u8, UHSMODE_A, 3, O>; -impl<'a, const O: u8> UHSMODE_W<'a, O> { +pub type UHSMODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, UHSMODE_A>; +impl<'a, REG, const O: u8> UHSMODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn sdr12(self) -> &'a mut W { + pub fn sdr12(self) -> &'a mut crate::W { self.variant(UHSMODE_A::SDR12) } #[doc = "`1`"] #[inline(always)] - pub fn sdr25(self) -> &'a mut W { + pub fn sdr25(self) -> &'a mut crate::W { self.variant(UHSMODE_A::SDR25) } #[doc = "`10`"] #[inline(always)] - pub fn sdr50(self) -> &'a mut W { + pub fn sdr50(self) -> &'a mut crate::W { self.variant(UHSMODE_A::SDR50) } #[doc = "`11`"] #[inline(always)] - pub fn sdr104(self) -> &'a mut W { + pub fn sdr104(self) -> &'a mut crate::W { self.variant(UHSMODE_A::SDR104) } #[doc = "`100`"] #[inline(always)] - pub fn ddr50(self) -> &'a mut W { + pub fn ddr50(self) -> &'a mut crate::W { self.variant(UHSMODE_A::DDR50) } } #[doc = "Field `TUNEON` reader - SD Clock tune in progress"] -pub type TUNEON_R = crate::BitReader; +pub type TUNEON_R = crate::BitReader; #[doc = "Field `TUNEON` writer - SD Clock tune in progress"] -pub type TUNEON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL2_SPEC, bool, O>; +pub type TUNEON_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TUNED` reader - Tuned clock is used for sampling data"] -pub type TUNED_R = crate::BitReader; +pub type TUNED_R = crate::BitReader; #[doc = "Field `TUNED` writer - Tuned clock is used for sampling data"] -pub type TUNED_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL2_SPEC, bool, O>; +pub type TUNED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Auto command not executed due to an error"] #[inline(always)] @@ -193,44 +167,65 @@ impl R { TUNED_R::new(((self.bits >> 23) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONTROL2") + .field("tuned", &format_args!("{}", self.tuned().bit())) + .field("tuneon", &format_args!("{}", self.tuneon().bit())) + .field("uhsmode", &format_args!("{}", self.uhsmode().bits())) + .field("notc12_err", &format_args!("{}", self.notc12_err().bit())) + .field("acbad_err", &format_args!("{}", self.acbad_err().bit())) + .field("acend_err", &format_args!("{}", self.acend_err().bit())) + .field("accrc_err", &format_args!("{}", self.accrc_err().bit())) + .field("acto_err", &format_args!("{}", self.acto_err().bit())) + .field("acnox_err", &format_args!("{}", self.acnox_err().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 16:18 - Select the speed of the SD card"] #[inline(always)] #[must_use] - pub fn uhsmode(&mut self) -> UHSMODE_W<16> { + pub fn uhsmode(&mut self) -> UHSMODE_W { UHSMODE_W::new(self) } #[doc = "Bit 22 - SD Clock tune in progress"] #[inline(always)] #[must_use] - pub fn tuneon(&mut self) -> TUNEON_W<22> { + pub fn tuneon(&mut self) -> TUNEON_W { TUNEON_W::new(self) } #[doc = "Bit 23 - Tuned clock is used for sampling data"] #[inline(always)] #[must_use] - pub fn tuned(&mut self) -> TUNED_W<23> { + pub fn tuned(&mut self) -> TUNED_W { TUNED_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control2](index.html) module"] +#[doc = "Control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONTROL2_SPEC; impl crate::RegisterSpec for CONTROL2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [control2::R](R) reader structure"] -impl crate::Readable for CONTROL2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [control2::W](W) writer structure"] +#[doc = "`read()` method returns [`control2::R`](R) reader structure"] +impl crate::Readable for CONTROL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`control2::W`](W) writer structure"] impl crate::Writable for CONTROL2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/data.rs b/crates/bcm2711-lpa/src/emmc/data.rs index 8c082b8..ac2280f 100644 --- a/crates/bcm2711-lpa/src/emmc/data.rs +++ b/crates/bcm2711-lpa/src/emmc/data.rs @@ -1,59 +1,38 @@ #[doc = "Register `DATA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DATA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data to/from the card\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +#[doc = "Data to/from the card\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DATA_SPEC; impl crate::RegisterSpec for DATA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [data::R](R) reader structure"] -impl crate::Readable for DATA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] impl crate::Writable for DATA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/dbg_sel.rs b/crates/bcm2711-lpa/src/emmc/dbg_sel.rs index c489a27..343a4db 100644 --- a/crates/bcm2711-lpa/src/emmc/dbg_sel.rs +++ b/crates/bcm2711-lpa/src/emmc/dbg_sel.rs @@ -1,39 +1,7 @@ #[doc = "Register `DBG_SEL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DBG_SEL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SELECT` reader - "] pub type SELECT_R = crate::BitReader; #[doc = "\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl SELECT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SELECT_A { + pub const fn variant(&self) -> SELECT_A { match self.bits { false => SELECT_A::RECEIVER_FIFO, true => SELECT_A::OTHERS, } } - #[doc = "Checks if the value of the field is `RECEIVER_FIFO`"] + #[doc = "`0`"] #[inline(always)] pub fn is_receiver_fifo(&self) -> bool { *self == SELECT_A::RECEIVER_FIFO } - #[doc = "Checks if the value of the field is `OTHERS`"] + #[doc = "`1`"] #[inline(always)] pub fn is_others(&self) -> bool { *self == SELECT_A::OTHERS } } #[doc = "Field `SELECT` writer - "] -pub type SELECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DBG_SEL_SPEC, SELECT_A, O>; -impl<'a, const O: u8> SELECT_W<'a, O> { +pub type SELECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SELECT_A>; +impl<'a, REG, const O: u8> SELECT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn receiver_fifo(self) -> &'a mut W { + pub fn receiver_fifo(self) -> &'a mut crate::W { self.variant(SELECT_A::RECEIVER_FIFO) } #[doc = "`1`"] #[inline(always)] - pub fn others(self) -> &'a mut W { + pub fn others(self) -> &'a mut crate::W { self.variant(SELECT_A::OTHERS) } } @@ -91,32 +62,45 @@ impl R { SELECT_R::new((self.bits & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBG_SEL") + .field("select", &format_args!("{}", self.select().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn select(&mut self) -> SELECT_W<0> { + pub fn select(&mut self) -> SELECT_W { SELECT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "What submodules are accessed by the debug bus\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbg_sel](index.html) module"] +#[doc = "What submodules are accessed by the debug bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbg_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DBG_SEL_SPEC; impl crate::RegisterSpec for DBG_SEL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dbg_sel::R](R) reader structure"] -impl crate::Readable for DBG_SEL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dbg_sel::W](W) writer structure"] +#[doc = "`read()` method returns [`dbg_sel::R`](R) reader structure"] +impl crate::Readable for DBG_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbg_sel::W`](W) writer structure"] impl crate::Writable for DBG_SEL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/exrdfifo_cfg.rs b/crates/bcm2711-lpa/src/emmc/exrdfifo_cfg.rs index 1c7e3be..13440a1 100644 --- a/crates/bcm2711-lpa/src/emmc/exrdfifo_cfg.rs +++ b/crates/bcm2711-lpa/src/emmc/exrdfifo_cfg.rs @@ -1,43 +1,11 @@ #[doc = "Register `EXRDFIFO_CFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EXRDFIFO_CFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RD_THRSH` reader - Read threshold in 32 bit words"] -pub type RD_THRSH_R = crate::FieldReader; +pub type RD_THRSH_R = crate::FieldReader; #[doc = "Field `RD_THRSH` writer - Read threshold in 32 bit words"] -pub type RD_THRSH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXRDFIFO_CFG_SPEC, u8, u8, 3, O>; +pub type RD_THRSH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:2 - Read threshold in 32 bit words"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { RD_THRSH_R::new((self.bits & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXRDFIFO_CFG") + .field("rd_thrsh", &format_args!("{}", self.rd_thrsh().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Read threshold in 32 bit words"] #[inline(always)] #[must_use] - pub fn rd_thrsh(&mut self) -> RD_THRSH_W<0> { + pub fn rd_thrsh(&mut self) -> RD_THRSH_W { RD_THRSH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Fine tune DMA request generation\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exrdfifo_cfg](index.html) module"] +#[doc = "Fine tune DMA request generation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exrdfifo_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrdfifo_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EXRDFIFO_CFG_SPEC; impl crate::RegisterSpec for EXRDFIFO_CFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [exrdfifo_cfg::R](R) reader structure"] -impl crate::Readable for EXRDFIFO_CFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [exrdfifo_cfg::W](W) writer structure"] +#[doc = "`read()` method returns [`exrdfifo_cfg::R`](R) reader structure"] +impl crate::Readable for EXRDFIFO_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`exrdfifo_cfg::W`](W) writer structure"] impl crate::Writable for EXRDFIFO_CFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/exrdfifo_en.rs b/crates/bcm2711-lpa/src/emmc/exrdfifo_en.rs index 26c7adc..e6b6583 100644 --- a/crates/bcm2711-lpa/src/emmc/exrdfifo_en.rs +++ b/crates/bcm2711-lpa/src/emmc/exrdfifo_en.rs @@ -1,43 +1,11 @@ #[doc = "Register `EXRDFIFO_EN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EXRDFIFO_EN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ENABLE` reader - Enable the extension FIFO"] -pub type ENABLE_R = crate::BitReader; +pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Enable the extension FIFO"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXRDFIFO_EN_SPEC, bool, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable the extension FIFO"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { ENABLE_R::new((self.bits & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXRDFIFO_EN") + .field("enable", &format_args!("{}", self.enable().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable the extension FIFO"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<0> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable the extension data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exrdfifo_en](index.html) module"] +#[doc = "Enable the extension data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exrdfifo_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrdfifo_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EXRDFIFO_EN_SPEC; impl crate::RegisterSpec for EXRDFIFO_EN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [exrdfifo_en::R](R) reader structure"] -impl crate::Readable for EXRDFIFO_EN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [exrdfifo_en::W](W) writer structure"] +#[doc = "`read()` method returns [`exrdfifo_en::R`](R) reader structure"] +impl crate::Readable for EXRDFIFO_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`exrdfifo_en::W`](W) writer structure"] impl crate::Writable for EXRDFIFO_EN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/force_irpt.rs b/crates/bcm2711-lpa/src/emmc/force_irpt.rs index eca9ec6..682b8fe 100644 --- a/crates/bcm2711-lpa/src/emmc/force_irpt.rs +++ b/crates/bcm2711-lpa/src/emmc/force_irpt.rs @@ -1,107 +1,75 @@ #[doc = "Register `FORCE_IRPT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FORCE_IRPT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_DONE` reader - Command has finished"] -pub type CMD_DONE_R = crate::BitReader; +pub type CMD_DONE_R = crate::BitReader; #[doc = "Field `CMD_DONE` writer - Command has finished"] -pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CMD_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_DONE` reader - Data transfer has finished"] -pub type DATA_DONE_R = crate::BitReader; +pub type DATA_DONE_R = crate::BitReader; #[doc = "Field `DATA_DONE` writer - Data transfer has finished"] -pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type DATA_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_R = crate::BitReader; +pub type BLOCK_GAP_R = crate::BitReader; #[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type BLOCK_GAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_RDY` reader - DATA can be written to"] -pub type WRITE_RDY_R = crate::BitReader; +pub type WRITE_RDY_R = crate::BitReader; #[doc = "Field `WRITE_RDY` writer - DATA can be written to"] -pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type WRITE_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_RDY` reader - DATA contains data to be read"] -pub type READ_RDY_R = crate::BitReader; +pub type READ_RDY_R = crate::BitReader; #[doc = "Field `READ_RDY` writer - DATA contains data to be read"] -pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type READ_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CARD` reader - Card made interrupt request"] -pub type CARD_R = crate::BitReader; +pub type CARD_R = crate::BitReader; #[doc = "Field `CARD` writer - Card made interrupt request"] -pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CARD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RETUNE` reader - Clock retune request"] -pub type RETUNE_R = crate::BitReader; +pub type RETUNE_R = crate::BitReader; #[doc = "Field `RETUNE` writer - Clock retune request"] -pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type RETUNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] -pub type BOOTACK_R = crate::BitReader; +pub type BOOTACK_R = crate::BitReader; #[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] -pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type BOOTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] -pub type ENDBOOT_R = crate::BitReader; +pub type ENDBOOT_R = crate::BitReader; #[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] -pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type ENDBOOT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTO_ERR` reader - Command timeout"] -pub type CTO_ERR_R = crate::BitReader; +pub type CTO_ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` writer - Command timeout"] -pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CCRC_ERR` reader - Command CRC error"] -pub type CCRC_ERR_R = crate::BitReader; +pub type CCRC_ERR_R = crate::BitReader; #[doc = "Field `CCRC_ERR` writer - Command CRC error"] -pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] -pub type CEND_ERR_R = crate::BitReader; +pub type CEND_ERR_R = crate::BitReader; #[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] -pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] -pub type CBAD_ERR_R = crate::BitReader; +pub type CBAD_ERR_R = crate::BitReader; #[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] -pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CBAD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTO_ERR` reader - Data timeout"] -pub type DTO_ERR_R = crate::BitReader; +pub type DTO_ERR_R = crate::BitReader; #[doc = "Field `DTO_ERR` writer - Data timeout"] -pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type DTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRC_ERR` reader - Data CRC error"] -pub type DCRC_ERR_R = crate::BitReader; +pub type DCRC_ERR_R = crate::BitReader; #[doc = "Field `DCRC_ERR` writer - Data CRC error"] -pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type DCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] -pub type DEND_ERR_R = crate::BitReader; +pub type DEND_ERR_R = crate::BitReader; #[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] -pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type DEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMD_ERR` reader - Auto command error"] -pub type ACMD_ERR_R = crate::BitReader; +pub type ACMD_ERR_R = crate::BitReader; #[doc = "Field `ACMD_ERR` writer - Auto command error"] -pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type ACMD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Command has finished"] #[inline(always)] @@ -189,128 +157,157 @@ impl R { ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FORCE_IRPT") + .field("acmd_err", &format_args!("{}", self.acmd_err().bit())) + .field("dend_err", &format_args!("{}", self.dend_err().bit())) + .field("dcrc_err", &format_args!("{}", self.dcrc_err().bit())) + .field("dto_err", &format_args!("{}", self.dto_err().bit())) + .field("cbad_err", &format_args!("{}", self.cbad_err().bit())) + .field("cend_err", &format_args!("{}", self.cend_err().bit())) + .field("ccrc_err", &format_args!("{}", self.ccrc_err().bit())) + .field("cto_err", &format_args!("{}", self.cto_err().bit())) + .field("endboot", &format_args!("{}", self.endboot().bit())) + .field("bootack", &format_args!("{}", self.bootack().bit())) + .field("retune", &format_args!("{}", self.retune().bit())) + .field("card", &format_args!("{}", self.card().bit())) + .field("read_rdy", &format_args!("{}", self.read_rdy().bit())) + .field("write_rdy", &format_args!("{}", self.write_rdy().bit())) + .field("block_gap", &format_args!("{}", self.block_gap().bit())) + .field("data_done", &format_args!("{}", self.data_done().bit())) + .field("cmd_done", &format_args!("{}", self.cmd_done().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command has finished"] #[inline(always)] #[must_use] - pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + pub fn cmd_done(&mut self) -> CMD_DONE_W { CMD_DONE_W::new(self) } #[doc = "Bit 1 - Data transfer has finished"] #[inline(always)] #[must_use] - pub fn data_done(&mut self) -> DATA_DONE_W<1> { + pub fn data_done(&mut self) -> DATA_DONE_W { DATA_DONE_W::new(self) } #[doc = "Bit 2 - Data transfer has stopped at block gap"] #[inline(always)] #[must_use] - pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + pub fn block_gap(&mut self) -> BLOCK_GAP_W { BLOCK_GAP_W::new(self) } #[doc = "Bit 4 - DATA can be written to"] #[inline(always)] #[must_use] - pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + pub fn write_rdy(&mut self) -> WRITE_RDY_W { WRITE_RDY_W::new(self) } #[doc = "Bit 5 - DATA contains data to be read"] #[inline(always)] #[must_use] - pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + pub fn read_rdy(&mut self) -> READ_RDY_W { READ_RDY_W::new(self) } #[doc = "Bit 8 - Card made interrupt request"] #[inline(always)] #[must_use] - pub fn card(&mut self) -> CARD_W<8> { + pub fn card(&mut self) -> CARD_W { CARD_W::new(self) } #[doc = "Bit 12 - Clock retune request"] #[inline(always)] #[must_use] - pub fn retune(&mut self) -> RETUNE_W<12> { + pub fn retune(&mut self) -> RETUNE_W { RETUNE_W::new(self) } #[doc = "Bit 13 - Boot has been acknowledged"] #[inline(always)] #[must_use] - pub fn bootack(&mut self) -> BOOTACK_W<13> { + pub fn bootack(&mut self) -> BOOTACK_W { BOOTACK_W::new(self) } #[doc = "Bit 14 - Boot operation has terminated"] #[inline(always)] #[must_use] - pub fn endboot(&mut self) -> ENDBOOT_W<14> { + pub fn endboot(&mut self) -> ENDBOOT_W { ENDBOOT_W::new(self) } #[doc = "Bit 16 - Command timeout"] #[inline(always)] #[must_use] - pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + pub fn cto_err(&mut self) -> CTO_ERR_W { CTO_ERR_W::new(self) } #[doc = "Bit 17 - Command CRC error"] #[inline(always)] #[must_use] - pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + pub fn ccrc_err(&mut self) -> CCRC_ERR_W { CCRC_ERR_W::new(self) } #[doc = "Bit 18 - Command end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + pub fn cend_err(&mut self) -> CEND_ERR_W { CEND_ERR_W::new(self) } #[doc = "Bit 19 - Incorrect response command index"] #[inline(always)] #[must_use] - pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + pub fn cbad_err(&mut self) -> CBAD_ERR_W { CBAD_ERR_W::new(self) } #[doc = "Bit 20 - Data timeout"] #[inline(always)] #[must_use] - pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + pub fn dto_err(&mut self) -> DTO_ERR_W { DTO_ERR_W::new(self) } #[doc = "Bit 21 - Data CRC error"] #[inline(always)] #[must_use] - pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + pub fn dcrc_err(&mut self) -> DCRC_ERR_W { DCRC_ERR_W::new(self) } #[doc = "Bit 22 - Data end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + pub fn dend_err(&mut self) -> DEND_ERR_W { DEND_ERR_W::new(self) } #[doc = "Bit 24 - Auto command error"] #[inline(always)] #[must_use] - pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + pub fn acmd_err(&mut self) -> ACMD_ERR_W { ACMD_ERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Force an interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [force_irpt](index.html) module"] +#[doc = "Force an interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`force_irpt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`force_irpt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FORCE_IRPT_SPEC; impl crate::RegisterSpec for FORCE_IRPT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [force_irpt::R](R) reader structure"] -impl crate::Readable for FORCE_IRPT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [force_irpt::W](W) writer structure"] +#[doc = "`read()` method returns [`force_irpt::R`](R) reader structure"] +impl crate::Readable for FORCE_IRPT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`force_irpt::W`](W) writer structure"] impl crate::Writable for FORCE_IRPT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/interrupt.rs b/crates/bcm2711-lpa/src/emmc/interrupt.rs index c687814..c28598f 100644 --- a/crates/bcm2711-lpa/src/emmc/interrupt.rs +++ b/crates/bcm2711-lpa/src/emmc/interrupt.rs @@ -1,109 +1,77 @@ #[doc = "Register `INTERRUPT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERRUPT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_DONE` reader - Command has finished"] -pub type CMD_DONE_R = crate::BitReader; +pub type CMD_DONE_R = crate::BitReader; #[doc = "Field `CMD_DONE` writer - Command has finished"] -pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CMD_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_DONE` reader - Data transfer has finished"] -pub type DATA_DONE_R = crate::BitReader; +pub type DATA_DONE_R = crate::BitReader; #[doc = "Field `DATA_DONE` writer - Data transfer has finished"] -pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type DATA_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_R = crate::BitReader; +pub type BLOCK_GAP_R = crate::BitReader; #[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type BLOCK_GAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_RDY` reader - DATA can be written to"] -pub type WRITE_RDY_R = crate::BitReader; +pub type WRITE_RDY_R = crate::BitReader; #[doc = "Field `WRITE_RDY` writer - DATA can be written to"] -pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type WRITE_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_RDY` reader - DATA contains data to be read"] -pub type READ_RDY_R = crate::BitReader; +pub type READ_RDY_R = crate::BitReader; #[doc = "Field `READ_RDY` writer - DATA contains data to be read"] -pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type READ_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CARD` reader - Card made interrupt request"] -pub type CARD_R = crate::BitReader; +pub type CARD_R = crate::BitReader; #[doc = "Field `CARD` writer - Card made interrupt request"] -pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CARD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RETUNE` reader - Clock retune request"] -pub type RETUNE_R = crate::BitReader; +pub type RETUNE_R = crate::BitReader; #[doc = "Field `RETUNE` writer - Clock retune request"] -pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type RETUNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] -pub type BOOTACK_R = crate::BitReader; +pub type BOOTACK_R = crate::BitReader; #[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] -pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type BOOTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] -pub type ENDBOOT_R = crate::BitReader; +pub type ENDBOOT_R = crate::BitReader; #[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] -pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type ENDBOOT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERR` reader - An error has occured"] -pub type ERR_R = crate::BitReader; +pub type ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` reader - Command timeout"] -pub type CTO_ERR_R = crate::BitReader; +pub type CTO_ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` writer - Command timeout"] -pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CCRC_ERR` reader - Command CRC error"] -pub type CCRC_ERR_R = crate::BitReader; +pub type CCRC_ERR_R = crate::BitReader; #[doc = "Field `CCRC_ERR` writer - Command CRC error"] -pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] -pub type CEND_ERR_R = crate::BitReader; +pub type CEND_ERR_R = crate::BitReader; #[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] -pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] -pub type CBAD_ERR_R = crate::BitReader; +pub type CBAD_ERR_R = crate::BitReader; #[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] -pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CBAD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTO_ERR` reader - Data timeout"] -pub type DTO_ERR_R = crate::BitReader; +pub type DTO_ERR_R = crate::BitReader; #[doc = "Field `DTO_ERR` writer - Data timeout"] -pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type DTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRC_ERR` reader - Data CRC error"] -pub type DCRC_ERR_R = crate::BitReader; +pub type DCRC_ERR_R = crate::BitReader; #[doc = "Field `DCRC_ERR` writer - Data CRC error"] -pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type DCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] -pub type DEND_ERR_R = crate::BitReader; +pub type DEND_ERR_R = crate::BitReader; #[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] -pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type DEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMD_ERR` reader - Auto command error"] -pub type ACMD_ERR_R = crate::BitReader; +pub type ACMD_ERR_R = crate::BitReader; #[doc = "Field `ACMD_ERR` writer - Auto command error"] -pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type ACMD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Command has finished"] #[inline(always)] @@ -196,128 +164,158 @@ impl R { ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTERRUPT") + .field("acmd_err", &format_args!("{}", self.acmd_err().bit())) + .field("dend_err", &format_args!("{}", self.dend_err().bit())) + .field("dcrc_err", &format_args!("{}", self.dcrc_err().bit())) + .field("dto_err", &format_args!("{}", self.dto_err().bit())) + .field("cbad_err", &format_args!("{}", self.cbad_err().bit())) + .field("cend_err", &format_args!("{}", self.cend_err().bit())) + .field("ccrc_err", &format_args!("{}", self.ccrc_err().bit())) + .field("cto_err", &format_args!("{}", self.cto_err().bit())) + .field("err", &format_args!("{}", self.err().bit())) + .field("endboot", &format_args!("{}", self.endboot().bit())) + .field("bootack", &format_args!("{}", self.bootack().bit())) + .field("retune", &format_args!("{}", self.retune().bit())) + .field("card", &format_args!("{}", self.card().bit())) + .field("read_rdy", &format_args!("{}", self.read_rdy().bit())) + .field("write_rdy", &format_args!("{}", self.write_rdy().bit())) + .field("block_gap", &format_args!("{}", self.block_gap().bit())) + .field("data_done", &format_args!("{}", self.data_done().bit())) + .field("cmd_done", &format_args!("{}", self.cmd_done().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command has finished"] #[inline(always)] #[must_use] - pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + pub fn cmd_done(&mut self) -> CMD_DONE_W { CMD_DONE_W::new(self) } #[doc = "Bit 1 - Data transfer has finished"] #[inline(always)] #[must_use] - pub fn data_done(&mut self) -> DATA_DONE_W<1> { + pub fn data_done(&mut self) -> DATA_DONE_W { DATA_DONE_W::new(self) } #[doc = "Bit 2 - Data transfer has stopped at block gap"] #[inline(always)] #[must_use] - pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + pub fn block_gap(&mut self) -> BLOCK_GAP_W { BLOCK_GAP_W::new(self) } #[doc = "Bit 4 - DATA can be written to"] #[inline(always)] #[must_use] - pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + pub fn write_rdy(&mut self) -> WRITE_RDY_W { WRITE_RDY_W::new(self) } #[doc = "Bit 5 - DATA contains data to be read"] #[inline(always)] #[must_use] - pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + pub fn read_rdy(&mut self) -> READ_RDY_W { READ_RDY_W::new(self) } #[doc = "Bit 8 - Card made interrupt request"] #[inline(always)] #[must_use] - pub fn card(&mut self) -> CARD_W<8> { + pub fn card(&mut self) -> CARD_W { CARD_W::new(self) } #[doc = "Bit 12 - Clock retune request"] #[inline(always)] #[must_use] - pub fn retune(&mut self) -> RETUNE_W<12> { + pub fn retune(&mut self) -> RETUNE_W { RETUNE_W::new(self) } #[doc = "Bit 13 - Boot has been acknowledged"] #[inline(always)] #[must_use] - pub fn bootack(&mut self) -> BOOTACK_W<13> { + pub fn bootack(&mut self) -> BOOTACK_W { BOOTACK_W::new(self) } #[doc = "Bit 14 - Boot operation has terminated"] #[inline(always)] #[must_use] - pub fn endboot(&mut self) -> ENDBOOT_W<14> { + pub fn endboot(&mut self) -> ENDBOOT_W { ENDBOOT_W::new(self) } #[doc = "Bit 16 - Command timeout"] #[inline(always)] #[must_use] - pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + pub fn cto_err(&mut self) -> CTO_ERR_W { CTO_ERR_W::new(self) } #[doc = "Bit 17 - Command CRC error"] #[inline(always)] #[must_use] - pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + pub fn ccrc_err(&mut self) -> CCRC_ERR_W { CCRC_ERR_W::new(self) } #[doc = "Bit 18 - Command end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + pub fn cend_err(&mut self) -> CEND_ERR_W { CEND_ERR_W::new(self) } #[doc = "Bit 19 - Incorrect response command index"] #[inline(always)] #[must_use] - pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + pub fn cbad_err(&mut self) -> CBAD_ERR_W { CBAD_ERR_W::new(self) } #[doc = "Bit 20 - Data timeout"] #[inline(always)] #[must_use] - pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + pub fn dto_err(&mut self) -> DTO_ERR_W { DTO_ERR_W::new(self) } #[doc = "Bit 21 - Data CRC error"] #[inline(always)] #[must_use] - pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + pub fn dcrc_err(&mut self) -> DCRC_ERR_W { DCRC_ERR_W::new(self) } #[doc = "Bit 22 - Data end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + pub fn dend_err(&mut self) -> DEND_ERR_W { DEND_ERR_W::new(self) } #[doc = "Bit 24 - Auto command error"] #[inline(always)] #[must_use] - pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + pub fn acmd_err(&mut self) -> ACMD_ERR_W { ACMD_ERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt flags\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt](index.html) module"] +#[doc = "Interrupt flags\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERRUPT_SPEC; impl crate::RegisterSpec for INTERRUPT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interrupt::R](R) reader structure"] -impl crate::Readable for INTERRUPT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interrupt::W](W) writer structure"] +#[doc = "`read()` method returns [`interrupt::R`](R) reader structure"] +impl crate::Readable for INTERRUPT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interrupt::W`](W) writer structure"] impl crate::Writable for INTERRUPT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/irpt_en.rs b/crates/bcm2711-lpa/src/emmc/irpt_en.rs index 0e71317..af7bc80 100644 --- a/crates/bcm2711-lpa/src/emmc/irpt_en.rs +++ b/crates/bcm2711-lpa/src/emmc/irpt_en.rs @@ -1,107 +1,75 @@ #[doc = "Register `IRPT_EN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRPT_EN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_DONE` reader - Command has finished"] -pub type CMD_DONE_R = crate::BitReader; +pub type CMD_DONE_R = crate::BitReader; #[doc = "Field `CMD_DONE` writer - Command has finished"] -pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CMD_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_DONE` reader - Data transfer has finished"] -pub type DATA_DONE_R = crate::BitReader; +pub type DATA_DONE_R = crate::BitReader; #[doc = "Field `DATA_DONE` writer - Data transfer has finished"] -pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type DATA_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_R = crate::BitReader; +pub type BLOCK_GAP_R = crate::BitReader; #[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type BLOCK_GAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_RDY` reader - DATA can be written to"] -pub type WRITE_RDY_R = crate::BitReader; +pub type WRITE_RDY_R = crate::BitReader; #[doc = "Field `WRITE_RDY` writer - DATA can be written to"] -pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type WRITE_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_RDY` reader - DATA contains data to be read"] -pub type READ_RDY_R = crate::BitReader; +pub type READ_RDY_R = crate::BitReader; #[doc = "Field `READ_RDY` writer - DATA contains data to be read"] -pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type READ_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CARD` reader - Card made interrupt request"] -pub type CARD_R = crate::BitReader; +pub type CARD_R = crate::BitReader; #[doc = "Field `CARD` writer - Card made interrupt request"] -pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CARD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RETUNE` reader - Clock retune request"] -pub type RETUNE_R = crate::BitReader; +pub type RETUNE_R = crate::BitReader; #[doc = "Field `RETUNE` writer - Clock retune request"] -pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type RETUNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] -pub type BOOTACK_R = crate::BitReader; +pub type BOOTACK_R = crate::BitReader; #[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] -pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type BOOTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] -pub type ENDBOOT_R = crate::BitReader; +pub type ENDBOOT_R = crate::BitReader; #[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] -pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type ENDBOOT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTO_ERR` reader - Command timeout"] -pub type CTO_ERR_R = crate::BitReader; +pub type CTO_ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` writer - Command timeout"] -pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CCRC_ERR` reader - Command CRC error"] -pub type CCRC_ERR_R = crate::BitReader; +pub type CCRC_ERR_R = crate::BitReader; #[doc = "Field `CCRC_ERR` writer - Command CRC error"] -pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] -pub type CEND_ERR_R = crate::BitReader; +pub type CEND_ERR_R = crate::BitReader; #[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] -pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] -pub type CBAD_ERR_R = crate::BitReader; +pub type CBAD_ERR_R = crate::BitReader; #[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] -pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CBAD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTO_ERR` reader - Data timeout"] -pub type DTO_ERR_R = crate::BitReader; +pub type DTO_ERR_R = crate::BitReader; #[doc = "Field `DTO_ERR` writer - Data timeout"] -pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type DTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRC_ERR` reader - Data CRC error"] -pub type DCRC_ERR_R = crate::BitReader; +pub type DCRC_ERR_R = crate::BitReader; #[doc = "Field `DCRC_ERR` writer - Data CRC error"] -pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type DCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] -pub type DEND_ERR_R = crate::BitReader; +pub type DEND_ERR_R = crate::BitReader; #[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] -pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type DEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMD_ERR` reader - Auto command error"] -pub type ACMD_ERR_R = crate::BitReader; +pub type ACMD_ERR_R = crate::BitReader; #[doc = "Field `ACMD_ERR` writer - Auto command error"] -pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type ACMD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Command has finished"] #[inline(always)] @@ -189,128 +157,157 @@ impl R { ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IRPT_EN") + .field("acmd_err", &format_args!("{}", self.acmd_err().bit())) + .field("dend_err", &format_args!("{}", self.dend_err().bit())) + .field("dcrc_err", &format_args!("{}", self.dcrc_err().bit())) + .field("dto_err", &format_args!("{}", self.dto_err().bit())) + .field("cbad_err", &format_args!("{}", self.cbad_err().bit())) + .field("cend_err", &format_args!("{}", self.cend_err().bit())) + .field("ccrc_err", &format_args!("{}", self.ccrc_err().bit())) + .field("cto_err", &format_args!("{}", self.cto_err().bit())) + .field("endboot", &format_args!("{}", self.endboot().bit())) + .field("bootack", &format_args!("{}", self.bootack().bit())) + .field("retune", &format_args!("{}", self.retune().bit())) + .field("card", &format_args!("{}", self.card().bit())) + .field("read_rdy", &format_args!("{}", self.read_rdy().bit())) + .field("write_rdy", &format_args!("{}", self.write_rdy().bit())) + .field("block_gap", &format_args!("{}", self.block_gap().bit())) + .field("data_done", &format_args!("{}", self.data_done().bit())) + .field("cmd_done", &format_args!("{}", self.cmd_done().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command has finished"] #[inline(always)] #[must_use] - pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + pub fn cmd_done(&mut self) -> CMD_DONE_W { CMD_DONE_W::new(self) } #[doc = "Bit 1 - Data transfer has finished"] #[inline(always)] #[must_use] - pub fn data_done(&mut self) -> DATA_DONE_W<1> { + pub fn data_done(&mut self) -> DATA_DONE_W { DATA_DONE_W::new(self) } #[doc = "Bit 2 - Data transfer has stopped at block gap"] #[inline(always)] #[must_use] - pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + pub fn block_gap(&mut self) -> BLOCK_GAP_W { BLOCK_GAP_W::new(self) } #[doc = "Bit 4 - DATA can be written to"] #[inline(always)] #[must_use] - pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + pub fn write_rdy(&mut self) -> WRITE_RDY_W { WRITE_RDY_W::new(self) } #[doc = "Bit 5 - DATA contains data to be read"] #[inline(always)] #[must_use] - pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + pub fn read_rdy(&mut self) -> READ_RDY_W { READ_RDY_W::new(self) } #[doc = "Bit 8 - Card made interrupt request"] #[inline(always)] #[must_use] - pub fn card(&mut self) -> CARD_W<8> { + pub fn card(&mut self) -> CARD_W { CARD_W::new(self) } #[doc = "Bit 12 - Clock retune request"] #[inline(always)] #[must_use] - pub fn retune(&mut self) -> RETUNE_W<12> { + pub fn retune(&mut self) -> RETUNE_W { RETUNE_W::new(self) } #[doc = "Bit 13 - Boot has been acknowledged"] #[inline(always)] #[must_use] - pub fn bootack(&mut self) -> BOOTACK_W<13> { + pub fn bootack(&mut self) -> BOOTACK_W { BOOTACK_W::new(self) } #[doc = "Bit 14 - Boot operation has terminated"] #[inline(always)] #[must_use] - pub fn endboot(&mut self) -> ENDBOOT_W<14> { + pub fn endboot(&mut self) -> ENDBOOT_W { ENDBOOT_W::new(self) } #[doc = "Bit 16 - Command timeout"] #[inline(always)] #[must_use] - pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + pub fn cto_err(&mut self) -> CTO_ERR_W { CTO_ERR_W::new(self) } #[doc = "Bit 17 - Command CRC error"] #[inline(always)] #[must_use] - pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + pub fn ccrc_err(&mut self) -> CCRC_ERR_W { CCRC_ERR_W::new(self) } #[doc = "Bit 18 - Command end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + pub fn cend_err(&mut self) -> CEND_ERR_W { CEND_ERR_W::new(self) } #[doc = "Bit 19 - Incorrect response command index"] #[inline(always)] #[must_use] - pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + pub fn cbad_err(&mut self) -> CBAD_ERR_W { CBAD_ERR_W::new(self) } #[doc = "Bit 20 - Data timeout"] #[inline(always)] #[must_use] - pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + pub fn dto_err(&mut self) -> DTO_ERR_W { DTO_ERR_W::new(self) } #[doc = "Bit 21 - Data CRC error"] #[inline(always)] #[must_use] - pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + pub fn dcrc_err(&mut self) -> DCRC_ERR_W { DCRC_ERR_W::new(self) } #[doc = "Bit 22 - Data end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + pub fn dend_err(&mut self) -> DEND_ERR_W { DEND_ERR_W::new(self) } #[doc = "Bit 24 - Auto command error"] #[inline(always)] #[must_use] - pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + pub fn acmd_err(&mut self) -> ACMD_ERR_W { ACMD_ERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable interrupt to core\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irpt_en](index.html) module"] +#[doc = "Enable interrupt to core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irpt_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irpt_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRPT_EN_SPEC; impl crate::RegisterSpec for IRPT_EN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irpt_en::R](R) reader structure"] -impl crate::Readable for IRPT_EN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irpt_en::W](W) writer structure"] +#[doc = "`read()` method returns [`irpt_en::R`](R) reader structure"] +impl crate::Readable for IRPT_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irpt_en::W`](W) writer structure"] impl crate::Writable for IRPT_EN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/irpt_mask.rs b/crates/bcm2711-lpa/src/emmc/irpt_mask.rs index 87a9fdd..e8dc746 100644 --- a/crates/bcm2711-lpa/src/emmc/irpt_mask.rs +++ b/crates/bcm2711-lpa/src/emmc/irpt_mask.rs @@ -1,107 +1,75 @@ #[doc = "Register `IRPT_MASK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRPT_MASK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_DONE` reader - Command has finished"] -pub type CMD_DONE_R = crate::BitReader; +pub type CMD_DONE_R = crate::BitReader; #[doc = "Field `CMD_DONE` writer - Command has finished"] -pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CMD_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_DONE` reader - Data transfer has finished"] -pub type DATA_DONE_R = crate::BitReader; +pub type DATA_DONE_R = crate::BitReader; #[doc = "Field `DATA_DONE` writer - Data transfer has finished"] -pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type DATA_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_R = crate::BitReader; +pub type BLOCK_GAP_R = crate::BitReader; #[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type BLOCK_GAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_RDY` reader - DATA can be written to"] -pub type WRITE_RDY_R = crate::BitReader; +pub type WRITE_RDY_R = crate::BitReader; #[doc = "Field `WRITE_RDY` writer - DATA can be written to"] -pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type WRITE_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_RDY` reader - DATA contains data to be read"] -pub type READ_RDY_R = crate::BitReader; +pub type READ_RDY_R = crate::BitReader; #[doc = "Field `READ_RDY` writer - DATA contains data to be read"] -pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type READ_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CARD` reader - Card made interrupt request"] -pub type CARD_R = crate::BitReader; +pub type CARD_R = crate::BitReader; #[doc = "Field `CARD` writer - Card made interrupt request"] -pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CARD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RETUNE` reader - Clock retune request"] -pub type RETUNE_R = crate::BitReader; +pub type RETUNE_R = crate::BitReader; #[doc = "Field `RETUNE` writer - Clock retune request"] -pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type RETUNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] -pub type BOOTACK_R = crate::BitReader; +pub type BOOTACK_R = crate::BitReader; #[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] -pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type BOOTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] -pub type ENDBOOT_R = crate::BitReader; +pub type ENDBOOT_R = crate::BitReader; #[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] -pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type ENDBOOT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTO_ERR` reader - Command timeout"] -pub type CTO_ERR_R = crate::BitReader; +pub type CTO_ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` writer - Command timeout"] -pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CCRC_ERR` reader - Command CRC error"] -pub type CCRC_ERR_R = crate::BitReader; +pub type CCRC_ERR_R = crate::BitReader; #[doc = "Field `CCRC_ERR` writer - Command CRC error"] -pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] -pub type CEND_ERR_R = crate::BitReader; +pub type CEND_ERR_R = crate::BitReader; #[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] -pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] -pub type CBAD_ERR_R = crate::BitReader; +pub type CBAD_ERR_R = crate::BitReader; #[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] -pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CBAD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTO_ERR` reader - Data timeout"] -pub type DTO_ERR_R = crate::BitReader; +pub type DTO_ERR_R = crate::BitReader; #[doc = "Field `DTO_ERR` writer - Data timeout"] -pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type DTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRC_ERR` reader - Data CRC error"] -pub type DCRC_ERR_R = crate::BitReader; +pub type DCRC_ERR_R = crate::BitReader; #[doc = "Field `DCRC_ERR` writer - Data CRC error"] -pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type DCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] -pub type DEND_ERR_R = crate::BitReader; +pub type DEND_ERR_R = crate::BitReader; #[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] -pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type DEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMD_ERR` reader - Auto command error"] -pub type ACMD_ERR_R = crate::BitReader; +pub type ACMD_ERR_R = crate::BitReader; #[doc = "Field `ACMD_ERR` writer - Auto command error"] -pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type ACMD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Command has finished"] #[inline(always)] @@ -189,128 +157,157 @@ impl R { ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IRPT_MASK") + .field("acmd_err", &format_args!("{}", self.acmd_err().bit())) + .field("dend_err", &format_args!("{}", self.dend_err().bit())) + .field("dcrc_err", &format_args!("{}", self.dcrc_err().bit())) + .field("dto_err", &format_args!("{}", self.dto_err().bit())) + .field("cbad_err", &format_args!("{}", self.cbad_err().bit())) + .field("cend_err", &format_args!("{}", self.cend_err().bit())) + .field("ccrc_err", &format_args!("{}", self.ccrc_err().bit())) + .field("cto_err", &format_args!("{}", self.cto_err().bit())) + .field("endboot", &format_args!("{}", self.endboot().bit())) + .field("bootack", &format_args!("{}", self.bootack().bit())) + .field("retune", &format_args!("{}", self.retune().bit())) + .field("card", &format_args!("{}", self.card().bit())) + .field("read_rdy", &format_args!("{}", self.read_rdy().bit())) + .field("write_rdy", &format_args!("{}", self.write_rdy().bit())) + .field("block_gap", &format_args!("{}", self.block_gap().bit())) + .field("data_done", &format_args!("{}", self.data_done().bit())) + .field("cmd_done", &format_args!("{}", self.cmd_done().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command has finished"] #[inline(always)] #[must_use] - pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + pub fn cmd_done(&mut self) -> CMD_DONE_W { CMD_DONE_W::new(self) } #[doc = "Bit 1 - Data transfer has finished"] #[inline(always)] #[must_use] - pub fn data_done(&mut self) -> DATA_DONE_W<1> { + pub fn data_done(&mut self) -> DATA_DONE_W { DATA_DONE_W::new(self) } #[doc = "Bit 2 - Data transfer has stopped at block gap"] #[inline(always)] #[must_use] - pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + pub fn block_gap(&mut self) -> BLOCK_GAP_W { BLOCK_GAP_W::new(self) } #[doc = "Bit 4 - DATA can be written to"] #[inline(always)] #[must_use] - pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + pub fn write_rdy(&mut self) -> WRITE_RDY_W { WRITE_RDY_W::new(self) } #[doc = "Bit 5 - DATA contains data to be read"] #[inline(always)] #[must_use] - pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + pub fn read_rdy(&mut self) -> READ_RDY_W { READ_RDY_W::new(self) } #[doc = "Bit 8 - Card made interrupt request"] #[inline(always)] #[must_use] - pub fn card(&mut self) -> CARD_W<8> { + pub fn card(&mut self) -> CARD_W { CARD_W::new(self) } #[doc = "Bit 12 - Clock retune request"] #[inline(always)] #[must_use] - pub fn retune(&mut self) -> RETUNE_W<12> { + pub fn retune(&mut self) -> RETUNE_W { RETUNE_W::new(self) } #[doc = "Bit 13 - Boot has been acknowledged"] #[inline(always)] #[must_use] - pub fn bootack(&mut self) -> BOOTACK_W<13> { + pub fn bootack(&mut self) -> BOOTACK_W { BOOTACK_W::new(self) } #[doc = "Bit 14 - Boot operation has terminated"] #[inline(always)] #[must_use] - pub fn endboot(&mut self) -> ENDBOOT_W<14> { + pub fn endboot(&mut self) -> ENDBOOT_W { ENDBOOT_W::new(self) } #[doc = "Bit 16 - Command timeout"] #[inline(always)] #[must_use] - pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + pub fn cto_err(&mut self) -> CTO_ERR_W { CTO_ERR_W::new(self) } #[doc = "Bit 17 - Command CRC error"] #[inline(always)] #[must_use] - pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + pub fn ccrc_err(&mut self) -> CCRC_ERR_W { CCRC_ERR_W::new(self) } #[doc = "Bit 18 - Command end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + pub fn cend_err(&mut self) -> CEND_ERR_W { CEND_ERR_W::new(self) } #[doc = "Bit 19 - Incorrect response command index"] #[inline(always)] #[must_use] - pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + pub fn cbad_err(&mut self) -> CBAD_ERR_W { CBAD_ERR_W::new(self) } #[doc = "Bit 20 - Data timeout"] #[inline(always)] #[must_use] - pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + pub fn dto_err(&mut self) -> DTO_ERR_W { DTO_ERR_W::new(self) } #[doc = "Bit 21 - Data CRC error"] #[inline(always)] #[must_use] - pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + pub fn dcrc_err(&mut self) -> DCRC_ERR_W { DCRC_ERR_W::new(self) } #[doc = "Bit 22 - Data end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + pub fn dend_err(&mut self) -> DEND_ERR_W { DEND_ERR_W::new(self) } #[doc = "Bit 24 - Auto command error"] #[inline(always)] #[must_use] - pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + pub fn acmd_err(&mut self) -> ACMD_ERR_W { ACMD_ERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mask interrupts that change in INTERRUPT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irpt_mask](index.html) module"] +#[doc = "Mask interrupts that change in INTERRUPT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irpt_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irpt_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRPT_MASK_SPEC; impl crate::RegisterSpec for IRPT_MASK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irpt_mask::R](R) reader structure"] -impl crate::Readable for IRPT_MASK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irpt_mask::W](W) writer structure"] +#[doc = "`read()` method returns [`irpt_mask::R`](R) reader structure"] +impl crate::Readable for IRPT_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irpt_mask::W`](W) writer structure"] impl crate::Writable for IRPT_MASK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/resp0.rs b/crates/bcm2711-lpa/src/emmc/resp0.rs index 1022d1a..79ea5ca 100644 --- a/crates/bcm2711-lpa/src/emmc/resp0.rs +++ b/crates/bcm2711-lpa/src/emmc/resp0.rs @@ -1,59 +1,38 @@ #[doc = "Register `RESP0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RESP0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status bits of the response\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp0](index.html) module"] +#[doc = "Status bits of the response\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESP0_SPEC; impl crate::RegisterSpec for RESP0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [resp0::R](R) reader structure"] -impl crate::Readable for RESP0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [resp0::W](W) writer structure"] +#[doc = "`read()` method returns [`resp0::R`](R) reader structure"] +impl crate::Readable for RESP0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resp0::W`](W) writer structure"] impl crate::Writable for RESP0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/resp1.rs b/crates/bcm2711-lpa/src/emmc/resp1.rs index d1e9b42..12a2f9a 100644 --- a/crates/bcm2711-lpa/src/emmc/resp1.rs +++ b/crates/bcm2711-lpa/src/emmc/resp1.rs @@ -1,59 +1,38 @@ #[doc = "Register `RESP1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RESP1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Bits 63:32 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp1](index.html) module"] +#[doc = "Bits 63:32 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESP1_SPEC; impl crate::RegisterSpec for RESP1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [resp1::R](R) reader structure"] -impl crate::Readable for RESP1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [resp1::W](W) writer structure"] +#[doc = "`read()` method returns [`resp1::R`](R) reader structure"] +impl crate::Readable for RESP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resp1::W`](W) writer structure"] impl crate::Writable for RESP1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/resp2.rs b/crates/bcm2711-lpa/src/emmc/resp2.rs index 418942a..5a51d34 100644 --- a/crates/bcm2711-lpa/src/emmc/resp2.rs +++ b/crates/bcm2711-lpa/src/emmc/resp2.rs @@ -1,59 +1,38 @@ #[doc = "Register `RESP2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RESP2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Bits 95:64 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp2](index.html) module"] +#[doc = "Bits 95:64 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESP2_SPEC; impl crate::RegisterSpec for RESP2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [resp2::R](R) reader structure"] -impl crate::Readable for RESP2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [resp2::W](W) writer structure"] +#[doc = "`read()` method returns [`resp2::R`](R) reader structure"] +impl crate::Readable for RESP2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resp2::W`](W) writer structure"] impl crate::Writable for RESP2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/resp3.rs b/crates/bcm2711-lpa/src/emmc/resp3.rs index 36b2c80..65ef18f 100644 --- a/crates/bcm2711-lpa/src/emmc/resp3.rs +++ b/crates/bcm2711-lpa/src/emmc/resp3.rs @@ -1,59 +1,38 @@ #[doc = "Register `RESP3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RESP3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Bits 127:96 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp3](index.html) module"] +#[doc = "Bits 127:96 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESP3_SPEC; impl crate::RegisterSpec for RESP3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [resp3::R](R) reader structure"] -impl crate::Readable for RESP3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [resp3::W](W) writer structure"] +#[doc = "`read()` method returns [`resp3::R`](R) reader structure"] +impl crate::Readable for RESP3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resp3::W`](W) writer structure"] impl crate::Writable for RESP3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/slotisr_ver.rs b/crates/bcm2711-lpa/src/emmc/slotisr_ver.rs index 6016436..0db90df 100644 --- a/crates/bcm2711-lpa/src/emmc/slotisr_ver.rs +++ b/crates/bcm2711-lpa/src/emmc/slotisr_ver.rs @@ -1,52 +1,19 @@ #[doc = "Register `SLOTISR_VER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SLOTISR_VER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLOT_STATUS` reader - OR of interrupt and wakeup signals for each slot"] -pub type SLOT_STATUS_R = crate::FieldReader; +pub type SLOT_STATUS_R = crate::FieldReader; #[doc = "Field `SLOT_STATUS` writer - OR of interrupt and wakeup signals for each slot"] -pub type SLOT_STATUS_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +pub type SLOT_STATUS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SDVERSION` reader - Host controller specification version"] -pub type SDVERSION_R = crate::FieldReader; +pub type SDVERSION_R = crate::FieldReader; #[doc = "Field `SDVERSION` writer - Host controller specification version"] -pub type SDVERSION_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +pub type SDVERSION_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `VENDOR` reader - Vendor version number"] -pub type VENDOR_R = crate::FieldReader; +pub type VENDOR_R = crate::FieldReader; #[doc = "Field `VENDOR` writer - Vendor version number"] -pub type VENDOR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +pub type VENDOR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - OR of interrupt and wakeup signals for each slot"] #[inline(always)] @@ -64,44 +31,62 @@ impl R { VENDOR_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLOTISR_VER") + .field("vendor", &format_args!("{}", self.vendor().bits())) + .field("sdversion", &format_args!("{}", self.sdversion().bits())) + .field( + "slot_status", + &format_args!("{}", self.slot_status().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - OR of interrupt and wakeup signals for each slot"] #[inline(always)] #[must_use] - pub fn slot_status(&mut self) -> SLOT_STATUS_W<0> { + pub fn slot_status(&mut self) -> SLOT_STATUS_W { SLOT_STATUS_W::new(self) } #[doc = "Bits 16:23 - Host controller specification version"] #[inline(always)] #[must_use] - pub fn sdversion(&mut self) -> SDVERSION_W<16> { + pub fn sdversion(&mut self) -> SDVERSION_W { SDVERSION_W::new(self) } #[doc = "Bits 24:31 - Vendor version number"] #[inline(always)] #[must_use] - pub fn vendor(&mut self) -> VENDOR_W<24> { + pub fn vendor(&mut self) -> VENDOR_W { VENDOR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Version information and slot interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slotisr_ver](index.html) module"] +#[doc = "Version information and slot interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slotisr_ver::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slotisr_ver::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLOTISR_VER_SPEC; impl crate::RegisterSpec for SLOTISR_VER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [slotisr_ver::R](R) reader structure"] -impl crate::Readable for SLOTISR_VER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [slotisr_ver::W](W) writer structure"] +#[doc = "`read()` method returns [`slotisr_ver::R`](R) reader structure"] +impl crate::Readable for SLOTISR_VER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slotisr_ver::W`](W) writer structure"] impl crate::Writable for SLOTISR_VER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/spi_int_spt.rs b/crates/bcm2711-lpa/src/emmc/spi_int_spt.rs index bce7edc..ba304fe 100644 --- a/crates/bcm2711-lpa/src/emmc/spi_int_spt.rs +++ b/crates/bcm2711-lpa/src/emmc/spi_int_spt.rs @@ -1,43 +1,11 @@ #[doc = "Register `SPI_INT_SPT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SPI_INT_SPT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SELECT` reader - "] -pub type SELECT_R = crate::FieldReader; +pub type SELECT_R = crate::FieldReader; #[doc = "Field `SELECT` writer - "] -pub type SELECT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SPI_INT_SPT_SPEC, u8, u8, 8, O>; +pub type SELECT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { SELECT_R::new((self.bits & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_INT_SPT") + .field("select", &format_args!("{}", self.select().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7"] #[inline(always)] #[must_use] - pub fn select(&mut self) -> SELECT_W<0> { + pub fn select(&mut self) -> SELECT_W { SELECT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupts in SPI mode depend on CS\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_int_spt](index.html) module"] +#[doc = "Interrupts in SPI mode depend on CS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_int_spt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_int_spt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SPI_INT_SPT_SPEC; impl crate::RegisterSpec for SPI_INT_SPT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [spi_int_spt::R](R) reader structure"] -impl crate::Readable for SPI_INT_SPT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [spi_int_spt::W](W) writer structure"] +#[doc = "`read()` method returns [`spi_int_spt::R`](R) reader structure"] +impl crate::Readable for SPI_INT_SPT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_int_spt::W`](W) writer structure"] impl crate::Writable for SPI_INT_SPT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/status.rs b/crates/bcm2711-lpa/src/emmc/status.rs index 0b86ab0..2b07e21 100644 --- a/crates/bcm2711-lpa/src/emmc/status.rs +++ b/crates/bcm2711-lpa/src/emmc/status.rs @@ -1,79 +1,47 @@ #[doc = "Register `STATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STATUS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_INHIBIT` reader - Command line still in use"] -pub type CMD_INHIBIT_R = crate::BitReader; +pub type CMD_INHIBIT_R = crate::BitReader; #[doc = "Field `CMD_INHIBIT` writer - Command line still in use"] -pub type CMD_INHIBIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type CMD_INHIBIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAT_INHIBIT` reader - Data lines still in use"] -pub type DAT_INHIBIT_R = crate::BitReader; +pub type DAT_INHIBIT_R = crate::BitReader; #[doc = "Field `DAT_INHIBIT` writer - Data lines still in use"] -pub type DAT_INHIBIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type DAT_INHIBIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAT_ACTIVE` reader - At least one data line is active"] -pub type DAT_ACTIVE_R = crate::BitReader; +pub type DAT_ACTIVE_R = crate::BitReader; #[doc = "Field `DAT_ACTIVE` writer - At least one data line is active"] -pub type DAT_ACTIVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type DAT_ACTIVE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_TRANSFER` reader - Write transfer is active"] -pub type WRITE_TRANSFER_R = crate::BitReader; +pub type WRITE_TRANSFER_R = crate::BitReader; #[doc = "Field `WRITE_TRANSFER` writer - Write transfer is active"] -pub type WRITE_TRANSFER_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type WRITE_TRANSFER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_TRANSFER` reader - Read transfer is active"] -pub type READ_TRANSFER_R = crate::BitReader; +pub type READ_TRANSFER_R = crate::BitReader; #[doc = "Field `READ_TRANSFER` writer - Read transfer is active"] -pub type READ_TRANSFER_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type READ_TRANSFER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUFFER_WRITE_ENABLE` reader - The buffer has space for new data"] -pub type BUFFER_WRITE_ENABLE_R = crate::BitReader; +pub type BUFFER_WRITE_ENABLE_R = crate::BitReader; #[doc = "Field `BUFFER_WRITE_ENABLE` writer - The buffer has space for new data"] -pub type BUFFER_WRITE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type BUFFER_WRITE_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUFFER_READ_ENABLE` reader - New data is available to read"] -pub type BUFFER_READ_ENABLE_R = crate::BitReader; +pub type BUFFER_READ_ENABLE_R = crate::BitReader; #[doc = "Field `BUFFER_READ_ENABLE` writer - New data is available to read"] -pub type BUFFER_READ_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type BUFFER_READ_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAT_LEVEL0` reader - Value of DAT\\[3:0\\]"] -pub type DAT_LEVEL0_R = crate::FieldReader; +pub type DAT_LEVEL0_R = crate::FieldReader; #[doc = "Field `DAT_LEVEL0` writer - Value of DAT\\[3:0\\]"] -pub type DAT_LEVEL0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STATUS_SPEC, u8, u8, 4, O>; +pub type DAT_LEVEL0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CMD_LEVEL` reader - Value of CMD"] -pub type CMD_LEVEL_R = crate::BitReader; +pub type CMD_LEVEL_R = crate::BitReader; #[doc = "Field `CMD_LEVEL` writer - Value of CMD"] -pub type CMD_LEVEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type CMD_LEVEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAT_LEVEL1` reader - Value of DAT\\[7:4\\]"] -pub type DAT_LEVEL1_R = crate::FieldReader; +pub type DAT_LEVEL1_R = crate::FieldReader; #[doc = "Field `DAT_LEVEL1` writer - Value of DAT\\[7:4\\]"] -pub type DAT_LEVEL1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STATUS_SPEC, u8, u8, 4, O>; +pub type DAT_LEVEL1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bit 0 - Command line still in use"] #[inline(always)] @@ -126,86 +94,120 @@ impl R { DAT_LEVEL1_R::new(((self.bits >> 25) & 0x0f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS") + .field("dat_level1", &format_args!("{}", self.dat_level1().bits())) + .field("cmd_level", &format_args!("{}", self.cmd_level().bit())) + .field("dat_level0", &format_args!("{}", self.dat_level0().bits())) + .field( + "buffer_read_enable", + &format_args!("{}", self.buffer_read_enable().bit()), + ) + .field( + "buffer_write_enable", + &format_args!("{}", self.buffer_write_enable().bit()), + ) + .field( + "read_transfer", + &format_args!("{}", self.read_transfer().bit()), + ) + .field( + "write_transfer", + &format_args!("{}", self.write_transfer().bit()), + ) + .field("dat_active", &format_args!("{}", self.dat_active().bit())) + .field("dat_inhibit", &format_args!("{}", self.dat_inhibit().bit())) + .field("cmd_inhibit", &format_args!("{}", self.cmd_inhibit().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command line still in use"] #[inline(always)] #[must_use] - pub fn cmd_inhibit(&mut self) -> CMD_INHIBIT_W<0> { + pub fn cmd_inhibit(&mut self) -> CMD_INHIBIT_W { CMD_INHIBIT_W::new(self) } #[doc = "Bit 1 - Data lines still in use"] #[inline(always)] #[must_use] - pub fn dat_inhibit(&mut self) -> DAT_INHIBIT_W<1> { + pub fn dat_inhibit(&mut self) -> DAT_INHIBIT_W { DAT_INHIBIT_W::new(self) } #[doc = "Bit 2 - At least one data line is active"] #[inline(always)] #[must_use] - pub fn dat_active(&mut self) -> DAT_ACTIVE_W<2> { + pub fn dat_active(&mut self) -> DAT_ACTIVE_W { DAT_ACTIVE_W::new(self) } #[doc = "Bit 8 - Write transfer is active"] #[inline(always)] #[must_use] - pub fn write_transfer(&mut self) -> WRITE_TRANSFER_W<8> { + pub fn write_transfer(&mut self) -> WRITE_TRANSFER_W { WRITE_TRANSFER_W::new(self) } #[doc = "Bit 9 - Read transfer is active"] #[inline(always)] #[must_use] - pub fn read_transfer(&mut self) -> READ_TRANSFER_W<9> { + pub fn read_transfer(&mut self) -> READ_TRANSFER_W { READ_TRANSFER_W::new(self) } #[doc = "Bit 10 - The buffer has space for new data"] #[inline(always)] #[must_use] - pub fn buffer_write_enable(&mut self) -> BUFFER_WRITE_ENABLE_W<10> { + pub fn buffer_write_enable(&mut self) -> BUFFER_WRITE_ENABLE_W { BUFFER_WRITE_ENABLE_W::new(self) } #[doc = "Bit 11 - New data is available to read"] #[inline(always)] #[must_use] - pub fn buffer_read_enable(&mut self) -> BUFFER_READ_ENABLE_W<11> { + pub fn buffer_read_enable(&mut self) -> BUFFER_READ_ENABLE_W { BUFFER_READ_ENABLE_W::new(self) } #[doc = "Bits 20:23 - Value of DAT\\[3:0\\]"] #[inline(always)] #[must_use] - pub fn dat_level0(&mut self) -> DAT_LEVEL0_W<20> { + pub fn dat_level0(&mut self) -> DAT_LEVEL0_W { DAT_LEVEL0_W::new(self) } #[doc = "Bit 24 - Value of CMD"] #[inline(always)] #[must_use] - pub fn cmd_level(&mut self) -> CMD_LEVEL_W<24> { + pub fn cmd_level(&mut self) -> CMD_LEVEL_W { CMD_LEVEL_W::new(self) } #[doc = "Bits 25:28 - Value of DAT\\[7:4\\]"] #[inline(always)] #[must_use] - pub fn dat_level1(&mut self) -> DAT_LEVEL1_W<25> { + pub fn dat_level1(&mut self) -> DAT_LEVEL1_W { DAT_LEVEL1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status info for debugging\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +#[doc = "Status info for debugging\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STATUS_SPEC; impl crate::RegisterSpec for STATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [status::R](R) reader structure"] -impl crate::Readable for STATUS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"] impl crate::Writable for STATUS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/tune_step.rs b/crates/bcm2711-lpa/src/emmc/tune_step.rs index 2f0169b..aa0dd84 100644 --- a/crates/bcm2711-lpa/src/emmc/tune_step.rs +++ b/crates/bcm2711-lpa/src/emmc/tune_step.rs @@ -1,43 +1,11 @@ #[doc = "Register `TUNE_STEP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TUNE_STEP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DELAY` reader - "] -pub type DELAY_R = crate::FieldReader; +pub type DELAY_R = crate::FieldReader; #[doc = "Field `DELAY` writer - "] -pub type DELAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEP_SPEC, u8, u8, 3, O>; +pub type DELAY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:2"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DELAY_R::new((self.bits & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TUNE_STEP") + .field("delay", &format_args!("{}", self.delay().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2"] #[inline(always)] #[must_use] - pub fn delay(&mut self) -> DELAY_W<0> { + pub fn delay(&mut self) -> DELAY_W { DELAY_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Sample clock delay step duration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_step](index.html) module"] +#[doc = "Sample clock delay step duration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_step::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_step::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TUNE_STEP_SPEC; impl crate::RegisterSpec for TUNE_STEP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tune_step::R](R) reader structure"] -impl crate::Readable for TUNE_STEP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tune_step::W](W) writer structure"] +#[doc = "`read()` method returns [`tune_step::R`](R) reader structure"] +impl crate::Readable for TUNE_STEP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tune_step::W`](W) writer structure"] impl crate::Writable for TUNE_STEP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/tune_steps_ddr.rs b/crates/bcm2711-lpa/src/emmc/tune_steps_ddr.rs index a8fea76..c4f1dd8 100644 --- a/crates/bcm2711-lpa/src/emmc/tune_steps_ddr.rs +++ b/crates/bcm2711-lpa/src/emmc/tune_steps_ddr.rs @@ -1,43 +1,11 @@ #[doc = "Register `TUNE_STEPS_DDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TUNE_STEPS_DDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `STEPS` reader - "] -pub type STEPS_R = crate::FieldReader; +pub type STEPS_R = crate::FieldReader; #[doc = "Field `STEPS` writer - "] -pub type STEPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEPS_DDR_SPEC, u8, u8, 6, O>; +pub type STEPS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { STEPS_R::new((self.bits & 0x3f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TUNE_STEPS_DDR") + .field("steps", &format_args!("{}", self.steps().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn steps(&mut self) -> STEPS_W<0> { + pub fn steps(&mut self) -> STEPS_W { STEPS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Sample clock delay step count for DDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_steps_ddr](index.html) module"] +#[doc = "Sample clock delay step count for DDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_steps_ddr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_steps_ddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TUNE_STEPS_DDR_SPEC; impl crate::RegisterSpec for TUNE_STEPS_DDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tune_steps_ddr::R](R) reader structure"] -impl crate::Readable for TUNE_STEPS_DDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tune_steps_ddr::W](W) writer structure"] +#[doc = "`read()` method returns [`tune_steps_ddr::R`](R) reader structure"] +impl crate::Readable for TUNE_STEPS_DDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tune_steps_ddr::W`](W) writer structure"] impl crate::Writable for TUNE_STEPS_DDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/emmc/tune_steps_std.rs b/crates/bcm2711-lpa/src/emmc/tune_steps_std.rs index c04740c..cf65897 100644 --- a/crates/bcm2711-lpa/src/emmc/tune_steps_std.rs +++ b/crates/bcm2711-lpa/src/emmc/tune_steps_std.rs @@ -1,43 +1,11 @@ #[doc = "Register `TUNE_STEPS_STD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TUNE_STEPS_STD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `STEPS` reader - "] -pub type STEPS_R = crate::FieldReader; +pub type STEPS_R = crate::FieldReader; #[doc = "Field `STEPS` writer - "] -pub type STEPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEPS_STD_SPEC, u8, u8, 6, O>; +pub type STEPS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { STEPS_R::new((self.bits & 0x3f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TUNE_STEPS_STD") + .field("steps", &format_args!("{}", self.steps().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn steps(&mut self) -> STEPS_W<0> { + pub fn steps(&mut self) -> STEPS_W { STEPS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Sample clock delay step count for SDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_steps_std](index.html) module"] +#[doc = "Sample clock delay step count for SDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_steps_std::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_steps_std::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TUNE_STEPS_STD_SPEC; impl crate::RegisterSpec for TUNE_STEPS_STD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tune_steps_std::R](R) reader structure"] -impl crate::Readable for TUNE_STEPS_STD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tune_steps_std::W](W) writer structure"] +#[doc = "`read()` method returns [`tune_steps_std::R`](R) reader structure"] +impl crate::Readable for TUNE_STEPS_STD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tune_steps_std::W`](W) writer structure"] impl crate::Writable for TUNE_STEPS_STD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/generic.rs b/crates/bcm2711-lpa/src/generic.rs index f10ca73..a34573a 100644 --- a/crates/bcm2711-lpa/src/generic.rs +++ b/crates/bcm2711-lpa/src/generic.rs @@ -31,6 +31,9 @@ macro_rules! raw_reg { const fn $mask() -> $U { <$U>::MAX >> ($size - WI) } + impl FieldSpec for $U { + type Ux = $U; + } }; } raw_reg!(u8, 8, mask_u8); @@ -42,21 +45,21 @@ pub trait RegisterSpec { #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] type Ux: RawReg; } +#[doc = " Raw field type"] +pub trait FieldSpec: Sized { + #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy + PartialEq + From; +} #[doc = " Trait implemented by readable registers to enable the `read` method."] #[doc = ""] #[doc = " Registers marked with `Writable` can be also be `modify`'ed."] -pub trait Readable: RegisterSpec { - #[doc = " Result from a call to `read` and argument to `modify`."] - type Reader: From> + core::ops::Deref>; -} +pub trait Readable: RegisterSpec {} #[doc = " Trait implemented by writeable registers."] #[doc = ""] #[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] #[doc = ""] #[doc = " Registers marked with `Readable` can be also be `modify`'ed."] pub trait Writable: RegisterSpec { - #[doc = " Writer type argument to `write`, et al."] - type Writer: From> + core::ops::DerefMut>; #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] @@ -107,11 +110,11 @@ impl Reg { #[doc = " let flag = reader.field2().bit_is_set();"] #[doc = " ```"] #[inline(always)] - pub fn read(&self) -> REG::Reader { - REG::Reader::from(R { + pub fn read(&self) -> R { + R { bits: self.register.get(), _reg: marker::PhantomData, - }) + } } } impl Reg { @@ -148,14 +151,14 @@ impl Reg { #[inline(always)] pub fn write(&self, f: F) where - F: FnOnce(&mut REG::Writer) -> &mut W, + F: FnOnce(&mut W) -> &mut W, { self.register.set( - f(&mut REG::Writer::from(W { + f(&mut W { bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, _reg: marker::PhantomData, - })) + }) .bits, ); } @@ -171,13 +174,13 @@ impl Reg { #[inline(always)] pub unsafe fn write_with_zero(&self, f: F) where - F: FnOnce(&mut REG::Writer) -> &mut W, + F: FnOnce(&mut W) -> &mut W, { self.register.set( - f(&mut REG::Writer::from(W { + f(&mut W { bits: REG::Ux::default(), _reg: marker::PhantomData, - })) + }) .bits, ); } @@ -211,37 +214,36 @@ impl Reg { #[inline(always)] pub fn modify(&self, f: F) where - for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); self.register.set( f( - ®::Reader::from(R { + &R { bits, _reg: marker::PhantomData, - }), - &mut REG::Writer::from(W { + }, + &mut W { bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, _reg: marker::PhantomData, - }), + }, ) .bits, ); } } +#[doc(hidden)] +pub mod raw; #[doc = " Register reader."] #[doc = ""] #[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] #[doc = " method."] -pub struct R { - pub(crate) bits: REG::Ux, - _reg: marker::PhantomData, -} +pub type R = raw::R; impl R { #[doc = " Reads raw bits from register."] #[inline(always)] - pub fn bits(&self) -> REG::Ux { + pub const fn bits(&self) -> REG::Ux { self.bits } } @@ -259,83 +261,27 @@ where #[doc = " Register writer."] #[doc = ""] #[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] -pub struct W { - #[doc = "Writable bits"] - pub(crate) bits: REG::Ux, - _reg: marker::PhantomData, -} -impl W { - #[doc = " Writes raw bits to the register."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Read datasheet or reference manual to find what values are allowed to pass."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { - self.bits = bits; - self - } -} -#[doc(hidden)] -pub struct FieldReaderRaw { - pub(crate) bits: U, - _reg: marker::PhantomData, -} -impl FieldReaderRaw -where - U: Copy, -{ - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(bits: U) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} -#[doc(hidden)] -pub struct BitReaderRaw { - pub(crate) bits: bool, - _reg: marker::PhantomData, -} -impl BitReaderRaw { - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(bits: bool) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} +pub type W = raw::W; #[doc = " Field reader."] #[doc = ""] #[doc = " Result of the `read` methods of fields."] -pub type FieldReader = FieldReaderRaw; +pub type FieldReader = raw::FieldReader; #[doc = " Bit-wise field reader"] -pub type BitReader = BitReaderRaw; -impl FieldReader -where - U: Copy, -{ +pub type BitReader = raw::BitReader; +impl FieldReader { #[doc = " Reads raw bits from field."] #[inline(always)] - pub fn bits(&self) -> U { + pub const fn bits(&self) -> FI::Ux { self.bits } } -impl PartialEq for FieldReader +impl PartialEq for FieldReader where - U: PartialEq, - FI: Copy, - U: From, + FI: FieldSpec + Copy, { #[inline(always)] fn eq(&self, other: &FI) -> bool { - self.bits.eq(&U::from(*other)) + self.bits.eq(&FI::Ux::from(*other)) } } impl PartialEq for BitReader @@ -351,17 +297,17 @@ where impl BitReader { #[doc = " Value of the field as raw bits."] #[inline(always)] - pub fn bit(&self) -> bool { + pub const fn bit(&self) -> bool { self.bits } #[doc = " Returns `true` if the bit is clear (0)."] #[inline(always)] - pub fn bit_is_clear(&self) -> bool { + pub const fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = " Returns `true` if the bit is set (1)."] #[inline(always)] - pub fn bit_is_set(&self) -> bool { + pub const fn bit_is_set(&self) -> bool { self.bit() } } @@ -369,111 +315,81 @@ impl BitReader { pub struct Safe; #[doc(hidden)] pub struct Unsafe; -#[doc(hidden)] -pub struct FieldWriterRaw<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> -where - REG: Writable + RegisterSpec, - N: From, -{ - pub(crate) w: &'a mut REG::Writer, - _field: marker::PhantomData<(N, FI, Safety)>, -} -impl<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> - FieldWriterRaw<'a, U, REG, N, FI, Safety, WI, O> -where - REG: Writable + RegisterSpec, - N: From, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut REG::Writer) -> Self { - Self { - w, - _field: marker::PhantomData, - } - } -} -#[doc(hidden)] -pub struct BitWriterRaw<'a, U, REG, FI, M, const O: u8> -where - REG: Writable + RegisterSpec, - bool: From, -{ - pub(crate) w: &'a mut REG::Writer, - _field: marker::PhantomData<(FI, M)>, -} -impl<'a, U, REG, FI, M, const O: u8> BitWriterRaw<'a, U, REG, FI, M, O> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut REG::Writer) -> Self { - Self { - w, - _field: marker::PhantomData, - } - } -} #[doc = " Write field Proxy with unsafe `bits`"] -pub type FieldWriter<'a, U, REG, N, FI, const WI: u8, const O: u8> = - FieldWriterRaw<'a, U, REG, N, FI, Unsafe, WI, O>; +pub type FieldWriter<'a, REG, const WI: u8, const O: u8, FI = u8> = + raw::FieldWriter<'a, REG, WI, O, FI, Unsafe>; #[doc = " Write field Proxy with safe `bits`"] -pub type FieldWriterSafe<'a, U, REG, N, FI, const WI: u8, const O: u8> = - FieldWriterRaw<'a, U, REG, N, FI, Safe, WI, O>; -impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> +pub type FieldWriterSafe<'a, REG, const WI: u8, const O: u8, FI = u8> = + raw::FieldWriter<'a, REG, WI, O, FI, Safe>; +impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI> where - REG: Writable + RegisterSpec, - N: From, + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, { #[doc = " Field width"] pub const WIDTH: u8 = WI; + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << OF); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } } -impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> +impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI> where - REG: Writable + RegisterSpec, - N: From, + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, { #[doc = " Field width"] pub const WIDTH: u8 = WI; + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << OF); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bits(FI::Ux::from(variant)) + } } macro_rules! bit_proxy { ($ writer : ident , $ mwv : ident) => { #[doc(hidden)] pub struct $mwv; #[doc = " Bit-wise write field proxy"] - pub type $writer<'a, U, REG, FI, const O: u8> = BitWriterRaw<'a, U, REG, FI, $mwv, O>; - impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> + pub type $writer<'a, REG, const O: u8, FI = bool> = raw::BitWriter<'a, REG, O, FI, $mwv>; + impl<'a, REG, const OF: u8, FI> $writer<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, + REG: Writable + RegisterSpec, bool: From, { #[doc = " Field width"] pub const WIDTH: u8 = 1; - } - }; -} -macro_rules! impl_bit_proxy { - ($ writer : ident) => { - impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> - where - REG: Writable + RegisterSpec, - U: RawReg, - bool: From, - { #[doc = " Writes bit to the field"] #[inline(always)] - pub fn bit(self, value: bool) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); - self.w.bits |= (U::from(value) & U::one()) << OF; + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << OF; self.w } #[doc = " Writes `variant` to the field"] #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + pub fn variant(self, variant: FI) -> &'a mut W { self.bit(bool::from(variant)) } } @@ -486,210 +402,94 @@ bit_proxy!(BitWriter1C, Bit1C); bit_proxy!(BitWriter0S, Bit0S); bit_proxy!(BitWriter1T, Bit1T); bit_proxy!(BitWriter0T, Bit0T); -impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> -where - REG: Writable + RegisterSpec, - U: RawReg + From, - N: From, -{ - #[doc = " Writes raw bits to the field"] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(self, value: N) -> &'a mut REG::Writer { - self.w.bits &= !(U::mask::() << OF); - self.w.bits |= (U::from(value) & U::mask::()) << OF; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { - unsafe { self.bits(N::from(variant)) } - } -} -impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> -where - REG: Writable + RegisterSpec, - U: RawReg + From, - N: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn bits(self, value: N) -> &'a mut REG::Writer { - self.w.bits &= !(U::mask::() << OF); - self.w.bits |= (U::from(value) & U::mask::()) << OF; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { - self.bits(N::from(variant)) - } -} -impl_bit_proxy!(BitWriter); -impl_bit_proxy!(BitWriter1S); -impl_bit_proxy!(BitWriter0C); -impl_bit_proxy!(BitWriter1C); -impl_bit_proxy!(BitWriter0S); -impl_bit_proxy!(BitWriter1T); -impl_bit_proxy!(BitWriter0T); -impl<'a, U, REG, FI, const OF: u8> BitWriter<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = " Sets the field bit"] #[inline(always)] - pub fn set_bit(self) -> &'a mut REG::Writer { - self.w.bits |= U::one() << OF; + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << OF; self.w } #[doc = " Clears the field bit"] #[inline(always)] - pub fn clear_bit(self) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter1S<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter1S<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = " Sets the field bit"] #[inline(always)] - pub fn set_bit(self) -> &'a mut REG::Writer { - self.w.bits |= U::one() << OF; + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << OF; self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter0C<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter0C<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = " Clears the field bit"] #[inline(always)] - pub fn clear_bit(self) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter1C<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter1C<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = "Clears the field bit by passing one"] #[inline(always)] - pub fn clear_bit_by_one(self) -> &'a mut REG::Writer { - self.w.bits |= U::one() << OF; + pub fn clear_bit_by_one(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << OF; self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter0S<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter0S<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = "Sets the field bit by passing zero"] #[inline(always)] - pub fn set_bit_by_zero(self) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); + pub fn set_bit_by_zero(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter1T<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter1T<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = "Toggle the field bit by passing one"] #[inline(always)] - pub fn toggle_bit(self) -> &'a mut REG::Writer { - self.w.bits |= U::one() << OF; + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << OF; self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter0T<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter0T<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = "Toggle the field bit by passing zero"] #[inline(always)] - pub fn toggle_bit(self) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); self.w } } mod atomic; -use atomic::AtomicOperations; -impl Reg -where - REG::Ux: AtomicOperations + Default + core::ops::Not, -{ - #[doc = " Set high every bit in the register that was set in the write proxy. Leave other bits"] - #[doc = " untouched. The write is done in a single atomic instruction."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " The resultant bit pattern may not be valid for the register."] - #[inline(always)] - pub unsafe fn set_bits(&self, f: F) - where - F: FnOnce(&mut REG::Writer) -> &mut W, - { - let bits = f(&mut REG::Writer::from(W { - bits: Default::default(), - _reg: marker::PhantomData, - })) - .bits; - REG::Ux::atomic_or(self.register.as_ptr(), bits); - } - #[doc = " Clear every bit in the register that was cleared in the write proxy. Leave other bits"] - #[doc = " untouched. The write is done in a single atomic instruction."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " The resultant bit pattern may not be valid for the register."] - #[inline(always)] - pub unsafe fn clear_bits(&self, f: F) - where - F: FnOnce(&mut REG::Writer) -> &mut W, - { - let bits = f(&mut REG::Writer::from(W { - bits: !REG::Ux::default(), - _reg: marker::PhantomData, - })) - .bits; - REG::Ux::atomic_and(self.register.as_ptr(), bits); - } - #[doc = " Toggle every bit in the register that was set in the write proxy. Leave other bits"] - #[doc = " untouched. The write is done in a single atomic instruction."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " The resultant bit pattern may not be valid for the register."] - #[inline(always)] - pub unsafe fn toggle_bits(&self, f: F) - where - F: FnOnce(&mut REG::Writer) -> &mut W, - { - let bits = f(&mut REG::Writer::from(W { - bits: Default::default(), - _reg: marker::PhantomData, - })) - .bits; - REG::Ux::atomic_xor(self.register.as_ptr(), bits); - } -} diff --git a/crates/bcm2711-lpa/src/generic/atomic.rs b/crates/bcm2711-lpa/src/generic/atomic.rs index acee997..89d6c54 100644 --- a/crates/bcm2711-lpa/src/generic/atomic.rs +++ b/crates/bcm2711-lpa/src/generic/atomic.rs @@ -1,3 +1,4 @@ +use super::*; use portable_atomic::Ordering; pub trait AtomicOperations { unsafe fn atomic_or(ptr: *mut Self, val: Self); @@ -25,3 +26,62 @@ impl_atomics!(u16, portable_atomic::AtomicU16); impl_atomics!(u32, portable_atomic::AtomicU32); #[cfg(any(target_pointer_width = "64", target_has_atomic = "64"))] impl_atomics!(u64, portable_atomic::AtomicU64); +impl Reg +where + REG::Ux: AtomicOperations + Default + core::ops::Not, +{ + #[doc = " Set high every bit in the register that was set in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn set_bits(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + let bits = f(&mut W { + bits: Default::default(), + _reg: marker::PhantomData, + }) + .bits; + REG::Ux::atomic_or(self.register.as_ptr(), bits); + } + #[doc = " Clear every bit in the register that was cleared in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn clear_bits(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + let bits = f(&mut W { + bits: !REG::Ux::default(), + _reg: marker::PhantomData, + }) + .bits; + REG::Ux::atomic_and(self.register.as_ptr(), bits); + } + #[doc = " Toggle every bit in the register that was set in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn toggle_bits(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + let bits = f(&mut W { + bits: Default::default(), + _reg: marker::PhantomData, + }) + .bits; + REG::Ux::atomic_xor(self.register.as_ptr(), bits); + } +} diff --git a/crates/bcm2711-lpa/src/generic/raw.rs b/crates/bcm2711-lpa/src/generic/raw.rs new file mode 100644 index 0000000..4ab1635 --- /dev/null +++ b/crates/bcm2711-lpa/src/generic/raw.rs @@ -0,0 +1,89 @@ +use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; +pub struct R { + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct FieldReader +where + FI: FieldSpec, +{ + pub(crate) bits: FI::Ux, + _reg: marker::PhantomData, +} +impl FieldReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: FI::Ux) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct BitReader { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct FieldWriter<'a, REG, const WI: u8, const O: u8, FI = u8, Safety = Unsafe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + pub(crate) w: &'a mut W, + _field: marker::PhantomData<(FI, Safety)>, +} +impl<'a, REG, const WI: u8, const O: u8, FI, Safety> FieldWriter<'a, REG, WI, O, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +pub struct BitWriter<'a, REG, const O: u8, FI = bool, M = BitM> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut W, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, REG, const O: u8, FI, M> BitWriter<'a, REG, O, FI, M> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} diff --git a/crates/bcm2711-lpa/src/gic_cpu.rs b/crates/bcm2711-lpa/src/gic_cpu.rs index 4034a7d..5e6916e 100644 --- a/crates/bcm2711-lpa/src/gic_cpu.rs +++ b/crates/bcm2711-lpa/src/gic_cpu.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - CPU Interface Control"] pub gicc_ctlr: GICC_CTLR, @@ -36,63 +37,78 @@ pub struct RegisterBlock { #[doc = "0x1000 - Deactivate Interrupt"] pub gicc_dir: GICC_DIR, } -#[doc = "GICC_CTLR (rw) register accessor: an alias for `Reg`"] +#[doc = "GICC_CTLR (rw) register accessor: CPU Interface Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_ctlr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_ctlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_ctlr`] +module"] pub type GICC_CTLR = crate::Reg; #[doc = "CPU Interface Control"] pub mod gicc_ctlr; -#[doc = "GICC_PMR (rw) register accessor: an alias for `Reg`"] +#[doc = "GICC_PMR (rw) register accessor: Interrupt Priority Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_pmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_pmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_pmr`] +module"] pub type GICC_PMR = crate::Reg; #[doc = "Interrupt Priority Mask"] pub mod gicc_pmr; -#[doc = "GICC_BPR (rw) register accessor: an alias for `Reg`"] +#[doc = "GICC_BPR (rw) register accessor: Binary Point\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_bpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_bpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_bpr`] +module"] pub type GICC_BPR = crate::Reg; #[doc = "Binary Point"] pub mod gicc_bpr; -#[doc = "GICC_IAR (r) register accessor: an alias for `Reg`"] +#[doc = "GICC_IAR (r) register accessor: Interrupt Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_iar::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_iar`] +module"] pub type GICC_IAR = crate::Reg; #[doc = "Interrupt Acknowledge"] pub mod gicc_iar; -#[doc = "GICC_EOIR (w) register accessor: an alias for `Reg`"] +#[doc = "GICC_EOIR (w) register accessor: End of Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_eoir::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_eoir`] +module"] pub type GICC_EOIR = crate::Reg; #[doc = "End of Interrupt"] pub mod gicc_eoir; -#[doc = "GICC_RPR (r) register accessor: an alias for `Reg`"] +#[doc = "GICC_RPR (r) register accessor: Running Priority\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_rpr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_rpr`] +module"] pub type GICC_RPR = crate::Reg; #[doc = "Running Priority"] pub mod gicc_rpr; -#[doc = "GICC_HPPIR (rw) register accessor: an alias for `Reg`"] +#[doc = "GICC_HPPIR (rw) register accessor: Highest Priority Pending Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_hppir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_hppir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_hppir`] +module"] pub type GICC_HPPIR = crate::Reg; #[doc = "Highest Priority Pending Interrupt"] pub mod gicc_hppir; -#[doc = "GICC_ABPR (rw) register accessor: an alias for `Reg`"] +#[doc = "GICC_ABPR (rw) register accessor: Aliased Binary Point\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_abpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_abpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_abpr`] +module"] pub type GICC_ABPR = crate::Reg; #[doc = "Aliased Binary Point"] pub mod gicc_abpr; -#[doc = "GICC_AIAR (r) register accessor: an alias for `Reg`"] +#[doc = "GICC_AIAR (r) register accessor: Aliased Interrupt Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_aiar::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_aiar`] +module"] pub type GICC_AIAR = crate::Reg; #[doc = "Aliased Interrupt Acknowledge"] pub mod gicc_aiar; -#[doc = "GICC_AEOIR (w) register accessor: an alias for `Reg`"] +#[doc = "GICC_AEOIR (w) register accessor: Aliased End of Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_aeoir::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_aeoir`] +module"] pub type GICC_AEOIR = crate::Reg; #[doc = "Aliased End of Interrupt"] pub mod gicc_aeoir; -#[doc = "GICC_AHPPIR (r) register accessor: an alias for `Reg`"] +#[doc = "GICC_AHPPIR (r) register accessor: Aliased Highest Priority Pending Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_ahppir::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_ahppir`] +module"] pub type GICC_AHPPIR = crate::Reg; #[doc = "Aliased Highest Priority Pending Interrupt"] pub mod gicc_ahppir; -#[doc = "GICC_APR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICC_APR0 (rw) register accessor: Active Priority\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_apr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_apr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_apr0`] +module"] pub type GICC_APR0 = crate::Reg; #[doc = "Active Priority"] pub mod gicc_apr0; -#[doc = "GICC_NSAPR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICC_NSAPR0 (rw) register accessor: Non-Secure Active Priority\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_nsapr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_nsapr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_nsapr0`] +module"] pub type GICC_NSAPR0 = crate::Reg; #[doc = "Non-Secure Active Priority"] pub mod gicc_nsapr0; -#[doc = "GICC_IIDR (rw) register accessor: an alias for `Reg`"] +#[doc = "GICC_IIDR (rw) register accessor: CPU Interface Identification Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_iidr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_iidr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_iidr`] +module"] pub type GICC_IIDR = crate::Reg; #[doc = "CPU Interface Identification Register"] pub mod gicc_iidr; -#[doc = "GICC_DIR (w) register accessor: an alias for `Reg`"] +#[doc = "GICC_DIR (w) register accessor: Deactivate Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_dir::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicc_dir`] +module"] pub type GICC_DIR = crate::Reg; #[doc = "Deactivate Interrupt"] pub mod gicc_dir; diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_abpr.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_abpr.rs index 3975333..efcb713 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_abpr.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_abpr.rs @@ -1,44 +1,11 @@ #[doc = "Register `GICC_ABPR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICC_ABPR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BINARY_POINT` reader - Split point between group priority and subpriority"] -pub type BINARY_POINT_R = crate::FieldReader; +pub type BINARY_POINT_R = crate::FieldReader; #[doc = "Field `BINARY_POINT` writer - Split point between group priority and subpriority"] -pub type BINARY_POINT_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICC_ABPR_SPEC, u8, u8, 3, O>; +pub type BINARY_POINT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:2 - Split point between group priority and subpriority"] #[inline(always)] @@ -46,32 +13,48 @@ impl R { BINARY_POINT_R::new((self.bits & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICC_ABPR") + .field( + "binary_point", + &format_args!("{}", self.binary_point().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Split point between group priority and subpriority"] #[inline(always)] #[must_use] - pub fn binary_point(&mut self) -> BINARY_POINT_W<0> { + pub fn binary_point(&mut self) -> BINARY_POINT_W { BINARY_POINT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Aliased Binary Point\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_abpr](index.html) module"] +#[doc = "Aliased Binary Point\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_abpr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_abpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_ABPR_SPEC; impl crate::RegisterSpec for GICC_ABPR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicc_abpr::R](R) reader structure"] -impl crate::Readable for GICC_ABPR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicc_abpr::W](W) writer structure"] +#[doc = "`read()` method returns [`gicc_abpr::R`](R) reader structure"] +impl crate::Readable for GICC_ABPR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicc_abpr::W`](W) writer structure"] impl crate::Writable for GICC_ABPR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_aeoir.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_aeoir.rs index 96afcae..32cf2fa 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_aeoir.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_aeoir.rs @@ -1,57 +1,45 @@ #[doc = "Register `GICC_AEOIR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTERRUPT_ID` writer - Interrupt ID"] -pub type INTERRUPT_ID_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICC_AEOIR_SPEC, u16, u16, 10, O>; +pub type INTERRUPT_ID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `CPUID` writer - CPUID that requested a software interrupt, 0 otherwise"] -pub type CPUID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICC_AEOIR_SPEC, u8, u8, 3, O>; +pub type CPUID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bits 0:9 - Interrupt ID"] #[inline(always)] #[must_use] - pub fn interrupt_id(&mut self) -> INTERRUPT_ID_W<0> { + pub fn interrupt_id(&mut self) -> INTERRUPT_ID_W { INTERRUPT_ID_W::new(self) } #[doc = "Bits 10:12 - CPUID that requested a software interrupt, 0 otherwise"] #[inline(always)] #[must_use] - pub fn cpuid(&mut self) -> CPUID_W<10> { + pub fn cpuid(&mut self) -> CPUID_W { CPUID_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Aliased End of Interrupt\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_aeoir](index.html) module"] +#[doc = "Aliased End of Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_aeoir::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_AEOIR_SPEC; impl crate::RegisterSpec for GICC_AEOIR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gicc_aeoir::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gicc_aeoir::W`](W) writer structure"] impl crate::Writable for GICC_AEOIR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_ahppir.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_ahppir.rs index bb21049..aab7b46 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_ahppir.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_ahppir.rs @@ -1,22 +1,9 @@ #[doc = "Register `GICC_AHPPIR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `INTERRUPT_ID` reader - Pending Interrupt ID"] -pub type INTERRUPT_ID_R = crate::FieldReader; +pub type INTERRUPT_ID_R = crate::FieldReader; #[doc = "Field `CPUID` reader - CPUID that requested a software interrupt, 0 otherwise"] -pub type CPUID_R = crate::FieldReader; +pub type CPUID_R = crate::FieldReader; impl R { #[doc = "Bits 0:9 - Pending Interrupt ID"] #[inline(always)] @@ -29,15 +16,29 @@ impl R { CPUID_R::new(((self.bits >> 10) & 7) as u8) } } -#[doc = "Aliased Highest Priority Pending Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_ahppir](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICC_AHPPIR") + .field("cpuid", &format_args!("{}", self.cpuid().bits())) + .field( + "interrupt_id", + &format_args!("{}", self.interrupt_id().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Aliased Highest Priority Pending Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_ahppir::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_AHPPIR_SPEC; impl crate::RegisterSpec for GICC_AHPPIR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicc_ahppir::R](R) reader structure"] -impl crate::Readable for GICC_AHPPIR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicc_ahppir::R`](R) reader structure"] +impl crate::Readable for GICC_AHPPIR_SPEC {} #[doc = "`reset()` method sets GICC_AHPPIR to value 0"] impl crate::Resettable for GICC_AHPPIR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_aiar.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_aiar.rs index 03c5d81..843a17c 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_aiar.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_aiar.rs @@ -1,22 +1,9 @@ #[doc = "Register `GICC_AIAR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `INTERRUPT_ID` reader - Interrupt ID"] -pub type INTERRUPT_ID_R = crate::FieldReader; +pub type INTERRUPT_ID_R = crate::FieldReader; #[doc = "Field `CPUID` reader - CPUID that requested a software interrupt, 0 otherwise"] -pub type CPUID_R = crate::FieldReader; +pub type CPUID_R = crate::FieldReader; impl R { #[doc = "Bits 0:9 - Interrupt ID"] #[inline(always)] @@ -29,15 +16,29 @@ impl R { CPUID_R::new(((self.bits >> 10) & 7) as u8) } } -#[doc = "Aliased Interrupt Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_aiar](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICC_AIAR") + .field("cpuid", &format_args!("{}", self.cpuid().bits())) + .field( + "interrupt_id", + &format_args!("{}", self.interrupt_id().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Aliased Interrupt Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_aiar::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_AIAR_SPEC; impl crate::RegisterSpec for GICC_AIAR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicc_aiar::R](R) reader structure"] -impl crate::Readable for GICC_AIAR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicc_aiar::R`](R) reader structure"] +impl crate::Readable for GICC_AIAR_SPEC {} #[doc = "`reset()` method sets GICC_AIAR to value 0"] impl crate::Resettable for GICC_AIAR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_apr0.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_apr0.rs index 27ab9b0..d99208d 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_apr0.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_apr0.rs @@ -1,59 +1,38 @@ #[doc = "Register `GICC_APR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICC_APR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Active Priority\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_apr0](index.html) module"] +#[doc = "Active Priority\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_apr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_apr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_APR0_SPEC; impl crate::RegisterSpec for GICC_APR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicc_apr0::R](R) reader structure"] -impl crate::Readable for GICC_APR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicc_apr0::W](W) writer structure"] +#[doc = "`read()` method returns [`gicc_apr0::R`](R) reader structure"] +impl crate::Readable for GICC_APR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicc_apr0::W`](W) writer structure"] impl crate::Writable for GICC_APR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_bpr.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_bpr.rs index 17bad97..8f8b226 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_bpr.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_bpr.rs @@ -1,43 +1,11 @@ #[doc = "Register `GICC_BPR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICC_BPR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BINARY_POINT` reader - Split point between group priority and subpriority"] -pub type BINARY_POINT_R = crate::FieldReader; +pub type BINARY_POINT_R = crate::FieldReader; #[doc = "Field `BINARY_POINT` writer - Split point between group priority and subpriority"] -pub type BINARY_POINT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICC_BPR_SPEC, u8, u8, 3, O>; +pub type BINARY_POINT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:2 - Split point between group priority and subpriority"] #[inline(always)] @@ -45,32 +13,48 @@ impl R { BINARY_POINT_R::new((self.bits & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICC_BPR") + .field( + "binary_point", + &format_args!("{}", self.binary_point().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Split point between group priority and subpriority"] #[inline(always)] #[must_use] - pub fn binary_point(&mut self) -> BINARY_POINT_W<0> { + pub fn binary_point(&mut self) -> BINARY_POINT_W { BINARY_POINT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Binary Point\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_bpr](index.html) module"] +#[doc = "Binary Point\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_bpr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_bpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_BPR_SPEC; impl crate::RegisterSpec for GICC_BPR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicc_bpr::R](R) reader structure"] -impl crate::Readable for GICC_BPR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicc_bpr::W](W) writer structure"] +#[doc = "`read()` method returns [`gicc_bpr::R`](R) reader structure"] +impl crate::Readable for GICC_BPR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicc_bpr::W`](W) writer structure"] impl crate::Writable for GICC_BPR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_ctlr.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_ctlr.rs index 97be545..d56368f 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_ctlr.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_ctlr.rs @@ -1,83 +1,51 @@ #[doc = "Register `GICC_CTLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICC_CTLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ENABLE_GROUP_0` reader - Enable signaling of group 0"] -pub type ENABLE_GROUP_0_R = crate::BitReader; +pub type ENABLE_GROUP_0_R = crate::BitReader; #[doc = "Field `ENABLE_GROUP_0` writer - Enable signaling of group 0"] -pub type ENABLE_GROUP_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +pub type ENABLE_GROUP_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE_GROUP_1` reader - Enable signaling of group 1"] -pub type ENABLE_GROUP_1_R = crate::BitReader; +pub type ENABLE_GROUP_1_R = crate::BitReader; #[doc = "Field `ENABLE_GROUP_1` writer - Enable signaling of group 1"] -pub type ENABLE_GROUP_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +pub type ENABLE_GROUP_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACKCTL` reader - Whether a read of IAR acknowledges the interrupt"] -pub type ACKCTL_R = crate::BitReader; +pub type ACKCTL_R = crate::BitReader; #[doc = "Field `ACKCTL` writer - Whether a read of IAR acknowledges the interrupt"] -pub type ACKCTL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +pub type ACKCTL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIQEN` reader - Group 0 triggers FIQ"] -pub type FIQEN_R = crate::BitReader; +pub type FIQEN_R = crate::BitReader; #[doc = "Field `FIQEN` writer - Group 0 triggers FIQ"] -pub type FIQEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +pub type FIQEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CBPR` reader - Common control of interrupts through GICC_BPR"] -pub type CBPR_R = crate::BitReader; +pub type CBPR_R = crate::BitReader; #[doc = "Field `CBPR` writer - Common control of interrupts through GICC_BPR"] -pub type CBPR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +pub type CBPR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIQBYPDISGRP0` reader - Bypass FIQ is not signaled to processor"] -pub type FIQBYPDISGRP0_R = crate::BitReader; +pub type FIQBYPDISGRP0_R = crate::BitReader; #[doc = "Field `FIQBYPDISGRP0` writer - Bypass FIQ is not signaled to processor"] -pub type FIQBYPDISGRP0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +pub type FIQBYPDISGRP0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IRQBYPDISGRP0` reader - Bypass IRQ is not signaled to processor"] -pub type IRQBYPDISGRP0_R = crate::BitReader; +pub type IRQBYPDISGRP0_R = crate::BitReader; #[doc = "Field `IRQBYPDISGRP0` writer - Bypass IRQ is not signaled to processor"] -pub type IRQBYPDISGRP0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +pub type IRQBYPDISGRP0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIQBYPDISGRP1` reader - Alias of group 1 FIQ bypass disable"] -pub type FIQBYPDISGRP1_R = crate::BitReader; +pub type FIQBYPDISGRP1_R = crate::BitReader; #[doc = "Field `FIQBYPDISGRP1` writer - Alias of group 1 FIQ bypass disable"] -pub type FIQBYPDISGRP1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +pub type FIQBYPDISGRP1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IRQBYPDISGRP1` reader - Alias of group 1 IRQ bypass disable"] -pub type IRQBYPDISGRP1_R = crate::BitReader; +pub type IRQBYPDISGRP1_R = crate::BitReader; #[doc = "Field `IRQBYPDISGRP1` writer - Alias of group 1 IRQ bypass disable"] -pub type IRQBYPDISGRP1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +pub type IRQBYPDISGRP1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOIMODES` reader - Secure EOIR does priority drop. DIR does deactivate."] -pub type EOIMODES_R = crate::BitReader; +pub type EOIMODES_R = crate::BitReader; #[doc = "Field `EOIMODES` writer - Secure EOIR does priority drop. DIR does deactivate."] -pub type EOIMODES_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +pub type EOIMODES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOIMODENS` reader - Non-Secure EOIR does priority drop. DIR does deactivate."] -pub type EOIMODENS_R = crate::BitReader; +pub type EOIMODENS_R = crate::BitReader; #[doc = "Field `EOIMODENS` writer - Non-Secure EOIR does priority drop. DIR does deactivate."] -pub type EOIMODENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICC_CTLR_SPEC, bool, O>; +pub type EOIMODENS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable signaling of group 0"] #[inline(always)] @@ -135,92 +103,133 @@ impl R { EOIMODENS_R::new(((self.bits >> 10) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICC_CTLR") + .field( + "enable_group_0", + &format_args!("{}", self.enable_group_0().bit()), + ) + .field( + "enable_group_1", + &format_args!("{}", self.enable_group_1().bit()), + ) + .field("ackctl", &format_args!("{}", self.ackctl().bit())) + .field("fiqen", &format_args!("{}", self.fiqen().bit())) + .field("cbpr", &format_args!("{}", self.cbpr().bit())) + .field( + "fiqbypdisgrp0", + &format_args!("{}", self.fiqbypdisgrp0().bit()), + ) + .field( + "irqbypdisgrp0", + &format_args!("{}", self.irqbypdisgrp0().bit()), + ) + .field( + "fiqbypdisgrp1", + &format_args!("{}", self.fiqbypdisgrp1().bit()), + ) + .field( + "irqbypdisgrp1", + &format_args!("{}", self.irqbypdisgrp1().bit()), + ) + .field("eoimodes", &format_args!("{}", self.eoimodes().bit())) + .field("eoimodens", &format_args!("{}", self.eoimodens().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable signaling of group 0"] #[inline(always)] #[must_use] - pub fn enable_group_0(&mut self) -> ENABLE_GROUP_0_W<0> { + pub fn enable_group_0(&mut self) -> ENABLE_GROUP_0_W { ENABLE_GROUP_0_W::new(self) } #[doc = "Bit 1 - Enable signaling of group 1"] #[inline(always)] #[must_use] - pub fn enable_group_1(&mut self) -> ENABLE_GROUP_1_W<1> { + pub fn enable_group_1(&mut self) -> ENABLE_GROUP_1_W { ENABLE_GROUP_1_W::new(self) } #[doc = "Bit 2 - Whether a read of IAR acknowledges the interrupt"] #[inline(always)] #[must_use] - pub fn ackctl(&mut self) -> ACKCTL_W<2> { + pub fn ackctl(&mut self) -> ACKCTL_W { ACKCTL_W::new(self) } #[doc = "Bit 3 - Group 0 triggers FIQ"] #[inline(always)] #[must_use] - pub fn fiqen(&mut self) -> FIQEN_W<3> { + pub fn fiqen(&mut self) -> FIQEN_W { FIQEN_W::new(self) } #[doc = "Bit 4 - Common control of interrupts through GICC_BPR"] #[inline(always)] #[must_use] - pub fn cbpr(&mut self) -> CBPR_W<4> { + pub fn cbpr(&mut self) -> CBPR_W { CBPR_W::new(self) } #[doc = "Bit 5 - Bypass FIQ is not signaled to processor"] #[inline(always)] #[must_use] - pub fn fiqbypdisgrp0(&mut self) -> FIQBYPDISGRP0_W<5> { + pub fn fiqbypdisgrp0(&mut self) -> FIQBYPDISGRP0_W { FIQBYPDISGRP0_W::new(self) } #[doc = "Bit 6 - Bypass IRQ is not signaled to processor"] #[inline(always)] #[must_use] - pub fn irqbypdisgrp0(&mut self) -> IRQBYPDISGRP0_W<6> { + pub fn irqbypdisgrp0(&mut self) -> IRQBYPDISGRP0_W { IRQBYPDISGRP0_W::new(self) } #[doc = "Bit 7 - Alias of group 1 FIQ bypass disable"] #[inline(always)] #[must_use] - pub fn fiqbypdisgrp1(&mut self) -> FIQBYPDISGRP1_W<7> { + pub fn fiqbypdisgrp1(&mut self) -> FIQBYPDISGRP1_W { FIQBYPDISGRP1_W::new(self) } #[doc = "Bit 8 - Alias of group 1 IRQ bypass disable"] #[inline(always)] #[must_use] - pub fn irqbypdisgrp1(&mut self) -> IRQBYPDISGRP1_W<8> { + pub fn irqbypdisgrp1(&mut self) -> IRQBYPDISGRP1_W { IRQBYPDISGRP1_W::new(self) } #[doc = "Bit 9 - Secure EOIR does priority drop. DIR does deactivate."] #[inline(always)] #[must_use] - pub fn eoimodes(&mut self) -> EOIMODES_W<9> { + pub fn eoimodes(&mut self) -> EOIMODES_W { EOIMODES_W::new(self) } #[doc = "Bit 10 - Non-Secure EOIR does priority drop. DIR does deactivate."] #[inline(always)] #[must_use] - pub fn eoimodens(&mut self) -> EOIMODENS_W<10> { + pub fn eoimodens(&mut self) -> EOIMODENS_W { EOIMODENS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "CPU Interface Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_ctlr](index.html) module"] +#[doc = "CPU Interface Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_ctlr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_ctlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_CTLR_SPEC; impl crate::RegisterSpec for GICC_CTLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicc_ctlr::R](R) reader structure"] -impl crate::Readable for GICC_CTLR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicc_ctlr::W](W) writer structure"] +#[doc = "`read()` method returns [`gicc_ctlr::R`](R) reader structure"] +impl crate::Readable for GICC_CTLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicc_ctlr::W`](W) writer structure"] impl crate::Writable for GICC_CTLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_dir.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_dir.rs index 085fb08..c291218 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_dir.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_dir.rs @@ -1,40 +1,29 @@ #[doc = "Register `GICC_DIR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +pub type W = crate::W; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Deactivate Interrupt\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_dir](index.html) module"] +#[doc = "Deactivate Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_dir::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_DIR_SPEC; impl crate::RegisterSpec for GICC_DIR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gicc_dir::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gicc_dir::W`](W) writer structure"] impl crate::Writable for GICC_DIR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_eoir.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_eoir.rs index 3b01bd6..39a0ad3 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_eoir.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_eoir.rs @@ -1,57 +1,45 @@ #[doc = "Register `GICC_EOIR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTERRUPT_ID` writer - Interrupt ID"] -pub type INTERRUPT_ID_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICC_EOIR_SPEC, u16, u16, 10, O>; +pub type INTERRUPT_ID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `CPUID` writer - CPUID that requested a software interrupt, 0 otherwise"] -pub type CPUID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICC_EOIR_SPEC, u8, u8, 3, O>; +pub type CPUID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bits 0:9 - Interrupt ID"] #[inline(always)] #[must_use] - pub fn interrupt_id(&mut self) -> INTERRUPT_ID_W<0> { + pub fn interrupt_id(&mut self) -> INTERRUPT_ID_W { INTERRUPT_ID_W::new(self) } #[doc = "Bits 10:12 - CPUID that requested a software interrupt, 0 otherwise"] #[inline(always)] #[must_use] - pub fn cpuid(&mut self) -> CPUID_W<10> { + pub fn cpuid(&mut self) -> CPUID_W { CPUID_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "End of Interrupt\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_eoir](index.html) module"] +#[doc = "End of Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_eoir::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_EOIR_SPEC; impl crate::RegisterSpec for GICC_EOIR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gicc_eoir::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gicc_eoir::W`](W) writer structure"] impl crate::Writable for GICC_EOIR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_hppir.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_hppir.rs index ac14818..eeade18 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_hppir.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_hppir.rs @@ -1,48 +1,15 @@ #[doc = "Register `GICC_HPPIR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICC_HPPIR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTERRUPT_ID` reader - Pending Interrupt ID"] -pub type INTERRUPT_ID_R = crate::FieldReader; +pub type INTERRUPT_ID_R = crate::FieldReader; #[doc = "Field `INTERRUPT_ID` writer - Pending Interrupt ID"] -pub type INTERRUPT_ID_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICC_HPPIR_SPEC, u16, u16, 10, O>; +pub type INTERRUPT_ID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `CPUID` reader - CPUID that requested a software interrupt, 0 otherwise"] -pub type CPUID_R = crate::FieldReader; +pub type CPUID_R = crate::FieldReader; #[doc = "Field `CPUID` writer - CPUID that requested a software interrupt, 0 otherwise"] -pub type CPUID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICC_HPPIR_SPEC, u8, u8, 3, O>; +pub type CPUID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:9 - Pending Interrupt ID"] #[inline(always)] @@ -55,38 +22,55 @@ impl R { CPUID_R::new(((self.bits >> 10) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICC_HPPIR") + .field("cpuid", &format_args!("{}", self.cpuid().bits())) + .field( + "interrupt_id", + &format_args!("{}", self.interrupt_id().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:9 - Pending Interrupt ID"] #[inline(always)] #[must_use] - pub fn interrupt_id(&mut self) -> INTERRUPT_ID_W<0> { + pub fn interrupt_id(&mut self) -> INTERRUPT_ID_W { INTERRUPT_ID_W::new(self) } #[doc = "Bits 10:12 - CPUID that requested a software interrupt, 0 otherwise"] #[inline(always)] #[must_use] - pub fn cpuid(&mut self) -> CPUID_W<10> { + pub fn cpuid(&mut self) -> CPUID_W { CPUID_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Highest Priority Pending Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_hppir](index.html) module"] +#[doc = "Highest Priority Pending Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_hppir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_hppir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_HPPIR_SPEC; impl crate::RegisterSpec for GICC_HPPIR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicc_hppir::R](R) reader structure"] -impl crate::Readable for GICC_HPPIR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicc_hppir::W](W) writer structure"] +#[doc = "`read()` method returns [`gicc_hppir::R`](R) reader structure"] +impl crate::Readable for GICC_HPPIR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicc_hppir::W`](W) writer structure"] impl crate::Writable for GICC_HPPIR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_iar.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_iar.rs index 5df4c51..56296b0 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_iar.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_iar.rs @@ -1,22 +1,9 @@ #[doc = "Register `GICC_IAR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `INTERRUPT_ID` reader - Interrupt ID"] -pub type INTERRUPT_ID_R = crate::FieldReader; +pub type INTERRUPT_ID_R = crate::FieldReader; #[doc = "Field `CPUID` reader - CPUID that requested a software interrupt, 0 otherwise"] -pub type CPUID_R = crate::FieldReader; +pub type CPUID_R = crate::FieldReader; impl R { #[doc = "Bits 0:9 - Interrupt ID"] #[inline(always)] @@ -29,15 +16,29 @@ impl R { CPUID_R::new(((self.bits >> 10) & 7) as u8) } } -#[doc = "Interrupt Acknowledge\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_iar](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICC_IAR") + .field("cpuid", &format_args!("{}", self.cpuid().bits())) + .field( + "interrupt_id", + &format_args!("{}", self.interrupt_id().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Interrupt Acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_iar::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_IAR_SPEC; impl crate::RegisterSpec for GICC_IAR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicc_iar::R](R) reader structure"] -impl crate::Readable for GICC_IAR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicc_iar::R`](R) reader structure"] +impl crate::Readable for GICC_IAR_SPEC {} #[doc = "`reset()` method sets GICC_IAR to value 0"] impl crate::Resettable for GICC_IAR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_iidr.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_iidr.rs index 58d00e8..46c6d1f 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_iidr.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_iidr.rs @@ -1,41 +1,9 @@ #[doc = "Register `GICC_IIDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICC_IIDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ID` reader - ID"] -pub type ID_R = crate::FieldReader; +pub type ID_R = crate::FieldReader; #[doc = "ID\n\nValue on reset: 33690683"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -49,27 +17,34 @@ impl From for u32 { variant as _ } } +impl crate::FieldSpec for ID_A { + type Ux = u32; +} impl ID_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 33690683 => Some(ID_A::VALID), _ => None, } } - #[doc = "Checks if the value of the field is `VALID`"] + #[doc = "ID is valid"] #[inline(always)] pub fn is_valid(&self) -> bool { *self == ID_A::VALID } } #[doc = "Field `ID` writer - ID"] -pub type ID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICC_IIDR_SPEC, u32, ID_A, 32, O>; -impl<'a, const O: u8> ID_W<'a, O> { +pub type ID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, ID_A>; +impl<'a, REG, const O: u8> ID_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "ID is valid"] #[inline(always)] - pub fn valid(self) -> &'a mut W { + pub fn valid(self) -> &'a mut crate::W { self.variant(ID_A::VALID) } } @@ -80,32 +55,45 @@ impl R { ID_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICC_IIDR") + .field("id", &format_args!("{}", self.id().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - ID"] #[inline(always)] #[must_use] - pub fn id(&mut self) -> ID_W<0> { + pub fn id(&mut self) -> ID_W { ID_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "CPU Interface Identification Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_iidr](index.html) module"] +#[doc = "CPU Interface Identification Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_iidr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_iidr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_IIDR_SPEC; impl crate::RegisterSpec for GICC_IIDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicc_iidr::R](R) reader structure"] -impl crate::Readable for GICC_IIDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicc_iidr::W](W) writer structure"] +#[doc = "`read()` method returns [`gicc_iidr::R`](R) reader structure"] +impl crate::Readable for GICC_IIDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicc_iidr::W`](W) writer structure"] impl crate::Writable for GICC_IIDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_nsapr0.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_nsapr0.rs index 516f769..3fbe506 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_nsapr0.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_nsapr0.rs @@ -1,59 +1,38 @@ #[doc = "Register `GICC_NSAPR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICC_NSAPR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Non-Secure Active Priority\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_nsapr0](index.html) module"] +#[doc = "Non-Secure Active Priority\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_nsapr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_nsapr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_NSAPR0_SPEC; impl crate::RegisterSpec for GICC_NSAPR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicc_nsapr0::R](R) reader structure"] -impl crate::Readable for GICC_NSAPR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicc_nsapr0::W](W) writer structure"] +#[doc = "`read()` method returns [`gicc_nsapr0::R`](R) reader structure"] +impl crate::Readable for GICC_NSAPR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicc_nsapr0::W`](W) writer structure"] impl crate::Writable for GICC_NSAPR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_pmr.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_pmr.rs index 826676d..b4c145e 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_pmr.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_pmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `GICC_PMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICC_PMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PRIORITY` reader - Interrupts with a higher number are not signaled"] -pub type PRIORITY_R = crate::FieldReader; +pub type PRIORITY_R = crate::FieldReader; #[doc = "Field `PRIORITY` writer - Interrupts with a higher number are not signaled"] -pub type PRIORITY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICC_PMR_SPEC, u8, u8, 8, O>; +pub type PRIORITY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupts with a higher number are not signaled"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { PRIORITY_R::new((self.bits & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICC_PMR") + .field("priority", &format_args!("{}", self.priority().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupts with a higher number are not signaled"] #[inline(always)] #[must_use] - pub fn priority(&mut self) -> PRIORITY_W<0> { + pub fn priority(&mut self) -> PRIORITY_W { PRIORITY_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_pmr](index.html) module"] +#[doc = "Interrupt Priority Mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_pmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicc_pmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_PMR_SPEC; impl crate::RegisterSpec for GICC_PMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicc_pmr::R](R) reader structure"] -impl crate::Readable for GICC_PMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicc_pmr::W](W) writer structure"] +#[doc = "`read()` method returns [`gicc_pmr::R`](R) reader structure"] +impl crate::Readable for GICC_PMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicc_pmr::W`](W) writer structure"] impl crate::Writable for GICC_PMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_cpu/gicc_rpr.rs b/crates/bcm2711-lpa/src/gic_cpu/gicc_rpr.rs index 0fd4ff9..3133e4f 100644 --- a/crates/bcm2711-lpa/src/gic_cpu/gicc_rpr.rs +++ b/crates/bcm2711-lpa/src/gic_cpu/gicc_rpr.rs @@ -1,20 +1,7 @@ #[doc = "Register `GICC_RPR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PRIORITY` reader - Current running priority"] -pub type PRIORITY_R = crate::FieldReader; +pub type PRIORITY_R = crate::FieldReader; impl R { #[doc = "Bits 0:7 - Current running priority"] #[inline(always)] @@ -22,15 +9,25 @@ impl R { PRIORITY_R::new((self.bits & 0xff) as u8) } } -#[doc = "Running Priority\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicc_rpr](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICC_RPR") + .field("priority", &format_args!("{}", self.priority().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Running Priority\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicc_rpr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICC_RPR_SPEC; impl crate::RegisterSpec for GICC_RPR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicc_rpr::R](R) reader structure"] -impl crate::Readable for GICC_RPR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicc_rpr::R`](R) reader structure"] +impl crate::Readable for GICC_RPR_SPEC {} #[doc = "`reset()` method sets GICC_RPR to value 0"] impl crate::Resettable for GICC_RPR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/gic_dist.rs b/crates/bcm2711-lpa/src/gic_dist.rs index d461b3d..ba8c534 100644 --- a/crates/bcm2711-lpa/src/gic_dist.rs +++ b/crates/bcm2711-lpa/src/gic_dist.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Distributor Control Register"] pub gicd_ctlr: GICD_CTLR, @@ -87,15 +88,18 @@ pub struct RegisterBlock { #[doc = "0xffc - Component ID 3"] pub gicd_cidr3: GICD_CIDR3, } -#[doc = "GICD_CTLR (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_CTLR (rw) register accessor: Distributor Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ctlr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ctlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ctlr`] +module"] pub type GICD_CTLR = crate::Reg; #[doc = "Distributor Control Register"] pub mod gicd_ctlr; -#[doc = "GICD_TYPER (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_TYPER (r) register accessor: Interrupt Controller Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_typer::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_typer`] +module"] pub type GICD_TYPER = crate::Reg; #[doc = "Interrupt Controller Type Register"] pub mod gicd_typer; -#[doc = "GICD_IIDR (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_IIDR (r) register accessor: Distributor Implementer Identification Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_iidr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_iidr`] +module"] pub type GICD_IIDR = crate::Reg; #[doc = "Distributor Implementer Identification Register"] pub mod gicd_iidr; @@ -149,91 +153,113 @@ pub use self::gicd_icfgr::GICD_ICFGR; #[doc = r"Cluster"] #[doc = "Interrupt Configuration"] pub mod gicd_icfgr; -#[doc = "GICD_PPISR (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_PPISR (rw) register accessor: Private Peripheral Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ppisr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ppisr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ppisr`] +module"] pub type GICD_PPISR = crate::Reg; #[doc = "Private Peripheral Interrupt Status Register"] pub mod gicd_ppisr; -#[doc = "GICD_SPISR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_SPISR0 (rw) register accessor: Shared Peripheral Interrupt Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spisr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spisr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_spisr0`] +module"] pub type GICD_SPISR0 = crate::Reg; #[doc = "Shared Peripheral Interrupt Status Registers"] pub mod gicd_spisr0; -#[doc = "GICD_SPISR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_SPISR1 (rw) register accessor: Shared Peripheral Interrupt Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spisr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spisr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_spisr1`] +module"] pub type GICD_SPISR1 = crate::Reg; #[doc = "Shared Peripheral Interrupt Status Registers"] pub mod gicd_spisr1; -#[doc = "GICD_SPISR2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_SPISR2 (rw) register accessor: Shared Peripheral Interrupt Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spisr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spisr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_spisr2`] +module"] pub type GICD_SPISR2 = crate::Reg; #[doc = "Shared Peripheral Interrupt Status Registers"] pub mod gicd_spisr2; -#[doc = "GICD_SPISR3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_SPISR3 (rw) register accessor: Shared Peripheral Interrupt Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spisr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spisr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_spisr3`] +module"] pub type GICD_SPISR3 = crate::Reg; #[doc = "Shared Peripheral Interrupt Status Registers"] pub mod gicd_spisr3; -#[doc = "GICD_SPISR4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_SPISR4 (rw) register accessor: Shared Peripheral Interrupt Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spisr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spisr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_spisr4`] +module"] pub type GICD_SPISR4 = crate::Reg; #[doc = "Shared Peripheral Interrupt Status Registers"] pub mod gicd_spisr4; -#[doc = "GICD_SPISR5 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_SPISR5 (rw) register accessor: Shared Peripheral Interrupt Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spisr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spisr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_spisr5`] +module"] pub type GICD_SPISR5 = crate::Reg; #[doc = "Shared Peripheral Interrupt Status Registers"] pub mod gicd_spisr5; -#[doc = "GICD_SGIR (w) register accessor: an alias for `Reg`"] +#[doc = "GICD_SGIR (w) register accessor: Software Generated Interrupt Register\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_sgir::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_sgir`] +module"] pub type GICD_SGIR = crate::Reg; #[doc = "Software Generated Interrupt Register"] pub mod gicd_sgir; -#[doc = "GICD_CPENDSGIRn (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_CPENDSGIRn (rw) register accessor: SGI Clear-Pending Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_cpendsgirn::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_cpendsgirn::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_cpendsgirn`] +module"] pub type GICD_CPENDSGIRN = crate::Reg; #[doc = "SGI Clear-Pending Registers"] pub mod gicd_cpendsgirn; -#[doc = "GICD_SPENDSGIRn (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_SPENDSGIRn (rw) register accessor: SGI Set-Pending Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spendsgirn::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spendsgirn::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_spendsgirn`] +module"] pub type GICD_SPENDSGIRN = crate::Reg; #[doc = "SGI Set-Pending Registers"] pub mod gicd_spendsgirn; -#[doc = "GICD_PIDR4 (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_PIDR4 (r) register accessor: Peripheral ID 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_pidr4`] +module"] pub type GICD_PIDR4 = crate::Reg; #[doc = "Peripheral ID 4"] pub mod gicd_pidr4; -#[doc = "GICD_PIDR5 (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_PIDR5 (r) register accessor: Peripheral ID 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_pidr5`] +module"] pub type GICD_PIDR5 = crate::Reg; #[doc = "Peripheral ID 5"] pub mod gicd_pidr5; -#[doc = "GICD_PIDR6 (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_PIDR6 (r) register accessor: Peripheral ID 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_pidr6`] +module"] pub type GICD_PIDR6 = crate::Reg; #[doc = "Peripheral ID 6"] pub mod gicd_pidr6; -#[doc = "GICD_PIDR7 (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_PIDR7 (r) register accessor: Peripheral ID 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_pidr7`] +module"] pub type GICD_PIDR7 = crate::Reg; #[doc = "Peripheral ID 7"] pub mod gicd_pidr7; -#[doc = "GICD_PIDR0 (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_PIDR0 (r) register accessor: Peripheral ID 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_pidr0`] +module"] pub type GICD_PIDR0 = crate::Reg; #[doc = "Peripheral ID 0"] pub mod gicd_pidr0; -#[doc = "GICD_PIDR1 (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_PIDR1 (r) register accessor: Peripheral ID 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_pidr1`] +module"] pub type GICD_PIDR1 = crate::Reg; #[doc = "Peripheral ID 1"] pub mod gicd_pidr1; -#[doc = "GICD_PIDR2 (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_PIDR2 (r) register accessor: Peripheral ID 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_pidr2`] +module"] pub type GICD_PIDR2 = crate::Reg; #[doc = "Peripheral ID 2"] pub mod gicd_pidr2; -#[doc = "GICD_PIDR3 (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_PIDR3 (r) register accessor: Peripheral ID 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_pidr3`] +module"] pub type GICD_PIDR3 = crate::Reg; #[doc = "Peripheral ID 3"] pub mod gicd_pidr3; -#[doc = "GICD_CIDR0 (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_CIDR0 (r) register accessor: Component ID 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_cidr0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_cidr0`] +module"] pub type GICD_CIDR0 = crate::Reg; #[doc = "Component ID 0"] pub mod gicd_cidr0; -#[doc = "GICD_CIDR1 (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_CIDR1 (r) register accessor: Component ID 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_cidr1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_cidr1`] +module"] pub type GICD_CIDR1 = crate::Reg; #[doc = "Component ID 1"] pub mod gicd_cidr1; -#[doc = "GICD_CIDR2 (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_CIDR2 (r) register accessor: Component ID 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_cidr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_cidr2`] +module"] pub type GICD_CIDR2 = crate::Reg; #[doc = "Component ID 2"] pub mod gicd_cidr2; -#[doc = "GICD_CIDR3 (r) register accessor: an alias for `Reg`"] +#[doc = "GICD_CIDR3 (r) register accessor: Component ID 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_cidr3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_cidr3`] +module"] pub type GICD_CIDR3 = crate::Reg; #[doc = "Component ID 3"] pub mod gicd_cidr3; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_cidr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr0.rs index 3ba16b0..4254623 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_cidr0.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr0.rs @@ -1,20 +1,7 @@ #[doc = "Register `GICD_CIDR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GICD_CIDR0` reader - Component ID 0"] -pub type GICD_CIDR0_R = crate::FieldReader; +pub type GICD_CIDR0_R = crate::FieldReader; #[doc = "Component ID 0\n\nValue on reset: 13"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -28,16 +15,19 @@ impl From for u32 { variant as _ } } +impl crate::FieldSpec for GICD_CIDR0_A { + type Ux = u32; +} impl GICD_CIDR0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 13 => Some(GICD_CIDR0_A::VALID), _ => None, } } - #[doc = "Checks if the value of the field is `VALID`"] + #[doc = "Valid"] #[inline(always)] pub fn is_valid(&self) -> bool { *self == GICD_CIDR0_A::VALID @@ -50,15 +40,25 @@ impl R { GICD_CIDR0_R::new(self.bits) } } -#[doc = "Component ID 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_cidr0](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_CIDR0") + .field("gicd_cidr0", &format_args!("{}", self.gicd_cidr0().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Component ID 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_cidr0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_CIDR0_SPEC; impl crate::RegisterSpec for GICD_CIDR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_cidr0::R](R) reader structure"] -impl crate::Readable for GICD_CIDR0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_cidr0::R`](R) reader structure"] +impl crate::Readable for GICD_CIDR0_SPEC {} #[doc = "`reset()` method sets GICD_CIDR0 to value 0x0d"] impl crate::Resettable for GICD_CIDR0_SPEC { const RESET_VALUE: Self::Ux = 0x0d; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_cidr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr1.rs index f1bd600..52aa465 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_cidr1.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr1.rs @@ -1,20 +1,7 @@ #[doc = "Register `GICD_CIDR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GICD_CIDR1` reader - Component ID 1"] -pub type GICD_CIDR1_R = crate::FieldReader; +pub type GICD_CIDR1_R = crate::FieldReader; #[doc = "Component ID 1\n\nValue on reset: 240"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -28,16 +15,19 @@ impl From for u32 { variant as _ } } +impl crate::FieldSpec for GICD_CIDR1_A { + type Ux = u32; +} impl GICD_CIDR1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 240 => Some(GICD_CIDR1_A::VALID), _ => None, } } - #[doc = "Checks if the value of the field is `VALID`"] + #[doc = "Valid"] #[inline(always)] pub fn is_valid(&self) -> bool { *self == GICD_CIDR1_A::VALID @@ -50,15 +40,25 @@ impl R { GICD_CIDR1_R::new(self.bits) } } -#[doc = "Component ID 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_cidr1](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_CIDR1") + .field("gicd_cidr1", &format_args!("{}", self.gicd_cidr1().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Component ID 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_cidr1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_CIDR1_SPEC; impl crate::RegisterSpec for GICD_CIDR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_cidr1::R](R) reader structure"] -impl crate::Readable for GICD_CIDR1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_cidr1::R`](R) reader structure"] +impl crate::Readable for GICD_CIDR1_SPEC {} #[doc = "`reset()` method sets GICD_CIDR1 to value 0xf0"] impl crate::Resettable for GICD_CIDR1_SPEC { const RESET_VALUE: Self::Ux = 0xf0; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_cidr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr2.rs index 54897e6..4c7d919 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_cidr2.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr2.rs @@ -1,20 +1,7 @@ #[doc = "Register `GICD_CIDR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GICD_CIDR2` reader - Component ID 2"] -pub type GICD_CIDR2_R = crate::FieldReader; +pub type GICD_CIDR2_R = crate::FieldReader; #[doc = "Component ID 2\n\nValue on reset: 5"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -28,16 +15,19 @@ impl From for u32 { variant as _ } } +impl crate::FieldSpec for GICD_CIDR2_A { + type Ux = u32; +} impl GICD_CIDR2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 5 => Some(GICD_CIDR2_A::VALID), _ => None, } } - #[doc = "Checks if the value of the field is `VALID`"] + #[doc = "Valid"] #[inline(always)] pub fn is_valid(&self) -> bool { *self == GICD_CIDR2_A::VALID @@ -50,15 +40,25 @@ impl R { GICD_CIDR2_R::new(self.bits) } } -#[doc = "Component ID 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_cidr2](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_CIDR2") + .field("gicd_cidr2", &format_args!("{}", self.gicd_cidr2().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Component ID 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_cidr2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_CIDR2_SPEC; impl crate::RegisterSpec for GICD_CIDR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_cidr2::R](R) reader structure"] -impl crate::Readable for GICD_CIDR2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_cidr2::R`](R) reader structure"] +impl crate::Readable for GICD_CIDR2_SPEC {} #[doc = "`reset()` method sets GICD_CIDR2 to value 0x05"] impl crate::Resettable for GICD_CIDR2_SPEC { const RESET_VALUE: Self::Ux = 0x05; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_cidr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr3.rs index f70dd88..29f17d9 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_cidr3.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_cidr3.rs @@ -1,20 +1,7 @@ #[doc = "Register `GICD_CIDR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GICD_CIDR3` reader - Component ID 3"] -pub type GICD_CIDR3_R = crate::FieldReader; +pub type GICD_CIDR3_R = crate::FieldReader; #[doc = "Component ID 3\n\nValue on reset: 177"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -28,16 +15,19 @@ impl From for u32 { variant as _ } } +impl crate::FieldSpec for GICD_CIDR3_A { + type Ux = u32; +} impl GICD_CIDR3_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 177 => Some(GICD_CIDR3_A::VALID), _ => None, } } - #[doc = "Checks if the value of the field is `VALID`"] + #[doc = "Valid"] #[inline(always)] pub fn is_valid(&self) -> bool { *self == GICD_CIDR3_A::VALID @@ -50,15 +40,25 @@ impl R { GICD_CIDR3_R::new(self.bits) } } -#[doc = "Component ID 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_cidr3](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_CIDR3") + .field("gicd_cidr3", &format_args!("{}", self.gicd_cidr3().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Component ID 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_cidr3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_CIDR3_SPEC; impl crate::RegisterSpec for GICD_CIDR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_cidr3::R](R) reader structure"] -impl crate::Readable for GICD_CIDR3_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_cidr3::R`](R) reader structure"] +impl crate::Readable for GICD_CIDR3_SPEC {} #[doc = "`reset()` method sets GICD_CIDR3 to value 0xb1"] impl crate::Resettable for GICD_CIDR3_SPEC { const RESET_VALUE: Self::Ux = 0xb1; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_cpendsgirn.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_cpendsgirn.rs index 5490c9c..ad22a08 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_cpendsgirn.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_cpendsgirn.rs @@ -1,59 +1,38 @@ #[doc = "Register `GICD_CPENDSGIRn` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_CPENDSGIRn` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SGI Clear-Pending Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_cpendsgirn](index.html) module"] +#[doc = "SGI Clear-Pending Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_cpendsgirn::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_cpendsgirn::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_CPENDSGIRN_SPEC; impl crate::RegisterSpec for GICD_CPENDSGIRN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_cpendsgirn::R](R) reader structure"] -impl crate::Readable for GICD_CPENDSGIRN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_cpendsgirn::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_cpendsgirn::R`](R) reader structure"] +impl crate::Readable for GICD_CPENDSGIRN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_cpendsgirn::W`](W) writer structure"] impl crate::Writable for GICD_CPENDSGIRN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ctlr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ctlr.rs index b9d2e83..61f351c 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ctlr.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ctlr.rs @@ -1,47 +1,15 @@ #[doc = "Register `GICD_CTLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_CTLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ENABLE_GROUP0` reader - Enable group 0 interrupts"] -pub type ENABLE_GROUP0_R = crate::BitReader; +pub type ENABLE_GROUP0_R = crate::BitReader; #[doc = "Field `ENABLE_GROUP0` writer - Enable group 0 interrupts"] -pub type ENABLE_GROUP0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_CTLR_SPEC, bool, O>; +pub type ENABLE_GROUP0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE_GROUP1` reader - Enable group 1 interrupts"] -pub type ENABLE_GROUP1_R = crate::BitReader; +pub type ENABLE_GROUP1_R = crate::BitReader; #[doc = "Field `ENABLE_GROUP1` writer - Enable group 1 interrupts"] -pub type ENABLE_GROUP1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_CTLR_SPEC, bool, O>; +pub type ENABLE_GROUP1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable group 0 interrupts"] #[inline(always)] @@ -54,38 +22,58 @@ impl R { ENABLE_GROUP1_R::new(((self.bits >> 1) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_CTLR") + .field( + "enable_group0", + &format_args!("{}", self.enable_group0().bit()), + ) + .field( + "enable_group1", + &format_args!("{}", self.enable_group1().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable group 0 interrupts"] #[inline(always)] #[must_use] - pub fn enable_group0(&mut self) -> ENABLE_GROUP0_W<0> { + pub fn enable_group0(&mut self) -> ENABLE_GROUP0_W { ENABLE_GROUP0_W::new(self) } #[doc = "Bit 1 - Enable group 1 interrupts"] #[inline(always)] #[must_use] - pub fn enable_group1(&mut self) -> ENABLE_GROUP1_W<1> { + pub fn enable_group1(&mut self) -> ENABLE_GROUP1_W { ENABLE_GROUP1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Distributor Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ctlr](index.html) module"] +#[doc = "Distributor Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ctlr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ctlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_CTLR_SPEC; impl crate::RegisterSpec for GICD_CTLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ctlr::R](R) reader structure"] -impl crate::Readable for GICD_CTLR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ctlr::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ctlr::R`](R) reader structure"] +impl crate::Readable for GICD_CTLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ctlr::W`](W) writer structure"] impl crate::Writable for GICD_CTLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver.rs index 31547ed..c312143 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct GICD_ICACTIVER { #[doc = "0x00 - Interrupt Clear-Active"] pub gicd_icactiver0: GICD_ICACTIVER0, @@ -16,31 +17,38 @@ pub struct GICD_ICACTIVER { #[doc = "0x18 - Interrupt Clear-Active"] pub gicd_icactiver6: GICD_ICACTIVER6, } -#[doc = "GICD_ICACTIVER0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICACTIVER0 (rw) register accessor: Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icactiver0`] +module"] pub type GICD_ICACTIVER0 = crate::Reg; #[doc = "Interrupt Clear-Active"] pub mod gicd_icactiver0; -#[doc = "GICD_ICACTIVER1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICACTIVER1 (rw) register accessor: Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icactiver1`] +module"] pub type GICD_ICACTIVER1 = crate::Reg; #[doc = "Interrupt Clear-Active"] pub mod gicd_icactiver1; -#[doc = "GICD_ICACTIVER2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICACTIVER2 (rw) register accessor: Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icactiver2`] +module"] pub type GICD_ICACTIVER2 = crate::Reg; #[doc = "Interrupt Clear-Active"] pub mod gicd_icactiver2; -#[doc = "GICD_ICACTIVER3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICACTIVER3 (rw) register accessor: Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icactiver3`] +module"] pub type GICD_ICACTIVER3 = crate::Reg; #[doc = "Interrupt Clear-Active"] pub mod gicd_icactiver3; -#[doc = "GICD_ICACTIVER4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICACTIVER4 (rw) register accessor: Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icactiver4`] +module"] pub type GICD_ICACTIVER4 = crate::Reg; #[doc = "Interrupt Clear-Active"] pub mod gicd_icactiver4; -#[doc = "GICD_ICACTIVER5 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICACTIVER5 (rw) register accessor: Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icactiver5`] +module"] pub type GICD_ICACTIVER5 = crate::Reg; #[doc = "Interrupt Clear-Active"] pub mod gicd_icactiver5; -#[doc = "GICD_ICACTIVER6 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICACTIVER6 (rw) register accessor: Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icactiver6`] +module"] pub type GICD_ICACTIVER6 = crate::Reg; #[doc = "Interrupt Clear-Active"] pub mod gicd_icactiver6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver0.rs index e6ed1e9..d1e28fd 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver0.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ICACTIVER0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICACTIVER0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT0` reader - Interrupt 0"] -pub type INT0_R = crate::BitReader; +pub type INT0_R = crate::BitReader; #[doc = "Field `INT0` writer - Interrupt 0"] -pub type INT0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT1` reader - Interrupt 1"] -pub type INT1_R = crate::BitReader; +pub type INT1_R = crate::BitReader; #[doc = "Field `INT1` writer - Interrupt 1"] -pub type INT1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT2` reader - Interrupt 2"] -pub type INT2_R = crate::BitReader; +pub type INT2_R = crate::BitReader; #[doc = "Field `INT2` writer - Interrupt 2"] -pub type INT2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT3` reader - Interrupt 3"] -pub type INT3_R = crate::BitReader; +pub type INT3_R = crate::BitReader; #[doc = "Field `INT3` writer - Interrupt 3"] -pub type INT3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT4` reader - Interrupt 4"] -pub type INT4_R = crate::BitReader; +pub type INT4_R = crate::BitReader; #[doc = "Field `INT4` writer - Interrupt 4"] -pub type INT4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT5` reader - Interrupt 5"] -pub type INT5_R = crate::BitReader; +pub type INT5_R = crate::BitReader; #[doc = "Field `INT5` writer - Interrupt 5"] -pub type INT5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT6` reader - Interrupt 6"] -pub type INT6_R = crate::BitReader; +pub type INT6_R = crate::BitReader; #[doc = "Field `INT6` writer - Interrupt 6"] -pub type INT6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT7` reader - Interrupt 7"] -pub type INT7_R = crate::BitReader; +pub type INT7_R = crate::BitReader; #[doc = "Field `INT7` writer - Interrupt 7"] -pub type INT7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT8` reader - Interrupt 8"] -pub type INT8_R = crate::BitReader; +pub type INT8_R = crate::BitReader; #[doc = "Field `INT8` writer - Interrupt 8"] -pub type INT8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT9` reader - Interrupt 9"] -pub type INT9_R = crate::BitReader; +pub type INT9_R = crate::BitReader; #[doc = "Field `INT9` writer - Interrupt 9"] -pub type INT9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT9_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT10` reader - Interrupt 10"] -pub type INT10_R = crate::BitReader; +pub type INT10_R = crate::BitReader; #[doc = "Field `INT10` writer - Interrupt 10"] -pub type INT10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT11` reader - Interrupt 11"] -pub type INT11_R = crate::BitReader; +pub type INT11_R = crate::BitReader; #[doc = "Field `INT11` writer - Interrupt 11"] -pub type INT11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT12` reader - Interrupt 12"] -pub type INT12_R = crate::BitReader; +pub type INT12_R = crate::BitReader; #[doc = "Field `INT12` writer - Interrupt 12"] -pub type INT12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT13` reader - Interrupt 13"] -pub type INT13_R = crate::BitReader; +pub type INT13_R = crate::BitReader; #[doc = "Field `INT13` writer - Interrupt 13"] -pub type INT13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT14` reader - Interrupt 14"] -pub type INT14_R = crate::BitReader; +pub type INT14_R = crate::BitReader; #[doc = "Field `INT14` writer - Interrupt 14"] -pub type INT14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT15` reader - Interrupt 15"] -pub type INT15_R = crate::BitReader; +pub type INT15_R = crate::BitReader; #[doc = "Field `INT15` writer - Interrupt 15"] -pub type INT15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT16` reader - Interrupt 16"] -pub type INT16_R = crate::BitReader; +pub type INT16_R = crate::BitReader; #[doc = "Field `INT16` writer - Interrupt 16"] -pub type INT16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT16_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT17` reader - Interrupt 17"] -pub type INT17_R = crate::BitReader; +pub type INT17_R = crate::BitReader; #[doc = "Field `INT17` writer - Interrupt 17"] -pub type INT17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT17_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT18` reader - Interrupt 18"] -pub type INT18_R = crate::BitReader; +pub type INT18_R = crate::BitReader; #[doc = "Field `INT18` writer - Interrupt 18"] -pub type INT18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT18_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT19` reader - Interrupt 19"] -pub type INT19_R = crate::BitReader; +pub type INT19_R = crate::BitReader; #[doc = "Field `INT19` writer - Interrupt 19"] -pub type INT19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT19_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT20` reader - Interrupt 20"] -pub type INT20_R = crate::BitReader; +pub type INT20_R = crate::BitReader; #[doc = "Field `INT20` writer - Interrupt 20"] -pub type INT20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT20_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT21` reader - Interrupt 21"] -pub type INT21_R = crate::BitReader; +pub type INT21_R = crate::BitReader; #[doc = "Field `INT21` writer - Interrupt 21"] -pub type INT21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT21_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT22` reader - Interrupt 22"] -pub type INT22_R = crate::BitReader; +pub type INT22_R = crate::BitReader; #[doc = "Field `INT22` writer - Interrupt 22"] -pub type INT22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT22_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT23` reader - Interrupt 23"] -pub type INT23_R = crate::BitReader; +pub type INT23_R = crate::BitReader; #[doc = "Field `INT23` writer - Interrupt 23"] -pub type INT23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT23_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT24` reader - Interrupt 24"] -pub type INT24_R = crate::BitReader; +pub type INT24_R = crate::BitReader; #[doc = "Field `INT24` writer - Interrupt 24"] -pub type INT24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT24_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT25` reader - Interrupt 25"] -pub type INT25_R = crate::BitReader; +pub type INT25_R = crate::BitReader; #[doc = "Field `INT25` writer - Interrupt 25"] -pub type INT25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT25_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT26` reader - Interrupt 26"] -pub type INT26_R = crate::BitReader; +pub type INT26_R = crate::BitReader; #[doc = "Field `INT26` writer - Interrupt 26"] -pub type INT26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT26_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT27` reader - Interrupt 27"] -pub type INT27_R = crate::BitReader; +pub type INT27_R = crate::BitReader; #[doc = "Field `INT27` writer - Interrupt 27"] -pub type INT27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT27_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT28` reader - Interrupt 28"] -pub type INT28_R = crate::BitReader; +pub type INT28_R = crate::BitReader; #[doc = "Field `INT28` writer - Interrupt 28"] -pub type INT28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT28_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT29` reader - Interrupt 29"] -pub type INT29_R = crate::BitReader; +pub type INT29_R = crate::BitReader; #[doc = "Field `INT29` writer - Interrupt 29"] -pub type INT29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT29_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT30` reader - Interrupt 30"] -pub type INT30_R = crate::BitReader; +pub type INT30_R = crate::BitReader; #[doc = "Field `INT30` writer - Interrupt 30"] -pub type INT30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT30_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT31` reader - Interrupt 31"] -pub type INT31_R = crate::BitReader; +pub type INT31_R = crate::BitReader; #[doc = "Field `INT31` writer - Interrupt 31"] -pub type INT31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER0_SPEC, bool, O>; +pub type INT31_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICACTIVER0") + .field("int0", &format_args!("{}", self.int0().bit())) + .field("int1", &format_args!("{}", self.int1().bit())) + .field("int2", &format_args!("{}", self.int2().bit())) + .field("int3", &format_args!("{}", self.int3().bit())) + .field("int4", &format_args!("{}", self.int4().bit())) + .field("int5", &format_args!("{}", self.int5().bit())) + .field("int6", &format_args!("{}", self.int6().bit())) + .field("int7", &format_args!("{}", self.int7().bit())) + .field("int8", &format_args!("{}", self.int8().bit())) + .field("int9", &format_args!("{}", self.int9().bit())) + .field("int10", &format_args!("{}", self.int10().bit())) + .field("int11", &format_args!("{}", self.int11().bit())) + .field("int12", &format_args!("{}", self.int12().bit())) + .field("int13", &format_args!("{}", self.int13().bit())) + .field("int14", &format_args!("{}", self.int14().bit())) + .field("int15", &format_args!("{}", self.int15().bit())) + .field("int16", &format_args!("{}", self.int16().bit())) + .field("int17", &format_args!("{}", self.int17().bit())) + .field("int18", &format_args!("{}", self.int18().bit())) + .field("int19", &format_args!("{}", self.int19().bit())) + .field("int20", &format_args!("{}", self.int20().bit())) + .field("int21", &format_args!("{}", self.int21().bit())) + .field("int22", &format_args!("{}", self.int22().bit())) + .field("int23", &format_args!("{}", self.int23().bit())) + .field("int24", &format_args!("{}", self.int24().bit())) + .field("int25", &format_args!("{}", self.int25().bit())) + .field("int26", &format_args!("{}", self.int26().bit())) + .field("int27", &format_args!("{}", self.int27().bit())) + .field("int28", &format_args!("{}", self.int28().bit())) + .field("int29", &format_args!("{}", self.int29().bit())) + .field("int30", &format_args!("{}", self.int30().bit())) + .field("int31", &format_args!("{}", self.int31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] #[must_use] - pub fn int0(&mut self) -> INT0_W<0> { + pub fn int0(&mut self) -> INT0_W { INT0_W::new(self) } #[doc = "Bit 1 - Interrupt 1"] #[inline(always)] #[must_use] - pub fn int1(&mut self) -> INT1_W<1> { + pub fn int1(&mut self) -> INT1_W { INT1_W::new(self) } #[doc = "Bit 2 - Interrupt 2"] #[inline(always)] #[must_use] - pub fn int2(&mut self) -> INT2_W<2> { + pub fn int2(&mut self) -> INT2_W { INT2_W::new(self) } #[doc = "Bit 3 - Interrupt 3"] #[inline(always)] #[must_use] - pub fn int3(&mut self) -> INT3_W<3> { + pub fn int3(&mut self) -> INT3_W { INT3_W::new(self) } #[doc = "Bit 4 - Interrupt 4"] #[inline(always)] #[must_use] - pub fn int4(&mut self) -> INT4_W<4> { + pub fn int4(&mut self) -> INT4_W { INT4_W::new(self) } #[doc = "Bit 5 - Interrupt 5"] #[inline(always)] #[must_use] - pub fn int5(&mut self) -> INT5_W<5> { + pub fn int5(&mut self) -> INT5_W { INT5_W::new(self) } #[doc = "Bit 6 - Interrupt 6"] #[inline(always)] #[must_use] - pub fn int6(&mut self) -> INT6_W<6> { + pub fn int6(&mut self) -> INT6_W { INT6_W::new(self) } #[doc = "Bit 7 - Interrupt 7"] #[inline(always)] #[must_use] - pub fn int7(&mut self) -> INT7_W<7> { + pub fn int7(&mut self) -> INT7_W { INT7_W::new(self) } #[doc = "Bit 8 - Interrupt 8"] #[inline(always)] #[must_use] - pub fn int8(&mut self) -> INT8_W<8> { + pub fn int8(&mut self) -> INT8_W { INT8_W::new(self) } #[doc = "Bit 9 - Interrupt 9"] #[inline(always)] #[must_use] - pub fn int9(&mut self) -> INT9_W<9> { + pub fn int9(&mut self) -> INT9_W { INT9_W::new(self) } #[doc = "Bit 10 - Interrupt 10"] #[inline(always)] #[must_use] - pub fn int10(&mut self) -> INT10_W<10> { + pub fn int10(&mut self) -> INT10_W { INT10_W::new(self) } #[doc = "Bit 11 - Interrupt 11"] #[inline(always)] #[must_use] - pub fn int11(&mut self) -> INT11_W<11> { + pub fn int11(&mut self) -> INT11_W { INT11_W::new(self) } #[doc = "Bit 12 - Interrupt 12"] #[inline(always)] #[must_use] - pub fn int12(&mut self) -> INT12_W<12> { + pub fn int12(&mut self) -> INT12_W { INT12_W::new(self) } #[doc = "Bit 13 - Interrupt 13"] #[inline(always)] #[must_use] - pub fn int13(&mut self) -> INT13_W<13> { + pub fn int13(&mut self) -> INT13_W { INT13_W::new(self) } #[doc = "Bit 14 - Interrupt 14"] #[inline(always)] #[must_use] - pub fn int14(&mut self) -> INT14_W<14> { + pub fn int14(&mut self) -> INT14_W { INT14_W::new(self) } #[doc = "Bit 15 - Interrupt 15"] #[inline(always)] #[must_use] - pub fn int15(&mut self) -> INT15_W<15> { + pub fn int15(&mut self) -> INT15_W { INT15_W::new(self) } #[doc = "Bit 16 - Interrupt 16"] #[inline(always)] #[must_use] - pub fn int16(&mut self) -> INT16_W<16> { + pub fn int16(&mut self) -> INT16_W { INT16_W::new(self) } #[doc = "Bit 17 - Interrupt 17"] #[inline(always)] #[must_use] - pub fn int17(&mut self) -> INT17_W<17> { + pub fn int17(&mut self) -> INT17_W { INT17_W::new(self) } #[doc = "Bit 18 - Interrupt 18"] #[inline(always)] #[must_use] - pub fn int18(&mut self) -> INT18_W<18> { + pub fn int18(&mut self) -> INT18_W { INT18_W::new(self) } #[doc = "Bit 19 - Interrupt 19"] #[inline(always)] #[must_use] - pub fn int19(&mut self) -> INT19_W<19> { + pub fn int19(&mut self) -> INT19_W { INT19_W::new(self) } #[doc = "Bit 20 - Interrupt 20"] #[inline(always)] #[must_use] - pub fn int20(&mut self) -> INT20_W<20> { + pub fn int20(&mut self) -> INT20_W { INT20_W::new(self) } #[doc = "Bit 21 - Interrupt 21"] #[inline(always)] #[must_use] - pub fn int21(&mut self) -> INT21_W<21> { + pub fn int21(&mut self) -> INT21_W { INT21_W::new(self) } #[doc = "Bit 22 - Interrupt 22"] #[inline(always)] #[must_use] - pub fn int22(&mut self) -> INT22_W<22> { + pub fn int22(&mut self) -> INT22_W { INT22_W::new(self) } #[doc = "Bit 23 - Interrupt 23"] #[inline(always)] #[must_use] - pub fn int23(&mut self) -> INT23_W<23> { + pub fn int23(&mut self) -> INT23_W { INT23_W::new(self) } #[doc = "Bit 24 - Interrupt 24"] #[inline(always)] #[must_use] - pub fn int24(&mut self) -> INT24_W<24> { + pub fn int24(&mut self) -> INT24_W { INT24_W::new(self) } #[doc = "Bit 25 - Interrupt 25"] #[inline(always)] #[must_use] - pub fn int25(&mut self) -> INT25_W<25> { + pub fn int25(&mut self) -> INT25_W { INT25_W::new(self) } #[doc = "Bit 26 - Interrupt 26"] #[inline(always)] #[must_use] - pub fn int26(&mut self) -> INT26_W<26> { + pub fn int26(&mut self) -> INT26_W { INT26_W::new(self) } #[doc = "Bit 27 - Interrupt 27"] #[inline(always)] #[must_use] - pub fn int27(&mut self) -> INT27_W<27> { + pub fn int27(&mut self) -> INT27_W { INT27_W::new(self) } #[doc = "Bit 28 - Interrupt 28"] #[inline(always)] #[must_use] - pub fn int28(&mut self) -> INT28_W<28> { + pub fn int28(&mut self) -> INT28_W { INT28_W::new(self) } #[doc = "Bit 29 - Interrupt 29"] #[inline(always)] #[must_use] - pub fn int29(&mut self) -> INT29_W<29> { + pub fn int29(&mut self) -> INT29_W { INT29_W::new(self) } #[doc = "Bit 30 - Interrupt 30"] #[inline(always)] #[must_use] - pub fn int30(&mut self) -> INT30_W<30> { + pub fn int30(&mut self) -> INT30_W { INT30_W::new(self) } #[doc = "Bit 31 - Interrupt 31"] #[inline(always)] #[must_use] - pub fn int31(&mut self) -> INT31_W<31> { + pub fn int31(&mut self) -> INT31_W { INT31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver0](index.html) module"] +#[doc = "Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICACTIVER0_SPEC; impl crate::RegisterSpec for GICD_ICACTIVER0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icactiver0::R](R) reader structure"] -impl crate::Readable for GICD_ICACTIVER0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icactiver0::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icactiver0::R`](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icactiver0::W`](W) writer structure"] impl crate::Writable for GICD_ICACTIVER0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver1.rs index f5e8549..bdcfea4 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver1.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver1.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ICACTIVER1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICACTIVER1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT32` reader - Interrupt 32"] -pub type INT32_R = crate::BitReader; +pub type INT32_R = crate::BitReader; #[doc = "Field `INT32` writer - Interrupt 32"] -pub type INT32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT32_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT33` reader - Interrupt 33"] -pub type INT33_R = crate::BitReader; +pub type INT33_R = crate::BitReader; #[doc = "Field `INT33` writer - Interrupt 33"] -pub type INT33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT33_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT34` reader - Interrupt 34"] -pub type INT34_R = crate::BitReader; +pub type INT34_R = crate::BitReader; #[doc = "Field `INT34` writer - Interrupt 34"] -pub type INT34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT34_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT35` reader - Interrupt 35"] -pub type INT35_R = crate::BitReader; +pub type INT35_R = crate::BitReader; #[doc = "Field `INT35` writer - Interrupt 35"] -pub type INT35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT35_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT36` reader - Interrupt 36"] -pub type INT36_R = crate::BitReader; +pub type INT36_R = crate::BitReader; #[doc = "Field `INT36` writer - Interrupt 36"] -pub type INT36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT36_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT37` reader - Interrupt 37"] -pub type INT37_R = crate::BitReader; +pub type INT37_R = crate::BitReader; #[doc = "Field `INT37` writer - Interrupt 37"] -pub type INT37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT37_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT38` reader - Interrupt 38"] -pub type INT38_R = crate::BitReader; +pub type INT38_R = crate::BitReader; #[doc = "Field `INT38` writer - Interrupt 38"] -pub type INT38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT38_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT39` reader - Interrupt 39"] -pub type INT39_R = crate::BitReader; +pub type INT39_R = crate::BitReader; #[doc = "Field `INT39` writer - Interrupt 39"] -pub type INT39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT39_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT40` reader - Interrupt 40"] -pub type INT40_R = crate::BitReader; +pub type INT40_R = crate::BitReader; #[doc = "Field `INT40` writer - Interrupt 40"] -pub type INT40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT40_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT41` reader - Interrupt 41"] -pub type INT41_R = crate::BitReader; +pub type INT41_R = crate::BitReader; #[doc = "Field `INT41` writer - Interrupt 41"] -pub type INT41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT41_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT42` reader - Interrupt 42"] -pub type INT42_R = crate::BitReader; +pub type INT42_R = crate::BitReader; #[doc = "Field `INT42` writer - Interrupt 42"] -pub type INT42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT42_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT43` reader - Interrupt 43"] -pub type INT43_R = crate::BitReader; +pub type INT43_R = crate::BitReader; #[doc = "Field `INT43` writer - Interrupt 43"] -pub type INT43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT43_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT44` reader - Interrupt 44"] -pub type INT44_R = crate::BitReader; +pub type INT44_R = crate::BitReader; #[doc = "Field `INT44` writer - Interrupt 44"] -pub type INT44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT44_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT45` reader - Interrupt 45"] -pub type INT45_R = crate::BitReader; +pub type INT45_R = crate::BitReader; #[doc = "Field `INT45` writer - Interrupt 45"] -pub type INT45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT45_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT46` reader - Interrupt 46"] -pub type INT46_R = crate::BitReader; +pub type INT46_R = crate::BitReader; #[doc = "Field `INT46` writer - Interrupt 46"] -pub type INT46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT46_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT47` reader - Interrupt 47"] -pub type INT47_R = crate::BitReader; +pub type INT47_R = crate::BitReader; #[doc = "Field `INT47` writer - Interrupt 47"] -pub type INT47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT47_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT48` reader - Interrupt 48"] -pub type INT48_R = crate::BitReader; +pub type INT48_R = crate::BitReader; #[doc = "Field `INT48` writer - Interrupt 48"] -pub type INT48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT48_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT49` reader - Interrupt 49"] -pub type INT49_R = crate::BitReader; +pub type INT49_R = crate::BitReader; #[doc = "Field `INT49` writer - Interrupt 49"] -pub type INT49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT49_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT50` reader - Interrupt 50"] -pub type INT50_R = crate::BitReader; +pub type INT50_R = crate::BitReader; #[doc = "Field `INT50` writer - Interrupt 50"] -pub type INT50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT50_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT51` reader - Interrupt 51"] -pub type INT51_R = crate::BitReader; +pub type INT51_R = crate::BitReader; #[doc = "Field `INT51` writer - Interrupt 51"] -pub type INT51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT51_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT52` reader - Interrupt 52"] -pub type INT52_R = crate::BitReader; +pub type INT52_R = crate::BitReader; #[doc = "Field `INT52` writer - Interrupt 52"] -pub type INT52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT52_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT53` reader - Interrupt 53"] -pub type INT53_R = crate::BitReader; +pub type INT53_R = crate::BitReader; #[doc = "Field `INT53` writer - Interrupt 53"] -pub type INT53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT53_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT54` reader - Interrupt 54"] -pub type INT54_R = crate::BitReader; +pub type INT54_R = crate::BitReader; #[doc = "Field `INT54` writer - Interrupt 54"] -pub type INT54_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT54_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT55` reader - Interrupt 55"] -pub type INT55_R = crate::BitReader; +pub type INT55_R = crate::BitReader; #[doc = "Field `INT55` writer - Interrupt 55"] -pub type INT55_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT55_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT56` reader - Interrupt 56"] -pub type INT56_R = crate::BitReader; +pub type INT56_R = crate::BitReader; #[doc = "Field `INT56` writer - Interrupt 56"] -pub type INT56_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT56_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT57` reader - Interrupt 57"] -pub type INT57_R = crate::BitReader; +pub type INT57_R = crate::BitReader; #[doc = "Field `INT57` writer - Interrupt 57"] -pub type INT57_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT57_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT58` reader - Interrupt 58"] -pub type INT58_R = crate::BitReader; +pub type INT58_R = crate::BitReader; #[doc = "Field `INT58` writer - Interrupt 58"] -pub type INT58_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT58_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT59` reader - Interrupt 59"] -pub type INT59_R = crate::BitReader; +pub type INT59_R = crate::BitReader; #[doc = "Field `INT59` writer - Interrupt 59"] -pub type INT59_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT59_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT60` reader - Interrupt 60"] -pub type INT60_R = crate::BitReader; +pub type INT60_R = crate::BitReader; #[doc = "Field `INT60` writer - Interrupt 60"] -pub type INT60_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT60_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT61` reader - Interrupt 61"] -pub type INT61_R = crate::BitReader; +pub type INT61_R = crate::BitReader; #[doc = "Field `INT61` writer - Interrupt 61"] -pub type INT61_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT61_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT62` reader - Interrupt 62"] -pub type INT62_R = crate::BitReader; +pub type INT62_R = crate::BitReader; #[doc = "Field `INT62` writer - Interrupt 62"] -pub type INT62_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT62_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT63` reader - Interrupt 63"] -pub type INT63_R = crate::BitReader; +pub type INT63_R = crate::BitReader; #[doc = "Field `INT63` writer - Interrupt 63"] -pub type INT63_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER1_SPEC, bool, O>; +pub type INT63_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT63_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICACTIVER1") + .field("int32", &format_args!("{}", self.int32().bit())) + .field("int33", &format_args!("{}", self.int33().bit())) + .field("int34", &format_args!("{}", self.int34().bit())) + .field("int35", &format_args!("{}", self.int35().bit())) + .field("int36", &format_args!("{}", self.int36().bit())) + .field("int37", &format_args!("{}", self.int37().bit())) + .field("int38", &format_args!("{}", self.int38().bit())) + .field("int39", &format_args!("{}", self.int39().bit())) + .field("int40", &format_args!("{}", self.int40().bit())) + .field("int41", &format_args!("{}", self.int41().bit())) + .field("int42", &format_args!("{}", self.int42().bit())) + .field("int43", &format_args!("{}", self.int43().bit())) + .field("int44", &format_args!("{}", self.int44().bit())) + .field("int45", &format_args!("{}", self.int45().bit())) + .field("int46", &format_args!("{}", self.int46().bit())) + .field("int47", &format_args!("{}", self.int47().bit())) + .field("int48", &format_args!("{}", self.int48().bit())) + .field("int49", &format_args!("{}", self.int49().bit())) + .field("int50", &format_args!("{}", self.int50().bit())) + .field("int51", &format_args!("{}", self.int51().bit())) + .field("int52", &format_args!("{}", self.int52().bit())) + .field("int53", &format_args!("{}", self.int53().bit())) + .field("int54", &format_args!("{}", self.int54().bit())) + .field("int55", &format_args!("{}", self.int55().bit())) + .field("int56", &format_args!("{}", self.int56().bit())) + .field("int57", &format_args!("{}", self.int57().bit())) + .field("int58", &format_args!("{}", self.int58().bit())) + .field("int59", &format_args!("{}", self.int59().bit())) + .field("int60", &format_args!("{}", self.int60().bit())) + .field("int61", &format_args!("{}", self.int61().bit())) + .field("int62", &format_args!("{}", self.int62().bit())) + .field("int63", &format_args!("{}", self.int63().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] #[must_use] - pub fn int32(&mut self) -> INT32_W<0> { + pub fn int32(&mut self) -> INT32_W { INT32_W::new(self) } #[doc = "Bit 1 - Interrupt 33"] #[inline(always)] #[must_use] - pub fn int33(&mut self) -> INT33_W<1> { + pub fn int33(&mut self) -> INT33_W { INT33_W::new(self) } #[doc = "Bit 2 - Interrupt 34"] #[inline(always)] #[must_use] - pub fn int34(&mut self) -> INT34_W<2> { + pub fn int34(&mut self) -> INT34_W { INT34_W::new(self) } #[doc = "Bit 3 - Interrupt 35"] #[inline(always)] #[must_use] - pub fn int35(&mut self) -> INT35_W<3> { + pub fn int35(&mut self) -> INT35_W { INT35_W::new(self) } #[doc = "Bit 4 - Interrupt 36"] #[inline(always)] #[must_use] - pub fn int36(&mut self) -> INT36_W<4> { + pub fn int36(&mut self) -> INT36_W { INT36_W::new(self) } #[doc = "Bit 5 - Interrupt 37"] #[inline(always)] #[must_use] - pub fn int37(&mut self) -> INT37_W<5> { + pub fn int37(&mut self) -> INT37_W { INT37_W::new(self) } #[doc = "Bit 6 - Interrupt 38"] #[inline(always)] #[must_use] - pub fn int38(&mut self) -> INT38_W<6> { + pub fn int38(&mut self) -> INT38_W { INT38_W::new(self) } #[doc = "Bit 7 - Interrupt 39"] #[inline(always)] #[must_use] - pub fn int39(&mut self) -> INT39_W<7> { + pub fn int39(&mut self) -> INT39_W { INT39_W::new(self) } #[doc = "Bit 8 - Interrupt 40"] #[inline(always)] #[must_use] - pub fn int40(&mut self) -> INT40_W<8> { + pub fn int40(&mut self) -> INT40_W { INT40_W::new(self) } #[doc = "Bit 9 - Interrupt 41"] #[inline(always)] #[must_use] - pub fn int41(&mut self) -> INT41_W<9> { + pub fn int41(&mut self) -> INT41_W { INT41_W::new(self) } #[doc = "Bit 10 - Interrupt 42"] #[inline(always)] #[must_use] - pub fn int42(&mut self) -> INT42_W<10> { + pub fn int42(&mut self) -> INT42_W { INT42_W::new(self) } #[doc = "Bit 11 - Interrupt 43"] #[inline(always)] #[must_use] - pub fn int43(&mut self) -> INT43_W<11> { + pub fn int43(&mut self) -> INT43_W { INT43_W::new(self) } #[doc = "Bit 12 - Interrupt 44"] #[inline(always)] #[must_use] - pub fn int44(&mut self) -> INT44_W<12> { + pub fn int44(&mut self) -> INT44_W { INT44_W::new(self) } #[doc = "Bit 13 - Interrupt 45"] #[inline(always)] #[must_use] - pub fn int45(&mut self) -> INT45_W<13> { + pub fn int45(&mut self) -> INT45_W { INT45_W::new(self) } #[doc = "Bit 14 - Interrupt 46"] #[inline(always)] #[must_use] - pub fn int46(&mut self) -> INT46_W<14> { + pub fn int46(&mut self) -> INT46_W { INT46_W::new(self) } #[doc = "Bit 15 - Interrupt 47"] #[inline(always)] #[must_use] - pub fn int47(&mut self) -> INT47_W<15> { + pub fn int47(&mut self) -> INT47_W { INT47_W::new(self) } #[doc = "Bit 16 - Interrupt 48"] #[inline(always)] #[must_use] - pub fn int48(&mut self) -> INT48_W<16> { + pub fn int48(&mut self) -> INT48_W { INT48_W::new(self) } #[doc = "Bit 17 - Interrupt 49"] #[inline(always)] #[must_use] - pub fn int49(&mut self) -> INT49_W<17> { + pub fn int49(&mut self) -> INT49_W { INT49_W::new(self) } #[doc = "Bit 18 - Interrupt 50"] #[inline(always)] #[must_use] - pub fn int50(&mut self) -> INT50_W<18> { + pub fn int50(&mut self) -> INT50_W { INT50_W::new(self) } #[doc = "Bit 19 - Interrupt 51"] #[inline(always)] #[must_use] - pub fn int51(&mut self) -> INT51_W<19> { + pub fn int51(&mut self) -> INT51_W { INT51_W::new(self) } #[doc = "Bit 20 - Interrupt 52"] #[inline(always)] #[must_use] - pub fn int52(&mut self) -> INT52_W<20> { + pub fn int52(&mut self) -> INT52_W { INT52_W::new(self) } #[doc = "Bit 21 - Interrupt 53"] #[inline(always)] #[must_use] - pub fn int53(&mut self) -> INT53_W<21> { + pub fn int53(&mut self) -> INT53_W { INT53_W::new(self) } #[doc = "Bit 22 - Interrupt 54"] #[inline(always)] #[must_use] - pub fn int54(&mut self) -> INT54_W<22> { + pub fn int54(&mut self) -> INT54_W { INT54_W::new(self) } #[doc = "Bit 23 - Interrupt 55"] #[inline(always)] #[must_use] - pub fn int55(&mut self) -> INT55_W<23> { + pub fn int55(&mut self) -> INT55_W { INT55_W::new(self) } #[doc = "Bit 24 - Interrupt 56"] #[inline(always)] #[must_use] - pub fn int56(&mut self) -> INT56_W<24> { + pub fn int56(&mut self) -> INT56_W { INT56_W::new(self) } #[doc = "Bit 25 - Interrupt 57"] #[inline(always)] #[must_use] - pub fn int57(&mut self) -> INT57_W<25> { + pub fn int57(&mut self) -> INT57_W { INT57_W::new(self) } #[doc = "Bit 26 - Interrupt 58"] #[inline(always)] #[must_use] - pub fn int58(&mut self) -> INT58_W<26> { + pub fn int58(&mut self) -> INT58_W { INT58_W::new(self) } #[doc = "Bit 27 - Interrupt 59"] #[inline(always)] #[must_use] - pub fn int59(&mut self) -> INT59_W<27> { + pub fn int59(&mut self) -> INT59_W { INT59_W::new(self) } #[doc = "Bit 28 - Interrupt 60"] #[inline(always)] #[must_use] - pub fn int60(&mut self) -> INT60_W<28> { + pub fn int60(&mut self) -> INT60_W { INT60_W::new(self) } #[doc = "Bit 29 - Interrupt 61"] #[inline(always)] #[must_use] - pub fn int61(&mut self) -> INT61_W<29> { + pub fn int61(&mut self) -> INT61_W { INT61_W::new(self) } #[doc = "Bit 30 - Interrupt 62"] #[inline(always)] #[must_use] - pub fn int62(&mut self) -> INT62_W<30> { + pub fn int62(&mut self) -> INT62_W { INT62_W::new(self) } #[doc = "Bit 31 - Interrupt 63"] #[inline(always)] #[must_use] - pub fn int63(&mut self) -> INT63_W<31> { + pub fn int63(&mut self) -> INT63_W { INT63_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver1](index.html) module"] +#[doc = "Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICACTIVER1_SPEC; impl crate::RegisterSpec for GICD_ICACTIVER1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icactiver1::R](R) reader structure"] -impl crate::Readable for GICD_ICACTIVER1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icactiver1::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icactiver1::R`](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icactiver1::W`](W) writer structure"] impl crate::Writable for GICD_ICACTIVER1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver2.rs index 7c0da7f..1d4be44 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver2.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver2.rs @@ -1,171 +1,135 @@ #[doc = "Register `GICD_ICACTIVER2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICACTIVER2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI0` reader - Software interrupt 0"] -pub type SWI0_R = crate::BitReader; +pub type SWI0_R = crate::BitReader; #[doc = "Field `SWI0` writer - Software interrupt 0"] -pub type SWI0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type SWI0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI1` reader - Software interrupt 1"] -pub type SWI1_R = crate::BitReader; +pub type SWI1_R = crate::BitReader; #[doc = "Field `SWI1` writer - Software interrupt 1"] -pub type SWI1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type SWI1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI2` reader - Software interrupt 2"] -pub type SWI2_R = crate::BitReader; +pub type SWI2_R = crate::BitReader; #[doc = "Field `SWI2` writer - Software interrupt 2"] -pub type SWI2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type SWI2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI3` reader - Software interrupt 3"] -pub type SWI3_R = crate::BitReader; +pub type SWI3_R = crate::BitReader; #[doc = "Field `SWI3` writer - Software interrupt 3"] -pub type SWI3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type SWI3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI4` reader - Software interrupt 4"] -pub type SWI4_R = crate::BitReader; +pub type SWI4_R = crate::BitReader; #[doc = "Field `SWI4` writer - Software interrupt 4"] -pub type SWI4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type SWI4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI5` reader - Software interrupt 5"] -pub type SWI5_R = crate::BitReader; +pub type SWI5_R = crate::BitReader; #[doc = "Field `SWI5` writer - Software interrupt 5"] -pub type SWI5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type SWI5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI6` reader - Software interrupt 6"] -pub type SWI6_R = crate::BitReader; +pub type SWI6_R = crate::BitReader; #[doc = "Field `SWI6` writer - Software interrupt 6"] -pub type SWI6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type SWI6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI7` reader - Software interrupt 7"] -pub type SWI7_R = crate::BitReader; +pub type SWI7_R = crate::BitReader; #[doc = "Field `SWI7` writer - Software interrupt 7"] -pub type SWI7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type SWI7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT80` reader - Interrupt 80"] -pub type INT80_R = crate::BitReader; +pub type INT80_R = crate::BitReader; #[doc = "Field `INT80` writer - Interrupt 80"] -pub type INT80_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT80_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT81` reader - Interrupt 81"] -pub type INT81_R = crate::BitReader; +pub type INT81_R = crate::BitReader; #[doc = "Field `INT81` writer - Interrupt 81"] -pub type INT81_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT81_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT82` reader - Interrupt 82"] -pub type INT82_R = crate::BitReader; +pub type INT82_R = crate::BitReader; #[doc = "Field `INT82` writer - Interrupt 82"] -pub type INT82_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT82_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT83` reader - Interrupt 83"] -pub type INT83_R = crate::BitReader; +pub type INT83_R = crate::BitReader; #[doc = "Field `INT83` writer - Interrupt 83"] -pub type INT83_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT83_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT84` reader - Interrupt 84"] -pub type INT84_R = crate::BitReader; +pub type INT84_R = crate::BitReader; #[doc = "Field `INT84` writer - Interrupt 84"] -pub type INT84_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT84_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT85` reader - Interrupt 85"] -pub type INT85_R = crate::BitReader; +pub type INT85_R = crate::BitReader; #[doc = "Field `INT85` writer - Interrupt 85"] -pub type INT85_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT85_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT86` reader - Interrupt 86"] -pub type INT86_R = crate::BitReader; +pub type INT86_R = crate::BitReader; #[doc = "Field `INT86` writer - Interrupt 86"] -pub type INT86_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT86_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT87` reader - Interrupt 87"] -pub type INT87_R = crate::BitReader; +pub type INT87_R = crate::BitReader; #[doc = "Field `INT87` writer - Interrupt 87"] -pub type INT87_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT87_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT88` reader - Interrupt 88"] -pub type INT88_R = crate::BitReader; +pub type INT88_R = crate::BitReader; #[doc = "Field `INT88` writer - Interrupt 88"] -pub type INT88_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT88_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT89` reader - Interrupt 89"] -pub type INT89_R = crate::BitReader; +pub type INT89_R = crate::BitReader; #[doc = "Field `INT89` writer - Interrupt 89"] -pub type INT89_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT89_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT90` reader - Interrupt 90"] -pub type INT90_R = crate::BitReader; +pub type INT90_R = crate::BitReader; #[doc = "Field `INT90` writer - Interrupt 90"] -pub type INT90_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT90_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT91` reader - Interrupt 91"] -pub type INT91_R = crate::BitReader; +pub type INT91_R = crate::BitReader; #[doc = "Field `INT91` writer - Interrupt 91"] -pub type INT91_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT91_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT92` reader - Interrupt 92"] -pub type INT92_R = crate::BitReader; +pub type INT92_R = crate::BitReader; #[doc = "Field `INT92` writer - Interrupt 92"] -pub type INT92_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT92_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT93` reader - Interrupt 93"] -pub type INT93_R = crate::BitReader; +pub type INT93_R = crate::BitReader; #[doc = "Field `INT93` writer - Interrupt 93"] -pub type INT93_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT93_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT94` reader - Interrupt 94"] -pub type INT94_R = crate::BitReader; +pub type INT94_R = crate::BitReader; #[doc = "Field `INT94` writer - Interrupt 94"] -pub type INT94_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT94_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT95` reader - Interrupt 95"] -pub type INT95_R = crate::BitReader; +pub type INT95_R = crate::BitReader; #[doc = "Field `INT95` writer - Interrupt 95"] -pub type INT95_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER2_SPEC, bool, O>; +pub type INT95_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -328,218 +292,268 @@ impl R { INT95_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICACTIVER2") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .field("swi0", &format_args!("{}", self.swi0().bit())) + .field("swi1", &format_args!("{}", self.swi1().bit())) + .field("swi2", &format_args!("{}", self.swi2().bit())) + .field("swi3", &format_args!("{}", self.swi3().bit())) + .field("swi4", &format_args!("{}", self.swi4().bit())) + .field("swi5", &format_args!("{}", self.swi5().bit())) + .field("swi6", &format_args!("{}", self.swi6().bit())) + .field("swi7", &format_args!("{}", self.swi7().bit())) + .field("int80", &format_args!("{}", self.int80().bit())) + .field("int81", &format_args!("{}", self.int81().bit())) + .field("int82", &format_args!("{}", self.int82().bit())) + .field("int83", &format_args!("{}", self.int83().bit())) + .field("int84", &format_args!("{}", self.int84().bit())) + .field("int85", &format_args!("{}", self.int85().bit())) + .field("int86", &format_args!("{}", self.int86().bit())) + .field("int87", &format_args!("{}", self.int87().bit())) + .field("int88", &format_args!("{}", self.int88().bit())) + .field("int89", &format_args!("{}", self.int89().bit())) + .field("int90", &format_args!("{}", self.int90().bit())) + .field("int91", &format_args!("{}", self.int91().bit())) + .field("int92", &format_args!("{}", self.int92().bit())) + .field("int93", &format_args!("{}", self.int93().bit())) + .field("int94", &format_args!("{}", self.int94().bit())) + .field("int95", &format_args!("{}", self.int95().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } #[doc = "Bit 8 - Software interrupt 0"] #[inline(always)] #[must_use] - pub fn swi0(&mut self) -> SWI0_W<8> { + pub fn swi0(&mut self) -> SWI0_W { SWI0_W::new(self) } #[doc = "Bit 9 - Software interrupt 1"] #[inline(always)] #[must_use] - pub fn swi1(&mut self) -> SWI1_W<9> { + pub fn swi1(&mut self) -> SWI1_W { SWI1_W::new(self) } #[doc = "Bit 10 - Software interrupt 2"] #[inline(always)] #[must_use] - pub fn swi2(&mut self) -> SWI2_W<10> { + pub fn swi2(&mut self) -> SWI2_W { SWI2_W::new(self) } #[doc = "Bit 11 - Software interrupt 3"] #[inline(always)] #[must_use] - pub fn swi3(&mut self) -> SWI3_W<11> { + pub fn swi3(&mut self) -> SWI3_W { SWI3_W::new(self) } #[doc = "Bit 12 - Software interrupt 4"] #[inline(always)] #[must_use] - pub fn swi4(&mut self) -> SWI4_W<12> { + pub fn swi4(&mut self) -> SWI4_W { SWI4_W::new(self) } #[doc = "Bit 13 - Software interrupt 5"] #[inline(always)] #[must_use] - pub fn swi5(&mut self) -> SWI5_W<13> { + pub fn swi5(&mut self) -> SWI5_W { SWI5_W::new(self) } #[doc = "Bit 14 - Software interrupt 6"] #[inline(always)] #[must_use] - pub fn swi6(&mut self) -> SWI6_W<14> { + pub fn swi6(&mut self) -> SWI6_W { SWI6_W::new(self) } #[doc = "Bit 15 - Software interrupt 7"] #[inline(always)] #[must_use] - pub fn swi7(&mut self) -> SWI7_W<15> { + pub fn swi7(&mut self) -> SWI7_W { SWI7_W::new(self) } #[doc = "Bit 16 - Interrupt 80"] #[inline(always)] #[must_use] - pub fn int80(&mut self) -> INT80_W<16> { + pub fn int80(&mut self) -> INT80_W { INT80_W::new(self) } #[doc = "Bit 17 - Interrupt 81"] #[inline(always)] #[must_use] - pub fn int81(&mut self) -> INT81_W<17> { + pub fn int81(&mut self) -> INT81_W { INT81_W::new(self) } #[doc = "Bit 18 - Interrupt 82"] #[inline(always)] #[must_use] - pub fn int82(&mut self) -> INT82_W<18> { + pub fn int82(&mut self) -> INT82_W { INT82_W::new(self) } #[doc = "Bit 19 - Interrupt 83"] #[inline(always)] #[must_use] - pub fn int83(&mut self) -> INT83_W<19> { + pub fn int83(&mut self) -> INT83_W { INT83_W::new(self) } #[doc = "Bit 20 - Interrupt 84"] #[inline(always)] #[must_use] - pub fn int84(&mut self) -> INT84_W<20> { + pub fn int84(&mut self) -> INT84_W { INT84_W::new(self) } #[doc = "Bit 21 - Interrupt 85"] #[inline(always)] #[must_use] - pub fn int85(&mut self) -> INT85_W<21> { + pub fn int85(&mut self) -> INT85_W { INT85_W::new(self) } #[doc = "Bit 22 - Interrupt 86"] #[inline(always)] #[must_use] - pub fn int86(&mut self) -> INT86_W<22> { + pub fn int86(&mut self) -> INT86_W { INT86_W::new(self) } #[doc = "Bit 23 - Interrupt 87"] #[inline(always)] #[must_use] - pub fn int87(&mut self) -> INT87_W<23> { + pub fn int87(&mut self) -> INT87_W { INT87_W::new(self) } #[doc = "Bit 24 - Interrupt 88"] #[inline(always)] #[must_use] - pub fn int88(&mut self) -> INT88_W<24> { + pub fn int88(&mut self) -> INT88_W { INT88_W::new(self) } #[doc = "Bit 25 - Interrupt 89"] #[inline(always)] #[must_use] - pub fn int89(&mut self) -> INT89_W<25> { + pub fn int89(&mut self) -> INT89_W { INT89_W::new(self) } #[doc = "Bit 26 - Interrupt 90"] #[inline(always)] #[must_use] - pub fn int90(&mut self) -> INT90_W<26> { + pub fn int90(&mut self) -> INT90_W { INT90_W::new(self) } #[doc = "Bit 27 - Interrupt 91"] #[inline(always)] #[must_use] - pub fn int91(&mut self) -> INT91_W<27> { + pub fn int91(&mut self) -> INT91_W { INT91_W::new(self) } #[doc = "Bit 28 - Interrupt 92"] #[inline(always)] #[must_use] - pub fn int92(&mut self) -> INT92_W<28> { + pub fn int92(&mut self) -> INT92_W { INT92_W::new(self) } #[doc = "Bit 29 - Interrupt 93"] #[inline(always)] #[must_use] - pub fn int93(&mut self) -> INT93_W<29> { + pub fn int93(&mut self) -> INT93_W { INT93_W::new(self) } #[doc = "Bit 30 - Interrupt 94"] #[inline(always)] #[must_use] - pub fn int94(&mut self) -> INT94_W<30> { + pub fn int94(&mut self) -> INT94_W { INT94_W::new(self) } #[doc = "Bit 31 - Interrupt 95"] #[inline(always)] #[must_use] - pub fn int95(&mut self) -> INT95_W<31> { + pub fn int95(&mut self) -> INT95_W { INT95_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver2](index.html) module"] +#[doc = "Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICACTIVER2_SPEC; impl crate::RegisterSpec for GICD_ICACTIVER2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icactiver2::R](R) reader structure"] -impl crate::Readable for GICD_ICACTIVER2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icactiver2::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icactiver2::R`](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icactiver2::W`](W) writer structure"] impl crate::Writable for GICD_ICACTIVER2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver3.rs index d3d5939..6fba2a3 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver3.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver3.rs @@ -1,171 +1,135 @@ #[doc = "Register `GICD_ICACTIVER3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICACTIVER3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER3_SPEC, bool, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -328,218 +292,274 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICACTIVER3") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bit 1 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<1> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bit 2 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<2> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bit 3 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<3> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } #[doc = "Bit 4 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<4> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bit 5 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<5> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bit 6 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<6> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bit 7 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<7> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } #[doc = "Bit 8 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<8> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bit 9 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<9> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 10 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<10> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bit 11 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } #[doc = "Bit 12 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bit 13 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bit 14 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bit 15 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } #[doc = "Bit 16 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<16> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bit 17 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<17> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 18 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<18> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 19 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<19> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 20 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<20> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 21 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<21> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 22 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<22> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 23 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } #[doc = "Bit 24 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bit 25 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<25> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bit 26 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<26> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bit 27 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<27> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } #[doc = "Bit 28 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<28> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<29> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bit 30 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<30> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bit 31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<31> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver3](index.html) module"] +#[doc = "Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICACTIVER3_SPEC; impl crate::RegisterSpec for GICD_ICACTIVER3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icactiver3::R](R) reader structure"] -impl crate::Readable for GICD_ICACTIVER3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icactiver3::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icactiver3::R`](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icactiver3::W`](W) writer structure"] impl crate::Writable for GICD_ICACTIVER3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver4.rs index 29c4093..6d97840 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver4.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver4.rs @@ -1,173 +1,135 @@ #[doc = "Register `GICD_ICACTIVER4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICACTIVER4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type UART_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICACTIVER4_SPEC, bool, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -330,218 +292,280 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICACTIVER4") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bit 1 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<1> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bit 2 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<2> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bit 3 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<3> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } #[doc = "Bit 4 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<4> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bit 5 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bit 6 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bit 7 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } #[doc = "Bit 8 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bit 9 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bit 10 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bit 11 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } #[doc = "Bit 12 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<12> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bit 13 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bit 15 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<15> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } #[doc = "Bit 16 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<16> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bit 17 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bit 18 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bit 19 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } #[doc = "Bit 20 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bit 21 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<21> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bit 22 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<22> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bit 23 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } #[doc = "Bit 24 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<24> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bit 25 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<25> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bit 26 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bit 27 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<27> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } #[doc = "Bit 28 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<28> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bit 29 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<29> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bit 30 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<30> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bit 31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver4](index.html) module"] +#[doc = "Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICACTIVER4_SPEC; impl crate::RegisterSpec for GICD_ICACTIVER4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icactiver4::R](R) reader structure"] -impl crate::Readable for GICD_ICACTIVER4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icactiver4::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icactiver4::R`](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icactiver4::W`](W) writer structure"] impl crate::Writable for GICD_ICACTIVER4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver5.rs index ed5553e..1812c50 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver5.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver5.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ICACTIVER5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICACTIVER5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT160` reader - Interrupt 160"] -pub type INT160_R = crate::BitReader; +pub type INT160_R = crate::BitReader; #[doc = "Field `INT160` writer - Interrupt 160"] -pub type INT160_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT160_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT161` reader - Interrupt 161"] -pub type INT161_R = crate::BitReader; +pub type INT161_R = crate::BitReader; #[doc = "Field `INT161` writer - Interrupt 161"] -pub type INT161_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT161_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT162` reader - Interrupt 162"] -pub type INT162_R = crate::BitReader; +pub type INT162_R = crate::BitReader; #[doc = "Field `INT162` writer - Interrupt 162"] -pub type INT162_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT162_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT163` reader - Interrupt 163"] -pub type INT163_R = crate::BitReader; +pub type INT163_R = crate::BitReader; #[doc = "Field `INT163` writer - Interrupt 163"] -pub type INT163_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT163_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT164` reader - Interrupt 164"] -pub type INT164_R = crate::BitReader; +pub type INT164_R = crate::BitReader; #[doc = "Field `INT164` writer - Interrupt 164"] -pub type INT164_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT164_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT165` reader - Interrupt 165"] -pub type INT165_R = crate::BitReader; +pub type INT165_R = crate::BitReader; #[doc = "Field `INT165` writer - Interrupt 165"] -pub type INT165_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT165_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT166` reader - Interrupt 166"] -pub type INT166_R = crate::BitReader; +pub type INT166_R = crate::BitReader; #[doc = "Field `INT166` writer - Interrupt 166"] -pub type INT166_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT166_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT167` reader - Interrupt 167"] -pub type INT167_R = crate::BitReader; +pub type INT167_R = crate::BitReader; #[doc = "Field `INT167` writer - Interrupt 167"] -pub type INT167_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT167_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT168` reader - Interrupt 168"] -pub type INT168_R = crate::BitReader; +pub type INT168_R = crate::BitReader; #[doc = "Field `INT168` writer - Interrupt 168"] -pub type INT168_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT168_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT169` reader - Interrupt 169"] -pub type INT169_R = crate::BitReader; +pub type INT169_R = crate::BitReader; #[doc = "Field `INT169` writer - Interrupt 169"] -pub type INT169_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT169_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT170` reader - Interrupt 170"] -pub type INT170_R = crate::BitReader; +pub type INT170_R = crate::BitReader; #[doc = "Field `INT170` writer - Interrupt 170"] -pub type INT170_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT170_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT171` reader - Interrupt 171"] -pub type INT171_R = crate::BitReader; +pub type INT171_R = crate::BitReader; #[doc = "Field `INT171` writer - Interrupt 171"] -pub type INT171_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT171_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT172` reader - Interrupt 172"] -pub type INT172_R = crate::BitReader; +pub type INT172_R = crate::BitReader; #[doc = "Field `INT172` writer - Interrupt 172"] -pub type INT172_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT172_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT173` reader - Interrupt 173"] -pub type INT173_R = crate::BitReader; +pub type INT173_R = crate::BitReader; #[doc = "Field `INT173` writer - Interrupt 173"] -pub type INT173_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT173_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT174` reader - Interrupt 174"] -pub type INT174_R = crate::BitReader; +pub type INT174_R = crate::BitReader; #[doc = "Field `INT174` writer - Interrupt 174"] -pub type INT174_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT174_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT175` reader - Interrupt 175"] -pub type INT175_R = crate::BitReader; +pub type INT175_R = crate::BitReader; #[doc = "Field `INT175` writer - Interrupt 175"] -pub type INT175_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT175_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT176` reader - Interrupt 176"] -pub type INT176_R = crate::BitReader; +pub type INT176_R = crate::BitReader; #[doc = "Field `INT176` writer - Interrupt 176"] -pub type INT176_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT176_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT177` reader - Interrupt 177"] -pub type INT177_R = crate::BitReader; +pub type INT177_R = crate::BitReader; #[doc = "Field `INT177` writer - Interrupt 177"] -pub type INT177_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT177_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT178` reader - Interrupt 178"] -pub type INT178_R = crate::BitReader; +pub type INT178_R = crate::BitReader; #[doc = "Field `INT178` writer - Interrupt 178"] -pub type INT178_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT178_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT179` reader - Interrupt 179"] -pub type INT179_R = crate::BitReader; +pub type INT179_R = crate::BitReader; #[doc = "Field `INT179` writer - Interrupt 179"] -pub type INT179_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT179_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT180` reader - Interrupt 180"] -pub type INT180_R = crate::BitReader; +pub type INT180_R = crate::BitReader; #[doc = "Field `INT180` writer - Interrupt 180"] -pub type INT180_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT180_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT181` reader - Interrupt 181"] -pub type INT181_R = crate::BitReader; +pub type INT181_R = crate::BitReader; #[doc = "Field `INT181` writer - Interrupt 181"] -pub type INT181_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT181_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT182` reader - Interrupt 182"] -pub type INT182_R = crate::BitReader; +pub type INT182_R = crate::BitReader; #[doc = "Field `INT182` writer - Interrupt 182"] -pub type INT182_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT182_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT183` reader - Interrupt 183"] -pub type INT183_R = crate::BitReader; +pub type INT183_R = crate::BitReader; #[doc = "Field `INT183` writer - Interrupt 183"] -pub type INT183_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT183_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT184` reader - Interrupt 184"] -pub type INT184_R = crate::BitReader; +pub type INT184_R = crate::BitReader; #[doc = "Field `INT184` writer - Interrupt 184"] -pub type INT184_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT184_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT185` reader - Interrupt 185"] -pub type INT185_R = crate::BitReader; +pub type INT185_R = crate::BitReader; #[doc = "Field `INT185` writer - Interrupt 185"] -pub type INT185_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT185_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT186` reader - Interrupt 186"] -pub type INT186_R = crate::BitReader; +pub type INT186_R = crate::BitReader; #[doc = "Field `INT186` writer - Interrupt 186"] -pub type INT186_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT186_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT187` reader - Interrupt 187"] -pub type INT187_R = crate::BitReader; +pub type INT187_R = crate::BitReader; #[doc = "Field `INT187` writer - Interrupt 187"] -pub type INT187_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT187_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT188` reader - Interrupt 188"] -pub type INT188_R = crate::BitReader; +pub type INT188_R = crate::BitReader; #[doc = "Field `INT188` writer - Interrupt 188"] -pub type INT188_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT188_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT189` reader - Interrupt 189"] -pub type INT189_R = crate::BitReader; +pub type INT189_R = crate::BitReader; #[doc = "Field `INT189` writer - Interrupt 189"] -pub type INT189_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT189_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT190` reader - Interrupt 190"] -pub type INT190_R = crate::BitReader; +pub type INT190_R = crate::BitReader; #[doc = "Field `INT190` writer - Interrupt 190"] -pub type INT190_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT190_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT191` reader - Interrupt 191"] -pub type INT191_R = crate::BitReader; +pub type INT191_R = crate::BitReader; #[doc = "Field `INT191` writer - Interrupt 191"] -pub type INT191_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER5_SPEC, bool, O>; +pub type INT191_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT191_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICACTIVER5") + .field("int160", &format_args!("{}", self.int160().bit())) + .field("int161", &format_args!("{}", self.int161().bit())) + .field("int162", &format_args!("{}", self.int162().bit())) + .field("int163", &format_args!("{}", self.int163().bit())) + .field("int164", &format_args!("{}", self.int164().bit())) + .field("int165", &format_args!("{}", self.int165().bit())) + .field("int166", &format_args!("{}", self.int166().bit())) + .field("int167", &format_args!("{}", self.int167().bit())) + .field("int168", &format_args!("{}", self.int168().bit())) + .field("int169", &format_args!("{}", self.int169().bit())) + .field("int170", &format_args!("{}", self.int170().bit())) + .field("int171", &format_args!("{}", self.int171().bit())) + .field("int172", &format_args!("{}", self.int172().bit())) + .field("int173", &format_args!("{}", self.int173().bit())) + .field("int174", &format_args!("{}", self.int174().bit())) + .field("int175", &format_args!("{}", self.int175().bit())) + .field("int176", &format_args!("{}", self.int176().bit())) + .field("int177", &format_args!("{}", self.int177().bit())) + .field("int178", &format_args!("{}", self.int178().bit())) + .field("int179", &format_args!("{}", self.int179().bit())) + .field("int180", &format_args!("{}", self.int180().bit())) + .field("int181", &format_args!("{}", self.int181().bit())) + .field("int182", &format_args!("{}", self.int182().bit())) + .field("int183", &format_args!("{}", self.int183().bit())) + .field("int184", &format_args!("{}", self.int184().bit())) + .field("int185", &format_args!("{}", self.int185().bit())) + .field("int186", &format_args!("{}", self.int186().bit())) + .field("int187", &format_args!("{}", self.int187().bit())) + .field("int188", &format_args!("{}", self.int188().bit())) + .field("int189", &format_args!("{}", self.int189().bit())) + .field("int190", &format_args!("{}", self.int190().bit())) + .field("int191", &format_args!("{}", self.int191().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] #[must_use] - pub fn int160(&mut self) -> INT160_W<0> { + pub fn int160(&mut self) -> INT160_W { INT160_W::new(self) } #[doc = "Bit 1 - Interrupt 161"] #[inline(always)] #[must_use] - pub fn int161(&mut self) -> INT161_W<1> { + pub fn int161(&mut self) -> INT161_W { INT161_W::new(self) } #[doc = "Bit 2 - Interrupt 162"] #[inline(always)] #[must_use] - pub fn int162(&mut self) -> INT162_W<2> { + pub fn int162(&mut self) -> INT162_W { INT162_W::new(self) } #[doc = "Bit 3 - Interrupt 163"] #[inline(always)] #[must_use] - pub fn int163(&mut self) -> INT163_W<3> { + pub fn int163(&mut self) -> INT163_W { INT163_W::new(self) } #[doc = "Bit 4 - Interrupt 164"] #[inline(always)] #[must_use] - pub fn int164(&mut self) -> INT164_W<4> { + pub fn int164(&mut self) -> INT164_W { INT164_W::new(self) } #[doc = "Bit 5 - Interrupt 165"] #[inline(always)] #[must_use] - pub fn int165(&mut self) -> INT165_W<5> { + pub fn int165(&mut self) -> INT165_W { INT165_W::new(self) } #[doc = "Bit 6 - Interrupt 166"] #[inline(always)] #[must_use] - pub fn int166(&mut self) -> INT166_W<6> { + pub fn int166(&mut self) -> INT166_W { INT166_W::new(self) } #[doc = "Bit 7 - Interrupt 167"] #[inline(always)] #[must_use] - pub fn int167(&mut self) -> INT167_W<7> { + pub fn int167(&mut self) -> INT167_W { INT167_W::new(self) } #[doc = "Bit 8 - Interrupt 168"] #[inline(always)] #[must_use] - pub fn int168(&mut self) -> INT168_W<8> { + pub fn int168(&mut self) -> INT168_W { INT168_W::new(self) } #[doc = "Bit 9 - Interrupt 169"] #[inline(always)] #[must_use] - pub fn int169(&mut self) -> INT169_W<9> { + pub fn int169(&mut self) -> INT169_W { INT169_W::new(self) } #[doc = "Bit 10 - Interrupt 170"] #[inline(always)] #[must_use] - pub fn int170(&mut self) -> INT170_W<10> { + pub fn int170(&mut self) -> INT170_W { INT170_W::new(self) } #[doc = "Bit 11 - Interrupt 171"] #[inline(always)] #[must_use] - pub fn int171(&mut self) -> INT171_W<11> { + pub fn int171(&mut self) -> INT171_W { INT171_W::new(self) } #[doc = "Bit 12 - Interrupt 172"] #[inline(always)] #[must_use] - pub fn int172(&mut self) -> INT172_W<12> { + pub fn int172(&mut self) -> INT172_W { INT172_W::new(self) } #[doc = "Bit 13 - Interrupt 173"] #[inline(always)] #[must_use] - pub fn int173(&mut self) -> INT173_W<13> { + pub fn int173(&mut self) -> INT173_W { INT173_W::new(self) } #[doc = "Bit 14 - Interrupt 174"] #[inline(always)] #[must_use] - pub fn int174(&mut self) -> INT174_W<14> { + pub fn int174(&mut self) -> INT174_W { INT174_W::new(self) } #[doc = "Bit 15 - Interrupt 175"] #[inline(always)] #[must_use] - pub fn int175(&mut self) -> INT175_W<15> { + pub fn int175(&mut self) -> INT175_W { INT175_W::new(self) } #[doc = "Bit 16 - Interrupt 176"] #[inline(always)] #[must_use] - pub fn int176(&mut self) -> INT176_W<16> { + pub fn int176(&mut self) -> INT176_W { INT176_W::new(self) } #[doc = "Bit 17 - Interrupt 177"] #[inline(always)] #[must_use] - pub fn int177(&mut self) -> INT177_W<17> { + pub fn int177(&mut self) -> INT177_W { INT177_W::new(self) } #[doc = "Bit 18 - Interrupt 178"] #[inline(always)] #[must_use] - pub fn int178(&mut self) -> INT178_W<18> { + pub fn int178(&mut self) -> INT178_W { INT178_W::new(self) } #[doc = "Bit 19 - Interrupt 179"] #[inline(always)] #[must_use] - pub fn int179(&mut self) -> INT179_W<19> { + pub fn int179(&mut self) -> INT179_W { INT179_W::new(self) } #[doc = "Bit 20 - Interrupt 180"] #[inline(always)] #[must_use] - pub fn int180(&mut self) -> INT180_W<20> { + pub fn int180(&mut self) -> INT180_W { INT180_W::new(self) } #[doc = "Bit 21 - Interrupt 181"] #[inline(always)] #[must_use] - pub fn int181(&mut self) -> INT181_W<21> { + pub fn int181(&mut self) -> INT181_W { INT181_W::new(self) } #[doc = "Bit 22 - Interrupt 182"] #[inline(always)] #[must_use] - pub fn int182(&mut self) -> INT182_W<22> { + pub fn int182(&mut self) -> INT182_W { INT182_W::new(self) } #[doc = "Bit 23 - Interrupt 183"] #[inline(always)] #[must_use] - pub fn int183(&mut self) -> INT183_W<23> { + pub fn int183(&mut self) -> INT183_W { INT183_W::new(self) } #[doc = "Bit 24 - Interrupt 184"] #[inline(always)] #[must_use] - pub fn int184(&mut self) -> INT184_W<24> { + pub fn int184(&mut self) -> INT184_W { INT184_W::new(self) } #[doc = "Bit 25 - Interrupt 185"] #[inline(always)] #[must_use] - pub fn int185(&mut self) -> INT185_W<25> { + pub fn int185(&mut self) -> INT185_W { INT185_W::new(self) } #[doc = "Bit 26 - Interrupt 186"] #[inline(always)] #[must_use] - pub fn int186(&mut self) -> INT186_W<26> { + pub fn int186(&mut self) -> INT186_W { INT186_W::new(self) } #[doc = "Bit 27 - Interrupt 187"] #[inline(always)] #[must_use] - pub fn int187(&mut self) -> INT187_W<27> { + pub fn int187(&mut self) -> INT187_W { INT187_W::new(self) } #[doc = "Bit 28 - Interrupt 188"] #[inline(always)] #[must_use] - pub fn int188(&mut self) -> INT188_W<28> { + pub fn int188(&mut self) -> INT188_W { INT188_W::new(self) } #[doc = "Bit 29 - Interrupt 189"] #[inline(always)] #[must_use] - pub fn int189(&mut self) -> INT189_W<29> { + pub fn int189(&mut self) -> INT189_W { INT189_W::new(self) } #[doc = "Bit 30 - Interrupt 190"] #[inline(always)] #[must_use] - pub fn int190(&mut self) -> INT190_W<30> { + pub fn int190(&mut self) -> INT190_W { INT190_W::new(self) } #[doc = "Bit 31 - Interrupt 191"] #[inline(always)] #[must_use] - pub fn int191(&mut self) -> INT191_W<31> { + pub fn int191(&mut self) -> INT191_W { INT191_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver5](index.html) module"] +#[doc = "Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICACTIVER5_SPEC; impl crate::RegisterSpec for GICD_ICACTIVER5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icactiver5::R](R) reader structure"] -impl crate::Readable for GICD_ICACTIVER5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icactiver5::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icactiver5::R`](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icactiver5::W`](W) writer structure"] impl crate::Writable for GICD_ICACTIVER5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver6.rs index 98912c7..585420b 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver6.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icactiver/gicd_icactiver6.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ICACTIVER6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICACTIVER6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT192` reader - Interrupt 192"] -pub type INT192_R = crate::BitReader; +pub type INT192_R = crate::BitReader; #[doc = "Field `INT192` writer - Interrupt 192"] -pub type INT192_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT192_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT193` reader - Interrupt 193"] -pub type INT193_R = crate::BitReader; +pub type INT193_R = crate::BitReader; #[doc = "Field `INT193` writer - Interrupt 193"] -pub type INT193_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT193_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT194` reader - Interrupt 194"] -pub type INT194_R = crate::BitReader; +pub type INT194_R = crate::BitReader; #[doc = "Field `INT194` writer - Interrupt 194"] -pub type INT194_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT194_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT195` reader - Interrupt 195"] -pub type INT195_R = crate::BitReader; +pub type INT195_R = crate::BitReader; #[doc = "Field `INT195` writer - Interrupt 195"] -pub type INT195_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT195_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT196` reader - Interrupt 196"] -pub type INT196_R = crate::BitReader; +pub type INT196_R = crate::BitReader; #[doc = "Field `INT196` writer - Interrupt 196"] -pub type INT196_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT196_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT197` reader - Interrupt 197"] -pub type INT197_R = crate::BitReader; +pub type INT197_R = crate::BitReader; #[doc = "Field `INT197` writer - Interrupt 197"] -pub type INT197_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT197_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT198` reader - Interrupt 198"] -pub type INT198_R = crate::BitReader; +pub type INT198_R = crate::BitReader; #[doc = "Field `INT198` writer - Interrupt 198"] -pub type INT198_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT198_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT199` reader - Interrupt 199"] -pub type INT199_R = crate::BitReader; +pub type INT199_R = crate::BitReader; #[doc = "Field `INT199` writer - Interrupt 199"] -pub type INT199_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT199_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT200` reader - Interrupt 200"] -pub type INT200_R = crate::BitReader; +pub type INT200_R = crate::BitReader; #[doc = "Field `INT200` writer - Interrupt 200"] -pub type INT200_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT200_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT201` reader - Interrupt 201"] -pub type INT201_R = crate::BitReader; +pub type INT201_R = crate::BitReader; #[doc = "Field `INT201` writer - Interrupt 201"] -pub type INT201_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT201_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT202` reader - Interrupt 202"] -pub type INT202_R = crate::BitReader; +pub type INT202_R = crate::BitReader; #[doc = "Field `INT202` writer - Interrupt 202"] -pub type INT202_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT202_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT203` reader - Interrupt 203"] -pub type INT203_R = crate::BitReader; +pub type INT203_R = crate::BitReader; #[doc = "Field `INT203` writer - Interrupt 203"] -pub type INT203_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT203_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT204` reader - Interrupt 204"] -pub type INT204_R = crate::BitReader; +pub type INT204_R = crate::BitReader; #[doc = "Field `INT204` writer - Interrupt 204"] -pub type INT204_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT204_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT205` reader - Interrupt 205"] -pub type INT205_R = crate::BitReader; +pub type INT205_R = crate::BitReader; #[doc = "Field `INT205` writer - Interrupt 205"] -pub type INT205_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT205_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT206` reader - Interrupt 206"] -pub type INT206_R = crate::BitReader; +pub type INT206_R = crate::BitReader; #[doc = "Field `INT206` writer - Interrupt 206"] -pub type INT206_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT206_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT207` reader - Interrupt 207"] -pub type INT207_R = crate::BitReader; +pub type INT207_R = crate::BitReader; #[doc = "Field `INT207` writer - Interrupt 207"] -pub type INT207_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT207_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT208` reader - Interrupt 208"] -pub type INT208_R = crate::BitReader; +pub type INT208_R = crate::BitReader; #[doc = "Field `INT208` writer - Interrupt 208"] -pub type INT208_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT208_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT209` reader - Interrupt 209"] -pub type INT209_R = crate::BitReader; +pub type INT209_R = crate::BitReader; #[doc = "Field `INT209` writer - Interrupt 209"] -pub type INT209_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT209_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT210` reader - Interrupt 210"] -pub type INT210_R = crate::BitReader; +pub type INT210_R = crate::BitReader; #[doc = "Field `INT210` writer - Interrupt 210"] -pub type INT210_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT210_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT211` reader - Interrupt 211"] -pub type INT211_R = crate::BitReader; +pub type INT211_R = crate::BitReader; #[doc = "Field `INT211` writer - Interrupt 211"] -pub type INT211_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT211_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT212` reader - Interrupt 212"] -pub type INT212_R = crate::BitReader; +pub type INT212_R = crate::BitReader; #[doc = "Field `INT212` writer - Interrupt 212"] -pub type INT212_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT212_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT213` reader - Interrupt 213"] -pub type INT213_R = crate::BitReader; +pub type INT213_R = crate::BitReader; #[doc = "Field `INT213` writer - Interrupt 213"] -pub type INT213_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT213_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT214` reader - Interrupt 214"] -pub type INT214_R = crate::BitReader; +pub type INT214_R = crate::BitReader; #[doc = "Field `INT214` writer - Interrupt 214"] -pub type INT214_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT214_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT215` reader - Interrupt 215"] -pub type INT215_R = crate::BitReader; +pub type INT215_R = crate::BitReader; #[doc = "Field `INT215` writer - Interrupt 215"] -pub type INT215_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT215_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT216` reader - Interrupt 216"] -pub type INT216_R = crate::BitReader; +pub type INT216_R = crate::BitReader; #[doc = "Field `INT216` writer - Interrupt 216"] -pub type INT216_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT216_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT217` reader - Interrupt 217"] -pub type INT217_R = crate::BitReader; +pub type INT217_R = crate::BitReader; #[doc = "Field `INT217` writer - Interrupt 217"] -pub type INT217_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT217_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT218` reader - Interrupt 218"] -pub type INT218_R = crate::BitReader; +pub type INT218_R = crate::BitReader; #[doc = "Field `INT218` writer - Interrupt 218"] -pub type INT218_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT218_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT219` reader - Interrupt 219"] -pub type INT219_R = crate::BitReader; +pub type INT219_R = crate::BitReader; #[doc = "Field `INT219` writer - Interrupt 219"] -pub type INT219_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT219_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT220` reader - Interrupt 220"] -pub type INT220_R = crate::BitReader; +pub type INT220_R = crate::BitReader; #[doc = "Field `INT220` writer - Interrupt 220"] -pub type INT220_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT220_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT221` reader - Interrupt 221"] -pub type INT221_R = crate::BitReader; +pub type INT221_R = crate::BitReader; #[doc = "Field `INT221` writer - Interrupt 221"] -pub type INT221_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT221_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT222` reader - Interrupt 222"] -pub type INT222_R = crate::BitReader; +pub type INT222_R = crate::BitReader; #[doc = "Field `INT222` writer - Interrupt 222"] -pub type INT222_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT222_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT223` reader - Interrupt 223"] -pub type INT223_R = crate::BitReader; +pub type INT223_R = crate::BitReader; #[doc = "Field `INT223` writer - Interrupt 223"] -pub type INT223_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICACTIVER6_SPEC, bool, O>; +pub type INT223_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT223_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICACTIVER6") + .field("int192", &format_args!("{}", self.int192().bit())) + .field("int193", &format_args!("{}", self.int193().bit())) + .field("int194", &format_args!("{}", self.int194().bit())) + .field("int195", &format_args!("{}", self.int195().bit())) + .field("int196", &format_args!("{}", self.int196().bit())) + .field("int197", &format_args!("{}", self.int197().bit())) + .field("int198", &format_args!("{}", self.int198().bit())) + .field("int199", &format_args!("{}", self.int199().bit())) + .field("int200", &format_args!("{}", self.int200().bit())) + .field("int201", &format_args!("{}", self.int201().bit())) + .field("int202", &format_args!("{}", self.int202().bit())) + .field("int203", &format_args!("{}", self.int203().bit())) + .field("int204", &format_args!("{}", self.int204().bit())) + .field("int205", &format_args!("{}", self.int205().bit())) + .field("int206", &format_args!("{}", self.int206().bit())) + .field("int207", &format_args!("{}", self.int207().bit())) + .field("int208", &format_args!("{}", self.int208().bit())) + .field("int209", &format_args!("{}", self.int209().bit())) + .field("int210", &format_args!("{}", self.int210().bit())) + .field("int211", &format_args!("{}", self.int211().bit())) + .field("int212", &format_args!("{}", self.int212().bit())) + .field("int213", &format_args!("{}", self.int213().bit())) + .field("int214", &format_args!("{}", self.int214().bit())) + .field("int215", &format_args!("{}", self.int215().bit())) + .field("int216", &format_args!("{}", self.int216().bit())) + .field("int217", &format_args!("{}", self.int217().bit())) + .field("int218", &format_args!("{}", self.int218().bit())) + .field("int219", &format_args!("{}", self.int219().bit())) + .field("int220", &format_args!("{}", self.int220().bit())) + .field("int221", &format_args!("{}", self.int221().bit())) + .field("int222", &format_args!("{}", self.int222().bit())) + .field("int223", &format_args!("{}", self.int223().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] #[must_use] - pub fn int192(&mut self) -> INT192_W<0> { + pub fn int192(&mut self) -> INT192_W { INT192_W::new(self) } #[doc = "Bit 1 - Interrupt 193"] #[inline(always)] #[must_use] - pub fn int193(&mut self) -> INT193_W<1> { + pub fn int193(&mut self) -> INT193_W { INT193_W::new(self) } #[doc = "Bit 2 - Interrupt 194"] #[inline(always)] #[must_use] - pub fn int194(&mut self) -> INT194_W<2> { + pub fn int194(&mut self) -> INT194_W { INT194_W::new(self) } #[doc = "Bit 3 - Interrupt 195"] #[inline(always)] #[must_use] - pub fn int195(&mut self) -> INT195_W<3> { + pub fn int195(&mut self) -> INT195_W { INT195_W::new(self) } #[doc = "Bit 4 - Interrupt 196"] #[inline(always)] #[must_use] - pub fn int196(&mut self) -> INT196_W<4> { + pub fn int196(&mut self) -> INT196_W { INT196_W::new(self) } #[doc = "Bit 5 - Interrupt 197"] #[inline(always)] #[must_use] - pub fn int197(&mut self) -> INT197_W<5> { + pub fn int197(&mut self) -> INT197_W { INT197_W::new(self) } #[doc = "Bit 6 - Interrupt 198"] #[inline(always)] #[must_use] - pub fn int198(&mut self) -> INT198_W<6> { + pub fn int198(&mut self) -> INT198_W { INT198_W::new(self) } #[doc = "Bit 7 - Interrupt 199"] #[inline(always)] #[must_use] - pub fn int199(&mut self) -> INT199_W<7> { + pub fn int199(&mut self) -> INT199_W { INT199_W::new(self) } #[doc = "Bit 8 - Interrupt 200"] #[inline(always)] #[must_use] - pub fn int200(&mut self) -> INT200_W<8> { + pub fn int200(&mut self) -> INT200_W { INT200_W::new(self) } #[doc = "Bit 9 - Interrupt 201"] #[inline(always)] #[must_use] - pub fn int201(&mut self) -> INT201_W<9> { + pub fn int201(&mut self) -> INT201_W { INT201_W::new(self) } #[doc = "Bit 10 - Interrupt 202"] #[inline(always)] #[must_use] - pub fn int202(&mut self) -> INT202_W<10> { + pub fn int202(&mut self) -> INT202_W { INT202_W::new(self) } #[doc = "Bit 11 - Interrupt 203"] #[inline(always)] #[must_use] - pub fn int203(&mut self) -> INT203_W<11> { + pub fn int203(&mut self) -> INT203_W { INT203_W::new(self) } #[doc = "Bit 12 - Interrupt 204"] #[inline(always)] #[must_use] - pub fn int204(&mut self) -> INT204_W<12> { + pub fn int204(&mut self) -> INT204_W { INT204_W::new(self) } #[doc = "Bit 13 - Interrupt 205"] #[inline(always)] #[must_use] - pub fn int205(&mut self) -> INT205_W<13> { + pub fn int205(&mut self) -> INT205_W { INT205_W::new(self) } #[doc = "Bit 14 - Interrupt 206"] #[inline(always)] #[must_use] - pub fn int206(&mut self) -> INT206_W<14> { + pub fn int206(&mut self) -> INT206_W { INT206_W::new(self) } #[doc = "Bit 15 - Interrupt 207"] #[inline(always)] #[must_use] - pub fn int207(&mut self) -> INT207_W<15> { + pub fn int207(&mut self) -> INT207_W { INT207_W::new(self) } #[doc = "Bit 16 - Interrupt 208"] #[inline(always)] #[must_use] - pub fn int208(&mut self) -> INT208_W<16> { + pub fn int208(&mut self) -> INT208_W { INT208_W::new(self) } #[doc = "Bit 17 - Interrupt 209"] #[inline(always)] #[must_use] - pub fn int209(&mut self) -> INT209_W<17> { + pub fn int209(&mut self) -> INT209_W { INT209_W::new(self) } #[doc = "Bit 18 - Interrupt 210"] #[inline(always)] #[must_use] - pub fn int210(&mut self) -> INT210_W<18> { + pub fn int210(&mut self) -> INT210_W { INT210_W::new(self) } #[doc = "Bit 19 - Interrupt 211"] #[inline(always)] #[must_use] - pub fn int211(&mut self) -> INT211_W<19> { + pub fn int211(&mut self) -> INT211_W { INT211_W::new(self) } #[doc = "Bit 20 - Interrupt 212"] #[inline(always)] #[must_use] - pub fn int212(&mut self) -> INT212_W<20> { + pub fn int212(&mut self) -> INT212_W { INT212_W::new(self) } #[doc = "Bit 21 - Interrupt 213"] #[inline(always)] #[must_use] - pub fn int213(&mut self) -> INT213_W<21> { + pub fn int213(&mut self) -> INT213_W { INT213_W::new(self) } #[doc = "Bit 22 - Interrupt 214"] #[inline(always)] #[must_use] - pub fn int214(&mut self) -> INT214_W<22> { + pub fn int214(&mut self) -> INT214_W { INT214_W::new(self) } #[doc = "Bit 23 - Interrupt 215"] #[inline(always)] #[must_use] - pub fn int215(&mut self) -> INT215_W<23> { + pub fn int215(&mut self) -> INT215_W { INT215_W::new(self) } #[doc = "Bit 24 - Interrupt 216"] #[inline(always)] #[must_use] - pub fn int216(&mut self) -> INT216_W<24> { + pub fn int216(&mut self) -> INT216_W { INT216_W::new(self) } #[doc = "Bit 25 - Interrupt 217"] #[inline(always)] #[must_use] - pub fn int217(&mut self) -> INT217_W<25> { + pub fn int217(&mut self) -> INT217_W { INT217_W::new(self) } #[doc = "Bit 26 - Interrupt 218"] #[inline(always)] #[must_use] - pub fn int218(&mut self) -> INT218_W<26> { + pub fn int218(&mut self) -> INT218_W { INT218_W::new(self) } #[doc = "Bit 27 - Interrupt 219"] #[inline(always)] #[must_use] - pub fn int219(&mut self) -> INT219_W<27> { + pub fn int219(&mut self) -> INT219_W { INT219_W::new(self) } #[doc = "Bit 28 - Interrupt 220"] #[inline(always)] #[must_use] - pub fn int220(&mut self) -> INT220_W<28> { + pub fn int220(&mut self) -> INT220_W { INT220_W::new(self) } #[doc = "Bit 29 - Interrupt 221"] #[inline(always)] #[must_use] - pub fn int221(&mut self) -> INT221_W<29> { + pub fn int221(&mut self) -> INT221_W { INT221_W::new(self) } #[doc = "Bit 30 - Interrupt 222"] #[inline(always)] #[must_use] - pub fn int222(&mut self) -> INT222_W<30> { + pub fn int222(&mut self) -> INT222_W { INT222_W::new(self) } #[doc = "Bit 31 - Interrupt 223"] #[inline(always)] #[must_use] - pub fn int223(&mut self) -> INT223_W<31> { + pub fn int223(&mut self) -> INT223_W { INT223_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icactiver6](index.html) module"] +#[doc = "Interrupt Clear-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icactiver6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icactiver6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICACTIVER6_SPEC; impl crate::RegisterSpec for GICD_ICACTIVER6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icactiver6::R](R) reader structure"] -impl crate::Readable for GICD_ICACTIVER6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icactiver6::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icactiver6::R`](R) reader structure"] +impl crate::Readable for GICD_ICACTIVER6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icactiver6::W`](W) writer structure"] impl crate::Writable for GICD_ICACTIVER6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler.rs index fd334cd..4d38500 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct GICD_ICENABLER { #[doc = "0x00 - Interrupt Clear-Enable"] pub gicd_icenabler0: GICD_ICENABLER0, @@ -16,31 +17,38 @@ pub struct GICD_ICENABLER { #[doc = "0x18 - Interrupt Clear-Enable"] pub gicd_icenabler6: GICD_ICENABLER6, } -#[doc = "GICD_ICENABLER0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICENABLER0 (rw) register accessor: Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icenabler0`] +module"] pub type GICD_ICENABLER0 = crate::Reg; #[doc = "Interrupt Clear-Enable"] pub mod gicd_icenabler0; -#[doc = "GICD_ICENABLER1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICENABLER1 (rw) register accessor: Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icenabler1`] +module"] pub type GICD_ICENABLER1 = crate::Reg; #[doc = "Interrupt Clear-Enable"] pub mod gicd_icenabler1; -#[doc = "GICD_ICENABLER2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICENABLER2 (rw) register accessor: Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icenabler2`] +module"] pub type GICD_ICENABLER2 = crate::Reg; #[doc = "Interrupt Clear-Enable"] pub mod gicd_icenabler2; -#[doc = "GICD_ICENABLER3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICENABLER3 (rw) register accessor: Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icenabler3`] +module"] pub type GICD_ICENABLER3 = crate::Reg; #[doc = "Interrupt Clear-Enable"] pub mod gicd_icenabler3; -#[doc = "GICD_ICENABLER4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICENABLER4 (rw) register accessor: Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icenabler4`] +module"] pub type GICD_ICENABLER4 = crate::Reg; #[doc = "Interrupt Clear-Enable"] pub mod gicd_icenabler4; -#[doc = "GICD_ICENABLER5 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICENABLER5 (rw) register accessor: Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icenabler5`] +module"] pub type GICD_ICENABLER5 = crate::Reg; #[doc = "Interrupt Clear-Enable"] pub mod gicd_icenabler5; -#[doc = "GICD_ICENABLER6 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICENABLER6 (rw) register accessor: Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icenabler6`] +module"] pub type GICD_ICENABLER6 = crate::Reg; #[doc = "Interrupt Clear-Enable"] pub mod gicd_icenabler6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler0.rs index 1ffa08c..267ac9b 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler0.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ICENABLER0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICENABLER0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT0` reader - Interrupt 0"] -pub type INT0_R = crate::BitReader; +pub type INT0_R = crate::BitReader; #[doc = "Field `INT0` writer - Interrupt 0"] -pub type INT0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT1` reader - Interrupt 1"] -pub type INT1_R = crate::BitReader; +pub type INT1_R = crate::BitReader; #[doc = "Field `INT1` writer - Interrupt 1"] -pub type INT1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT2` reader - Interrupt 2"] -pub type INT2_R = crate::BitReader; +pub type INT2_R = crate::BitReader; #[doc = "Field `INT2` writer - Interrupt 2"] -pub type INT2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT3` reader - Interrupt 3"] -pub type INT3_R = crate::BitReader; +pub type INT3_R = crate::BitReader; #[doc = "Field `INT3` writer - Interrupt 3"] -pub type INT3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT4` reader - Interrupt 4"] -pub type INT4_R = crate::BitReader; +pub type INT4_R = crate::BitReader; #[doc = "Field `INT4` writer - Interrupt 4"] -pub type INT4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT5` reader - Interrupt 5"] -pub type INT5_R = crate::BitReader; +pub type INT5_R = crate::BitReader; #[doc = "Field `INT5` writer - Interrupt 5"] -pub type INT5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT6` reader - Interrupt 6"] -pub type INT6_R = crate::BitReader; +pub type INT6_R = crate::BitReader; #[doc = "Field `INT6` writer - Interrupt 6"] -pub type INT6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT7` reader - Interrupt 7"] -pub type INT7_R = crate::BitReader; +pub type INT7_R = crate::BitReader; #[doc = "Field `INT7` writer - Interrupt 7"] -pub type INT7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT8` reader - Interrupt 8"] -pub type INT8_R = crate::BitReader; +pub type INT8_R = crate::BitReader; #[doc = "Field `INT8` writer - Interrupt 8"] -pub type INT8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT9` reader - Interrupt 9"] -pub type INT9_R = crate::BitReader; +pub type INT9_R = crate::BitReader; #[doc = "Field `INT9` writer - Interrupt 9"] -pub type INT9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT9_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT10` reader - Interrupt 10"] -pub type INT10_R = crate::BitReader; +pub type INT10_R = crate::BitReader; #[doc = "Field `INT10` writer - Interrupt 10"] -pub type INT10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT11` reader - Interrupt 11"] -pub type INT11_R = crate::BitReader; +pub type INT11_R = crate::BitReader; #[doc = "Field `INT11` writer - Interrupt 11"] -pub type INT11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT12` reader - Interrupt 12"] -pub type INT12_R = crate::BitReader; +pub type INT12_R = crate::BitReader; #[doc = "Field `INT12` writer - Interrupt 12"] -pub type INT12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT13` reader - Interrupt 13"] -pub type INT13_R = crate::BitReader; +pub type INT13_R = crate::BitReader; #[doc = "Field `INT13` writer - Interrupt 13"] -pub type INT13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT14` reader - Interrupt 14"] -pub type INT14_R = crate::BitReader; +pub type INT14_R = crate::BitReader; #[doc = "Field `INT14` writer - Interrupt 14"] -pub type INT14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT15` reader - Interrupt 15"] -pub type INT15_R = crate::BitReader; +pub type INT15_R = crate::BitReader; #[doc = "Field `INT15` writer - Interrupt 15"] -pub type INT15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT16` reader - Interrupt 16"] -pub type INT16_R = crate::BitReader; +pub type INT16_R = crate::BitReader; #[doc = "Field `INT16` writer - Interrupt 16"] -pub type INT16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT16_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT17` reader - Interrupt 17"] -pub type INT17_R = crate::BitReader; +pub type INT17_R = crate::BitReader; #[doc = "Field `INT17` writer - Interrupt 17"] -pub type INT17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT17_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT18` reader - Interrupt 18"] -pub type INT18_R = crate::BitReader; +pub type INT18_R = crate::BitReader; #[doc = "Field `INT18` writer - Interrupt 18"] -pub type INT18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT18_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT19` reader - Interrupt 19"] -pub type INT19_R = crate::BitReader; +pub type INT19_R = crate::BitReader; #[doc = "Field `INT19` writer - Interrupt 19"] -pub type INT19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT19_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT20` reader - Interrupt 20"] -pub type INT20_R = crate::BitReader; +pub type INT20_R = crate::BitReader; #[doc = "Field `INT20` writer - Interrupt 20"] -pub type INT20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT20_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT21` reader - Interrupt 21"] -pub type INT21_R = crate::BitReader; +pub type INT21_R = crate::BitReader; #[doc = "Field `INT21` writer - Interrupt 21"] -pub type INT21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT21_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT22` reader - Interrupt 22"] -pub type INT22_R = crate::BitReader; +pub type INT22_R = crate::BitReader; #[doc = "Field `INT22` writer - Interrupt 22"] -pub type INT22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT22_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT23` reader - Interrupt 23"] -pub type INT23_R = crate::BitReader; +pub type INT23_R = crate::BitReader; #[doc = "Field `INT23` writer - Interrupt 23"] -pub type INT23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT23_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT24` reader - Interrupt 24"] -pub type INT24_R = crate::BitReader; +pub type INT24_R = crate::BitReader; #[doc = "Field `INT24` writer - Interrupt 24"] -pub type INT24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT24_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT25` reader - Interrupt 25"] -pub type INT25_R = crate::BitReader; +pub type INT25_R = crate::BitReader; #[doc = "Field `INT25` writer - Interrupt 25"] -pub type INT25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT25_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT26` reader - Interrupt 26"] -pub type INT26_R = crate::BitReader; +pub type INT26_R = crate::BitReader; #[doc = "Field `INT26` writer - Interrupt 26"] -pub type INT26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT26_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT27` reader - Interrupt 27"] -pub type INT27_R = crate::BitReader; +pub type INT27_R = crate::BitReader; #[doc = "Field `INT27` writer - Interrupt 27"] -pub type INT27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT27_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT28` reader - Interrupt 28"] -pub type INT28_R = crate::BitReader; +pub type INT28_R = crate::BitReader; #[doc = "Field `INT28` writer - Interrupt 28"] -pub type INT28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT28_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT29` reader - Interrupt 29"] -pub type INT29_R = crate::BitReader; +pub type INT29_R = crate::BitReader; #[doc = "Field `INT29` writer - Interrupt 29"] -pub type INT29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT29_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT30` reader - Interrupt 30"] -pub type INT30_R = crate::BitReader; +pub type INT30_R = crate::BitReader; #[doc = "Field `INT30` writer - Interrupt 30"] -pub type INT30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT30_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT31` reader - Interrupt 31"] -pub type INT31_R = crate::BitReader; +pub type INT31_R = crate::BitReader; #[doc = "Field `INT31` writer - Interrupt 31"] -pub type INT31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER0_SPEC, bool, O>; +pub type INT31_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICENABLER0") + .field("int0", &format_args!("{}", self.int0().bit())) + .field("int1", &format_args!("{}", self.int1().bit())) + .field("int2", &format_args!("{}", self.int2().bit())) + .field("int3", &format_args!("{}", self.int3().bit())) + .field("int4", &format_args!("{}", self.int4().bit())) + .field("int5", &format_args!("{}", self.int5().bit())) + .field("int6", &format_args!("{}", self.int6().bit())) + .field("int7", &format_args!("{}", self.int7().bit())) + .field("int8", &format_args!("{}", self.int8().bit())) + .field("int9", &format_args!("{}", self.int9().bit())) + .field("int10", &format_args!("{}", self.int10().bit())) + .field("int11", &format_args!("{}", self.int11().bit())) + .field("int12", &format_args!("{}", self.int12().bit())) + .field("int13", &format_args!("{}", self.int13().bit())) + .field("int14", &format_args!("{}", self.int14().bit())) + .field("int15", &format_args!("{}", self.int15().bit())) + .field("int16", &format_args!("{}", self.int16().bit())) + .field("int17", &format_args!("{}", self.int17().bit())) + .field("int18", &format_args!("{}", self.int18().bit())) + .field("int19", &format_args!("{}", self.int19().bit())) + .field("int20", &format_args!("{}", self.int20().bit())) + .field("int21", &format_args!("{}", self.int21().bit())) + .field("int22", &format_args!("{}", self.int22().bit())) + .field("int23", &format_args!("{}", self.int23().bit())) + .field("int24", &format_args!("{}", self.int24().bit())) + .field("int25", &format_args!("{}", self.int25().bit())) + .field("int26", &format_args!("{}", self.int26().bit())) + .field("int27", &format_args!("{}", self.int27().bit())) + .field("int28", &format_args!("{}", self.int28().bit())) + .field("int29", &format_args!("{}", self.int29().bit())) + .field("int30", &format_args!("{}", self.int30().bit())) + .field("int31", &format_args!("{}", self.int31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] #[must_use] - pub fn int0(&mut self) -> INT0_W<0> { + pub fn int0(&mut self) -> INT0_W { INT0_W::new(self) } #[doc = "Bit 1 - Interrupt 1"] #[inline(always)] #[must_use] - pub fn int1(&mut self) -> INT1_W<1> { + pub fn int1(&mut self) -> INT1_W { INT1_W::new(self) } #[doc = "Bit 2 - Interrupt 2"] #[inline(always)] #[must_use] - pub fn int2(&mut self) -> INT2_W<2> { + pub fn int2(&mut self) -> INT2_W { INT2_W::new(self) } #[doc = "Bit 3 - Interrupt 3"] #[inline(always)] #[must_use] - pub fn int3(&mut self) -> INT3_W<3> { + pub fn int3(&mut self) -> INT3_W { INT3_W::new(self) } #[doc = "Bit 4 - Interrupt 4"] #[inline(always)] #[must_use] - pub fn int4(&mut self) -> INT4_W<4> { + pub fn int4(&mut self) -> INT4_W { INT4_W::new(self) } #[doc = "Bit 5 - Interrupt 5"] #[inline(always)] #[must_use] - pub fn int5(&mut self) -> INT5_W<5> { + pub fn int5(&mut self) -> INT5_W { INT5_W::new(self) } #[doc = "Bit 6 - Interrupt 6"] #[inline(always)] #[must_use] - pub fn int6(&mut self) -> INT6_W<6> { + pub fn int6(&mut self) -> INT6_W { INT6_W::new(self) } #[doc = "Bit 7 - Interrupt 7"] #[inline(always)] #[must_use] - pub fn int7(&mut self) -> INT7_W<7> { + pub fn int7(&mut self) -> INT7_W { INT7_W::new(self) } #[doc = "Bit 8 - Interrupt 8"] #[inline(always)] #[must_use] - pub fn int8(&mut self) -> INT8_W<8> { + pub fn int8(&mut self) -> INT8_W { INT8_W::new(self) } #[doc = "Bit 9 - Interrupt 9"] #[inline(always)] #[must_use] - pub fn int9(&mut self) -> INT9_W<9> { + pub fn int9(&mut self) -> INT9_W { INT9_W::new(self) } #[doc = "Bit 10 - Interrupt 10"] #[inline(always)] #[must_use] - pub fn int10(&mut self) -> INT10_W<10> { + pub fn int10(&mut self) -> INT10_W { INT10_W::new(self) } #[doc = "Bit 11 - Interrupt 11"] #[inline(always)] #[must_use] - pub fn int11(&mut self) -> INT11_W<11> { + pub fn int11(&mut self) -> INT11_W { INT11_W::new(self) } #[doc = "Bit 12 - Interrupt 12"] #[inline(always)] #[must_use] - pub fn int12(&mut self) -> INT12_W<12> { + pub fn int12(&mut self) -> INT12_W { INT12_W::new(self) } #[doc = "Bit 13 - Interrupt 13"] #[inline(always)] #[must_use] - pub fn int13(&mut self) -> INT13_W<13> { + pub fn int13(&mut self) -> INT13_W { INT13_W::new(self) } #[doc = "Bit 14 - Interrupt 14"] #[inline(always)] #[must_use] - pub fn int14(&mut self) -> INT14_W<14> { + pub fn int14(&mut self) -> INT14_W { INT14_W::new(self) } #[doc = "Bit 15 - Interrupt 15"] #[inline(always)] #[must_use] - pub fn int15(&mut self) -> INT15_W<15> { + pub fn int15(&mut self) -> INT15_W { INT15_W::new(self) } #[doc = "Bit 16 - Interrupt 16"] #[inline(always)] #[must_use] - pub fn int16(&mut self) -> INT16_W<16> { + pub fn int16(&mut self) -> INT16_W { INT16_W::new(self) } #[doc = "Bit 17 - Interrupt 17"] #[inline(always)] #[must_use] - pub fn int17(&mut self) -> INT17_W<17> { + pub fn int17(&mut self) -> INT17_W { INT17_W::new(self) } #[doc = "Bit 18 - Interrupt 18"] #[inline(always)] #[must_use] - pub fn int18(&mut self) -> INT18_W<18> { + pub fn int18(&mut self) -> INT18_W { INT18_W::new(self) } #[doc = "Bit 19 - Interrupt 19"] #[inline(always)] #[must_use] - pub fn int19(&mut self) -> INT19_W<19> { + pub fn int19(&mut self) -> INT19_W { INT19_W::new(self) } #[doc = "Bit 20 - Interrupt 20"] #[inline(always)] #[must_use] - pub fn int20(&mut self) -> INT20_W<20> { + pub fn int20(&mut self) -> INT20_W { INT20_W::new(self) } #[doc = "Bit 21 - Interrupt 21"] #[inline(always)] #[must_use] - pub fn int21(&mut self) -> INT21_W<21> { + pub fn int21(&mut self) -> INT21_W { INT21_W::new(self) } #[doc = "Bit 22 - Interrupt 22"] #[inline(always)] #[must_use] - pub fn int22(&mut self) -> INT22_W<22> { + pub fn int22(&mut self) -> INT22_W { INT22_W::new(self) } #[doc = "Bit 23 - Interrupt 23"] #[inline(always)] #[must_use] - pub fn int23(&mut self) -> INT23_W<23> { + pub fn int23(&mut self) -> INT23_W { INT23_W::new(self) } #[doc = "Bit 24 - Interrupt 24"] #[inline(always)] #[must_use] - pub fn int24(&mut self) -> INT24_W<24> { + pub fn int24(&mut self) -> INT24_W { INT24_W::new(self) } #[doc = "Bit 25 - Interrupt 25"] #[inline(always)] #[must_use] - pub fn int25(&mut self) -> INT25_W<25> { + pub fn int25(&mut self) -> INT25_W { INT25_W::new(self) } #[doc = "Bit 26 - Interrupt 26"] #[inline(always)] #[must_use] - pub fn int26(&mut self) -> INT26_W<26> { + pub fn int26(&mut self) -> INT26_W { INT26_W::new(self) } #[doc = "Bit 27 - Interrupt 27"] #[inline(always)] #[must_use] - pub fn int27(&mut self) -> INT27_W<27> { + pub fn int27(&mut self) -> INT27_W { INT27_W::new(self) } #[doc = "Bit 28 - Interrupt 28"] #[inline(always)] #[must_use] - pub fn int28(&mut self) -> INT28_W<28> { + pub fn int28(&mut self) -> INT28_W { INT28_W::new(self) } #[doc = "Bit 29 - Interrupt 29"] #[inline(always)] #[must_use] - pub fn int29(&mut self) -> INT29_W<29> { + pub fn int29(&mut self) -> INT29_W { INT29_W::new(self) } #[doc = "Bit 30 - Interrupt 30"] #[inline(always)] #[must_use] - pub fn int30(&mut self) -> INT30_W<30> { + pub fn int30(&mut self) -> INT30_W { INT30_W::new(self) } #[doc = "Bit 31 - Interrupt 31"] #[inline(always)] #[must_use] - pub fn int31(&mut self) -> INT31_W<31> { + pub fn int31(&mut self) -> INT31_W { INT31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler0](index.html) module"] +#[doc = "Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICENABLER0_SPEC; impl crate::RegisterSpec for GICD_ICENABLER0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icenabler0::R](R) reader structure"] -impl crate::Readable for GICD_ICENABLER0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icenabler0::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icenabler0::R`](R) reader structure"] +impl crate::Readable for GICD_ICENABLER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icenabler0::W`](W) writer structure"] impl crate::Writable for GICD_ICENABLER0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler1.rs index d070bb5..914db6d 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler1.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler1.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ICENABLER1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICENABLER1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT32` reader - Interrupt 32"] -pub type INT32_R = crate::BitReader; +pub type INT32_R = crate::BitReader; #[doc = "Field `INT32` writer - Interrupt 32"] -pub type INT32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT32_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT33` reader - Interrupt 33"] -pub type INT33_R = crate::BitReader; +pub type INT33_R = crate::BitReader; #[doc = "Field `INT33` writer - Interrupt 33"] -pub type INT33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT33_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT34` reader - Interrupt 34"] -pub type INT34_R = crate::BitReader; +pub type INT34_R = crate::BitReader; #[doc = "Field `INT34` writer - Interrupt 34"] -pub type INT34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT34_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT35` reader - Interrupt 35"] -pub type INT35_R = crate::BitReader; +pub type INT35_R = crate::BitReader; #[doc = "Field `INT35` writer - Interrupt 35"] -pub type INT35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT35_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT36` reader - Interrupt 36"] -pub type INT36_R = crate::BitReader; +pub type INT36_R = crate::BitReader; #[doc = "Field `INT36` writer - Interrupt 36"] -pub type INT36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT36_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT37` reader - Interrupt 37"] -pub type INT37_R = crate::BitReader; +pub type INT37_R = crate::BitReader; #[doc = "Field `INT37` writer - Interrupt 37"] -pub type INT37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT37_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT38` reader - Interrupt 38"] -pub type INT38_R = crate::BitReader; +pub type INT38_R = crate::BitReader; #[doc = "Field `INT38` writer - Interrupt 38"] -pub type INT38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT38_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT39` reader - Interrupt 39"] -pub type INT39_R = crate::BitReader; +pub type INT39_R = crate::BitReader; #[doc = "Field `INT39` writer - Interrupt 39"] -pub type INT39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT39_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT40` reader - Interrupt 40"] -pub type INT40_R = crate::BitReader; +pub type INT40_R = crate::BitReader; #[doc = "Field `INT40` writer - Interrupt 40"] -pub type INT40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT40_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT41` reader - Interrupt 41"] -pub type INT41_R = crate::BitReader; +pub type INT41_R = crate::BitReader; #[doc = "Field `INT41` writer - Interrupt 41"] -pub type INT41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT41_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT42` reader - Interrupt 42"] -pub type INT42_R = crate::BitReader; +pub type INT42_R = crate::BitReader; #[doc = "Field `INT42` writer - Interrupt 42"] -pub type INT42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT42_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT43` reader - Interrupt 43"] -pub type INT43_R = crate::BitReader; +pub type INT43_R = crate::BitReader; #[doc = "Field `INT43` writer - Interrupt 43"] -pub type INT43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT43_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT44` reader - Interrupt 44"] -pub type INT44_R = crate::BitReader; +pub type INT44_R = crate::BitReader; #[doc = "Field `INT44` writer - Interrupt 44"] -pub type INT44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT44_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT45` reader - Interrupt 45"] -pub type INT45_R = crate::BitReader; +pub type INT45_R = crate::BitReader; #[doc = "Field `INT45` writer - Interrupt 45"] -pub type INT45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT45_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT46` reader - Interrupt 46"] -pub type INT46_R = crate::BitReader; +pub type INT46_R = crate::BitReader; #[doc = "Field `INT46` writer - Interrupt 46"] -pub type INT46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT46_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT47` reader - Interrupt 47"] -pub type INT47_R = crate::BitReader; +pub type INT47_R = crate::BitReader; #[doc = "Field `INT47` writer - Interrupt 47"] -pub type INT47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT47_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT48` reader - Interrupt 48"] -pub type INT48_R = crate::BitReader; +pub type INT48_R = crate::BitReader; #[doc = "Field `INT48` writer - Interrupt 48"] -pub type INT48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT48_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT49` reader - Interrupt 49"] -pub type INT49_R = crate::BitReader; +pub type INT49_R = crate::BitReader; #[doc = "Field `INT49` writer - Interrupt 49"] -pub type INT49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT49_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT50` reader - Interrupt 50"] -pub type INT50_R = crate::BitReader; +pub type INT50_R = crate::BitReader; #[doc = "Field `INT50` writer - Interrupt 50"] -pub type INT50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT50_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT51` reader - Interrupt 51"] -pub type INT51_R = crate::BitReader; +pub type INT51_R = crate::BitReader; #[doc = "Field `INT51` writer - Interrupt 51"] -pub type INT51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT51_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT52` reader - Interrupt 52"] -pub type INT52_R = crate::BitReader; +pub type INT52_R = crate::BitReader; #[doc = "Field `INT52` writer - Interrupt 52"] -pub type INT52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT52_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT53` reader - Interrupt 53"] -pub type INT53_R = crate::BitReader; +pub type INT53_R = crate::BitReader; #[doc = "Field `INT53` writer - Interrupt 53"] -pub type INT53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT53_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT54` reader - Interrupt 54"] -pub type INT54_R = crate::BitReader; +pub type INT54_R = crate::BitReader; #[doc = "Field `INT54` writer - Interrupt 54"] -pub type INT54_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT54_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT55` reader - Interrupt 55"] -pub type INT55_R = crate::BitReader; +pub type INT55_R = crate::BitReader; #[doc = "Field `INT55` writer - Interrupt 55"] -pub type INT55_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT55_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT56` reader - Interrupt 56"] -pub type INT56_R = crate::BitReader; +pub type INT56_R = crate::BitReader; #[doc = "Field `INT56` writer - Interrupt 56"] -pub type INT56_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT56_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT57` reader - Interrupt 57"] -pub type INT57_R = crate::BitReader; +pub type INT57_R = crate::BitReader; #[doc = "Field `INT57` writer - Interrupt 57"] -pub type INT57_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT57_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT58` reader - Interrupt 58"] -pub type INT58_R = crate::BitReader; +pub type INT58_R = crate::BitReader; #[doc = "Field `INT58` writer - Interrupt 58"] -pub type INT58_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT58_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT59` reader - Interrupt 59"] -pub type INT59_R = crate::BitReader; +pub type INT59_R = crate::BitReader; #[doc = "Field `INT59` writer - Interrupt 59"] -pub type INT59_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT59_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT60` reader - Interrupt 60"] -pub type INT60_R = crate::BitReader; +pub type INT60_R = crate::BitReader; #[doc = "Field `INT60` writer - Interrupt 60"] -pub type INT60_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT60_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT61` reader - Interrupt 61"] -pub type INT61_R = crate::BitReader; +pub type INT61_R = crate::BitReader; #[doc = "Field `INT61` writer - Interrupt 61"] -pub type INT61_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT61_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT62` reader - Interrupt 62"] -pub type INT62_R = crate::BitReader; +pub type INT62_R = crate::BitReader; #[doc = "Field `INT62` writer - Interrupt 62"] -pub type INT62_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT62_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT63` reader - Interrupt 63"] -pub type INT63_R = crate::BitReader; +pub type INT63_R = crate::BitReader; #[doc = "Field `INT63` writer - Interrupt 63"] -pub type INT63_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER1_SPEC, bool, O>; +pub type INT63_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT63_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICENABLER1") + .field("int32", &format_args!("{}", self.int32().bit())) + .field("int33", &format_args!("{}", self.int33().bit())) + .field("int34", &format_args!("{}", self.int34().bit())) + .field("int35", &format_args!("{}", self.int35().bit())) + .field("int36", &format_args!("{}", self.int36().bit())) + .field("int37", &format_args!("{}", self.int37().bit())) + .field("int38", &format_args!("{}", self.int38().bit())) + .field("int39", &format_args!("{}", self.int39().bit())) + .field("int40", &format_args!("{}", self.int40().bit())) + .field("int41", &format_args!("{}", self.int41().bit())) + .field("int42", &format_args!("{}", self.int42().bit())) + .field("int43", &format_args!("{}", self.int43().bit())) + .field("int44", &format_args!("{}", self.int44().bit())) + .field("int45", &format_args!("{}", self.int45().bit())) + .field("int46", &format_args!("{}", self.int46().bit())) + .field("int47", &format_args!("{}", self.int47().bit())) + .field("int48", &format_args!("{}", self.int48().bit())) + .field("int49", &format_args!("{}", self.int49().bit())) + .field("int50", &format_args!("{}", self.int50().bit())) + .field("int51", &format_args!("{}", self.int51().bit())) + .field("int52", &format_args!("{}", self.int52().bit())) + .field("int53", &format_args!("{}", self.int53().bit())) + .field("int54", &format_args!("{}", self.int54().bit())) + .field("int55", &format_args!("{}", self.int55().bit())) + .field("int56", &format_args!("{}", self.int56().bit())) + .field("int57", &format_args!("{}", self.int57().bit())) + .field("int58", &format_args!("{}", self.int58().bit())) + .field("int59", &format_args!("{}", self.int59().bit())) + .field("int60", &format_args!("{}", self.int60().bit())) + .field("int61", &format_args!("{}", self.int61().bit())) + .field("int62", &format_args!("{}", self.int62().bit())) + .field("int63", &format_args!("{}", self.int63().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] #[must_use] - pub fn int32(&mut self) -> INT32_W<0> { + pub fn int32(&mut self) -> INT32_W { INT32_W::new(self) } #[doc = "Bit 1 - Interrupt 33"] #[inline(always)] #[must_use] - pub fn int33(&mut self) -> INT33_W<1> { + pub fn int33(&mut self) -> INT33_W { INT33_W::new(self) } #[doc = "Bit 2 - Interrupt 34"] #[inline(always)] #[must_use] - pub fn int34(&mut self) -> INT34_W<2> { + pub fn int34(&mut self) -> INT34_W { INT34_W::new(self) } #[doc = "Bit 3 - Interrupt 35"] #[inline(always)] #[must_use] - pub fn int35(&mut self) -> INT35_W<3> { + pub fn int35(&mut self) -> INT35_W { INT35_W::new(self) } #[doc = "Bit 4 - Interrupt 36"] #[inline(always)] #[must_use] - pub fn int36(&mut self) -> INT36_W<4> { + pub fn int36(&mut self) -> INT36_W { INT36_W::new(self) } #[doc = "Bit 5 - Interrupt 37"] #[inline(always)] #[must_use] - pub fn int37(&mut self) -> INT37_W<5> { + pub fn int37(&mut self) -> INT37_W { INT37_W::new(self) } #[doc = "Bit 6 - Interrupt 38"] #[inline(always)] #[must_use] - pub fn int38(&mut self) -> INT38_W<6> { + pub fn int38(&mut self) -> INT38_W { INT38_W::new(self) } #[doc = "Bit 7 - Interrupt 39"] #[inline(always)] #[must_use] - pub fn int39(&mut self) -> INT39_W<7> { + pub fn int39(&mut self) -> INT39_W { INT39_W::new(self) } #[doc = "Bit 8 - Interrupt 40"] #[inline(always)] #[must_use] - pub fn int40(&mut self) -> INT40_W<8> { + pub fn int40(&mut self) -> INT40_W { INT40_W::new(self) } #[doc = "Bit 9 - Interrupt 41"] #[inline(always)] #[must_use] - pub fn int41(&mut self) -> INT41_W<9> { + pub fn int41(&mut self) -> INT41_W { INT41_W::new(self) } #[doc = "Bit 10 - Interrupt 42"] #[inline(always)] #[must_use] - pub fn int42(&mut self) -> INT42_W<10> { + pub fn int42(&mut self) -> INT42_W { INT42_W::new(self) } #[doc = "Bit 11 - Interrupt 43"] #[inline(always)] #[must_use] - pub fn int43(&mut self) -> INT43_W<11> { + pub fn int43(&mut self) -> INT43_W { INT43_W::new(self) } #[doc = "Bit 12 - Interrupt 44"] #[inline(always)] #[must_use] - pub fn int44(&mut self) -> INT44_W<12> { + pub fn int44(&mut self) -> INT44_W { INT44_W::new(self) } #[doc = "Bit 13 - Interrupt 45"] #[inline(always)] #[must_use] - pub fn int45(&mut self) -> INT45_W<13> { + pub fn int45(&mut self) -> INT45_W { INT45_W::new(self) } #[doc = "Bit 14 - Interrupt 46"] #[inline(always)] #[must_use] - pub fn int46(&mut self) -> INT46_W<14> { + pub fn int46(&mut self) -> INT46_W { INT46_W::new(self) } #[doc = "Bit 15 - Interrupt 47"] #[inline(always)] #[must_use] - pub fn int47(&mut self) -> INT47_W<15> { + pub fn int47(&mut self) -> INT47_W { INT47_W::new(self) } #[doc = "Bit 16 - Interrupt 48"] #[inline(always)] #[must_use] - pub fn int48(&mut self) -> INT48_W<16> { + pub fn int48(&mut self) -> INT48_W { INT48_W::new(self) } #[doc = "Bit 17 - Interrupt 49"] #[inline(always)] #[must_use] - pub fn int49(&mut self) -> INT49_W<17> { + pub fn int49(&mut self) -> INT49_W { INT49_W::new(self) } #[doc = "Bit 18 - Interrupt 50"] #[inline(always)] #[must_use] - pub fn int50(&mut self) -> INT50_W<18> { + pub fn int50(&mut self) -> INT50_W { INT50_W::new(self) } #[doc = "Bit 19 - Interrupt 51"] #[inline(always)] #[must_use] - pub fn int51(&mut self) -> INT51_W<19> { + pub fn int51(&mut self) -> INT51_W { INT51_W::new(self) } #[doc = "Bit 20 - Interrupt 52"] #[inline(always)] #[must_use] - pub fn int52(&mut self) -> INT52_W<20> { + pub fn int52(&mut self) -> INT52_W { INT52_W::new(self) } #[doc = "Bit 21 - Interrupt 53"] #[inline(always)] #[must_use] - pub fn int53(&mut self) -> INT53_W<21> { + pub fn int53(&mut self) -> INT53_W { INT53_W::new(self) } #[doc = "Bit 22 - Interrupt 54"] #[inline(always)] #[must_use] - pub fn int54(&mut self) -> INT54_W<22> { + pub fn int54(&mut self) -> INT54_W { INT54_W::new(self) } #[doc = "Bit 23 - Interrupt 55"] #[inline(always)] #[must_use] - pub fn int55(&mut self) -> INT55_W<23> { + pub fn int55(&mut self) -> INT55_W { INT55_W::new(self) } #[doc = "Bit 24 - Interrupt 56"] #[inline(always)] #[must_use] - pub fn int56(&mut self) -> INT56_W<24> { + pub fn int56(&mut self) -> INT56_W { INT56_W::new(self) } #[doc = "Bit 25 - Interrupt 57"] #[inline(always)] #[must_use] - pub fn int57(&mut self) -> INT57_W<25> { + pub fn int57(&mut self) -> INT57_W { INT57_W::new(self) } #[doc = "Bit 26 - Interrupt 58"] #[inline(always)] #[must_use] - pub fn int58(&mut self) -> INT58_W<26> { + pub fn int58(&mut self) -> INT58_W { INT58_W::new(self) } #[doc = "Bit 27 - Interrupt 59"] #[inline(always)] #[must_use] - pub fn int59(&mut self) -> INT59_W<27> { + pub fn int59(&mut self) -> INT59_W { INT59_W::new(self) } #[doc = "Bit 28 - Interrupt 60"] #[inline(always)] #[must_use] - pub fn int60(&mut self) -> INT60_W<28> { + pub fn int60(&mut self) -> INT60_W { INT60_W::new(self) } #[doc = "Bit 29 - Interrupt 61"] #[inline(always)] #[must_use] - pub fn int61(&mut self) -> INT61_W<29> { + pub fn int61(&mut self) -> INT61_W { INT61_W::new(self) } #[doc = "Bit 30 - Interrupt 62"] #[inline(always)] #[must_use] - pub fn int62(&mut self) -> INT62_W<30> { + pub fn int62(&mut self) -> INT62_W { INT62_W::new(self) } #[doc = "Bit 31 - Interrupt 63"] #[inline(always)] #[must_use] - pub fn int63(&mut self) -> INT63_W<31> { + pub fn int63(&mut self) -> INT63_W { INT63_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler1](index.html) module"] +#[doc = "Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICENABLER1_SPEC; impl crate::RegisterSpec for GICD_ICENABLER1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icenabler1::R](R) reader structure"] -impl crate::Readable for GICD_ICENABLER1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icenabler1::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icenabler1::R`](R) reader structure"] +impl crate::Readable for GICD_ICENABLER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icenabler1::W`](W) writer structure"] impl crate::Writable for GICD_ICENABLER1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler2.rs index 3428c57..7995d43 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler2.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler2.rs @@ -1,171 +1,135 @@ #[doc = "Register `GICD_ICENABLER2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICENABLER2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI0` reader - Software interrupt 0"] -pub type SWI0_R = crate::BitReader; +pub type SWI0_R = crate::BitReader; #[doc = "Field `SWI0` writer - Software interrupt 0"] -pub type SWI0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type SWI0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI1` reader - Software interrupt 1"] -pub type SWI1_R = crate::BitReader; +pub type SWI1_R = crate::BitReader; #[doc = "Field `SWI1` writer - Software interrupt 1"] -pub type SWI1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type SWI1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI2` reader - Software interrupt 2"] -pub type SWI2_R = crate::BitReader; +pub type SWI2_R = crate::BitReader; #[doc = "Field `SWI2` writer - Software interrupt 2"] -pub type SWI2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type SWI2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI3` reader - Software interrupt 3"] -pub type SWI3_R = crate::BitReader; +pub type SWI3_R = crate::BitReader; #[doc = "Field `SWI3` writer - Software interrupt 3"] -pub type SWI3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type SWI3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI4` reader - Software interrupt 4"] -pub type SWI4_R = crate::BitReader; +pub type SWI4_R = crate::BitReader; #[doc = "Field `SWI4` writer - Software interrupt 4"] -pub type SWI4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type SWI4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI5` reader - Software interrupt 5"] -pub type SWI5_R = crate::BitReader; +pub type SWI5_R = crate::BitReader; #[doc = "Field `SWI5` writer - Software interrupt 5"] -pub type SWI5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type SWI5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI6` reader - Software interrupt 6"] -pub type SWI6_R = crate::BitReader; +pub type SWI6_R = crate::BitReader; #[doc = "Field `SWI6` writer - Software interrupt 6"] -pub type SWI6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type SWI6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI7` reader - Software interrupt 7"] -pub type SWI7_R = crate::BitReader; +pub type SWI7_R = crate::BitReader; #[doc = "Field `SWI7` writer - Software interrupt 7"] -pub type SWI7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type SWI7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT80` reader - Interrupt 80"] -pub type INT80_R = crate::BitReader; +pub type INT80_R = crate::BitReader; #[doc = "Field `INT80` writer - Interrupt 80"] -pub type INT80_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT80_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT81` reader - Interrupt 81"] -pub type INT81_R = crate::BitReader; +pub type INT81_R = crate::BitReader; #[doc = "Field `INT81` writer - Interrupt 81"] -pub type INT81_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT81_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT82` reader - Interrupt 82"] -pub type INT82_R = crate::BitReader; +pub type INT82_R = crate::BitReader; #[doc = "Field `INT82` writer - Interrupt 82"] -pub type INT82_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT82_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT83` reader - Interrupt 83"] -pub type INT83_R = crate::BitReader; +pub type INT83_R = crate::BitReader; #[doc = "Field `INT83` writer - Interrupt 83"] -pub type INT83_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT83_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT84` reader - Interrupt 84"] -pub type INT84_R = crate::BitReader; +pub type INT84_R = crate::BitReader; #[doc = "Field `INT84` writer - Interrupt 84"] -pub type INT84_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT84_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT85` reader - Interrupt 85"] -pub type INT85_R = crate::BitReader; +pub type INT85_R = crate::BitReader; #[doc = "Field `INT85` writer - Interrupt 85"] -pub type INT85_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT85_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT86` reader - Interrupt 86"] -pub type INT86_R = crate::BitReader; +pub type INT86_R = crate::BitReader; #[doc = "Field `INT86` writer - Interrupt 86"] -pub type INT86_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT86_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT87` reader - Interrupt 87"] -pub type INT87_R = crate::BitReader; +pub type INT87_R = crate::BitReader; #[doc = "Field `INT87` writer - Interrupt 87"] -pub type INT87_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT87_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT88` reader - Interrupt 88"] -pub type INT88_R = crate::BitReader; +pub type INT88_R = crate::BitReader; #[doc = "Field `INT88` writer - Interrupt 88"] -pub type INT88_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT88_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT89` reader - Interrupt 89"] -pub type INT89_R = crate::BitReader; +pub type INT89_R = crate::BitReader; #[doc = "Field `INT89` writer - Interrupt 89"] -pub type INT89_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT89_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT90` reader - Interrupt 90"] -pub type INT90_R = crate::BitReader; +pub type INT90_R = crate::BitReader; #[doc = "Field `INT90` writer - Interrupt 90"] -pub type INT90_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT90_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT91` reader - Interrupt 91"] -pub type INT91_R = crate::BitReader; +pub type INT91_R = crate::BitReader; #[doc = "Field `INT91` writer - Interrupt 91"] -pub type INT91_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT91_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT92` reader - Interrupt 92"] -pub type INT92_R = crate::BitReader; +pub type INT92_R = crate::BitReader; #[doc = "Field `INT92` writer - Interrupt 92"] -pub type INT92_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT92_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT93` reader - Interrupt 93"] -pub type INT93_R = crate::BitReader; +pub type INT93_R = crate::BitReader; #[doc = "Field `INT93` writer - Interrupt 93"] -pub type INT93_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT93_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT94` reader - Interrupt 94"] -pub type INT94_R = crate::BitReader; +pub type INT94_R = crate::BitReader; #[doc = "Field `INT94` writer - Interrupt 94"] -pub type INT94_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT94_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT95` reader - Interrupt 95"] -pub type INT95_R = crate::BitReader; +pub type INT95_R = crate::BitReader; #[doc = "Field `INT95` writer - Interrupt 95"] -pub type INT95_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER2_SPEC, bool, O>; +pub type INT95_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -328,218 +292,268 @@ impl R { INT95_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICENABLER2") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .field("swi0", &format_args!("{}", self.swi0().bit())) + .field("swi1", &format_args!("{}", self.swi1().bit())) + .field("swi2", &format_args!("{}", self.swi2().bit())) + .field("swi3", &format_args!("{}", self.swi3().bit())) + .field("swi4", &format_args!("{}", self.swi4().bit())) + .field("swi5", &format_args!("{}", self.swi5().bit())) + .field("swi6", &format_args!("{}", self.swi6().bit())) + .field("swi7", &format_args!("{}", self.swi7().bit())) + .field("int80", &format_args!("{}", self.int80().bit())) + .field("int81", &format_args!("{}", self.int81().bit())) + .field("int82", &format_args!("{}", self.int82().bit())) + .field("int83", &format_args!("{}", self.int83().bit())) + .field("int84", &format_args!("{}", self.int84().bit())) + .field("int85", &format_args!("{}", self.int85().bit())) + .field("int86", &format_args!("{}", self.int86().bit())) + .field("int87", &format_args!("{}", self.int87().bit())) + .field("int88", &format_args!("{}", self.int88().bit())) + .field("int89", &format_args!("{}", self.int89().bit())) + .field("int90", &format_args!("{}", self.int90().bit())) + .field("int91", &format_args!("{}", self.int91().bit())) + .field("int92", &format_args!("{}", self.int92().bit())) + .field("int93", &format_args!("{}", self.int93().bit())) + .field("int94", &format_args!("{}", self.int94().bit())) + .field("int95", &format_args!("{}", self.int95().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } #[doc = "Bit 8 - Software interrupt 0"] #[inline(always)] #[must_use] - pub fn swi0(&mut self) -> SWI0_W<8> { + pub fn swi0(&mut self) -> SWI0_W { SWI0_W::new(self) } #[doc = "Bit 9 - Software interrupt 1"] #[inline(always)] #[must_use] - pub fn swi1(&mut self) -> SWI1_W<9> { + pub fn swi1(&mut self) -> SWI1_W { SWI1_W::new(self) } #[doc = "Bit 10 - Software interrupt 2"] #[inline(always)] #[must_use] - pub fn swi2(&mut self) -> SWI2_W<10> { + pub fn swi2(&mut self) -> SWI2_W { SWI2_W::new(self) } #[doc = "Bit 11 - Software interrupt 3"] #[inline(always)] #[must_use] - pub fn swi3(&mut self) -> SWI3_W<11> { + pub fn swi3(&mut self) -> SWI3_W { SWI3_W::new(self) } #[doc = "Bit 12 - Software interrupt 4"] #[inline(always)] #[must_use] - pub fn swi4(&mut self) -> SWI4_W<12> { + pub fn swi4(&mut self) -> SWI4_W { SWI4_W::new(self) } #[doc = "Bit 13 - Software interrupt 5"] #[inline(always)] #[must_use] - pub fn swi5(&mut self) -> SWI5_W<13> { + pub fn swi5(&mut self) -> SWI5_W { SWI5_W::new(self) } #[doc = "Bit 14 - Software interrupt 6"] #[inline(always)] #[must_use] - pub fn swi6(&mut self) -> SWI6_W<14> { + pub fn swi6(&mut self) -> SWI6_W { SWI6_W::new(self) } #[doc = "Bit 15 - Software interrupt 7"] #[inline(always)] #[must_use] - pub fn swi7(&mut self) -> SWI7_W<15> { + pub fn swi7(&mut self) -> SWI7_W { SWI7_W::new(self) } #[doc = "Bit 16 - Interrupt 80"] #[inline(always)] #[must_use] - pub fn int80(&mut self) -> INT80_W<16> { + pub fn int80(&mut self) -> INT80_W { INT80_W::new(self) } #[doc = "Bit 17 - Interrupt 81"] #[inline(always)] #[must_use] - pub fn int81(&mut self) -> INT81_W<17> { + pub fn int81(&mut self) -> INT81_W { INT81_W::new(self) } #[doc = "Bit 18 - Interrupt 82"] #[inline(always)] #[must_use] - pub fn int82(&mut self) -> INT82_W<18> { + pub fn int82(&mut self) -> INT82_W { INT82_W::new(self) } #[doc = "Bit 19 - Interrupt 83"] #[inline(always)] #[must_use] - pub fn int83(&mut self) -> INT83_W<19> { + pub fn int83(&mut self) -> INT83_W { INT83_W::new(self) } #[doc = "Bit 20 - Interrupt 84"] #[inline(always)] #[must_use] - pub fn int84(&mut self) -> INT84_W<20> { + pub fn int84(&mut self) -> INT84_W { INT84_W::new(self) } #[doc = "Bit 21 - Interrupt 85"] #[inline(always)] #[must_use] - pub fn int85(&mut self) -> INT85_W<21> { + pub fn int85(&mut self) -> INT85_W { INT85_W::new(self) } #[doc = "Bit 22 - Interrupt 86"] #[inline(always)] #[must_use] - pub fn int86(&mut self) -> INT86_W<22> { + pub fn int86(&mut self) -> INT86_W { INT86_W::new(self) } #[doc = "Bit 23 - Interrupt 87"] #[inline(always)] #[must_use] - pub fn int87(&mut self) -> INT87_W<23> { + pub fn int87(&mut self) -> INT87_W { INT87_W::new(self) } #[doc = "Bit 24 - Interrupt 88"] #[inline(always)] #[must_use] - pub fn int88(&mut self) -> INT88_W<24> { + pub fn int88(&mut self) -> INT88_W { INT88_W::new(self) } #[doc = "Bit 25 - Interrupt 89"] #[inline(always)] #[must_use] - pub fn int89(&mut self) -> INT89_W<25> { + pub fn int89(&mut self) -> INT89_W { INT89_W::new(self) } #[doc = "Bit 26 - Interrupt 90"] #[inline(always)] #[must_use] - pub fn int90(&mut self) -> INT90_W<26> { + pub fn int90(&mut self) -> INT90_W { INT90_W::new(self) } #[doc = "Bit 27 - Interrupt 91"] #[inline(always)] #[must_use] - pub fn int91(&mut self) -> INT91_W<27> { + pub fn int91(&mut self) -> INT91_W { INT91_W::new(self) } #[doc = "Bit 28 - Interrupt 92"] #[inline(always)] #[must_use] - pub fn int92(&mut self) -> INT92_W<28> { + pub fn int92(&mut self) -> INT92_W { INT92_W::new(self) } #[doc = "Bit 29 - Interrupt 93"] #[inline(always)] #[must_use] - pub fn int93(&mut self) -> INT93_W<29> { + pub fn int93(&mut self) -> INT93_W { INT93_W::new(self) } #[doc = "Bit 30 - Interrupt 94"] #[inline(always)] #[must_use] - pub fn int94(&mut self) -> INT94_W<30> { + pub fn int94(&mut self) -> INT94_W { INT94_W::new(self) } #[doc = "Bit 31 - Interrupt 95"] #[inline(always)] #[must_use] - pub fn int95(&mut self) -> INT95_W<31> { + pub fn int95(&mut self) -> INT95_W { INT95_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler2](index.html) module"] +#[doc = "Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICENABLER2_SPEC; impl crate::RegisterSpec for GICD_ICENABLER2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icenabler2::R](R) reader structure"] -impl crate::Readable for GICD_ICENABLER2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icenabler2::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icenabler2::R`](R) reader structure"] +impl crate::Readable for GICD_ICENABLER2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icenabler2::W`](W) writer structure"] impl crate::Writable for GICD_ICENABLER2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler3.rs index c043ac0..f2445ac 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler3.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler3.rs @@ -1,171 +1,135 @@ #[doc = "Register `GICD_ICENABLER3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICENABLER3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER3_SPEC, bool, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -328,218 +292,274 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICENABLER3") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bit 1 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<1> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bit 2 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<2> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bit 3 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<3> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } #[doc = "Bit 4 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<4> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bit 5 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<5> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bit 6 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<6> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bit 7 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<7> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } #[doc = "Bit 8 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<8> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bit 9 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<9> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 10 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<10> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bit 11 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } #[doc = "Bit 12 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bit 13 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bit 14 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bit 15 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } #[doc = "Bit 16 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<16> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bit 17 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<17> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 18 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<18> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 19 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<19> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 20 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<20> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 21 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<21> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 22 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<22> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 23 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } #[doc = "Bit 24 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bit 25 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<25> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bit 26 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<26> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bit 27 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<27> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } #[doc = "Bit 28 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<28> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<29> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bit 30 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<30> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bit 31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<31> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler3](index.html) module"] +#[doc = "Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICENABLER3_SPEC; impl crate::RegisterSpec for GICD_ICENABLER3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icenabler3::R](R) reader structure"] -impl crate::Readable for GICD_ICENABLER3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icenabler3::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icenabler3::R`](R) reader structure"] +impl crate::Readable for GICD_ICENABLER3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icenabler3::W`](W) writer structure"] impl crate::Writable for GICD_ICENABLER3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler4.rs index dbcf304..9fdc31d 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler4.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler4.rs @@ -1,173 +1,135 @@ #[doc = "Register `GICD_ICENABLER4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICENABLER4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type UART_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICENABLER4_SPEC, bool, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -330,218 +292,280 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICENABLER4") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bit 1 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<1> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bit 2 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<2> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bit 3 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<3> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } #[doc = "Bit 4 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<4> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bit 5 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bit 6 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bit 7 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } #[doc = "Bit 8 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bit 9 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bit 10 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bit 11 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } #[doc = "Bit 12 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<12> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bit 13 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bit 15 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<15> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } #[doc = "Bit 16 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<16> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bit 17 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bit 18 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bit 19 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } #[doc = "Bit 20 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bit 21 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<21> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bit 22 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<22> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bit 23 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } #[doc = "Bit 24 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<24> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bit 25 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<25> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bit 26 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bit 27 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<27> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } #[doc = "Bit 28 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<28> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bit 29 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<29> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bit 30 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<30> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bit 31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler4](index.html) module"] +#[doc = "Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICENABLER4_SPEC; impl crate::RegisterSpec for GICD_ICENABLER4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icenabler4::R](R) reader structure"] -impl crate::Readable for GICD_ICENABLER4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icenabler4::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icenabler4::R`](R) reader structure"] +impl crate::Readable for GICD_ICENABLER4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icenabler4::W`](W) writer structure"] impl crate::Writable for GICD_ICENABLER4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler5.rs index bcd5f42..20af349 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler5.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler5.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ICENABLER5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICENABLER5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT160` reader - Interrupt 160"] -pub type INT160_R = crate::BitReader; +pub type INT160_R = crate::BitReader; #[doc = "Field `INT160` writer - Interrupt 160"] -pub type INT160_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT160_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT161` reader - Interrupt 161"] -pub type INT161_R = crate::BitReader; +pub type INT161_R = crate::BitReader; #[doc = "Field `INT161` writer - Interrupt 161"] -pub type INT161_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT161_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT162` reader - Interrupt 162"] -pub type INT162_R = crate::BitReader; +pub type INT162_R = crate::BitReader; #[doc = "Field `INT162` writer - Interrupt 162"] -pub type INT162_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT162_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT163` reader - Interrupt 163"] -pub type INT163_R = crate::BitReader; +pub type INT163_R = crate::BitReader; #[doc = "Field `INT163` writer - Interrupt 163"] -pub type INT163_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT163_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT164` reader - Interrupt 164"] -pub type INT164_R = crate::BitReader; +pub type INT164_R = crate::BitReader; #[doc = "Field `INT164` writer - Interrupt 164"] -pub type INT164_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT164_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT165` reader - Interrupt 165"] -pub type INT165_R = crate::BitReader; +pub type INT165_R = crate::BitReader; #[doc = "Field `INT165` writer - Interrupt 165"] -pub type INT165_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT165_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT166` reader - Interrupt 166"] -pub type INT166_R = crate::BitReader; +pub type INT166_R = crate::BitReader; #[doc = "Field `INT166` writer - Interrupt 166"] -pub type INT166_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT166_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT167` reader - Interrupt 167"] -pub type INT167_R = crate::BitReader; +pub type INT167_R = crate::BitReader; #[doc = "Field `INT167` writer - Interrupt 167"] -pub type INT167_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT167_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT168` reader - Interrupt 168"] -pub type INT168_R = crate::BitReader; +pub type INT168_R = crate::BitReader; #[doc = "Field `INT168` writer - Interrupt 168"] -pub type INT168_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT168_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT169` reader - Interrupt 169"] -pub type INT169_R = crate::BitReader; +pub type INT169_R = crate::BitReader; #[doc = "Field `INT169` writer - Interrupt 169"] -pub type INT169_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT169_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT170` reader - Interrupt 170"] -pub type INT170_R = crate::BitReader; +pub type INT170_R = crate::BitReader; #[doc = "Field `INT170` writer - Interrupt 170"] -pub type INT170_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT170_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT171` reader - Interrupt 171"] -pub type INT171_R = crate::BitReader; +pub type INT171_R = crate::BitReader; #[doc = "Field `INT171` writer - Interrupt 171"] -pub type INT171_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT171_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT172` reader - Interrupt 172"] -pub type INT172_R = crate::BitReader; +pub type INT172_R = crate::BitReader; #[doc = "Field `INT172` writer - Interrupt 172"] -pub type INT172_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT172_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT173` reader - Interrupt 173"] -pub type INT173_R = crate::BitReader; +pub type INT173_R = crate::BitReader; #[doc = "Field `INT173` writer - Interrupt 173"] -pub type INT173_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT173_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT174` reader - Interrupt 174"] -pub type INT174_R = crate::BitReader; +pub type INT174_R = crate::BitReader; #[doc = "Field `INT174` writer - Interrupt 174"] -pub type INT174_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT174_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT175` reader - Interrupt 175"] -pub type INT175_R = crate::BitReader; +pub type INT175_R = crate::BitReader; #[doc = "Field `INT175` writer - Interrupt 175"] -pub type INT175_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT175_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT176` reader - Interrupt 176"] -pub type INT176_R = crate::BitReader; +pub type INT176_R = crate::BitReader; #[doc = "Field `INT176` writer - Interrupt 176"] -pub type INT176_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT176_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT177` reader - Interrupt 177"] -pub type INT177_R = crate::BitReader; +pub type INT177_R = crate::BitReader; #[doc = "Field `INT177` writer - Interrupt 177"] -pub type INT177_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT177_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT178` reader - Interrupt 178"] -pub type INT178_R = crate::BitReader; +pub type INT178_R = crate::BitReader; #[doc = "Field `INT178` writer - Interrupt 178"] -pub type INT178_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT178_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT179` reader - Interrupt 179"] -pub type INT179_R = crate::BitReader; +pub type INT179_R = crate::BitReader; #[doc = "Field `INT179` writer - Interrupt 179"] -pub type INT179_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT179_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT180` reader - Interrupt 180"] -pub type INT180_R = crate::BitReader; +pub type INT180_R = crate::BitReader; #[doc = "Field `INT180` writer - Interrupt 180"] -pub type INT180_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT180_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT181` reader - Interrupt 181"] -pub type INT181_R = crate::BitReader; +pub type INT181_R = crate::BitReader; #[doc = "Field `INT181` writer - Interrupt 181"] -pub type INT181_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT181_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT182` reader - Interrupt 182"] -pub type INT182_R = crate::BitReader; +pub type INT182_R = crate::BitReader; #[doc = "Field `INT182` writer - Interrupt 182"] -pub type INT182_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT182_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT183` reader - Interrupt 183"] -pub type INT183_R = crate::BitReader; +pub type INT183_R = crate::BitReader; #[doc = "Field `INT183` writer - Interrupt 183"] -pub type INT183_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT183_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT184` reader - Interrupt 184"] -pub type INT184_R = crate::BitReader; +pub type INT184_R = crate::BitReader; #[doc = "Field `INT184` writer - Interrupt 184"] -pub type INT184_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT184_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT185` reader - Interrupt 185"] -pub type INT185_R = crate::BitReader; +pub type INT185_R = crate::BitReader; #[doc = "Field `INT185` writer - Interrupt 185"] -pub type INT185_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT185_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT186` reader - Interrupt 186"] -pub type INT186_R = crate::BitReader; +pub type INT186_R = crate::BitReader; #[doc = "Field `INT186` writer - Interrupt 186"] -pub type INT186_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT186_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT187` reader - Interrupt 187"] -pub type INT187_R = crate::BitReader; +pub type INT187_R = crate::BitReader; #[doc = "Field `INT187` writer - Interrupt 187"] -pub type INT187_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT187_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT188` reader - Interrupt 188"] -pub type INT188_R = crate::BitReader; +pub type INT188_R = crate::BitReader; #[doc = "Field `INT188` writer - Interrupt 188"] -pub type INT188_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT188_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT189` reader - Interrupt 189"] -pub type INT189_R = crate::BitReader; +pub type INT189_R = crate::BitReader; #[doc = "Field `INT189` writer - Interrupt 189"] -pub type INT189_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT189_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT190` reader - Interrupt 190"] -pub type INT190_R = crate::BitReader; +pub type INT190_R = crate::BitReader; #[doc = "Field `INT190` writer - Interrupt 190"] -pub type INT190_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT190_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT191` reader - Interrupt 191"] -pub type INT191_R = crate::BitReader; +pub type INT191_R = crate::BitReader; #[doc = "Field `INT191` writer - Interrupt 191"] -pub type INT191_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER5_SPEC, bool, O>; +pub type INT191_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT191_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICENABLER5") + .field("int160", &format_args!("{}", self.int160().bit())) + .field("int161", &format_args!("{}", self.int161().bit())) + .field("int162", &format_args!("{}", self.int162().bit())) + .field("int163", &format_args!("{}", self.int163().bit())) + .field("int164", &format_args!("{}", self.int164().bit())) + .field("int165", &format_args!("{}", self.int165().bit())) + .field("int166", &format_args!("{}", self.int166().bit())) + .field("int167", &format_args!("{}", self.int167().bit())) + .field("int168", &format_args!("{}", self.int168().bit())) + .field("int169", &format_args!("{}", self.int169().bit())) + .field("int170", &format_args!("{}", self.int170().bit())) + .field("int171", &format_args!("{}", self.int171().bit())) + .field("int172", &format_args!("{}", self.int172().bit())) + .field("int173", &format_args!("{}", self.int173().bit())) + .field("int174", &format_args!("{}", self.int174().bit())) + .field("int175", &format_args!("{}", self.int175().bit())) + .field("int176", &format_args!("{}", self.int176().bit())) + .field("int177", &format_args!("{}", self.int177().bit())) + .field("int178", &format_args!("{}", self.int178().bit())) + .field("int179", &format_args!("{}", self.int179().bit())) + .field("int180", &format_args!("{}", self.int180().bit())) + .field("int181", &format_args!("{}", self.int181().bit())) + .field("int182", &format_args!("{}", self.int182().bit())) + .field("int183", &format_args!("{}", self.int183().bit())) + .field("int184", &format_args!("{}", self.int184().bit())) + .field("int185", &format_args!("{}", self.int185().bit())) + .field("int186", &format_args!("{}", self.int186().bit())) + .field("int187", &format_args!("{}", self.int187().bit())) + .field("int188", &format_args!("{}", self.int188().bit())) + .field("int189", &format_args!("{}", self.int189().bit())) + .field("int190", &format_args!("{}", self.int190().bit())) + .field("int191", &format_args!("{}", self.int191().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] #[must_use] - pub fn int160(&mut self) -> INT160_W<0> { + pub fn int160(&mut self) -> INT160_W { INT160_W::new(self) } #[doc = "Bit 1 - Interrupt 161"] #[inline(always)] #[must_use] - pub fn int161(&mut self) -> INT161_W<1> { + pub fn int161(&mut self) -> INT161_W { INT161_W::new(self) } #[doc = "Bit 2 - Interrupt 162"] #[inline(always)] #[must_use] - pub fn int162(&mut self) -> INT162_W<2> { + pub fn int162(&mut self) -> INT162_W { INT162_W::new(self) } #[doc = "Bit 3 - Interrupt 163"] #[inline(always)] #[must_use] - pub fn int163(&mut self) -> INT163_W<3> { + pub fn int163(&mut self) -> INT163_W { INT163_W::new(self) } #[doc = "Bit 4 - Interrupt 164"] #[inline(always)] #[must_use] - pub fn int164(&mut self) -> INT164_W<4> { + pub fn int164(&mut self) -> INT164_W { INT164_W::new(self) } #[doc = "Bit 5 - Interrupt 165"] #[inline(always)] #[must_use] - pub fn int165(&mut self) -> INT165_W<5> { + pub fn int165(&mut self) -> INT165_W { INT165_W::new(self) } #[doc = "Bit 6 - Interrupt 166"] #[inline(always)] #[must_use] - pub fn int166(&mut self) -> INT166_W<6> { + pub fn int166(&mut self) -> INT166_W { INT166_W::new(self) } #[doc = "Bit 7 - Interrupt 167"] #[inline(always)] #[must_use] - pub fn int167(&mut self) -> INT167_W<7> { + pub fn int167(&mut self) -> INT167_W { INT167_W::new(self) } #[doc = "Bit 8 - Interrupt 168"] #[inline(always)] #[must_use] - pub fn int168(&mut self) -> INT168_W<8> { + pub fn int168(&mut self) -> INT168_W { INT168_W::new(self) } #[doc = "Bit 9 - Interrupt 169"] #[inline(always)] #[must_use] - pub fn int169(&mut self) -> INT169_W<9> { + pub fn int169(&mut self) -> INT169_W { INT169_W::new(self) } #[doc = "Bit 10 - Interrupt 170"] #[inline(always)] #[must_use] - pub fn int170(&mut self) -> INT170_W<10> { + pub fn int170(&mut self) -> INT170_W { INT170_W::new(self) } #[doc = "Bit 11 - Interrupt 171"] #[inline(always)] #[must_use] - pub fn int171(&mut self) -> INT171_W<11> { + pub fn int171(&mut self) -> INT171_W { INT171_W::new(self) } #[doc = "Bit 12 - Interrupt 172"] #[inline(always)] #[must_use] - pub fn int172(&mut self) -> INT172_W<12> { + pub fn int172(&mut self) -> INT172_W { INT172_W::new(self) } #[doc = "Bit 13 - Interrupt 173"] #[inline(always)] #[must_use] - pub fn int173(&mut self) -> INT173_W<13> { + pub fn int173(&mut self) -> INT173_W { INT173_W::new(self) } #[doc = "Bit 14 - Interrupt 174"] #[inline(always)] #[must_use] - pub fn int174(&mut self) -> INT174_W<14> { + pub fn int174(&mut self) -> INT174_W { INT174_W::new(self) } #[doc = "Bit 15 - Interrupt 175"] #[inline(always)] #[must_use] - pub fn int175(&mut self) -> INT175_W<15> { + pub fn int175(&mut self) -> INT175_W { INT175_W::new(self) } #[doc = "Bit 16 - Interrupt 176"] #[inline(always)] #[must_use] - pub fn int176(&mut self) -> INT176_W<16> { + pub fn int176(&mut self) -> INT176_W { INT176_W::new(self) } #[doc = "Bit 17 - Interrupt 177"] #[inline(always)] #[must_use] - pub fn int177(&mut self) -> INT177_W<17> { + pub fn int177(&mut self) -> INT177_W { INT177_W::new(self) } #[doc = "Bit 18 - Interrupt 178"] #[inline(always)] #[must_use] - pub fn int178(&mut self) -> INT178_W<18> { + pub fn int178(&mut self) -> INT178_W { INT178_W::new(self) } #[doc = "Bit 19 - Interrupt 179"] #[inline(always)] #[must_use] - pub fn int179(&mut self) -> INT179_W<19> { + pub fn int179(&mut self) -> INT179_W { INT179_W::new(self) } #[doc = "Bit 20 - Interrupt 180"] #[inline(always)] #[must_use] - pub fn int180(&mut self) -> INT180_W<20> { + pub fn int180(&mut self) -> INT180_W { INT180_W::new(self) } #[doc = "Bit 21 - Interrupt 181"] #[inline(always)] #[must_use] - pub fn int181(&mut self) -> INT181_W<21> { + pub fn int181(&mut self) -> INT181_W { INT181_W::new(self) } #[doc = "Bit 22 - Interrupt 182"] #[inline(always)] #[must_use] - pub fn int182(&mut self) -> INT182_W<22> { + pub fn int182(&mut self) -> INT182_W { INT182_W::new(self) } #[doc = "Bit 23 - Interrupt 183"] #[inline(always)] #[must_use] - pub fn int183(&mut self) -> INT183_W<23> { + pub fn int183(&mut self) -> INT183_W { INT183_W::new(self) } #[doc = "Bit 24 - Interrupt 184"] #[inline(always)] #[must_use] - pub fn int184(&mut self) -> INT184_W<24> { + pub fn int184(&mut self) -> INT184_W { INT184_W::new(self) } #[doc = "Bit 25 - Interrupt 185"] #[inline(always)] #[must_use] - pub fn int185(&mut self) -> INT185_W<25> { + pub fn int185(&mut self) -> INT185_W { INT185_W::new(self) } #[doc = "Bit 26 - Interrupt 186"] #[inline(always)] #[must_use] - pub fn int186(&mut self) -> INT186_W<26> { + pub fn int186(&mut self) -> INT186_W { INT186_W::new(self) } #[doc = "Bit 27 - Interrupt 187"] #[inline(always)] #[must_use] - pub fn int187(&mut self) -> INT187_W<27> { + pub fn int187(&mut self) -> INT187_W { INT187_W::new(self) } #[doc = "Bit 28 - Interrupt 188"] #[inline(always)] #[must_use] - pub fn int188(&mut self) -> INT188_W<28> { + pub fn int188(&mut self) -> INT188_W { INT188_W::new(self) } #[doc = "Bit 29 - Interrupt 189"] #[inline(always)] #[must_use] - pub fn int189(&mut self) -> INT189_W<29> { + pub fn int189(&mut self) -> INT189_W { INT189_W::new(self) } #[doc = "Bit 30 - Interrupt 190"] #[inline(always)] #[must_use] - pub fn int190(&mut self) -> INT190_W<30> { + pub fn int190(&mut self) -> INT190_W { INT190_W::new(self) } #[doc = "Bit 31 - Interrupt 191"] #[inline(always)] #[must_use] - pub fn int191(&mut self) -> INT191_W<31> { + pub fn int191(&mut self) -> INT191_W { INT191_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler5](index.html) module"] +#[doc = "Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICENABLER5_SPEC; impl crate::RegisterSpec for GICD_ICENABLER5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icenabler5::R](R) reader structure"] -impl crate::Readable for GICD_ICENABLER5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icenabler5::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icenabler5::R`](R) reader structure"] +impl crate::Readable for GICD_ICENABLER5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icenabler5::W`](W) writer structure"] impl crate::Writable for GICD_ICENABLER5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler6.rs index 89efc95..19cee55 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler6.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icenabler/gicd_icenabler6.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ICENABLER6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICENABLER6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT192` reader - Interrupt 192"] -pub type INT192_R = crate::BitReader; +pub type INT192_R = crate::BitReader; #[doc = "Field `INT192` writer - Interrupt 192"] -pub type INT192_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT192_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT193` reader - Interrupt 193"] -pub type INT193_R = crate::BitReader; +pub type INT193_R = crate::BitReader; #[doc = "Field `INT193` writer - Interrupt 193"] -pub type INT193_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT193_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT194` reader - Interrupt 194"] -pub type INT194_R = crate::BitReader; +pub type INT194_R = crate::BitReader; #[doc = "Field `INT194` writer - Interrupt 194"] -pub type INT194_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT194_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT195` reader - Interrupt 195"] -pub type INT195_R = crate::BitReader; +pub type INT195_R = crate::BitReader; #[doc = "Field `INT195` writer - Interrupt 195"] -pub type INT195_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT195_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT196` reader - Interrupt 196"] -pub type INT196_R = crate::BitReader; +pub type INT196_R = crate::BitReader; #[doc = "Field `INT196` writer - Interrupt 196"] -pub type INT196_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT196_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT197` reader - Interrupt 197"] -pub type INT197_R = crate::BitReader; +pub type INT197_R = crate::BitReader; #[doc = "Field `INT197` writer - Interrupt 197"] -pub type INT197_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT197_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT198` reader - Interrupt 198"] -pub type INT198_R = crate::BitReader; +pub type INT198_R = crate::BitReader; #[doc = "Field `INT198` writer - Interrupt 198"] -pub type INT198_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT198_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT199` reader - Interrupt 199"] -pub type INT199_R = crate::BitReader; +pub type INT199_R = crate::BitReader; #[doc = "Field `INT199` writer - Interrupt 199"] -pub type INT199_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT199_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT200` reader - Interrupt 200"] -pub type INT200_R = crate::BitReader; +pub type INT200_R = crate::BitReader; #[doc = "Field `INT200` writer - Interrupt 200"] -pub type INT200_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT200_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT201` reader - Interrupt 201"] -pub type INT201_R = crate::BitReader; +pub type INT201_R = crate::BitReader; #[doc = "Field `INT201` writer - Interrupt 201"] -pub type INT201_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT201_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT202` reader - Interrupt 202"] -pub type INT202_R = crate::BitReader; +pub type INT202_R = crate::BitReader; #[doc = "Field `INT202` writer - Interrupt 202"] -pub type INT202_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT202_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT203` reader - Interrupt 203"] -pub type INT203_R = crate::BitReader; +pub type INT203_R = crate::BitReader; #[doc = "Field `INT203` writer - Interrupt 203"] -pub type INT203_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT203_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT204` reader - Interrupt 204"] -pub type INT204_R = crate::BitReader; +pub type INT204_R = crate::BitReader; #[doc = "Field `INT204` writer - Interrupt 204"] -pub type INT204_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT204_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT205` reader - Interrupt 205"] -pub type INT205_R = crate::BitReader; +pub type INT205_R = crate::BitReader; #[doc = "Field `INT205` writer - Interrupt 205"] -pub type INT205_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT205_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT206` reader - Interrupt 206"] -pub type INT206_R = crate::BitReader; +pub type INT206_R = crate::BitReader; #[doc = "Field `INT206` writer - Interrupt 206"] -pub type INT206_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT206_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT207` reader - Interrupt 207"] -pub type INT207_R = crate::BitReader; +pub type INT207_R = crate::BitReader; #[doc = "Field `INT207` writer - Interrupt 207"] -pub type INT207_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT207_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT208` reader - Interrupt 208"] -pub type INT208_R = crate::BitReader; +pub type INT208_R = crate::BitReader; #[doc = "Field `INT208` writer - Interrupt 208"] -pub type INT208_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT208_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT209` reader - Interrupt 209"] -pub type INT209_R = crate::BitReader; +pub type INT209_R = crate::BitReader; #[doc = "Field `INT209` writer - Interrupt 209"] -pub type INT209_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT209_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT210` reader - Interrupt 210"] -pub type INT210_R = crate::BitReader; +pub type INT210_R = crate::BitReader; #[doc = "Field `INT210` writer - Interrupt 210"] -pub type INT210_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT210_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT211` reader - Interrupt 211"] -pub type INT211_R = crate::BitReader; +pub type INT211_R = crate::BitReader; #[doc = "Field `INT211` writer - Interrupt 211"] -pub type INT211_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT211_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT212` reader - Interrupt 212"] -pub type INT212_R = crate::BitReader; +pub type INT212_R = crate::BitReader; #[doc = "Field `INT212` writer - Interrupt 212"] -pub type INT212_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT212_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT213` reader - Interrupt 213"] -pub type INT213_R = crate::BitReader; +pub type INT213_R = crate::BitReader; #[doc = "Field `INT213` writer - Interrupt 213"] -pub type INT213_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT213_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT214` reader - Interrupt 214"] -pub type INT214_R = crate::BitReader; +pub type INT214_R = crate::BitReader; #[doc = "Field `INT214` writer - Interrupt 214"] -pub type INT214_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT214_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT215` reader - Interrupt 215"] -pub type INT215_R = crate::BitReader; +pub type INT215_R = crate::BitReader; #[doc = "Field `INT215` writer - Interrupt 215"] -pub type INT215_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT215_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT216` reader - Interrupt 216"] -pub type INT216_R = crate::BitReader; +pub type INT216_R = crate::BitReader; #[doc = "Field `INT216` writer - Interrupt 216"] -pub type INT216_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT216_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT217` reader - Interrupt 217"] -pub type INT217_R = crate::BitReader; +pub type INT217_R = crate::BitReader; #[doc = "Field `INT217` writer - Interrupt 217"] -pub type INT217_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT217_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT218` reader - Interrupt 218"] -pub type INT218_R = crate::BitReader; +pub type INT218_R = crate::BitReader; #[doc = "Field `INT218` writer - Interrupt 218"] -pub type INT218_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT218_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT219` reader - Interrupt 219"] -pub type INT219_R = crate::BitReader; +pub type INT219_R = crate::BitReader; #[doc = "Field `INT219` writer - Interrupt 219"] -pub type INT219_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT219_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT220` reader - Interrupt 220"] -pub type INT220_R = crate::BitReader; +pub type INT220_R = crate::BitReader; #[doc = "Field `INT220` writer - Interrupt 220"] -pub type INT220_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT220_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT221` reader - Interrupt 221"] -pub type INT221_R = crate::BitReader; +pub type INT221_R = crate::BitReader; #[doc = "Field `INT221` writer - Interrupt 221"] -pub type INT221_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT221_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT222` reader - Interrupt 222"] -pub type INT222_R = crate::BitReader; +pub type INT222_R = crate::BitReader; #[doc = "Field `INT222` writer - Interrupt 222"] -pub type INT222_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT222_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT223` reader - Interrupt 223"] -pub type INT223_R = crate::BitReader; +pub type INT223_R = crate::BitReader; #[doc = "Field `INT223` writer - Interrupt 223"] -pub type INT223_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICENABLER6_SPEC, bool, O>; +pub type INT223_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT223_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICENABLER6") + .field("int192", &format_args!("{}", self.int192().bit())) + .field("int193", &format_args!("{}", self.int193().bit())) + .field("int194", &format_args!("{}", self.int194().bit())) + .field("int195", &format_args!("{}", self.int195().bit())) + .field("int196", &format_args!("{}", self.int196().bit())) + .field("int197", &format_args!("{}", self.int197().bit())) + .field("int198", &format_args!("{}", self.int198().bit())) + .field("int199", &format_args!("{}", self.int199().bit())) + .field("int200", &format_args!("{}", self.int200().bit())) + .field("int201", &format_args!("{}", self.int201().bit())) + .field("int202", &format_args!("{}", self.int202().bit())) + .field("int203", &format_args!("{}", self.int203().bit())) + .field("int204", &format_args!("{}", self.int204().bit())) + .field("int205", &format_args!("{}", self.int205().bit())) + .field("int206", &format_args!("{}", self.int206().bit())) + .field("int207", &format_args!("{}", self.int207().bit())) + .field("int208", &format_args!("{}", self.int208().bit())) + .field("int209", &format_args!("{}", self.int209().bit())) + .field("int210", &format_args!("{}", self.int210().bit())) + .field("int211", &format_args!("{}", self.int211().bit())) + .field("int212", &format_args!("{}", self.int212().bit())) + .field("int213", &format_args!("{}", self.int213().bit())) + .field("int214", &format_args!("{}", self.int214().bit())) + .field("int215", &format_args!("{}", self.int215().bit())) + .field("int216", &format_args!("{}", self.int216().bit())) + .field("int217", &format_args!("{}", self.int217().bit())) + .field("int218", &format_args!("{}", self.int218().bit())) + .field("int219", &format_args!("{}", self.int219().bit())) + .field("int220", &format_args!("{}", self.int220().bit())) + .field("int221", &format_args!("{}", self.int221().bit())) + .field("int222", &format_args!("{}", self.int222().bit())) + .field("int223", &format_args!("{}", self.int223().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] #[must_use] - pub fn int192(&mut self) -> INT192_W<0> { + pub fn int192(&mut self) -> INT192_W { INT192_W::new(self) } #[doc = "Bit 1 - Interrupt 193"] #[inline(always)] #[must_use] - pub fn int193(&mut self) -> INT193_W<1> { + pub fn int193(&mut self) -> INT193_W { INT193_W::new(self) } #[doc = "Bit 2 - Interrupt 194"] #[inline(always)] #[must_use] - pub fn int194(&mut self) -> INT194_W<2> { + pub fn int194(&mut self) -> INT194_W { INT194_W::new(self) } #[doc = "Bit 3 - Interrupt 195"] #[inline(always)] #[must_use] - pub fn int195(&mut self) -> INT195_W<3> { + pub fn int195(&mut self) -> INT195_W { INT195_W::new(self) } #[doc = "Bit 4 - Interrupt 196"] #[inline(always)] #[must_use] - pub fn int196(&mut self) -> INT196_W<4> { + pub fn int196(&mut self) -> INT196_W { INT196_W::new(self) } #[doc = "Bit 5 - Interrupt 197"] #[inline(always)] #[must_use] - pub fn int197(&mut self) -> INT197_W<5> { + pub fn int197(&mut self) -> INT197_W { INT197_W::new(self) } #[doc = "Bit 6 - Interrupt 198"] #[inline(always)] #[must_use] - pub fn int198(&mut self) -> INT198_W<6> { + pub fn int198(&mut self) -> INT198_W { INT198_W::new(self) } #[doc = "Bit 7 - Interrupt 199"] #[inline(always)] #[must_use] - pub fn int199(&mut self) -> INT199_W<7> { + pub fn int199(&mut self) -> INT199_W { INT199_W::new(self) } #[doc = "Bit 8 - Interrupt 200"] #[inline(always)] #[must_use] - pub fn int200(&mut self) -> INT200_W<8> { + pub fn int200(&mut self) -> INT200_W { INT200_W::new(self) } #[doc = "Bit 9 - Interrupt 201"] #[inline(always)] #[must_use] - pub fn int201(&mut self) -> INT201_W<9> { + pub fn int201(&mut self) -> INT201_W { INT201_W::new(self) } #[doc = "Bit 10 - Interrupt 202"] #[inline(always)] #[must_use] - pub fn int202(&mut self) -> INT202_W<10> { + pub fn int202(&mut self) -> INT202_W { INT202_W::new(self) } #[doc = "Bit 11 - Interrupt 203"] #[inline(always)] #[must_use] - pub fn int203(&mut self) -> INT203_W<11> { + pub fn int203(&mut self) -> INT203_W { INT203_W::new(self) } #[doc = "Bit 12 - Interrupt 204"] #[inline(always)] #[must_use] - pub fn int204(&mut self) -> INT204_W<12> { + pub fn int204(&mut self) -> INT204_W { INT204_W::new(self) } #[doc = "Bit 13 - Interrupt 205"] #[inline(always)] #[must_use] - pub fn int205(&mut self) -> INT205_W<13> { + pub fn int205(&mut self) -> INT205_W { INT205_W::new(self) } #[doc = "Bit 14 - Interrupt 206"] #[inline(always)] #[must_use] - pub fn int206(&mut self) -> INT206_W<14> { + pub fn int206(&mut self) -> INT206_W { INT206_W::new(self) } #[doc = "Bit 15 - Interrupt 207"] #[inline(always)] #[must_use] - pub fn int207(&mut self) -> INT207_W<15> { + pub fn int207(&mut self) -> INT207_W { INT207_W::new(self) } #[doc = "Bit 16 - Interrupt 208"] #[inline(always)] #[must_use] - pub fn int208(&mut self) -> INT208_W<16> { + pub fn int208(&mut self) -> INT208_W { INT208_W::new(self) } #[doc = "Bit 17 - Interrupt 209"] #[inline(always)] #[must_use] - pub fn int209(&mut self) -> INT209_W<17> { + pub fn int209(&mut self) -> INT209_W { INT209_W::new(self) } #[doc = "Bit 18 - Interrupt 210"] #[inline(always)] #[must_use] - pub fn int210(&mut self) -> INT210_W<18> { + pub fn int210(&mut self) -> INT210_W { INT210_W::new(self) } #[doc = "Bit 19 - Interrupt 211"] #[inline(always)] #[must_use] - pub fn int211(&mut self) -> INT211_W<19> { + pub fn int211(&mut self) -> INT211_W { INT211_W::new(self) } #[doc = "Bit 20 - Interrupt 212"] #[inline(always)] #[must_use] - pub fn int212(&mut self) -> INT212_W<20> { + pub fn int212(&mut self) -> INT212_W { INT212_W::new(self) } #[doc = "Bit 21 - Interrupt 213"] #[inline(always)] #[must_use] - pub fn int213(&mut self) -> INT213_W<21> { + pub fn int213(&mut self) -> INT213_W { INT213_W::new(self) } #[doc = "Bit 22 - Interrupt 214"] #[inline(always)] #[must_use] - pub fn int214(&mut self) -> INT214_W<22> { + pub fn int214(&mut self) -> INT214_W { INT214_W::new(self) } #[doc = "Bit 23 - Interrupt 215"] #[inline(always)] #[must_use] - pub fn int215(&mut self) -> INT215_W<23> { + pub fn int215(&mut self) -> INT215_W { INT215_W::new(self) } #[doc = "Bit 24 - Interrupt 216"] #[inline(always)] #[must_use] - pub fn int216(&mut self) -> INT216_W<24> { + pub fn int216(&mut self) -> INT216_W { INT216_W::new(self) } #[doc = "Bit 25 - Interrupt 217"] #[inline(always)] #[must_use] - pub fn int217(&mut self) -> INT217_W<25> { + pub fn int217(&mut self) -> INT217_W { INT217_W::new(self) } #[doc = "Bit 26 - Interrupt 218"] #[inline(always)] #[must_use] - pub fn int218(&mut self) -> INT218_W<26> { + pub fn int218(&mut self) -> INT218_W { INT218_W::new(self) } #[doc = "Bit 27 - Interrupt 219"] #[inline(always)] #[must_use] - pub fn int219(&mut self) -> INT219_W<27> { + pub fn int219(&mut self) -> INT219_W { INT219_W::new(self) } #[doc = "Bit 28 - Interrupt 220"] #[inline(always)] #[must_use] - pub fn int220(&mut self) -> INT220_W<28> { + pub fn int220(&mut self) -> INT220_W { INT220_W::new(self) } #[doc = "Bit 29 - Interrupt 221"] #[inline(always)] #[must_use] - pub fn int221(&mut self) -> INT221_W<29> { + pub fn int221(&mut self) -> INT221_W { INT221_W::new(self) } #[doc = "Bit 30 - Interrupt 222"] #[inline(always)] #[must_use] - pub fn int222(&mut self) -> INT222_W<30> { + pub fn int222(&mut self) -> INT222_W { INT222_W::new(self) } #[doc = "Bit 31 - Interrupt 223"] #[inline(always)] #[must_use] - pub fn int223(&mut self) -> INT223_W<31> { + pub fn int223(&mut self) -> INT223_W { INT223_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icenabler6](index.html) module"] +#[doc = "Interrupt Clear-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icenabler6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icenabler6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICENABLER6_SPEC; impl crate::RegisterSpec for GICD_ICENABLER6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icenabler6::R](R) reader structure"] -impl crate::Readable for GICD_ICENABLER6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icenabler6::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icenabler6::R`](R) reader structure"] +impl crate::Readable for GICD_ICENABLER6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icenabler6::W`](W) writer structure"] impl crate::Writable for GICD_ICENABLER6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr.rs index d60c5c5..cb2db86 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct GICD_ICFGR { #[doc = "0x00 - Interrupt Configuration 0 - 15"] pub gicd_icfgr0: GICD_ICFGR0, @@ -30,59 +31,73 @@ pub struct GICD_ICFGR { #[doc = "0x34 - Interrupt Configuration 208 - 223"] pub gicd_icfgr52: GICD_ICFGR52, } -#[doc = "GICD_ICFGR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR0 (rw) register accessor: Interrupt Configuration 0 - 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr0`] +module"] pub type GICD_ICFGR0 = crate::Reg; #[doc = "Interrupt Configuration 0 - 15"] pub mod gicd_icfgr0; -#[doc = "GICD_ICFGR4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR4 (rw) register accessor: Interrupt Configuration 16 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr4`] +module"] pub type GICD_ICFGR4 = crate::Reg; #[doc = "Interrupt Configuration 16 - 31"] pub mod gicd_icfgr4; -#[doc = "GICD_ICFGR8 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR8 (rw) register accessor: Interrupt Configuration 32 - 47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr8`] +module"] pub type GICD_ICFGR8 = crate::Reg; #[doc = "Interrupt Configuration 32 - 47"] pub mod gicd_icfgr8; -#[doc = "GICD_ICFGR12 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR12 (rw) register accessor: Interrupt Configuration 48 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr12`] +module"] pub type GICD_ICFGR12 = crate::Reg; #[doc = "Interrupt Configuration 48 - 63"] pub mod gicd_icfgr12; -#[doc = "GICD_ICFGR16 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR16 (rw) register accessor: Interrupt Configuration 64 - 79\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr16`] +module"] pub type GICD_ICFGR16 = crate::Reg; #[doc = "Interrupt Configuration 64 - 79"] pub mod gicd_icfgr16; -#[doc = "GICD_ICFGR20 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR20 (rw) register accessor: Interrupt Configuration 80 - 95\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr20`] +module"] pub type GICD_ICFGR20 = crate::Reg; #[doc = "Interrupt Configuration 80 - 95"] pub mod gicd_icfgr20; -#[doc = "GICD_ICFGR24 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR24 (rw) register accessor: Interrupt Configuration 96 - 111\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr24`] +module"] pub type GICD_ICFGR24 = crate::Reg; #[doc = "Interrupt Configuration 96 - 111"] pub mod gicd_icfgr24; -#[doc = "GICD_ICFGR28 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR28 (rw) register accessor: Interrupt Configuration 112 - 127\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr28::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr28`] +module"] pub type GICD_ICFGR28 = crate::Reg; #[doc = "Interrupt Configuration 112 - 127"] pub mod gicd_icfgr28; -#[doc = "GICD_ICFGR32 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR32 (rw) register accessor: Interrupt Configuration 128 - 143\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr32::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr32`] +module"] pub type GICD_ICFGR32 = crate::Reg; #[doc = "Interrupt Configuration 128 - 143"] pub mod gicd_icfgr32; -#[doc = "GICD_ICFGR36 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR36 (rw) register accessor: Interrupt Configuration 144 - 159\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr36::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr36`] +module"] pub type GICD_ICFGR36 = crate::Reg; #[doc = "Interrupt Configuration 144 - 159"] pub mod gicd_icfgr36; -#[doc = "GICD_ICFGR40 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR40 (rw) register accessor: Interrupt Configuration 160 - 175\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr40::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr40`] +module"] pub type GICD_ICFGR40 = crate::Reg; #[doc = "Interrupt Configuration 160 - 175"] pub mod gicd_icfgr40; -#[doc = "GICD_ICFGR44 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR44 (rw) register accessor: Interrupt Configuration 176 - 191\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr44::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr44`] +module"] pub type GICD_ICFGR44 = crate::Reg; #[doc = "Interrupt Configuration 176 - 191"] pub mod gicd_icfgr44; -#[doc = "GICD_ICFGR48 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR48 (rw) register accessor: Interrupt Configuration 192 - 207\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr48`] +module"] pub type GICD_ICFGR48 = crate::Reg; #[doc = "Interrupt Configuration 192 - 207"] pub mod gicd_icfgr48; -#[doc = "GICD_ICFGR52 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICFGR52 (rw) register accessor: Interrupt Configuration 208 - 223\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr52::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icfgr52`] +module"] pub type GICD_ICFGR52 = crate::Reg; #[doc = "Interrupt Configuration 208 - 223"] pub mod gicd_icfgr52; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr0.rs index 4603c16..cac6b6a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr0.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr0.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT0` reader - Interrupt 0"] pub type INT0_R = crate::BitReader; #[doc = "Interrupt 0\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl INT0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT0_A { + pub const fn variant(&self) -> INT0_A { match self.bits { false => INT0_A::LEVEL, true => INT0_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT0_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT0_A::EDGE } } #[doc = "Field `INT0` writer - Interrupt 0"] -pub type INT0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT0_A, O>; -impl<'a, const O: u8> INT0_W<'a, O> { +pub type INT0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT0_A>; +impl<'a, REG, const O: u8> INT0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT0_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT0_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl INT1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT1_A { + pub const fn variant(&self) -> INT1_A { match self.bits { false => INT1_A::LEVEL, true => INT1_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT1_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT1_A::EDGE } } #[doc = "Field `INT1` writer - Interrupt 1"] -pub type INT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT1_A, O>; -impl<'a, const O: u8> INT1_W<'a, O> { +pub type INT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT1_A>; +impl<'a, REG, const O: u8> INT1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT1_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT1_A::EDGE) } } @@ -153,34 +127,37 @@ impl From for bool { impl INT2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT2_A { + pub const fn variant(&self) -> INT2_A { match self.bits { false => INT2_A::LEVEL, true => INT2_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT2_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT2_A::EDGE } } #[doc = "Field `INT2` writer - Interrupt 2"] -pub type INT2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT2_A, O>; -impl<'a, const O: u8> INT2_W<'a, O> { +pub type INT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT2_A>; +impl<'a, REG, const O: u8> INT2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT2_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT2_A::EDGE) } } @@ -203,34 +180,37 @@ impl From for bool { impl INT3_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT3_A { + pub const fn variant(&self) -> INT3_A { match self.bits { false => INT3_A::LEVEL, true => INT3_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT3_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT3_A::EDGE } } #[doc = "Field `INT3` writer - Interrupt 3"] -pub type INT3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT3_A, O>; -impl<'a, const O: u8> INT3_W<'a, O> { +pub type INT3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT3_A>; +impl<'a, REG, const O: u8> INT3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT3_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT3_A::EDGE) } } @@ -253,34 +233,37 @@ impl From for bool { impl INT4_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT4_A { + pub const fn variant(&self) -> INT4_A { match self.bits { false => INT4_A::LEVEL, true => INT4_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT4_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT4_A::EDGE } } #[doc = "Field `INT4` writer - Interrupt 4"] -pub type INT4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT4_A, O>; -impl<'a, const O: u8> INT4_W<'a, O> { +pub type INT4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT4_A>; +impl<'a, REG, const O: u8> INT4_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT4_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT4_A::EDGE) } } @@ -303,34 +286,37 @@ impl From for bool { impl INT5_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT5_A { + pub const fn variant(&self) -> INT5_A { match self.bits { false => INT5_A::LEVEL, true => INT5_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT5_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT5_A::EDGE } } #[doc = "Field `INT5` writer - Interrupt 5"] -pub type INT5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT5_A, O>; -impl<'a, const O: u8> INT5_W<'a, O> { +pub type INT5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT5_A>; +impl<'a, REG, const O: u8> INT5_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT5_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT5_A::EDGE) } } @@ -353,34 +339,37 @@ impl From for bool { impl INT6_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT6_A { + pub const fn variant(&self) -> INT6_A { match self.bits { false => INT6_A::LEVEL, true => INT6_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT6_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT6_A::EDGE } } #[doc = "Field `INT6` writer - Interrupt 6"] -pub type INT6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT6_A, O>; -impl<'a, const O: u8> INT6_W<'a, O> { +pub type INT6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT6_A>; +impl<'a, REG, const O: u8> INT6_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT6_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT6_A::EDGE) } } @@ -403,34 +392,37 @@ impl From for bool { impl INT7_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT7_A { + pub const fn variant(&self) -> INT7_A { match self.bits { false => INT7_A::LEVEL, true => INT7_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT7_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT7_A::EDGE } } #[doc = "Field `INT7` writer - Interrupt 7"] -pub type INT7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT7_A, O>; -impl<'a, const O: u8> INT7_W<'a, O> { +pub type INT7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT7_A>; +impl<'a, REG, const O: u8> INT7_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT7_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT7_A::EDGE) } } @@ -453,34 +445,37 @@ impl From for bool { impl INT8_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT8_A { + pub const fn variant(&self) -> INT8_A { match self.bits { false => INT8_A::LEVEL, true => INT8_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT8_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT8_A::EDGE } } #[doc = "Field `INT8` writer - Interrupt 8"] -pub type INT8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT8_A, O>; -impl<'a, const O: u8> INT8_W<'a, O> { +pub type INT8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT8_A>; +impl<'a, REG, const O: u8> INT8_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT8_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT8_A::EDGE) } } @@ -503,34 +498,37 @@ impl From for bool { impl INT9_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT9_A { + pub const fn variant(&self) -> INT9_A { match self.bits { false => INT9_A::LEVEL, true => INT9_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT9_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT9_A::EDGE } } #[doc = "Field `INT9` writer - Interrupt 9"] -pub type INT9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT9_A, O>; -impl<'a, const O: u8> INT9_W<'a, O> { +pub type INT9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT9_A>; +impl<'a, REG, const O: u8> INT9_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT9_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT9_A::EDGE) } } @@ -553,34 +551,37 @@ impl From for bool { impl INT10_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT10_A { + pub const fn variant(&self) -> INT10_A { match self.bits { false => INT10_A::LEVEL, true => INT10_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT10_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT10_A::EDGE } } #[doc = "Field `INT10` writer - Interrupt 10"] -pub type INT10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT10_A, O>; -impl<'a, const O: u8> INT10_W<'a, O> { +pub type INT10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT10_A>; +impl<'a, REG, const O: u8> INT10_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT10_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT10_A::EDGE) } } @@ -603,34 +604,37 @@ impl From for bool { impl INT11_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT11_A { + pub const fn variant(&self) -> INT11_A { match self.bits { false => INT11_A::LEVEL, true => INT11_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT11_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT11_A::EDGE } } #[doc = "Field `INT11` writer - Interrupt 11"] -pub type INT11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT11_A, O>; -impl<'a, const O: u8> INT11_W<'a, O> { +pub type INT11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT11_A>; +impl<'a, REG, const O: u8> INT11_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT11_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT11_A::EDGE) } } @@ -653,34 +657,37 @@ impl From for bool { impl INT12_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT12_A { + pub const fn variant(&self) -> INT12_A { match self.bits { false => INT12_A::LEVEL, true => INT12_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT12_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT12_A::EDGE } } #[doc = "Field `INT12` writer - Interrupt 12"] -pub type INT12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT12_A, O>; -impl<'a, const O: u8> INT12_W<'a, O> { +pub type INT12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT12_A>; +impl<'a, REG, const O: u8> INT12_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT12_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT12_A::EDGE) } } @@ -703,34 +710,37 @@ impl From for bool { impl INT13_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT13_A { + pub const fn variant(&self) -> INT13_A { match self.bits { false => INT13_A::LEVEL, true => INT13_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT13_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT13_A::EDGE } } #[doc = "Field `INT13` writer - Interrupt 13"] -pub type INT13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT13_A, O>; -impl<'a, const O: u8> INT13_W<'a, O> { +pub type INT13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT13_A>; +impl<'a, REG, const O: u8> INT13_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT13_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT13_A::EDGE) } } @@ -753,34 +763,37 @@ impl From for bool { impl INT14_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT14_A { + pub const fn variant(&self) -> INT14_A { match self.bits { false => INT14_A::LEVEL, true => INT14_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT14_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT14_A::EDGE } } #[doc = "Field `INT14` writer - Interrupt 14"] -pub type INT14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT14_A, O>; -impl<'a, const O: u8> INT14_W<'a, O> { +pub type INT14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT14_A>; +impl<'a, REG, const O: u8> INT14_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT14_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT14_A::EDGE) } } @@ -803,34 +816,37 @@ impl From for bool { impl INT15_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT15_A { + pub const fn variant(&self) -> INT15_A { match self.bits { false => INT15_A::LEVEL, true => INT15_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT15_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT15_A::EDGE } } #[doc = "Field `INT15` writer - Interrupt 15"] -pub type INT15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR0_SPEC, INT15_A, O>; -impl<'a, const O: u8> INT15_W<'a, O> { +pub type INT15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT15_A>; +impl<'a, REG, const O: u8> INT15_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT15_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT15_A::EDGE) } } @@ -916,122 +932,150 @@ impl R { INT15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR0") + .field("int0", &format_args!("{}", self.int0().bit())) + .field("int1", &format_args!("{}", self.int1().bit())) + .field("int2", &format_args!("{}", self.int2().bit())) + .field("int3", &format_args!("{}", self.int3().bit())) + .field("int4", &format_args!("{}", self.int4().bit())) + .field("int5", &format_args!("{}", self.int5().bit())) + .field("int6", &format_args!("{}", self.int6().bit())) + .field("int7", &format_args!("{}", self.int7().bit())) + .field("int8", &format_args!("{}", self.int8().bit())) + .field("int9", &format_args!("{}", self.int9().bit())) + .field("int10", &format_args!("{}", self.int10().bit())) + .field("int11", &format_args!("{}", self.int11().bit())) + .field("int12", &format_args!("{}", self.int12().bit())) + .field("int13", &format_args!("{}", self.int13().bit())) + .field("int14", &format_args!("{}", self.int14().bit())) + .field("int15", &format_args!("{}", self.int15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Interrupt 0"] #[inline(always)] #[must_use] - pub fn int0(&mut self) -> INT0_W<1> { + pub fn int0(&mut self) -> INT0_W { INT0_W::new(self) } #[doc = "Bit 3 - Interrupt 1"] #[inline(always)] #[must_use] - pub fn int1(&mut self) -> INT1_W<3> { + pub fn int1(&mut self) -> INT1_W { INT1_W::new(self) } #[doc = "Bit 5 - Interrupt 2"] #[inline(always)] #[must_use] - pub fn int2(&mut self) -> INT2_W<5> { + pub fn int2(&mut self) -> INT2_W { INT2_W::new(self) } #[doc = "Bit 7 - Interrupt 3"] #[inline(always)] #[must_use] - pub fn int3(&mut self) -> INT3_W<7> { + pub fn int3(&mut self) -> INT3_W { INT3_W::new(self) } #[doc = "Bit 9 - Interrupt 4"] #[inline(always)] #[must_use] - pub fn int4(&mut self) -> INT4_W<9> { + pub fn int4(&mut self) -> INT4_W { INT4_W::new(self) } #[doc = "Bit 11 - Interrupt 5"] #[inline(always)] #[must_use] - pub fn int5(&mut self) -> INT5_W<11> { + pub fn int5(&mut self) -> INT5_W { INT5_W::new(self) } #[doc = "Bit 13 - Interrupt 6"] #[inline(always)] #[must_use] - pub fn int6(&mut self) -> INT6_W<13> { + pub fn int6(&mut self) -> INT6_W { INT6_W::new(self) } #[doc = "Bit 15 - Interrupt 7"] #[inline(always)] #[must_use] - pub fn int7(&mut self) -> INT7_W<15> { + pub fn int7(&mut self) -> INT7_W { INT7_W::new(self) } #[doc = "Bit 17 - Interrupt 8"] #[inline(always)] #[must_use] - pub fn int8(&mut self) -> INT8_W<17> { + pub fn int8(&mut self) -> INT8_W { INT8_W::new(self) } #[doc = "Bit 19 - Interrupt 9"] #[inline(always)] #[must_use] - pub fn int9(&mut self) -> INT9_W<19> { + pub fn int9(&mut self) -> INT9_W { INT9_W::new(self) } #[doc = "Bit 21 - Interrupt 10"] #[inline(always)] #[must_use] - pub fn int10(&mut self) -> INT10_W<21> { + pub fn int10(&mut self) -> INT10_W { INT10_W::new(self) } #[doc = "Bit 23 - Interrupt 11"] #[inline(always)] #[must_use] - pub fn int11(&mut self) -> INT11_W<23> { + pub fn int11(&mut self) -> INT11_W { INT11_W::new(self) } #[doc = "Bit 25 - Interrupt 12"] #[inline(always)] #[must_use] - pub fn int12(&mut self) -> INT12_W<25> { + pub fn int12(&mut self) -> INT12_W { INT12_W::new(self) } #[doc = "Bit 27 - Interrupt 13"] #[inline(always)] #[must_use] - pub fn int13(&mut self) -> INT13_W<27> { + pub fn int13(&mut self) -> INT13_W { INT13_W::new(self) } #[doc = "Bit 29 - Interrupt 14"] #[inline(always)] #[must_use] - pub fn int14(&mut self) -> INT14_W<29> { + pub fn int14(&mut self) -> INT14_W { INT14_W::new(self) } #[doc = "Bit 31 - Interrupt 15"] #[inline(always)] #[must_use] - pub fn int15(&mut self) -> INT15_W<31> { + pub fn int15(&mut self) -> INT15_W { INT15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 0 - 15\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr0](index.html) module"] +#[doc = "Interrupt Configuration 0 - 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR0_SPEC; impl crate::RegisterSpec for GICD_ICFGR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr0::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr0::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr0::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr0::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr12.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr12.rs index 7cdc4e5..5ecdb1f 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr12.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr12.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR12` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR12` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT48` reader - Interrupt 48"] pub type INT48_R = crate::BitReader; #[doc = "Interrupt 48\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl INT48_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT48_A { + pub const fn variant(&self) -> INT48_A { match self.bits { false => INT48_A::LEVEL, true => INT48_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT48_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT48_A::EDGE } } #[doc = "Field `INT48` writer - Interrupt 48"] -pub type INT48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT48_A, O>; -impl<'a, const O: u8> INT48_W<'a, O> { +pub type INT48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT48_A>; +impl<'a, REG, const O: u8> INT48_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT48_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT48_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl INT49_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT49_A { + pub const fn variant(&self) -> INT49_A { match self.bits { false => INT49_A::LEVEL, true => INT49_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT49_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT49_A::EDGE } } #[doc = "Field `INT49` writer - Interrupt 49"] -pub type INT49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT49_A, O>; -impl<'a, const O: u8> INT49_W<'a, O> { +pub type INT49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT49_A>; +impl<'a, REG, const O: u8> INT49_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT49_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT49_A::EDGE) } } @@ -153,34 +127,37 @@ impl From for bool { impl INT50_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT50_A { + pub const fn variant(&self) -> INT50_A { match self.bits { false => INT50_A::LEVEL, true => INT50_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT50_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT50_A::EDGE } } #[doc = "Field `INT50` writer - Interrupt 50"] -pub type INT50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT50_A, O>; -impl<'a, const O: u8> INT50_W<'a, O> { +pub type INT50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT50_A>; +impl<'a, REG, const O: u8> INT50_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT50_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT50_A::EDGE) } } @@ -203,34 +180,37 @@ impl From for bool { impl INT51_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT51_A { + pub const fn variant(&self) -> INT51_A { match self.bits { false => INT51_A::LEVEL, true => INT51_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT51_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT51_A::EDGE } } #[doc = "Field `INT51` writer - Interrupt 51"] -pub type INT51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT51_A, O>; -impl<'a, const O: u8> INT51_W<'a, O> { +pub type INT51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT51_A>; +impl<'a, REG, const O: u8> INT51_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT51_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT51_A::EDGE) } } @@ -253,34 +233,37 @@ impl From for bool { impl INT52_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT52_A { + pub const fn variant(&self) -> INT52_A { match self.bits { false => INT52_A::LEVEL, true => INT52_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT52_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT52_A::EDGE } } #[doc = "Field `INT52` writer - Interrupt 52"] -pub type INT52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT52_A, O>; -impl<'a, const O: u8> INT52_W<'a, O> { +pub type INT52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT52_A>; +impl<'a, REG, const O: u8> INT52_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT52_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT52_A::EDGE) } } @@ -303,34 +286,37 @@ impl From for bool { impl INT53_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT53_A { + pub const fn variant(&self) -> INT53_A { match self.bits { false => INT53_A::LEVEL, true => INT53_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT53_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT53_A::EDGE } } #[doc = "Field `INT53` writer - Interrupt 53"] -pub type INT53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT53_A, O>; -impl<'a, const O: u8> INT53_W<'a, O> { +pub type INT53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT53_A>; +impl<'a, REG, const O: u8> INT53_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT53_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT53_A::EDGE) } } @@ -353,34 +339,37 @@ impl From for bool { impl INT54_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT54_A { + pub const fn variant(&self) -> INT54_A { match self.bits { false => INT54_A::LEVEL, true => INT54_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT54_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT54_A::EDGE } } #[doc = "Field `INT54` writer - Interrupt 54"] -pub type INT54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT54_A, O>; -impl<'a, const O: u8> INT54_W<'a, O> { +pub type INT54_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT54_A>; +impl<'a, REG, const O: u8> INT54_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT54_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT54_A::EDGE) } } @@ -403,34 +392,37 @@ impl From for bool { impl INT55_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT55_A { + pub const fn variant(&self) -> INT55_A { match self.bits { false => INT55_A::LEVEL, true => INT55_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT55_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT55_A::EDGE } } #[doc = "Field `INT55` writer - Interrupt 55"] -pub type INT55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT55_A, O>; -impl<'a, const O: u8> INT55_W<'a, O> { +pub type INT55_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT55_A>; +impl<'a, REG, const O: u8> INT55_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT55_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT55_A::EDGE) } } @@ -453,34 +445,37 @@ impl From for bool { impl INT56_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT56_A { + pub const fn variant(&self) -> INT56_A { match self.bits { false => INT56_A::LEVEL, true => INT56_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT56_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT56_A::EDGE } } #[doc = "Field `INT56` writer - Interrupt 56"] -pub type INT56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT56_A, O>; -impl<'a, const O: u8> INT56_W<'a, O> { +pub type INT56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT56_A>; +impl<'a, REG, const O: u8> INT56_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT56_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT56_A::EDGE) } } @@ -503,34 +498,37 @@ impl From for bool { impl INT57_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT57_A { + pub const fn variant(&self) -> INT57_A { match self.bits { false => INT57_A::LEVEL, true => INT57_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT57_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT57_A::EDGE } } #[doc = "Field `INT57` writer - Interrupt 57"] -pub type INT57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT57_A, O>; -impl<'a, const O: u8> INT57_W<'a, O> { +pub type INT57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT57_A>; +impl<'a, REG, const O: u8> INT57_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT57_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT57_A::EDGE) } } @@ -553,34 +551,37 @@ impl From for bool { impl INT58_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT58_A { + pub const fn variant(&self) -> INT58_A { match self.bits { false => INT58_A::LEVEL, true => INT58_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT58_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT58_A::EDGE } } #[doc = "Field `INT58` writer - Interrupt 58"] -pub type INT58_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT58_A, O>; -impl<'a, const O: u8> INT58_W<'a, O> { +pub type INT58_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT58_A>; +impl<'a, REG, const O: u8> INT58_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT58_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT58_A::EDGE) } } @@ -603,34 +604,37 @@ impl From for bool { impl INT59_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT59_A { + pub const fn variant(&self) -> INT59_A { match self.bits { false => INT59_A::LEVEL, true => INT59_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT59_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT59_A::EDGE } } #[doc = "Field `INT59` writer - Interrupt 59"] -pub type INT59_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT59_A, O>; -impl<'a, const O: u8> INT59_W<'a, O> { +pub type INT59_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT59_A>; +impl<'a, REG, const O: u8> INT59_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT59_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT59_A::EDGE) } } @@ -653,34 +657,37 @@ impl From for bool { impl INT60_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT60_A { + pub const fn variant(&self) -> INT60_A { match self.bits { false => INT60_A::LEVEL, true => INT60_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT60_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT60_A::EDGE } } #[doc = "Field `INT60` writer - Interrupt 60"] -pub type INT60_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT60_A, O>; -impl<'a, const O: u8> INT60_W<'a, O> { +pub type INT60_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT60_A>; +impl<'a, REG, const O: u8> INT60_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT60_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT60_A::EDGE) } } @@ -703,34 +710,37 @@ impl From for bool { impl INT61_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT61_A { + pub const fn variant(&self) -> INT61_A { match self.bits { false => INT61_A::LEVEL, true => INT61_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT61_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT61_A::EDGE } } #[doc = "Field `INT61` writer - Interrupt 61"] -pub type INT61_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT61_A, O>; -impl<'a, const O: u8> INT61_W<'a, O> { +pub type INT61_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT61_A>; +impl<'a, REG, const O: u8> INT61_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT61_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT61_A::EDGE) } } @@ -753,34 +763,37 @@ impl From for bool { impl INT62_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT62_A { + pub const fn variant(&self) -> INT62_A { match self.bits { false => INT62_A::LEVEL, true => INT62_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT62_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT62_A::EDGE } } #[doc = "Field `INT62` writer - Interrupt 62"] -pub type INT62_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT62_A, O>; -impl<'a, const O: u8> INT62_W<'a, O> { +pub type INT62_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT62_A>; +impl<'a, REG, const O: u8> INT62_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT62_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT62_A::EDGE) } } @@ -803,34 +816,37 @@ impl From for bool { impl INT63_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT63_A { + pub const fn variant(&self) -> INT63_A { match self.bits { false => INT63_A::LEVEL, true => INT63_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT63_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT63_A::EDGE } } #[doc = "Field `INT63` writer - Interrupt 63"] -pub type INT63_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR12_SPEC, INT63_A, O>; -impl<'a, const O: u8> INT63_W<'a, O> { +pub type INT63_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT63_A>; +impl<'a, REG, const O: u8> INT63_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT63_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT63_A::EDGE) } } @@ -916,122 +932,150 @@ impl R { INT63_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR12") + .field("int48", &format_args!("{}", self.int48().bit())) + .field("int49", &format_args!("{}", self.int49().bit())) + .field("int50", &format_args!("{}", self.int50().bit())) + .field("int51", &format_args!("{}", self.int51().bit())) + .field("int52", &format_args!("{}", self.int52().bit())) + .field("int53", &format_args!("{}", self.int53().bit())) + .field("int54", &format_args!("{}", self.int54().bit())) + .field("int55", &format_args!("{}", self.int55().bit())) + .field("int56", &format_args!("{}", self.int56().bit())) + .field("int57", &format_args!("{}", self.int57().bit())) + .field("int58", &format_args!("{}", self.int58().bit())) + .field("int59", &format_args!("{}", self.int59().bit())) + .field("int60", &format_args!("{}", self.int60().bit())) + .field("int61", &format_args!("{}", self.int61().bit())) + .field("int62", &format_args!("{}", self.int62().bit())) + .field("int63", &format_args!("{}", self.int63().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Interrupt 48"] #[inline(always)] #[must_use] - pub fn int48(&mut self) -> INT48_W<1> { + pub fn int48(&mut self) -> INT48_W { INT48_W::new(self) } #[doc = "Bit 3 - Interrupt 49"] #[inline(always)] #[must_use] - pub fn int49(&mut self) -> INT49_W<3> { + pub fn int49(&mut self) -> INT49_W { INT49_W::new(self) } #[doc = "Bit 5 - Interrupt 50"] #[inline(always)] #[must_use] - pub fn int50(&mut self) -> INT50_W<5> { + pub fn int50(&mut self) -> INT50_W { INT50_W::new(self) } #[doc = "Bit 7 - Interrupt 51"] #[inline(always)] #[must_use] - pub fn int51(&mut self) -> INT51_W<7> { + pub fn int51(&mut self) -> INT51_W { INT51_W::new(self) } #[doc = "Bit 9 - Interrupt 52"] #[inline(always)] #[must_use] - pub fn int52(&mut self) -> INT52_W<9> { + pub fn int52(&mut self) -> INT52_W { INT52_W::new(self) } #[doc = "Bit 11 - Interrupt 53"] #[inline(always)] #[must_use] - pub fn int53(&mut self) -> INT53_W<11> { + pub fn int53(&mut self) -> INT53_W { INT53_W::new(self) } #[doc = "Bit 13 - Interrupt 54"] #[inline(always)] #[must_use] - pub fn int54(&mut self) -> INT54_W<13> { + pub fn int54(&mut self) -> INT54_W { INT54_W::new(self) } #[doc = "Bit 15 - Interrupt 55"] #[inline(always)] #[must_use] - pub fn int55(&mut self) -> INT55_W<15> { + pub fn int55(&mut self) -> INT55_W { INT55_W::new(self) } #[doc = "Bit 17 - Interrupt 56"] #[inline(always)] #[must_use] - pub fn int56(&mut self) -> INT56_W<17> { + pub fn int56(&mut self) -> INT56_W { INT56_W::new(self) } #[doc = "Bit 19 - Interrupt 57"] #[inline(always)] #[must_use] - pub fn int57(&mut self) -> INT57_W<19> { + pub fn int57(&mut self) -> INT57_W { INT57_W::new(self) } #[doc = "Bit 21 - Interrupt 58"] #[inline(always)] #[must_use] - pub fn int58(&mut self) -> INT58_W<21> { + pub fn int58(&mut self) -> INT58_W { INT58_W::new(self) } #[doc = "Bit 23 - Interrupt 59"] #[inline(always)] #[must_use] - pub fn int59(&mut self) -> INT59_W<23> { + pub fn int59(&mut self) -> INT59_W { INT59_W::new(self) } #[doc = "Bit 25 - Interrupt 60"] #[inline(always)] #[must_use] - pub fn int60(&mut self) -> INT60_W<25> { + pub fn int60(&mut self) -> INT60_W { INT60_W::new(self) } #[doc = "Bit 27 - Interrupt 61"] #[inline(always)] #[must_use] - pub fn int61(&mut self) -> INT61_W<27> { + pub fn int61(&mut self) -> INT61_W { INT61_W::new(self) } #[doc = "Bit 29 - Interrupt 62"] #[inline(always)] #[must_use] - pub fn int62(&mut self) -> INT62_W<29> { + pub fn int62(&mut self) -> INT62_W { INT62_W::new(self) } #[doc = "Bit 31 - Interrupt 63"] #[inline(always)] #[must_use] - pub fn int63(&mut self) -> INT63_W<31> { + pub fn int63(&mut self) -> INT63_W { INT63_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 48 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr12](index.html) module"] +#[doc = "Interrupt Configuration 48 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR12_SPEC; impl crate::RegisterSpec for GICD_ICFGR12_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr12::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR12_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr12::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr12::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr12::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR12_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr16.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr16.rs index 0131fb6..c4b7b18 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr16.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr16.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR16` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR16` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] pub type TIMER_R = crate::BitReader; #[doc = "ARMC Timer\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl TIMER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TIMER_A { + pub const fn variant(&self) -> TIMER_A { match self.bits { false => TIMER_A::LEVEL, true => TIMER_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == TIMER_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == TIMER_A::EDGE } } #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, TIMER_A, O>; -impl<'a, const O: u8> TIMER_W<'a, O> { +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TIMER_A>; +impl<'a, REG, const O: u8> TIMER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(TIMER_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(TIMER_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl MAILBOX_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> MAILBOX_A { + pub const fn variant(&self) -> MAILBOX_A { match self.bits { false => MAILBOX_A::LEVEL, true => MAILBOX_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == MAILBOX_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == MAILBOX_A::EDGE } } #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, MAILBOX_A, O>; -impl<'a, const O: u8> MAILBOX_W<'a, O> { +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MAILBOX_A>; +impl<'a, REG, const O: u8> MAILBOX_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(MAILBOX_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(MAILBOX_A::EDGE) } } @@ -153,35 +127,37 @@ impl From for bool { impl DOORBELL0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DOORBELL0_A { + pub const fn variant(&self) -> DOORBELL0_A { match self.bits { false => DOORBELL0_A::LEVEL, true => DOORBELL0_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DOORBELL0_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DOORBELL0_A::EDGE } } #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, DOORBELL0_A, O>; -impl<'a, const O: u8> DOORBELL0_W<'a, O> { +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DOORBELL0_A>; +impl<'a, REG, const O: u8> DOORBELL0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DOORBELL0_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DOORBELL0_A::EDGE) } } @@ -204,35 +180,37 @@ impl From for bool { impl DOORBELL1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DOORBELL1_A { + pub const fn variant(&self) -> DOORBELL1_A { match self.bits { false => DOORBELL1_A::LEVEL, true => DOORBELL1_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DOORBELL1_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DOORBELL1_A::EDGE } } #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, DOORBELL1_A, O>; -impl<'a, const O: u8> DOORBELL1_W<'a, O> { +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DOORBELL1_A>; +impl<'a, REG, const O: u8> DOORBELL1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DOORBELL1_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DOORBELL1_A::EDGE) } } @@ -255,35 +233,37 @@ impl From for bool { impl VPU0_HALTED_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> VPU0_HALTED_A { + pub const fn variant(&self) -> VPU0_HALTED_A { match self.bits { false => VPU0_HALTED_A::LEVEL, true => VPU0_HALTED_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == VPU0_HALTED_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == VPU0_HALTED_A::EDGE } } #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, VPU0_HALTED_A, O>; -impl<'a, const O: u8> VPU0_HALTED_W<'a, O> { +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, VPU0_HALTED_A>; +impl<'a, REG, const O: u8> VPU0_HALTED_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(VPU0_HALTED_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(VPU0_HALTED_A::EDGE) } } @@ -306,35 +286,37 @@ impl From for bool { impl VPU1_HALTED_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> VPU1_HALTED_A { + pub const fn variant(&self) -> VPU1_HALTED_A { match self.bits { false => VPU1_HALTED_A::LEVEL, true => VPU1_HALTED_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == VPU1_HALTED_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == VPU1_HALTED_A::EDGE } } #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, VPU1_HALTED_A, O>; -impl<'a, const O: u8> VPU1_HALTED_W<'a, O> { +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, VPU1_HALTED_A>; +impl<'a, REG, const O: u8> VPU1_HALTED_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(VPU1_HALTED_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(VPU1_HALTED_A::EDGE) } } @@ -357,35 +339,38 @@ impl From for bool { impl ARM_ADDRESS_ERROR_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ARM_ADDRESS_ERROR_A { + pub const fn variant(&self) -> ARM_ADDRESS_ERROR_A { match self.bits { false => ARM_ADDRESS_ERROR_A::LEVEL, true => ARM_ADDRESS_ERROR_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == ARM_ADDRESS_ERROR_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == ARM_ADDRESS_ERROR_A::EDGE } } #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, ARM_ADDRESS_ERROR_A, O>; -impl<'a, const O: u8> ARM_ADDRESS_ERROR_W<'a, O> { +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = + crate::BitWriter<'a, REG, O, ARM_ADDRESS_ERROR_A>; +impl<'a, REG, const O: u8> ARM_ADDRESS_ERROR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(ARM_ADDRESS_ERROR_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(ARM_ADDRESS_ERROR_A::EDGE) } } @@ -408,35 +393,37 @@ impl From for bool { impl ARM_AXI_ERROR_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ARM_AXI_ERROR_A { + pub const fn variant(&self) -> ARM_AXI_ERROR_A { match self.bits { false => ARM_AXI_ERROR_A::LEVEL, true => ARM_AXI_ERROR_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == ARM_AXI_ERROR_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == ARM_AXI_ERROR_A::EDGE } } #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, ARM_AXI_ERROR_A, O>; -impl<'a, const O: u8> ARM_AXI_ERROR_W<'a, O> { +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ARM_AXI_ERROR_A>; +impl<'a, REG, const O: u8> ARM_AXI_ERROR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(ARM_AXI_ERROR_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(ARM_AXI_ERROR_A::EDGE) } } @@ -459,34 +446,37 @@ impl From for bool { impl SWI0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SWI0_A { + pub const fn variant(&self) -> SWI0_A { match self.bits { false => SWI0_A::LEVEL, true => SWI0_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == SWI0_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == SWI0_A::EDGE } } #[doc = "Field `SWI0` writer - Software interrupt 0"] -pub type SWI0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI0_A, O>; -impl<'a, const O: u8> SWI0_W<'a, O> { +pub type SWI0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SWI0_A>; +impl<'a, REG, const O: u8> SWI0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(SWI0_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(SWI0_A::EDGE) } } @@ -509,34 +499,37 @@ impl From for bool { impl SWI1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SWI1_A { + pub const fn variant(&self) -> SWI1_A { match self.bits { false => SWI1_A::LEVEL, true => SWI1_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == SWI1_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == SWI1_A::EDGE } } #[doc = "Field `SWI1` writer - Software interrupt 1"] -pub type SWI1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI1_A, O>; -impl<'a, const O: u8> SWI1_W<'a, O> { +pub type SWI1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SWI1_A>; +impl<'a, REG, const O: u8> SWI1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(SWI1_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(SWI1_A::EDGE) } } @@ -559,34 +552,37 @@ impl From for bool { impl SWI2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SWI2_A { + pub const fn variant(&self) -> SWI2_A { match self.bits { false => SWI2_A::LEVEL, true => SWI2_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == SWI2_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == SWI2_A::EDGE } } #[doc = "Field `SWI2` writer - Software interrupt 2"] -pub type SWI2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI2_A, O>; -impl<'a, const O: u8> SWI2_W<'a, O> { +pub type SWI2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SWI2_A>; +impl<'a, REG, const O: u8> SWI2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(SWI2_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(SWI2_A::EDGE) } } @@ -609,34 +605,37 @@ impl From for bool { impl SWI3_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SWI3_A { + pub const fn variant(&self) -> SWI3_A { match self.bits { false => SWI3_A::LEVEL, true => SWI3_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == SWI3_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == SWI3_A::EDGE } } #[doc = "Field `SWI3` writer - Software interrupt 3"] -pub type SWI3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI3_A, O>; -impl<'a, const O: u8> SWI3_W<'a, O> { +pub type SWI3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SWI3_A>; +impl<'a, REG, const O: u8> SWI3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(SWI3_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(SWI3_A::EDGE) } } @@ -659,34 +658,37 @@ impl From for bool { impl SWI4_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SWI4_A { + pub const fn variant(&self) -> SWI4_A { match self.bits { false => SWI4_A::LEVEL, true => SWI4_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == SWI4_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == SWI4_A::EDGE } } #[doc = "Field `SWI4` writer - Software interrupt 4"] -pub type SWI4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI4_A, O>; -impl<'a, const O: u8> SWI4_W<'a, O> { +pub type SWI4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SWI4_A>; +impl<'a, REG, const O: u8> SWI4_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(SWI4_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(SWI4_A::EDGE) } } @@ -709,34 +711,37 @@ impl From for bool { impl SWI5_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SWI5_A { + pub const fn variant(&self) -> SWI5_A { match self.bits { false => SWI5_A::LEVEL, true => SWI5_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == SWI5_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == SWI5_A::EDGE } } #[doc = "Field `SWI5` writer - Software interrupt 5"] -pub type SWI5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI5_A, O>; -impl<'a, const O: u8> SWI5_W<'a, O> { +pub type SWI5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SWI5_A>; +impl<'a, REG, const O: u8> SWI5_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(SWI5_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(SWI5_A::EDGE) } } @@ -759,34 +764,37 @@ impl From for bool { impl SWI6_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SWI6_A { + pub const fn variant(&self) -> SWI6_A { match self.bits { false => SWI6_A::LEVEL, true => SWI6_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == SWI6_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == SWI6_A::EDGE } } #[doc = "Field `SWI6` writer - Software interrupt 6"] -pub type SWI6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI6_A, O>; -impl<'a, const O: u8> SWI6_W<'a, O> { +pub type SWI6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SWI6_A>; +impl<'a, REG, const O: u8> SWI6_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(SWI6_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(SWI6_A::EDGE) } } @@ -809,34 +817,37 @@ impl From for bool { impl SWI7_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SWI7_A { + pub const fn variant(&self) -> SWI7_A { match self.bits { false => SWI7_A::LEVEL, true => SWI7_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == SWI7_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == SWI7_A::EDGE } } #[doc = "Field `SWI7` writer - Software interrupt 7"] -pub type SWI7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR16_SPEC, SWI7_A, O>; -impl<'a, const O: u8> SWI7_W<'a, O> { +pub type SWI7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SWI7_A>; +impl<'a, REG, const O: u8> SWI7_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(SWI7_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(SWI7_A::EDGE) } } @@ -922,122 +933,156 @@ impl R { SWI7_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR16") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .field("swi0", &format_args!("{}", self.swi0().bit())) + .field("swi1", &format_args!("{}", self.swi1().bit())) + .field("swi2", &format_args!("{}", self.swi2().bit())) + .field("swi3", &format_args!("{}", self.swi3().bit())) + .field("swi4", &format_args!("{}", self.swi4().bit())) + .field("swi5", &format_args!("{}", self.swi5().bit())) + .field("swi6", &format_args!("{}", self.swi6().bit())) + .field("swi7", &format_args!("{}", self.swi7().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<1> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 3 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<3> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 5 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<5> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 7 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<7> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 9 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<9> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 11 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<11> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 13 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<13> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 15 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<15> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } #[doc = "Bit 17 - Software interrupt 0"] #[inline(always)] #[must_use] - pub fn swi0(&mut self) -> SWI0_W<17> { + pub fn swi0(&mut self) -> SWI0_W { SWI0_W::new(self) } #[doc = "Bit 19 - Software interrupt 1"] #[inline(always)] #[must_use] - pub fn swi1(&mut self) -> SWI1_W<19> { + pub fn swi1(&mut self) -> SWI1_W { SWI1_W::new(self) } #[doc = "Bit 21 - Software interrupt 2"] #[inline(always)] #[must_use] - pub fn swi2(&mut self) -> SWI2_W<21> { + pub fn swi2(&mut self) -> SWI2_W { SWI2_W::new(self) } #[doc = "Bit 23 - Software interrupt 3"] #[inline(always)] #[must_use] - pub fn swi3(&mut self) -> SWI3_W<23> { + pub fn swi3(&mut self) -> SWI3_W { SWI3_W::new(self) } #[doc = "Bit 25 - Software interrupt 4"] #[inline(always)] #[must_use] - pub fn swi4(&mut self) -> SWI4_W<25> { + pub fn swi4(&mut self) -> SWI4_W { SWI4_W::new(self) } #[doc = "Bit 27 - Software interrupt 5"] #[inline(always)] #[must_use] - pub fn swi5(&mut self) -> SWI5_W<27> { + pub fn swi5(&mut self) -> SWI5_W { SWI5_W::new(self) } #[doc = "Bit 29 - Software interrupt 6"] #[inline(always)] #[must_use] - pub fn swi6(&mut self) -> SWI6_W<29> { + pub fn swi6(&mut self) -> SWI6_W { SWI6_W::new(self) } #[doc = "Bit 31 - Software interrupt 7"] #[inline(always)] #[must_use] - pub fn swi7(&mut self) -> SWI7_W<31> { + pub fn swi7(&mut self) -> SWI7_W { SWI7_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 64 - 79\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr16](index.html) module"] +#[doc = "Interrupt Configuration 64 - 79\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr16::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr16::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR16_SPEC; impl crate::RegisterSpec for GICD_ICFGR16_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr16::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR16_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr16::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr16::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR16_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr16::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR16_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr20.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr20.rs index 6cb9587..563917b 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr20.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr20.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR20` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR20` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT80` reader - Interrupt 80"] pub type INT80_R = crate::BitReader; #[doc = "Interrupt 80\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl INT80_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT80_A { + pub const fn variant(&self) -> INT80_A { match self.bits { false => INT80_A::LEVEL, true => INT80_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT80_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT80_A::EDGE } } #[doc = "Field `INT80` writer - Interrupt 80"] -pub type INT80_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT80_A, O>; -impl<'a, const O: u8> INT80_W<'a, O> { +pub type INT80_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT80_A>; +impl<'a, REG, const O: u8> INT80_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT80_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT80_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl INT81_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT81_A { + pub const fn variant(&self) -> INT81_A { match self.bits { false => INT81_A::LEVEL, true => INT81_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT81_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT81_A::EDGE } } #[doc = "Field `INT81` writer - Interrupt 81"] -pub type INT81_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT81_A, O>; -impl<'a, const O: u8> INT81_W<'a, O> { +pub type INT81_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT81_A>; +impl<'a, REG, const O: u8> INT81_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT81_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT81_A::EDGE) } } @@ -153,34 +127,37 @@ impl From for bool { impl INT82_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT82_A { + pub const fn variant(&self) -> INT82_A { match self.bits { false => INT82_A::LEVEL, true => INT82_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT82_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT82_A::EDGE } } #[doc = "Field `INT82` writer - Interrupt 82"] -pub type INT82_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT82_A, O>; -impl<'a, const O: u8> INT82_W<'a, O> { +pub type INT82_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT82_A>; +impl<'a, REG, const O: u8> INT82_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT82_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT82_A::EDGE) } } @@ -203,34 +180,37 @@ impl From for bool { impl INT83_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT83_A { + pub const fn variant(&self) -> INT83_A { match self.bits { false => INT83_A::LEVEL, true => INT83_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT83_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT83_A::EDGE } } #[doc = "Field `INT83` writer - Interrupt 83"] -pub type INT83_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT83_A, O>; -impl<'a, const O: u8> INT83_W<'a, O> { +pub type INT83_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT83_A>; +impl<'a, REG, const O: u8> INT83_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT83_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT83_A::EDGE) } } @@ -253,34 +233,37 @@ impl From for bool { impl INT84_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT84_A { + pub const fn variant(&self) -> INT84_A { match self.bits { false => INT84_A::LEVEL, true => INT84_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT84_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT84_A::EDGE } } #[doc = "Field `INT84` writer - Interrupt 84"] -pub type INT84_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT84_A, O>; -impl<'a, const O: u8> INT84_W<'a, O> { +pub type INT84_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT84_A>; +impl<'a, REG, const O: u8> INT84_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT84_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT84_A::EDGE) } } @@ -303,34 +286,37 @@ impl From for bool { impl INT85_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT85_A { + pub const fn variant(&self) -> INT85_A { match self.bits { false => INT85_A::LEVEL, true => INT85_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT85_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT85_A::EDGE } } #[doc = "Field `INT85` writer - Interrupt 85"] -pub type INT85_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT85_A, O>; -impl<'a, const O: u8> INT85_W<'a, O> { +pub type INT85_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT85_A>; +impl<'a, REG, const O: u8> INT85_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT85_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT85_A::EDGE) } } @@ -353,34 +339,37 @@ impl From for bool { impl INT86_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT86_A { + pub const fn variant(&self) -> INT86_A { match self.bits { false => INT86_A::LEVEL, true => INT86_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT86_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT86_A::EDGE } } #[doc = "Field `INT86` writer - Interrupt 86"] -pub type INT86_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT86_A, O>; -impl<'a, const O: u8> INT86_W<'a, O> { +pub type INT86_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT86_A>; +impl<'a, REG, const O: u8> INT86_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT86_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT86_A::EDGE) } } @@ -403,34 +392,37 @@ impl From for bool { impl INT87_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT87_A { + pub const fn variant(&self) -> INT87_A { match self.bits { false => INT87_A::LEVEL, true => INT87_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT87_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT87_A::EDGE } } #[doc = "Field `INT87` writer - Interrupt 87"] -pub type INT87_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT87_A, O>; -impl<'a, const O: u8> INT87_W<'a, O> { +pub type INT87_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT87_A>; +impl<'a, REG, const O: u8> INT87_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT87_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT87_A::EDGE) } } @@ -453,34 +445,37 @@ impl From for bool { impl INT88_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT88_A { + pub const fn variant(&self) -> INT88_A { match self.bits { false => INT88_A::LEVEL, true => INT88_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT88_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT88_A::EDGE } } #[doc = "Field `INT88` writer - Interrupt 88"] -pub type INT88_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT88_A, O>; -impl<'a, const O: u8> INT88_W<'a, O> { +pub type INT88_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT88_A>; +impl<'a, REG, const O: u8> INT88_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT88_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT88_A::EDGE) } } @@ -503,34 +498,37 @@ impl From for bool { impl INT89_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT89_A { + pub const fn variant(&self) -> INT89_A { match self.bits { false => INT89_A::LEVEL, true => INT89_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT89_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT89_A::EDGE } } #[doc = "Field `INT89` writer - Interrupt 89"] -pub type INT89_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT89_A, O>; -impl<'a, const O: u8> INT89_W<'a, O> { +pub type INT89_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT89_A>; +impl<'a, REG, const O: u8> INT89_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT89_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT89_A::EDGE) } } @@ -553,34 +551,37 @@ impl From for bool { impl INT90_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT90_A { + pub const fn variant(&self) -> INT90_A { match self.bits { false => INT90_A::LEVEL, true => INT90_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT90_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT90_A::EDGE } } #[doc = "Field `INT90` writer - Interrupt 90"] -pub type INT90_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT90_A, O>; -impl<'a, const O: u8> INT90_W<'a, O> { +pub type INT90_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT90_A>; +impl<'a, REG, const O: u8> INT90_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT90_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT90_A::EDGE) } } @@ -603,34 +604,37 @@ impl From for bool { impl INT91_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT91_A { + pub const fn variant(&self) -> INT91_A { match self.bits { false => INT91_A::LEVEL, true => INT91_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT91_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT91_A::EDGE } } #[doc = "Field `INT91` writer - Interrupt 91"] -pub type INT91_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT91_A, O>; -impl<'a, const O: u8> INT91_W<'a, O> { +pub type INT91_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT91_A>; +impl<'a, REG, const O: u8> INT91_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT91_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT91_A::EDGE) } } @@ -653,34 +657,37 @@ impl From for bool { impl INT92_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT92_A { + pub const fn variant(&self) -> INT92_A { match self.bits { false => INT92_A::LEVEL, true => INT92_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT92_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT92_A::EDGE } } #[doc = "Field `INT92` writer - Interrupt 92"] -pub type INT92_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT92_A, O>; -impl<'a, const O: u8> INT92_W<'a, O> { +pub type INT92_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT92_A>; +impl<'a, REG, const O: u8> INT92_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT92_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT92_A::EDGE) } } @@ -703,34 +710,37 @@ impl From for bool { impl INT93_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT93_A { + pub const fn variant(&self) -> INT93_A { match self.bits { false => INT93_A::LEVEL, true => INT93_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT93_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT93_A::EDGE } } #[doc = "Field `INT93` writer - Interrupt 93"] -pub type INT93_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT93_A, O>; -impl<'a, const O: u8> INT93_W<'a, O> { +pub type INT93_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT93_A>; +impl<'a, REG, const O: u8> INT93_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT93_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT93_A::EDGE) } } @@ -753,34 +763,37 @@ impl From for bool { impl INT94_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT94_A { + pub const fn variant(&self) -> INT94_A { match self.bits { false => INT94_A::LEVEL, true => INT94_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT94_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT94_A::EDGE } } #[doc = "Field `INT94` writer - Interrupt 94"] -pub type INT94_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT94_A, O>; -impl<'a, const O: u8> INT94_W<'a, O> { +pub type INT94_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT94_A>; +impl<'a, REG, const O: u8> INT94_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT94_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT94_A::EDGE) } } @@ -803,34 +816,37 @@ impl From for bool { impl INT95_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT95_A { + pub const fn variant(&self) -> INT95_A { match self.bits { false => INT95_A::LEVEL, true => INT95_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT95_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT95_A::EDGE } } #[doc = "Field `INT95` writer - Interrupt 95"] -pub type INT95_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR20_SPEC, INT95_A, O>; -impl<'a, const O: u8> INT95_W<'a, O> { +pub type INT95_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT95_A>; +impl<'a, REG, const O: u8> INT95_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT95_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT95_A::EDGE) } } @@ -916,122 +932,150 @@ impl R { INT95_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR20") + .field("int80", &format_args!("{}", self.int80().bit())) + .field("int81", &format_args!("{}", self.int81().bit())) + .field("int82", &format_args!("{}", self.int82().bit())) + .field("int83", &format_args!("{}", self.int83().bit())) + .field("int84", &format_args!("{}", self.int84().bit())) + .field("int85", &format_args!("{}", self.int85().bit())) + .field("int86", &format_args!("{}", self.int86().bit())) + .field("int87", &format_args!("{}", self.int87().bit())) + .field("int88", &format_args!("{}", self.int88().bit())) + .field("int89", &format_args!("{}", self.int89().bit())) + .field("int90", &format_args!("{}", self.int90().bit())) + .field("int91", &format_args!("{}", self.int91().bit())) + .field("int92", &format_args!("{}", self.int92().bit())) + .field("int93", &format_args!("{}", self.int93().bit())) + .field("int94", &format_args!("{}", self.int94().bit())) + .field("int95", &format_args!("{}", self.int95().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Interrupt 80"] #[inline(always)] #[must_use] - pub fn int80(&mut self) -> INT80_W<1> { + pub fn int80(&mut self) -> INT80_W { INT80_W::new(self) } #[doc = "Bit 3 - Interrupt 81"] #[inline(always)] #[must_use] - pub fn int81(&mut self) -> INT81_W<3> { + pub fn int81(&mut self) -> INT81_W { INT81_W::new(self) } #[doc = "Bit 5 - Interrupt 82"] #[inline(always)] #[must_use] - pub fn int82(&mut self) -> INT82_W<5> { + pub fn int82(&mut self) -> INT82_W { INT82_W::new(self) } #[doc = "Bit 7 - Interrupt 83"] #[inline(always)] #[must_use] - pub fn int83(&mut self) -> INT83_W<7> { + pub fn int83(&mut self) -> INT83_W { INT83_W::new(self) } #[doc = "Bit 9 - Interrupt 84"] #[inline(always)] #[must_use] - pub fn int84(&mut self) -> INT84_W<9> { + pub fn int84(&mut self) -> INT84_W { INT84_W::new(self) } #[doc = "Bit 11 - Interrupt 85"] #[inline(always)] #[must_use] - pub fn int85(&mut self) -> INT85_W<11> { + pub fn int85(&mut self) -> INT85_W { INT85_W::new(self) } #[doc = "Bit 13 - Interrupt 86"] #[inline(always)] #[must_use] - pub fn int86(&mut self) -> INT86_W<13> { + pub fn int86(&mut self) -> INT86_W { INT86_W::new(self) } #[doc = "Bit 15 - Interrupt 87"] #[inline(always)] #[must_use] - pub fn int87(&mut self) -> INT87_W<15> { + pub fn int87(&mut self) -> INT87_W { INT87_W::new(self) } #[doc = "Bit 17 - Interrupt 88"] #[inline(always)] #[must_use] - pub fn int88(&mut self) -> INT88_W<17> { + pub fn int88(&mut self) -> INT88_W { INT88_W::new(self) } #[doc = "Bit 19 - Interrupt 89"] #[inline(always)] #[must_use] - pub fn int89(&mut self) -> INT89_W<19> { + pub fn int89(&mut self) -> INT89_W { INT89_W::new(self) } #[doc = "Bit 21 - Interrupt 90"] #[inline(always)] #[must_use] - pub fn int90(&mut self) -> INT90_W<21> { + pub fn int90(&mut self) -> INT90_W { INT90_W::new(self) } #[doc = "Bit 23 - Interrupt 91"] #[inline(always)] #[must_use] - pub fn int91(&mut self) -> INT91_W<23> { + pub fn int91(&mut self) -> INT91_W { INT91_W::new(self) } #[doc = "Bit 25 - Interrupt 92"] #[inline(always)] #[must_use] - pub fn int92(&mut self) -> INT92_W<25> { + pub fn int92(&mut self) -> INT92_W { INT92_W::new(self) } #[doc = "Bit 27 - Interrupt 93"] #[inline(always)] #[must_use] - pub fn int93(&mut self) -> INT93_W<27> { + pub fn int93(&mut self) -> INT93_W { INT93_W::new(self) } #[doc = "Bit 29 - Interrupt 94"] #[inline(always)] #[must_use] - pub fn int94(&mut self) -> INT94_W<29> { + pub fn int94(&mut self) -> INT94_W { INT94_W::new(self) } #[doc = "Bit 31 - Interrupt 95"] #[inline(always)] #[must_use] - pub fn int95(&mut self) -> INT95_W<31> { + pub fn int95(&mut self) -> INT95_W { INT95_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 80 - 95\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr20](index.html) module"] +#[doc = "Interrupt Configuration 80 - 95\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr20::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr20::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR20_SPEC; impl crate::RegisterSpec for GICD_ICFGR20_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr20::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR20_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr20::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr20::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR20_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr20::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR20_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr24.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr24.rs index c06d1ba..4137b35 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr24.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr24.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR24` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR24` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] pub type TIMER_0_R = crate::BitReader; #[doc = "Timer 0\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl TIMER_0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TIMER_0_A { + pub const fn variant(&self) -> TIMER_0_A { match self.bits { false => TIMER_0_A::LEVEL, true => TIMER_0_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == TIMER_0_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == TIMER_0_A::EDGE } } #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, TIMER_0_A, O>; -impl<'a, const O: u8> TIMER_0_W<'a, O> { +pub type TIMER_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TIMER_0_A>; +impl<'a, REG, const O: u8> TIMER_0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(TIMER_0_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(TIMER_0_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl TIMER_1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TIMER_1_A { + pub const fn variant(&self) -> TIMER_1_A { match self.bits { false => TIMER_1_A::LEVEL, true => TIMER_1_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == TIMER_1_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == TIMER_1_A::EDGE } } #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, TIMER_1_A, O>; -impl<'a, const O: u8> TIMER_1_W<'a, O> { +pub type TIMER_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TIMER_1_A>; +impl<'a, REG, const O: u8> TIMER_1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(TIMER_1_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(TIMER_1_A::EDGE) } } @@ -153,34 +127,37 @@ impl From for bool { impl TIMER_2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TIMER_2_A { + pub const fn variant(&self) -> TIMER_2_A { match self.bits { false => TIMER_2_A::LEVEL, true => TIMER_2_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == TIMER_2_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == TIMER_2_A::EDGE } } #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, TIMER_2_A, O>; -impl<'a, const O: u8> TIMER_2_W<'a, O> { +pub type TIMER_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TIMER_2_A>; +impl<'a, REG, const O: u8> TIMER_2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(TIMER_2_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(TIMER_2_A::EDGE) } } @@ -203,34 +180,37 @@ impl From for bool { impl TIMER_3_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TIMER_3_A { + pub const fn variant(&self) -> TIMER_3_A { match self.bits { false => TIMER_3_A::LEVEL, true => TIMER_3_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == TIMER_3_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == TIMER_3_A::EDGE } } #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, TIMER_3_A, O>; -impl<'a, const O: u8> TIMER_3_W<'a, O> { +pub type TIMER_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TIMER_3_A>; +impl<'a, REG, const O: u8> TIMER_3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(TIMER_3_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(TIMER_3_A::EDGE) } } @@ -253,34 +233,37 @@ impl From for bool { impl H264_0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> H264_0_A { + pub const fn variant(&self) -> H264_0_A { match self.bits { false => H264_0_A::LEVEL, true => H264_0_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == H264_0_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == H264_0_A::EDGE } } #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, H264_0_A, O>; -impl<'a, const O: u8> H264_0_W<'a, O> { +pub type H264_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, H264_0_A>; +impl<'a, REG, const O: u8> H264_0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(H264_0_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(H264_0_A::EDGE) } } @@ -303,34 +286,37 @@ impl From for bool { impl H264_1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> H264_1_A { + pub const fn variant(&self) -> H264_1_A { match self.bits { false => H264_1_A::LEVEL, true => H264_1_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == H264_1_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == H264_1_A::EDGE } } #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, H264_1_A, O>; -impl<'a, const O: u8> H264_1_W<'a, O> { +pub type H264_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, H264_1_A>; +impl<'a, REG, const O: u8> H264_1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(H264_1_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(H264_1_A::EDGE) } } @@ -353,34 +339,37 @@ impl From for bool { impl H264_2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> H264_2_A { + pub const fn variant(&self) -> H264_2_A { match self.bits { false => H264_2_A::LEVEL, true => H264_2_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == H264_2_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == H264_2_A::EDGE } } #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, H264_2_A, O>; -impl<'a, const O: u8> H264_2_W<'a, O> { +pub type H264_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, H264_2_A>; +impl<'a, REG, const O: u8> H264_2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(H264_2_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(H264_2_A::EDGE) } } @@ -403,34 +392,37 @@ impl From for bool { impl JPEG_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> JPEG_A { + pub const fn variant(&self) -> JPEG_A { match self.bits { false => JPEG_A::LEVEL, true => JPEG_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == JPEG_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == JPEG_A::EDGE } } #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, JPEG_A, O>; -impl<'a, const O: u8> JPEG_W<'a, O> { +pub type JPEG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, JPEG_A>; +impl<'a, REG, const O: u8> JPEG_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(JPEG_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(JPEG_A::EDGE) } } @@ -453,34 +445,37 @@ impl From for bool { impl ISP_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ISP_A { + pub const fn variant(&self) -> ISP_A { match self.bits { false => ISP_A::LEVEL, true => ISP_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == ISP_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == ISP_A::EDGE } } #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, ISP_A, O>; -impl<'a, const O: u8> ISP_W<'a, O> { +pub type ISP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ISP_A>; +impl<'a, REG, const O: u8> ISP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(ISP_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(ISP_A::EDGE) } } @@ -503,34 +498,37 @@ impl From for bool { impl USB_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> USB_A { + pub const fn variant(&self) -> USB_A { match self.bits { false => USB_A::LEVEL, true => USB_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == USB_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == USB_A::EDGE } } #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, USB_A, O>; -impl<'a, const O: u8> USB_W<'a, O> { +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, USB_A>; +impl<'a, REG, const O: u8> USB_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(USB_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(USB_A::EDGE) } } @@ -553,34 +551,37 @@ impl From for bool { impl V3D_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> V3D_A { + pub const fn variant(&self) -> V3D_A { match self.bits { false => V3D_A::LEVEL, true => V3D_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == V3D_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == V3D_A::EDGE } } #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, V3D_A, O>; -impl<'a, const O: u8> V3D_W<'a, O> { +pub type V3D_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, V3D_A>; +impl<'a, REG, const O: u8> V3D_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(V3D_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(V3D_A::EDGE) } } @@ -603,35 +604,37 @@ impl From for bool { impl TRANSPOSER_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TRANSPOSER_A { + pub const fn variant(&self) -> TRANSPOSER_A { match self.bits { false => TRANSPOSER_A::LEVEL, true => TRANSPOSER_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == TRANSPOSER_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == TRANSPOSER_A::EDGE } } #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, TRANSPOSER_A, O>; -impl<'a, const O: u8> TRANSPOSER_W<'a, O> { +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TRANSPOSER_A>; +impl<'a, REG, const O: u8> TRANSPOSER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(TRANSPOSER_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(TRANSPOSER_A::EDGE) } } @@ -654,35 +657,38 @@ impl From for bool { impl MULTICORE_SYNC_0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> MULTICORE_SYNC_0_A { + pub const fn variant(&self) -> MULTICORE_SYNC_0_A { match self.bits { false => MULTICORE_SYNC_0_A::LEVEL, true => MULTICORE_SYNC_0_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == MULTICORE_SYNC_0_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == MULTICORE_SYNC_0_A::EDGE } } #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, MULTICORE_SYNC_0_A, O>; -impl<'a, const O: u8> MULTICORE_SYNC_0_W<'a, O> { +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = + crate::BitWriter<'a, REG, O, MULTICORE_SYNC_0_A>; +impl<'a, REG, const O: u8> MULTICORE_SYNC_0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(MULTICORE_SYNC_0_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(MULTICORE_SYNC_0_A::EDGE) } } @@ -705,35 +711,38 @@ impl From for bool { impl MULTICORE_SYNC_1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> MULTICORE_SYNC_1_A { + pub const fn variant(&self) -> MULTICORE_SYNC_1_A { match self.bits { false => MULTICORE_SYNC_1_A::LEVEL, true => MULTICORE_SYNC_1_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == MULTICORE_SYNC_1_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == MULTICORE_SYNC_1_A::EDGE } } #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, MULTICORE_SYNC_1_A, O>; -impl<'a, const O: u8> MULTICORE_SYNC_1_W<'a, O> { +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = + crate::BitWriter<'a, REG, O, MULTICORE_SYNC_1_A>; +impl<'a, REG, const O: u8> MULTICORE_SYNC_1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(MULTICORE_SYNC_1_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(MULTICORE_SYNC_1_A::EDGE) } } @@ -756,35 +765,38 @@ impl From for bool { impl MULTICORE_SYNC_2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> MULTICORE_SYNC_2_A { + pub const fn variant(&self) -> MULTICORE_SYNC_2_A { match self.bits { false => MULTICORE_SYNC_2_A::LEVEL, true => MULTICORE_SYNC_2_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == MULTICORE_SYNC_2_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == MULTICORE_SYNC_2_A::EDGE } } #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, MULTICORE_SYNC_2_A, O>; -impl<'a, const O: u8> MULTICORE_SYNC_2_W<'a, O> { +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = + crate::BitWriter<'a, REG, O, MULTICORE_SYNC_2_A>; +impl<'a, REG, const O: u8> MULTICORE_SYNC_2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(MULTICORE_SYNC_2_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(MULTICORE_SYNC_2_A::EDGE) } } @@ -807,35 +819,38 @@ impl From for bool { impl MULTICORE_SYNC_3_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> MULTICORE_SYNC_3_A { + pub const fn variant(&self) -> MULTICORE_SYNC_3_A { match self.bits { false => MULTICORE_SYNC_3_A::LEVEL, true => MULTICORE_SYNC_3_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == MULTICORE_SYNC_3_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == MULTICORE_SYNC_3_A::EDGE } } #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR24_SPEC, MULTICORE_SYNC_3_A, O>; -impl<'a, const O: u8> MULTICORE_SYNC_3_W<'a, O> { +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = + crate::BitWriter<'a, REG, O, MULTICORE_SYNC_3_A>; +impl<'a, REG, const O: u8> MULTICORE_SYNC_3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(MULTICORE_SYNC_3_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(MULTICORE_SYNC_3_A::EDGE) } } @@ -921,122 +936,162 @@ impl R { MULTICORE_SYNC_3_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR24") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<1> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bit 3 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<3> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bit 5 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<5> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bit 7 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<7> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } #[doc = "Bit 9 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<9> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bit 11 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<11> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bit 13 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<13> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bit 15 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<15> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } #[doc = "Bit 17 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<17> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bit 19 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<19> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 21 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<21> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bit 23 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<23> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } #[doc = "Bit 25 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<25> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bit 27 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<27> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bit 29 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<29> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bit 31 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<31> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 96 - 111\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr24](index.html) module"] +#[doc = "Interrupt Configuration 96 - 111\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr24::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr24::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR24_SPEC; impl crate::RegisterSpec for GICD_ICFGR24_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr24::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR24_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr24::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr24::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR24_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr24::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR24_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr28.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr28.rs index b2f01d2..a92d41f 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr28.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr28.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR28` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR28` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMA_0` reader - DMA 0"] pub type DMA_0_R = crate::BitReader; #[doc = "DMA 0\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl DMA_0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_0_A { + pub const fn variant(&self) -> DMA_0_A { match self.bits { false => DMA_0_A::LEVEL, true => DMA_0_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_0_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_0_A::EDGE } } #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_0_A, O>; -impl<'a, const O: u8> DMA_0_W<'a, O> { +pub type DMA_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_0_A>; +impl<'a, REG, const O: u8> DMA_0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_0_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_0_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl DMA_1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_1_A { + pub const fn variant(&self) -> DMA_1_A { match self.bits { false => DMA_1_A::LEVEL, true => DMA_1_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_1_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_1_A::EDGE } } #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_1_A, O>; -impl<'a, const O: u8> DMA_1_W<'a, O> { +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_1_A>; +impl<'a, REG, const O: u8> DMA_1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_1_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_1_A::EDGE) } } @@ -153,34 +127,37 @@ impl From for bool { impl DMA_2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_2_A { + pub const fn variant(&self) -> DMA_2_A { match self.bits { false => DMA_2_A::LEVEL, true => DMA_2_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_2_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_2_A::EDGE } } #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_2_A, O>; -impl<'a, const O: u8> DMA_2_W<'a, O> { +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_2_A>; +impl<'a, REG, const O: u8> DMA_2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_2_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_2_A::EDGE) } } @@ -203,34 +180,37 @@ impl From for bool { impl DMA_3_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_3_A { + pub const fn variant(&self) -> DMA_3_A { match self.bits { false => DMA_3_A::LEVEL, true => DMA_3_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_3_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_3_A::EDGE } } #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_3_A, O>; -impl<'a, const O: u8> DMA_3_W<'a, O> { +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_3_A>; +impl<'a, REG, const O: u8> DMA_3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_3_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_3_A::EDGE) } } @@ -253,34 +233,37 @@ impl From for bool { impl DMA_4_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_4_A { + pub const fn variant(&self) -> DMA_4_A { match self.bits { false => DMA_4_A::LEVEL, true => DMA_4_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_4_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_4_A::EDGE } } #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_4_A, O>; -impl<'a, const O: u8> DMA_4_W<'a, O> { +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_4_A>; +impl<'a, REG, const O: u8> DMA_4_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_4_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_4_A::EDGE) } } @@ -303,34 +286,37 @@ impl From for bool { impl DMA_5_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_5_A { + pub const fn variant(&self) -> DMA_5_A { match self.bits { false => DMA_5_A::LEVEL, true => DMA_5_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_5_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_5_A::EDGE } } #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_5_A, O>; -impl<'a, const O: u8> DMA_5_W<'a, O> { +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_5_A>; +impl<'a, REG, const O: u8> DMA_5_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_5_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_5_A::EDGE) } } @@ -353,34 +339,37 @@ impl From for bool { impl DMA_6_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_6_A { + pub const fn variant(&self) -> DMA_6_A { match self.bits { false => DMA_6_A::LEVEL, true => DMA_6_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_6_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_6_A::EDGE } } #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_6_A, O>; -impl<'a, const O: u8> DMA_6_W<'a, O> { +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_6_A>; +impl<'a, REG, const O: u8> DMA_6_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_6_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_6_A::EDGE) } } @@ -403,34 +392,37 @@ impl From for bool { impl DMA_7_8_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_7_8_A { + pub const fn variant(&self) -> DMA_7_8_A { match self.bits { false => DMA_7_8_A::LEVEL, true => DMA_7_8_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_7_8_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_7_8_A::EDGE } } #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_7_8_A, O>; -impl<'a, const O: u8> DMA_7_8_W<'a, O> { +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_7_8_A>; +impl<'a, REG, const O: u8> DMA_7_8_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_7_8_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_7_8_A::EDGE) } } @@ -453,34 +445,37 @@ impl From for bool { impl DMA_9_10_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_9_10_A { + pub const fn variant(&self) -> DMA_9_10_A { match self.bits { false => DMA_9_10_A::LEVEL, true => DMA_9_10_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_9_10_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_9_10_A::EDGE } } #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_9_10_A, O>; -impl<'a, const O: u8> DMA_9_10_W<'a, O> { +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_9_10_A>; +impl<'a, REG, const O: u8> DMA_9_10_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_9_10_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_9_10_A::EDGE) } } @@ -503,34 +498,37 @@ impl From for bool { impl DMA_11_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_11_A { + pub const fn variant(&self) -> DMA_11_A { match self.bits { false => DMA_11_A::LEVEL, true => DMA_11_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_11_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_11_A::EDGE } } #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_11_A, O>; -impl<'a, const O: u8> DMA_11_W<'a, O> { +pub type DMA_11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_11_A>; +impl<'a, REG, const O: u8> DMA_11_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_11_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_11_A::EDGE) } } @@ -553,34 +551,37 @@ impl From for bool { impl DMA_12_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_12_A { + pub const fn variant(&self) -> DMA_12_A { match self.bits { false => DMA_12_A::LEVEL, true => DMA_12_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_12_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_12_A::EDGE } } #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_12_A, O>; -impl<'a, const O: u8> DMA_12_W<'a, O> { +pub type DMA_12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_12_A>; +impl<'a, REG, const O: u8> DMA_12_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_12_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_12_A::EDGE) } } @@ -603,34 +604,37 @@ impl From for bool { impl DMA_13_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_13_A { + pub const fn variant(&self) -> DMA_13_A { match self.bits { false => DMA_13_A::LEVEL, true => DMA_13_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_13_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_13_A::EDGE } } #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_13_A, O>; -impl<'a, const O: u8> DMA_13_W<'a, O> { +pub type DMA_13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_13_A>; +impl<'a, REG, const O: u8> DMA_13_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_13_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_13_A::EDGE) } } @@ -653,34 +657,37 @@ impl From for bool { impl DMA_14_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_14_A { + pub const fn variant(&self) -> DMA_14_A { match self.bits { false => DMA_14_A::LEVEL, true => DMA_14_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_14_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_14_A::EDGE } } #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_14_A, O>; -impl<'a, const O: u8> DMA_14_W<'a, O> { +pub type DMA_14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_14_A>; +impl<'a, REG, const O: u8> DMA_14_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_14_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_14_A::EDGE) } } @@ -703,34 +710,37 @@ impl From for bool { impl AUX_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> AUX_A { + pub const fn variant(&self) -> AUX_A { match self.bits { false => AUX_A::LEVEL, true => AUX_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == AUX_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == AUX_A::EDGE } } #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, AUX_A, O>; -impl<'a, const O: u8> AUX_W<'a, O> { +pub type AUX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, AUX_A>; +impl<'a, REG, const O: u8> AUX_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(AUX_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(AUX_A::EDGE) } } @@ -753,34 +763,37 @@ impl From for bool { impl ARM_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ARM_A { + pub const fn variant(&self) -> ARM_A { match self.bits { false => ARM_A::LEVEL, true => ARM_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == ARM_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == ARM_A::EDGE } } #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, ARM_A, O>; -impl<'a, const O: u8> ARM_W<'a, O> { +pub type ARM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ARM_A>; +impl<'a, REG, const O: u8> ARM_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(ARM_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(ARM_A::EDGE) } } @@ -803,34 +816,37 @@ impl From for bool { impl DMA_15_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DMA_15_A { + pub const fn variant(&self) -> DMA_15_A { match self.bits { false => DMA_15_A::LEVEL, true => DMA_15_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DMA_15_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DMA_15_A::EDGE } } #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR28_SPEC, DMA_15_A, O>; -impl<'a, const O: u8> DMA_15_W<'a, O> { +pub type DMA_15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DMA_15_A>; +impl<'a, REG, const O: u8> DMA_15_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DMA_15_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DMA_15_A::EDGE) } } @@ -916,122 +932,150 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR28") + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<1> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bit 3 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<3> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 5 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<5> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 7 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<7> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 9 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<9> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 11 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<11> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 13 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<13> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 15 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<15> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } #[doc = "Bit 17 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<17> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bit 19 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<19> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bit 21 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<21> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bit 23 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<23> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } #[doc = "Bit 25 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<25> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bit 27 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<27> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bit 29 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<29> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bit 31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<31> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 112 - 127\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr28](index.html) module"] +#[doc = "Interrupt Configuration 112 - 127\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr28::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr28::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR28_SPEC; impl crate::RegisterSpec for GICD_ICFGR28_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr28::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR28_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr28::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr28::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR28_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr28::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR28_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr32.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr32.rs index 63dbc4d..ab58073 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr32.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr32.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR32` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR32` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] pub type HDMI_CEC_R = crate::BitReader; #[doc = "HDMI CEC\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl HDMI_CEC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> HDMI_CEC_A { + pub const fn variant(&self) -> HDMI_CEC_A { match self.bits { false => HDMI_CEC_A::LEVEL, true => HDMI_CEC_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == HDMI_CEC_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == HDMI_CEC_A::EDGE } } #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, HDMI_CEC_A, O>; -impl<'a, const O: u8> HDMI_CEC_W<'a, O> { +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, HDMI_CEC_A>; +impl<'a, REG, const O: u8> HDMI_CEC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(HDMI_CEC_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(HDMI_CEC_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl HVS_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> HVS_A { + pub const fn variant(&self) -> HVS_A { match self.bits { false => HVS_A::LEVEL, true => HVS_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == HVS_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == HVS_A::EDGE } } #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, HVS_A, O>; -impl<'a, const O: u8> HVS_W<'a, O> { +pub type HVS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, HVS_A>; +impl<'a, REG, const O: u8> HVS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(HVS_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(HVS_A::EDGE) } } @@ -153,34 +127,37 @@ impl From for bool { impl RPIVID_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RPIVID_A { + pub const fn variant(&self) -> RPIVID_A { match self.bits { false => RPIVID_A::LEVEL, true => RPIVID_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == RPIVID_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == RPIVID_A::EDGE } } #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, RPIVID_A, O>; -impl<'a, const O: u8> RPIVID_W<'a, O> { +pub type RPIVID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, RPIVID_A>; +impl<'a, REG, const O: u8> RPIVID_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(RPIVID_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(RPIVID_A::EDGE) } } @@ -203,34 +180,37 @@ impl From for bool { impl SDC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SDC_A { + pub const fn variant(&self) -> SDC_A { match self.bits { false => SDC_A::LEVEL, true => SDC_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == SDC_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == SDC_A::EDGE } } #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, SDC_A, O>; -impl<'a, const O: u8> SDC_W<'a, O> { +pub type SDC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SDC_A>; +impl<'a, REG, const O: u8> SDC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(SDC_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(SDC_A::EDGE) } } @@ -253,34 +233,37 @@ impl From for bool { impl DSI_0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DSI_0_A { + pub const fn variant(&self) -> DSI_0_A { match self.bits { false => DSI_0_A::LEVEL, true => DSI_0_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DSI_0_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DSI_0_A::EDGE } } #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, DSI_0_A, O>; -impl<'a, const O: u8> DSI_0_W<'a, O> { +pub type DSI_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DSI_0_A>; +impl<'a, REG, const O: u8> DSI_0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DSI_0_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DSI_0_A::EDGE) } } @@ -303,35 +286,37 @@ impl From for bool { impl PIXEL_VALVE_2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PIXEL_VALVE_2_A { + pub const fn variant(&self) -> PIXEL_VALVE_2_A { match self.bits { false => PIXEL_VALVE_2_A::LEVEL, true => PIXEL_VALVE_2_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == PIXEL_VALVE_2_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == PIXEL_VALVE_2_A::EDGE } } #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, PIXEL_VALVE_2_A, O>; -impl<'a, const O: u8> PIXEL_VALVE_2_W<'a, O> { +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PIXEL_VALVE_2_A>; +impl<'a, REG, const O: u8> PIXEL_VALVE_2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(PIXEL_VALVE_2_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(PIXEL_VALVE_2_A::EDGE) } } @@ -354,34 +339,37 @@ impl From for bool { impl CAMERA_0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> CAMERA_0_A { + pub const fn variant(&self) -> CAMERA_0_A { match self.bits { false => CAMERA_0_A::LEVEL, true => CAMERA_0_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == CAMERA_0_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == CAMERA_0_A::EDGE } } #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, CAMERA_0_A, O>; -impl<'a, const O: u8> CAMERA_0_W<'a, O> { +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CAMERA_0_A>; +impl<'a, REG, const O: u8> CAMERA_0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(CAMERA_0_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(CAMERA_0_A::EDGE) } } @@ -404,34 +392,37 @@ impl From for bool { impl CAMERA_1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> CAMERA_1_A { + pub const fn variant(&self) -> CAMERA_1_A { match self.bits { false => CAMERA_1_A::LEVEL, true => CAMERA_1_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == CAMERA_1_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == CAMERA_1_A::EDGE } } #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, CAMERA_1_A, O>; -impl<'a, const O: u8> CAMERA_1_W<'a, O> { +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CAMERA_1_A>; +impl<'a, REG, const O: u8> CAMERA_1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(CAMERA_1_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(CAMERA_1_A::EDGE) } } @@ -454,34 +445,37 @@ impl From for bool { impl HDMI_0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> HDMI_0_A { + pub const fn variant(&self) -> HDMI_0_A { match self.bits { false => HDMI_0_A::LEVEL, true => HDMI_0_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == HDMI_0_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == HDMI_0_A::EDGE } } #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, HDMI_0_A, O>; -impl<'a, const O: u8> HDMI_0_W<'a, O> { +pub type HDMI_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, HDMI_0_A>; +impl<'a, REG, const O: u8> HDMI_0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(HDMI_0_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(HDMI_0_A::EDGE) } } @@ -504,34 +498,37 @@ impl From for bool { impl HDMI_1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> HDMI_1_A { + pub const fn variant(&self) -> HDMI_1_A { match self.bits { false => HDMI_1_A::LEVEL, true => HDMI_1_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == HDMI_1_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == HDMI_1_A::EDGE } } #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, HDMI_1_A, O>; -impl<'a, const O: u8> HDMI_1_W<'a, O> { +pub type HDMI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, HDMI_1_A>; +impl<'a, REG, const O: u8> HDMI_1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(HDMI_1_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(HDMI_1_A::EDGE) } } @@ -554,35 +551,37 @@ impl From for bool { impl PIXEL_VALVE_3_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PIXEL_VALVE_3_A { + pub const fn variant(&self) -> PIXEL_VALVE_3_A { match self.bits { false => PIXEL_VALVE_3_A::LEVEL, true => PIXEL_VALVE_3_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == PIXEL_VALVE_3_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == PIXEL_VALVE_3_A::EDGE } } #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, PIXEL_VALVE_3_A, O>; -impl<'a, const O: u8> PIXEL_VALVE_3_W<'a, O> { +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PIXEL_VALVE_3_A>; +impl<'a, REG, const O: u8> PIXEL_VALVE_3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(PIXEL_VALVE_3_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(PIXEL_VALVE_3_A::EDGE) } } @@ -605,35 +604,37 @@ impl From for bool { impl SPI_BSC_SLAVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SPI_BSC_SLAVE_A { + pub const fn variant(&self) -> SPI_BSC_SLAVE_A { match self.bits { false => SPI_BSC_SLAVE_A::LEVEL, true => SPI_BSC_SLAVE_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == SPI_BSC_SLAVE_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == SPI_BSC_SLAVE_A::EDGE } } #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, SPI_BSC_SLAVE_A, O>; -impl<'a, const O: u8> SPI_BSC_SLAVE_W<'a, O> { +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SPI_BSC_SLAVE_A>; +impl<'a, REG, const O: u8> SPI_BSC_SLAVE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(SPI_BSC_SLAVE_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(SPI_BSC_SLAVE_A::EDGE) } } @@ -656,34 +657,37 @@ impl From for bool { impl DSI_1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DSI_1_A { + pub const fn variant(&self) -> DSI_1_A { match self.bits { false => DSI_1_A::LEVEL, true => DSI_1_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == DSI_1_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == DSI_1_A::EDGE } } #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, DSI_1_A, O>; -impl<'a, const O: u8> DSI_1_W<'a, O> { +pub type DSI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DSI_1_A>; +impl<'a, REG, const O: u8> DSI_1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(DSI_1_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(DSI_1_A::EDGE) } } @@ -706,35 +710,37 @@ impl From for bool { impl PIXEL_VALVE_0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PIXEL_VALVE_0_A { + pub const fn variant(&self) -> PIXEL_VALVE_0_A { match self.bits { false => PIXEL_VALVE_0_A::LEVEL, true => PIXEL_VALVE_0_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == PIXEL_VALVE_0_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == PIXEL_VALVE_0_A::EDGE } } #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, PIXEL_VALVE_0_A, O>; -impl<'a, const O: u8> PIXEL_VALVE_0_W<'a, O> { +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PIXEL_VALVE_0_A>; +impl<'a, REG, const O: u8> PIXEL_VALVE_0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(PIXEL_VALVE_0_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(PIXEL_VALVE_0_A::EDGE) } } @@ -757,35 +763,37 @@ impl From for bool { impl PIXEL_VALVE_1_2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PIXEL_VALVE_1_2_A { + pub const fn variant(&self) -> PIXEL_VALVE_1_2_A { match self.bits { false => PIXEL_VALVE_1_2_A::LEVEL, true => PIXEL_VALVE_1_2_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == PIXEL_VALVE_1_2_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == PIXEL_VALVE_1_2_A::EDGE } } #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, PIXEL_VALVE_1_2_A, O>; -impl<'a, const O: u8> PIXEL_VALVE_1_2_W<'a, O> { +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PIXEL_VALVE_1_2_A>; +impl<'a, REG, const O: u8> PIXEL_VALVE_1_2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(PIXEL_VALVE_1_2_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(PIXEL_VALVE_1_2_A::EDGE) } } @@ -808,34 +816,37 @@ impl From for bool { impl CPR_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> CPR_A { + pub const fn variant(&self) -> CPR_A { match self.bits { false => CPR_A::LEVEL, true => CPR_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == CPR_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == CPR_A::EDGE } } #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR32_SPEC, CPR_A, O>; -impl<'a, const O: u8> CPR_W<'a, O> { +pub type CPR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CPR_A>; +impl<'a, REG, const O: u8> CPR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(CPR_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(CPR_A::EDGE) } } @@ -921,122 +932,165 @@ impl R { CPR_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR32") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<1> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bit 3 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<3> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bit 5 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<5> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bit 7 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<7> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } #[doc = "Bit 9 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<9> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bit 11 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<11> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bit 13 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<13> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bit 15 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<15> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } #[doc = "Bit 17 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<17> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bit 19 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<19> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bit 21 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<21> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bit 23 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<23> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } #[doc = "Bit 25 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<25> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bit 27 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<27> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bit 29 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<29> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bit 31 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<31> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 128 - 143\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr32](index.html) module"] +#[doc = "Interrupt Configuration 128 - 143\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr32::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr32::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR32_SPEC; impl crate::RegisterSpec for GICD_ICFGR32_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr32::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR32_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr32::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr32::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR32_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr32::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR32_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr36.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr36.rs index bc05ab7..bcacc71 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr36.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr36.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR36` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR36` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SMI` reader - SMI"] pub type SMI_R = crate::BitReader; #[doc = "SMI\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl SMI_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SMI_A { + pub const fn variant(&self) -> SMI_A { match self.bits { false => SMI_A::LEVEL, true => SMI_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == SMI_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == SMI_A::EDGE } } #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, SMI_A, O>; -impl<'a, const O: u8> SMI_W<'a, O> { +pub type SMI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SMI_A>; +impl<'a, REG, const O: u8> SMI_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(SMI_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(SMI_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl GPIO_0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> GPIO_0_A { + pub const fn variant(&self) -> GPIO_0_A { match self.bits { false => GPIO_0_A::LEVEL, true => GPIO_0_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == GPIO_0_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == GPIO_0_A::EDGE } } #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, GPIO_0_A, O>; -impl<'a, const O: u8> GPIO_0_W<'a, O> { +pub type GPIO_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, GPIO_0_A>; +impl<'a, REG, const O: u8> GPIO_0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(GPIO_0_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(GPIO_0_A::EDGE) } } @@ -153,34 +127,37 @@ impl From for bool { impl GPIO_1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> GPIO_1_A { + pub const fn variant(&self) -> GPIO_1_A { match self.bits { false => GPIO_1_A::LEVEL, true => GPIO_1_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == GPIO_1_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == GPIO_1_A::EDGE } } #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, GPIO_1_A, O>; -impl<'a, const O: u8> GPIO_1_W<'a, O> { +pub type GPIO_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, GPIO_1_A>; +impl<'a, REG, const O: u8> GPIO_1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(GPIO_1_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(GPIO_1_A::EDGE) } } @@ -203,34 +180,37 @@ impl From for bool { impl GPIO_2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> GPIO_2_A { + pub const fn variant(&self) -> GPIO_2_A { match self.bits { false => GPIO_2_A::LEVEL, true => GPIO_2_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == GPIO_2_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == GPIO_2_A::EDGE } } #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, GPIO_2_A, O>; -impl<'a, const O: u8> GPIO_2_W<'a, O> { +pub type GPIO_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, GPIO_2_A>; +impl<'a, REG, const O: u8> GPIO_2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(GPIO_2_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(GPIO_2_A::EDGE) } } @@ -253,34 +233,37 @@ impl From for bool { impl GPIO_3_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> GPIO_3_A { + pub const fn variant(&self) -> GPIO_3_A { match self.bits { false => GPIO_3_A::LEVEL, true => GPIO_3_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == GPIO_3_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == GPIO_3_A::EDGE } } #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, GPIO_3_A, O>; -impl<'a, const O: u8> GPIO_3_W<'a, O> { +pub type GPIO_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, GPIO_3_A>; +impl<'a, REG, const O: u8> GPIO_3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(GPIO_3_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(GPIO_3_A::EDGE) } } @@ -303,34 +286,37 @@ impl From for bool { impl I2C_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> I2C_A { + pub const fn variant(&self) -> I2C_A { match self.bits { false => I2C_A::LEVEL, true => I2C_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == I2C_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == I2C_A::EDGE } } #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, I2C_A, O>; -impl<'a, const O: u8> I2C_W<'a, O> { +pub type I2C_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, I2C_A>; +impl<'a, REG, const O: u8> I2C_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(I2C_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(I2C_A::EDGE) } } @@ -353,34 +339,37 @@ impl From for bool { impl SPI_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SPI_A { + pub const fn variant(&self) -> SPI_A { match self.bits { false => SPI_A::LEVEL, true => SPI_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == SPI_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == SPI_A::EDGE } } #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, SPI_A, O>; -impl<'a, const O: u8> SPI_W<'a, O> { +pub type SPI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SPI_A>; +impl<'a, REG, const O: u8> SPI_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(SPI_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(SPI_A::EDGE) } } @@ -403,34 +392,37 @@ impl From for bool { impl PCM_I2S_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PCM_I2S_A { + pub const fn variant(&self) -> PCM_I2S_A { match self.bits { false => PCM_I2S_A::LEVEL, true => PCM_I2S_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == PCM_I2S_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == PCM_I2S_A::EDGE } } #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, PCM_I2S_A, O>; -impl<'a, const O: u8> PCM_I2S_W<'a, O> { +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PCM_I2S_A>; +impl<'a, REG, const O: u8> PCM_I2S_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(PCM_I2S_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(PCM_I2S_A::EDGE) } } @@ -453,34 +445,37 @@ impl From for bool { impl SDHOST_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SDHOST_A { + pub const fn variant(&self) -> SDHOST_A { match self.bits { false => SDHOST_A::LEVEL, true => SDHOST_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == SDHOST_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == SDHOST_A::EDGE } } #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, SDHOST_A, O>; -impl<'a, const O: u8> SDHOST_W<'a, O> { +pub type SDHOST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SDHOST_A>; +impl<'a, REG, const O: u8> SDHOST_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(SDHOST_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(SDHOST_A::EDGE) } } @@ -503,34 +498,37 @@ impl From for bool { impl UART_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> UART_A { + pub const fn variant(&self) -> UART_A { match self.bits { false => UART_A::LEVEL, true => UART_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == UART_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == UART_A::EDGE } } #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, UART_A, O>; -impl<'a, const O: u8> UART_W<'a, O> { +pub type UART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, UART_A>; +impl<'a, REG, const O: u8> UART_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(UART_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(UART_A::EDGE) } } @@ -553,34 +551,37 @@ impl From for bool { impl ETH_PCIE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ETH_PCIE_A { + pub const fn variant(&self) -> ETH_PCIE_A { match self.bits { false => ETH_PCIE_A::LEVEL, true => ETH_PCIE_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == ETH_PCIE_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == ETH_PCIE_A::EDGE } } #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, ETH_PCIE_A, O>; -impl<'a, const O: u8> ETH_PCIE_W<'a, O> { +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ETH_PCIE_A>; +impl<'a, REG, const O: u8> ETH_PCIE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(ETH_PCIE_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(ETH_PCIE_A::EDGE) } } @@ -603,34 +604,37 @@ impl From for bool { impl VEC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> VEC_A { + pub const fn variant(&self) -> VEC_A { match self.bits { false => VEC_A::LEVEL, true => VEC_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == VEC_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == VEC_A::EDGE } } #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, VEC_A, O>; -impl<'a, const O: u8> VEC_W<'a, O> { +pub type VEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, VEC_A>; +impl<'a, REG, const O: u8> VEC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(VEC_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(VEC_A::EDGE) } } @@ -653,34 +657,37 @@ impl From for bool { impl CPG_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> CPG_A { + pub const fn variant(&self) -> CPG_A { match self.bits { false => CPG_A::LEVEL, true => CPG_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == CPG_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == CPG_A::EDGE } } #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, CPG_A, O>; -impl<'a, const O: u8> CPG_W<'a, O> { +pub type CPG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CPG_A>; +impl<'a, REG, const O: u8> CPG_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(CPG_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(CPG_A::EDGE) } } @@ -703,34 +710,37 @@ impl From for bool { impl RNG_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RNG_A { + pub const fn variant(&self) -> RNG_A { match self.bits { false => RNG_A::LEVEL, true => RNG_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == RNG_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == RNG_A::EDGE } } #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, RNG_A, O>; -impl<'a, const O: u8> RNG_W<'a, O> { +pub type RNG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, RNG_A>; +impl<'a, REG, const O: u8> RNG_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(RNG_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(RNG_A::EDGE) } } @@ -753,34 +763,37 @@ impl From for bool { impl EMMC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> EMMC_A { + pub const fn variant(&self) -> EMMC_A { match self.bits { false => EMMC_A::LEVEL, true => EMMC_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == EMMC_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == EMMC_A::EDGE } } #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, EMMC_A, O>; -impl<'a, const O: u8> EMMC_W<'a, O> { +pub type EMMC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, EMMC_A>; +impl<'a, REG, const O: u8> EMMC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(EMMC_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(EMMC_A::EDGE) } } @@ -803,35 +816,37 @@ impl From for bool { impl ETH_PCIE_SECURE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ETH_PCIE_SECURE_A { + pub const fn variant(&self) -> ETH_PCIE_SECURE_A { match self.bits { false => ETH_PCIE_SECURE_A::LEVEL, true => ETH_PCIE_SECURE_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == ETH_PCIE_SECURE_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == ETH_PCIE_SECURE_A::EDGE } } #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_ICFGR36_SPEC, ETH_PCIE_SECURE_A, O>; -impl<'a, const O: u8> ETH_PCIE_SECURE_W<'a, O> { +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ETH_PCIE_SECURE_A>; +impl<'a, REG, const O: u8> ETH_PCIE_SECURE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(ETH_PCIE_SECURE_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(ETH_PCIE_SECURE_A::EDGE) } } @@ -917,122 +932,153 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR36") + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<1> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bit 3 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<3> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bit 5 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<5> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bit 7 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<7> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } #[doc = "Bit 9 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<9> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bit 11 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<11> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bit 13 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<13> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bit 15 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<15> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } #[doc = "Bit 17 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<17> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bit 19 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<19> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bit 21 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<21> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bit 23 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<23> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } #[doc = "Bit 25 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<25> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bit 27 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<27> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bit 29 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<29> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bit 31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 144 - 159\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr36](index.html) module"] +#[doc = "Interrupt Configuration 144 - 159\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr36::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr36::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR36_SPEC; impl crate::RegisterSpec for GICD_ICFGR36_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr36::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR36_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr36::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr36::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR36_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr36::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR36_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr4.rs index f2835e9..9c1e7c0 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr4.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr4.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT16` reader - Interrupt 16"] pub type INT16_R = crate::BitReader; #[doc = "Interrupt 16\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl INT16_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT16_A { + pub const fn variant(&self) -> INT16_A { match self.bits { false => INT16_A::LEVEL, true => INT16_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT16_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT16_A::EDGE } } #[doc = "Field `INT16` writer - Interrupt 16"] -pub type INT16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT16_A, O>; -impl<'a, const O: u8> INT16_W<'a, O> { +pub type INT16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT16_A>; +impl<'a, REG, const O: u8> INT16_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT16_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT16_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl INT17_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT17_A { + pub const fn variant(&self) -> INT17_A { match self.bits { false => INT17_A::LEVEL, true => INT17_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT17_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT17_A::EDGE } } #[doc = "Field `INT17` writer - Interrupt 17"] -pub type INT17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT17_A, O>; -impl<'a, const O: u8> INT17_W<'a, O> { +pub type INT17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT17_A>; +impl<'a, REG, const O: u8> INT17_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT17_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT17_A::EDGE) } } @@ -153,34 +127,37 @@ impl From for bool { impl INT18_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT18_A { + pub const fn variant(&self) -> INT18_A { match self.bits { false => INT18_A::LEVEL, true => INT18_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT18_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT18_A::EDGE } } #[doc = "Field `INT18` writer - Interrupt 18"] -pub type INT18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT18_A, O>; -impl<'a, const O: u8> INT18_W<'a, O> { +pub type INT18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT18_A>; +impl<'a, REG, const O: u8> INT18_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT18_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT18_A::EDGE) } } @@ -203,34 +180,37 @@ impl From for bool { impl INT19_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT19_A { + pub const fn variant(&self) -> INT19_A { match self.bits { false => INT19_A::LEVEL, true => INT19_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT19_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT19_A::EDGE } } #[doc = "Field `INT19` writer - Interrupt 19"] -pub type INT19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT19_A, O>; -impl<'a, const O: u8> INT19_W<'a, O> { +pub type INT19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT19_A>; +impl<'a, REG, const O: u8> INT19_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT19_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT19_A::EDGE) } } @@ -253,34 +233,37 @@ impl From for bool { impl INT20_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT20_A { + pub const fn variant(&self) -> INT20_A { match self.bits { false => INT20_A::LEVEL, true => INT20_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT20_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT20_A::EDGE } } #[doc = "Field `INT20` writer - Interrupt 20"] -pub type INT20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT20_A, O>; -impl<'a, const O: u8> INT20_W<'a, O> { +pub type INT20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT20_A>; +impl<'a, REG, const O: u8> INT20_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT20_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT20_A::EDGE) } } @@ -303,34 +286,37 @@ impl From for bool { impl INT21_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT21_A { + pub const fn variant(&self) -> INT21_A { match self.bits { false => INT21_A::LEVEL, true => INT21_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT21_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT21_A::EDGE } } #[doc = "Field `INT21` writer - Interrupt 21"] -pub type INT21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT21_A, O>; -impl<'a, const O: u8> INT21_W<'a, O> { +pub type INT21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT21_A>; +impl<'a, REG, const O: u8> INT21_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT21_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT21_A::EDGE) } } @@ -353,34 +339,37 @@ impl From for bool { impl INT22_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT22_A { + pub const fn variant(&self) -> INT22_A { match self.bits { false => INT22_A::LEVEL, true => INT22_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT22_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT22_A::EDGE } } #[doc = "Field `INT22` writer - Interrupt 22"] -pub type INT22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT22_A, O>; -impl<'a, const O: u8> INT22_W<'a, O> { +pub type INT22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT22_A>; +impl<'a, REG, const O: u8> INT22_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT22_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT22_A::EDGE) } } @@ -403,34 +392,37 @@ impl From for bool { impl INT23_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT23_A { + pub const fn variant(&self) -> INT23_A { match self.bits { false => INT23_A::LEVEL, true => INT23_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT23_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT23_A::EDGE } } #[doc = "Field `INT23` writer - Interrupt 23"] -pub type INT23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT23_A, O>; -impl<'a, const O: u8> INT23_W<'a, O> { +pub type INT23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT23_A>; +impl<'a, REG, const O: u8> INT23_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT23_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT23_A::EDGE) } } @@ -453,34 +445,37 @@ impl From for bool { impl INT24_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT24_A { + pub const fn variant(&self) -> INT24_A { match self.bits { false => INT24_A::LEVEL, true => INT24_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT24_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT24_A::EDGE } } #[doc = "Field `INT24` writer - Interrupt 24"] -pub type INT24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT24_A, O>; -impl<'a, const O: u8> INT24_W<'a, O> { +pub type INT24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT24_A>; +impl<'a, REG, const O: u8> INT24_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT24_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT24_A::EDGE) } } @@ -503,34 +498,37 @@ impl From for bool { impl INT25_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT25_A { + pub const fn variant(&self) -> INT25_A { match self.bits { false => INT25_A::LEVEL, true => INT25_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT25_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT25_A::EDGE } } #[doc = "Field `INT25` writer - Interrupt 25"] -pub type INT25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT25_A, O>; -impl<'a, const O: u8> INT25_W<'a, O> { +pub type INT25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT25_A>; +impl<'a, REG, const O: u8> INT25_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT25_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT25_A::EDGE) } } @@ -553,34 +551,37 @@ impl From for bool { impl INT26_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT26_A { + pub const fn variant(&self) -> INT26_A { match self.bits { false => INT26_A::LEVEL, true => INT26_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT26_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT26_A::EDGE } } #[doc = "Field `INT26` writer - Interrupt 26"] -pub type INT26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT26_A, O>; -impl<'a, const O: u8> INT26_W<'a, O> { +pub type INT26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT26_A>; +impl<'a, REG, const O: u8> INT26_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT26_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT26_A::EDGE) } } @@ -603,34 +604,37 @@ impl From for bool { impl INT27_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT27_A { + pub const fn variant(&self) -> INT27_A { match self.bits { false => INT27_A::LEVEL, true => INT27_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT27_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT27_A::EDGE } } #[doc = "Field `INT27` writer - Interrupt 27"] -pub type INT27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT27_A, O>; -impl<'a, const O: u8> INT27_W<'a, O> { +pub type INT27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT27_A>; +impl<'a, REG, const O: u8> INT27_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT27_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT27_A::EDGE) } } @@ -653,34 +657,37 @@ impl From for bool { impl INT28_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT28_A { + pub const fn variant(&self) -> INT28_A { match self.bits { false => INT28_A::LEVEL, true => INT28_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT28_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT28_A::EDGE } } #[doc = "Field `INT28` writer - Interrupt 28"] -pub type INT28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT28_A, O>; -impl<'a, const O: u8> INT28_W<'a, O> { +pub type INT28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT28_A>; +impl<'a, REG, const O: u8> INT28_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT28_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT28_A::EDGE) } } @@ -703,34 +710,37 @@ impl From for bool { impl INT29_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT29_A { + pub const fn variant(&self) -> INT29_A { match self.bits { false => INT29_A::LEVEL, true => INT29_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT29_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT29_A::EDGE } } #[doc = "Field `INT29` writer - Interrupt 29"] -pub type INT29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT29_A, O>; -impl<'a, const O: u8> INT29_W<'a, O> { +pub type INT29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT29_A>; +impl<'a, REG, const O: u8> INT29_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT29_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT29_A::EDGE) } } @@ -753,34 +763,37 @@ impl From for bool { impl INT30_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT30_A { + pub const fn variant(&self) -> INT30_A { match self.bits { false => INT30_A::LEVEL, true => INT30_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT30_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT30_A::EDGE } } #[doc = "Field `INT30` writer - Interrupt 30"] -pub type INT30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT30_A, O>; -impl<'a, const O: u8> INT30_W<'a, O> { +pub type INT30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT30_A>; +impl<'a, REG, const O: u8> INT30_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT30_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT30_A::EDGE) } } @@ -803,34 +816,37 @@ impl From for bool { impl INT31_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT31_A { + pub const fn variant(&self) -> INT31_A { match self.bits { false => INT31_A::LEVEL, true => INT31_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT31_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT31_A::EDGE } } #[doc = "Field `INT31` writer - Interrupt 31"] -pub type INT31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR4_SPEC, INT31_A, O>; -impl<'a, const O: u8> INT31_W<'a, O> { +pub type INT31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT31_A>; +impl<'a, REG, const O: u8> INT31_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT31_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT31_A::EDGE) } } @@ -916,122 +932,150 @@ impl R { INT31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR4") + .field("int16", &format_args!("{}", self.int16().bit())) + .field("int17", &format_args!("{}", self.int17().bit())) + .field("int18", &format_args!("{}", self.int18().bit())) + .field("int19", &format_args!("{}", self.int19().bit())) + .field("int20", &format_args!("{}", self.int20().bit())) + .field("int21", &format_args!("{}", self.int21().bit())) + .field("int22", &format_args!("{}", self.int22().bit())) + .field("int23", &format_args!("{}", self.int23().bit())) + .field("int24", &format_args!("{}", self.int24().bit())) + .field("int25", &format_args!("{}", self.int25().bit())) + .field("int26", &format_args!("{}", self.int26().bit())) + .field("int27", &format_args!("{}", self.int27().bit())) + .field("int28", &format_args!("{}", self.int28().bit())) + .field("int29", &format_args!("{}", self.int29().bit())) + .field("int30", &format_args!("{}", self.int30().bit())) + .field("int31", &format_args!("{}", self.int31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Interrupt 16"] #[inline(always)] #[must_use] - pub fn int16(&mut self) -> INT16_W<1> { + pub fn int16(&mut self) -> INT16_W { INT16_W::new(self) } #[doc = "Bit 3 - Interrupt 17"] #[inline(always)] #[must_use] - pub fn int17(&mut self) -> INT17_W<3> { + pub fn int17(&mut self) -> INT17_W { INT17_W::new(self) } #[doc = "Bit 5 - Interrupt 18"] #[inline(always)] #[must_use] - pub fn int18(&mut self) -> INT18_W<5> { + pub fn int18(&mut self) -> INT18_W { INT18_W::new(self) } #[doc = "Bit 7 - Interrupt 19"] #[inline(always)] #[must_use] - pub fn int19(&mut self) -> INT19_W<7> { + pub fn int19(&mut self) -> INT19_W { INT19_W::new(self) } #[doc = "Bit 9 - Interrupt 20"] #[inline(always)] #[must_use] - pub fn int20(&mut self) -> INT20_W<9> { + pub fn int20(&mut self) -> INT20_W { INT20_W::new(self) } #[doc = "Bit 11 - Interrupt 21"] #[inline(always)] #[must_use] - pub fn int21(&mut self) -> INT21_W<11> { + pub fn int21(&mut self) -> INT21_W { INT21_W::new(self) } #[doc = "Bit 13 - Interrupt 22"] #[inline(always)] #[must_use] - pub fn int22(&mut self) -> INT22_W<13> { + pub fn int22(&mut self) -> INT22_W { INT22_W::new(self) } #[doc = "Bit 15 - Interrupt 23"] #[inline(always)] #[must_use] - pub fn int23(&mut self) -> INT23_W<15> { + pub fn int23(&mut self) -> INT23_W { INT23_W::new(self) } #[doc = "Bit 17 - Interrupt 24"] #[inline(always)] #[must_use] - pub fn int24(&mut self) -> INT24_W<17> { + pub fn int24(&mut self) -> INT24_W { INT24_W::new(self) } #[doc = "Bit 19 - Interrupt 25"] #[inline(always)] #[must_use] - pub fn int25(&mut self) -> INT25_W<19> { + pub fn int25(&mut self) -> INT25_W { INT25_W::new(self) } #[doc = "Bit 21 - Interrupt 26"] #[inline(always)] #[must_use] - pub fn int26(&mut self) -> INT26_W<21> { + pub fn int26(&mut self) -> INT26_W { INT26_W::new(self) } #[doc = "Bit 23 - Interrupt 27"] #[inline(always)] #[must_use] - pub fn int27(&mut self) -> INT27_W<23> { + pub fn int27(&mut self) -> INT27_W { INT27_W::new(self) } #[doc = "Bit 25 - Interrupt 28"] #[inline(always)] #[must_use] - pub fn int28(&mut self) -> INT28_W<25> { + pub fn int28(&mut self) -> INT28_W { INT28_W::new(self) } #[doc = "Bit 27 - Interrupt 29"] #[inline(always)] #[must_use] - pub fn int29(&mut self) -> INT29_W<27> { + pub fn int29(&mut self) -> INT29_W { INT29_W::new(self) } #[doc = "Bit 29 - Interrupt 30"] #[inline(always)] #[must_use] - pub fn int30(&mut self) -> INT30_W<29> { + pub fn int30(&mut self) -> INT30_W { INT30_W::new(self) } #[doc = "Bit 31 - Interrupt 31"] #[inline(always)] #[must_use] - pub fn int31(&mut self) -> INT31_W<31> { + pub fn int31(&mut self) -> INT31_W { INT31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 16 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr4](index.html) module"] +#[doc = "Interrupt Configuration 16 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR4_SPEC; impl crate::RegisterSpec for GICD_ICFGR4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr4::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr4::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr4::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr4::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr40.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr40.rs index 3bda818..e2984b7 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr40.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr40.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR40` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR40` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT160` reader - Interrupt 160"] pub type INT160_R = crate::BitReader; #[doc = "Interrupt 160\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl INT160_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT160_A { + pub const fn variant(&self) -> INT160_A { match self.bits { false => INT160_A::LEVEL, true => INT160_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT160_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT160_A::EDGE } } #[doc = "Field `INT160` writer - Interrupt 160"] -pub type INT160_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT160_A, O>; -impl<'a, const O: u8> INT160_W<'a, O> { +pub type INT160_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT160_A>; +impl<'a, REG, const O: u8> INT160_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT160_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT160_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl INT161_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT161_A { + pub const fn variant(&self) -> INT161_A { match self.bits { false => INT161_A::LEVEL, true => INT161_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT161_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT161_A::EDGE } } #[doc = "Field `INT161` writer - Interrupt 161"] -pub type INT161_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT161_A, O>; -impl<'a, const O: u8> INT161_W<'a, O> { +pub type INT161_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT161_A>; +impl<'a, REG, const O: u8> INT161_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT161_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT161_A::EDGE) } } @@ -153,34 +127,37 @@ impl From for bool { impl INT162_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT162_A { + pub const fn variant(&self) -> INT162_A { match self.bits { false => INT162_A::LEVEL, true => INT162_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT162_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT162_A::EDGE } } #[doc = "Field `INT162` writer - Interrupt 162"] -pub type INT162_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT162_A, O>; -impl<'a, const O: u8> INT162_W<'a, O> { +pub type INT162_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT162_A>; +impl<'a, REG, const O: u8> INT162_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT162_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT162_A::EDGE) } } @@ -203,34 +180,37 @@ impl From for bool { impl INT163_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT163_A { + pub const fn variant(&self) -> INT163_A { match self.bits { false => INT163_A::LEVEL, true => INT163_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT163_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT163_A::EDGE } } #[doc = "Field `INT163` writer - Interrupt 163"] -pub type INT163_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT163_A, O>; -impl<'a, const O: u8> INT163_W<'a, O> { +pub type INT163_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT163_A>; +impl<'a, REG, const O: u8> INT163_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT163_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT163_A::EDGE) } } @@ -253,34 +233,37 @@ impl From for bool { impl INT164_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT164_A { + pub const fn variant(&self) -> INT164_A { match self.bits { false => INT164_A::LEVEL, true => INT164_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT164_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT164_A::EDGE } } #[doc = "Field `INT164` writer - Interrupt 164"] -pub type INT164_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT164_A, O>; -impl<'a, const O: u8> INT164_W<'a, O> { +pub type INT164_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT164_A>; +impl<'a, REG, const O: u8> INT164_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT164_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT164_A::EDGE) } } @@ -303,34 +286,37 @@ impl From for bool { impl INT165_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT165_A { + pub const fn variant(&self) -> INT165_A { match self.bits { false => INT165_A::LEVEL, true => INT165_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT165_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT165_A::EDGE } } #[doc = "Field `INT165` writer - Interrupt 165"] -pub type INT165_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT165_A, O>; -impl<'a, const O: u8> INT165_W<'a, O> { +pub type INT165_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT165_A>; +impl<'a, REG, const O: u8> INT165_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT165_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT165_A::EDGE) } } @@ -353,34 +339,37 @@ impl From for bool { impl INT166_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT166_A { + pub const fn variant(&self) -> INT166_A { match self.bits { false => INT166_A::LEVEL, true => INT166_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT166_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT166_A::EDGE } } #[doc = "Field `INT166` writer - Interrupt 166"] -pub type INT166_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT166_A, O>; -impl<'a, const O: u8> INT166_W<'a, O> { +pub type INT166_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT166_A>; +impl<'a, REG, const O: u8> INT166_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT166_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT166_A::EDGE) } } @@ -403,34 +392,37 @@ impl From for bool { impl INT167_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT167_A { + pub const fn variant(&self) -> INT167_A { match self.bits { false => INT167_A::LEVEL, true => INT167_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT167_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT167_A::EDGE } } #[doc = "Field `INT167` writer - Interrupt 167"] -pub type INT167_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT167_A, O>; -impl<'a, const O: u8> INT167_W<'a, O> { +pub type INT167_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT167_A>; +impl<'a, REG, const O: u8> INT167_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT167_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT167_A::EDGE) } } @@ -453,34 +445,37 @@ impl From for bool { impl INT168_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT168_A { + pub const fn variant(&self) -> INT168_A { match self.bits { false => INT168_A::LEVEL, true => INT168_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT168_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT168_A::EDGE } } #[doc = "Field `INT168` writer - Interrupt 168"] -pub type INT168_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT168_A, O>; -impl<'a, const O: u8> INT168_W<'a, O> { +pub type INT168_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT168_A>; +impl<'a, REG, const O: u8> INT168_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT168_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT168_A::EDGE) } } @@ -503,34 +498,37 @@ impl From for bool { impl INT169_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT169_A { + pub const fn variant(&self) -> INT169_A { match self.bits { false => INT169_A::LEVEL, true => INT169_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT169_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT169_A::EDGE } } #[doc = "Field `INT169` writer - Interrupt 169"] -pub type INT169_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT169_A, O>; -impl<'a, const O: u8> INT169_W<'a, O> { +pub type INT169_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT169_A>; +impl<'a, REG, const O: u8> INT169_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT169_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT169_A::EDGE) } } @@ -553,34 +551,37 @@ impl From for bool { impl INT170_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT170_A { + pub const fn variant(&self) -> INT170_A { match self.bits { false => INT170_A::LEVEL, true => INT170_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT170_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT170_A::EDGE } } #[doc = "Field `INT170` writer - Interrupt 170"] -pub type INT170_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT170_A, O>; -impl<'a, const O: u8> INT170_W<'a, O> { +pub type INT170_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT170_A>; +impl<'a, REG, const O: u8> INT170_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT170_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT170_A::EDGE) } } @@ -603,34 +604,37 @@ impl From for bool { impl INT171_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT171_A { + pub const fn variant(&self) -> INT171_A { match self.bits { false => INT171_A::LEVEL, true => INT171_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT171_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT171_A::EDGE } } #[doc = "Field `INT171` writer - Interrupt 171"] -pub type INT171_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT171_A, O>; -impl<'a, const O: u8> INT171_W<'a, O> { +pub type INT171_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT171_A>; +impl<'a, REG, const O: u8> INT171_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT171_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT171_A::EDGE) } } @@ -653,34 +657,37 @@ impl From for bool { impl INT172_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT172_A { + pub const fn variant(&self) -> INT172_A { match self.bits { false => INT172_A::LEVEL, true => INT172_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT172_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT172_A::EDGE } } #[doc = "Field `INT172` writer - Interrupt 172"] -pub type INT172_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT172_A, O>; -impl<'a, const O: u8> INT172_W<'a, O> { +pub type INT172_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT172_A>; +impl<'a, REG, const O: u8> INT172_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT172_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT172_A::EDGE) } } @@ -703,34 +710,37 @@ impl From for bool { impl INT173_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT173_A { + pub const fn variant(&self) -> INT173_A { match self.bits { false => INT173_A::LEVEL, true => INT173_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT173_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT173_A::EDGE } } #[doc = "Field `INT173` writer - Interrupt 173"] -pub type INT173_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT173_A, O>; -impl<'a, const O: u8> INT173_W<'a, O> { +pub type INT173_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT173_A>; +impl<'a, REG, const O: u8> INT173_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT173_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT173_A::EDGE) } } @@ -753,34 +763,37 @@ impl From for bool { impl INT174_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT174_A { + pub const fn variant(&self) -> INT174_A { match self.bits { false => INT174_A::LEVEL, true => INT174_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT174_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT174_A::EDGE } } #[doc = "Field `INT174` writer - Interrupt 174"] -pub type INT174_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT174_A, O>; -impl<'a, const O: u8> INT174_W<'a, O> { +pub type INT174_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT174_A>; +impl<'a, REG, const O: u8> INT174_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT174_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT174_A::EDGE) } } @@ -803,34 +816,37 @@ impl From for bool { impl INT175_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT175_A { + pub const fn variant(&self) -> INT175_A { match self.bits { false => INT175_A::LEVEL, true => INT175_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT175_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT175_A::EDGE } } #[doc = "Field `INT175` writer - Interrupt 175"] -pub type INT175_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR40_SPEC, INT175_A, O>; -impl<'a, const O: u8> INT175_W<'a, O> { +pub type INT175_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT175_A>; +impl<'a, REG, const O: u8> INT175_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT175_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT175_A::EDGE) } } @@ -916,122 +932,150 @@ impl R { INT175_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR40") + .field("int160", &format_args!("{}", self.int160().bit())) + .field("int161", &format_args!("{}", self.int161().bit())) + .field("int162", &format_args!("{}", self.int162().bit())) + .field("int163", &format_args!("{}", self.int163().bit())) + .field("int164", &format_args!("{}", self.int164().bit())) + .field("int165", &format_args!("{}", self.int165().bit())) + .field("int166", &format_args!("{}", self.int166().bit())) + .field("int167", &format_args!("{}", self.int167().bit())) + .field("int168", &format_args!("{}", self.int168().bit())) + .field("int169", &format_args!("{}", self.int169().bit())) + .field("int170", &format_args!("{}", self.int170().bit())) + .field("int171", &format_args!("{}", self.int171().bit())) + .field("int172", &format_args!("{}", self.int172().bit())) + .field("int173", &format_args!("{}", self.int173().bit())) + .field("int174", &format_args!("{}", self.int174().bit())) + .field("int175", &format_args!("{}", self.int175().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Interrupt 160"] #[inline(always)] #[must_use] - pub fn int160(&mut self) -> INT160_W<1> { + pub fn int160(&mut self) -> INT160_W { INT160_W::new(self) } #[doc = "Bit 3 - Interrupt 161"] #[inline(always)] #[must_use] - pub fn int161(&mut self) -> INT161_W<3> { + pub fn int161(&mut self) -> INT161_W { INT161_W::new(self) } #[doc = "Bit 5 - Interrupt 162"] #[inline(always)] #[must_use] - pub fn int162(&mut self) -> INT162_W<5> { + pub fn int162(&mut self) -> INT162_W { INT162_W::new(self) } #[doc = "Bit 7 - Interrupt 163"] #[inline(always)] #[must_use] - pub fn int163(&mut self) -> INT163_W<7> { + pub fn int163(&mut self) -> INT163_W { INT163_W::new(self) } #[doc = "Bit 9 - Interrupt 164"] #[inline(always)] #[must_use] - pub fn int164(&mut self) -> INT164_W<9> { + pub fn int164(&mut self) -> INT164_W { INT164_W::new(self) } #[doc = "Bit 11 - Interrupt 165"] #[inline(always)] #[must_use] - pub fn int165(&mut self) -> INT165_W<11> { + pub fn int165(&mut self) -> INT165_W { INT165_W::new(self) } #[doc = "Bit 13 - Interrupt 166"] #[inline(always)] #[must_use] - pub fn int166(&mut self) -> INT166_W<13> { + pub fn int166(&mut self) -> INT166_W { INT166_W::new(self) } #[doc = "Bit 15 - Interrupt 167"] #[inline(always)] #[must_use] - pub fn int167(&mut self) -> INT167_W<15> { + pub fn int167(&mut self) -> INT167_W { INT167_W::new(self) } #[doc = "Bit 17 - Interrupt 168"] #[inline(always)] #[must_use] - pub fn int168(&mut self) -> INT168_W<17> { + pub fn int168(&mut self) -> INT168_W { INT168_W::new(self) } #[doc = "Bit 19 - Interrupt 169"] #[inline(always)] #[must_use] - pub fn int169(&mut self) -> INT169_W<19> { + pub fn int169(&mut self) -> INT169_W { INT169_W::new(self) } #[doc = "Bit 21 - Interrupt 170"] #[inline(always)] #[must_use] - pub fn int170(&mut self) -> INT170_W<21> { + pub fn int170(&mut self) -> INT170_W { INT170_W::new(self) } #[doc = "Bit 23 - Interrupt 171"] #[inline(always)] #[must_use] - pub fn int171(&mut self) -> INT171_W<23> { + pub fn int171(&mut self) -> INT171_W { INT171_W::new(self) } #[doc = "Bit 25 - Interrupt 172"] #[inline(always)] #[must_use] - pub fn int172(&mut self) -> INT172_W<25> { + pub fn int172(&mut self) -> INT172_W { INT172_W::new(self) } #[doc = "Bit 27 - Interrupt 173"] #[inline(always)] #[must_use] - pub fn int173(&mut self) -> INT173_W<27> { + pub fn int173(&mut self) -> INT173_W { INT173_W::new(self) } #[doc = "Bit 29 - Interrupt 174"] #[inline(always)] #[must_use] - pub fn int174(&mut self) -> INT174_W<29> { + pub fn int174(&mut self) -> INT174_W { INT174_W::new(self) } #[doc = "Bit 31 - Interrupt 175"] #[inline(always)] #[must_use] - pub fn int175(&mut self) -> INT175_W<31> { + pub fn int175(&mut self) -> INT175_W { INT175_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 160 - 175\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr40](index.html) module"] +#[doc = "Interrupt Configuration 160 - 175\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr40::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr40::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR40_SPEC; impl crate::RegisterSpec for GICD_ICFGR40_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr40::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR40_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr40::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr40::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR40_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr40::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR40_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr44.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr44.rs index 9411024..bf618d2 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr44.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr44.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR44` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR44` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT176` reader - Interrupt 176"] pub type INT176_R = crate::BitReader; #[doc = "Interrupt 176\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl INT176_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT176_A { + pub const fn variant(&self) -> INT176_A { match self.bits { false => INT176_A::LEVEL, true => INT176_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT176_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT176_A::EDGE } } #[doc = "Field `INT176` writer - Interrupt 176"] -pub type INT176_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT176_A, O>; -impl<'a, const O: u8> INT176_W<'a, O> { +pub type INT176_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT176_A>; +impl<'a, REG, const O: u8> INT176_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT176_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT176_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl INT177_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT177_A { + pub const fn variant(&self) -> INT177_A { match self.bits { false => INT177_A::LEVEL, true => INT177_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT177_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT177_A::EDGE } } #[doc = "Field `INT177` writer - Interrupt 177"] -pub type INT177_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT177_A, O>; -impl<'a, const O: u8> INT177_W<'a, O> { +pub type INT177_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT177_A>; +impl<'a, REG, const O: u8> INT177_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT177_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT177_A::EDGE) } } @@ -153,34 +127,37 @@ impl From for bool { impl INT178_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT178_A { + pub const fn variant(&self) -> INT178_A { match self.bits { false => INT178_A::LEVEL, true => INT178_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT178_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT178_A::EDGE } } #[doc = "Field `INT178` writer - Interrupt 178"] -pub type INT178_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT178_A, O>; -impl<'a, const O: u8> INT178_W<'a, O> { +pub type INT178_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT178_A>; +impl<'a, REG, const O: u8> INT178_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT178_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT178_A::EDGE) } } @@ -203,34 +180,37 @@ impl From for bool { impl INT179_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT179_A { + pub const fn variant(&self) -> INT179_A { match self.bits { false => INT179_A::LEVEL, true => INT179_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT179_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT179_A::EDGE } } #[doc = "Field `INT179` writer - Interrupt 179"] -pub type INT179_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT179_A, O>; -impl<'a, const O: u8> INT179_W<'a, O> { +pub type INT179_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT179_A>; +impl<'a, REG, const O: u8> INT179_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT179_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT179_A::EDGE) } } @@ -253,34 +233,37 @@ impl From for bool { impl INT180_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT180_A { + pub const fn variant(&self) -> INT180_A { match self.bits { false => INT180_A::LEVEL, true => INT180_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT180_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT180_A::EDGE } } #[doc = "Field `INT180` writer - Interrupt 180"] -pub type INT180_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT180_A, O>; -impl<'a, const O: u8> INT180_W<'a, O> { +pub type INT180_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT180_A>; +impl<'a, REG, const O: u8> INT180_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT180_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT180_A::EDGE) } } @@ -303,34 +286,37 @@ impl From for bool { impl INT181_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT181_A { + pub const fn variant(&self) -> INT181_A { match self.bits { false => INT181_A::LEVEL, true => INT181_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT181_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT181_A::EDGE } } #[doc = "Field `INT181` writer - Interrupt 181"] -pub type INT181_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT181_A, O>; -impl<'a, const O: u8> INT181_W<'a, O> { +pub type INT181_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT181_A>; +impl<'a, REG, const O: u8> INT181_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT181_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT181_A::EDGE) } } @@ -353,34 +339,37 @@ impl From for bool { impl INT182_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT182_A { + pub const fn variant(&self) -> INT182_A { match self.bits { false => INT182_A::LEVEL, true => INT182_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT182_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT182_A::EDGE } } #[doc = "Field `INT182` writer - Interrupt 182"] -pub type INT182_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT182_A, O>; -impl<'a, const O: u8> INT182_W<'a, O> { +pub type INT182_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT182_A>; +impl<'a, REG, const O: u8> INT182_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT182_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT182_A::EDGE) } } @@ -403,34 +392,37 @@ impl From for bool { impl INT183_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT183_A { + pub const fn variant(&self) -> INT183_A { match self.bits { false => INT183_A::LEVEL, true => INT183_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT183_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT183_A::EDGE } } #[doc = "Field `INT183` writer - Interrupt 183"] -pub type INT183_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT183_A, O>; -impl<'a, const O: u8> INT183_W<'a, O> { +pub type INT183_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT183_A>; +impl<'a, REG, const O: u8> INT183_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT183_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT183_A::EDGE) } } @@ -453,34 +445,37 @@ impl From for bool { impl INT184_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT184_A { + pub const fn variant(&self) -> INT184_A { match self.bits { false => INT184_A::LEVEL, true => INT184_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT184_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT184_A::EDGE } } #[doc = "Field `INT184` writer - Interrupt 184"] -pub type INT184_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT184_A, O>; -impl<'a, const O: u8> INT184_W<'a, O> { +pub type INT184_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT184_A>; +impl<'a, REG, const O: u8> INT184_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT184_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT184_A::EDGE) } } @@ -503,34 +498,37 @@ impl From for bool { impl INT185_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT185_A { + pub const fn variant(&self) -> INT185_A { match self.bits { false => INT185_A::LEVEL, true => INT185_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT185_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT185_A::EDGE } } #[doc = "Field `INT185` writer - Interrupt 185"] -pub type INT185_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT185_A, O>; -impl<'a, const O: u8> INT185_W<'a, O> { +pub type INT185_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT185_A>; +impl<'a, REG, const O: u8> INT185_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT185_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT185_A::EDGE) } } @@ -553,34 +551,37 @@ impl From for bool { impl INT186_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT186_A { + pub const fn variant(&self) -> INT186_A { match self.bits { false => INT186_A::LEVEL, true => INT186_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT186_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT186_A::EDGE } } #[doc = "Field `INT186` writer - Interrupt 186"] -pub type INT186_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT186_A, O>; -impl<'a, const O: u8> INT186_W<'a, O> { +pub type INT186_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT186_A>; +impl<'a, REG, const O: u8> INT186_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT186_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT186_A::EDGE) } } @@ -603,34 +604,37 @@ impl From for bool { impl INT187_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT187_A { + pub const fn variant(&self) -> INT187_A { match self.bits { false => INT187_A::LEVEL, true => INT187_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT187_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT187_A::EDGE } } #[doc = "Field `INT187` writer - Interrupt 187"] -pub type INT187_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT187_A, O>; -impl<'a, const O: u8> INT187_W<'a, O> { +pub type INT187_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT187_A>; +impl<'a, REG, const O: u8> INT187_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT187_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT187_A::EDGE) } } @@ -653,34 +657,37 @@ impl From for bool { impl INT188_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT188_A { + pub const fn variant(&self) -> INT188_A { match self.bits { false => INT188_A::LEVEL, true => INT188_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT188_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT188_A::EDGE } } #[doc = "Field `INT188` writer - Interrupt 188"] -pub type INT188_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT188_A, O>; -impl<'a, const O: u8> INT188_W<'a, O> { +pub type INT188_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT188_A>; +impl<'a, REG, const O: u8> INT188_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT188_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT188_A::EDGE) } } @@ -703,34 +710,37 @@ impl From for bool { impl INT189_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT189_A { + pub const fn variant(&self) -> INT189_A { match self.bits { false => INT189_A::LEVEL, true => INT189_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT189_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT189_A::EDGE } } #[doc = "Field `INT189` writer - Interrupt 189"] -pub type INT189_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT189_A, O>; -impl<'a, const O: u8> INT189_W<'a, O> { +pub type INT189_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT189_A>; +impl<'a, REG, const O: u8> INT189_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT189_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT189_A::EDGE) } } @@ -753,34 +763,37 @@ impl From for bool { impl INT190_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT190_A { + pub const fn variant(&self) -> INT190_A { match self.bits { false => INT190_A::LEVEL, true => INT190_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT190_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT190_A::EDGE } } #[doc = "Field `INT190` writer - Interrupt 190"] -pub type INT190_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT190_A, O>; -impl<'a, const O: u8> INT190_W<'a, O> { +pub type INT190_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT190_A>; +impl<'a, REG, const O: u8> INT190_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT190_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT190_A::EDGE) } } @@ -803,34 +816,37 @@ impl From for bool { impl INT191_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT191_A { + pub const fn variant(&self) -> INT191_A { match self.bits { false => INT191_A::LEVEL, true => INT191_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT191_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT191_A::EDGE } } #[doc = "Field `INT191` writer - Interrupt 191"] -pub type INT191_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR44_SPEC, INT191_A, O>; -impl<'a, const O: u8> INT191_W<'a, O> { +pub type INT191_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT191_A>; +impl<'a, REG, const O: u8> INT191_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT191_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT191_A::EDGE) } } @@ -916,122 +932,150 @@ impl R { INT191_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR44") + .field("int176", &format_args!("{}", self.int176().bit())) + .field("int177", &format_args!("{}", self.int177().bit())) + .field("int178", &format_args!("{}", self.int178().bit())) + .field("int179", &format_args!("{}", self.int179().bit())) + .field("int180", &format_args!("{}", self.int180().bit())) + .field("int181", &format_args!("{}", self.int181().bit())) + .field("int182", &format_args!("{}", self.int182().bit())) + .field("int183", &format_args!("{}", self.int183().bit())) + .field("int184", &format_args!("{}", self.int184().bit())) + .field("int185", &format_args!("{}", self.int185().bit())) + .field("int186", &format_args!("{}", self.int186().bit())) + .field("int187", &format_args!("{}", self.int187().bit())) + .field("int188", &format_args!("{}", self.int188().bit())) + .field("int189", &format_args!("{}", self.int189().bit())) + .field("int190", &format_args!("{}", self.int190().bit())) + .field("int191", &format_args!("{}", self.int191().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Interrupt 176"] #[inline(always)] #[must_use] - pub fn int176(&mut self) -> INT176_W<1> { + pub fn int176(&mut self) -> INT176_W { INT176_W::new(self) } #[doc = "Bit 3 - Interrupt 177"] #[inline(always)] #[must_use] - pub fn int177(&mut self) -> INT177_W<3> { + pub fn int177(&mut self) -> INT177_W { INT177_W::new(self) } #[doc = "Bit 5 - Interrupt 178"] #[inline(always)] #[must_use] - pub fn int178(&mut self) -> INT178_W<5> { + pub fn int178(&mut self) -> INT178_W { INT178_W::new(self) } #[doc = "Bit 7 - Interrupt 179"] #[inline(always)] #[must_use] - pub fn int179(&mut self) -> INT179_W<7> { + pub fn int179(&mut self) -> INT179_W { INT179_W::new(self) } #[doc = "Bit 9 - Interrupt 180"] #[inline(always)] #[must_use] - pub fn int180(&mut self) -> INT180_W<9> { + pub fn int180(&mut self) -> INT180_W { INT180_W::new(self) } #[doc = "Bit 11 - Interrupt 181"] #[inline(always)] #[must_use] - pub fn int181(&mut self) -> INT181_W<11> { + pub fn int181(&mut self) -> INT181_W { INT181_W::new(self) } #[doc = "Bit 13 - Interrupt 182"] #[inline(always)] #[must_use] - pub fn int182(&mut self) -> INT182_W<13> { + pub fn int182(&mut self) -> INT182_W { INT182_W::new(self) } #[doc = "Bit 15 - Interrupt 183"] #[inline(always)] #[must_use] - pub fn int183(&mut self) -> INT183_W<15> { + pub fn int183(&mut self) -> INT183_W { INT183_W::new(self) } #[doc = "Bit 17 - Interrupt 184"] #[inline(always)] #[must_use] - pub fn int184(&mut self) -> INT184_W<17> { + pub fn int184(&mut self) -> INT184_W { INT184_W::new(self) } #[doc = "Bit 19 - Interrupt 185"] #[inline(always)] #[must_use] - pub fn int185(&mut self) -> INT185_W<19> { + pub fn int185(&mut self) -> INT185_W { INT185_W::new(self) } #[doc = "Bit 21 - Interrupt 186"] #[inline(always)] #[must_use] - pub fn int186(&mut self) -> INT186_W<21> { + pub fn int186(&mut self) -> INT186_W { INT186_W::new(self) } #[doc = "Bit 23 - Interrupt 187"] #[inline(always)] #[must_use] - pub fn int187(&mut self) -> INT187_W<23> { + pub fn int187(&mut self) -> INT187_W { INT187_W::new(self) } #[doc = "Bit 25 - Interrupt 188"] #[inline(always)] #[must_use] - pub fn int188(&mut self) -> INT188_W<25> { + pub fn int188(&mut self) -> INT188_W { INT188_W::new(self) } #[doc = "Bit 27 - Interrupt 189"] #[inline(always)] #[must_use] - pub fn int189(&mut self) -> INT189_W<27> { + pub fn int189(&mut self) -> INT189_W { INT189_W::new(self) } #[doc = "Bit 29 - Interrupt 190"] #[inline(always)] #[must_use] - pub fn int190(&mut self) -> INT190_W<29> { + pub fn int190(&mut self) -> INT190_W { INT190_W::new(self) } #[doc = "Bit 31 - Interrupt 191"] #[inline(always)] #[must_use] - pub fn int191(&mut self) -> INT191_W<31> { + pub fn int191(&mut self) -> INT191_W { INT191_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 176 - 191\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr44](index.html) module"] +#[doc = "Interrupt Configuration 176 - 191\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr44::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr44::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR44_SPEC; impl crate::RegisterSpec for GICD_ICFGR44_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr44::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR44_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr44::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr44::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR44_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr44::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR44_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr48.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr48.rs index 13e56f7..e315e8e 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr48.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr48.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR48` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR48` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT192` reader - Interrupt 192"] pub type INT192_R = crate::BitReader; #[doc = "Interrupt 192\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl INT192_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT192_A { + pub const fn variant(&self) -> INT192_A { match self.bits { false => INT192_A::LEVEL, true => INT192_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT192_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT192_A::EDGE } } #[doc = "Field `INT192` writer - Interrupt 192"] -pub type INT192_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT192_A, O>; -impl<'a, const O: u8> INT192_W<'a, O> { +pub type INT192_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT192_A>; +impl<'a, REG, const O: u8> INT192_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT192_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT192_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl INT193_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT193_A { + pub const fn variant(&self) -> INT193_A { match self.bits { false => INT193_A::LEVEL, true => INT193_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT193_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT193_A::EDGE } } #[doc = "Field `INT193` writer - Interrupt 193"] -pub type INT193_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT193_A, O>; -impl<'a, const O: u8> INT193_W<'a, O> { +pub type INT193_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT193_A>; +impl<'a, REG, const O: u8> INT193_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT193_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT193_A::EDGE) } } @@ -153,34 +127,37 @@ impl From for bool { impl INT194_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT194_A { + pub const fn variant(&self) -> INT194_A { match self.bits { false => INT194_A::LEVEL, true => INT194_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT194_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT194_A::EDGE } } #[doc = "Field `INT194` writer - Interrupt 194"] -pub type INT194_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT194_A, O>; -impl<'a, const O: u8> INT194_W<'a, O> { +pub type INT194_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT194_A>; +impl<'a, REG, const O: u8> INT194_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT194_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT194_A::EDGE) } } @@ -203,34 +180,37 @@ impl From for bool { impl INT195_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT195_A { + pub const fn variant(&self) -> INT195_A { match self.bits { false => INT195_A::LEVEL, true => INT195_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT195_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT195_A::EDGE } } #[doc = "Field `INT195` writer - Interrupt 195"] -pub type INT195_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT195_A, O>; -impl<'a, const O: u8> INT195_W<'a, O> { +pub type INT195_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT195_A>; +impl<'a, REG, const O: u8> INT195_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT195_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT195_A::EDGE) } } @@ -253,34 +233,37 @@ impl From for bool { impl INT196_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT196_A { + pub const fn variant(&self) -> INT196_A { match self.bits { false => INT196_A::LEVEL, true => INT196_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT196_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT196_A::EDGE } } #[doc = "Field `INT196` writer - Interrupt 196"] -pub type INT196_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT196_A, O>; -impl<'a, const O: u8> INT196_W<'a, O> { +pub type INT196_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT196_A>; +impl<'a, REG, const O: u8> INT196_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT196_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT196_A::EDGE) } } @@ -303,34 +286,37 @@ impl From for bool { impl INT197_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT197_A { + pub const fn variant(&self) -> INT197_A { match self.bits { false => INT197_A::LEVEL, true => INT197_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT197_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT197_A::EDGE } } #[doc = "Field `INT197` writer - Interrupt 197"] -pub type INT197_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT197_A, O>; -impl<'a, const O: u8> INT197_W<'a, O> { +pub type INT197_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT197_A>; +impl<'a, REG, const O: u8> INT197_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT197_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT197_A::EDGE) } } @@ -353,34 +339,37 @@ impl From for bool { impl INT198_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT198_A { + pub const fn variant(&self) -> INT198_A { match self.bits { false => INT198_A::LEVEL, true => INT198_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT198_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT198_A::EDGE } } #[doc = "Field `INT198` writer - Interrupt 198"] -pub type INT198_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT198_A, O>; -impl<'a, const O: u8> INT198_W<'a, O> { +pub type INT198_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT198_A>; +impl<'a, REG, const O: u8> INT198_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT198_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT198_A::EDGE) } } @@ -403,34 +392,37 @@ impl From for bool { impl INT199_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT199_A { + pub const fn variant(&self) -> INT199_A { match self.bits { false => INT199_A::LEVEL, true => INT199_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT199_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT199_A::EDGE } } #[doc = "Field `INT199` writer - Interrupt 199"] -pub type INT199_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT199_A, O>; -impl<'a, const O: u8> INT199_W<'a, O> { +pub type INT199_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT199_A>; +impl<'a, REG, const O: u8> INT199_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT199_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT199_A::EDGE) } } @@ -453,34 +445,37 @@ impl From for bool { impl INT200_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT200_A { + pub const fn variant(&self) -> INT200_A { match self.bits { false => INT200_A::LEVEL, true => INT200_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT200_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT200_A::EDGE } } #[doc = "Field `INT200` writer - Interrupt 200"] -pub type INT200_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT200_A, O>; -impl<'a, const O: u8> INT200_W<'a, O> { +pub type INT200_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT200_A>; +impl<'a, REG, const O: u8> INT200_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT200_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT200_A::EDGE) } } @@ -503,34 +498,37 @@ impl From for bool { impl INT201_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT201_A { + pub const fn variant(&self) -> INT201_A { match self.bits { false => INT201_A::LEVEL, true => INT201_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT201_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT201_A::EDGE } } #[doc = "Field `INT201` writer - Interrupt 201"] -pub type INT201_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT201_A, O>; -impl<'a, const O: u8> INT201_W<'a, O> { +pub type INT201_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT201_A>; +impl<'a, REG, const O: u8> INT201_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT201_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT201_A::EDGE) } } @@ -553,34 +551,37 @@ impl From for bool { impl INT202_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT202_A { + pub const fn variant(&self) -> INT202_A { match self.bits { false => INT202_A::LEVEL, true => INT202_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT202_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT202_A::EDGE } } #[doc = "Field `INT202` writer - Interrupt 202"] -pub type INT202_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT202_A, O>; -impl<'a, const O: u8> INT202_W<'a, O> { +pub type INT202_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT202_A>; +impl<'a, REG, const O: u8> INT202_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT202_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT202_A::EDGE) } } @@ -603,34 +604,37 @@ impl From for bool { impl INT203_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT203_A { + pub const fn variant(&self) -> INT203_A { match self.bits { false => INT203_A::LEVEL, true => INT203_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT203_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT203_A::EDGE } } #[doc = "Field `INT203` writer - Interrupt 203"] -pub type INT203_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT203_A, O>; -impl<'a, const O: u8> INT203_W<'a, O> { +pub type INT203_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT203_A>; +impl<'a, REG, const O: u8> INT203_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT203_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT203_A::EDGE) } } @@ -653,34 +657,37 @@ impl From for bool { impl INT204_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT204_A { + pub const fn variant(&self) -> INT204_A { match self.bits { false => INT204_A::LEVEL, true => INT204_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT204_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT204_A::EDGE } } #[doc = "Field `INT204` writer - Interrupt 204"] -pub type INT204_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT204_A, O>; -impl<'a, const O: u8> INT204_W<'a, O> { +pub type INT204_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT204_A>; +impl<'a, REG, const O: u8> INT204_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT204_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT204_A::EDGE) } } @@ -703,34 +710,37 @@ impl From for bool { impl INT205_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT205_A { + pub const fn variant(&self) -> INT205_A { match self.bits { false => INT205_A::LEVEL, true => INT205_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT205_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT205_A::EDGE } } #[doc = "Field `INT205` writer - Interrupt 205"] -pub type INT205_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT205_A, O>; -impl<'a, const O: u8> INT205_W<'a, O> { +pub type INT205_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT205_A>; +impl<'a, REG, const O: u8> INT205_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT205_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT205_A::EDGE) } } @@ -753,34 +763,37 @@ impl From for bool { impl INT206_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT206_A { + pub const fn variant(&self) -> INT206_A { match self.bits { false => INT206_A::LEVEL, true => INT206_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT206_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT206_A::EDGE } } #[doc = "Field `INT206` writer - Interrupt 206"] -pub type INT206_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT206_A, O>; -impl<'a, const O: u8> INT206_W<'a, O> { +pub type INT206_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT206_A>; +impl<'a, REG, const O: u8> INT206_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT206_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT206_A::EDGE) } } @@ -803,34 +816,37 @@ impl From for bool { impl INT207_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT207_A { + pub const fn variant(&self) -> INT207_A { match self.bits { false => INT207_A::LEVEL, true => INT207_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT207_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT207_A::EDGE } } #[doc = "Field `INT207` writer - Interrupt 207"] -pub type INT207_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR48_SPEC, INT207_A, O>; -impl<'a, const O: u8> INT207_W<'a, O> { +pub type INT207_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT207_A>; +impl<'a, REG, const O: u8> INT207_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT207_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT207_A::EDGE) } } @@ -916,122 +932,150 @@ impl R { INT207_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR48") + .field("int192", &format_args!("{}", self.int192().bit())) + .field("int193", &format_args!("{}", self.int193().bit())) + .field("int194", &format_args!("{}", self.int194().bit())) + .field("int195", &format_args!("{}", self.int195().bit())) + .field("int196", &format_args!("{}", self.int196().bit())) + .field("int197", &format_args!("{}", self.int197().bit())) + .field("int198", &format_args!("{}", self.int198().bit())) + .field("int199", &format_args!("{}", self.int199().bit())) + .field("int200", &format_args!("{}", self.int200().bit())) + .field("int201", &format_args!("{}", self.int201().bit())) + .field("int202", &format_args!("{}", self.int202().bit())) + .field("int203", &format_args!("{}", self.int203().bit())) + .field("int204", &format_args!("{}", self.int204().bit())) + .field("int205", &format_args!("{}", self.int205().bit())) + .field("int206", &format_args!("{}", self.int206().bit())) + .field("int207", &format_args!("{}", self.int207().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Interrupt 192"] #[inline(always)] #[must_use] - pub fn int192(&mut self) -> INT192_W<1> { + pub fn int192(&mut self) -> INT192_W { INT192_W::new(self) } #[doc = "Bit 3 - Interrupt 193"] #[inline(always)] #[must_use] - pub fn int193(&mut self) -> INT193_W<3> { + pub fn int193(&mut self) -> INT193_W { INT193_W::new(self) } #[doc = "Bit 5 - Interrupt 194"] #[inline(always)] #[must_use] - pub fn int194(&mut self) -> INT194_W<5> { + pub fn int194(&mut self) -> INT194_W { INT194_W::new(self) } #[doc = "Bit 7 - Interrupt 195"] #[inline(always)] #[must_use] - pub fn int195(&mut self) -> INT195_W<7> { + pub fn int195(&mut self) -> INT195_W { INT195_W::new(self) } #[doc = "Bit 9 - Interrupt 196"] #[inline(always)] #[must_use] - pub fn int196(&mut self) -> INT196_W<9> { + pub fn int196(&mut self) -> INT196_W { INT196_W::new(self) } #[doc = "Bit 11 - Interrupt 197"] #[inline(always)] #[must_use] - pub fn int197(&mut self) -> INT197_W<11> { + pub fn int197(&mut self) -> INT197_W { INT197_W::new(self) } #[doc = "Bit 13 - Interrupt 198"] #[inline(always)] #[must_use] - pub fn int198(&mut self) -> INT198_W<13> { + pub fn int198(&mut self) -> INT198_W { INT198_W::new(self) } #[doc = "Bit 15 - Interrupt 199"] #[inline(always)] #[must_use] - pub fn int199(&mut self) -> INT199_W<15> { + pub fn int199(&mut self) -> INT199_W { INT199_W::new(self) } #[doc = "Bit 17 - Interrupt 200"] #[inline(always)] #[must_use] - pub fn int200(&mut self) -> INT200_W<17> { + pub fn int200(&mut self) -> INT200_W { INT200_W::new(self) } #[doc = "Bit 19 - Interrupt 201"] #[inline(always)] #[must_use] - pub fn int201(&mut self) -> INT201_W<19> { + pub fn int201(&mut self) -> INT201_W { INT201_W::new(self) } #[doc = "Bit 21 - Interrupt 202"] #[inline(always)] #[must_use] - pub fn int202(&mut self) -> INT202_W<21> { + pub fn int202(&mut self) -> INT202_W { INT202_W::new(self) } #[doc = "Bit 23 - Interrupt 203"] #[inline(always)] #[must_use] - pub fn int203(&mut self) -> INT203_W<23> { + pub fn int203(&mut self) -> INT203_W { INT203_W::new(self) } #[doc = "Bit 25 - Interrupt 204"] #[inline(always)] #[must_use] - pub fn int204(&mut self) -> INT204_W<25> { + pub fn int204(&mut self) -> INT204_W { INT204_W::new(self) } #[doc = "Bit 27 - Interrupt 205"] #[inline(always)] #[must_use] - pub fn int205(&mut self) -> INT205_W<27> { + pub fn int205(&mut self) -> INT205_W { INT205_W::new(self) } #[doc = "Bit 29 - Interrupt 206"] #[inline(always)] #[must_use] - pub fn int206(&mut self) -> INT206_W<29> { + pub fn int206(&mut self) -> INT206_W { INT206_W::new(self) } #[doc = "Bit 31 - Interrupt 207"] #[inline(always)] #[must_use] - pub fn int207(&mut self) -> INT207_W<31> { + pub fn int207(&mut self) -> INT207_W { INT207_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 192 - 207\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr48](index.html) module"] +#[doc = "Interrupt Configuration 192 - 207\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr48::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr48::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR48_SPEC; impl crate::RegisterSpec for GICD_ICFGR48_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr48::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR48_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr48::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr48::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR48_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr48::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR48_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr52.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr52.rs index cb7b1b0..0ad5a00 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr52.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr52.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR52` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR52` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT208` reader - Interrupt 208"] pub type INT208_R = crate::BitReader; #[doc = "Interrupt 208\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl INT208_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT208_A { + pub const fn variant(&self) -> INT208_A { match self.bits { false => INT208_A::LEVEL, true => INT208_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT208_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT208_A::EDGE } } #[doc = "Field `INT208` writer - Interrupt 208"] -pub type INT208_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT208_A, O>; -impl<'a, const O: u8> INT208_W<'a, O> { +pub type INT208_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT208_A>; +impl<'a, REG, const O: u8> INT208_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT208_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT208_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl INT209_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT209_A { + pub const fn variant(&self) -> INT209_A { match self.bits { false => INT209_A::LEVEL, true => INT209_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT209_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT209_A::EDGE } } #[doc = "Field `INT209` writer - Interrupt 209"] -pub type INT209_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT209_A, O>; -impl<'a, const O: u8> INT209_W<'a, O> { +pub type INT209_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT209_A>; +impl<'a, REG, const O: u8> INT209_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT209_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT209_A::EDGE) } } @@ -153,34 +127,37 @@ impl From for bool { impl INT210_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT210_A { + pub const fn variant(&self) -> INT210_A { match self.bits { false => INT210_A::LEVEL, true => INT210_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT210_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT210_A::EDGE } } #[doc = "Field `INT210` writer - Interrupt 210"] -pub type INT210_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT210_A, O>; -impl<'a, const O: u8> INT210_W<'a, O> { +pub type INT210_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT210_A>; +impl<'a, REG, const O: u8> INT210_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT210_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT210_A::EDGE) } } @@ -203,34 +180,37 @@ impl From for bool { impl INT211_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT211_A { + pub const fn variant(&self) -> INT211_A { match self.bits { false => INT211_A::LEVEL, true => INT211_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT211_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT211_A::EDGE } } #[doc = "Field `INT211` writer - Interrupt 211"] -pub type INT211_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT211_A, O>; -impl<'a, const O: u8> INT211_W<'a, O> { +pub type INT211_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT211_A>; +impl<'a, REG, const O: u8> INT211_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT211_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT211_A::EDGE) } } @@ -253,34 +233,37 @@ impl From for bool { impl INT212_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT212_A { + pub const fn variant(&self) -> INT212_A { match self.bits { false => INT212_A::LEVEL, true => INT212_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT212_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT212_A::EDGE } } #[doc = "Field `INT212` writer - Interrupt 212"] -pub type INT212_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT212_A, O>; -impl<'a, const O: u8> INT212_W<'a, O> { +pub type INT212_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT212_A>; +impl<'a, REG, const O: u8> INT212_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT212_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT212_A::EDGE) } } @@ -303,34 +286,37 @@ impl From for bool { impl INT213_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT213_A { + pub const fn variant(&self) -> INT213_A { match self.bits { false => INT213_A::LEVEL, true => INT213_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT213_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT213_A::EDGE } } #[doc = "Field `INT213` writer - Interrupt 213"] -pub type INT213_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT213_A, O>; -impl<'a, const O: u8> INT213_W<'a, O> { +pub type INT213_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT213_A>; +impl<'a, REG, const O: u8> INT213_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT213_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT213_A::EDGE) } } @@ -353,34 +339,37 @@ impl From for bool { impl INT214_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT214_A { + pub const fn variant(&self) -> INT214_A { match self.bits { false => INT214_A::LEVEL, true => INT214_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT214_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT214_A::EDGE } } #[doc = "Field `INT214` writer - Interrupt 214"] -pub type INT214_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT214_A, O>; -impl<'a, const O: u8> INT214_W<'a, O> { +pub type INT214_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT214_A>; +impl<'a, REG, const O: u8> INT214_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT214_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT214_A::EDGE) } } @@ -403,34 +392,37 @@ impl From for bool { impl INT215_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT215_A { + pub const fn variant(&self) -> INT215_A { match self.bits { false => INT215_A::LEVEL, true => INT215_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT215_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT215_A::EDGE } } #[doc = "Field `INT215` writer - Interrupt 215"] -pub type INT215_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT215_A, O>; -impl<'a, const O: u8> INT215_W<'a, O> { +pub type INT215_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT215_A>; +impl<'a, REG, const O: u8> INT215_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT215_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT215_A::EDGE) } } @@ -453,34 +445,37 @@ impl From for bool { impl INT216_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT216_A { + pub const fn variant(&self) -> INT216_A { match self.bits { false => INT216_A::LEVEL, true => INT216_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT216_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT216_A::EDGE } } #[doc = "Field `INT216` writer - Interrupt 216"] -pub type INT216_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT216_A, O>; -impl<'a, const O: u8> INT216_W<'a, O> { +pub type INT216_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT216_A>; +impl<'a, REG, const O: u8> INT216_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT216_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT216_A::EDGE) } } @@ -503,34 +498,37 @@ impl From for bool { impl INT217_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT217_A { + pub const fn variant(&self) -> INT217_A { match self.bits { false => INT217_A::LEVEL, true => INT217_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT217_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT217_A::EDGE } } #[doc = "Field `INT217` writer - Interrupt 217"] -pub type INT217_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT217_A, O>; -impl<'a, const O: u8> INT217_W<'a, O> { +pub type INT217_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT217_A>; +impl<'a, REG, const O: u8> INT217_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT217_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT217_A::EDGE) } } @@ -553,34 +551,37 @@ impl From for bool { impl INT218_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT218_A { + pub const fn variant(&self) -> INT218_A { match self.bits { false => INT218_A::LEVEL, true => INT218_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT218_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT218_A::EDGE } } #[doc = "Field `INT218` writer - Interrupt 218"] -pub type INT218_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT218_A, O>; -impl<'a, const O: u8> INT218_W<'a, O> { +pub type INT218_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT218_A>; +impl<'a, REG, const O: u8> INT218_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT218_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT218_A::EDGE) } } @@ -603,34 +604,37 @@ impl From for bool { impl INT219_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT219_A { + pub const fn variant(&self) -> INT219_A { match self.bits { false => INT219_A::LEVEL, true => INT219_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT219_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT219_A::EDGE } } #[doc = "Field `INT219` writer - Interrupt 219"] -pub type INT219_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT219_A, O>; -impl<'a, const O: u8> INT219_W<'a, O> { +pub type INT219_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT219_A>; +impl<'a, REG, const O: u8> INT219_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT219_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT219_A::EDGE) } } @@ -653,34 +657,37 @@ impl From for bool { impl INT220_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT220_A { + pub const fn variant(&self) -> INT220_A { match self.bits { false => INT220_A::LEVEL, true => INT220_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT220_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT220_A::EDGE } } #[doc = "Field `INT220` writer - Interrupt 220"] -pub type INT220_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT220_A, O>; -impl<'a, const O: u8> INT220_W<'a, O> { +pub type INT220_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT220_A>; +impl<'a, REG, const O: u8> INT220_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT220_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT220_A::EDGE) } } @@ -703,34 +710,37 @@ impl From for bool { impl INT221_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT221_A { + pub const fn variant(&self) -> INT221_A { match self.bits { false => INT221_A::LEVEL, true => INT221_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT221_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT221_A::EDGE } } #[doc = "Field `INT221` writer - Interrupt 221"] -pub type INT221_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT221_A, O>; -impl<'a, const O: u8> INT221_W<'a, O> { +pub type INT221_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT221_A>; +impl<'a, REG, const O: u8> INT221_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT221_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT221_A::EDGE) } } @@ -753,34 +763,37 @@ impl From for bool { impl INT222_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT222_A { + pub const fn variant(&self) -> INT222_A { match self.bits { false => INT222_A::LEVEL, true => INT222_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT222_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT222_A::EDGE } } #[doc = "Field `INT222` writer - Interrupt 222"] -pub type INT222_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT222_A, O>; -impl<'a, const O: u8> INT222_W<'a, O> { +pub type INT222_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT222_A>; +impl<'a, REG, const O: u8> INT222_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT222_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT222_A::EDGE) } } @@ -803,34 +816,37 @@ impl From for bool { impl INT223_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT223_A { + pub const fn variant(&self) -> INT223_A { match self.bits { false => INT223_A::LEVEL, true => INT223_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT223_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT223_A::EDGE } } #[doc = "Field `INT223` writer - Interrupt 223"] -pub type INT223_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR52_SPEC, INT223_A, O>; -impl<'a, const O: u8> INT223_W<'a, O> { +pub type INT223_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT223_A>; +impl<'a, REG, const O: u8> INT223_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT223_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT223_A::EDGE) } } @@ -916,122 +932,150 @@ impl R { INT223_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR52") + .field("int208", &format_args!("{}", self.int208().bit())) + .field("int209", &format_args!("{}", self.int209().bit())) + .field("int210", &format_args!("{}", self.int210().bit())) + .field("int211", &format_args!("{}", self.int211().bit())) + .field("int212", &format_args!("{}", self.int212().bit())) + .field("int213", &format_args!("{}", self.int213().bit())) + .field("int214", &format_args!("{}", self.int214().bit())) + .field("int215", &format_args!("{}", self.int215().bit())) + .field("int216", &format_args!("{}", self.int216().bit())) + .field("int217", &format_args!("{}", self.int217().bit())) + .field("int218", &format_args!("{}", self.int218().bit())) + .field("int219", &format_args!("{}", self.int219().bit())) + .field("int220", &format_args!("{}", self.int220().bit())) + .field("int221", &format_args!("{}", self.int221().bit())) + .field("int222", &format_args!("{}", self.int222().bit())) + .field("int223", &format_args!("{}", self.int223().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Interrupt 208"] #[inline(always)] #[must_use] - pub fn int208(&mut self) -> INT208_W<1> { + pub fn int208(&mut self) -> INT208_W { INT208_W::new(self) } #[doc = "Bit 3 - Interrupt 209"] #[inline(always)] #[must_use] - pub fn int209(&mut self) -> INT209_W<3> { + pub fn int209(&mut self) -> INT209_W { INT209_W::new(self) } #[doc = "Bit 5 - Interrupt 210"] #[inline(always)] #[must_use] - pub fn int210(&mut self) -> INT210_W<5> { + pub fn int210(&mut self) -> INT210_W { INT210_W::new(self) } #[doc = "Bit 7 - Interrupt 211"] #[inline(always)] #[must_use] - pub fn int211(&mut self) -> INT211_W<7> { + pub fn int211(&mut self) -> INT211_W { INT211_W::new(self) } #[doc = "Bit 9 - Interrupt 212"] #[inline(always)] #[must_use] - pub fn int212(&mut self) -> INT212_W<9> { + pub fn int212(&mut self) -> INT212_W { INT212_W::new(self) } #[doc = "Bit 11 - Interrupt 213"] #[inline(always)] #[must_use] - pub fn int213(&mut self) -> INT213_W<11> { + pub fn int213(&mut self) -> INT213_W { INT213_W::new(self) } #[doc = "Bit 13 - Interrupt 214"] #[inline(always)] #[must_use] - pub fn int214(&mut self) -> INT214_W<13> { + pub fn int214(&mut self) -> INT214_W { INT214_W::new(self) } #[doc = "Bit 15 - Interrupt 215"] #[inline(always)] #[must_use] - pub fn int215(&mut self) -> INT215_W<15> { + pub fn int215(&mut self) -> INT215_W { INT215_W::new(self) } #[doc = "Bit 17 - Interrupt 216"] #[inline(always)] #[must_use] - pub fn int216(&mut self) -> INT216_W<17> { + pub fn int216(&mut self) -> INT216_W { INT216_W::new(self) } #[doc = "Bit 19 - Interrupt 217"] #[inline(always)] #[must_use] - pub fn int217(&mut self) -> INT217_W<19> { + pub fn int217(&mut self) -> INT217_W { INT217_W::new(self) } #[doc = "Bit 21 - Interrupt 218"] #[inline(always)] #[must_use] - pub fn int218(&mut self) -> INT218_W<21> { + pub fn int218(&mut self) -> INT218_W { INT218_W::new(self) } #[doc = "Bit 23 - Interrupt 219"] #[inline(always)] #[must_use] - pub fn int219(&mut self) -> INT219_W<23> { + pub fn int219(&mut self) -> INT219_W { INT219_W::new(self) } #[doc = "Bit 25 - Interrupt 220"] #[inline(always)] #[must_use] - pub fn int220(&mut self) -> INT220_W<25> { + pub fn int220(&mut self) -> INT220_W { INT220_W::new(self) } #[doc = "Bit 27 - Interrupt 221"] #[inline(always)] #[must_use] - pub fn int221(&mut self) -> INT221_W<27> { + pub fn int221(&mut self) -> INT221_W { INT221_W::new(self) } #[doc = "Bit 29 - Interrupt 222"] #[inline(always)] #[must_use] - pub fn int222(&mut self) -> INT222_W<29> { + pub fn int222(&mut self) -> INT222_W { INT222_W::new(self) } #[doc = "Bit 31 - Interrupt 223"] #[inline(always)] #[must_use] - pub fn int223(&mut self) -> INT223_W<31> { + pub fn int223(&mut self) -> INT223_W { INT223_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 208 - 223\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr52](index.html) module"] +#[doc = "Interrupt Configuration 208 - 223\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr52::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr52::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR52_SPEC; impl crate::RegisterSpec for GICD_ICFGR52_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr52::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR52_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr52::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr52::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR52_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr52::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR52_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr8.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr8.rs index 90c87a0..93fdbf2 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr8.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icfgr/gicd_icfgr8.rs @@ -1,39 +1,7 @@ #[doc = "Register `GICD_ICFGR8` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICFGR8` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT32` reader - Interrupt 32"] pub type INT32_R = crate::BitReader; #[doc = "Interrupt 32\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl INT32_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT32_A { + pub const fn variant(&self) -> INT32_A { match self.bits { false => INT32_A::LEVEL, true => INT32_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT32_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT32_A::EDGE } } #[doc = "Field `INT32` writer - Interrupt 32"] -pub type INT32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT32_A, O>; -impl<'a, const O: u8> INT32_W<'a, O> { +pub type INT32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT32_A>; +impl<'a, REG, const O: u8> INT32_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT32_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT32_A::EDGE) } } @@ -103,34 +74,37 @@ impl From for bool { impl INT33_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT33_A { + pub const fn variant(&self) -> INT33_A { match self.bits { false => INT33_A::LEVEL, true => INT33_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT33_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT33_A::EDGE } } #[doc = "Field `INT33` writer - Interrupt 33"] -pub type INT33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT33_A, O>; -impl<'a, const O: u8> INT33_W<'a, O> { +pub type INT33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT33_A>; +impl<'a, REG, const O: u8> INT33_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT33_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT33_A::EDGE) } } @@ -153,34 +127,37 @@ impl From for bool { impl INT34_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT34_A { + pub const fn variant(&self) -> INT34_A { match self.bits { false => INT34_A::LEVEL, true => INT34_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT34_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT34_A::EDGE } } #[doc = "Field `INT34` writer - Interrupt 34"] -pub type INT34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT34_A, O>; -impl<'a, const O: u8> INT34_W<'a, O> { +pub type INT34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT34_A>; +impl<'a, REG, const O: u8> INT34_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT34_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT34_A::EDGE) } } @@ -203,34 +180,37 @@ impl From for bool { impl INT35_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT35_A { + pub const fn variant(&self) -> INT35_A { match self.bits { false => INT35_A::LEVEL, true => INT35_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT35_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT35_A::EDGE } } #[doc = "Field `INT35` writer - Interrupt 35"] -pub type INT35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT35_A, O>; -impl<'a, const O: u8> INT35_W<'a, O> { +pub type INT35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT35_A>; +impl<'a, REG, const O: u8> INT35_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT35_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT35_A::EDGE) } } @@ -253,34 +233,37 @@ impl From for bool { impl INT36_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT36_A { + pub const fn variant(&self) -> INT36_A { match self.bits { false => INT36_A::LEVEL, true => INT36_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT36_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT36_A::EDGE } } #[doc = "Field `INT36` writer - Interrupt 36"] -pub type INT36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT36_A, O>; -impl<'a, const O: u8> INT36_W<'a, O> { +pub type INT36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT36_A>; +impl<'a, REG, const O: u8> INT36_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT36_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT36_A::EDGE) } } @@ -303,34 +286,37 @@ impl From for bool { impl INT37_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT37_A { + pub const fn variant(&self) -> INT37_A { match self.bits { false => INT37_A::LEVEL, true => INT37_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT37_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT37_A::EDGE } } #[doc = "Field `INT37` writer - Interrupt 37"] -pub type INT37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT37_A, O>; -impl<'a, const O: u8> INT37_W<'a, O> { +pub type INT37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT37_A>; +impl<'a, REG, const O: u8> INT37_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT37_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT37_A::EDGE) } } @@ -353,34 +339,37 @@ impl From for bool { impl INT38_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT38_A { + pub const fn variant(&self) -> INT38_A { match self.bits { false => INT38_A::LEVEL, true => INT38_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT38_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT38_A::EDGE } } #[doc = "Field `INT38` writer - Interrupt 38"] -pub type INT38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT38_A, O>; -impl<'a, const O: u8> INT38_W<'a, O> { +pub type INT38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT38_A>; +impl<'a, REG, const O: u8> INT38_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT38_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT38_A::EDGE) } } @@ -403,34 +392,37 @@ impl From for bool { impl INT39_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT39_A { + pub const fn variant(&self) -> INT39_A { match self.bits { false => INT39_A::LEVEL, true => INT39_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT39_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT39_A::EDGE } } #[doc = "Field `INT39` writer - Interrupt 39"] -pub type INT39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT39_A, O>; -impl<'a, const O: u8> INT39_W<'a, O> { +pub type INT39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT39_A>; +impl<'a, REG, const O: u8> INT39_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT39_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT39_A::EDGE) } } @@ -453,34 +445,37 @@ impl From for bool { impl INT40_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT40_A { + pub const fn variant(&self) -> INT40_A { match self.bits { false => INT40_A::LEVEL, true => INT40_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT40_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT40_A::EDGE } } #[doc = "Field `INT40` writer - Interrupt 40"] -pub type INT40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT40_A, O>; -impl<'a, const O: u8> INT40_W<'a, O> { +pub type INT40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT40_A>; +impl<'a, REG, const O: u8> INT40_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT40_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT40_A::EDGE) } } @@ -503,34 +498,37 @@ impl From for bool { impl INT41_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT41_A { + pub const fn variant(&self) -> INT41_A { match self.bits { false => INT41_A::LEVEL, true => INT41_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT41_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT41_A::EDGE } } #[doc = "Field `INT41` writer - Interrupt 41"] -pub type INT41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT41_A, O>; -impl<'a, const O: u8> INT41_W<'a, O> { +pub type INT41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT41_A>; +impl<'a, REG, const O: u8> INT41_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT41_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT41_A::EDGE) } } @@ -553,34 +551,37 @@ impl From for bool { impl INT42_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT42_A { + pub const fn variant(&self) -> INT42_A { match self.bits { false => INT42_A::LEVEL, true => INT42_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT42_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT42_A::EDGE } } #[doc = "Field `INT42` writer - Interrupt 42"] -pub type INT42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT42_A, O>; -impl<'a, const O: u8> INT42_W<'a, O> { +pub type INT42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT42_A>; +impl<'a, REG, const O: u8> INT42_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT42_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT42_A::EDGE) } } @@ -603,34 +604,37 @@ impl From for bool { impl INT43_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT43_A { + pub const fn variant(&self) -> INT43_A { match self.bits { false => INT43_A::LEVEL, true => INT43_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT43_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT43_A::EDGE } } #[doc = "Field `INT43` writer - Interrupt 43"] -pub type INT43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT43_A, O>; -impl<'a, const O: u8> INT43_W<'a, O> { +pub type INT43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT43_A>; +impl<'a, REG, const O: u8> INT43_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT43_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT43_A::EDGE) } } @@ -653,34 +657,37 @@ impl From for bool { impl INT44_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT44_A { + pub const fn variant(&self) -> INT44_A { match self.bits { false => INT44_A::LEVEL, true => INT44_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT44_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT44_A::EDGE } } #[doc = "Field `INT44` writer - Interrupt 44"] -pub type INT44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT44_A, O>; -impl<'a, const O: u8> INT44_W<'a, O> { +pub type INT44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT44_A>; +impl<'a, REG, const O: u8> INT44_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT44_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT44_A::EDGE) } } @@ -703,34 +710,37 @@ impl From for bool { impl INT45_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT45_A { + pub const fn variant(&self) -> INT45_A { match self.bits { false => INT45_A::LEVEL, true => INT45_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT45_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT45_A::EDGE } } #[doc = "Field `INT45` writer - Interrupt 45"] -pub type INT45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT45_A, O>; -impl<'a, const O: u8> INT45_W<'a, O> { +pub type INT45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT45_A>; +impl<'a, REG, const O: u8> INT45_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT45_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT45_A::EDGE) } } @@ -753,34 +763,37 @@ impl From for bool { impl INT46_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT46_A { + pub const fn variant(&self) -> INT46_A { match self.bits { false => INT46_A::LEVEL, true => INT46_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT46_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT46_A::EDGE } } #[doc = "Field `INT46` writer - Interrupt 46"] -pub type INT46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT46_A, O>; -impl<'a, const O: u8> INT46_W<'a, O> { +pub type INT46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT46_A>; +impl<'a, REG, const O: u8> INT46_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT46_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT46_A::EDGE) } } @@ -803,34 +816,37 @@ impl From for bool { impl INT47_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> INT47_A { + pub const fn variant(&self) -> INT47_A { match self.bits { false => INT47_A::LEVEL, true => INT47_A::EDGE, } } - #[doc = "Checks if the value of the field is `LEVEL`"] + #[doc = "Level sensitive"] #[inline(always)] pub fn is_level(&self) -> bool { *self == INT47_A::LEVEL } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Edge triggered"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == INT47_A::EDGE } } #[doc = "Field `INT47` writer - Interrupt 47"] -pub type INT47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_ICFGR8_SPEC, INT47_A, O>; -impl<'a, const O: u8> INT47_W<'a, O> { +pub type INT47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INT47_A>; +impl<'a, REG, const O: u8> INT47_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Level sensitive"] #[inline(always)] - pub fn level(self) -> &'a mut W { + pub fn level(self) -> &'a mut crate::W { self.variant(INT47_A::LEVEL) } #[doc = "Edge triggered"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(INT47_A::EDGE) } } @@ -916,122 +932,150 @@ impl R { INT47_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICFGR8") + .field("int32", &format_args!("{}", self.int32().bit())) + .field("int33", &format_args!("{}", self.int33().bit())) + .field("int34", &format_args!("{}", self.int34().bit())) + .field("int35", &format_args!("{}", self.int35().bit())) + .field("int36", &format_args!("{}", self.int36().bit())) + .field("int37", &format_args!("{}", self.int37().bit())) + .field("int38", &format_args!("{}", self.int38().bit())) + .field("int39", &format_args!("{}", self.int39().bit())) + .field("int40", &format_args!("{}", self.int40().bit())) + .field("int41", &format_args!("{}", self.int41().bit())) + .field("int42", &format_args!("{}", self.int42().bit())) + .field("int43", &format_args!("{}", self.int43().bit())) + .field("int44", &format_args!("{}", self.int44().bit())) + .field("int45", &format_args!("{}", self.int45().bit())) + .field("int46", &format_args!("{}", self.int46().bit())) + .field("int47", &format_args!("{}", self.int47().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Interrupt 32"] #[inline(always)] #[must_use] - pub fn int32(&mut self) -> INT32_W<1> { + pub fn int32(&mut self) -> INT32_W { INT32_W::new(self) } #[doc = "Bit 3 - Interrupt 33"] #[inline(always)] #[must_use] - pub fn int33(&mut self) -> INT33_W<3> { + pub fn int33(&mut self) -> INT33_W { INT33_W::new(self) } #[doc = "Bit 5 - Interrupt 34"] #[inline(always)] #[must_use] - pub fn int34(&mut self) -> INT34_W<5> { + pub fn int34(&mut self) -> INT34_W { INT34_W::new(self) } #[doc = "Bit 7 - Interrupt 35"] #[inline(always)] #[must_use] - pub fn int35(&mut self) -> INT35_W<7> { + pub fn int35(&mut self) -> INT35_W { INT35_W::new(self) } #[doc = "Bit 9 - Interrupt 36"] #[inline(always)] #[must_use] - pub fn int36(&mut self) -> INT36_W<9> { + pub fn int36(&mut self) -> INT36_W { INT36_W::new(self) } #[doc = "Bit 11 - Interrupt 37"] #[inline(always)] #[must_use] - pub fn int37(&mut self) -> INT37_W<11> { + pub fn int37(&mut self) -> INT37_W { INT37_W::new(self) } #[doc = "Bit 13 - Interrupt 38"] #[inline(always)] #[must_use] - pub fn int38(&mut self) -> INT38_W<13> { + pub fn int38(&mut self) -> INT38_W { INT38_W::new(self) } #[doc = "Bit 15 - Interrupt 39"] #[inline(always)] #[must_use] - pub fn int39(&mut self) -> INT39_W<15> { + pub fn int39(&mut self) -> INT39_W { INT39_W::new(self) } #[doc = "Bit 17 - Interrupt 40"] #[inline(always)] #[must_use] - pub fn int40(&mut self) -> INT40_W<17> { + pub fn int40(&mut self) -> INT40_W { INT40_W::new(self) } #[doc = "Bit 19 - Interrupt 41"] #[inline(always)] #[must_use] - pub fn int41(&mut self) -> INT41_W<19> { + pub fn int41(&mut self) -> INT41_W { INT41_W::new(self) } #[doc = "Bit 21 - Interrupt 42"] #[inline(always)] #[must_use] - pub fn int42(&mut self) -> INT42_W<21> { + pub fn int42(&mut self) -> INT42_W { INT42_W::new(self) } #[doc = "Bit 23 - Interrupt 43"] #[inline(always)] #[must_use] - pub fn int43(&mut self) -> INT43_W<23> { + pub fn int43(&mut self) -> INT43_W { INT43_W::new(self) } #[doc = "Bit 25 - Interrupt 44"] #[inline(always)] #[must_use] - pub fn int44(&mut self) -> INT44_W<25> { + pub fn int44(&mut self) -> INT44_W { INT44_W::new(self) } #[doc = "Bit 27 - Interrupt 45"] #[inline(always)] #[must_use] - pub fn int45(&mut self) -> INT45_W<27> { + pub fn int45(&mut self) -> INT45_W { INT45_W::new(self) } #[doc = "Bit 29 - Interrupt 46"] #[inline(always)] #[must_use] - pub fn int46(&mut self) -> INT46_W<29> { + pub fn int46(&mut self) -> INT46_W { INT46_W::new(self) } #[doc = "Bit 31 - Interrupt 47"] #[inline(always)] #[must_use] - pub fn int47(&mut self) -> INT47_W<31> { + pub fn int47(&mut self) -> INT47_W { INT47_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Configuration 32 - 47\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icfgr8](index.html) module"] +#[doc = "Interrupt Configuration 32 - 47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icfgr8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icfgr8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICFGR8_SPEC; impl crate::RegisterSpec for GICD_ICFGR8_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icfgr8::R](R) reader structure"] -impl crate::Readable for GICD_ICFGR8_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icfgr8::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icfgr8::R`](R) reader structure"] +impl crate::Readable for GICD_ICFGR8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icfgr8::W`](W) writer structure"] impl crate::Writable for GICD_ICFGR8_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr.rs index 8a6748a..ddc5d8b 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct GICD_ICPENDR { #[doc = "0x00 - Interrupt Clear-Pending"] pub gicd_icpendr0: GICD_ICPENDR0, @@ -16,31 +17,38 @@ pub struct GICD_ICPENDR { #[doc = "0x18 - Interrupt Clear-Pending"] pub gicd_icpendr6: GICD_ICPENDR6, } -#[doc = "GICD_ICPENDR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICPENDR0 (rw) register accessor: Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icpendr0`] +module"] pub type GICD_ICPENDR0 = crate::Reg; #[doc = "Interrupt Clear-Pending"] pub mod gicd_icpendr0; -#[doc = "GICD_ICPENDR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICPENDR1 (rw) register accessor: Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icpendr1`] +module"] pub type GICD_ICPENDR1 = crate::Reg; #[doc = "Interrupt Clear-Pending"] pub mod gicd_icpendr1; -#[doc = "GICD_ICPENDR2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICPENDR2 (rw) register accessor: Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icpendr2`] +module"] pub type GICD_ICPENDR2 = crate::Reg; #[doc = "Interrupt Clear-Pending"] pub mod gicd_icpendr2; -#[doc = "GICD_ICPENDR3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICPENDR3 (rw) register accessor: Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icpendr3`] +module"] pub type GICD_ICPENDR3 = crate::Reg; #[doc = "Interrupt Clear-Pending"] pub mod gicd_icpendr3; -#[doc = "GICD_ICPENDR4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICPENDR4 (rw) register accessor: Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icpendr4`] +module"] pub type GICD_ICPENDR4 = crate::Reg; #[doc = "Interrupt Clear-Pending"] pub mod gicd_icpendr4; -#[doc = "GICD_ICPENDR5 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICPENDR5 (rw) register accessor: Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icpendr5`] +module"] pub type GICD_ICPENDR5 = crate::Reg; #[doc = "Interrupt Clear-Pending"] pub mod gicd_icpendr5; -#[doc = "GICD_ICPENDR6 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ICPENDR6 (rw) register accessor: Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_icpendr6`] +module"] pub type GICD_ICPENDR6 = crate::Reg; #[doc = "Interrupt Clear-Pending"] pub mod gicd_icpendr6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr0.rs index 10f341b..a454d13 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr0.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ICPENDR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICPENDR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT0` reader - Interrupt 0"] -pub type INT0_R = crate::BitReader; +pub type INT0_R = crate::BitReader; #[doc = "Field `INT0` writer - Interrupt 0"] -pub type INT0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT1` reader - Interrupt 1"] -pub type INT1_R = crate::BitReader; +pub type INT1_R = crate::BitReader; #[doc = "Field `INT1` writer - Interrupt 1"] -pub type INT1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT2` reader - Interrupt 2"] -pub type INT2_R = crate::BitReader; +pub type INT2_R = crate::BitReader; #[doc = "Field `INT2` writer - Interrupt 2"] -pub type INT2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT3` reader - Interrupt 3"] -pub type INT3_R = crate::BitReader; +pub type INT3_R = crate::BitReader; #[doc = "Field `INT3` writer - Interrupt 3"] -pub type INT3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT4` reader - Interrupt 4"] -pub type INT4_R = crate::BitReader; +pub type INT4_R = crate::BitReader; #[doc = "Field `INT4` writer - Interrupt 4"] -pub type INT4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT5` reader - Interrupt 5"] -pub type INT5_R = crate::BitReader; +pub type INT5_R = crate::BitReader; #[doc = "Field `INT5` writer - Interrupt 5"] -pub type INT5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT6` reader - Interrupt 6"] -pub type INT6_R = crate::BitReader; +pub type INT6_R = crate::BitReader; #[doc = "Field `INT6` writer - Interrupt 6"] -pub type INT6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT7` reader - Interrupt 7"] -pub type INT7_R = crate::BitReader; +pub type INT7_R = crate::BitReader; #[doc = "Field `INT7` writer - Interrupt 7"] -pub type INT7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT8` reader - Interrupt 8"] -pub type INT8_R = crate::BitReader; +pub type INT8_R = crate::BitReader; #[doc = "Field `INT8` writer - Interrupt 8"] -pub type INT8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT9` reader - Interrupt 9"] -pub type INT9_R = crate::BitReader; +pub type INT9_R = crate::BitReader; #[doc = "Field `INT9` writer - Interrupt 9"] -pub type INT9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT9_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT10` reader - Interrupt 10"] -pub type INT10_R = crate::BitReader; +pub type INT10_R = crate::BitReader; #[doc = "Field `INT10` writer - Interrupt 10"] -pub type INT10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT11` reader - Interrupt 11"] -pub type INT11_R = crate::BitReader; +pub type INT11_R = crate::BitReader; #[doc = "Field `INT11` writer - Interrupt 11"] -pub type INT11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT12` reader - Interrupt 12"] -pub type INT12_R = crate::BitReader; +pub type INT12_R = crate::BitReader; #[doc = "Field `INT12` writer - Interrupt 12"] -pub type INT12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT13` reader - Interrupt 13"] -pub type INT13_R = crate::BitReader; +pub type INT13_R = crate::BitReader; #[doc = "Field `INT13` writer - Interrupt 13"] -pub type INT13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT14` reader - Interrupt 14"] -pub type INT14_R = crate::BitReader; +pub type INT14_R = crate::BitReader; #[doc = "Field `INT14` writer - Interrupt 14"] -pub type INT14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT15` reader - Interrupt 15"] -pub type INT15_R = crate::BitReader; +pub type INT15_R = crate::BitReader; #[doc = "Field `INT15` writer - Interrupt 15"] -pub type INT15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT16` reader - Interrupt 16"] -pub type INT16_R = crate::BitReader; +pub type INT16_R = crate::BitReader; #[doc = "Field `INT16` writer - Interrupt 16"] -pub type INT16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT16_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT17` reader - Interrupt 17"] -pub type INT17_R = crate::BitReader; +pub type INT17_R = crate::BitReader; #[doc = "Field `INT17` writer - Interrupt 17"] -pub type INT17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT17_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT18` reader - Interrupt 18"] -pub type INT18_R = crate::BitReader; +pub type INT18_R = crate::BitReader; #[doc = "Field `INT18` writer - Interrupt 18"] -pub type INT18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT18_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT19` reader - Interrupt 19"] -pub type INT19_R = crate::BitReader; +pub type INT19_R = crate::BitReader; #[doc = "Field `INT19` writer - Interrupt 19"] -pub type INT19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT19_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT20` reader - Interrupt 20"] -pub type INT20_R = crate::BitReader; +pub type INT20_R = crate::BitReader; #[doc = "Field `INT20` writer - Interrupt 20"] -pub type INT20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT20_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT21` reader - Interrupt 21"] -pub type INT21_R = crate::BitReader; +pub type INT21_R = crate::BitReader; #[doc = "Field `INT21` writer - Interrupt 21"] -pub type INT21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT21_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT22` reader - Interrupt 22"] -pub type INT22_R = crate::BitReader; +pub type INT22_R = crate::BitReader; #[doc = "Field `INT22` writer - Interrupt 22"] -pub type INT22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT22_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT23` reader - Interrupt 23"] -pub type INT23_R = crate::BitReader; +pub type INT23_R = crate::BitReader; #[doc = "Field `INT23` writer - Interrupt 23"] -pub type INT23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT23_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT24` reader - Interrupt 24"] -pub type INT24_R = crate::BitReader; +pub type INT24_R = crate::BitReader; #[doc = "Field `INT24` writer - Interrupt 24"] -pub type INT24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT24_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT25` reader - Interrupt 25"] -pub type INT25_R = crate::BitReader; +pub type INT25_R = crate::BitReader; #[doc = "Field `INT25` writer - Interrupt 25"] -pub type INT25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT25_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT26` reader - Interrupt 26"] -pub type INT26_R = crate::BitReader; +pub type INT26_R = crate::BitReader; #[doc = "Field `INT26` writer - Interrupt 26"] -pub type INT26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT26_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT27` reader - Interrupt 27"] -pub type INT27_R = crate::BitReader; +pub type INT27_R = crate::BitReader; #[doc = "Field `INT27` writer - Interrupt 27"] -pub type INT27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT27_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT28` reader - Interrupt 28"] -pub type INT28_R = crate::BitReader; +pub type INT28_R = crate::BitReader; #[doc = "Field `INT28` writer - Interrupt 28"] -pub type INT28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT28_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT29` reader - Interrupt 29"] -pub type INT29_R = crate::BitReader; +pub type INT29_R = crate::BitReader; #[doc = "Field `INT29` writer - Interrupt 29"] -pub type INT29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT29_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT30` reader - Interrupt 30"] -pub type INT30_R = crate::BitReader; +pub type INT30_R = crate::BitReader; #[doc = "Field `INT30` writer - Interrupt 30"] -pub type INT30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT30_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT31` reader - Interrupt 31"] -pub type INT31_R = crate::BitReader; +pub type INT31_R = crate::BitReader; #[doc = "Field `INT31` writer - Interrupt 31"] -pub type INT31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR0_SPEC, bool, O>; +pub type INT31_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICPENDR0") + .field("int0", &format_args!("{}", self.int0().bit())) + .field("int1", &format_args!("{}", self.int1().bit())) + .field("int2", &format_args!("{}", self.int2().bit())) + .field("int3", &format_args!("{}", self.int3().bit())) + .field("int4", &format_args!("{}", self.int4().bit())) + .field("int5", &format_args!("{}", self.int5().bit())) + .field("int6", &format_args!("{}", self.int6().bit())) + .field("int7", &format_args!("{}", self.int7().bit())) + .field("int8", &format_args!("{}", self.int8().bit())) + .field("int9", &format_args!("{}", self.int9().bit())) + .field("int10", &format_args!("{}", self.int10().bit())) + .field("int11", &format_args!("{}", self.int11().bit())) + .field("int12", &format_args!("{}", self.int12().bit())) + .field("int13", &format_args!("{}", self.int13().bit())) + .field("int14", &format_args!("{}", self.int14().bit())) + .field("int15", &format_args!("{}", self.int15().bit())) + .field("int16", &format_args!("{}", self.int16().bit())) + .field("int17", &format_args!("{}", self.int17().bit())) + .field("int18", &format_args!("{}", self.int18().bit())) + .field("int19", &format_args!("{}", self.int19().bit())) + .field("int20", &format_args!("{}", self.int20().bit())) + .field("int21", &format_args!("{}", self.int21().bit())) + .field("int22", &format_args!("{}", self.int22().bit())) + .field("int23", &format_args!("{}", self.int23().bit())) + .field("int24", &format_args!("{}", self.int24().bit())) + .field("int25", &format_args!("{}", self.int25().bit())) + .field("int26", &format_args!("{}", self.int26().bit())) + .field("int27", &format_args!("{}", self.int27().bit())) + .field("int28", &format_args!("{}", self.int28().bit())) + .field("int29", &format_args!("{}", self.int29().bit())) + .field("int30", &format_args!("{}", self.int30().bit())) + .field("int31", &format_args!("{}", self.int31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] #[must_use] - pub fn int0(&mut self) -> INT0_W<0> { + pub fn int0(&mut self) -> INT0_W { INT0_W::new(self) } #[doc = "Bit 1 - Interrupt 1"] #[inline(always)] #[must_use] - pub fn int1(&mut self) -> INT1_W<1> { + pub fn int1(&mut self) -> INT1_W { INT1_W::new(self) } #[doc = "Bit 2 - Interrupt 2"] #[inline(always)] #[must_use] - pub fn int2(&mut self) -> INT2_W<2> { + pub fn int2(&mut self) -> INT2_W { INT2_W::new(self) } #[doc = "Bit 3 - Interrupt 3"] #[inline(always)] #[must_use] - pub fn int3(&mut self) -> INT3_W<3> { + pub fn int3(&mut self) -> INT3_W { INT3_W::new(self) } #[doc = "Bit 4 - Interrupt 4"] #[inline(always)] #[must_use] - pub fn int4(&mut self) -> INT4_W<4> { + pub fn int4(&mut self) -> INT4_W { INT4_W::new(self) } #[doc = "Bit 5 - Interrupt 5"] #[inline(always)] #[must_use] - pub fn int5(&mut self) -> INT5_W<5> { + pub fn int5(&mut self) -> INT5_W { INT5_W::new(self) } #[doc = "Bit 6 - Interrupt 6"] #[inline(always)] #[must_use] - pub fn int6(&mut self) -> INT6_W<6> { + pub fn int6(&mut self) -> INT6_W { INT6_W::new(self) } #[doc = "Bit 7 - Interrupt 7"] #[inline(always)] #[must_use] - pub fn int7(&mut self) -> INT7_W<7> { + pub fn int7(&mut self) -> INT7_W { INT7_W::new(self) } #[doc = "Bit 8 - Interrupt 8"] #[inline(always)] #[must_use] - pub fn int8(&mut self) -> INT8_W<8> { + pub fn int8(&mut self) -> INT8_W { INT8_W::new(self) } #[doc = "Bit 9 - Interrupt 9"] #[inline(always)] #[must_use] - pub fn int9(&mut self) -> INT9_W<9> { + pub fn int9(&mut self) -> INT9_W { INT9_W::new(self) } #[doc = "Bit 10 - Interrupt 10"] #[inline(always)] #[must_use] - pub fn int10(&mut self) -> INT10_W<10> { + pub fn int10(&mut self) -> INT10_W { INT10_W::new(self) } #[doc = "Bit 11 - Interrupt 11"] #[inline(always)] #[must_use] - pub fn int11(&mut self) -> INT11_W<11> { + pub fn int11(&mut self) -> INT11_W { INT11_W::new(self) } #[doc = "Bit 12 - Interrupt 12"] #[inline(always)] #[must_use] - pub fn int12(&mut self) -> INT12_W<12> { + pub fn int12(&mut self) -> INT12_W { INT12_W::new(self) } #[doc = "Bit 13 - Interrupt 13"] #[inline(always)] #[must_use] - pub fn int13(&mut self) -> INT13_W<13> { + pub fn int13(&mut self) -> INT13_W { INT13_W::new(self) } #[doc = "Bit 14 - Interrupt 14"] #[inline(always)] #[must_use] - pub fn int14(&mut self) -> INT14_W<14> { + pub fn int14(&mut self) -> INT14_W { INT14_W::new(self) } #[doc = "Bit 15 - Interrupt 15"] #[inline(always)] #[must_use] - pub fn int15(&mut self) -> INT15_W<15> { + pub fn int15(&mut self) -> INT15_W { INT15_W::new(self) } #[doc = "Bit 16 - Interrupt 16"] #[inline(always)] #[must_use] - pub fn int16(&mut self) -> INT16_W<16> { + pub fn int16(&mut self) -> INT16_W { INT16_W::new(self) } #[doc = "Bit 17 - Interrupt 17"] #[inline(always)] #[must_use] - pub fn int17(&mut self) -> INT17_W<17> { + pub fn int17(&mut self) -> INT17_W { INT17_W::new(self) } #[doc = "Bit 18 - Interrupt 18"] #[inline(always)] #[must_use] - pub fn int18(&mut self) -> INT18_W<18> { + pub fn int18(&mut self) -> INT18_W { INT18_W::new(self) } #[doc = "Bit 19 - Interrupt 19"] #[inline(always)] #[must_use] - pub fn int19(&mut self) -> INT19_W<19> { + pub fn int19(&mut self) -> INT19_W { INT19_W::new(self) } #[doc = "Bit 20 - Interrupt 20"] #[inline(always)] #[must_use] - pub fn int20(&mut self) -> INT20_W<20> { + pub fn int20(&mut self) -> INT20_W { INT20_W::new(self) } #[doc = "Bit 21 - Interrupt 21"] #[inline(always)] #[must_use] - pub fn int21(&mut self) -> INT21_W<21> { + pub fn int21(&mut self) -> INT21_W { INT21_W::new(self) } #[doc = "Bit 22 - Interrupt 22"] #[inline(always)] #[must_use] - pub fn int22(&mut self) -> INT22_W<22> { + pub fn int22(&mut self) -> INT22_W { INT22_W::new(self) } #[doc = "Bit 23 - Interrupt 23"] #[inline(always)] #[must_use] - pub fn int23(&mut self) -> INT23_W<23> { + pub fn int23(&mut self) -> INT23_W { INT23_W::new(self) } #[doc = "Bit 24 - Interrupt 24"] #[inline(always)] #[must_use] - pub fn int24(&mut self) -> INT24_W<24> { + pub fn int24(&mut self) -> INT24_W { INT24_W::new(self) } #[doc = "Bit 25 - Interrupt 25"] #[inline(always)] #[must_use] - pub fn int25(&mut self) -> INT25_W<25> { + pub fn int25(&mut self) -> INT25_W { INT25_W::new(self) } #[doc = "Bit 26 - Interrupt 26"] #[inline(always)] #[must_use] - pub fn int26(&mut self) -> INT26_W<26> { + pub fn int26(&mut self) -> INT26_W { INT26_W::new(self) } #[doc = "Bit 27 - Interrupt 27"] #[inline(always)] #[must_use] - pub fn int27(&mut self) -> INT27_W<27> { + pub fn int27(&mut self) -> INT27_W { INT27_W::new(self) } #[doc = "Bit 28 - Interrupt 28"] #[inline(always)] #[must_use] - pub fn int28(&mut self) -> INT28_W<28> { + pub fn int28(&mut self) -> INT28_W { INT28_W::new(self) } #[doc = "Bit 29 - Interrupt 29"] #[inline(always)] #[must_use] - pub fn int29(&mut self) -> INT29_W<29> { + pub fn int29(&mut self) -> INT29_W { INT29_W::new(self) } #[doc = "Bit 30 - Interrupt 30"] #[inline(always)] #[must_use] - pub fn int30(&mut self) -> INT30_W<30> { + pub fn int30(&mut self) -> INT30_W { INT30_W::new(self) } #[doc = "Bit 31 - Interrupt 31"] #[inline(always)] #[must_use] - pub fn int31(&mut self) -> INT31_W<31> { + pub fn int31(&mut self) -> INT31_W { INT31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr0](index.html) module"] +#[doc = "Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICPENDR0_SPEC; impl crate::RegisterSpec for GICD_ICPENDR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icpendr0::R](R) reader structure"] -impl crate::Readable for GICD_ICPENDR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icpendr0::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icpendr0::R`](R) reader structure"] +impl crate::Readable for GICD_ICPENDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icpendr0::W`](W) writer structure"] impl crate::Writable for GICD_ICPENDR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr1.rs index 1ed2815..c63ac66 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr1.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr1.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ICPENDR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICPENDR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT32` reader - Interrupt 32"] -pub type INT32_R = crate::BitReader; +pub type INT32_R = crate::BitReader; #[doc = "Field `INT32` writer - Interrupt 32"] -pub type INT32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT32_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT33` reader - Interrupt 33"] -pub type INT33_R = crate::BitReader; +pub type INT33_R = crate::BitReader; #[doc = "Field `INT33` writer - Interrupt 33"] -pub type INT33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT33_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT34` reader - Interrupt 34"] -pub type INT34_R = crate::BitReader; +pub type INT34_R = crate::BitReader; #[doc = "Field `INT34` writer - Interrupt 34"] -pub type INT34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT34_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT35` reader - Interrupt 35"] -pub type INT35_R = crate::BitReader; +pub type INT35_R = crate::BitReader; #[doc = "Field `INT35` writer - Interrupt 35"] -pub type INT35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT35_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT36` reader - Interrupt 36"] -pub type INT36_R = crate::BitReader; +pub type INT36_R = crate::BitReader; #[doc = "Field `INT36` writer - Interrupt 36"] -pub type INT36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT36_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT37` reader - Interrupt 37"] -pub type INT37_R = crate::BitReader; +pub type INT37_R = crate::BitReader; #[doc = "Field `INT37` writer - Interrupt 37"] -pub type INT37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT37_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT38` reader - Interrupt 38"] -pub type INT38_R = crate::BitReader; +pub type INT38_R = crate::BitReader; #[doc = "Field `INT38` writer - Interrupt 38"] -pub type INT38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT38_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT39` reader - Interrupt 39"] -pub type INT39_R = crate::BitReader; +pub type INT39_R = crate::BitReader; #[doc = "Field `INT39` writer - Interrupt 39"] -pub type INT39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT39_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT40` reader - Interrupt 40"] -pub type INT40_R = crate::BitReader; +pub type INT40_R = crate::BitReader; #[doc = "Field `INT40` writer - Interrupt 40"] -pub type INT40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT40_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT41` reader - Interrupt 41"] -pub type INT41_R = crate::BitReader; +pub type INT41_R = crate::BitReader; #[doc = "Field `INT41` writer - Interrupt 41"] -pub type INT41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT41_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT42` reader - Interrupt 42"] -pub type INT42_R = crate::BitReader; +pub type INT42_R = crate::BitReader; #[doc = "Field `INT42` writer - Interrupt 42"] -pub type INT42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT42_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT43` reader - Interrupt 43"] -pub type INT43_R = crate::BitReader; +pub type INT43_R = crate::BitReader; #[doc = "Field `INT43` writer - Interrupt 43"] -pub type INT43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT43_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT44` reader - Interrupt 44"] -pub type INT44_R = crate::BitReader; +pub type INT44_R = crate::BitReader; #[doc = "Field `INT44` writer - Interrupt 44"] -pub type INT44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT44_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT45` reader - Interrupt 45"] -pub type INT45_R = crate::BitReader; +pub type INT45_R = crate::BitReader; #[doc = "Field `INT45` writer - Interrupt 45"] -pub type INT45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT45_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT46` reader - Interrupt 46"] -pub type INT46_R = crate::BitReader; +pub type INT46_R = crate::BitReader; #[doc = "Field `INT46` writer - Interrupt 46"] -pub type INT46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT46_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT47` reader - Interrupt 47"] -pub type INT47_R = crate::BitReader; +pub type INT47_R = crate::BitReader; #[doc = "Field `INT47` writer - Interrupt 47"] -pub type INT47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT47_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT48` reader - Interrupt 48"] -pub type INT48_R = crate::BitReader; +pub type INT48_R = crate::BitReader; #[doc = "Field `INT48` writer - Interrupt 48"] -pub type INT48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT48_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT49` reader - Interrupt 49"] -pub type INT49_R = crate::BitReader; +pub type INT49_R = crate::BitReader; #[doc = "Field `INT49` writer - Interrupt 49"] -pub type INT49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT49_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT50` reader - Interrupt 50"] -pub type INT50_R = crate::BitReader; +pub type INT50_R = crate::BitReader; #[doc = "Field `INT50` writer - Interrupt 50"] -pub type INT50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT50_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT51` reader - Interrupt 51"] -pub type INT51_R = crate::BitReader; +pub type INT51_R = crate::BitReader; #[doc = "Field `INT51` writer - Interrupt 51"] -pub type INT51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT51_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT52` reader - Interrupt 52"] -pub type INT52_R = crate::BitReader; +pub type INT52_R = crate::BitReader; #[doc = "Field `INT52` writer - Interrupt 52"] -pub type INT52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT52_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT53` reader - Interrupt 53"] -pub type INT53_R = crate::BitReader; +pub type INT53_R = crate::BitReader; #[doc = "Field `INT53` writer - Interrupt 53"] -pub type INT53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT53_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT54` reader - Interrupt 54"] -pub type INT54_R = crate::BitReader; +pub type INT54_R = crate::BitReader; #[doc = "Field `INT54` writer - Interrupt 54"] -pub type INT54_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT54_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT55` reader - Interrupt 55"] -pub type INT55_R = crate::BitReader; +pub type INT55_R = crate::BitReader; #[doc = "Field `INT55` writer - Interrupt 55"] -pub type INT55_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT55_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT56` reader - Interrupt 56"] -pub type INT56_R = crate::BitReader; +pub type INT56_R = crate::BitReader; #[doc = "Field `INT56` writer - Interrupt 56"] -pub type INT56_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT56_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT57` reader - Interrupt 57"] -pub type INT57_R = crate::BitReader; +pub type INT57_R = crate::BitReader; #[doc = "Field `INT57` writer - Interrupt 57"] -pub type INT57_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT57_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT58` reader - Interrupt 58"] -pub type INT58_R = crate::BitReader; +pub type INT58_R = crate::BitReader; #[doc = "Field `INT58` writer - Interrupt 58"] -pub type INT58_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT58_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT59` reader - Interrupt 59"] -pub type INT59_R = crate::BitReader; +pub type INT59_R = crate::BitReader; #[doc = "Field `INT59` writer - Interrupt 59"] -pub type INT59_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT59_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT60` reader - Interrupt 60"] -pub type INT60_R = crate::BitReader; +pub type INT60_R = crate::BitReader; #[doc = "Field `INT60` writer - Interrupt 60"] -pub type INT60_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT60_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT61` reader - Interrupt 61"] -pub type INT61_R = crate::BitReader; +pub type INT61_R = crate::BitReader; #[doc = "Field `INT61` writer - Interrupt 61"] -pub type INT61_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT61_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT62` reader - Interrupt 62"] -pub type INT62_R = crate::BitReader; +pub type INT62_R = crate::BitReader; #[doc = "Field `INT62` writer - Interrupt 62"] -pub type INT62_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT62_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT63` reader - Interrupt 63"] -pub type INT63_R = crate::BitReader; +pub type INT63_R = crate::BitReader; #[doc = "Field `INT63` writer - Interrupt 63"] -pub type INT63_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR1_SPEC, bool, O>; +pub type INT63_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT63_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICPENDR1") + .field("int32", &format_args!("{}", self.int32().bit())) + .field("int33", &format_args!("{}", self.int33().bit())) + .field("int34", &format_args!("{}", self.int34().bit())) + .field("int35", &format_args!("{}", self.int35().bit())) + .field("int36", &format_args!("{}", self.int36().bit())) + .field("int37", &format_args!("{}", self.int37().bit())) + .field("int38", &format_args!("{}", self.int38().bit())) + .field("int39", &format_args!("{}", self.int39().bit())) + .field("int40", &format_args!("{}", self.int40().bit())) + .field("int41", &format_args!("{}", self.int41().bit())) + .field("int42", &format_args!("{}", self.int42().bit())) + .field("int43", &format_args!("{}", self.int43().bit())) + .field("int44", &format_args!("{}", self.int44().bit())) + .field("int45", &format_args!("{}", self.int45().bit())) + .field("int46", &format_args!("{}", self.int46().bit())) + .field("int47", &format_args!("{}", self.int47().bit())) + .field("int48", &format_args!("{}", self.int48().bit())) + .field("int49", &format_args!("{}", self.int49().bit())) + .field("int50", &format_args!("{}", self.int50().bit())) + .field("int51", &format_args!("{}", self.int51().bit())) + .field("int52", &format_args!("{}", self.int52().bit())) + .field("int53", &format_args!("{}", self.int53().bit())) + .field("int54", &format_args!("{}", self.int54().bit())) + .field("int55", &format_args!("{}", self.int55().bit())) + .field("int56", &format_args!("{}", self.int56().bit())) + .field("int57", &format_args!("{}", self.int57().bit())) + .field("int58", &format_args!("{}", self.int58().bit())) + .field("int59", &format_args!("{}", self.int59().bit())) + .field("int60", &format_args!("{}", self.int60().bit())) + .field("int61", &format_args!("{}", self.int61().bit())) + .field("int62", &format_args!("{}", self.int62().bit())) + .field("int63", &format_args!("{}", self.int63().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] #[must_use] - pub fn int32(&mut self) -> INT32_W<0> { + pub fn int32(&mut self) -> INT32_W { INT32_W::new(self) } #[doc = "Bit 1 - Interrupt 33"] #[inline(always)] #[must_use] - pub fn int33(&mut self) -> INT33_W<1> { + pub fn int33(&mut self) -> INT33_W { INT33_W::new(self) } #[doc = "Bit 2 - Interrupt 34"] #[inline(always)] #[must_use] - pub fn int34(&mut self) -> INT34_W<2> { + pub fn int34(&mut self) -> INT34_W { INT34_W::new(self) } #[doc = "Bit 3 - Interrupt 35"] #[inline(always)] #[must_use] - pub fn int35(&mut self) -> INT35_W<3> { + pub fn int35(&mut self) -> INT35_W { INT35_W::new(self) } #[doc = "Bit 4 - Interrupt 36"] #[inline(always)] #[must_use] - pub fn int36(&mut self) -> INT36_W<4> { + pub fn int36(&mut self) -> INT36_W { INT36_W::new(self) } #[doc = "Bit 5 - Interrupt 37"] #[inline(always)] #[must_use] - pub fn int37(&mut self) -> INT37_W<5> { + pub fn int37(&mut self) -> INT37_W { INT37_W::new(self) } #[doc = "Bit 6 - Interrupt 38"] #[inline(always)] #[must_use] - pub fn int38(&mut self) -> INT38_W<6> { + pub fn int38(&mut self) -> INT38_W { INT38_W::new(self) } #[doc = "Bit 7 - Interrupt 39"] #[inline(always)] #[must_use] - pub fn int39(&mut self) -> INT39_W<7> { + pub fn int39(&mut self) -> INT39_W { INT39_W::new(self) } #[doc = "Bit 8 - Interrupt 40"] #[inline(always)] #[must_use] - pub fn int40(&mut self) -> INT40_W<8> { + pub fn int40(&mut self) -> INT40_W { INT40_W::new(self) } #[doc = "Bit 9 - Interrupt 41"] #[inline(always)] #[must_use] - pub fn int41(&mut self) -> INT41_W<9> { + pub fn int41(&mut self) -> INT41_W { INT41_W::new(self) } #[doc = "Bit 10 - Interrupt 42"] #[inline(always)] #[must_use] - pub fn int42(&mut self) -> INT42_W<10> { + pub fn int42(&mut self) -> INT42_W { INT42_W::new(self) } #[doc = "Bit 11 - Interrupt 43"] #[inline(always)] #[must_use] - pub fn int43(&mut self) -> INT43_W<11> { + pub fn int43(&mut self) -> INT43_W { INT43_W::new(self) } #[doc = "Bit 12 - Interrupt 44"] #[inline(always)] #[must_use] - pub fn int44(&mut self) -> INT44_W<12> { + pub fn int44(&mut self) -> INT44_W { INT44_W::new(self) } #[doc = "Bit 13 - Interrupt 45"] #[inline(always)] #[must_use] - pub fn int45(&mut self) -> INT45_W<13> { + pub fn int45(&mut self) -> INT45_W { INT45_W::new(self) } #[doc = "Bit 14 - Interrupt 46"] #[inline(always)] #[must_use] - pub fn int46(&mut self) -> INT46_W<14> { + pub fn int46(&mut self) -> INT46_W { INT46_W::new(self) } #[doc = "Bit 15 - Interrupt 47"] #[inline(always)] #[must_use] - pub fn int47(&mut self) -> INT47_W<15> { + pub fn int47(&mut self) -> INT47_W { INT47_W::new(self) } #[doc = "Bit 16 - Interrupt 48"] #[inline(always)] #[must_use] - pub fn int48(&mut self) -> INT48_W<16> { + pub fn int48(&mut self) -> INT48_W { INT48_W::new(self) } #[doc = "Bit 17 - Interrupt 49"] #[inline(always)] #[must_use] - pub fn int49(&mut self) -> INT49_W<17> { + pub fn int49(&mut self) -> INT49_W { INT49_W::new(self) } #[doc = "Bit 18 - Interrupt 50"] #[inline(always)] #[must_use] - pub fn int50(&mut self) -> INT50_W<18> { + pub fn int50(&mut self) -> INT50_W { INT50_W::new(self) } #[doc = "Bit 19 - Interrupt 51"] #[inline(always)] #[must_use] - pub fn int51(&mut self) -> INT51_W<19> { + pub fn int51(&mut self) -> INT51_W { INT51_W::new(self) } #[doc = "Bit 20 - Interrupt 52"] #[inline(always)] #[must_use] - pub fn int52(&mut self) -> INT52_W<20> { + pub fn int52(&mut self) -> INT52_W { INT52_W::new(self) } #[doc = "Bit 21 - Interrupt 53"] #[inline(always)] #[must_use] - pub fn int53(&mut self) -> INT53_W<21> { + pub fn int53(&mut self) -> INT53_W { INT53_W::new(self) } #[doc = "Bit 22 - Interrupt 54"] #[inline(always)] #[must_use] - pub fn int54(&mut self) -> INT54_W<22> { + pub fn int54(&mut self) -> INT54_W { INT54_W::new(self) } #[doc = "Bit 23 - Interrupt 55"] #[inline(always)] #[must_use] - pub fn int55(&mut self) -> INT55_W<23> { + pub fn int55(&mut self) -> INT55_W { INT55_W::new(self) } #[doc = "Bit 24 - Interrupt 56"] #[inline(always)] #[must_use] - pub fn int56(&mut self) -> INT56_W<24> { + pub fn int56(&mut self) -> INT56_W { INT56_W::new(self) } #[doc = "Bit 25 - Interrupt 57"] #[inline(always)] #[must_use] - pub fn int57(&mut self) -> INT57_W<25> { + pub fn int57(&mut self) -> INT57_W { INT57_W::new(self) } #[doc = "Bit 26 - Interrupt 58"] #[inline(always)] #[must_use] - pub fn int58(&mut self) -> INT58_W<26> { + pub fn int58(&mut self) -> INT58_W { INT58_W::new(self) } #[doc = "Bit 27 - Interrupt 59"] #[inline(always)] #[must_use] - pub fn int59(&mut self) -> INT59_W<27> { + pub fn int59(&mut self) -> INT59_W { INT59_W::new(self) } #[doc = "Bit 28 - Interrupt 60"] #[inline(always)] #[must_use] - pub fn int60(&mut self) -> INT60_W<28> { + pub fn int60(&mut self) -> INT60_W { INT60_W::new(self) } #[doc = "Bit 29 - Interrupt 61"] #[inline(always)] #[must_use] - pub fn int61(&mut self) -> INT61_W<29> { + pub fn int61(&mut self) -> INT61_W { INT61_W::new(self) } #[doc = "Bit 30 - Interrupt 62"] #[inline(always)] #[must_use] - pub fn int62(&mut self) -> INT62_W<30> { + pub fn int62(&mut self) -> INT62_W { INT62_W::new(self) } #[doc = "Bit 31 - Interrupt 63"] #[inline(always)] #[must_use] - pub fn int63(&mut self) -> INT63_W<31> { + pub fn int63(&mut self) -> INT63_W { INT63_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr1](index.html) module"] +#[doc = "Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICPENDR1_SPEC; impl crate::RegisterSpec for GICD_ICPENDR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icpendr1::R](R) reader structure"] -impl crate::Readable for GICD_ICPENDR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icpendr1::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icpendr1::R`](R) reader structure"] +impl crate::Readable for GICD_ICPENDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icpendr1::W`](W) writer structure"] impl crate::Writable for GICD_ICPENDR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr2.rs index 3df1ff7..1124427 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr2.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr2.rs @@ -1,169 +1,135 @@ #[doc = "Register `GICD_ICPENDR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICPENDR2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI0` reader - Software interrupt 0"] -pub type SWI0_R = crate::BitReader; +pub type SWI0_R = crate::BitReader; #[doc = "Field `SWI0` writer - Software interrupt 0"] -pub type SWI0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type SWI0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI1` reader - Software interrupt 1"] -pub type SWI1_R = crate::BitReader; +pub type SWI1_R = crate::BitReader; #[doc = "Field `SWI1` writer - Software interrupt 1"] -pub type SWI1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type SWI1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI2` reader - Software interrupt 2"] -pub type SWI2_R = crate::BitReader; +pub type SWI2_R = crate::BitReader; #[doc = "Field `SWI2` writer - Software interrupt 2"] -pub type SWI2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type SWI2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI3` reader - Software interrupt 3"] -pub type SWI3_R = crate::BitReader; +pub type SWI3_R = crate::BitReader; #[doc = "Field `SWI3` writer - Software interrupt 3"] -pub type SWI3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type SWI3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI4` reader - Software interrupt 4"] -pub type SWI4_R = crate::BitReader; +pub type SWI4_R = crate::BitReader; #[doc = "Field `SWI4` writer - Software interrupt 4"] -pub type SWI4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type SWI4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI5` reader - Software interrupt 5"] -pub type SWI5_R = crate::BitReader; +pub type SWI5_R = crate::BitReader; #[doc = "Field `SWI5` writer - Software interrupt 5"] -pub type SWI5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type SWI5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI6` reader - Software interrupt 6"] -pub type SWI6_R = crate::BitReader; +pub type SWI6_R = crate::BitReader; #[doc = "Field `SWI6` writer - Software interrupt 6"] -pub type SWI6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type SWI6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SWI7` reader - Software interrupt 7"] -pub type SWI7_R = crate::BitReader; +pub type SWI7_R = crate::BitReader; #[doc = "Field `SWI7` writer - Software interrupt 7"] -pub type SWI7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type SWI7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT80` reader - Interrupt 80"] -pub type INT80_R = crate::BitReader; +pub type INT80_R = crate::BitReader; #[doc = "Field `INT80` writer - Interrupt 80"] -pub type INT80_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT80_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT81` reader - Interrupt 81"] -pub type INT81_R = crate::BitReader; +pub type INT81_R = crate::BitReader; #[doc = "Field `INT81` writer - Interrupt 81"] -pub type INT81_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT81_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT82` reader - Interrupt 82"] -pub type INT82_R = crate::BitReader; +pub type INT82_R = crate::BitReader; #[doc = "Field `INT82` writer - Interrupt 82"] -pub type INT82_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT82_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT83` reader - Interrupt 83"] -pub type INT83_R = crate::BitReader; +pub type INT83_R = crate::BitReader; #[doc = "Field `INT83` writer - Interrupt 83"] -pub type INT83_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT83_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT84` reader - Interrupt 84"] -pub type INT84_R = crate::BitReader; +pub type INT84_R = crate::BitReader; #[doc = "Field `INT84` writer - Interrupt 84"] -pub type INT84_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT84_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT85` reader - Interrupt 85"] -pub type INT85_R = crate::BitReader; +pub type INT85_R = crate::BitReader; #[doc = "Field `INT85` writer - Interrupt 85"] -pub type INT85_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT85_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT86` reader - Interrupt 86"] -pub type INT86_R = crate::BitReader; +pub type INT86_R = crate::BitReader; #[doc = "Field `INT86` writer - Interrupt 86"] -pub type INT86_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT86_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT87` reader - Interrupt 87"] -pub type INT87_R = crate::BitReader; +pub type INT87_R = crate::BitReader; #[doc = "Field `INT87` writer - Interrupt 87"] -pub type INT87_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT87_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT88` reader - Interrupt 88"] -pub type INT88_R = crate::BitReader; +pub type INT88_R = crate::BitReader; #[doc = "Field `INT88` writer - Interrupt 88"] -pub type INT88_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT88_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT89` reader - Interrupt 89"] -pub type INT89_R = crate::BitReader; +pub type INT89_R = crate::BitReader; #[doc = "Field `INT89` writer - Interrupt 89"] -pub type INT89_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT89_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT90` reader - Interrupt 90"] -pub type INT90_R = crate::BitReader; +pub type INT90_R = crate::BitReader; #[doc = "Field `INT90` writer - Interrupt 90"] -pub type INT90_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT90_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT91` reader - Interrupt 91"] -pub type INT91_R = crate::BitReader; +pub type INT91_R = crate::BitReader; #[doc = "Field `INT91` writer - Interrupt 91"] -pub type INT91_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT91_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT92` reader - Interrupt 92"] -pub type INT92_R = crate::BitReader; +pub type INT92_R = crate::BitReader; #[doc = "Field `INT92` writer - Interrupt 92"] -pub type INT92_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT92_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT93` reader - Interrupt 93"] -pub type INT93_R = crate::BitReader; +pub type INT93_R = crate::BitReader; #[doc = "Field `INT93` writer - Interrupt 93"] -pub type INT93_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT93_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT94` reader - Interrupt 94"] -pub type INT94_R = crate::BitReader; +pub type INT94_R = crate::BitReader; #[doc = "Field `INT94` writer - Interrupt 94"] -pub type INT94_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT94_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT95` reader - Interrupt 95"] -pub type INT95_R = crate::BitReader; +pub type INT95_R = crate::BitReader; #[doc = "Field `INT95` writer - Interrupt 95"] -pub type INT95_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR2_SPEC, bool, O>; +pub type INT95_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -326,218 +292,268 @@ impl R { INT95_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICPENDR2") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .field("swi0", &format_args!("{}", self.swi0().bit())) + .field("swi1", &format_args!("{}", self.swi1().bit())) + .field("swi2", &format_args!("{}", self.swi2().bit())) + .field("swi3", &format_args!("{}", self.swi3().bit())) + .field("swi4", &format_args!("{}", self.swi4().bit())) + .field("swi5", &format_args!("{}", self.swi5().bit())) + .field("swi6", &format_args!("{}", self.swi6().bit())) + .field("swi7", &format_args!("{}", self.swi7().bit())) + .field("int80", &format_args!("{}", self.int80().bit())) + .field("int81", &format_args!("{}", self.int81().bit())) + .field("int82", &format_args!("{}", self.int82().bit())) + .field("int83", &format_args!("{}", self.int83().bit())) + .field("int84", &format_args!("{}", self.int84().bit())) + .field("int85", &format_args!("{}", self.int85().bit())) + .field("int86", &format_args!("{}", self.int86().bit())) + .field("int87", &format_args!("{}", self.int87().bit())) + .field("int88", &format_args!("{}", self.int88().bit())) + .field("int89", &format_args!("{}", self.int89().bit())) + .field("int90", &format_args!("{}", self.int90().bit())) + .field("int91", &format_args!("{}", self.int91().bit())) + .field("int92", &format_args!("{}", self.int92().bit())) + .field("int93", &format_args!("{}", self.int93().bit())) + .field("int94", &format_args!("{}", self.int94().bit())) + .field("int95", &format_args!("{}", self.int95().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } #[doc = "Bit 8 - Software interrupt 0"] #[inline(always)] #[must_use] - pub fn swi0(&mut self) -> SWI0_W<8> { + pub fn swi0(&mut self) -> SWI0_W { SWI0_W::new(self) } #[doc = "Bit 9 - Software interrupt 1"] #[inline(always)] #[must_use] - pub fn swi1(&mut self) -> SWI1_W<9> { + pub fn swi1(&mut self) -> SWI1_W { SWI1_W::new(self) } #[doc = "Bit 10 - Software interrupt 2"] #[inline(always)] #[must_use] - pub fn swi2(&mut self) -> SWI2_W<10> { + pub fn swi2(&mut self) -> SWI2_W { SWI2_W::new(self) } #[doc = "Bit 11 - Software interrupt 3"] #[inline(always)] #[must_use] - pub fn swi3(&mut self) -> SWI3_W<11> { + pub fn swi3(&mut self) -> SWI3_W { SWI3_W::new(self) } #[doc = "Bit 12 - Software interrupt 4"] #[inline(always)] #[must_use] - pub fn swi4(&mut self) -> SWI4_W<12> { + pub fn swi4(&mut self) -> SWI4_W { SWI4_W::new(self) } #[doc = "Bit 13 - Software interrupt 5"] #[inline(always)] #[must_use] - pub fn swi5(&mut self) -> SWI5_W<13> { + pub fn swi5(&mut self) -> SWI5_W { SWI5_W::new(self) } #[doc = "Bit 14 - Software interrupt 6"] #[inline(always)] #[must_use] - pub fn swi6(&mut self) -> SWI6_W<14> { + pub fn swi6(&mut self) -> SWI6_W { SWI6_W::new(self) } #[doc = "Bit 15 - Software interrupt 7"] #[inline(always)] #[must_use] - pub fn swi7(&mut self) -> SWI7_W<15> { + pub fn swi7(&mut self) -> SWI7_W { SWI7_W::new(self) } #[doc = "Bit 16 - Interrupt 80"] #[inline(always)] #[must_use] - pub fn int80(&mut self) -> INT80_W<16> { + pub fn int80(&mut self) -> INT80_W { INT80_W::new(self) } #[doc = "Bit 17 - Interrupt 81"] #[inline(always)] #[must_use] - pub fn int81(&mut self) -> INT81_W<17> { + pub fn int81(&mut self) -> INT81_W { INT81_W::new(self) } #[doc = "Bit 18 - Interrupt 82"] #[inline(always)] #[must_use] - pub fn int82(&mut self) -> INT82_W<18> { + pub fn int82(&mut self) -> INT82_W { INT82_W::new(self) } #[doc = "Bit 19 - Interrupt 83"] #[inline(always)] #[must_use] - pub fn int83(&mut self) -> INT83_W<19> { + pub fn int83(&mut self) -> INT83_W { INT83_W::new(self) } #[doc = "Bit 20 - Interrupt 84"] #[inline(always)] #[must_use] - pub fn int84(&mut self) -> INT84_W<20> { + pub fn int84(&mut self) -> INT84_W { INT84_W::new(self) } #[doc = "Bit 21 - Interrupt 85"] #[inline(always)] #[must_use] - pub fn int85(&mut self) -> INT85_W<21> { + pub fn int85(&mut self) -> INT85_W { INT85_W::new(self) } #[doc = "Bit 22 - Interrupt 86"] #[inline(always)] #[must_use] - pub fn int86(&mut self) -> INT86_W<22> { + pub fn int86(&mut self) -> INT86_W { INT86_W::new(self) } #[doc = "Bit 23 - Interrupt 87"] #[inline(always)] #[must_use] - pub fn int87(&mut self) -> INT87_W<23> { + pub fn int87(&mut self) -> INT87_W { INT87_W::new(self) } #[doc = "Bit 24 - Interrupt 88"] #[inline(always)] #[must_use] - pub fn int88(&mut self) -> INT88_W<24> { + pub fn int88(&mut self) -> INT88_W { INT88_W::new(self) } #[doc = "Bit 25 - Interrupt 89"] #[inline(always)] #[must_use] - pub fn int89(&mut self) -> INT89_W<25> { + pub fn int89(&mut self) -> INT89_W { INT89_W::new(self) } #[doc = "Bit 26 - Interrupt 90"] #[inline(always)] #[must_use] - pub fn int90(&mut self) -> INT90_W<26> { + pub fn int90(&mut self) -> INT90_W { INT90_W::new(self) } #[doc = "Bit 27 - Interrupt 91"] #[inline(always)] #[must_use] - pub fn int91(&mut self) -> INT91_W<27> { + pub fn int91(&mut self) -> INT91_W { INT91_W::new(self) } #[doc = "Bit 28 - Interrupt 92"] #[inline(always)] #[must_use] - pub fn int92(&mut self) -> INT92_W<28> { + pub fn int92(&mut self) -> INT92_W { INT92_W::new(self) } #[doc = "Bit 29 - Interrupt 93"] #[inline(always)] #[must_use] - pub fn int93(&mut self) -> INT93_W<29> { + pub fn int93(&mut self) -> INT93_W { INT93_W::new(self) } #[doc = "Bit 30 - Interrupt 94"] #[inline(always)] #[must_use] - pub fn int94(&mut self) -> INT94_W<30> { + pub fn int94(&mut self) -> INT94_W { INT94_W::new(self) } #[doc = "Bit 31 - Interrupt 95"] #[inline(always)] #[must_use] - pub fn int95(&mut self) -> INT95_W<31> { + pub fn int95(&mut self) -> INT95_W { INT95_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr2](index.html) module"] +#[doc = "Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICPENDR2_SPEC; impl crate::RegisterSpec for GICD_ICPENDR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icpendr2::R](R) reader structure"] -impl crate::Readable for GICD_ICPENDR2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icpendr2::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icpendr2::R`](R) reader structure"] +impl crate::Readable for GICD_ICPENDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icpendr2::W`](W) writer structure"] impl crate::Writable for GICD_ICPENDR2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr3.rs index bcd5e0e..f06a68f 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr3.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr3.rs @@ -1,171 +1,135 @@ #[doc = "Register `GICD_ICPENDR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICPENDR3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR3_SPEC, bool, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -328,218 +292,274 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICPENDR3") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bit 1 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<1> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bit 2 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<2> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bit 3 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<3> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } #[doc = "Bit 4 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<4> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bit 5 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<5> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bit 6 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<6> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bit 7 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<7> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } #[doc = "Bit 8 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<8> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bit 9 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<9> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 10 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<10> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bit 11 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } #[doc = "Bit 12 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bit 13 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bit 14 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bit 15 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } #[doc = "Bit 16 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<16> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bit 17 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<17> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 18 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<18> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 19 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<19> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 20 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<20> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 21 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<21> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 22 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<22> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 23 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } #[doc = "Bit 24 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bit 25 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<25> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bit 26 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<26> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bit 27 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<27> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } #[doc = "Bit 28 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<28> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<29> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bit 30 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<30> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bit 31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<31> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr3](index.html) module"] +#[doc = "Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICPENDR3_SPEC; impl crate::RegisterSpec for GICD_ICPENDR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icpendr3::R](R) reader structure"] -impl crate::Readable for GICD_ICPENDR3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icpendr3::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icpendr3::R`](R) reader structure"] +impl crate::Readable for GICD_ICPENDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icpendr3::W`](W) writer structure"] impl crate::Writable for GICD_ICPENDR3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr4.rs index d787e95..61c4a90 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr4.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr4.rs @@ -1,173 +1,135 @@ #[doc = "Register `GICD_ICPENDR4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICPENDR4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type UART_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, GICD_ICPENDR4_SPEC, bool, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -330,218 +292,280 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICPENDR4") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bit 1 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<1> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bit 2 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<2> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bit 3 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<3> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } #[doc = "Bit 4 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<4> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bit 5 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bit 6 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bit 7 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } #[doc = "Bit 8 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bit 9 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bit 10 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bit 11 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } #[doc = "Bit 12 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<12> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bit 13 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bit 15 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<15> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } #[doc = "Bit 16 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<16> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bit 17 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bit 18 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bit 19 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } #[doc = "Bit 20 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bit 21 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<21> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bit 22 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<22> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bit 23 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } #[doc = "Bit 24 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<24> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bit 25 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<25> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bit 26 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bit 27 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<27> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } #[doc = "Bit 28 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<28> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bit 29 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<29> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bit 30 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<30> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bit 31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr4](index.html) module"] +#[doc = "Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICPENDR4_SPEC; impl crate::RegisterSpec for GICD_ICPENDR4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icpendr4::R](R) reader structure"] -impl crate::Readable for GICD_ICPENDR4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icpendr4::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icpendr4::R`](R) reader structure"] +impl crate::Readable for GICD_ICPENDR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icpendr4::W`](W) writer structure"] impl crate::Writable for GICD_ICPENDR4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr5.rs index 120ad5f..321de1d 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr5.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr5.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ICPENDR5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICPENDR5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT160` reader - Interrupt 160"] -pub type INT160_R = crate::BitReader; +pub type INT160_R = crate::BitReader; #[doc = "Field `INT160` writer - Interrupt 160"] -pub type INT160_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT160_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT161` reader - Interrupt 161"] -pub type INT161_R = crate::BitReader; +pub type INT161_R = crate::BitReader; #[doc = "Field `INT161` writer - Interrupt 161"] -pub type INT161_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT161_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT162` reader - Interrupt 162"] -pub type INT162_R = crate::BitReader; +pub type INT162_R = crate::BitReader; #[doc = "Field `INT162` writer - Interrupt 162"] -pub type INT162_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT162_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT163` reader - Interrupt 163"] -pub type INT163_R = crate::BitReader; +pub type INT163_R = crate::BitReader; #[doc = "Field `INT163` writer - Interrupt 163"] -pub type INT163_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT163_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT164` reader - Interrupt 164"] -pub type INT164_R = crate::BitReader; +pub type INT164_R = crate::BitReader; #[doc = "Field `INT164` writer - Interrupt 164"] -pub type INT164_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT164_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT165` reader - Interrupt 165"] -pub type INT165_R = crate::BitReader; +pub type INT165_R = crate::BitReader; #[doc = "Field `INT165` writer - Interrupt 165"] -pub type INT165_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT165_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT166` reader - Interrupt 166"] -pub type INT166_R = crate::BitReader; +pub type INT166_R = crate::BitReader; #[doc = "Field `INT166` writer - Interrupt 166"] -pub type INT166_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT166_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT167` reader - Interrupt 167"] -pub type INT167_R = crate::BitReader; +pub type INT167_R = crate::BitReader; #[doc = "Field `INT167` writer - Interrupt 167"] -pub type INT167_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT167_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT168` reader - Interrupt 168"] -pub type INT168_R = crate::BitReader; +pub type INT168_R = crate::BitReader; #[doc = "Field `INT168` writer - Interrupt 168"] -pub type INT168_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT168_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT169` reader - Interrupt 169"] -pub type INT169_R = crate::BitReader; +pub type INT169_R = crate::BitReader; #[doc = "Field `INT169` writer - Interrupt 169"] -pub type INT169_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT169_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT170` reader - Interrupt 170"] -pub type INT170_R = crate::BitReader; +pub type INT170_R = crate::BitReader; #[doc = "Field `INT170` writer - Interrupt 170"] -pub type INT170_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT170_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT171` reader - Interrupt 171"] -pub type INT171_R = crate::BitReader; +pub type INT171_R = crate::BitReader; #[doc = "Field `INT171` writer - Interrupt 171"] -pub type INT171_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT171_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT172` reader - Interrupt 172"] -pub type INT172_R = crate::BitReader; +pub type INT172_R = crate::BitReader; #[doc = "Field `INT172` writer - Interrupt 172"] -pub type INT172_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT172_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT173` reader - Interrupt 173"] -pub type INT173_R = crate::BitReader; +pub type INT173_R = crate::BitReader; #[doc = "Field `INT173` writer - Interrupt 173"] -pub type INT173_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT173_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT174` reader - Interrupt 174"] -pub type INT174_R = crate::BitReader; +pub type INT174_R = crate::BitReader; #[doc = "Field `INT174` writer - Interrupt 174"] -pub type INT174_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT174_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT175` reader - Interrupt 175"] -pub type INT175_R = crate::BitReader; +pub type INT175_R = crate::BitReader; #[doc = "Field `INT175` writer - Interrupt 175"] -pub type INT175_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT175_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT176` reader - Interrupt 176"] -pub type INT176_R = crate::BitReader; +pub type INT176_R = crate::BitReader; #[doc = "Field `INT176` writer - Interrupt 176"] -pub type INT176_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT176_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT177` reader - Interrupt 177"] -pub type INT177_R = crate::BitReader; +pub type INT177_R = crate::BitReader; #[doc = "Field `INT177` writer - Interrupt 177"] -pub type INT177_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT177_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT178` reader - Interrupt 178"] -pub type INT178_R = crate::BitReader; +pub type INT178_R = crate::BitReader; #[doc = "Field `INT178` writer - Interrupt 178"] -pub type INT178_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT178_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT179` reader - Interrupt 179"] -pub type INT179_R = crate::BitReader; +pub type INT179_R = crate::BitReader; #[doc = "Field `INT179` writer - Interrupt 179"] -pub type INT179_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT179_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT180` reader - Interrupt 180"] -pub type INT180_R = crate::BitReader; +pub type INT180_R = crate::BitReader; #[doc = "Field `INT180` writer - Interrupt 180"] -pub type INT180_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT180_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT181` reader - Interrupt 181"] -pub type INT181_R = crate::BitReader; +pub type INT181_R = crate::BitReader; #[doc = "Field `INT181` writer - Interrupt 181"] -pub type INT181_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT181_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT182` reader - Interrupt 182"] -pub type INT182_R = crate::BitReader; +pub type INT182_R = crate::BitReader; #[doc = "Field `INT182` writer - Interrupt 182"] -pub type INT182_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT182_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT183` reader - Interrupt 183"] -pub type INT183_R = crate::BitReader; +pub type INT183_R = crate::BitReader; #[doc = "Field `INT183` writer - Interrupt 183"] -pub type INT183_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT183_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT184` reader - Interrupt 184"] -pub type INT184_R = crate::BitReader; +pub type INT184_R = crate::BitReader; #[doc = "Field `INT184` writer - Interrupt 184"] -pub type INT184_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT184_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT185` reader - Interrupt 185"] -pub type INT185_R = crate::BitReader; +pub type INT185_R = crate::BitReader; #[doc = "Field `INT185` writer - Interrupt 185"] -pub type INT185_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT185_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT186` reader - Interrupt 186"] -pub type INT186_R = crate::BitReader; +pub type INT186_R = crate::BitReader; #[doc = "Field `INT186` writer - Interrupt 186"] -pub type INT186_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT186_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT187` reader - Interrupt 187"] -pub type INT187_R = crate::BitReader; +pub type INT187_R = crate::BitReader; #[doc = "Field `INT187` writer - Interrupt 187"] -pub type INT187_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT187_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT188` reader - Interrupt 188"] -pub type INT188_R = crate::BitReader; +pub type INT188_R = crate::BitReader; #[doc = "Field `INT188` writer - Interrupt 188"] -pub type INT188_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT188_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT189` reader - Interrupt 189"] -pub type INT189_R = crate::BitReader; +pub type INT189_R = crate::BitReader; #[doc = "Field `INT189` writer - Interrupt 189"] -pub type INT189_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT189_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT190` reader - Interrupt 190"] -pub type INT190_R = crate::BitReader; +pub type INT190_R = crate::BitReader; #[doc = "Field `INT190` writer - Interrupt 190"] -pub type INT190_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT190_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT191` reader - Interrupt 191"] -pub type INT191_R = crate::BitReader; +pub type INT191_R = crate::BitReader; #[doc = "Field `INT191` writer - Interrupt 191"] -pub type INT191_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR5_SPEC, bool, O>; +pub type INT191_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT191_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICPENDR5") + .field("int160", &format_args!("{}", self.int160().bit())) + .field("int161", &format_args!("{}", self.int161().bit())) + .field("int162", &format_args!("{}", self.int162().bit())) + .field("int163", &format_args!("{}", self.int163().bit())) + .field("int164", &format_args!("{}", self.int164().bit())) + .field("int165", &format_args!("{}", self.int165().bit())) + .field("int166", &format_args!("{}", self.int166().bit())) + .field("int167", &format_args!("{}", self.int167().bit())) + .field("int168", &format_args!("{}", self.int168().bit())) + .field("int169", &format_args!("{}", self.int169().bit())) + .field("int170", &format_args!("{}", self.int170().bit())) + .field("int171", &format_args!("{}", self.int171().bit())) + .field("int172", &format_args!("{}", self.int172().bit())) + .field("int173", &format_args!("{}", self.int173().bit())) + .field("int174", &format_args!("{}", self.int174().bit())) + .field("int175", &format_args!("{}", self.int175().bit())) + .field("int176", &format_args!("{}", self.int176().bit())) + .field("int177", &format_args!("{}", self.int177().bit())) + .field("int178", &format_args!("{}", self.int178().bit())) + .field("int179", &format_args!("{}", self.int179().bit())) + .field("int180", &format_args!("{}", self.int180().bit())) + .field("int181", &format_args!("{}", self.int181().bit())) + .field("int182", &format_args!("{}", self.int182().bit())) + .field("int183", &format_args!("{}", self.int183().bit())) + .field("int184", &format_args!("{}", self.int184().bit())) + .field("int185", &format_args!("{}", self.int185().bit())) + .field("int186", &format_args!("{}", self.int186().bit())) + .field("int187", &format_args!("{}", self.int187().bit())) + .field("int188", &format_args!("{}", self.int188().bit())) + .field("int189", &format_args!("{}", self.int189().bit())) + .field("int190", &format_args!("{}", self.int190().bit())) + .field("int191", &format_args!("{}", self.int191().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] #[must_use] - pub fn int160(&mut self) -> INT160_W<0> { + pub fn int160(&mut self) -> INT160_W { INT160_W::new(self) } #[doc = "Bit 1 - Interrupt 161"] #[inline(always)] #[must_use] - pub fn int161(&mut self) -> INT161_W<1> { + pub fn int161(&mut self) -> INT161_W { INT161_W::new(self) } #[doc = "Bit 2 - Interrupt 162"] #[inline(always)] #[must_use] - pub fn int162(&mut self) -> INT162_W<2> { + pub fn int162(&mut self) -> INT162_W { INT162_W::new(self) } #[doc = "Bit 3 - Interrupt 163"] #[inline(always)] #[must_use] - pub fn int163(&mut self) -> INT163_W<3> { + pub fn int163(&mut self) -> INT163_W { INT163_W::new(self) } #[doc = "Bit 4 - Interrupt 164"] #[inline(always)] #[must_use] - pub fn int164(&mut self) -> INT164_W<4> { + pub fn int164(&mut self) -> INT164_W { INT164_W::new(self) } #[doc = "Bit 5 - Interrupt 165"] #[inline(always)] #[must_use] - pub fn int165(&mut self) -> INT165_W<5> { + pub fn int165(&mut self) -> INT165_W { INT165_W::new(self) } #[doc = "Bit 6 - Interrupt 166"] #[inline(always)] #[must_use] - pub fn int166(&mut self) -> INT166_W<6> { + pub fn int166(&mut self) -> INT166_W { INT166_W::new(self) } #[doc = "Bit 7 - Interrupt 167"] #[inline(always)] #[must_use] - pub fn int167(&mut self) -> INT167_W<7> { + pub fn int167(&mut self) -> INT167_W { INT167_W::new(self) } #[doc = "Bit 8 - Interrupt 168"] #[inline(always)] #[must_use] - pub fn int168(&mut self) -> INT168_W<8> { + pub fn int168(&mut self) -> INT168_W { INT168_W::new(self) } #[doc = "Bit 9 - Interrupt 169"] #[inline(always)] #[must_use] - pub fn int169(&mut self) -> INT169_W<9> { + pub fn int169(&mut self) -> INT169_W { INT169_W::new(self) } #[doc = "Bit 10 - Interrupt 170"] #[inline(always)] #[must_use] - pub fn int170(&mut self) -> INT170_W<10> { + pub fn int170(&mut self) -> INT170_W { INT170_W::new(self) } #[doc = "Bit 11 - Interrupt 171"] #[inline(always)] #[must_use] - pub fn int171(&mut self) -> INT171_W<11> { + pub fn int171(&mut self) -> INT171_W { INT171_W::new(self) } #[doc = "Bit 12 - Interrupt 172"] #[inline(always)] #[must_use] - pub fn int172(&mut self) -> INT172_W<12> { + pub fn int172(&mut self) -> INT172_W { INT172_W::new(self) } #[doc = "Bit 13 - Interrupt 173"] #[inline(always)] #[must_use] - pub fn int173(&mut self) -> INT173_W<13> { + pub fn int173(&mut self) -> INT173_W { INT173_W::new(self) } #[doc = "Bit 14 - Interrupt 174"] #[inline(always)] #[must_use] - pub fn int174(&mut self) -> INT174_W<14> { + pub fn int174(&mut self) -> INT174_W { INT174_W::new(self) } #[doc = "Bit 15 - Interrupt 175"] #[inline(always)] #[must_use] - pub fn int175(&mut self) -> INT175_W<15> { + pub fn int175(&mut self) -> INT175_W { INT175_W::new(self) } #[doc = "Bit 16 - Interrupt 176"] #[inline(always)] #[must_use] - pub fn int176(&mut self) -> INT176_W<16> { + pub fn int176(&mut self) -> INT176_W { INT176_W::new(self) } #[doc = "Bit 17 - Interrupt 177"] #[inline(always)] #[must_use] - pub fn int177(&mut self) -> INT177_W<17> { + pub fn int177(&mut self) -> INT177_W { INT177_W::new(self) } #[doc = "Bit 18 - Interrupt 178"] #[inline(always)] #[must_use] - pub fn int178(&mut self) -> INT178_W<18> { + pub fn int178(&mut self) -> INT178_W { INT178_W::new(self) } #[doc = "Bit 19 - Interrupt 179"] #[inline(always)] #[must_use] - pub fn int179(&mut self) -> INT179_W<19> { + pub fn int179(&mut self) -> INT179_W { INT179_W::new(self) } #[doc = "Bit 20 - Interrupt 180"] #[inline(always)] #[must_use] - pub fn int180(&mut self) -> INT180_W<20> { + pub fn int180(&mut self) -> INT180_W { INT180_W::new(self) } #[doc = "Bit 21 - Interrupt 181"] #[inline(always)] #[must_use] - pub fn int181(&mut self) -> INT181_W<21> { + pub fn int181(&mut self) -> INT181_W { INT181_W::new(self) } #[doc = "Bit 22 - Interrupt 182"] #[inline(always)] #[must_use] - pub fn int182(&mut self) -> INT182_W<22> { + pub fn int182(&mut self) -> INT182_W { INT182_W::new(self) } #[doc = "Bit 23 - Interrupt 183"] #[inline(always)] #[must_use] - pub fn int183(&mut self) -> INT183_W<23> { + pub fn int183(&mut self) -> INT183_W { INT183_W::new(self) } #[doc = "Bit 24 - Interrupt 184"] #[inline(always)] #[must_use] - pub fn int184(&mut self) -> INT184_W<24> { + pub fn int184(&mut self) -> INT184_W { INT184_W::new(self) } #[doc = "Bit 25 - Interrupt 185"] #[inline(always)] #[must_use] - pub fn int185(&mut self) -> INT185_W<25> { + pub fn int185(&mut self) -> INT185_W { INT185_W::new(self) } #[doc = "Bit 26 - Interrupt 186"] #[inline(always)] #[must_use] - pub fn int186(&mut self) -> INT186_W<26> { + pub fn int186(&mut self) -> INT186_W { INT186_W::new(self) } #[doc = "Bit 27 - Interrupt 187"] #[inline(always)] #[must_use] - pub fn int187(&mut self) -> INT187_W<27> { + pub fn int187(&mut self) -> INT187_W { INT187_W::new(self) } #[doc = "Bit 28 - Interrupt 188"] #[inline(always)] #[must_use] - pub fn int188(&mut self) -> INT188_W<28> { + pub fn int188(&mut self) -> INT188_W { INT188_W::new(self) } #[doc = "Bit 29 - Interrupt 189"] #[inline(always)] #[must_use] - pub fn int189(&mut self) -> INT189_W<29> { + pub fn int189(&mut self) -> INT189_W { INT189_W::new(self) } #[doc = "Bit 30 - Interrupt 190"] #[inline(always)] #[must_use] - pub fn int190(&mut self) -> INT190_W<30> { + pub fn int190(&mut self) -> INT190_W { INT190_W::new(self) } #[doc = "Bit 31 - Interrupt 191"] #[inline(always)] #[must_use] - pub fn int191(&mut self) -> INT191_W<31> { + pub fn int191(&mut self) -> INT191_W { INT191_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr5](index.html) module"] +#[doc = "Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICPENDR5_SPEC; impl crate::RegisterSpec for GICD_ICPENDR5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icpendr5::R](R) reader structure"] -impl crate::Readable for GICD_ICPENDR5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icpendr5::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icpendr5::R`](R) reader structure"] +impl crate::Readable for GICD_ICPENDR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icpendr5::W`](W) writer structure"] impl crate::Writable for GICD_ICPENDR5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr6.rs index e918954..9bd4b8c 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr6.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_icpendr/gicd_icpendr6.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ICPENDR6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ICPENDR6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT192` reader - Interrupt 192"] -pub type INT192_R = crate::BitReader; +pub type INT192_R = crate::BitReader; #[doc = "Field `INT192` writer - Interrupt 192"] -pub type INT192_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT192_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT193` reader - Interrupt 193"] -pub type INT193_R = crate::BitReader; +pub type INT193_R = crate::BitReader; #[doc = "Field `INT193` writer - Interrupt 193"] -pub type INT193_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT193_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT194` reader - Interrupt 194"] -pub type INT194_R = crate::BitReader; +pub type INT194_R = crate::BitReader; #[doc = "Field `INT194` writer - Interrupt 194"] -pub type INT194_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT194_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT195` reader - Interrupt 195"] -pub type INT195_R = crate::BitReader; +pub type INT195_R = crate::BitReader; #[doc = "Field `INT195` writer - Interrupt 195"] -pub type INT195_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT195_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT196` reader - Interrupt 196"] -pub type INT196_R = crate::BitReader; +pub type INT196_R = crate::BitReader; #[doc = "Field `INT196` writer - Interrupt 196"] -pub type INT196_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT196_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT197` reader - Interrupt 197"] -pub type INT197_R = crate::BitReader; +pub type INT197_R = crate::BitReader; #[doc = "Field `INT197` writer - Interrupt 197"] -pub type INT197_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT197_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT198` reader - Interrupt 198"] -pub type INT198_R = crate::BitReader; +pub type INT198_R = crate::BitReader; #[doc = "Field `INT198` writer - Interrupt 198"] -pub type INT198_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT198_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT199` reader - Interrupt 199"] -pub type INT199_R = crate::BitReader; +pub type INT199_R = crate::BitReader; #[doc = "Field `INT199` writer - Interrupt 199"] -pub type INT199_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT199_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT200` reader - Interrupt 200"] -pub type INT200_R = crate::BitReader; +pub type INT200_R = crate::BitReader; #[doc = "Field `INT200` writer - Interrupt 200"] -pub type INT200_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT200_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT201` reader - Interrupt 201"] -pub type INT201_R = crate::BitReader; +pub type INT201_R = crate::BitReader; #[doc = "Field `INT201` writer - Interrupt 201"] -pub type INT201_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT201_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT202` reader - Interrupt 202"] -pub type INT202_R = crate::BitReader; +pub type INT202_R = crate::BitReader; #[doc = "Field `INT202` writer - Interrupt 202"] -pub type INT202_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT202_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT203` reader - Interrupt 203"] -pub type INT203_R = crate::BitReader; +pub type INT203_R = crate::BitReader; #[doc = "Field `INT203` writer - Interrupt 203"] -pub type INT203_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT203_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT204` reader - Interrupt 204"] -pub type INT204_R = crate::BitReader; +pub type INT204_R = crate::BitReader; #[doc = "Field `INT204` writer - Interrupt 204"] -pub type INT204_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT204_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT205` reader - Interrupt 205"] -pub type INT205_R = crate::BitReader; +pub type INT205_R = crate::BitReader; #[doc = "Field `INT205` writer - Interrupt 205"] -pub type INT205_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT205_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT206` reader - Interrupt 206"] -pub type INT206_R = crate::BitReader; +pub type INT206_R = crate::BitReader; #[doc = "Field `INT206` writer - Interrupt 206"] -pub type INT206_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT206_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT207` reader - Interrupt 207"] -pub type INT207_R = crate::BitReader; +pub type INT207_R = crate::BitReader; #[doc = "Field `INT207` writer - Interrupt 207"] -pub type INT207_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT207_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT208` reader - Interrupt 208"] -pub type INT208_R = crate::BitReader; +pub type INT208_R = crate::BitReader; #[doc = "Field `INT208` writer - Interrupt 208"] -pub type INT208_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT208_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT209` reader - Interrupt 209"] -pub type INT209_R = crate::BitReader; +pub type INT209_R = crate::BitReader; #[doc = "Field `INT209` writer - Interrupt 209"] -pub type INT209_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT209_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT210` reader - Interrupt 210"] -pub type INT210_R = crate::BitReader; +pub type INT210_R = crate::BitReader; #[doc = "Field `INT210` writer - Interrupt 210"] -pub type INT210_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT210_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT211` reader - Interrupt 211"] -pub type INT211_R = crate::BitReader; +pub type INT211_R = crate::BitReader; #[doc = "Field `INT211` writer - Interrupt 211"] -pub type INT211_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT211_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT212` reader - Interrupt 212"] -pub type INT212_R = crate::BitReader; +pub type INT212_R = crate::BitReader; #[doc = "Field `INT212` writer - Interrupt 212"] -pub type INT212_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT212_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT213` reader - Interrupt 213"] -pub type INT213_R = crate::BitReader; +pub type INT213_R = crate::BitReader; #[doc = "Field `INT213` writer - Interrupt 213"] -pub type INT213_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT213_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT214` reader - Interrupt 214"] -pub type INT214_R = crate::BitReader; +pub type INT214_R = crate::BitReader; #[doc = "Field `INT214` writer - Interrupt 214"] -pub type INT214_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT214_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT215` reader - Interrupt 215"] -pub type INT215_R = crate::BitReader; +pub type INT215_R = crate::BitReader; #[doc = "Field `INT215` writer - Interrupt 215"] -pub type INT215_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT215_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT216` reader - Interrupt 216"] -pub type INT216_R = crate::BitReader; +pub type INT216_R = crate::BitReader; #[doc = "Field `INT216` writer - Interrupt 216"] -pub type INT216_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT216_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT217` reader - Interrupt 217"] -pub type INT217_R = crate::BitReader; +pub type INT217_R = crate::BitReader; #[doc = "Field `INT217` writer - Interrupt 217"] -pub type INT217_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT217_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT218` reader - Interrupt 218"] -pub type INT218_R = crate::BitReader; +pub type INT218_R = crate::BitReader; #[doc = "Field `INT218` writer - Interrupt 218"] -pub type INT218_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT218_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT219` reader - Interrupt 219"] -pub type INT219_R = crate::BitReader; +pub type INT219_R = crate::BitReader; #[doc = "Field `INT219` writer - Interrupt 219"] -pub type INT219_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT219_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT220` reader - Interrupt 220"] -pub type INT220_R = crate::BitReader; +pub type INT220_R = crate::BitReader; #[doc = "Field `INT220` writer - Interrupt 220"] -pub type INT220_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT220_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT221` reader - Interrupt 221"] -pub type INT221_R = crate::BitReader; +pub type INT221_R = crate::BitReader; #[doc = "Field `INT221` writer - Interrupt 221"] -pub type INT221_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT221_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT222` reader - Interrupt 222"] -pub type INT222_R = crate::BitReader; +pub type INT222_R = crate::BitReader; #[doc = "Field `INT222` writer - Interrupt 222"] -pub type INT222_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT222_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT223` reader - Interrupt 223"] -pub type INT223_R = crate::BitReader; +pub type INT223_R = crate::BitReader; #[doc = "Field `INT223` writer - Interrupt 223"] -pub type INT223_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GICD_ICPENDR6_SPEC, bool, O>; +pub type INT223_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT223_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ICPENDR6") + .field("int192", &format_args!("{}", self.int192().bit())) + .field("int193", &format_args!("{}", self.int193().bit())) + .field("int194", &format_args!("{}", self.int194().bit())) + .field("int195", &format_args!("{}", self.int195().bit())) + .field("int196", &format_args!("{}", self.int196().bit())) + .field("int197", &format_args!("{}", self.int197().bit())) + .field("int198", &format_args!("{}", self.int198().bit())) + .field("int199", &format_args!("{}", self.int199().bit())) + .field("int200", &format_args!("{}", self.int200().bit())) + .field("int201", &format_args!("{}", self.int201().bit())) + .field("int202", &format_args!("{}", self.int202().bit())) + .field("int203", &format_args!("{}", self.int203().bit())) + .field("int204", &format_args!("{}", self.int204().bit())) + .field("int205", &format_args!("{}", self.int205().bit())) + .field("int206", &format_args!("{}", self.int206().bit())) + .field("int207", &format_args!("{}", self.int207().bit())) + .field("int208", &format_args!("{}", self.int208().bit())) + .field("int209", &format_args!("{}", self.int209().bit())) + .field("int210", &format_args!("{}", self.int210().bit())) + .field("int211", &format_args!("{}", self.int211().bit())) + .field("int212", &format_args!("{}", self.int212().bit())) + .field("int213", &format_args!("{}", self.int213().bit())) + .field("int214", &format_args!("{}", self.int214().bit())) + .field("int215", &format_args!("{}", self.int215().bit())) + .field("int216", &format_args!("{}", self.int216().bit())) + .field("int217", &format_args!("{}", self.int217().bit())) + .field("int218", &format_args!("{}", self.int218().bit())) + .field("int219", &format_args!("{}", self.int219().bit())) + .field("int220", &format_args!("{}", self.int220().bit())) + .field("int221", &format_args!("{}", self.int221().bit())) + .field("int222", &format_args!("{}", self.int222().bit())) + .field("int223", &format_args!("{}", self.int223().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] #[must_use] - pub fn int192(&mut self) -> INT192_W<0> { + pub fn int192(&mut self) -> INT192_W { INT192_W::new(self) } #[doc = "Bit 1 - Interrupt 193"] #[inline(always)] #[must_use] - pub fn int193(&mut self) -> INT193_W<1> { + pub fn int193(&mut self) -> INT193_W { INT193_W::new(self) } #[doc = "Bit 2 - Interrupt 194"] #[inline(always)] #[must_use] - pub fn int194(&mut self) -> INT194_W<2> { + pub fn int194(&mut self) -> INT194_W { INT194_W::new(self) } #[doc = "Bit 3 - Interrupt 195"] #[inline(always)] #[must_use] - pub fn int195(&mut self) -> INT195_W<3> { + pub fn int195(&mut self) -> INT195_W { INT195_W::new(self) } #[doc = "Bit 4 - Interrupt 196"] #[inline(always)] #[must_use] - pub fn int196(&mut self) -> INT196_W<4> { + pub fn int196(&mut self) -> INT196_W { INT196_W::new(self) } #[doc = "Bit 5 - Interrupt 197"] #[inline(always)] #[must_use] - pub fn int197(&mut self) -> INT197_W<5> { + pub fn int197(&mut self) -> INT197_W { INT197_W::new(self) } #[doc = "Bit 6 - Interrupt 198"] #[inline(always)] #[must_use] - pub fn int198(&mut self) -> INT198_W<6> { + pub fn int198(&mut self) -> INT198_W { INT198_W::new(self) } #[doc = "Bit 7 - Interrupt 199"] #[inline(always)] #[must_use] - pub fn int199(&mut self) -> INT199_W<7> { + pub fn int199(&mut self) -> INT199_W { INT199_W::new(self) } #[doc = "Bit 8 - Interrupt 200"] #[inline(always)] #[must_use] - pub fn int200(&mut self) -> INT200_W<8> { + pub fn int200(&mut self) -> INT200_W { INT200_W::new(self) } #[doc = "Bit 9 - Interrupt 201"] #[inline(always)] #[must_use] - pub fn int201(&mut self) -> INT201_W<9> { + pub fn int201(&mut self) -> INT201_W { INT201_W::new(self) } #[doc = "Bit 10 - Interrupt 202"] #[inline(always)] #[must_use] - pub fn int202(&mut self) -> INT202_W<10> { + pub fn int202(&mut self) -> INT202_W { INT202_W::new(self) } #[doc = "Bit 11 - Interrupt 203"] #[inline(always)] #[must_use] - pub fn int203(&mut self) -> INT203_W<11> { + pub fn int203(&mut self) -> INT203_W { INT203_W::new(self) } #[doc = "Bit 12 - Interrupt 204"] #[inline(always)] #[must_use] - pub fn int204(&mut self) -> INT204_W<12> { + pub fn int204(&mut self) -> INT204_W { INT204_W::new(self) } #[doc = "Bit 13 - Interrupt 205"] #[inline(always)] #[must_use] - pub fn int205(&mut self) -> INT205_W<13> { + pub fn int205(&mut self) -> INT205_W { INT205_W::new(self) } #[doc = "Bit 14 - Interrupt 206"] #[inline(always)] #[must_use] - pub fn int206(&mut self) -> INT206_W<14> { + pub fn int206(&mut self) -> INT206_W { INT206_W::new(self) } #[doc = "Bit 15 - Interrupt 207"] #[inline(always)] #[must_use] - pub fn int207(&mut self) -> INT207_W<15> { + pub fn int207(&mut self) -> INT207_W { INT207_W::new(self) } #[doc = "Bit 16 - Interrupt 208"] #[inline(always)] #[must_use] - pub fn int208(&mut self) -> INT208_W<16> { + pub fn int208(&mut self) -> INT208_W { INT208_W::new(self) } #[doc = "Bit 17 - Interrupt 209"] #[inline(always)] #[must_use] - pub fn int209(&mut self) -> INT209_W<17> { + pub fn int209(&mut self) -> INT209_W { INT209_W::new(self) } #[doc = "Bit 18 - Interrupt 210"] #[inline(always)] #[must_use] - pub fn int210(&mut self) -> INT210_W<18> { + pub fn int210(&mut self) -> INT210_W { INT210_W::new(self) } #[doc = "Bit 19 - Interrupt 211"] #[inline(always)] #[must_use] - pub fn int211(&mut self) -> INT211_W<19> { + pub fn int211(&mut self) -> INT211_W { INT211_W::new(self) } #[doc = "Bit 20 - Interrupt 212"] #[inline(always)] #[must_use] - pub fn int212(&mut self) -> INT212_W<20> { + pub fn int212(&mut self) -> INT212_W { INT212_W::new(self) } #[doc = "Bit 21 - Interrupt 213"] #[inline(always)] #[must_use] - pub fn int213(&mut self) -> INT213_W<21> { + pub fn int213(&mut self) -> INT213_W { INT213_W::new(self) } #[doc = "Bit 22 - Interrupt 214"] #[inline(always)] #[must_use] - pub fn int214(&mut self) -> INT214_W<22> { + pub fn int214(&mut self) -> INT214_W { INT214_W::new(self) } #[doc = "Bit 23 - Interrupt 215"] #[inline(always)] #[must_use] - pub fn int215(&mut self) -> INT215_W<23> { + pub fn int215(&mut self) -> INT215_W { INT215_W::new(self) } #[doc = "Bit 24 - Interrupt 216"] #[inline(always)] #[must_use] - pub fn int216(&mut self) -> INT216_W<24> { + pub fn int216(&mut self) -> INT216_W { INT216_W::new(self) } #[doc = "Bit 25 - Interrupt 217"] #[inline(always)] #[must_use] - pub fn int217(&mut self) -> INT217_W<25> { + pub fn int217(&mut self) -> INT217_W { INT217_W::new(self) } #[doc = "Bit 26 - Interrupt 218"] #[inline(always)] #[must_use] - pub fn int218(&mut self) -> INT218_W<26> { + pub fn int218(&mut self) -> INT218_W { INT218_W::new(self) } #[doc = "Bit 27 - Interrupt 219"] #[inline(always)] #[must_use] - pub fn int219(&mut self) -> INT219_W<27> { + pub fn int219(&mut self) -> INT219_W { INT219_W::new(self) } #[doc = "Bit 28 - Interrupt 220"] #[inline(always)] #[must_use] - pub fn int220(&mut self) -> INT220_W<28> { + pub fn int220(&mut self) -> INT220_W { INT220_W::new(self) } #[doc = "Bit 29 - Interrupt 221"] #[inline(always)] #[must_use] - pub fn int221(&mut self) -> INT221_W<29> { + pub fn int221(&mut self) -> INT221_W { INT221_W::new(self) } #[doc = "Bit 30 - Interrupt 222"] #[inline(always)] #[must_use] - pub fn int222(&mut self) -> INT222_W<30> { + pub fn int222(&mut self) -> INT222_W { INT222_W::new(self) } #[doc = "Bit 31 - Interrupt 223"] #[inline(always)] #[must_use] - pub fn int223(&mut self) -> INT223_W<31> { + pub fn int223(&mut self) -> INT223_W { INT223_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_icpendr6](index.html) module"] +#[doc = "Interrupt Clear-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_icpendr6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_icpendr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ICPENDR6_SPEC; impl crate::RegisterSpec for GICD_ICPENDR6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_icpendr6::R](R) reader structure"] -impl crate::Readable for GICD_ICPENDR6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_icpendr6::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_icpendr6::R`](R) reader structure"] +impl crate::Readable for GICD_ICPENDR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_icpendr6::W`](W) writer structure"] impl crate::Writable for GICD_ICPENDR6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr.rs index 11c8975..5bac0f6 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct GICD_IGROUPR { #[doc = "0x00 - Interrupt Group"] pub gicd_igroupr0: GICD_IGROUPR0, @@ -16,31 +17,38 @@ pub struct GICD_IGROUPR { #[doc = "0x18 - Interrupt Group"] pub gicd_igroupr6: GICD_IGROUPR6, } -#[doc = "GICD_IGROUPR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IGROUPR0 (rw) register accessor: Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_igroupr0`] +module"] pub type GICD_IGROUPR0 = crate::Reg; #[doc = "Interrupt Group"] pub mod gicd_igroupr0; -#[doc = "GICD_IGROUPR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IGROUPR1 (rw) register accessor: Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_igroupr1`] +module"] pub type GICD_IGROUPR1 = crate::Reg; #[doc = "Interrupt Group"] pub mod gicd_igroupr1; -#[doc = "GICD_IGROUPR2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IGROUPR2 (rw) register accessor: Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_igroupr2`] +module"] pub type GICD_IGROUPR2 = crate::Reg; #[doc = "Interrupt Group"] pub mod gicd_igroupr2; -#[doc = "GICD_IGROUPR3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IGROUPR3 (rw) register accessor: Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_igroupr3`] +module"] pub type GICD_IGROUPR3 = crate::Reg; #[doc = "Interrupt Group"] pub mod gicd_igroupr3; -#[doc = "GICD_IGROUPR4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IGROUPR4 (rw) register accessor: Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_igroupr4`] +module"] pub type GICD_IGROUPR4 = crate::Reg; #[doc = "Interrupt Group"] pub mod gicd_igroupr4; -#[doc = "GICD_IGROUPR5 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IGROUPR5 (rw) register accessor: Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_igroupr5`] +module"] pub type GICD_IGROUPR5 = crate::Reg; #[doc = "Interrupt Group"] pub mod gicd_igroupr5; -#[doc = "GICD_IGROUPR6 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IGROUPR6 (rw) register accessor: Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_igroupr6`] +module"] pub type GICD_IGROUPR6 = crate::Reg; #[doc = "Interrupt Group"] pub mod gicd_igroupr6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr0.rs index d68154b..5e8cdd0 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr0.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_IGROUPR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IGROUPR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT0` reader - Interrupt 0"] -pub type INT0_R = crate::BitReader; +pub type INT0_R = crate::BitReader; #[doc = "Field `INT0` writer - Interrupt 0"] -pub type INT0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT1` reader - Interrupt 1"] -pub type INT1_R = crate::BitReader; +pub type INT1_R = crate::BitReader; #[doc = "Field `INT1` writer - Interrupt 1"] -pub type INT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT2` reader - Interrupt 2"] -pub type INT2_R = crate::BitReader; +pub type INT2_R = crate::BitReader; #[doc = "Field `INT2` writer - Interrupt 2"] -pub type INT2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT3` reader - Interrupt 3"] -pub type INT3_R = crate::BitReader; +pub type INT3_R = crate::BitReader; #[doc = "Field `INT3` writer - Interrupt 3"] -pub type INT3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT4` reader - Interrupt 4"] -pub type INT4_R = crate::BitReader; +pub type INT4_R = crate::BitReader; #[doc = "Field `INT4` writer - Interrupt 4"] -pub type INT4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT5` reader - Interrupt 5"] -pub type INT5_R = crate::BitReader; +pub type INT5_R = crate::BitReader; #[doc = "Field `INT5` writer - Interrupt 5"] -pub type INT5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT6` reader - Interrupt 6"] -pub type INT6_R = crate::BitReader; +pub type INT6_R = crate::BitReader; #[doc = "Field `INT6` writer - Interrupt 6"] -pub type INT6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT7` reader - Interrupt 7"] -pub type INT7_R = crate::BitReader; +pub type INT7_R = crate::BitReader; #[doc = "Field `INT7` writer - Interrupt 7"] -pub type INT7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT8` reader - Interrupt 8"] -pub type INT8_R = crate::BitReader; +pub type INT8_R = crate::BitReader; #[doc = "Field `INT8` writer - Interrupt 8"] -pub type INT8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT9` reader - Interrupt 9"] -pub type INT9_R = crate::BitReader; +pub type INT9_R = crate::BitReader; #[doc = "Field `INT9` writer - Interrupt 9"] -pub type INT9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT10` reader - Interrupt 10"] -pub type INT10_R = crate::BitReader; +pub type INT10_R = crate::BitReader; #[doc = "Field `INT10` writer - Interrupt 10"] -pub type INT10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT11` reader - Interrupt 11"] -pub type INT11_R = crate::BitReader; +pub type INT11_R = crate::BitReader; #[doc = "Field `INT11` writer - Interrupt 11"] -pub type INT11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT12` reader - Interrupt 12"] -pub type INT12_R = crate::BitReader; +pub type INT12_R = crate::BitReader; #[doc = "Field `INT12` writer - Interrupt 12"] -pub type INT12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT13` reader - Interrupt 13"] -pub type INT13_R = crate::BitReader; +pub type INT13_R = crate::BitReader; #[doc = "Field `INT13` writer - Interrupt 13"] -pub type INT13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT14` reader - Interrupt 14"] -pub type INT14_R = crate::BitReader; +pub type INT14_R = crate::BitReader; #[doc = "Field `INT14` writer - Interrupt 14"] -pub type INT14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT15` reader - Interrupt 15"] -pub type INT15_R = crate::BitReader; +pub type INT15_R = crate::BitReader; #[doc = "Field `INT15` writer - Interrupt 15"] -pub type INT15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT16` reader - Interrupt 16"] -pub type INT16_R = crate::BitReader; +pub type INT16_R = crate::BitReader; #[doc = "Field `INT16` writer - Interrupt 16"] -pub type INT16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT17` reader - Interrupt 17"] -pub type INT17_R = crate::BitReader; +pub type INT17_R = crate::BitReader; #[doc = "Field `INT17` writer - Interrupt 17"] -pub type INT17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT18` reader - Interrupt 18"] -pub type INT18_R = crate::BitReader; +pub type INT18_R = crate::BitReader; #[doc = "Field `INT18` writer - Interrupt 18"] -pub type INT18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT19` reader - Interrupt 19"] -pub type INT19_R = crate::BitReader; +pub type INT19_R = crate::BitReader; #[doc = "Field `INT19` writer - Interrupt 19"] -pub type INT19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT20` reader - Interrupt 20"] -pub type INT20_R = crate::BitReader; +pub type INT20_R = crate::BitReader; #[doc = "Field `INT20` writer - Interrupt 20"] -pub type INT20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT21` reader - Interrupt 21"] -pub type INT21_R = crate::BitReader; +pub type INT21_R = crate::BitReader; #[doc = "Field `INT21` writer - Interrupt 21"] -pub type INT21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT22` reader - Interrupt 22"] -pub type INT22_R = crate::BitReader; +pub type INT22_R = crate::BitReader; #[doc = "Field `INT22` writer - Interrupt 22"] -pub type INT22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT23` reader - Interrupt 23"] -pub type INT23_R = crate::BitReader; +pub type INT23_R = crate::BitReader; #[doc = "Field `INT23` writer - Interrupt 23"] -pub type INT23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT24` reader - Interrupt 24"] -pub type INT24_R = crate::BitReader; +pub type INT24_R = crate::BitReader; #[doc = "Field `INT24` writer - Interrupt 24"] -pub type INT24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT25` reader - Interrupt 25"] -pub type INT25_R = crate::BitReader; +pub type INT25_R = crate::BitReader; #[doc = "Field `INT25` writer - Interrupt 25"] -pub type INT25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT26` reader - Interrupt 26"] -pub type INT26_R = crate::BitReader; +pub type INT26_R = crate::BitReader; #[doc = "Field `INT26` writer - Interrupt 26"] -pub type INT26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT27` reader - Interrupt 27"] -pub type INT27_R = crate::BitReader; +pub type INT27_R = crate::BitReader; #[doc = "Field `INT27` writer - Interrupt 27"] -pub type INT27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT28` reader - Interrupt 28"] -pub type INT28_R = crate::BitReader; +pub type INT28_R = crate::BitReader; #[doc = "Field `INT28` writer - Interrupt 28"] -pub type INT28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT29` reader - Interrupt 29"] -pub type INT29_R = crate::BitReader; +pub type INT29_R = crate::BitReader; #[doc = "Field `INT29` writer - Interrupt 29"] -pub type INT29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT30` reader - Interrupt 30"] -pub type INT30_R = crate::BitReader; +pub type INT30_R = crate::BitReader; #[doc = "Field `INT30` writer - Interrupt 30"] -pub type INT30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT31` reader - Interrupt 31"] -pub type INT31_R = crate::BitReader; +pub type INT31_R = crate::BitReader; #[doc = "Field `INT31` writer - Interrupt 31"] -pub type INT31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR0_SPEC, bool, O>; +pub type INT31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IGROUPR0") + .field("int0", &format_args!("{}", self.int0().bit())) + .field("int1", &format_args!("{}", self.int1().bit())) + .field("int2", &format_args!("{}", self.int2().bit())) + .field("int3", &format_args!("{}", self.int3().bit())) + .field("int4", &format_args!("{}", self.int4().bit())) + .field("int5", &format_args!("{}", self.int5().bit())) + .field("int6", &format_args!("{}", self.int6().bit())) + .field("int7", &format_args!("{}", self.int7().bit())) + .field("int8", &format_args!("{}", self.int8().bit())) + .field("int9", &format_args!("{}", self.int9().bit())) + .field("int10", &format_args!("{}", self.int10().bit())) + .field("int11", &format_args!("{}", self.int11().bit())) + .field("int12", &format_args!("{}", self.int12().bit())) + .field("int13", &format_args!("{}", self.int13().bit())) + .field("int14", &format_args!("{}", self.int14().bit())) + .field("int15", &format_args!("{}", self.int15().bit())) + .field("int16", &format_args!("{}", self.int16().bit())) + .field("int17", &format_args!("{}", self.int17().bit())) + .field("int18", &format_args!("{}", self.int18().bit())) + .field("int19", &format_args!("{}", self.int19().bit())) + .field("int20", &format_args!("{}", self.int20().bit())) + .field("int21", &format_args!("{}", self.int21().bit())) + .field("int22", &format_args!("{}", self.int22().bit())) + .field("int23", &format_args!("{}", self.int23().bit())) + .field("int24", &format_args!("{}", self.int24().bit())) + .field("int25", &format_args!("{}", self.int25().bit())) + .field("int26", &format_args!("{}", self.int26().bit())) + .field("int27", &format_args!("{}", self.int27().bit())) + .field("int28", &format_args!("{}", self.int28().bit())) + .field("int29", &format_args!("{}", self.int29().bit())) + .field("int30", &format_args!("{}", self.int30().bit())) + .field("int31", &format_args!("{}", self.int31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] #[must_use] - pub fn int0(&mut self) -> INT0_W<0> { + pub fn int0(&mut self) -> INT0_W { INT0_W::new(self) } #[doc = "Bit 1 - Interrupt 1"] #[inline(always)] #[must_use] - pub fn int1(&mut self) -> INT1_W<1> { + pub fn int1(&mut self) -> INT1_W { INT1_W::new(self) } #[doc = "Bit 2 - Interrupt 2"] #[inline(always)] #[must_use] - pub fn int2(&mut self) -> INT2_W<2> { + pub fn int2(&mut self) -> INT2_W { INT2_W::new(self) } #[doc = "Bit 3 - Interrupt 3"] #[inline(always)] #[must_use] - pub fn int3(&mut self) -> INT3_W<3> { + pub fn int3(&mut self) -> INT3_W { INT3_W::new(self) } #[doc = "Bit 4 - Interrupt 4"] #[inline(always)] #[must_use] - pub fn int4(&mut self) -> INT4_W<4> { + pub fn int4(&mut self) -> INT4_W { INT4_W::new(self) } #[doc = "Bit 5 - Interrupt 5"] #[inline(always)] #[must_use] - pub fn int5(&mut self) -> INT5_W<5> { + pub fn int5(&mut self) -> INT5_W { INT5_W::new(self) } #[doc = "Bit 6 - Interrupt 6"] #[inline(always)] #[must_use] - pub fn int6(&mut self) -> INT6_W<6> { + pub fn int6(&mut self) -> INT6_W { INT6_W::new(self) } #[doc = "Bit 7 - Interrupt 7"] #[inline(always)] #[must_use] - pub fn int7(&mut self) -> INT7_W<7> { + pub fn int7(&mut self) -> INT7_W { INT7_W::new(self) } #[doc = "Bit 8 - Interrupt 8"] #[inline(always)] #[must_use] - pub fn int8(&mut self) -> INT8_W<8> { + pub fn int8(&mut self) -> INT8_W { INT8_W::new(self) } #[doc = "Bit 9 - Interrupt 9"] #[inline(always)] #[must_use] - pub fn int9(&mut self) -> INT9_W<9> { + pub fn int9(&mut self) -> INT9_W { INT9_W::new(self) } #[doc = "Bit 10 - Interrupt 10"] #[inline(always)] #[must_use] - pub fn int10(&mut self) -> INT10_W<10> { + pub fn int10(&mut self) -> INT10_W { INT10_W::new(self) } #[doc = "Bit 11 - Interrupt 11"] #[inline(always)] #[must_use] - pub fn int11(&mut self) -> INT11_W<11> { + pub fn int11(&mut self) -> INT11_W { INT11_W::new(self) } #[doc = "Bit 12 - Interrupt 12"] #[inline(always)] #[must_use] - pub fn int12(&mut self) -> INT12_W<12> { + pub fn int12(&mut self) -> INT12_W { INT12_W::new(self) } #[doc = "Bit 13 - Interrupt 13"] #[inline(always)] #[must_use] - pub fn int13(&mut self) -> INT13_W<13> { + pub fn int13(&mut self) -> INT13_W { INT13_W::new(self) } #[doc = "Bit 14 - Interrupt 14"] #[inline(always)] #[must_use] - pub fn int14(&mut self) -> INT14_W<14> { + pub fn int14(&mut self) -> INT14_W { INT14_W::new(self) } #[doc = "Bit 15 - Interrupt 15"] #[inline(always)] #[must_use] - pub fn int15(&mut self) -> INT15_W<15> { + pub fn int15(&mut self) -> INT15_W { INT15_W::new(self) } #[doc = "Bit 16 - Interrupt 16"] #[inline(always)] #[must_use] - pub fn int16(&mut self) -> INT16_W<16> { + pub fn int16(&mut self) -> INT16_W { INT16_W::new(self) } #[doc = "Bit 17 - Interrupt 17"] #[inline(always)] #[must_use] - pub fn int17(&mut self) -> INT17_W<17> { + pub fn int17(&mut self) -> INT17_W { INT17_W::new(self) } #[doc = "Bit 18 - Interrupt 18"] #[inline(always)] #[must_use] - pub fn int18(&mut self) -> INT18_W<18> { + pub fn int18(&mut self) -> INT18_W { INT18_W::new(self) } #[doc = "Bit 19 - Interrupt 19"] #[inline(always)] #[must_use] - pub fn int19(&mut self) -> INT19_W<19> { + pub fn int19(&mut self) -> INT19_W { INT19_W::new(self) } #[doc = "Bit 20 - Interrupt 20"] #[inline(always)] #[must_use] - pub fn int20(&mut self) -> INT20_W<20> { + pub fn int20(&mut self) -> INT20_W { INT20_W::new(self) } #[doc = "Bit 21 - Interrupt 21"] #[inline(always)] #[must_use] - pub fn int21(&mut self) -> INT21_W<21> { + pub fn int21(&mut self) -> INT21_W { INT21_W::new(self) } #[doc = "Bit 22 - Interrupt 22"] #[inline(always)] #[must_use] - pub fn int22(&mut self) -> INT22_W<22> { + pub fn int22(&mut self) -> INT22_W { INT22_W::new(self) } #[doc = "Bit 23 - Interrupt 23"] #[inline(always)] #[must_use] - pub fn int23(&mut self) -> INT23_W<23> { + pub fn int23(&mut self) -> INT23_W { INT23_W::new(self) } #[doc = "Bit 24 - Interrupt 24"] #[inline(always)] #[must_use] - pub fn int24(&mut self) -> INT24_W<24> { + pub fn int24(&mut self) -> INT24_W { INT24_W::new(self) } #[doc = "Bit 25 - Interrupt 25"] #[inline(always)] #[must_use] - pub fn int25(&mut self) -> INT25_W<25> { + pub fn int25(&mut self) -> INT25_W { INT25_W::new(self) } #[doc = "Bit 26 - Interrupt 26"] #[inline(always)] #[must_use] - pub fn int26(&mut self) -> INT26_W<26> { + pub fn int26(&mut self) -> INT26_W { INT26_W::new(self) } #[doc = "Bit 27 - Interrupt 27"] #[inline(always)] #[must_use] - pub fn int27(&mut self) -> INT27_W<27> { + pub fn int27(&mut self) -> INT27_W { INT27_W::new(self) } #[doc = "Bit 28 - Interrupt 28"] #[inline(always)] #[must_use] - pub fn int28(&mut self) -> INT28_W<28> { + pub fn int28(&mut self) -> INT28_W { INT28_W::new(self) } #[doc = "Bit 29 - Interrupt 29"] #[inline(always)] #[must_use] - pub fn int29(&mut self) -> INT29_W<29> { + pub fn int29(&mut self) -> INT29_W { INT29_W::new(self) } #[doc = "Bit 30 - Interrupt 30"] #[inline(always)] #[must_use] - pub fn int30(&mut self) -> INT30_W<30> { + pub fn int30(&mut self) -> INT30_W { INT30_W::new(self) } #[doc = "Bit 31 - Interrupt 31"] #[inline(always)] #[must_use] - pub fn int31(&mut self) -> INT31_W<31> { + pub fn int31(&mut self) -> INT31_W { INT31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr0](index.html) module"] +#[doc = "Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IGROUPR0_SPEC; impl crate::RegisterSpec for GICD_IGROUPR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_igroupr0::R](R) reader structure"] -impl crate::Readable for GICD_IGROUPR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_igroupr0::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_igroupr0::R`](R) reader structure"] +impl crate::Readable for GICD_IGROUPR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_igroupr0::W`](W) writer structure"] impl crate::Writable for GICD_IGROUPR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr1.rs index ad44459..7ea91f6 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr1.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr1.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_IGROUPR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IGROUPR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT32` reader - Interrupt 32"] -pub type INT32_R = crate::BitReader; +pub type INT32_R = crate::BitReader; #[doc = "Field `INT32` writer - Interrupt 32"] -pub type INT32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT33` reader - Interrupt 33"] -pub type INT33_R = crate::BitReader; +pub type INT33_R = crate::BitReader; #[doc = "Field `INT33` writer - Interrupt 33"] -pub type INT33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT34` reader - Interrupt 34"] -pub type INT34_R = crate::BitReader; +pub type INT34_R = crate::BitReader; #[doc = "Field `INT34` writer - Interrupt 34"] -pub type INT34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT35` reader - Interrupt 35"] -pub type INT35_R = crate::BitReader; +pub type INT35_R = crate::BitReader; #[doc = "Field `INT35` writer - Interrupt 35"] -pub type INT35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT36` reader - Interrupt 36"] -pub type INT36_R = crate::BitReader; +pub type INT36_R = crate::BitReader; #[doc = "Field `INT36` writer - Interrupt 36"] -pub type INT36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT37` reader - Interrupt 37"] -pub type INT37_R = crate::BitReader; +pub type INT37_R = crate::BitReader; #[doc = "Field `INT37` writer - Interrupt 37"] -pub type INT37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT38` reader - Interrupt 38"] -pub type INT38_R = crate::BitReader; +pub type INT38_R = crate::BitReader; #[doc = "Field `INT38` writer - Interrupt 38"] -pub type INT38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT39` reader - Interrupt 39"] -pub type INT39_R = crate::BitReader; +pub type INT39_R = crate::BitReader; #[doc = "Field `INT39` writer - Interrupt 39"] -pub type INT39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT40` reader - Interrupt 40"] -pub type INT40_R = crate::BitReader; +pub type INT40_R = crate::BitReader; #[doc = "Field `INT40` writer - Interrupt 40"] -pub type INT40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT41` reader - Interrupt 41"] -pub type INT41_R = crate::BitReader; +pub type INT41_R = crate::BitReader; #[doc = "Field `INT41` writer - Interrupt 41"] -pub type INT41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT42` reader - Interrupt 42"] -pub type INT42_R = crate::BitReader; +pub type INT42_R = crate::BitReader; #[doc = "Field `INT42` writer - Interrupt 42"] -pub type INT42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT43` reader - Interrupt 43"] -pub type INT43_R = crate::BitReader; +pub type INT43_R = crate::BitReader; #[doc = "Field `INT43` writer - Interrupt 43"] -pub type INT43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT44` reader - Interrupt 44"] -pub type INT44_R = crate::BitReader; +pub type INT44_R = crate::BitReader; #[doc = "Field `INT44` writer - Interrupt 44"] -pub type INT44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT45` reader - Interrupt 45"] -pub type INT45_R = crate::BitReader; +pub type INT45_R = crate::BitReader; #[doc = "Field `INT45` writer - Interrupt 45"] -pub type INT45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT46` reader - Interrupt 46"] -pub type INT46_R = crate::BitReader; +pub type INT46_R = crate::BitReader; #[doc = "Field `INT46` writer - Interrupt 46"] -pub type INT46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT47` reader - Interrupt 47"] -pub type INT47_R = crate::BitReader; +pub type INT47_R = crate::BitReader; #[doc = "Field `INT47` writer - Interrupt 47"] -pub type INT47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT48` reader - Interrupt 48"] -pub type INT48_R = crate::BitReader; +pub type INT48_R = crate::BitReader; #[doc = "Field `INT48` writer - Interrupt 48"] -pub type INT48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT49` reader - Interrupt 49"] -pub type INT49_R = crate::BitReader; +pub type INT49_R = crate::BitReader; #[doc = "Field `INT49` writer - Interrupt 49"] -pub type INT49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT50` reader - Interrupt 50"] -pub type INT50_R = crate::BitReader; +pub type INT50_R = crate::BitReader; #[doc = "Field `INT50` writer - Interrupt 50"] -pub type INT50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT51` reader - Interrupt 51"] -pub type INT51_R = crate::BitReader; +pub type INT51_R = crate::BitReader; #[doc = "Field `INT51` writer - Interrupt 51"] -pub type INT51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT52` reader - Interrupt 52"] -pub type INT52_R = crate::BitReader; +pub type INT52_R = crate::BitReader; #[doc = "Field `INT52` writer - Interrupt 52"] -pub type INT52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT53` reader - Interrupt 53"] -pub type INT53_R = crate::BitReader; +pub type INT53_R = crate::BitReader; #[doc = "Field `INT53` writer - Interrupt 53"] -pub type INT53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT54` reader - Interrupt 54"] -pub type INT54_R = crate::BitReader; +pub type INT54_R = crate::BitReader; #[doc = "Field `INT54` writer - Interrupt 54"] -pub type INT54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT54_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT55` reader - Interrupt 55"] -pub type INT55_R = crate::BitReader; +pub type INT55_R = crate::BitReader; #[doc = "Field `INT55` writer - Interrupt 55"] -pub type INT55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT55_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT56` reader - Interrupt 56"] -pub type INT56_R = crate::BitReader; +pub type INT56_R = crate::BitReader; #[doc = "Field `INT56` writer - Interrupt 56"] -pub type INT56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT57` reader - Interrupt 57"] -pub type INT57_R = crate::BitReader; +pub type INT57_R = crate::BitReader; #[doc = "Field `INT57` writer - Interrupt 57"] -pub type INT57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT58` reader - Interrupt 58"] -pub type INT58_R = crate::BitReader; +pub type INT58_R = crate::BitReader; #[doc = "Field `INT58` writer - Interrupt 58"] -pub type INT58_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT58_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT59` reader - Interrupt 59"] -pub type INT59_R = crate::BitReader; +pub type INT59_R = crate::BitReader; #[doc = "Field `INT59` writer - Interrupt 59"] -pub type INT59_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT59_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT60` reader - Interrupt 60"] -pub type INT60_R = crate::BitReader; +pub type INT60_R = crate::BitReader; #[doc = "Field `INT60` writer - Interrupt 60"] -pub type INT60_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT60_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT61` reader - Interrupt 61"] -pub type INT61_R = crate::BitReader; +pub type INT61_R = crate::BitReader; #[doc = "Field `INT61` writer - Interrupt 61"] -pub type INT61_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT61_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT62` reader - Interrupt 62"] -pub type INT62_R = crate::BitReader; +pub type INT62_R = crate::BitReader; #[doc = "Field `INT62` writer - Interrupt 62"] -pub type INT62_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT62_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT63` reader - Interrupt 63"] -pub type INT63_R = crate::BitReader; +pub type INT63_R = crate::BitReader; #[doc = "Field `INT63` writer - Interrupt 63"] -pub type INT63_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR1_SPEC, bool, O>; +pub type INT63_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT63_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IGROUPR1") + .field("int32", &format_args!("{}", self.int32().bit())) + .field("int33", &format_args!("{}", self.int33().bit())) + .field("int34", &format_args!("{}", self.int34().bit())) + .field("int35", &format_args!("{}", self.int35().bit())) + .field("int36", &format_args!("{}", self.int36().bit())) + .field("int37", &format_args!("{}", self.int37().bit())) + .field("int38", &format_args!("{}", self.int38().bit())) + .field("int39", &format_args!("{}", self.int39().bit())) + .field("int40", &format_args!("{}", self.int40().bit())) + .field("int41", &format_args!("{}", self.int41().bit())) + .field("int42", &format_args!("{}", self.int42().bit())) + .field("int43", &format_args!("{}", self.int43().bit())) + .field("int44", &format_args!("{}", self.int44().bit())) + .field("int45", &format_args!("{}", self.int45().bit())) + .field("int46", &format_args!("{}", self.int46().bit())) + .field("int47", &format_args!("{}", self.int47().bit())) + .field("int48", &format_args!("{}", self.int48().bit())) + .field("int49", &format_args!("{}", self.int49().bit())) + .field("int50", &format_args!("{}", self.int50().bit())) + .field("int51", &format_args!("{}", self.int51().bit())) + .field("int52", &format_args!("{}", self.int52().bit())) + .field("int53", &format_args!("{}", self.int53().bit())) + .field("int54", &format_args!("{}", self.int54().bit())) + .field("int55", &format_args!("{}", self.int55().bit())) + .field("int56", &format_args!("{}", self.int56().bit())) + .field("int57", &format_args!("{}", self.int57().bit())) + .field("int58", &format_args!("{}", self.int58().bit())) + .field("int59", &format_args!("{}", self.int59().bit())) + .field("int60", &format_args!("{}", self.int60().bit())) + .field("int61", &format_args!("{}", self.int61().bit())) + .field("int62", &format_args!("{}", self.int62().bit())) + .field("int63", &format_args!("{}", self.int63().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] #[must_use] - pub fn int32(&mut self) -> INT32_W<0> { + pub fn int32(&mut self) -> INT32_W { INT32_W::new(self) } #[doc = "Bit 1 - Interrupt 33"] #[inline(always)] #[must_use] - pub fn int33(&mut self) -> INT33_W<1> { + pub fn int33(&mut self) -> INT33_W { INT33_W::new(self) } #[doc = "Bit 2 - Interrupt 34"] #[inline(always)] #[must_use] - pub fn int34(&mut self) -> INT34_W<2> { + pub fn int34(&mut self) -> INT34_W { INT34_W::new(self) } #[doc = "Bit 3 - Interrupt 35"] #[inline(always)] #[must_use] - pub fn int35(&mut self) -> INT35_W<3> { + pub fn int35(&mut self) -> INT35_W { INT35_W::new(self) } #[doc = "Bit 4 - Interrupt 36"] #[inline(always)] #[must_use] - pub fn int36(&mut self) -> INT36_W<4> { + pub fn int36(&mut self) -> INT36_W { INT36_W::new(self) } #[doc = "Bit 5 - Interrupt 37"] #[inline(always)] #[must_use] - pub fn int37(&mut self) -> INT37_W<5> { + pub fn int37(&mut self) -> INT37_W { INT37_W::new(self) } #[doc = "Bit 6 - Interrupt 38"] #[inline(always)] #[must_use] - pub fn int38(&mut self) -> INT38_W<6> { + pub fn int38(&mut self) -> INT38_W { INT38_W::new(self) } #[doc = "Bit 7 - Interrupt 39"] #[inline(always)] #[must_use] - pub fn int39(&mut self) -> INT39_W<7> { + pub fn int39(&mut self) -> INT39_W { INT39_W::new(self) } #[doc = "Bit 8 - Interrupt 40"] #[inline(always)] #[must_use] - pub fn int40(&mut self) -> INT40_W<8> { + pub fn int40(&mut self) -> INT40_W { INT40_W::new(self) } #[doc = "Bit 9 - Interrupt 41"] #[inline(always)] #[must_use] - pub fn int41(&mut self) -> INT41_W<9> { + pub fn int41(&mut self) -> INT41_W { INT41_W::new(self) } #[doc = "Bit 10 - Interrupt 42"] #[inline(always)] #[must_use] - pub fn int42(&mut self) -> INT42_W<10> { + pub fn int42(&mut self) -> INT42_W { INT42_W::new(self) } #[doc = "Bit 11 - Interrupt 43"] #[inline(always)] #[must_use] - pub fn int43(&mut self) -> INT43_W<11> { + pub fn int43(&mut self) -> INT43_W { INT43_W::new(self) } #[doc = "Bit 12 - Interrupt 44"] #[inline(always)] #[must_use] - pub fn int44(&mut self) -> INT44_W<12> { + pub fn int44(&mut self) -> INT44_W { INT44_W::new(self) } #[doc = "Bit 13 - Interrupt 45"] #[inline(always)] #[must_use] - pub fn int45(&mut self) -> INT45_W<13> { + pub fn int45(&mut self) -> INT45_W { INT45_W::new(self) } #[doc = "Bit 14 - Interrupt 46"] #[inline(always)] #[must_use] - pub fn int46(&mut self) -> INT46_W<14> { + pub fn int46(&mut self) -> INT46_W { INT46_W::new(self) } #[doc = "Bit 15 - Interrupt 47"] #[inline(always)] #[must_use] - pub fn int47(&mut self) -> INT47_W<15> { + pub fn int47(&mut self) -> INT47_W { INT47_W::new(self) } #[doc = "Bit 16 - Interrupt 48"] #[inline(always)] #[must_use] - pub fn int48(&mut self) -> INT48_W<16> { + pub fn int48(&mut self) -> INT48_W { INT48_W::new(self) } #[doc = "Bit 17 - Interrupt 49"] #[inline(always)] #[must_use] - pub fn int49(&mut self) -> INT49_W<17> { + pub fn int49(&mut self) -> INT49_W { INT49_W::new(self) } #[doc = "Bit 18 - Interrupt 50"] #[inline(always)] #[must_use] - pub fn int50(&mut self) -> INT50_W<18> { + pub fn int50(&mut self) -> INT50_W { INT50_W::new(self) } #[doc = "Bit 19 - Interrupt 51"] #[inline(always)] #[must_use] - pub fn int51(&mut self) -> INT51_W<19> { + pub fn int51(&mut self) -> INT51_W { INT51_W::new(self) } #[doc = "Bit 20 - Interrupt 52"] #[inline(always)] #[must_use] - pub fn int52(&mut self) -> INT52_W<20> { + pub fn int52(&mut self) -> INT52_W { INT52_W::new(self) } #[doc = "Bit 21 - Interrupt 53"] #[inline(always)] #[must_use] - pub fn int53(&mut self) -> INT53_W<21> { + pub fn int53(&mut self) -> INT53_W { INT53_W::new(self) } #[doc = "Bit 22 - Interrupt 54"] #[inline(always)] #[must_use] - pub fn int54(&mut self) -> INT54_W<22> { + pub fn int54(&mut self) -> INT54_W { INT54_W::new(self) } #[doc = "Bit 23 - Interrupt 55"] #[inline(always)] #[must_use] - pub fn int55(&mut self) -> INT55_W<23> { + pub fn int55(&mut self) -> INT55_W { INT55_W::new(self) } #[doc = "Bit 24 - Interrupt 56"] #[inline(always)] #[must_use] - pub fn int56(&mut self) -> INT56_W<24> { + pub fn int56(&mut self) -> INT56_W { INT56_W::new(self) } #[doc = "Bit 25 - Interrupt 57"] #[inline(always)] #[must_use] - pub fn int57(&mut self) -> INT57_W<25> { + pub fn int57(&mut self) -> INT57_W { INT57_W::new(self) } #[doc = "Bit 26 - Interrupt 58"] #[inline(always)] #[must_use] - pub fn int58(&mut self) -> INT58_W<26> { + pub fn int58(&mut self) -> INT58_W { INT58_W::new(self) } #[doc = "Bit 27 - Interrupt 59"] #[inline(always)] #[must_use] - pub fn int59(&mut self) -> INT59_W<27> { + pub fn int59(&mut self) -> INT59_W { INT59_W::new(self) } #[doc = "Bit 28 - Interrupt 60"] #[inline(always)] #[must_use] - pub fn int60(&mut self) -> INT60_W<28> { + pub fn int60(&mut self) -> INT60_W { INT60_W::new(self) } #[doc = "Bit 29 - Interrupt 61"] #[inline(always)] #[must_use] - pub fn int61(&mut self) -> INT61_W<29> { + pub fn int61(&mut self) -> INT61_W { INT61_W::new(self) } #[doc = "Bit 30 - Interrupt 62"] #[inline(always)] #[must_use] - pub fn int62(&mut self) -> INT62_W<30> { + pub fn int62(&mut self) -> INT62_W { INT62_W::new(self) } #[doc = "Bit 31 - Interrupt 63"] #[inline(always)] #[must_use] - pub fn int63(&mut self) -> INT63_W<31> { + pub fn int63(&mut self) -> INT63_W { INT63_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr1](index.html) module"] +#[doc = "Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IGROUPR1_SPEC; impl crate::RegisterSpec for GICD_IGROUPR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_igroupr1::R](R) reader structure"] -impl crate::Readable for GICD_IGROUPR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_igroupr1::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_igroupr1::R`](R) reader structure"] +impl crate::Readable for GICD_IGROUPR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_igroupr1::W`](W) writer structure"] impl crate::Writable for GICD_IGROUPR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr2.rs index b5c50f4..6652c31 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr2.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr2.rs @@ -1,168 +1,135 @@ #[doc = "Register `GICD_IGROUPR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IGROUPR2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI0` reader - Software interrupt 0"] -pub type SWI0_R = crate::BitReader; +pub type SWI0_R = crate::BitReader; #[doc = "Field `SWI0` writer - Software interrupt 0"] -pub type SWI0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type SWI0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI1` reader - Software interrupt 1"] -pub type SWI1_R = crate::BitReader; +pub type SWI1_R = crate::BitReader; #[doc = "Field `SWI1` writer - Software interrupt 1"] -pub type SWI1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type SWI1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI2` reader - Software interrupt 2"] -pub type SWI2_R = crate::BitReader; +pub type SWI2_R = crate::BitReader; #[doc = "Field `SWI2` writer - Software interrupt 2"] -pub type SWI2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type SWI2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI3` reader - Software interrupt 3"] -pub type SWI3_R = crate::BitReader; +pub type SWI3_R = crate::BitReader; #[doc = "Field `SWI3` writer - Software interrupt 3"] -pub type SWI3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type SWI3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI4` reader - Software interrupt 4"] -pub type SWI4_R = crate::BitReader; +pub type SWI4_R = crate::BitReader; #[doc = "Field `SWI4` writer - Software interrupt 4"] -pub type SWI4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type SWI4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI5` reader - Software interrupt 5"] -pub type SWI5_R = crate::BitReader; +pub type SWI5_R = crate::BitReader; #[doc = "Field `SWI5` writer - Software interrupt 5"] -pub type SWI5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type SWI5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI6` reader - Software interrupt 6"] -pub type SWI6_R = crate::BitReader; +pub type SWI6_R = crate::BitReader; #[doc = "Field `SWI6` writer - Software interrupt 6"] -pub type SWI6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type SWI6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI7` reader - Software interrupt 7"] -pub type SWI7_R = crate::BitReader; +pub type SWI7_R = crate::BitReader; #[doc = "Field `SWI7` writer - Software interrupt 7"] -pub type SWI7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type SWI7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT80` reader - Interrupt 80"] -pub type INT80_R = crate::BitReader; +pub type INT80_R = crate::BitReader; #[doc = "Field `INT80` writer - Interrupt 80"] -pub type INT80_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT80_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT81` reader - Interrupt 81"] -pub type INT81_R = crate::BitReader; +pub type INT81_R = crate::BitReader; #[doc = "Field `INT81` writer - Interrupt 81"] -pub type INT81_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT81_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT82` reader - Interrupt 82"] -pub type INT82_R = crate::BitReader; +pub type INT82_R = crate::BitReader; #[doc = "Field `INT82` writer - Interrupt 82"] -pub type INT82_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT82_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT83` reader - Interrupt 83"] -pub type INT83_R = crate::BitReader; +pub type INT83_R = crate::BitReader; #[doc = "Field `INT83` writer - Interrupt 83"] -pub type INT83_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT83_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT84` reader - Interrupt 84"] -pub type INT84_R = crate::BitReader; +pub type INT84_R = crate::BitReader; #[doc = "Field `INT84` writer - Interrupt 84"] -pub type INT84_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT84_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT85` reader - Interrupt 85"] -pub type INT85_R = crate::BitReader; +pub type INT85_R = crate::BitReader; #[doc = "Field `INT85` writer - Interrupt 85"] -pub type INT85_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT85_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT86` reader - Interrupt 86"] -pub type INT86_R = crate::BitReader; +pub type INT86_R = crate::BitReader; #[doc = "Field `INT86` writer - Interrupt 86"] -pub type INT86_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT86_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT87` reader - Interrupt 87"] -pub type INT87_R = crate::BitReader; +pub type INT87_R = crate::BitReader; #[doc = "Field `INT87` writer - Interrupt 87"] -pub type INT87_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT87_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT88` reader - Interrupt 88"] -pub type INT88_R = crate::BitReader; +pub type INT88_R = crate::BitReader; #[doc = "Field `INT88` writer - Interrupt 88"] -pub type INT88_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT88_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT89` reader - Interrupt 89"] -pub type INT89_R = crate::BitReader; +pub type INT89_R = crate::BitReader; #[doc = "Field `INT89` writer - Interrupt 89"] -pub type INT89_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT89_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT90` reader - Interrupt 90"] -pub type INT90_R = crate::BitReader; +pub type INT90_R = crate::BitReader; #[doc = "Field `INT90` writer - Interrupt 90"] -pub type INT90_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT90_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT91` reader - Interrupt 91"] -pub type INT91_R = crate::BitReader; +pub type INT91_R = crate::BitReader; #[doc = "Field `INT91` writer - Interrupt 91"] -pub type INT91_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT91_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT92` reader - Interrupt 92"] -pub type INT92_R = crate::BitReader; +pub type INT92_R = crate::BitReader; #[doc = "Field `INT92` writer - Interrupt 92"] -pub type INT92_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT92_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT93` reader - Interrupt 93"] -pub type INT93_R = crate::BitReader; +pub type INT93_R = crate::BitReader; #[doc = "Field `INT93` writer - Interrupt 93"] -pub type INT93_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT93_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT94` reader - Interrupt 94"] -pub type INT94_R = crate::BitReader; +pub type INT94_R = crate::BitReader; #[doc = "Field `INT94` writer - Interrupt 94"] -pub type INT94_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT94_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT95` reader - Interrupt 95"] -pub type INT95_R = crate::BitReader; +pub type INT95_R = crate::BitReader; #[doc = "Field `INT95` writer - Interrupt 95"] -pub type INT95_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR2_SPEC, bool, O>; +pub type INT95_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -325,218 +292,268 @@ impl R { INT95_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IGROUPR2") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .field("swi0", &format_args!("{}", self.swi0().bit())) + .field("swi1", &format_args!("{}", self.swi1().bit())) + .field("swi2", &format_args!("{}", self.swi2().bit())) + .field("swi3", &format_args!("{}", self.swi3().bit())) + .field("swi4", &format_args!("{}", self.swi4().bit())) + .field("swi5", &format_args!("{}", self.swi5().bit())) + .field("swi6", &format_args!("{}", self.swi6().bit())) + .field("swi7", &format_args!("{}", self.swi7().bit())) + .field("int80", &format_args!("{}", self.int80().bit())) + .field("int81", &format_args!("{}", self.int81().bit())) + .field("int82", &format_args!("{}", self.int82().bit())) + .field("int83", &format_args!("{}", self.int83().bit())) + .field("int84", &format_args!("{}", self.int84().bit())) + .field("int85", &format_args!("{}", self.int85().bit())) + .field("int86", &format_args!("{}", self.int86().bit())) + .field("int87", &format_args!("{}", self.int87().bit())) + .field("int88", &format_args!("{}", self.int88().bit())) + .field("int89", &format_args!("{}", self.int89().bit())) + .field("int90", &format_args!("{}", self.int90().bit())) + .field("int91", &format_args!("{}", self.int91().bit())) + .field("int92", &format_args!("{}", self.int92().bit())) + .field("int93", &format_args!("{}", self.int93().bit())) + .field("int94", &format_args!("{}", self.int94().bit())) + .field("int95", &format_args!("{}", self.int95().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } #[doc = "Bit 8 - Software interrupt 0"] #[inline(always)] #[must_use] - pub fn swi0(&mut self) -> SWI0_W<8> { + pub fn swi0(&mut self) -> SWI0_W { SWI0_W::new(self) } #[doc = "Bit 9 - Software interrupt 1"] #[inline(always)] #[must_use] - pub fn swi1(&mut self) -> SWI1_W<9> { + pub fn swi1(&mut self) -> SWI1_W { SWI1_W::new(self) } #[doc = "Bit 10 - Software interrupt 2"] #[inline(always)] #[must_use] - pub fn swi2(&mut self) -> SWI2_W<10> { + pub fn swi2(&mut self) -> SWI2_W { SWI2_W::new(self) } #[doc = "Bit 11 - Software interrupt 3"] #[inline(always)] #[must_use] - pub fn swi3(&mut self) -> SWI3_W<11> { + pub fn swi3(&mut self) -> SWI3_W { SWI3_W::new(self) } #[doc = "Bit 12 - Software interrupt 4"] #[inline(always)] #[must_use] - pub fn swi4(&mut self) -> SWI4_W<12> { + pub fn swi4(&mut self) -> SWI4_W { SWI4_W::new(self) } #[doc = "Bit 13 - Software interrupt 5"] #[inline(always)] #[must_use] - pub fn swi5(&mut self) -> SWI5_W<13> { + pub fn swi5(&mut self) -> SWI5_W { SWI5_W::new(self) } #[doc = "Bit 14 - Software interrupt 6"] #[inline(always)] #[must_use] - pub fn swi6(&mut self) -> SWI6_W<14> { + pub fn swi6(&mut self) -> SWI6_W { SWI6_W::new(self) } #[doc = "Bit 15 - Software interrupt 7"] #[inline(always)] #[must_use] - pub fn swi7(&mut self) -> SWI7_W<15> { + pub fn swi7(&mut self) -> SWI7_W { SWI7_W::new(self) } #[doc = "Bit 16 - Interrupt 80"] #[inline(always)] #[must_use] - pub fn int80(&mut self) -> INT80_W<16> { + pub fn int80(&mut self) -> INT80_W { INT80_W::new(self) } #[doc = "Bit 17 - Interrupt 81"] #[inline(always)] #[must_use] - pub fn int81(&mut self) -> INT81_W<17> { + pub fn int81(&mut self) -> INT81_W { INT81_W::new(self) } #[doc = "Bit 18 - Interrupt 82"] #[inline(always)] #[must_use] - pub fn int82(&mut self) -> INT82_W<18> { + pub fn int82(&mut self) -> INT82_W { INT82_W::new(self) } #[doc = "Bit 19 - Interrupt 83"] #[inline(always)] #[must_use] - pub fn int83(&mut self) -> INT83_W<19> { + pub fn int83(&mut self) -> INT83_W { INT83_W::new(self) } #[doc = "Bit 20 - Interrupt 84"] #[inline(always)] #[must_use] - pub fn int84(&mut self) -> INT84_W<20> { + pub fn int84(&mut self) -> INT84_W { INT84_W::new(self) } #[doc = "Bit 21 - Interrupt 85"] #[inline(always)] #[must_use] - pub fn int85(&mut self) -> INT85_W<21> { + pub fn int85(&mut self) -> INT85_W { INT85_W::new(self) } #[doc = "Bit 22 - Interrupt 86"] #[inline(always)] #[must_use] - pub fn int86(&mut self) -> INT86_W<22> { + pub fn int86(&mut self) -> INT86_W { INT86_W::new(self) } #[doc = "Bit 23 - Interrupt 87"] #[inline(always)] #[must_use] - pub fn int87(&mut self) -> INT87_W<23> { + pub fn int87(&mut self) -> INT87_W { INT87_W::new(self) } #[doc = "Bit 24 - Interrupt 88"] #[inline(always)] #[must_use] - pub fn int88(&mut self) -> INT88_W<24> { + pub fn int88(&mut self) -> INT88_W { INT88_W::new(self) } #[doc = "Bit 25 - Interrupt 89"] #[inline(always)] #[must_use] - pub fn int89(&mut self) -> INT89_W<25> { + pub fn int89(&mut self) -> INT89_W { INT89_W::new(self) } #[doc = "Bit 26 - Interrupt 90"] #[inline(always)] #[must_use] - pub fn int90(&mut self) -> INT90_W<26> { + pub fn int90(&mut self) -> INT90_W { INT90_W::new(self) } #[doc = "Bit 27 - Interrupt 91"] #[inline(always)] #[must_use] - pub fn int91(&mut self) -> INT91_W<27> { + pub fn int91(&mut self) -> INT91_W { INT91_W::new(self) } #[doc = "Bit 28 - Interrupt 92"] #[inline(always)] #[must_use] - pub fn int92(&mut self) -> INT92_W<28> { + pub fn int92(&mut self) -> INT92_W { INT92_W::new(self) } #[doc = "Bit 29 - Interrupt 93"] #[inline(always)] #[must_use] - pub fn int93(&mut self) -> INT93_W<29> { + pub fn int93(&mut self) -> INT93_W { INT93_W::new(self) } #[doc = "Bit 30 - Interrupt 94"] #[inline(always)] #[must_use] - pub fn int94(&mut self) -> INT94_W<30> { + pub fn int94(&mut self) -> INT94_W { INT94_W::new(self) } #[doc = "Bit 31 - Interrupt 95"] #[inline(always)] #[must_use] - pub fn int95(&mut self) -> INT95_W<31> { + pub fn int95(&mut self) -> INT95_W { INT95_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr2](index.html) module"] +#[doc = "Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IGROUPR2_SPEC; impl crate::RegisterSpec for GICD_IGROUPR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_igroupr2::R](R) reader structure"] -impl crate::Readable for GICD_IGROUPR2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_igroupr2::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_igroupr2::R`](R) reader structure"] +impl crate::Readable for GICD_IGROUPR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_igroupr2::W`](W) writer structure"] impl crate::Writable for GICD_IGROUPR2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr3.rs index 61b2616..742fb7e 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr3.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr3.rs @@ -1,171 +1,135 @@ #[doc = "Register `GICD_IGROUPR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IGROUPR3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR3_SPEC, bool, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -328,218 +292,274 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IGROUPR3") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bit 1 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<1> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bit 2 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<2> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bit 3 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<3> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } #[doc = "Bit 4 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<4> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bit 5 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<5> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bit 6 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<6> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bit 7 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<7> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } #[doc = "Bit 8 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<8> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bit 9 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<9> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 10 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<10> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bit 11 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } #[doc = "Bit 12 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bit 13 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bit 14 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bit 15 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } #[doc = "Bit 16 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<16> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bit 17 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<17> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 18 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<18> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 19 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<19> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 20 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<20> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 21 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<21> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 22 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<22> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 23 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } #[doc = "Bit 24 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bit 25 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<25> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bit 26 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<26> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bit 27 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<27> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } #[doc = "Bit 28 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<28> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<29> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bit 30 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<30> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bit 31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<31> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr3](index.html) module"] +#[doc = "Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IGROUPR3_SPEC; impl crate::RegisterSpec for GICD_IGROUPR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_igroupr3::R](R) reader structure"] -impl crate::Readable for GICD_IGROUPR3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_igroupr3::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_igroupr3::R`](R) reader structure"] +impl crate::Readable for GICD_IGROUPR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_igroupr3::W`](W) writer structure"] impl crate::Writable for GICD_IGROUPR3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr4.rs index f2c5903..399aa88 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr4.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr4.rs @@ -1,169 +1,135 @@ #[doc = "Register `GICD_IGROUPR4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IGROUPR4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type UART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_IGROUPR4_SPEC, bool, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -326,218 +292,280 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IGROUPR4") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bit 1 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<1> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bit 2 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<2> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bit 3 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<3> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } #[doc = "Bit 4 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<4> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bit 5 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bit 6 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bit 7 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } #[doc = "Bit 8 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bit 9 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bit 10 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bit 11 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } #[doc = "Bit 12 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<12> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bit 13 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bit 15 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<15> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } #[doc = "Bit 16 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<16> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bit 17 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bit 18 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bit 19 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } #[doc = "Bit 20 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bit 21 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<21> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bit 22 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<22> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bit 23 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } #[doc = "Bit 24 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<24> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bit 25 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<25> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bit 26 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bit 27 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<27> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } #[doc = "Bit 28 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<28> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bit 29 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<29> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bit 30 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<30> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bit 31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr4](index.html) module"] +#[doc = "Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IGROUPR4_SPEC; impl crate::RegisterSpec for GICD_IGROUPR4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_igroupr4::R](R) reader structure"] -impl crate::Readable for GICD_IGROUPR4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_igroupr4::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_igroupr4::R`](R) reader structure"] +impl crate::Readable for GICD_IGROUPR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_igroupr4::W`](W) writer structure"] impl crate::Writable for GICD_IGROUPR4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr5.rs index 1a56750..db16be6 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr5.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr5.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_IGROUPR5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IGROUPR5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT160` reader - Interrupt 160"] -pub type INT160_R = crate::BitReader; +pub type INT160_R = crate::BitReader; #[doc = "Field `INT160` writer - Interrupt 160"] -pub type INT160_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT160_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT161` reader - Interrupt 161"] -pub type INT161_R = crate::BitReader; +pub type INT161_R = crate::BitReader; #[doc = "Field `INT161` writer - Interrupt 161"] -pub type INT161_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT161_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT162` reader - Interrupt 162"] -pub type INT162_R = crate::BitReader; +pub type INT162_R = crate::BitReader; #[doc = "Field `INT162` writer - Interrupt 162"] -pub type INT162_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT162_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT163` reader - Interrupt 163"] -pub type INT163_R = crate::BitReader; +pub type INT163_R = crate::BitReader; #[doc = "Field `INT163` writer - Interrupt 163"] -pub type INT163_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT163_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT164` reader - Interrupt 164"] -pub type INT164_R = crate::BitReader; +pub type INT164_R = crate::BitReader; #[doc = "Field `INT164` writer - Interrupt 164"] -pub type INT164_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT164_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT165` reader - Interrupt 165"] -pub type INT165_R = crate::BitReader; +pub type INT165_R = crate::BitReader; #[doc = "Field `INT165` writer - Interrupt 165"] -pub type INT165_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT165_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT166` reader - Interrupt 166"] -pub type INT166_R = crate::BitReader; +pub type INT166_R = crate::BitReader; #[doc = "Field `INT166` writer - Interrupt 166"] -pub type INT166_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT166_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT167` reader - Interrupt 167"] -pub type INT167_R = crate::BitReader; +pub type INT167_R = crate::BitReader; #[doc = "Field `INT167` writer - Interrupt 167"] -pub type INT167_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT167_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT168` reader - Interrupt 168"] -pub type INT168_R = crate::BitReader; +pub type INT168_R = crate::BitReader; #[doc = "Field `INT168` writer - Interrupt 168"] -pub type INT168_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT168_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT169` reader - Interrupt 169"] -pub type INT169_R = crate::BitReader; +pub type INT169_R = crate::BitReader; #[doc = "Field `INT169` writer - Interrupt 169"] -pub type INT169_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT169_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT170` reader - Interrupt 170"] -pub type INT170_R = crate::BitReader; +pub type INT170_R = crate::BitReader; #[doc = "Field `INT170` writer - Interrupt 170"] -pub type INT170_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT170_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT171` reader - Interrupt 171"] -pub type INT171_R = crate::BitReader; +pub type INT171_R = crate::BitReader; #[doc = "Field `INT171` writer - Interrupt 171"] -pub type INT171_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT171_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT172` reader - Interrupt 172"] -pub type INT172_R = crate::BitReader; +pub type INT172_R = crate::BitReader; #[doc = "Field `INT172` writer - Interrupt 172"] -pub type INT172_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT172_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT173` reader - Interrupt 173"] -pub type INT173_R = crate::BitReader; +pub type INT173_R = crate::BitReader; #[doc = "Field `INT173` writer - Interrupt 173"] -pub type INT173_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT173_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT174` reader - Interrupt 174"] -pub type INT174_R = crate::BitReader; +pub type INT174_R = crate::BitReader; #[doc = "Field `INT174` writer - Interrupt 174"] -pub type INT174_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT174_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT175` reader - Interrupt 175"] -pub type INT175_R = crate::BitReader; +pub type INT175_R = crate::BitReader; #[doc = "Field `INT175` writer - Interrupt 175"] -pub type INT175_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT175_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT176` reader - Interrupt 176"] -pub type INT176_R = crate::BitReader; +pub type INT176_R = crate::BitReader; #[doc = "Field `INT176` writer - Interrupt 176"] -pub type INT176_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT176_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT177` reader - Interrupt 177"] -pub type INT177_R = crate::BitReader; +pub type INT177_R = crate::BitReader; #[doc = "Field `INT177` writer - Interrupt 177"] -pub type INT177_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT177_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT178` reader - Interrupt 178"] -pub type INT178_R = crate::BitReader; +pub type INT178_R = crate::BitReader; #[doc = "Field `INT178` writer - Interrupt 178"] -pub type INT178_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT178_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT179` reader - Interrupt 179"] -pub type INT179_R = crate::BitReader; +pub type INT179_R = crate::BitReader; #[doc = "Field `INT179` writer - Interrupt 179"] -pub type INT179_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT179_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT180` reader - Interrupt 180"] -pub type INT180_R = crate::BitReader; +pub type INT180_R = crate::BitReader; #[doc = "Field `INT180` writer - Interrupt 180"] -pub type INT180_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT180_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT181` reader - Interrupt 181"] -pub type INT181_R = crate::BitReader; +pub type INT181_R = crate::BitReader; #[doc = "Field `INT181` writer - Interrupt 181"] -pub type INT181_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT181_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT182` reader - Interrupt 182"] -pub type INT182_R = crate::BitReader; +pub type INT182_R = crate::BitReader; #[doc = "Field `INT182` writer - Interrupt 182"] -pub type INT182_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT182_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT183` reader - Interrupt 183"] -pub type INT183_R = crate::BitReader; +pub type INT183_R = crate::BitReader; #[doc = "Field `INT183` writer - Interrupt 183"] -pub type INT183_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT183_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT184` reader - Interrupt 184"] -pub type INT184_R = crate::BitReader; +pub type INT184_R = crate::BitReader; #[doc = "Field `INT184` writer - Interrupt 184"] -pub type INT184_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT184_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT185` reader - Interrupt 185"] -pub type INT185_R = crate::BitReader; +pub type INT185_R = crate::BitReader; #[doc = "Field `INT185` writer - Interrupt 185"] -pub type INT185_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT185_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT186` reader - Interrupt 186"] -pub type INT186_R = crate::BitReader; +pub type INT186_R = crate::BitReader; #[doc = "Field `INT186` writer - Interrupt 186"] -pub type INT186_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT186_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT187` reader - Interrupt 187"] -pub type INT187_R = crate::BitReader; +pub type INT187_R = crate::BitReader; #[doc = "Field `INT187` writer - Interrupt 187"] -pub type INT187_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT187_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT188` reader - Interrupt 188"] -pub type INT188_R = crate::BitReader; +pub type INT188_R = crate::BitReader; #[doc = "Field `INT188` writer - Interrupt 188"] -pub type INT188_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT188_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT189` reader - Interrupt 189"] -pub type INT189_R = crate::BitReader; +pub type INT189_R = crate::BitReader; #[doc = "Field `INT189` writer - Interrupt 189"] -pub type INT189_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT189_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT190` reader - Interrupt 190"] -pub type INT190_R = crate::BitReader; +pub type INT190_R = crate::BitReader; #[doc = "Field `INT190` writer - Interrupt 190"] -pub type INT190_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT190_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT191` reader - Interrupt 191"] -pub type INT191_R = crate::BitReader; +pub type INT191_R = crate::BitReader; #[doc = "Field `INT191` writer - Interrupt 191"] -pub type INT191_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR5_SPEC, bool, O>; +pub type INT191_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT191_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IGROUPR5") + .field("int160", &format_args!("{}", self.int160().bit())) + .field("int161", &format_args!("{}", self.int161().bit())) + .field("int162", &format_args!("{}", self.int162().bit())) + .field("int163", &format_args!("{}", self.int163().bit())) + .field("int164", &format_args!("{}", self.int164().bit())) + .field("int165", &format_args!("{}", self.int165().bit())) + .field("int166", &format_args!("{}", self.int166().bit())) + .field("int167", &format_args!("{}", self.int167().bit())) + .field("int168", &format_args!("{}", self.int168().bit())) + .field("int169", &format_args!("{}", self.int169().bit())) + .field("int170", &format_args!("{}", self.int170().bit())) + .field("int171", &format_args!("{}", self.int171().bit())) + .field("int172", &format_args!("{}", self.int172().bit())) + .field("int173", &format_args!("{}", self.int173().bit())) + .field("int174", &format_args!("{}", self.int174().bit())) + .field("int175", &format_args!("{}", self.int175().bit())) + .field("int176", &format_args!("{}", self.int176().bit())) + .field("int177", &format_args!("{}", self.int177().bit())) + .field("int178", &format_args!("{}", self.int178().bit())) + .field("int179", &format_args!("{}", self.int179().bit())) + .field("int180", &format_args!("{}", self.int180().bit())) + .field("int181", &format_args!("{}", self.int181().bit())) + .field("int182", &format_args!("{}", self.int182().bit())) + .field("int183", &format_args!("{}", self.int183().bit())) + .field("int184", &format_args!("{}", self.int184().bit())) + .field("int185", &format_args!("{}", self.int185().bit())) + .field("int186", &format_args!("{}", self.int186().bit())) + .field("int187", &format_args!("{}", self.int187().bit())) + .field("int188", &format_args!("{}", self.int188().bit())) + .field("int189", &format_args!("{}", self.int189().bit())) + .field("int190", &format_args!("{}", self.int190().bit())) + .field("int191", &format_args!("{}", self.int191().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] #[must_use] - pub fn int160(&mut self) -> INT160_W<0> { + pub fn int160(&mut self) -> INT160_W { INT160_W::new(self) } #[doc = "Bit 1 - Interrupt 161"] #[inline(always)] #[must_use] - pub fn int161(&mut self) -> INT161_W<1> { + pub fn int161(&mut self) -> INT161_W { INT161_W::new(self) } #[doc = "Bit 2 - Interrupt 162"] #[inline(always)] #[must_use] - pub fn int162(&mut self) -> INT162_W<2> { + pub fn int162(&mut self) -> INT162_W { INT162_W::new(self) } #[doc = "Bit 3 - Interrupt 163"] #[inline(always)] #[must_use] - pub fn int163(&mut self) -> INT163_W<3> { + pub fn int163(&mut self) -> INT163_W { INT163_W::new(self) } #[doc = "Bit 4 - Interrupt 164"] #[inline(always)] #[must_use] - pub fn int164(&mut self) -> INT164_W<4> { + pub fn int164(&mut self) -> INT164_W { INT164_W::new(self) } #[doc = "Bit 5 - Interrupt 165"] #[inline(always)] #[must_use] - pub fn int165(&mut self) -> INT165_W<5> { + pub fn int165(&mut self) -> INT165_W { INT165_W::new(self) } #[doc = "Bit 6 - Interrupt 166"] #[inline(always)] #[must_use] - pub fn int166(&mut self) -> INT166_W<6> { + pub fn int166(&mut self) -> INT166_W { INT166_W::new(self) } #[doc = "Bit 7 - Interrupt 167"] #[inline(always)] #[must_use] - pub fn int167(&mut self) -> INT167_W<7> { + pub fn int167(&mut self) -> INT167_W { INT167_W::new(self) } #[doc = "Bit 8 - Interrupt 168"] #[inline(always)] #[must_use] - pub fn int168(&mut self) -> INT168_W<8> { + pub fn int168(&mut self) -> INT168_W { INT168_W::new(self) } #[doc = "Bit 9 - Interrupt 169"] #[inline(always)] #[must_use] - pub fn int169(&mut self) -> INT169_W<9> { + pub fn int169(&mut self) -> INT169_W { INT169_W::new(self) } #[doc = "Bit 10 - Interrupt 170"] #[inline(always)] #[must_use] - pub fn int170(&mut self) -> INT170_W<10> { + pub fn int170(&mut self) -> INT170_W { INT170_W::new(self) } #[doc = "Bit 11 - Interrupt 171"] #[inline(always)] #[must_use] - pub fn int171(&mut self) -> INT171_W<11> { + pub fn int171(&mut self) -> INT171_W { INT171_W::new(self) } #[doc = "Bit 12 - Interrupt 172"] #[inline(always)] #[must_use] - pub fn int172(&mut self) -> INT172_W<12> { + pub fn int172(&mut self) -> INT172_W { INT172_W::new(self) } #[doc = "Bit 13 - Interrupt 173"] #[inline(always)] #[must_use] - pub fn int173(&mut self) -> INT173_W<13> { + pub fn int173(&mut self) -> INT173_W { INT173_W::new(self) } #[doc = "Bit 14 - Interrupt 174"] #[inline(always)] #[must_use] - pub fn int174(&mut self) -> INT174_W<14> { + pub fn int174(&mut self) -> INT174_W { INT174_W::new(self) } #[doc = "Bit 15 - Interrupt 175"] #[inline(always)] #[must_use] - pub fn int175(&mut self) -> INT175_W<15> { + pub fn int175(&mut self) -> INT175_W { INT175_W::new(self) } #[doc = "Bit 16 - Interrupt 176"] #[inline(always)] #[must_use] - pub fn int176(&mut self) -> INT176_W<16> { + pub fn int176(&mut self) -> INT176_W { INT176_W::new(self) } #[doc = "Bit 17 - Interrupt 177"] #[inline(always)] #[must_use] - pub fn int177(&mut self) -> INT177_W<17> { + pub fn int177(&mut self) -> INT177_W { INT177_W::new(self) } #[doc = "Bit 18 - Interrupt 178"] #[inline(always)] #[must_use] - pub fn int178(&mut self) -> INT178_W<18> { + pub fn int178(&mut self) -> INT178_W { INT178_W::new(self) } #[doc = "Bit 19 - Interrupt 179"] #[inline(always)] #[must_use] - pub fn int179(&mut self) -> INT179_W<19> { + pub fn int179(&mut self) -> INT179_W { INT179_W::new(self) } #[doc = "Bit 20 - Interrupt 180"] #[inline(always)] #[must_use] - pub fn int180(&mut self) -> INT180_W<20> { + pub fn int180(&mut self) -> INT180_W { INT180_W::new(self) } #[doc = "Bit 21 - Interrupt 181"] #[inline(always)] #[must_use] - pub fn int181(&mut self) -> INT181_W<21> { + pub fn int181(&mut self) -> INT181_W { INT181_W::new(self) } #[doc = "Bit 22 - Interrupt 182"] #[inline(always)] #[must_use] - pub fn int182(&mut self) -> INT182_W<22> { + pub fn int182(&mut self) -> INT182_W { INT182_W::new(self) } #[doc = "Bit 23 - Interrupt 183"] #[inline(always)] #[must_use] - pub fn int183(&mut self) -> INT183_W<23> { + pub fn int183(&mut self) -> INT183_W { INT183_W::new(self) } #[doc = "Bit 24 - Interrupt 184"] #[inline(always)] #[must_use] - pub fn int184(&mut self) -> INT184_W<24> { + pub fn int184(&mut self) -> INT184_W { INT184_W::new(self) } #[doc = "Bit 25 - Interrupt 185"] #[inline(always)] #[must_use] - pub fn int185(&mut self) -> INT185_W<25> { + pub fn int185(&mut self) -> INT185_W { INT185_W::new(self) } #[doc = "Bit 26 - Interrupt 186"] #[inline(always)] #[must_use] - pub fn int186(&mut self) -> INT186_W<26> { + pub fn int186(&mut self) -> INT186_W { INT186_W::new(self) } #[doc = "Bit 27 - Interrupt 187"] #[inline(always)] #[must_use] - pub fn int187(&mut self) -> INT187_W<27> { + pub fn int187(&mut self) -> INT187_W { INT187_W::new(self) } #[doc = "Bit 28 - Interrupt 188"] #[inline(always)] #[must_use] - pub fn int188(&mut self) -> INT188_W<28> { + pub fn int188(&mut self) -> INT188_W { INT188_W::new(self) } #[doc = "Bit 29 - Interrupt 189"] #[inline(always)] #[must_use] - pub fn int189(&mut self) -> INT189_W<29> { + pub fn int189(&mut self) -> INT189_W { INT189_W::new(self) } #[doc = "Bit 30 - Interrupt 190"] #[inline(always)] #[must_use] - pub fn int190(&mut self) -> INT190_W<30> { + pub fn int190(&mut self) -> INT190_W { INT190_W::new(self) } #[doc = "Bit 31 - Interrupt 191"] #[inline(always)] #[must_use] - pub fn int191(&mut self) -> INT191_W<31> { + pub fn int191(&mut self) -> INT191_W { INT191_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr5](index.html) module"] +#[doc = "Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IGROUPR5_SPEC; impl crate::RegisterSpec for GICD_IGROUPR5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_igroupr5::R](R) reader structure"] -impl crate::Readable for GICD_IGROUPR5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_igroupr5::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_igroupr5::R`](R) reader structure"] +impl crate::Readable for GICD_IGROUPR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_igroupr5::W`](W) writer structure"] impl crate::Writable for GICD_IGROUPR5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr6.rs index 093bad3..7c7e098 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr6.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_igroupr/gicd_igroupr6.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_IGROUPR6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IGROUPR6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT192` reader - Interrupt 192"] -pub type INT192_R = crate::BitReader; +pub type INT192_R = crate::BitReader; #[doc = "Field `INT192` writer - Interrupt 192"] -pub type INT192_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT192_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT193` reader - Interrupt 193"] -pub type INT193_R = crate::BitReader; +pub type INT193_R = crate::BitReader; #[doc = "Field `INT193` writer - Interrupt 193"] -pub type INT193_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT193_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT194` reader - Interrupt 194"] -pub type INT194_R = crate::BitReader; +pub type INT194_R = crate::BitReader; #[doc = "Field `INT194` writer - Interrupt 194"] -pub type INT194_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT194_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT195` reader - Interrupt 195"] -pub type INT195_R = crate::BitReader; +pub type INT195_R = crate::BitReader; #[doc = "Field `INT195` writer - Interrupt 195"] -pub type INT195_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT195_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT196` reader - Interrupt 196"] -pub type INT196_R = crate::BitReader; +pub type INT196_R = crate::BitReader; #[doc = "Field `INT196` writer - Interrupt 196"] -pub type INT196_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT196_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT197` reader - Interrupt 197"] -pub type INT197_R = crate::BitReader; +pub type INT197_R = crate::BitReader; #[doc = "Field `INT197` writer - Interrupt 197"] -pub type INT197_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT197_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT198` reader - Interrupt 198"] -pub type INT198_R = crate::BitReader; +pub type INT198_R = crate::BitReader; #[doc = "Field `INT198` writer - Interrupt 198"] -pub type INT198_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT198_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT199` reader - Interrupt 199"] -pub type INT199_R = crate::BitReader; +pub type INT199_R = crate::BitReader; #[doc = "Field `INT199` writer - Interrupt 199"] -pub type INT199_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT199_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT200` reader - Interrupt 200"] -pub type INT200_R = crate::BitReader; +pub type INT200_R = crate::BitReader; #[doc = "Field `INT200` writer - Interrupt 200"] -pub type INT200_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT200_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT201` reader - Interrupt 201"] -pub type INT201_R = crate::BitReader; +pub type INT201_R = crate::BitReader; #[doc = "Field `INT201` writer - Interrupt 201"] -pub type INT201_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT201_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT202` reader - Interrupt 202"] -pub type INT202_R = crate::BitReader; +pub type INT202_R = crate::BitReader; #[doc = "Field `INT202` writer - Interrupt 202"] -pub type INT202_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT202_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT203` reader - Interrupt 203"] -pub type INT203_R = crate::BitReader; +pub type INT203_R = crate::BitReader; #[doc = "Field `INT203` writer - Interrupt 203"] -pub type INT203_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT203_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT204` reader - Interrupt 204"] -pub type INT204_R = crate::BitReader; +pub type INT204_R = crate::BitReader; #[doc = "Field `INT204` writer - Interrupt 204"] -pub type INT204_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT204_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT205` reader - Interrupt 205"] -pub type INT205_R = crate::BitReader; +pub type INT205_R = crate::BitReader; #[doc = "Field `INT205` writer - Interrupt 205"] -pub type INT205_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT205_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT206` reader - Interrupt 206"] -pub type INT206_R = crate::BitReader; +pub type INT206_R = crate::BitReader; #[doc = "Field `INT206` writer - Interrupt 206"] -pub type INT206_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT206_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT207` reader - Interrupt 207"] -pub type INT207_R = crate::BitReader; +pub type INT207_R = crate::BitReader; #[doc = "Field `INT207` writer - Interrupt 207"] -pub type INT207_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT207_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT208` reader - Interrupt 208"] -pub type INT208_R = crate::BitReader; +pub type INT208_R = crate::BitReader; #[doc = "Field `INT208` writer - Interrupt 208"] -pub type INT208_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT208_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT209` reader - Interrupt 209"] -pub type INT209_R = crate::BitReader; +pub type INT209_R = crate::BitReader; #[doc = "Field `INT209` writer - Interrupt 209"] -pub type INT209_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT209_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT210` reader - Interrupt 210"] -pub type INT210_R = crate::BitReader; +pub type INT210_R = crate::BitReader; #[doc = "Field `INT210` writer - Interrupt 210"] -pub type INT210_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT210_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT211` reader - Interrupt 211"] -pub type INT211_R = crate::BitReader; +pub type INT211_R = crate::BitReader; #[doc = "Field `INT211` writer - Interrupt 211"] -pub type INT211_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT211_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT212` reader - Interrupt 212"] -pub type INT212_R = crate::BitReader; +pub type INT212_R = crate::BitReader; #[doc = "Field `INT212` writer - Interrupt 212"] -pub type INT212_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT212_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT213` reader - Interrupt 213"] -pub type INT213_R = crate::BitReader; +pub type INT213_R = crate::BitReader; #[doc = "Field `INT213` writer - Interrupt 213"] -pub type INT213_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT213_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT214` reader - Interrupt 214"] -pub type INT214_R = crate::BitReader; +pub type INT214_R = crate::BitReader; #[doc = "Field `INT214` writer - Interrupt 214"] -pub type INT214_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT214_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT215` reader - Interrupt 215"] -pub type INT215_R = crate::BitReader; +pub type INT215_R = crate::BitReader; #[doc = "Field `INT215` writer - Interrupt 215"] -pub type INT215_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT215_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT216` reader - Interrupt 216"] -pub type INT216_R = crate::BitReader; +pub type INT216_R = crate::BitReader; #[doc = "Field `INT216` writer - Interrupt 216"] -pub type INT216_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT216_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT217` reader - Interrupt 217"] -pub type INT217_R = crate::BitReader; +pub type INT217_R = crate::BitReader; #[doc = "Field `INT217` writer - Interrupt 217"] -pub type INT217_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT217_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT218` reader - Interrupt 218"] -pub type INT218_R = crate::BitReader; +pub type INT218_R = crate::BitReader; #[doc = "Field `INT218` writer - Interrupt 218"] -pub type INT218_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT218_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT219` reader - Interrupt 219"] -pub type INT219_R = crate::BitReader; +pub type INT219_R = crate::BitReader; #[doc = "Field `INT219` writer - Interrupt 219"] -pub type INT219_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT219_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT220` reader - Interrupt 220"] -pub type INT220_R = crate::BitReader; +pub type INT220_R = crate::BitReader; #[doc = "Field `INT220` writer - Interrupt 220"] -pub type INT220_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT220_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT221` reader - Interrupt 221"] -pub type INT221_R = crate::BitReader; +pub type INT221_R = crate::BitReader; #[doc = "Field `INT221` writer - Interrupt 221"] -pub type INT221_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT221_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT222` reader - Interrupt 222"] -pub type INT222_R = crate::BitReader; +pub type INT222_R = crate::BitReader; #[doc = "Field `INT222` writer - Interrupt 222"] -pub type INT222_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT222_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INT223` reader - Interrupt 223"] -pub type INT223_R = crate::BitReader; +pub type INT223_R = crate::BitReader; #[doc = "Field `INT223` writer - Interrupt 223"] -pub type INT223_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_IGROUPR6_SPEC, bool, O>; +pub type INT223_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT223_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IGROUPR6") + .field("int192", &format_args!("{}", self.int192().bit())) + .field("int193", &format_args!("{}", self.int193().bit())) + .field("int194", &format_args!("{}", self.int194().bit())) + .field("int195", &format_args!("{}", self.int195().bit())) + .field("int196", &format_args!("{}", self.int196().bit())) + .field("int197", &format_args!("{}", self.int197().bit())) + .field("int198", &format_args!("{}", self.int198().bit())) + .field("int199", &format_args!("{}", self.int199().bit())) + .field("int200", &format_args!("{}", self.int200().bit())) + .field("int201", &format_args!("{}", self.int201().bit())) + .field("int202", &format_args!("{}", self.int202().bit())) + .field("int203", &format_args!("{}", self.int203().bit())) + .field("int204", &format_args!("{}", self.int204().bit())) + .field("int205", &format_args!("{}", self.int205().bit())) + .field("int206", &format_args!("{}", self.int206().bit())) + .field("int207", &format_args!("{}", self.int207().bit())) + .field("int208", &format_args!("{}", self.int208().bit())) + .field("int209", &format_args!("{}", self.int209().bit())) + .field("int210", &format_args!("{}", self.int210().bit())) + .field("int211", &format_args!("{}", self.int211().bit())) + .field("int212", &format_args!("{}", self.int212().bit())) + .field("int213", &format_args!("{}", self.int213().bit())) + .field("int214", &format_args!("{}", self.int214().bit())) + .field("int215", &format_args!("{}", self.int215().bit())) + .field("int216", &format_args!("{}", self.int216().bit())) + .field("int217", &format_args!("{}", self.int217().bit())) + .field("int218", &format_args!("{}", self.int218().bit())) + .field("int219", &format_args!("{}", self.int219().bit())) + .field("int220", &format_args!("{}", self.int220().bit())) + .field("int221", &format_args!("{}", self.int221().bit())) + .field("int222", &format_args!("{}", self.int222().bit())) + .field("int223", &format_args!("{}", self.int223().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] #[must_use] - pub fn int192(&mut self) -> INT192_W<0> { + pub fn int192(&mut self) -> INT192_W { INT192_W::new(self) } #[doc = "Bit 1 - Interrupt 193"] #[inline(always)] #[must_use] - pub fn int193(&mut self) -> INT193_W<1> { + pub fn int193(&mut self) -> INT193_W { INT193_W::new(self) } #[doc = "Bit 2 - Interrupt 194"] #[inline(always)] #[must_use] - pub fn int194(&mut self) -> INT194_W<2> { + pub fn int194(&mut self) -> INT194_W { INT194_W::new(self) } #[doc = "Bit 3 - Interrupt 195"] #[inline(always)] #[must_use] - pub fn int195(&mut self) -> INT195_W<3> { + pub fn int195(&mut self) -> INT195_W { INT195_W::new(self) } #[doc = "Bit 4 - Interrupt 196"] #[inline(always)] #[must_use] - pub fn int196(&mut self) -> INT196_W<4> { + pub fn int196(&mut self) -> INT196_W { INT196_W::new(self) } #[doc = "Bit 5 - Interrupt 197"] #[inline(always)] #[must_use] - pub fn int197(&mut self) -> INT197_W<5> { + pub fn int197(&mut self) -> INT197_W { INT197_W::new(self) } #[doc = "Bit 6 - Interrupt 198"] #[inline(always)] #[must_use] - pub fn int198(&mut self) -> INT198_W<6> { + pub fn int198(&mut self) -> INT198_W { INT198_W::new(self) } #[doc = "Bit 7 - Interrupt 199"] #[inline(always)] #[must_use] - pub fn int199(&mut self) -> INT199_W<7> { + pub fn int199(&mut self) -> INT199_W { INT199_W::new(self) } #[doc = "Bit 8 - Interrupt 200"] #[inline(always)] #[must_use] - pub fn int200(&mut self) -> INT200_W<8> { + pub fn int200(&mut self) -> INT200_W { INT200_W::new(self) } #[doc = "Bit 9 - Interrupt 201"] #[inline(always)] #[must_use] - pub fn int201(&mut self) -> INT201_W<9> { + pub fn int201(&mut self) -> INT201_W { INT201_W::new(self) } #[doc = "Bit 10 - Interrupt 202"] #[inline(always)] #[must_use] - pub fn int202(&mut self) -> INT202_W<10> { + pub fn int202(&mut self) -> INT202_W { INT202_W::new(self) } #[doc = "Bit 11 - Interrupt 203"] #[inline(always)] #[must_use] - pub fn int203(&mut self) -> INT203_W<11> { + pub fn int203(&mut self) -> INT203_W { INT203_W::new(self) } #[doc = "Bit 12 - Interrupt 204"] #[inline(always)] #[must_use] - pub fn int204(&mut self) -> INT204_W<12> { + pub fn int204(&mut self) -> INT204_W { INT204_W::new(self) } #[doc = "Bit 13 - Interrupt 205"] #[inline(always)] #[must_use] - pub fn int205(&mut self) -> INT205_W<13> { + pub fn int205(&mut self) -> INT205_W { INT205_W::new(self) } #[doc = "Bit 14 - Interrupt 206"] #[inline(always)] #[must_use] - pub fn int206(&mut self) -> INT206_W<14> { + pub fn int206(&mut self) -> INT206_W { INT206_W::new(self) } #[doc = "Bit 15 - Interrupt 207"] #[inline(always)] #[must_use] - pub fn int207(&mut self) -> INT207_W<15> { + pub fn int207(&mut self) -> INT207_W { INT207_W::new(self) } #[doc = "Bit 16 - Interrupt 208"] #[inline(always)] #[must_use] - pub fn int208(&mut self) -> INT208_W<16> { + pub fn int208(&mut self) -> INT208_W { INT208_W::new(self) } #[doc = "Bit 17 - Interrupt 209"] #[inline(always)] #[must_use] - pub fn int209(&mut self) -> INT209_W<17> { + pub fn int209(&mut self) -> INT209_W { INT209_W::new(self) } #[doc = "Bit 18 - Interrupt 210"] #[inline(always)] #[must_use] - pub fn int210(&mut self) -> INT210_W<18> { + pub fn int210(&mut self) -> INT210_W { INT210_W::new(self) } #[doc = "Bit 19 - Interrupt 211"] #[inline(always)] #[must_use] - pub fn int211(&mut self) -> INT211_W<19> { + pub fn int211(&mut self) -> INT211_W { INT211_W::new(self) } #[doc = "Bit 20 - Interrupt 212"] #[inline(always)] #[must_use] - pub fn int212(&mut self) -> INT212_W<20> { + pub fn int212(&mut self) -> INT212_W { INT212_W::new(self) } #[doc = "Bit 21 - Interrupt 213"] #[inline(always)] #[must_use] - pub fn int213(&mut self) -> INT213_W<21> { + pub fn int213(&mut self) -> INT213_W { INT213_W::new(self) } #[doc = "Bit 22 - Interrupt 214"] #[inline(always)] #[must_use] - pub fn int214(&mut self) -> INT214_W<22> { + pub fn int214(&mut self) -> INT214_W { INT214_W::new(self) } #[doc = "Bit 23 - Interrupt 215"] #[inline(always)] #[must_use] - pub fn int215(&mut self) -> INT215_W<23> { + pub fn int215(&mut self) -> INT215_W { INT215_W::new(self) } #[doc = "Bit 24 - Interrupt 216"] #[inline(always)] #[must_use] - pub fn int216(&mut self) -> INT216_W<24> { + pub fn int216(&mut self) -> INT216_W { INT216_W::new(self) } #[doc = "Bit 25 - Interrupt 217"] #[inline(always)] #[must_use] - pub fn int217(&mut self) -> INT217_W<25> { + pub fn int217(&mut self) -> INT217_W { INT217_W::new(self) } #[doc = "Bit 26 - Interrupt 218"] #[inline(always)] #[must_use] - pub fn int218(&mut self) -> INT218_W<26> { + pub fn int218(&mut self) -> INT218_W { INT218_W::new(self) } #[doc = "Bit 27 - Interrupt 219"] #[inline(always)] #[must_use] - pub fn int219(&mut self) -> INT219_W<27> { + pub fn int219(&mut self) -> INT219_W { INT219_W::new(self) } #[doc = "Bit 28 - Interrupt 220"] #[inline(always)] #[must_use] - pub fn int220(&mut self) -> INT220_W<28> { + pub fn int220(&mut self) -> INT220_W { INT220_W::new(self) } #[doc = "Bit 29 - Interrupt 221"] #[inline(always)] #[must_use] - pub fn int221(&mut self) -> INT221_W<29> { + pub fn int221(&mut self) -> INT221_W { INT221_W::new(self) } #[doc = "Bit 30 - Interrupt 222"] #[inline(always)] #[must_use] - pub fn int222(&mut self) -> INT222_W<30> { + pub fn int222(&mut self) -> INT222_W { INT222_W::new(self) } #[doc = "Bit 31 - Interrupt 223"] #[inline(always)] #[must_use] - pub fn int223(&mut self) -> INT223_W<31> { + pub fn int223(&mut self) -> INT223_W { INT223_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Group\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_igroupr6](index.html) module"] +#[doc = "Interrupt Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_igroupr6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_igroupr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IGROUPR6_SPEC; impl crate::RegisterSpec for GICD_IGROUPR6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_igroupr6::R](R) reader structure"] -impl crate::Readable for GICD_IGROUPR6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_igroupr6::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_igroupr6::R`](R) reader structure"] +impl crate::Readable for GICD_IGROUPR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_igroupr6::W`](W) writer structure"] impl crate::Writable for GICD_IGROUPR6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_iidr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_iidr.rs index 681069e..6aa681e 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_iidr.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_iidr.rs @@ -1,26 +1,13 @@ #[doc = "Register `GICD_IIDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `IMPLEMENTER` reader - Implementer"] -pub type IMPLEMENTER_R = crate::FieldReader; +pub type IMPLEMENTER_R = crate::FieldReader; #[doc = "Field `REVISION` reader - Revision"] -pub type REVISION_R = crate::FieldReader; +pub type REVISION_R = crate::FieldReader; #[doc = "Field `VARIANT` reader - Variant"] -pub type VARIANT_R = crate::FieldReader; +pub type VARIANT_R = crate::FieldReader; #[doc = "Field `PRODUCT_ID` reader - Product ID"] -pub type PRODUCT_ID_R = crate::FieldReader; +pub type PRODUCT_ID_R = crate::FieldReader; impl R { #[doc = "Bits 0:11 - Implementer"] #[inline(always)] @@ -43,15 +30,31 @@ impl R { PRODUCT_ID_R::new(((self.bits >> 24) & 0xff) as u8) } } -#[doc = "Distributor Implementer Identification Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_iidr](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IIDR") + .field("product_id", &format_args!("{}", self.product_id().bits())) + .field("variant", &format_args!("{}", self.variant().bits())) + .field("revision", &format_args!("{}", self.revision().bits())) + .field( + "implementer", + &format_args!("{}", self.implementer().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Distributor Implementer Identification Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_iidr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IIDR_SPEC; impl crate::RegisterSpec for GICD_IIDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_iidr::R](R) reader structure"] -impl crate::Readable for GICD_IIDR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_iidr::R`](R) reader structure"] +impl crate::Readable for GICD_IIDR_SPEC {} #[doc = "`reset()` method sets GICD_IIDR to value 0x0200_143b"] impl crate::Resettable for GICD_IIDR_SPEC { const RESET_VALUE: Self::Ux = 0x0200_143b; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr.rs index 85468af..e0b5a9a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct GICD_IPRIORITYR { #[doc = "0x00 - Interrupt Priority 0 - 3 (Lower is first)"] pub gicd_ipriorityr0: GICD_IPRIORITYR0, @@ -114,227 +115,283 @@ pub struct GICD_IPRIORITYR { #[doc = "0xdc - Interrupt Priority 220 - 223 (Lower is first)"] pub gicd_ipriorityr55: GICD_IPRIORITYR55, } -#[doc = "GICD_IPRIORITYR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR0 (rw) register accessor: Interrupt Priority 0 - 3 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr0`] +module"] pub type GICD_IPRIORITYR0 = crate::Reg; #[doc = "Interrupt Priority 0 - 3 (Lower is first)"] pub mod gicd_ipriorityr0; -#[doc = "GICD_IPRIORITYR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR1 (rw) register accessor: Interrupt Priority 4 - 7 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr1`] +module"] pub type GICD_IPRIORITYR1 = crate::Reg; #[doc = "Interrupt Priority 4 - 7 (Lower is first)"] pub mod gicd_ipriorityr1; -#[doc = "GICD_IPRIORITYR2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR2 (rw) register accessor: Interrupt Priority 8 - 11 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr2`] +module"] pub type GICD_IPRIORITYR2 = crate::Reg; #[doc = "Interrupt Priority 8 - 11 (Lower is first)"] pub mod gicd_ipriorityr2; -#[doc = "GICD_IPRIORITYR3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR3 (rw) register accessor: Interrupt Priority 12 - 15 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr3`] +module"] pub type GICD_IPRIORITYR3 = crate::Reg; #[doc = "Interrupt Priority 12 - 15 (Lower is first)"] pub mod gicd_ipriorityr3; -#[doc = "GICD_IPRIORITYR4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR4 (rw) register accessor: Interrupt Priority 16 - 19 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr4`] +module"] pub type GICD_IPRIORITYR4 = crate::Reg; #[doc = "Interrupt Priority 16 - 19 (Lower is first)"] pub mod gicd_ipriorityr4; -#[doc = "GICD_IPRIORITYR5 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR5 (rw) register accessor: Interrupt Priority 20 - 23 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr5`] +module"] pub type GICD_IPRIORITYR5 = crate::Reg; #[doc = "Interrupt Priority 20 - 23 (Lower is first)"] pub mod gicd_ipriorityr5; -#[doc = "GICD_IPRIORITYR6 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR6 (rw) register accessor: Interrupt Priority 24 - 27 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr6`] +module"] pub type GICD_IPRIORITYR6 = crate::Reg; #[doc = "Interrupt Priority 24 - 27 (Lower is first)"] pub mod gicd_ipriorityr6; -#[doc = "GICD_IPRIORITYR7 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR7 (rw) register accessor: Interrupt Priority 28 - 31 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr7`] +module"] pub type GICD_IPRIORITYR7 = crate::Reg; #[doc = "Interrupt Priority 28 - 31 (Lower is first)"] pub mod gicd_ipriorityr7; -#[doc = "GICD_IPRIORITYR8 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR8 (rw) register accessor: Interrupt Priority 32 - 35 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr8`] +module"] pub type GICD_IPRIORITYR8 = crate::Reg; #[doc = "Interrupt Priority 32 - 35 (Lower is first)"] pub mod gicd_ipriorityr8; -#[doc = "GICD_IPRIORITYR9 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR9 (rw) register accessor: Interrupt Priority 36 - 39 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr9`] +module"] pub type GICD_IPRIORITYR9 = crate::Reg; #[doc = "Interrupt Priority 36 - 39 (Lower is first)"] pub mod gicd_ipriorityr9; -#[doc = "GICD_IPRIORITYR10 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR10 (rw) register accessor: Interrupt Priority 40 - 43 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr10`] +module"] pub type GICD_IPRIORITYR10 = crate::Reg; #[doc = "Interrupt Priority 40 - 43 (Lower is first)"] pub mod gicd_ipriorityr10; -#[doc = "GICD_IPRIORITYR11 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR11 (rw) register accessor: Interrupt Priority 44 - 47 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr11`] +module"] pub type GICD_IPRIORITYR11 = crate::Reg; #[doc = "Interrupt Priority 44 - 47 (Lower is first)"] pub mod gicd_ipriorityr11; -#[doc = "GICD_IPRIORITYR12 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR12 (rw) register accessor: Interrupt Priority 48 - 51 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr12`] +module"] pub type GICD_IPRIORITYR12 = crate::Reg; #[doc = "Interrupt Priority 48 - 51 (Lower is first)"] pub mod gicd_ipriorityr12; -#[doc = "GICD_IPRIORITYR13 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR13 (rw) register accessor: Interrupt Priority 52 - 55 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr13`] +module"] pub type GICD_IPRIORITYR13 = crate::Reg; #[doc = "Interrupt Priority 52 - 55 (Lower is first)"] pub mod gicd_ipriorityr13; -#[doc = "GICD_IPRIORITYR14 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR14 (rw) register accessor: Interrupt Priority 56 - 59 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr14`] +module"] pub type GICD_IPRIORITYR14 = crate::Reg; #[doc = "Interrupt Priority 56 - 59 (Lower is first)"] pub mod gicd_ipriorityr14; -#[doc = "GICD_IPRIORITYR15 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR15 (rw) register accessor: Interrupt Priority 60 - 63 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr15`] +module"] pub type GICD_IPRIORITYR15 = crate::Reg; #[doc = "Interrupt Priority 60 - 63 (Lower is first)"] pub mod gicd_ipriorityr15; -#[doc = "GICD_IPRIORITYR16 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR16 (rw) register accessor: Interrupt Priority 64 - 67 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr16`] +module"] pub type GICD_IPRIORITYR16 = crate::Reg; #[doc = "Interrupt Priority 64 - 67 (Lower is first)"] pub mod gicd_ipriorityr16; -#[doc = "GICD_IPRIORITYR17 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR17 (rw) register accessor: Interrupt Priority 68 - 71 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr17::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr17::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr17`] +module"] pub type GICD_IPRIORITYR17 = crate::Reg; #[doc = "Interrupt Priority 68 - 71 (Lower is first)"] pub mod gicd_ipriorityr17; -#[doc = "GICD_IPRIORITYR18 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR18 (rw) register accessor: Interrupt Priority 72 - 75 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr18::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr18::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr18`] +module"] pub type GICD_IPRIORITYR18 = crate::Reg; #[doc = "Interrupt Priority 72 - 75 (Lower is first)"] pub mod gicd_ipriorityr18; -#[doc = "GICD_IPRIORITYR19 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR19 (rw) register accessor: Interrupt Priority 76 - 79 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr19::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr19`] +module"] pub type GICD_IPRIORITYR19 = crate::Reg; #[doc = "Interrupt Priority 76 - 79 (Lower is first)"] pub mod gicd_ipriorityr19; -#[doc = "GICD_IPRIORITYR20 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR20 (rw) register accessor: Interrupt Priority 80 - 83 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr20`] +module"] pub type GICD_IPRIORITYR20 = crate::Reg; #[doc = "Interrupt Priority 80 - 83 (Lower is first)"] pub mod gicd_ipriorityr20; -#[doc = "GICD_IPRIORITYR21 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR21 (rw) register accessor: Interrupt Priority 84 - 87 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr21::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr21::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr21`] +module"] pub type GICD_IPRIORITYR21 = crate::Reg; #[doc = "Interrupt Priority 84 - 87 (Lower is first)"] pub mod gicd_ipriorityr21; -#[doc = "GICD_IPRIORITYR22 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR22 (rw) register accessor: Interrupt Priority 88 - 91 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr22::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr22::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr22`] +module"] pub type GICD_IPRIORITYR22 = crate::Reg; #[doc = "Interrupt Priority 88 - 91 (Lower is first)"] pub mod gicd_ipriorityr22; -#[doc = "GICD_IPRIORITYR23 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR23 (rw) register accessor: Interrupt Priority 92 - 95 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr23::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr23`] +module"] pub type GICD_IPRIORITYR23 = crate::Reg; #[doc = "Interrupt Priority 92 - 95 (Lower is first)"] pub mod gicd_ipriorityr23; -#[doc = "GICD_IPRIORITYR24 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR24 (rw) register accessor: Interrupt Priority 96 - 99 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr24`] +module"] pub type GICD_IPRIORITYR24 = crate::Reg; #[doc = "Interrupt Priority 96 - 99 (Lower is first)"] pub mod gicd_ipriorityr24; -#[doc = "GICD_IPRIORITYR25 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR25 (rw) register accessor: Interrupt Priority 100 - 103 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr25::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr25::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr25`] +module"] pub type GICD_IPRIORITYR25 = crate::Reg; #[doc = "Interrupt Priority 100 - 103 (Lower is first)"] pub mod gicd_ipriorityr25; -#[doc = "GICD_IPRIORITYR26 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR26 (rw) register accessor: Interrupt Priority 104 - 107 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr26::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr26::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr26`] +module"] pub type GICD_IPRIORITYR26 = crate::Reg; #[doc = "Interrupt Priority 104 - 107 (Lower is first)"] pub mod gicd_ipriorityr26; -#[doc = "GICD_IPRIORITYR27 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR27 (rw) register accessor: Interrupt Priority 108 - 111 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr27::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr27`] +module"] pub type GICD_IPRIORITYR27 = crate::Reg; #[doc = "Interrupt Priority 108 - 111 (Lower is first)"] pub mod gicd_ipriorityr27; -#[doc = "GICD_IPRIORITYR28 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR28 (rw) register accessor: Interrupt Priority 112 - 115 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr28::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr28`] +module"] pub type GICD_IPRIORITYR28 = crate::Reg; #[doc = "Interrupt Priority 112 - 115 (Lower is first)"] pub mod gicd_ipriorityr28; -#[doc = "GICD_IPRIORITYR29 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR29 (rw) register accessor: Interrupt Priority 116 - 119 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr29::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr29::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr29`] +module"] pub type GICD_IPRIORITYR29 = crate::Reg; #[doc = "Interrupt Priority 116 - 119 (Lower is first)"] pub mod gicd_ipriorityr29; -#[doc = "GICD_IPRIORITYR30 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR30 (rw) register accessor: Interrupt Priority 120 - 123 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr30::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr30::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr30`] +module"] pub type GICD_IPRIORITYR30 = crate::Reg; #[doc = "Interrupt Priority 120 - 123 (Lower is first)"] pub mod gicd_ipriorityr30; -#[doc = "GICD_IPRIORITYR31 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR31 (rw) register accessor: Interrupt Priority 124 - 127 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr31::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr31`] +module"] pub type GICD_IPRIORITYR31 = crate::Reg; #[doc = "Interrupt Priority 124 - 127 (Lower is first)"] pub mod gicd_ipriorityr31; -#[doc = "GICD_IPRIORITYR32 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR32 (rw) register accessor: Interrupt Priority 128 - 131 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr32::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr32`] +module"] pub type GICD_IPRIORITYR32 = crate::Reg; #[doc = "Interrupt Priority 128 - 131 (Lower is first)"] pub mod gicd_ipriorityr32; -#[doc = "GICD_IPRIORITYR33 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR33 (rw) register accessor: Interrupt Priority 132 - 135 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr33::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr33::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr33`] +module"] pub type GICD_IPRIORITYR33 = crate::Reg; #[doc = "Interrupt Priority 132 - 135 (Lower is first)"] pub mod gicd_ipriorityr33; -#[doc = "GICD_IPRIORITYR34 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR34 (rw) register accessor: Interrupt Priority 136 - 139 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr34::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr34::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr34`] +module"] pub type GICD_IPRIORITYR34 = crate::Reg; #[doc = "Interrupt Priority 136 - 139 (Lower is first)"] pub mod gicd_ipriorityr34; -#[doc = "GICD_IPRIORITYR35 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR35 (rw) register accessor: Interrupt Priority 140 - 143 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr35::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr35`] +module"] pub type GICD_IPRIORITYR35 = crate::Reg; #[doc = "Interrupt Priority 140 - 143 (Lower is first)"] pub mod gicd_ipriorityr35; -#[doc = "GICD_IPRIORITYR36 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR36 (rw) register accessor: Interrupt Priority 144 - 147 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr36::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr36`] +module"] pub type GICD_IPRIORITYR36 = crate::Reg; #[doc = "Interrupt Priority 144 - 147 (Lower is first)"] pub mod gicd_ipriorityr36; -#[doc = "GICD_IPRIORITYR37 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR37 (rw) register accessor: Interrupt Priority 148 - 151 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr37::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr37::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr37`] +module"] pub type GICD_IPRIORITYR37 = crate::Reg; #[doc = "Interrupt Priority 148 - 151 (Lower is first)"] pub mod gicd_ipriorityr37; -#[doc = "GICD_IPRIORITYR38 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR38 (rw) register accessor: Interrupt Priority 152 - 155 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr38::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr38::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr38`] +module"] pub type GICD_IPRIORITYR38 = crate::Reg; #[doc = "Interrupt Priority 152 - 155 (Lower is first)"] pub mod gicd_ipriorityr38; -#[doc = "GICD_IPRIORITYR39 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR39 (rw) register accessor: Interrupt Priority 156 - 159 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr39::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr39`] +module"] pub type GICD_IPRIORITYR39 = crate::Reg; #[doc = "Interrupt Priority 156 - 159 (Lower is first)"] pub mod gicd_ipriorityr39; -#[doc = "GICD_IPRIORITYR40 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR40 (rw) register accessor: Interrupt Priority 160 - 163 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr40::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr40`] +module"] pub type GICD_IPRIORITYR40 = crate::Reg; #[doc = "Interrupt Priority 160 - 163 (Lower is first)"] pub mod gicd_ipriorityr40; -#[doc = "GICD_IPRIORITYR41 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR41 (rw) register accessor: Interrupt Priority 164 - 167 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr41::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr41::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr41`] +module"] pub type GICD_IPRIORITYR41 = crate::Reg; #[doc = "Interrupt Priority 164 - 167 (Lower is first)"] pub mod gicd_ipriorityr41; -#[doc = "GICD_IPRIORITYR42 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR42 (rw) register accessor: Interrupt Priority 168 - 171 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr42::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr42::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr42`] +module"] pub type GICD_IPRIORITYR42 = crate::Reg; #[doc = "Interrupt Priority 168 - 171 (Lower is first)"] pub mod gicd_ipriorityr42; -#[doc = "GICD_IPRIORITYR43 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR43 (rw) register accessor: Interrupt Priority 172 - 175 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr43::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr43`] +module"] pub type GICD_IPRIORITYR43 = crate::Reg; #[doc = "Interrupt Priority 172 - 175 (Lower is first)"] pub mod gicd_ipriorityr43; -#[doc = "GICD_IPRIORITYR44 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR44 (rw) register accessor: Interrupt Priority 176 - 179 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr44::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr44`] +module"] pub type GICD_IPRIORITYR44 = crate::Reg; #[doc = "Interrupt Priority 176 - 179 (Lower is first)"] pub mod gicd_ipriorityr44; -#[doc = "GICD_IPRIORITYR45 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR45 (rw) register accessor: Interrupt Priority 180 - 183 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr45::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr45::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr45`] +module"] pub type GICD_IPRIORITYR45 = crate::Reg; #[doc = "Interrupt Priority 180 - 183 (Lower is first)"] pub mod gicd_ipriorityr45; -#[doc = "GICD_IPRIORITYR46 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR46 (rw) register accessor: Interrupt Priority 184 - 187 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr46::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr46::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr46`] +module"] pub type GICD_IPRIORITYR46 = crate::Reg; #[doc = "Interrupt Priority 184 - 187 (Lower is first)"] pub mod gicd_ipriorityr46; -#[doc = "GICD_IPRIORITYR47 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR47 (rw) register accessor: Interrupt Priority 188 - 191 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr47::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr47`] +module"] pub type GICD_IPRIORITYR47 = crate::Reg; #[doc = "Interrupt Priority 188 - 191 (Lower is first)"] pub mod gicd_ipriorityr47; -#[doc = "GICD_IPRIORITYR48 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR48 (rw) register accessor: Interrupt Priority 192 - 195 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr48`] +module"] pub type GICD_IPRIORITYR48 = crate::Reg; #[doc = "Interrupt Priority 192 - 195 (Lower is first)"] pub mod gicd_ipriorityr48; -#[doc = "GICD_IPRIORITYR49 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR49 (rw) register accessor: Interrupt Priority 196 - 199 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr49::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr49::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr49`] +module"] pub type GICD_IPRIORITYR49 = crate::Reg; #[doc = "Interrupt Priority 196 - 199 (Lower is first)"] pub mod gicd_ipriorityr49; -#[doc = "GICD_IPRIORITYR50 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR50 (rw) register accessor: Interrupt Priority 200 - 203 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr50::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr50::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr50`] +module"] pub type GICD_IPRIORITYR50 = crate::Reg; #[doc = "Interrupt Priority 200 - 203 (Lower is first)"] pub mod gicd_ipriorityr50; -#[doc = "GICD_IPRIORITYR51 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR51 (rw) register accessor: Interrupt Priority 204 - 207 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr51::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr51`] +module"] pub type GICD_IPRIORITYR51 = crate::Reg; #[doc = "Interrupt Priority 204 - 207 (Lower is first)"] pub mod gicd_ipriorityr51; -#[doc = "GICD_IPRIORITYR52 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR52 (rw) register accessor: Interrupt Priority 208 - 211 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr52::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr52`] +module"] pub type GICD_IPRIORITYR52 = crate::Reg; #[doc = "Interrupt Priority 208 - 211 (Lower is first)"] pub mod gicd_ipriorityr52; -#[doc = "GICD_IPRIORITYR53 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR53 (rw) register accessor: Interrupt Priority 212 - 215 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr53::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr53::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr53`] +module"] pub type GICD_IPRIORITYR53 = crate::Reg; #[doc = "Interrupt Priority 212 - 215 (Lower is first)"] pub mod gicd_ipriorityr53; -#[doc = "GICD_IPRIORITYR54 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR54 (rw) register accessor: Interrupt Priority 216 - 219 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr54::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr54::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr54`] +module"] pub type GICD_IPRIORITYR54 = crate::Reg; #[doc = "Interrupt Priority 216 - 219 (Lower is first)"] pub mod gicd_ipriorityr54; -#[doc = "GICD_IPRIORITYR55 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_IPRIORITYR55 (rw) register accessor: Interrupt Priority 220 - 223 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr55::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ipriorityr55`] +module"] pub type GICD_IPRIORITYR55 = crate::Reg; #[doc = "Interrupt Priority 220 - 223 (Lower is first)"] pub mod gicd_ipriorityr55; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr0.rs index 739cf21..ec512ce 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr0.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr0.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT0` reader - Interrupt 0"] -pub type INT0_R = crate::FieldReader; +pub type INT0_R = crate::FieldReader; #[doc = "Field `INT0` writer - Interrupt 0"] -pub type INT0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR0_SPEC, u8, u8, 8, O>; +pub type INT0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT1` reader - Interrupt 1"] -pub type INT1_R = crate::FieldReader; +pub type INT1_R = crate::FieldReader; #[doc = "Field `INT1` writer - Interrupt 1"] -pub type INT1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR0_SPEC, u8, u8, 8, O>; +pub type INT1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT2` reader - Interrupt 2"] -pub type INT2_R = crate::FieldReader; +pub type INT2_R = crate::FieldReader; #[doc = "Field `INT2` writer - Interrupt 2"] -pub type INT2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR0_SPEC, u8, u8, 8, O>; +pub type INT2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT3` reader - Interrupt 3"] -pub type INT3_R = crate::FieldReader; +pub type INT3_R = crate::FieldReader; #[doc = "Field `INT3` writer - Interrupt 3"] -pub type INT3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR0_SPEC, u8, u8, 8, O>; +pub type INT3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 0"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { INT3_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR0") + .field("int0", &format_args!("{}", self.int0().bits())) + .field("int1", &format_args!("{}", self.int1().bits())) + .field("int2", &format_args!("{}", self.int2().bits())) + .field("int3", &format_args!("{}", self.int3().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 0"] #[inline(always)] #[must_use] - pub fn int0(&mut self) -> INT0_W<0> { + pub fn int0(&mut self) -> INT0_W { INT0_W::new(self) } #[doc = "Bits 8:15 - Interrupt 1"] #[inline(always)] #[must_use] - pub fn int1(&mut self) -> INT1_W<8> { + pub fn int1(&mut self) -> INT1_W { INT1_W::new(self) } #[doc = "Bits 16:23 - Interrupt 2"] #[inline(always)] #[must_use] - pub fn int2(&mut self) -> INT2_W<16> { + pub fn int2(&mut self) -> INT2_W { INT2_W::new(self) } #[doc = "Bits 24:31 - Interrupt 3"] #[inline(always)] #[must_use] - pub fn int3(&mut self) -> INT3_W<24> { + pub fn int3(&mut self) -> INT3_W { INT3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 0 - 3 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr0](index.html) module"] +#[doc = "Interrupt Priority 0 - 3 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR0_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr0::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr0::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr0::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr0::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr1.rs index 368e075..3143efd 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr1.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr1.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT4` reader - Interrupt 4"] -pub type INT4_R = crate::FieldReader; +pub type INT4_R = crate::FieldReader; #[doc = "Field `INT4` writer - Interrupt 4"] -pub type INT4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR1_SPEC, u8, u8, 8, O>; +pub type INT4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT5` reader - Interrupt 5"] -pub type INT5_R = crate::FieldReader; +pub type INT5_R = crate::FieldReader; #[doc = "Field `INT5` writer - Interrupt 5"] -pub type INT5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR1_SPEC, u8, u8, 8, O>; +pub type INT5_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT6` reader - Interrupt 6"] -pub type INT6_R = crate::FieldReader; +pub type INT6_R = crate::FieldReader; #[doc = "Field `INT6` writer - Interrupt 6"] -pub type INT6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR1_SPEC, u8, u8, 8, O>; +pub type INT6_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT7` reader - Interrupt 7"] -pub type INT7_R = crate::FieldReader; +pub type INT7_R = crate::FieldReader; #[doc = "Field `INT7` writer - Interrupt 7"] -pub type INT7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR1_SPEC, u8, u8, 8, O>; +pub type INT7_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 4"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { INT7_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR1") + .field("int4", &format_args!("{}", self.int4().bits())) + .field("int5", &format_args!("{}", self.int5().bits())) + .field("int6", &format_args!("{}", self.int6().bits())) + .field("int7", &format_args!("{}", self.int7().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 4"] #[inline(always)] #[must_use] - pub fn int4(&mut self) -> INT4_W<0> { + pub fn int4(&mut self) -> INT4_W { INT4_W::new(self) } #[doc = "Bits 8:15 - Interrupt 5"] #[inline(always)] #[must_use] - pub fn int5(&mut self) -> INT5_W<8> { + pub fn int5(&mut self) -> INT5_W { INT5_W::new(self) } #[doc = "Bits 16:23 - Interrupt 6"] #[inline(always)] #[must_use] - pub fn int6(&mut self) -> INT6_W<16> { + pub fn int6(&mut self) -> INT6_W { INT6_W::new(self) } #[doc = "Bits 24:31 - Interrupt 7"] #[inline(always)] #[must_use] - pub fn int7(&mut self) -> INT7_W<24> { + pub fn int7(&mut self) -> INT7_W { INT7_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 4 - 7 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr1](index.html) module"] +#[doc = "Interrupt Priority 4 - 7 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR1_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr1::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr1::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr1::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr1::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr10.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr10.rs index 5447dfb..e97756a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr10.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr10.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR10` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR10` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT40` reader - Interrupt 40"] -pub type INT40_R = crate::FieldReader; +pub type INT40_R = crate::FieldReader; #[doc = "Field `INT40` writer - Interrupt 40"] -pub type INT40_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR10_SPEC, u8, u8, 8, O>; +pub type INT40_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT41` reader - Interrupt 41"] -pub type INT41_R = crate::FieldReader; +pub type INT41_R = crate::FieldReader; #[doc = "Field `INT41` writer - Interrupt 41"] -pub type INT41_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR10_SPEC, u8, u8, 8, O>; +pub type INT41_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT42` reader - Interrupt 42"] -pub type INT42_R = crate::FieldReader; +pub type INT42_R = crate::FieldReader; #[doc = "Field `INT42` writer - Interrupt 42"] -pub type INT42_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR10_SPEC, u8, u8, 8, O>; +pub type INT42_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT43` reader - Interrupt 43"] -pub type INT43_R = crate::FieldReader; +pub type INT43_R = crate::FieldReader; #[doc = "Field `INT43` writer - Interrupt 43"] -pub type INT43_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR10_SPEC, u8, u8, 8, O>; +pub type INT43_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 40"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT43_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR10") + .field("int40", &format_args!("{}", self.int40().bits())) + .field("int41", &format_args!("{}", self.int41().bits())) + .field("int42", &format_args!("{}", self.int42().bits())) + .field("int43", &format_args!("{}", self.int43().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 40"] #[inline(always)] #[must_use] - pub fn int40(&mut self) -> INT40_W<0> { + pub fn int40(&mut self) -> INT40_W { INT40_W::new(self) } #[doc = "Bits 8:15 - Interrupt 41"] #[inline(always)] #[must_use] - pub fn int41(&mut self) -> INT41_W<8> { + pub fn int41(&mut self) -> INT41_W { INT41_W::new(self) } #[doc = "Bits 16:23 - Interrupt 42"] #[inline(always)] #[must_use] - pub fn int42(&mut self) -> INT42_W<16> { + pub fn int42(&mut self) -> INT42_W { INT42_W::new(self) } #[doc = "Bits 24:31 - Interrupt 43"] #[inline(always)] #[must_use] - pub fn int43(&mut self) -> INT43_W<24> { + pub fn int43(&mut self) -> INT43_W { INT43_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 40 - 43 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr10](index.html) module"] +#[doc = "Interrupt Priority 40 - 43 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR10_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR10_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr10::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR10_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr10::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr10::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr10::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR10_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr11.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr11.rs index bc71e03..338aaa9 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr11.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr11.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR11` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR11` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT44` reader - Interrupt 44"] -pub type INT44_R = crate::FieldReader; +pub type INT44_R = crate::FieldReader; #[doc = "Field `INT44` writer - Interrupt 44"] -pub type INT44_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR11_SPEC, u8, u8, 8, O>; +pub type INT44_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT45` reader - Interrupt 45"] -pub type INT45_R = crate::FieldReader; +pub type INT45_R = crate::FieldReader; #[doc = "Field `INT45` writer - Interrupt 45"] -pub type INT45_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR11_SPEC, u8, u8, 8, O>; +pub type INT45_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT46` reader - Interrupt 46"] -pub type INT46_R = crate::FieldReader; +pub type INT46_R = crate::FieldReader; #[doc = "Field `INT46` writer - Interrupt 46"] -pub type INT46_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR11_SPEC, u8, u8, 8, O>; +pub type INT46_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT47` reader - Interrupt 47"] -pub type INT47_R = crate::FieldReader; +pub type INT47_R = crate::FieldReader; #[doc = "Field `INT47` writer - Interrupt 47"] -pub type INT47_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR11_SPEC, u8, u8, 8, O>; +pub type INT47_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 44"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT47_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR11") + .field("int44", &format_args!("{}", self.int44().bits())) + .field("int45", &format_args!("{}", self.int45().bits())) + .field("int46", &format_args!("{}", self.int46().bits())) + .field("int47", &format_args!("{}", self.int47().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 44"] #[inline(always)] #[must_use] - pub fn int44(&mut self) -> INT44_W<0> { + pub fn int44(&mut self) -> INT44_W { INT44_W::new(self) } #[doc = "Bits 8:15 - Interrupt 45"] #[inline(always)] #[must_use] - pub fn int45(&mut self) -> INT45_W<8> { + pub fn int45(&mut self) -> INT45_W { INT45_W::new(self) } #[doc = "Bits 16:23 - Interrupt 46"] #[inline(always)] #[must_use] - pub fn int46(&mut self) -> INT46_W<16> { + pub fn int46(&mut self) -> INT46_W { INT46_W::new(self) } #[doc = "Bits 24:31 - Interrupt 47"] #[inline(always)] #[must_use] - pub fn int47(&mut self) -> INT47_W<24> { + pub fn int47(&mut self) -> INT47_W { INT47_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 44 - 47 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr11](index.html) module"] +#[doc = "Interrupt Priority 44 - 47 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR11_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR11_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr11::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR11_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr11::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr11::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr11::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR11_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr12.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr12.rs index 44785a0..2d7d147 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr12.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr12.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR12` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR12` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT48` reader - Interrupt 48"] -pub type INT48_R = crate::FieldReader; +pub type INT48_R = crate::FieldReader; #[doc = "Field `INT48` writer - Interrupt 48"] -pub type INT48_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR12_SPEC, u8, u8, 8, O>; +pub type INT48_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT49` reader - Interrupt 49"] -pub type INT49_R = crate::FieldReader; +pub type INT49_R = crate::FieldReader; #[doc = "Field `INT49` writer - Interrupt 49"] -pub type INT49_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR12_SPEC, u8, u8, 8, O>; +pub type INT49_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT50` reader - Interrupt 50"] -pub type INT50_R = crate::FieldReader; +pub type INT50_R = crate::FieldReader; #[doc = "Field `INT50` writer - Interrupt 50"] -pub type INT50_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR12_SPEC, u8, u8, 8, O>; +pub type INT50_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT51` reader - Interrupt 51"] -pub type INT51_R = crate::FieldReader; +pub type INT51_R = crate::FieldReader; #[doc = "Field `INT51` writer - Interrupt 51"] -pub type INT51_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR12_SPEC, u8, u8, 8, O>; +pub type INT51_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 48"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT51_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR12") + .field("int48", &format_args!("{}", self.int48().bits())) + .field("int49", &format_args!("{}", self.int49().bits())) + .field("int50", &format_args!("{}", self.int50().bits())) + .field("int51", &format_args!("{}", self.int51().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 48"] #[inline(always)] #[must_use] - pub fn int48(&mut self) -> INT48_W<0> { + pub fn int48(&mut self) -> INT48_W { INT48_W::new(self) } #[doc = "Bits 8:15 - Interrupt 49"] #[inline(always)] #[must_use] - pub fn int49(&mut self) -> INT49_W<8> { + pub fn int49(&mut self) -> INT49_W { INT49_W::new(self) } #[doc = "Bits 16:23 - Interrupt 50"] #[inline(always)] #[must_use] - pub fn int50(&mut self) -> INT50_W<16> { + pub fn int50(&mut self) -> INT50_W { INT50_W::new(self) } #[doc = "Bits 24:31 - Interrupt 51"] #[inline(always)] #[must_use] - pub fn int51(&mut self) -> INT51_W<24> { + pub fn int51(&mut self) -> INT51_W { INT51_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 48 - 51 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr12](index.html) module"] +#[doc = "Interrupt Priority 48 - 51 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR12_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR12_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr12::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR12_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr12::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr12::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr12::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR12_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr13.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr13.rs index 53f82e8..485c477 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr13.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr13.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR13` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR13` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT52` reader - Interrupt 52"] -pub type INT52_R = crate::FieldReader; +pub type INT52_R = crate::FieldReader; #[doc = "Field `INT52` writer - Interrupt 52"] -pub type INT52_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR13_SPEC, u8, u8, 8, O>; +pub type INT52_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT53` reader - Interrupt 53"] -pub type INT53_R = crate::FieldReader; +pub type INT53_R = crate::FieldReader; #[doc = "Field `INT53` writer - Interrupt 53"] -pub type INT53_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR13_SPEC, u8, u8, 8, O>; +pub type INT53_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT54` reader - Interrupt 54"] -pub type INT54_R = crate::FieldReader; +pub type INT54_R = crate::FieldReader; #[doc = "Field `INT54` writer - Interrupt 54"] -pub type INT54_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR13_SPEC, u8, u8, 8, O>; +pub type INT54_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT55` reader - Interrupt 55"] -pub type INT55_R = crate::FieldReader; +pub type INT55_R = crate::FieldReader; #[doc = "Field `INT55` writer - Interrupt 55"] -pub type INT55_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR13_SPEC, u8, u8, 8, O>; +pub type INT55_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 52"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT55_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR13") + .field("int52", &format_args!("{}", self.int52().bits())) + .field("int53", &format_args!("{}", self.int53().bits())) + .field("int54", &format_args!("{}", self.int54().bits())) + .field("int55", &format_args!("{}", self.int55().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 52"] #[inline(always)] #[must_use] - pub fn int52(&mut self) -> INT52_W<0> { + pub fn int52(&mut self) -> INT52_W { INT52_W::new(self) } #[doc = "Bits 8:15 - Interrupt 53"] #[inline(always)] #[must_use] - pub fn int53(&mut self) -> INT53_W<8> { + pub fn int53(&mut self) -> INT53_W { INT53_W::new(self) } #[doc = "Bits 16:23 - Interrupt 54"] #[inline(always)] #[must_use] - pub fn int54(&mut self) -> INT54_W<16> { + pub fn int54(&mut self) -> INT54_W { INT54_W::new(self) } #[doc = "Bits 24:31 - Interrupt 55"] #[inline(always)] #[must_use] - pub fn int55(&mut self) -> INT55_W<24> { + pub fn int55(&mut self) -> INT55_W { INT55_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 52 - 55 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr13](index.html) module"] +#[doc = "Interrupt Priority 52 - 55 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR13_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR13_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr13::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR13_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr13::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr13::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr13::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR13_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr14.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr14.rs index d45e8d4..cdea11b 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr14.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr14.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR14` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR14` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT56` reader - Interrupt 56"] -pub type INT56_R = crate::FieldReader; +pub type INT56_R = crate::FieldReader; #[doc = "Field `INT56` writer - Interrupt 56"] -pub type INT56_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR14_SPEC, u8, u8, 8, O>; +pub type INT56_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT57` reader - Interrupt 57"] -pub type INT57_R = crate::FieldReader; +pub type INT57_R = crate::FieldReader; #[doc = "Field `INT57` writer - Interrupt 57"] -pub type INT57_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR14_SPEC, u8, u8, 8, O>; +pub type INT57_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT58` reader - Interrupt 58"] -pub type INT58_R = crate::FieldReader; +pub type INT58_R = crate::FieldReader; #[doc = "Field `INT58` writer - Interrupt 58"] -pub type INT58_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR14_SPEC, u8, u8, 8, O>; +pub type INT58_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT59` reader - Interrupt 59"] -pub type INT59_R = crate::FieldReader; +pub type INT59_R = crate::FieldReader; #[doc = "Field `INT59` writer - Interrupt 59"] -pub type INT59_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR14_SPEC, u8, u8, 8, O>; +pub type INT59_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 56"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT59_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR14") + .field("int56", &format_args!("{}", self.int56().bits())) + .field("int57", &format_args!("{}", self.int57().bits())) + .field("int58", &format_args!("{}", self.int58().bits())) + .field("int59", &format_args!("{}", self.int59().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 56"] #[inline(always)] #[must_use] - pub fn int56(&mut self) -> INT56_W<0> { + pub fn int56(&mut self) -> INT56_W { INT56_W::new(self) } #[doc = "Bits 8:15 - Interrupt 57"] #[inline(always)] #[must_use] - pub fn int57(&mut self) -> INT57_W<8> { + pub fn int57(&mut self) -> INT57_W { INT57_W::new(self) } #[doc = "Bits 16:23 - Interrupt 58"] #[inline(always)] #[must_use] - pub fn int58(&mut self) -> INT58_W<16> { + pub fn int58(&mut self) -> INT58_W { INT58_W::new(self) } #[doc = "Bits 24:31 - Interrupt 59"] #[inline(always)] #[must_use] - pub fn int59(&mut self) -> INT59_W<24> { + pub fn int59(&mut self) -> INT59_W { INT59_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 56 - 59 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr14](index.html) module"] +#[doc = "Interrupt Priority 56 - 59 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR14_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR14_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr14::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR14_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr14::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr14::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr14::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR14_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr15.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr15.rs index 8200e81..9aea127 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr15.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr15.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR15` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR15` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT60` reader - Interrupt 60"] -pub type INT60_R = crate::FieldReader; +pub type INT60_R = crate::FieldReader; #[doc = "Field `INT60` writer - Interrupt 60"] -pub type INT60_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR15_SPEC, u8, u8, 8, O>; +pub type INT60_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT61` reader - Interrupt 61"] -pub type INT61_R = crate::FieldReader; +pub type INT61_R = crate::FieldReader; #[doc = "Field `INT61` writer - Interrupt 61"] -pub type INT61_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR15_SPEC, u8, u8, 8, O>; +pub type INT61_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT62` reader - Interrupt 62"] -pub type INT62_R = crate::FieldReader; +pub type INT62_R = crate::FieldReader; #[doc = "Field `INT62` writer - Interrupt 62"] -pub type INT62_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR15_SPEC, u8, u8, 8, O>; +pub type INT62_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT63` reader - Interrupt 63"] -pub type INT63_R = crate::FieldReader; +pub type INT63_R = crate::FieldReader; #[doc = "Field `INT63` writer - Interrupt 63"] -pub type INT63_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR15_SPEC, u8, u8, 8, O>; +pub type INT63_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 60"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT63_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR15") + .field("int60", &format_args!("{}", self.int60().bits())) + .field("int61", &format_args!("{}", self.int61().bits())) + .field("int62", &format_args!("{}", self.int62().bits())) + .field("int63", &format_args!("{}", self.int63().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 60"] #[inline(always)] #[must_use] - pub fn int60(&mut self) -> INT60_W<0> { + pub fn int60(&mut self) -> INT60_W { INT60_W::new(self) } #[doc = "Bits 8:15 - Interrupt 61"] #[inline(always)] #[must_use] - pub fn int61(&mut self) -> INT61_W<8> { + pub fn int61(&mut self) -> INT61_W { INT61_W::new(self) } #[doc = "Bits 16:23 - Interrupt 62"] #[inline(always)] #[must_use] - pub fn int62(&mut self) -> INT62_W<16> { + pub fn int62(&mut self) -> INT62_W { INT62_W::new(self) } #[doc = "Bits 24:31 - Interrupt 63"] #[inline(always)] #[must_use] - pub fn int63(&mut self) -> INT63_W<24> { + pub fn int63(&mut self) -> INT63_W { INT63_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 60 - 63 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr15](index.html) module"] +#[doc = "Interrupt Priority 60 - 63 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR15_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR15_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr15::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR15_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr15::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr15::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr15::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR15_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr16.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr16.rs index 17c0f1d..8a604ee 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr16.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr16.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR16` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR16` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::FieldReader; +pub type TIMER_R = crate::FieldReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR16_SPEC, u8, u8, 8, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::FieldReader; +pub type MAILBOX_R = crate::FieldReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR16_SPEC, u8, u8, 8, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::FieldReader; +pub type DOORBELL0_R = crate::FieldReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR16_SPEC, u8, u8, 8, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::FieldReader; +pub type DOORBELL1_R = crate::FieldReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR16_SPEC, u8, u8, 8, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - ARMC Timer"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { DOORBELL1_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR16") + .field("timer", &format_args!("{}", self.timer().bits())) + .field("mailbox", &format_args!("{}", self.mailbox().bits())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bits())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bits 8:15 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<8> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bits 16:23 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<16> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bits 24:31 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<24> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 64 - 67 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr16](index.html) module"] +#[doc = "Interrupt Priority 64 - 67 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr16::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr16::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR16_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR16_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr16::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR16_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr16::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr16::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR16_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr16::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR16_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr17.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr17.rs index e51048c..2bd895e 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr17.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr17.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR17` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR17` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::FieldReader; +pub type VPU0_HALTED_R = crate::FieldReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR17_SPEC, u8, u8, 8, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::FieldReader; +pub type VPU1_HALTED_R = crate::FieldReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR17_SPEC, u8, u8, 8, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::FieldReader; +pub type ARM_ADDRESS_ERROR_R = crate::FieldReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR17_SPEC, u8, u8, 8, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::FieldReader; +pub type ARM_AXI_ERROR_R = crate::FieldReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR17_SPEC, u8, u8, 8, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - VPU0 halted"] #[inline(always)] @@ -76,50 +40,78 @@ impl R { ARM_AXI_ERROR_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR17") + .field( + "vpu0_halted", + &format_args!("{}", self.vpu0_halted().bits()), + ) + .field( + "vpu1_halted", + &format_args!("{}", self.vpu1_halted().bits()), + ) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bits()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<0> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bits 8:15 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<8> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bits 16:23 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<16> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bits 24:31 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<24> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 68 - 71 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr17](index.html) module"] +#[doc = "Interrupt Priority 68 - 71 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr17::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr17::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR17_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR17_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr17::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR17_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr17::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr17::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR17_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr17::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR17_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr18.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr18.rs index 46956b3..8448e10 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr18.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr18.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR18` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR18` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SWI0` reader - Software interrupt 0"] -pub type SWI0_R = crate::FieldReader; +pub type SWI0_R = crate::FieldReader; #[doc = "Field `SWI0` writer - Software interrupt 0"] -pub type SWI0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR18_SPEC, u8, u8, 8, O>; +pub type SWI0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SWI1` reader - Software interrupt 1"] -pub type SWI1_R = crate::FieldReader; +pub type SWI1_R = crate::FieldReader; #[doc = "Field `SWI1` writer - Software interrupt 1"] -pub type SWI1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR18_SPEC, u8, u8, 8, O>; +pub type SWI1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SWI2` reader - Software interrupt 2"] -pub type SWI2_R = crate::FieldReader; +pub type SWI2_R = crate::FieldReader; #[doc = "Field `SWI2` writer - Software interrupt 2"] -pub type SWI2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR18_SPEC, u8, u8, 8, O>; +pub type SWI2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SWI3` reader - Software interrupt 3"] -pub type SWI3_R = crate::FieldReader; +pub type SWI3_R = crate::FieldReader; #[doc = "Field `SWI3` writer - Software interrupt 3"] -pub type SWI3_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR18_SPEC, u8, u8, 8, O>; +pub type SWI3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Software interrupt 0"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { SWI3_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR18") + .field("swi0", &format_args!("{}", self.swi0().bits())) + .field("swi1", &format_args!("{}", self.swi1().bits())) + .field("swi2", &format_args!("{}", self.swi2().bits())) + .field("swi3", &format_args!("{}", self.swi3().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Software interrupt 0"] #[inline(always)] #[must_use] - pub fn swi0(&mut self) -> SWI0_W<0> { + pub fn swi0(&mut self) -> SWI0_W { SWI0_W::new(self) } #[doc = "Bits 8:15 - Software interrupt 1"] #[inline(always)] #[must_use] - pub fn swi1(&mut self) -> SWI1_W<8> { + pub fn swi1(&mut self) -> SWI1_W { SWI1_W::new(self) } #[doc = "Bits 16:23 - Software interrupt 2"] #[inline(always)] #[must_use] - pub fn swi2(&mut self) -> SWI2_W<16> { + pub fn swi2(&mut self) -> SWI2_W { SWI2_W::new(self) } #[doc = "Bits 24:31 - Software interrupt 3"] #[inline(always)] #[must_use] - pub fn swi3(&mut self) -> SWI3_W<24> { + pub fn swi3(&mut self) -> SWI3_W { SWI3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 72 - 75 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr18](index.html) module"] +#[doc = "Interrupt Priority 72 - 75 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr18::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr18::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR18_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR18_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr18::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR18_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr18::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr18::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR18_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr18::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR18_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr19.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr19.rs index d2e13b4..37f71e2 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr19.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr19.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR19` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR19` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SWI4` reader - Software interrupt 4"] -pub type SWI4_R = crate::FieldReader; +pub type SWI4_R = crate::FieldReader; #[doc = "Field `SWI4` writer - Software interrupt 4"] -pub type SWI4_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR19_SPEC, u8, u8, 8, O>; +pub type SWI4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SWI5` reader - Software interrupt 5"] -pub type SWI5_R = crate::FieldReader; +pub type SWI5_R = crate::FieldReader; #[doc = "Field `SWI5` writer - Software interrupt 5"] -pub type SWI5_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR19_SPEC, u8, u8, 8, O>; +pub type SWI5_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SWI6` reader - Software interrupt 6"] -pub type SWI6_R = crate::FieldReader; +pub type SWI6_R = crate::FieldReader; #[doc = "Field `SWI6` writer - Software interrupt 6"] -pub type SWI6_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR19_SPEC, u8, u8, 8, O>; +pub type SWI6_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SWI7` reader - Software interrupt 7"] -pub type SWI7_R = crate::FieldReader; +pub type SWI7_R = crate::FieldReader; #[doc = "Field `SWI7` writer - Software interrupt 7"] -pub type SWI7_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR19_SPEC, u8, u8, 8, O>; +pub type SWI7_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Software interrupt 4"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { SWI7_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR19") + .field("swi4", &format_args!("{}", self.swi4().bits())) + .field("swi5", &format_args!("{}", self.swi5().bits())) + .field("swi6", &format_args!("{}", self.swi6().bits())) + .field("swi7", &format_args!("{}", self.swi7().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Software interrupt 4"] #[inline(always)] #[must_use] - pub fn swi4(&mut self) -> SWI4_W<0> { + pub fn swi4(&mut self) -> SWI4_W { SWI4_W::new(self) } #[doc = "Bits 8:15 - Software interrupt 5"] #[inline(always)] #[must_use] - pub fn swi5(&mut self) -> SWI5_W<8> { + pub fn swi5(&mut self) -> SWI5_W { SWI5_W::new(self) } #[doc = "Bits 16:23 - Software interrupt 6"] #[inline(always)] #[must_use] - pub fn swi6(&mut self) -> SWI6_W<16> { + pub fn swi6(&mut self) -> SWI6_W { SWI6_W::new(self) } #[doc = "Bits 24:31 - Software interrupt 7"] #[inline(always)] #[must_use] - pub fn swi7(&mut self) -> SWI7_W<24> { + pub fn swi7(&mut self) -> SWI7_W { SWI7_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 76 - 79 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr19](index.html) module"] +#[doc = "Interrupt Priority 76 - 79 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr19::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr19::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR19_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR19_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr19::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR19_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr19::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr19::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR19_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr19::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR19_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr2.rs index 0d60965..f4f3f46 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr2.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr2.rs @@ -1,57 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT8` reader - Interrupt 8"] -pub type INT8_R = crate::FieldReader; +pub type INT8_R = crate::FieldReader; #[doc = "Field `INT8` writer - Interrupt 8"] -pub type INT8_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR2_SPEC, u8, u8, 8, O>; +pub type INT8_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT9` reader - Interrupt 9"] -pub type INT9_R = crate::FieldReader; +pub type INT9_R = crate::FieldReader; #[doc = "Field `INT9` writer - Interrupt 9"] -pub type INT9_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR2_SPEC, u8, u8, 8, O>; +pub type INT9_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT10` reader - Interrupt 10"] -pub type INT10_R = crate::FieldReader; +pub type INT10_R = crate::FieldReader; #[doc = "Field `INT10` writer - Interrupt 10"] -pub type INT10_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR2_SPEC, u8, u8, 8, O>; +pub type INT10_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT11` reader - Interrupt 11"] -pub type INT11_R = crate::FieldReader; +pub type INT11_R = crate::FieldReader; #[doc = "Field `INT11` writer - Interrupt 11"] -pub type INT11_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR2_SPEC, u8, u8, 8, O>; +pub type INT11_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 8"] #[inline(always)] @@ -74,50 +40,66 @@ impl R { INT11_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR2") + .field("int8", &format_args!("{}", self.int8().bits())) + .field("int9", &format_args!("{}", self.int9().bits())) + .field("int10", &format_args!("{}", self.int10().bits())) + .field("int11", &format_args!("{}", self.int11().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 8"] #[inline(always)] #[must_use] - pub fn int8(&mut self) -> INT8_W<0> { + pub fn int8(&mut self) -> INT8_W { INT8_W::new(self) } #[doc = "Bits 8:15 - Interrupt 9"] #[inline(always)] #[must_use] - pub fn int9(&mut self) -> INT9_W<8> { + pub fn int9(&mut self) -> INT9_W { INT9_W::new(self) } #[doc = "Bits 16:23 - Interrupt 10"] #[inline(always)] #[must_use] - pub fn int10(&mut self) -> INT10_W<16> { + pub fn int10(&mut self) -> INT10_W { INT10_W::new(self) } #[doc = "Bits 24:31 - Interrupt 11"] #[inline(always)] #[must_use] - pub fn int11(&mut self) -> INT11_W<24> { + pub fn int11(&mut self) -> INT11_W { INT11_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 8 - 11 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr2](index.html) module"] +#[doc = "Interrupt Priority 8 - 11 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR2_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr2::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr2::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr2::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr2::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr20.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr20.rs index 37a9dcc..b13c5a6 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr20.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr20.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR20` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR20` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT80` reader - Interrupt 80"] -pub type INT80_R = crate::FieldReader; +pub type INT80_R = crate::FieldReader; #[doc = "Field `INT80` writer - Interrupt 80"] -pub type INT80_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR20_SPEC, u8, u8, 8, O>; +pub type INT80_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT81` reader - Interrupt 81"] -pub type INT81_R = crate::FieldReader; +pub type INT81_R = crate::FieldReader; #[doc = "Field `INT81` writer - Interrupt 81"] -pub type INT81_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR20_SPEC, u8, u8, 8, O>; +pub type INT81_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT82` reader - Interrupt 82"] -pub type INT82_R = crate::FieldReader; +pub type INT82_R = crate::FieldReader; #[doc = "Field `INT82` writer - Interrupt 82"] -pub type INT82_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR20_SPEC, u8, u8, 8, O>; +pub type INT82_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT83` reader - Interrupt 83"] -pub type INT83_R = crate::FieldReader; +pub type INT83_R = crate::FieldReader; #[doc = "Field `INT83` writer - Interrupt 83"] -pub type INT83_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR20_SPEC, u8, u8, 8, O>; +pub type INT83_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 80"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT83_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR20") + .field("int80", &format_args!("{}", self.int80().bits())) + .field("int81", &format_args!("{}", self.int81().bits())) + .field("int82", &format_args!("{}", self.int82().bits())) + .field("int83", &format_args!("{}", self.int83().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 80"] #[inline(always)] #[must_use] - pub fn int80(&mut self) -> INT80_W<0> { + pub fn int80(&mut self) -> INT80_W { INT80_W::new(self) } #[doc = "Bits 8:15 - Interrupt 81"] #[inline(always)] #[must_use] - pub fn int81(&mut self) -> INT81_W<8> { + pub fn int81(&mut self) -> INT81_W { INT81_W::new(self) } #[doc = "Bits 16:23 - Interrupt 82"] #[inline(always)] #[must_use] - pub fn int82(&mut self) -> INT82_W<16> { + pub fn int82(&mut self) -> INT82_W { INT82_W::new(self) } #[doc = "Bits 24:31 - Interrupt 83"] #[inline(always)] #[must_use] - pub fn int83(&mut self) -> INT83_W<24> { + pub fn int83(&mut self) -> INT83_W { INT83_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 80 - 83 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr20](index.html) module"] +#[doc = "Interrupt Priority 80 - 83 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr20::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr20::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR20_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR20_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr20::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR20_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr20::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr20::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR20_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr20::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR20_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr21.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr21.rs index 7b48d2c..f7c67a7 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr21.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr21.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR21` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR21` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT84` reader - Interrupt 84"] -pub type INT84_R = crate::FieldReader; +pub type INT84_R = crate::FieldReader; #[doc = "Field `INT84` writer - Interrupt 84"] -pub type INT84_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR21_SPEC, u8, u8, 8, O>; +pub type INT84_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT85` reader - Interrupt 85"] -pub type INT85_R = crate::FieldReader; +pub type INT85_R = crate::FieldReader; #[doc = "Field `INT85` writer - Interrupt 85"] -pub type INT85_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR21_SPEC, u8, u8, 8, O>; +pub type INT85_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT86` reader - Interrupt 86"] -pub type INT86_R = crate::FieldReader; +pub type INT86_R = crate::FieldReader; #[doc = "Field `INT86` writer - Interrupt 86"] -pub type INT86_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR21_SPEC, u8, u8, 8, O>; +pub type INT86_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT87` reader - Interrupt 87"] -pub type INT87_R = crate::FieldReader; +pub type INT87_R = crate::FieldReader; #[doc = "Field `INT87` writer - Interrupt 87"] -pub type INT87_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR21_SPEC, u8, u8, 8, O>; +pub type INT87_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 84"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT87_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR21") + .field("int84", &format_args!("{}", self.int84().bits())) + .field("int85", &format_args!("{}", self.int85().bits())) + .field("int86", &format_args!("{}", self.int86().bits())) + .field("int87", &format_args!("{}", self.int87().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 84"] #[inline(always)] #[must_use] - pub fn int84(&mut self) -> INT84_W<0> { + pub fn int84(&mut self) -> INT84_W { INT84_W::new(self) } #[doc = "Bits 8:15 - Interrupt 85"] #[inline(always)] #[must_use] - pub fn int85(&mut self) -> INT85_W<8> { + pub fn int85(&mut self) -> INT85_W { INT85_W::new(self) } #[doc = "Bits 16:23 - Interrupt 86"] #[inline(always)] #[must_use] - pub fn int86(&mut self) -> INT86_W<16> { + pub fn int86(&mut self) -> INT86_W { INT86_W::new(self) } #[doc = "Bits 24:31 - Interrupt 87"] #[inline(always)] #[must_use] - pub fn int87(&mut self) -> INT87_W<24> { + pub fn int87(&mut self) -> INT87_W { INT87_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 84 - 87 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr21](index.html) module"] +#[doc = "Interrupt Priority 84 - 87 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr21::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr21::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR21_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR21_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr21::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR21_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr21::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr21::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR21_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr21::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR21_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr22.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr22.rs index f685300..ac598d4 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr22.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr22.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR22` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR22` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT88` reader - Interrupt 88"] -pub type INT88_R = crate::FieldReader; +pub type INT88_R = crate::FieldReader; #[doc = "Field `INT88` writer - Interrupt 88"] -pub type INT88_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR22_SPEC, u8, u8, 8, O>; +pub type INT88_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT89` reader - Interrupt 89"] -pub type INT89_R = crate::FieldReader; +pub type INT89_R = crate::FieldReader; #[doc = "Field `INT89` writer - Interrupt 89"] -pub type INT89_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR22_SPEC, u8, u8, 8, O>; +pub type INT89_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT90` reader - Interrupt 90"] -pub type INT90_R = crate::FieldReader; +pub type INT90_R = crate::FieldReader; #[doc = "Field `INT90` writer - Interrupt 90"] -pub type INT90_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR22_SPEC, u8, u8, 8, O>; +pub type INT90_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT91` reader - Interrupt 91"] -pub type INT91_R = crate::FieldReader; +pub type INT91_R = crate::FieldReader; #[doc = "Field `INT91` writer - Interrupt 91"] -pub type INT91_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR22_SPEC, u8, u8, 8, O>; +pub type INT91_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 88"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT91_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR22") + .field("int88", &format_args!("{}", self.int88().bits())) + .field("int89", &format_args!("{}", self.int89().bits())) + .field("int90", &format_args!("{}", self.int90().bits())) + .field("int91", &format_args!("{}", self.int91().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 88"] #[inline(always)] #[must_use] - pub fn int88(&mut self) -> INT88_W<0> { + pub fn int88(&mut self) -> INT88_W { INT88_W::new(self) } #[doc = "Bits 8:15 - Interrupt 89"] #[inline(always)] #[must_use] - pub fn int89(&mut self) -> INT89_W<8> { + pub fn int89(&mut self) -> INT89_W { INT89_W::new(self) } #[doc = "Bits 16:23 - Interrupt 90"] #[inline(always)] #[must_use] - pub fn int90(&mut self) -> INT90_W<16> { + pub fn int90(&mut self) -> INT90_W { INT90_W::new(self) } #[doc = "Bits 24:31 - Interrupt 91"] #[inline(always)] #[must_use] - pub fn int91(&mut self) -> INT91_W<24> { + pub fn int91(&mut self) -> INT91_W { INT91_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 88 - 91 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr22](index.html) module"] +#[doc = "Interrupt Priority 88 - 91 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr22::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr22::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR22_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR22_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr22::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR22_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr22::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr22::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR22_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr22::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR22_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr23.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr23.rs index 8e51a9d..ff696d9 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr23.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr23.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR23` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR23` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT92` reader - Interrupt 92"] -pub type INT92_R = crate::FieldReader; +pub type INT92_R = crate::FieldReader; #[doc = "Field `INT92` writer - Interrupt 92"] -pub type INT92_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR23_SPEC, u8, u8, 8, O>; +pub type INT92_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT93` reader - Interrupt 93"] -pub type INT93_R = crate::FieldReader; +pub type INT93_R = crate::FieldReader; #[doc = "Field `INT93` writer - Interrupt 93"] -pub type INT93_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR23_SPEC, u8, u8, 8, O>; +pub type INT93_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT94` reader - Interrupt 94"] -pub type INT94_R = crate::FieldReader; +pub type INT94_R = crate::FieldReader; #[doc = "Field `INT94` writer - Interrupt 94"] -pub type INT94_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR23_SPEC, u8, u8, 8, O>; +pub type INT94_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT95` reader - Interrupt 95"] -pub type INT95_R = crate::FieldReader; +pub type INT95_R = crate::FieldReader; #[doc = "Field `INT95` writer - Interrupt 95"] -pub type INT95_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR23_SPEC, u8, u8, 8, O>; +pub type INT95_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 92"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT95_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR23") + .field("int92", &format_args!("{}", self.int92().bits())) + .field("int93", &format_args!("{}", self.int93().bits())) + .field("int94", &format_args!("{}", self.int94().bits())) + .field("int95", &format_args!("{}", self.int95().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 92"] #[inline(always)] #[must_use] - pub fn int92(&mut self) -> INT92_W<0> { + pub fn int92(&mut self) -> INT92_W { INT92_W::new(self) } #[doc = "Bits 8:15 - Interrupt 93"] #[inline(always)] #[must_use] - pub fn int93(&mut self) -> INT93_W<8> { + pub fn int93(&mut self) -> INT93_W { INT93_W::new(self) } #[doc = "Bits 16:23 - Interrupt 94"] #[inline(always)] #[must_use] - pub fn int94(&mut self) -> INT94_W<16> { + pub fn int94(&mut self) -> INT94_W { INT94_W::new(self) } #[doc = "Bits 24:31 - Interrupt 95"] #[inline(always)] #[must_use] - pub fn int95(&mut self) -> INT95_W<24> { + pub fn int95(&mut self) -> INT95_W { INT95_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 92 - 95 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr23](index.html) module"] +#[doc = "Interrupt Priority 92 - 95 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr23::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr23::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR23_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR23_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr23::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR23_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr23::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr23::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR23_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr23::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR23_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr24.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr24.rs index 50266ea..b1be94e 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr24.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr24.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR24` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR24` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::FieldReader; +pub type TIMER_0_R = crate::FieldReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR24_SPEC, u8, u8, 8, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::FieldReader; +pub type TIMER_1_R = crate::FieldReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR24_SPEC, u8, u8, 8, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::FieldReader; +pub type TIMER_2_R = crate::FieldReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR24_SPEC, u8, u8, 8, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::FieldReader; +pub type TIMER_3_R = crate::FieldReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR24_SPEC, u8, u8, 8, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Timer 0"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { TIMER_3_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR24") + .field("timer_0", &format_args!("{}", self.timer_0().bits())) + .field("timer_1", &format_args!("{}", self.timer_1().bits())) + .field("timer_2", &format_args!("{}", self.timer_2().bits())) + .field("timer_3", &format_args!("{}", self.timer_3().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bits 8:15 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<8> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bits 16:23 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<16> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bits 24:31 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<24> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 96 - 99 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr24](index.html) module"] +#[doc = "Interrupt Priority 96 - 99 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr24::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr24::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR24_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR24_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr24::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR24_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr24::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr24::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR24_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr24::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR24_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr25.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr25.rs index 4b641b7..8ab82f2 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr25.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr25.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR25` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR25` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::FieldReader; +pub type H264_0_R = crate::FieldReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR25_SPEC, u8, u8, 8, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::FieldReader; +pub type H264_1_R = crate::FieldReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR25_SPEC, u8, u8, 8, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::FieldReader; +pub type H264_2_R = crate::FieldReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR25_SPEC, u8, u8, 8, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::FieldReader; +pub type JPEG_R = crate::FieldReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR25_SPEC, u8, u8, 8, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - H264 0"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { JPEG_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR25") + .field("h264_0", &format_args!("{}", self.h264_0().bits())) + .field("h264_1", &format_args!("{}", self.h264_1().bits())) + .field("h264_2", &format_args!("{}", self.h264_2().bits())) + .field("jpeg", &format_args!("{}", self.jpeg().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<0> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bits 8:15 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<8> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bits 16:23 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<16> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bits 24:31 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<24> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 100 - 103 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr25](index.html) module"] +#[doc = "Interrupt Priority 100 - 103 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr25::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr25::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR25_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR25_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr25::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR25_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr25::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr25::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR25_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr25::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR25_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr26.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr26.rs index eb37a1c..856c96d 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr26.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr26.rs @@ -1,56 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR26` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR26` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::FieldReader; +pub type ISP_R = crate::FieldReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR26_SPEC, u8, u8, 8, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::FieldReader; +pub type USB_R = crate::FieldReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR26_SPEC, u8, u8, 8, O>; +pub type USB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::FieldReader; +pub type V3D_R = crate::FieldReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR26_SPEC, u8, u8, 8, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::FieldReader; +pub type TRANSPOSER_R = crate::FieldReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR26_SPEC, u8, u8, 8, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - ISP"] #[inline(always)] @@ -73,50 +40,66 @@ impl R { TRANSPOSER_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR26") + .field("isp", &format_args!("{}", self.isp().bits())) + .field("usb", &format_args!("{}", self.usb().bits())) + .field("v3d", &format_args!("{}", self.v3d().bits())) + .field("transposer", &format_args!("{}", self.transposer().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<0> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bits 8:15 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<8> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bits 16:23 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<16> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bits 24:31 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<24> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 104 - 107 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr26](index.html) module"] +#[doc = "Interrupt Priority 104 - 107 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr26::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr26::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR26_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR26_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr26::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR26_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr26::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr26::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR26_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr26::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR26_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr27.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr27.rs index bc2edba..1e0fe8c 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr27.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr27.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR27` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR27` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::FieldReader; +pub type MULTICORE_SYNC_0_R = crate::FieldReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR27_SPEC, u8, u8, 8, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::FieldReader; +pub type MULTICORE_SYNC_1_R = crate::FieldReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR27_SPEC, u8, u8, 8, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::FieldReader; +pub type MULTICORE_SYNC_2_R = crate::FieldReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR27_SPEC, u8, u8, 8, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::FieldReader; +pub type MULTICORE_SYNC_3_R = crate::FieldReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR27_SPEC, u8, u8, 8, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Multicore Sync 0"] #[inline(always)] @@ -76,50 +40,78 @@ impl R { MULTICORE_SYNC_3_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR27") + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bits()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bits()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bits()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<0> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bits 8:15 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<8> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bits 16:23 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<16> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bits 24:31 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<24> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 108 - 111 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr27](index.html) module"] +#[doc = "Interrupt Priority 108 - 111 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr27::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr27::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR27_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR27_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr27::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR27_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr27::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr27::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR27_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr27::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR27_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr28.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr28.rs index 3d2a0de..5a91734 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr28.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr28.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR28` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR28` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::FieldReader; +pub type DMA_0_R = crate::FieldReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR28_SPEC, u8, u8, 8, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::FieldReader; +pub type DMA_1_R = crate::FieldReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR28_SPEC, u8, u8, 8, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::FieldReader; +pub type DMA_2_R = crate::FieldReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR28_SPEC, u8, u8, 8, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::FieldReader; +pub type DMA_3_R = crate::FieldReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR28_SPEC, u8, u8, 8, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - DMA 0"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { DMA_3_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR28") + .field("dma_0", &format_args!("{}", self.dma_0().bits())) + .field("dma_1", &format_args!("{}", self.dma_1().bits())) + .field("dma_2", &format_args!("{}", self.dma_2().bits())) + .field("dma_3", &format_args!("{}", self.dma_3().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<0> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bits 8:15 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<8> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bits 16:23 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<16> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bits 24:31 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<24> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 112 - 115 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr28](index.html) module"] +#[doc = "Interrupt Priority 112 - 115 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr28::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr28::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR28_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR28_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr28::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR28_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr28::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr28::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR28_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr28::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR28_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr29.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr29.rs index 6af1747..b951ca4 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr29.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr29.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR29` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR29` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::FieldReader; +pub type DMA_4_R = crate::FieldReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR29_SPEC, u8, u8, 8, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::FieldReader; +pub type DMA_5_R = crate::FieldReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR29_SPEC, u8, u8, 8, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::FieldReader; +pub type DMA_6_R = crate::FieldReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR29_SPEC, u8, u8, 8, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::FieldReader; +pub type DMA_7_8_R = crate::FieldReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR29_SPEC, u8, u8, 8, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - DMA 4"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { DMA_7_8_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR29") + .field("dma_4", &format_args!("{}", self.dma_4().bits())) + .field("dma_5", &format_args!("{}", self.dma_5().bits())) + .field("dma_6", &format_args!("{}", self.dma_6().bits())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<0> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bits 8:15 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<8> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bits 16:23 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<16> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bits 24:31 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<24> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 116 - 119 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr29](index.html) module"] +#[doc = "Interrupt Priority 116 - 119 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr29::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr29::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR29_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR29_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr29::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR29_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr29::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr29::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR29_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr29::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR29_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr3.rs index 51f3ec6..3bd4feb 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr3.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr3.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT12` reader - Interrupt 12"] -pub type INT12_R = crate::FieldReader; +pub type INT12_R = crate::FieldReader; #[doc = "Field `INT12` writer - Interrupt 12"] -pub type INT12_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR3_SPEC, u8, u8, 8, O>; +pub type INT12_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT13` reader - Interrupt 13"] -pub type INT13_R = crate::FieldReader; +pub type INT13_R = crate::FieldReader; #[doc = "Field `INT13` writer - Interrupt 13"] -pub type INT13_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR3_SPEC, u8, u8, 8, O>; +pub type INT13_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT14` reader - Interrupt 14"] -pub type INT14_R = crate::FieldReader; +pub type INT14_R = crate::FieldReader; #[doc = "Field `INT14` writer - Interrupt 14"] -pub type INT14_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR3_SPEC, u8, u8, 8, O>; +pub type INT14_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT15` reader - Interrupt 15"] -pub type INT15_R = crate::FieldReader; +pub type INT15_R = crate::FieldReader; #[doc = "Field `INT15` writer - Interrupt 15"] -pub type INT15_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR3_SPEC, u8, u8, 8, O>; +pub type INT15_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 12"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT15_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR3") + .field("int12", &format_args!("{}", self.int12().bits())) + .field("int13", &format_args!("{}", self.int13().bits())) + .field("int14", &format_args!("{}", self.int14().bits())) + .field("int15", &format_args!("{}", self.int15().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 12"] #[inline(always)] #[must_use] - pub fn int12(&mut self) -> INT12_W<0> { + pub fn int12(&mut self) -> INT12_W { INT12_W::new(self) } #[doc = "Bits 8:15 - Interrupt 13"] #[inline(always)] #[must_use] - pub fn int13(&mut self) -> INT13_W<8> { + pub fn int13(&mut self) -> INT13_W { INT13_W::new(self) } #[doc = "Bits 16:23 - Interrupt 14"] #[inline(always)] #[must_use] - pub fn int14(&mut self) -> INT14_W<16> { + pub fn int14(&mut self) -> INT14_W { INT14_W::new(self) } #[doc = "Bits 24:31 - Interrupt 15"] #[inline(always)] #[must_use] - pub fn int15(&mut self) -> INT15_W<24> { + pub fn int15(&mut self) -> INT15_W { INT15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 12 - 15 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr3](index.html) module"] +#[doc = "Interrupt Priority 12 - 15 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR3_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr3::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr3::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr3::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr3::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr30.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr30.rs index 033026a..302ff75 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr30.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr30.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR30` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR30` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::FieldReader; +pub type DMA_9_10_R = crate::FieldReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR30_SPEC, u8, u8, 8, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::FieldReader; +pub type DMA_11_R = crate::FieldReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR30_SPEC, u8, u8, 8, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::FieldReader; +pub type DMA_12_R = crate::FieldReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR30_SPEC, u8, u8, 8, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::FieldReader; +pub type DMA_13_R = crate::FieldReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR30_SPEC, u8, u8, 8, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - OR of DMA 9 and 10"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { DMA_13_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR30") + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bits())) + .field("dma_11", &format_args!("{}", self.dma_11().bits())) + .field("dma_12", &format_args!("{}", self.dma_12().bits())) + .field("dma_13", &format_args!("{}", self.dma_13().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<0> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bits 8:15 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<8> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bits 16:23 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<16> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bits 24:31 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<24> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 120 - 123 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr30](index.html) module"] +#[doc = "Interrupt Priority 120 - 123 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr30::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr30::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR30_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR30_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr30::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR30_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr30::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr30::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR30_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr30::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR30_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr31.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr31.rs index 1f826ee..df4d600 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr31.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr31.rs @@ -1,57 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR31` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR31` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::FieldReader; +pub type DMA_14_R = crate::FieldReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR31_SPEC, u8, u8, 8, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::FieldReader; +pub type AUX_R = crate::FieldReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR31_SPEC, u8, u8, 8, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::FieldReader; +pub type ARM_R = crate::FieldReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR31_SPEC, u8, u8, 8, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::FieldReader; +pub type DMA_15_R = crate::FieldReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR31_SPEC, u8, u8, 8, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - DMA 14"] #[inline(always)] @@ -74,50 +40,66 @@ impl R { DMA_15_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR31") + .field("dma_14", &format_args!("{}", self.dma_14().bits())) + .field("aux", &format_args!("{}", self.aux().bits())) + .field("arm", &format_args!("{}", self.arm().bits())) + .field("dma_15", &format_args!("{}", self.dma_15().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<0> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bits 8:15 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<8> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bits 16:23 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<16> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bits 24:31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<24> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 124 - 127 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr31](index.html) module"] +#[doc = "Interrupt Priority 124 - 127 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr31::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr31::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR31_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR31_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr31::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR31_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr31::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr31::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR31_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr31::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR31_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr32.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr32.rs index 48637f3..1e1fd99 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr32.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr32.rs @@ -1,57 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR32` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR32` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::FieldReader; +pub type HDMI_CEC_R = crate::FieldReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR32_SPEC, u8, u8, 8, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::FieldReader; +pub type HVS_R = crate::FieldReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR32_SPEC, u8, u8, 8, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::FieldReader; +pub type RPIVID_R = crate::FieldReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR32_SPEC, u8, u8, 8, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::FieldReader; +pub type SDC_R = crate::FieldReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR32_SPEC, u8, u8, 8, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - HDMI CEC"] #[inline(always)] @@ -74,50 +40,66 @@ impl R { SDC_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR32") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bits())) + .field("hvs", &format_args!("{}", self.hvs().bits())) + .field("rpivid", &format_args!("{}", self.rpivid().bits())) + .field("sdc", &format_args!("{}", self.sdc().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bits 8:15 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<8> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bits 16:23 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<16> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bits 24:31 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<24> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 128 - 131 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr32](index.html) module"] +#[doc = "Interrupt Priority 128 - 131 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr32::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr32::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR32_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR32_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr32::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR32_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr32::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr32::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR32_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr32::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR32_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr33.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr33.rs index ea20e5c..6b3a086 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr33.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr33.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR33` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR33` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::FieldReader; +pub type DSI_0_R = crate::FieldReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR33_SPEC, u8, u8, 8, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::FieldReader; +pub type PIXEL_VALVE_2_R = crate::FieldReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR33_SPEC, u8, u8, 8, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::FieldReader; +pub type CAMERA_0_R = crate::FieldReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR33_SPEC, u8, u8, 8, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::FieldReader; +pub type CAMERA_1_R = crate::FieldReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR33_SPEC, u8, u8, 8, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - DSI 0"] #[inline(always)] @@ -76,50 +40,69 @@ impl R { CAMERA_1_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR33") + .field("dsi_0", &format_args!("{}", self.dsi_0().bits())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bits()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bits())) + .field("camera_1", &format_args!("{}", self.camera_1().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<0> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bits 8:15 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<8> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bits 16:23 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<16> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bits 24:31 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<24> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 132 - 135 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr33](index.html) module"] +#[doc = "Interrupt Priority 132 - 135 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr33::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr33::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR33_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR33_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr33::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR33_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr33::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr33::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR33_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr33::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR33_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr34.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr34.rs index 4f20607..615851a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr34.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr34.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR34` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR34` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::FieldReader; +pub type HDMI_0_R = crate::FieldReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR34_SPEC, u8, u8, 8, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::FieldReader; +pub type HDMI_1_R = crate::FieldReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR34_SPEC, u8, u8, 8, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::FieldReader; +pub type PIXEL_VALVE_3_R = crate::FieldReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR34_SPEC, u8, u8, 8, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::FieldReader; +pub type SPI_BSC_SLAVE_R = crate::FieldReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR34_SPEC, u8, u8, 8, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - HDMI 0"] #[inline(always)] @@ -76,50 +40,72 @@ impl R { SPI_BSC_SLAVE_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR34") + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bits())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bits())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bits()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<0> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bits 8:15 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<8> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bits 16:23 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<16> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bits 24:31 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<24> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 136 - 139 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr34](index.html) module"] +#[doc = "Interrupt Priority 136 - 139 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr34::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr34::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR34_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR34_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr34::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR34_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr34::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr34::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR34_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr34::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR34_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr35.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr35.rs index 39dabab..c4e5531 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr35.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr35.rs @@ -1,58 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR35` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR35` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::FieldReader; +pub type DSI_1_R = crate::FieldReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR35_SPEC, u8, u8, 8, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::FieldReader; +pub type PIXEL_VALVE_0_R = crate::FieldReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR35_SPEC, u8, u8, 8, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::FieldReader; +pub type PIXEL_VALVE_1_2_R = crate::FieldReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR35_SPEC, u8, u8, 8, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::FieldReader; +pub type CPR_R = crate::FieldReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR35_SPEC, u8, u8, 8, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - DSI 1"] #[inline(always)] @@ -75,50 +40,72 @@ impl R { CPR_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR35") + .field("dsi_1", &format_args!("{}", self.dsi_1().bits())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bits()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bits()), + ) + .field("cpr", &format_args!("{}", self.cpr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<0> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bits 8:15 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<8> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bits 16:23 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<16> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bits 24:31 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<24> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 140 - 143 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr35](index.html) module"] +#[doc = "Interrupt Priority 140 - 143 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr35::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr35::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR35_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR35_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr35::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR35_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr35::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr35::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR35_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr35::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR35_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr36.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr36.rs index a371367..d0d5b86 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr36.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr36.rs @@ -1,58 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR36` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR36` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::FieldReader; +pub type SMI_R = crate::FieldReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR36_SPEC, u8, u8, 8, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::FieldReader; +pub type GPIO_0_R = crate::FieldReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR36_SPEC, u8, u8, 8, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::FieldReader; +pub type GPIO_1_R = crate::FieldReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR36_SPEC, u8, u8, 8, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::FieldReader; +pub type GPIO_2_R = crate::FieldReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR36_SPEC, u8, u8, 8, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - SMI"] #[inline(always)] @@ -75,50 +40,66 @@ impl R { GPIO_2_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR36") + .field("smi", &format_args!("{}", self.smi().bits())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bits())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bits())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<0> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bits 8:15 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<8> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bits 16:23 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<16> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bits 24:31 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<24> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 144 - 147 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr36](index.html) module"] +#[doc = "Interrupt Priority 144 - 147 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr36::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr36::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR36_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR36_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr36::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR36_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr36::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr36::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR36_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr36::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR36_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr37.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr37.rs index cac90f2..146e8cc 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr37.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr37.rs @@ -1,57 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR37` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR37` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::FieldReader; +pub type GPIO_3_R = crate::FieldReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR37_SPEC, u8, u8, 8, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::FieldReader; +pub type I2C_R = crate::FieldReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR37_SPEC, u8, u8, 8, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::FieldReader; +pub type SPI_R = crate::FieldReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR37_SPEC, u8, u8, 8, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::FieldReader; +pub type PCM_I2S_R = crate::FieldReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR37_SPEC, u8, u8, 8, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - GPIO 3"] #[inline(always)] @@ -74,50 +40,66 @@ impl R { PCM_I2S_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR37") + .field("gpio_3", &format_args!("{}", self.gpio_3().bits())) + .field("i2c", &format_args!("{}", self.i2c().bits())) + .field("spi", &format_args!("{}", self.spi().bits())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<0> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bits 8:15 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<8> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bits 16:23 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<16> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bits 24:31 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<24> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 148 - 151 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr37](index.html) module"] +#[doc = "Interrupt Priority 148 - 151 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr37::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr37::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR37_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR37_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr37::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR37_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr37::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr37::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR37_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr37::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR37_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr38.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr38.rs index 3e53e17..9086dfd 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr38.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr38.rs @@ -1,58 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR38` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR38` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::FieldReader; +pub type SDHOST_R = crate::FieldReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR38_SPEC, u8, u8, 8, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::FieldReader; +pub type UART_R = crate::FieldReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR38_SPEC, u8, u8, 8, O>; +pub type UART_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::FieldReader; +pub type ETH_PCIE_R = crate::FieldReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR38_SPEC, u8, u8, 8, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::FieldReader; +pub type VEC_R = crate::FieldReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR38_SPEC, u8, u8, 8, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - SDHOST"] #[inline(always)] @@ -75,50 +40,66 @@ impl R { VEC_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR38") + .field("sdhost", &format_args!("{}", self.sdhost().bits())) + .field("uart", &format_args!("{}", self.uart().bits())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bits())) + .field("vec", &format_args!("{}", self.vec().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<0> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bits 8:15 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<8> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bits 16:23 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<16> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bits 24:31 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<24> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 152 - 155 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr38](index.html) module"] +#[doc = "Interrupt Priority 152 - 155 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr38::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr38::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR38_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR38_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr38::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR38_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr38::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr38::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR38_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr38::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR38_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr39.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr39.rs index 8f843ad..3d8944a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr39.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr39.rs @@ -1,57 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR39` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR39` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::FieldReader; +pub type CPG_R = crate::FieldReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR39_SPEC, u8, u8, 8, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::FieldReader; +pub type RNG_R = crate::FieldReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_IPRIORITYR39_SPEC, u8, u8, 8, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::FieldReader; +pub type EMMC_R = crate::FieldReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR39_SPEC, u8, u8, 8, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::FieldReader; +pub type ETH_PCIE_SECURE_R = crate::FieldReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR39_SPEC, u8, u8, 8, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - CPG"] #[inline(always)] @@ -74,50 +40,69 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR39") + .field("cpg", &format_args!("{}", self.cpg().bits())) + .field("rng", &format_args!("{}", self.rng().bits())) + .field("emmc", &format_args!("{}", self.emmc().bits())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<0> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bits 8:15 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<8> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bits 16:23 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<16> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bits 24:31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<24> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 156 - 159 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr39](index.html) module"] +#[doc = "Interrupt Priority 156 - 159 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr39::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr39::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR39_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR39_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr39::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR39_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr39::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr39::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR39_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr39::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR39_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr4.rs index b2f7304..070cbdf 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr4.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr4.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT16` reader - Interrupt 16"] -pub type INT16_R = crate::FieldReader; +pub type INT16_R = crate::FieldReader; #[doc = "Field `INT16` writer - Interrupt 16"] -pub type INT16_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR4_SPEC, u8, u8, 8, O>; +pub type INT16_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT17` reader - Interrupt 17"] -pub type INT17_R = crate::FieldReader; +pub type INT17_R = crate::FieldReader; #[doc = "Field `INT17` writer - Interrupt 17"] -pub type INT17_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR4_SPEC, u8, u8, 8, O>; +pub type INT17_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT18` reader - Interrupt 18"] -pub type INT18_R = crate::FieldReader; +pub type INT18_R = crate::FieldReader; #[doc = "Field `INT18` writer - Interrupt 18"] -pub type INT18_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR4_SPEC, u8, u8, 8, O>; +pub type INT18_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT19` reader - Interrupt 19"] -pub type INT19_R = crate::FieldReader; +pub type INT19_R = crate::FieldReader; #[doc = "Field `INT19` writer - Interrupt 19"] -pub type INT19_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR4_SPEC, u8, u8, 8, O>; +pub type INT19_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 16"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT19_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR4") + .field("int16", &format_args!("{}", self.int16().bits())) + .field("int17", &format_args!("{}", self.int17().bits())) + .field("int18", &format_args!("{}", self.int18().bits())) + .field("int19", &format_args!("{}", self.int19().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 16"] #[inline(always)] #[must_use] - pub fn int16(&mut self) -> INT16_W<0> { + pub fn int16(&mut self) -> INT16_W { INT16_W::new(self) } #[doc = "Bits 8:15 - Interrupt 17"] #[inline(always)] #[must_use] - pub fn int17(&mut self) -> INT17_W<8> { + pub fn int17(&mut self) -> INT17_W { INT17_W::new(self) } #[doc = "Bits 16:23 - Interrupt 18"] #[inline(always)] #[must_use] - pub fn int18(&mut self) -> INT18_W<16> { + pub fn int18(&mut self) -> INT18_W { INT18_W::new(self) } #[doc = "Bits 24:31 - Interrupt 19"] #[inline(always)] #[must_use] - pub fn int19(&mut self) -> INT19_W<24> { + pub fn int19(&mut self) -> INT19_W { INT19_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 16 - 19 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr4](index.html) module"] +#[doc = "Interrupt Priority 16 - 19 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR4_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr4::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr4::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr4::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr4::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr40.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr40.rs index 38b1963..a2a63d0 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr40.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr40.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR40` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR40` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT160` reader - Interrupt 160"] -pub type INT160_R = crate::FieldReader; +pub type INT160_R = crate::FieldReader; #[doc = "Field `INT160` writer - Interrupt 160"] -pub type INT160_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR40_SPEC, u8, u8, 8, O>; +pub type INT160_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT161` reader - Interrupt 161"] -pub type INT161_R = crate::FieldReader; +pub type INT161_R = crate::FieldReader; #[doc = "Field `INT161` writer - Interrupt 161"] -pub type INT161_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR40_SPEC, u8, u8, 8, O>; +pub type INT161_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT162` reader - Interrupt 162"] -pub type INT162_R = crate::FieldReader; +pub type INT162_R = crate::FieldReader; #[doc = "Field `INT162` writer - Interrupt 162"] -pub type INT162_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR40_SPEC, u8, u8, 8, O>; +pub type INT162_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT163` reader - Interrupt 163"] -pub type INT163_R = crate::FieldReader; +pub type INT163_R = crate::FieldReader; #[doc = "Field `INT163` writer - Interrupt 163"] -pub type INT163_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR40_SPEC, u8, u8, 8, O>; +pub type INT163_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 160"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT163_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR40") + .field("int160", &format_args!("{}", self.int160().bits())) + .field("int161", &format_args!("{}", self.int161().bits())) + .field("int162", &format_args!("{}", self.int162().bits())) + .field("int163", &format_args!("{}", self.int163().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 160"] #[inline(always)] #[must_use] - pub fn int160(&mut self) -> INT160_W<0> { + pub fn int160(&mut self) -> INT160_W { INT160_W::new(self) } #[doc = "Bits 8:15 - Interrupt 161"] #[inline(always)] #[must_use] - pub fn int161(&mut self) -> INT161_W<8> { + pub fn int161(&mut self) -> INT161_W { INT161_W::new(self) } #[doc = "Bits 16:23 - Interrupt 162"] #[inline(always)] #[must_use] - pub fn int162(&mut self) -> INT162_W<16> { + pub fn int162(&mut self) -> INT162_W { INT162_W::new(self) } #[doc = "Bits 24:31 - Interrupt 163"] #[inline(always)] #[must_use] - pub fn int163(&mut self) -> INT163_W<24> { + pub fn int163(&mut self) -> INT163_W { INT163_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 160 - 163 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr40](index.html) module"] +#[doc = "Interrupt Priority 160 - 163 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr40::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr40::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR40_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR40_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr40::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR40_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr40::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr40::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR40_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr40::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR40_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr41.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr41.rs index 8ad3688..2878594 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr41.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr41.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR41` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR41` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT164` reader - Interrupt 164"] -pub type INT164_R = crate::FieldReader; +pub type INT164_R = crate::FieldReader; #[doc = "Field `INT164` writer - Interrupt 164"] -pub type INT164_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR41_SPEC, u8, u8, 8, O>; +pub type INT164_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT165` reader - Interrupt 165"] -pub type INT165_R = crate::FieldReader; +pub type INT165_R = crate::FieldReader; #[doc = "Field `INT165` writer - Interrupt 165"] -pub type INT165_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR41_SPEC, u8, u8, 8, O>; +pub type INT165_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT166` reader - Interrupt 166"] -pub type INT166_R = crate::FieldReader; +pub type INT166_R = crate::FieldReader; #[doc = "Field `INT166` writer - Interrupt 166"] -pub type INT166_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR41_SPEC, u8, u8, 8, O>; +pub type INT166_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT167` reader - Interrupt 167"] -pub type INT167_R = crate::FieldReader; +pub type INT167_R = crate::FieldReader; #[doc = "Field `INT167` writer - Interrupt 167"] -pub type INT167_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR41_SPEC, u8, u8, 8, O>; +pub type INT167_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 164"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT167_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR41") + .field("int164", &format_args!("{}", self.int164().bits())) + .field("int165", &format_args!("{}", self.int165().bits())) + .field("int166", &format_args!("{}", self.int166().bits())) + .field("int167", &format_args!("{}", self.int167().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 164"] #[inline(always)] #[must_use] - pub fn int164(&mut self) -> INT164_W<0> { + pub fn int164(&mut self) -> INT164_W { INT164_W::new(self) } #[doc = "Bits 8:15 - Interrupt 165"] #[inline(always)] #[must_use] - pub fn int165(&mut self) -> INT165_W<8> { + pub fn int165(&mut self) -> INT165_W { INT165_W::new(self) } #[doc = "Bits 16:23 - Interrupt 166"] #[inline(always)] #[must_use] - pub fn int166(&mut self) -> INT166_W<16> { + pub fn int166(&mut self) -> INT166_W { INT166_W::new(self) } #[doc = "Bits 24:31 - Interrupt 167"] #[inline(always)] #[must_use] - pub fn int167(&mut self) -> INT167_W<24> { + pub fn int167(&mut self) -> INT167_W { INT167_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 164 - 167 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr41](index.html) module"] +#[doc = "Interrupt Priority 164 - 167 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr41::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr41::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR41_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR41_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr41::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR41_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr41::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr41::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR41_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr41::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR41_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr42.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr42.rs index 38fa882..5f84ad2 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr42.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr42.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR42` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR42` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT168` reader - Interrupt 168"] -pub type INT168_R = crate::FieldReader; +pub type INT168_R = crate::FieldReader; #[doc = "Field `INT168` writer - Interrupt 168"] -pub type INT168_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR42_SPEC, u8, u8, 8, O>; +pub type INT168_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT169` reader - Interrupt 169"] -pub type INT169_R = crate::FieldReader; +pub type INT169_R = crate::FieldReader; #[doc = "Field `INT169` writer - Interrupt 169"] -pub type INT169_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR42_SPEC, u8, u8, 8, O>; +pub type INT169_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT170` reader - Interrupt 170"] -pub type INT170_R = crate::FieldReader; +pub type INT170_R = crate::FieldReader; #[doc = "Field `INT170` writer - Interrupt 170"] -pub type INT170_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR42_SPEC, u8, u8, 8, O>; +pub type INT170_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT171` reader - Interrupt 171"] -pub type INT171_R = crate::FieldReader; +pub type INT171_R = crate::FieldReader; #[doc = "Field `INT171` writer - Interrupt 171"] -pub type INT171_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR42_SPEC, u8, u8, 8, O>; +pub type INT171_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 168"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT171_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR42") + .field("int168", &format_args!("{}", self.int168().bits())) + .field("int169", &format_args!("{}", self.int169().bits())) + .field("int170", &format_args!("{}", self.int170().bits())) + .field("int171", &format_args!("{}", self.int171().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 168"] #[inline(always)] #[must_use] - pub fn int168(&mut self) -> INT168_W<0> { + pub fn int168(&mut self) -> INT168_W { INT168_W::new(self) } #[doc = "Bits 8:15 - Interrupt 169"] #[inline(always)] #[must_use] - pub fn int169(&mut self) -> INT169_W<8> { + pub fn int169(&mut self) -> INT169_W { INT169_W::new(self) } #[doc = "Bits 16:23 - Interrupt 170"] #[inline(always)] #[must_use] - pub fn int170(&mut self) -> INT170_W<16> { + pub fn int170(&mut self) -> INT170_W { INT170_W::new(self) } #[doc = "Bits 24:31 - Interrupt 171"] #[inline(always)] #[must_use] - pub fn int171(&mut self) -> INT171_W<24> { + pub fn int171(&mut self) -> INT171_W { INT171_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 168 - 171 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr42](index.html) module"] +#[doc = "Interrupt Priority 168 - 171 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr42::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr42::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR42_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR42_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr42::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR42_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr42::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr42::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR42_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr42::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR42_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr43.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr43.rs index 126b6c7..4622c47 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr43.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr43.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR43` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR43` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT172` reader - Interrupt 172"] -pub type INT172_R = crate::FieldReader; +pub type INT172_R = crate::FieldReader; #[doc = "Field `INT172` writer - Interrupt 172"] -pub type INT172_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR43_SPEC, u8, u8, 8, O>; +pub type INT172_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT173` reader - Interrupt 173"] -pub type INT173_R = crate::FieldReader; +pub type INT173_R = crate::FieldReader; #[doc = "Field `INT173` writer - Interrupt 173"] -pub type INT173_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR43_SPEC, u8, u8, 8, O>; +pub type INT173_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT174` reader - Interrupt 174"] -pub type INT174_R = crate::FieldReader; +pub type INT174_R = crate::FieldReader; #[doc = "Field `INT174` writer - Interrupt 174"] -pub type INT174_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR43_SPEC, u8, u8, 8, O>; +pub type INT174_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT175` reader - Interrupt 175"] -pub type INT175_R = crate::FieldReader; +pub type INT175_R = crate::FieldReader; #[doc = "Field `INT175` writer - Interrupt 175"] -pub type INT175_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR43_SPEC, u8, u8, 8, O>; +pub type INT175_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 172"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT175_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR43") + .field("int172", &format_args!("{}", self.int172().bits())) + .field("int173", &format_args!("{}", self.int173().bits())) + .field("int174", &format_args!("{}", self.int174().bits())) + .field("int175", &format_args!("{}", self.int175().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 172"] #[inline(always)] #[must_use] - pub fn int172(&mut self) -> INT172_W<0> { + pub fn int172(&mut self) -> INT172_W { INT172_W::new(self) } #[doc = "Bits 8:15 - Interrupt 173"] #[inline(always)] #[must_use] - pub fn int173(&mut self) -> INT173_W<8> { + pub fn int173(&mut self) -> INT173_W { INT173_W::new(self) } #[doc = "Bits 16:23 - Interrupt 174"] #[inline(always)] #[must_use] - pub fn int174(&mut self) -> INT174_W<16> { + pub fn int174(&mut self) -> INT174_W { INT174_W::new(self) } #[doc = "Bits 24:31 - Interrupt 175"] #[inline(always)] #[must_use] - pub fn int175(&mut self) -> INT175_W<24> { + pub fn int175(&mut self) -> INT175_W { INT175_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 172 - 175 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr43](index.html) module"] +#[doc = "Interrupt Priority 172 - 175 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr43::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr43::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR43_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR43_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr43::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR43_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr43::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr43::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR43_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr43::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR43_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr44.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr44.rs index 9698e94..b6e59cb 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr44.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr44.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR44` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR44` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT176` reader - Interrupt 176"] -pub type INT176_R = crate::FieldReader; +pub type INT176_R = crate::FieldReader; #[doc = "Field `INT176` writer - Interrupt 176"] -pub type INT176_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR44_SPEC, u8, u8, 8, O>; +pub type INT176_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT177` reader - Interrupt 177"] -pub type INT177_R = crate::FieldReader; +pub type INT177_R = crate::FieldReader; #[doc = "Field `INT177` writer - Interrupt 177"] -pub type INT177_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR44_SPEC, u8, u8, 8, O>; +pub type INT177_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT178` reader - Interrupt 178"] -pub type INT178_R = crate::FieldReader; +pub type INT178_R = crate::FieldReader; #[doc = "Field `INT178` writer - Interrupt 178"] -pub type INT178_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR44_SPEC, u8, u8, 8, O>; +pub type INT178_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT179` reader - Interrupt 179"] -pub type INT179_R = crate::FieldReader; +pub type INT179_R = crate::FieldReader; #[doc = "Field `INT179` writer - Interrupt 179"] -pub type INT179_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR44_SPEC, u8, u8, 8, O>; +pub type INT179_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 176"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT179_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR44") + .field("int176", &format_args!("{}", self.int176().bits())) + .field("int177", &format_args!("{}", self.int177().bits())) + .field("int178", &format_args!("{}", self.int178().bits())) + .field("int179", &format_args!("{}", self.int179().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 176"] #[inline(always)] #[must_use] - pub fn int176(&mut self) -> INT176_W<0> { + pub fn int176(&mut self) -> INT176_W { INT176_W::new(self) } #[doc = "Bits 8:15 - Interrupt 177"] #[inline(always)] #[must_use] - pub fn int177(&mut self) -> INT177_W<8> { + pub fn int177(&mut self) -> INT177_W { INT177_W::new(self) } #[doc = "Bits 16:23 - Interrupt 178"] #[inline(always)] #[must_use] - pub fn int178(&mut self) -> INT178_W<16> { + pub fn int178(&mut self) -> INT178_W { INT178_W::new(self) } #[doc = "Bits 24:31 - Interrupt 179"] #[inline(always)] #[must_use] - pub fn int179(&mut self) -> INT179_W<24> { + pub fn int179(&mut self) -> INT179_W { INT179_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 176 - 179 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr44](index.html) module"] +#[doc = "Interrupt Priority 176 - 179 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr44::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr44::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR44_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR44_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr44::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR44_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr44::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr44::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR44_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr44::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR44_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr45.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr45.rs index b18c757..4adde4d 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr45.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr45.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR45` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR45` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT180` reader - Interrupt 180"] -pub type INT180_R = crate::FieldReader; +pub type INT180_R = crate::FieldReader; #[doc = "Field `INT180` writer - Interrupt 180"] -pub type INT180_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR45_SPEC, u8, u8, 8, O>; +pub type INT180_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT181` reader - Interrupt 181"] -pub type INT181_R = crate::FieldReader; +pub type INT181_R = crate::FieldReader; #[doc = "Field `INT181` writer - Interrupt 181"] -pub type INT181_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR45_SPEC, u8, u8, 8, O>; +pub type INT181_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT182` reader - Interrupt 182"] -pub type INT182_R = crate::FieldReader; +pub type INT182_R = crate::FieldReader; #[doc = "Field `INT182` writer - Interrupt 182"] -pub type INT182_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR45_SPEC, u8, u8, 8, O>; +pub type INT182_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT183` reader - Interrupt 183"] -pub type INT183_R = crate::FieldReader; +pub type INT183_R = crate::FieldReader; #[doc = "Field `INT183` writer - Interrupt 183"] -pub type INT183_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR45_SPEC, u8, u8, 8, O>; +pub type INT183_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 180"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT183_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR45") + .field("int180", &format_args!("{}", self.int180().bits())) + .field("int181", &format_args!("{}", self.int181().bits())) + .field("int182", &format_args!("{}", self.int182().bits())) + .field("int183", &format_args!("{}", self.int183().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 180"] #[inline(always)] #[must_use] - pub fn int180(&mut self) -> INT180_W<0> { + pub fn int180(&mut self) -> INT180_W { INT180_W::new(self) } #[doc = "Bits 8:15 - Interrupt 181"] #[inline(always)] #[must_use] - pub fn int181(&mut self) -> INT181_W<8> { + pub fn int181(&mut self) -> INT181_W { INT181_W::new(self) } #[doc = "Bits 16:23 - Interrupt 182"] #[inline(always)] #[must_use] - pub fn int182(&mut self) -> INT182_W<16> { + pub fn int182(&mut self) -> INT182_W { INT182_W::new(self) } #[doc = "Bits 24:31 - Interrupt 183"] #[inline(always)] #[must_use] - pub fn int183(&mut self) -> INT183_W<24> { + pub fn int183(&mut self) -> INT183_W { INT183_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 180 - 183 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr45](index.html) module"] +#[doc = "Interrupt Priority 180 - 183 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr45::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr45::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR45_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR45_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr45::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR45_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr45::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr45::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR45_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr45::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR45_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr46.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr46.rs index 032ba0d..c74e6ee 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr46.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr46.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR46` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR46` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT184` reader - Interrupt 184"] -pub type INT184_R = crate::FieldReader; +pub type INT184_R = crate::FieldReader; #[doc = "Field `INT184` writer - Interrupt 184"] -pub type INT184_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR46_SPEC, u8, u8, 8, O>; +pub type INT184_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT185` reader - Interrupt 185"] -pub type INT185_R = crate::FieldReader; +pub type INT185_R = crate::FieldReader; #[doc = "Field `INT185` writer - Interrupt 185"] -pub type INT185_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR46_SPEC, u8, u8, 8, O>; +pub type INT185_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT186` reader - Interrupt 186"] -pub type INT186_R = crate::FieldReader; +pub type INT186_R = crate::FieldReader; #[doc = "Field `INT186` writer - Interrupt 186"] -pub type INT186_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR46_SPEC, u8, u8, 8, O>; +pub type INT186_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT187` reader - Interrupt 187"] -pub type INT187_R = crate::FieldReader; +pub type INT187_R = crate::FieldReader; #[doc = "Field `INT187` writer - Interrupt 187"] -pub type INT187_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR46_SPEC, u8, u8, 8, O>; +pub type INT187_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 184"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT187_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR46") + .field("int184", &format_args!("{}", self.int184().bits())) + .field("int185", &format_args!("{}", self.int185().bits())) + .field("int186", &format_args!("{}", self.int186().bits())) + .field("int187", &format_args!("{}", self.int187().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 184"] #[inline(always)] #[must_use] - pub fn int184(&mut self) -> INT184_W<0> { + pub fn int184(&mut self) -> INT184_W { INT184_W::new(self) } #[doc = "Bits 8:15 - Interrupt 185"] #[inline(always)] #[must_use] - pub fn int185(&mut self) -> INT185_W<8> { + pub fn int185(&mut self) -> INT185_W { INT185_W::new(self) } #[doc = "Bits 16:23 - Interrupt 186"] #[inline(always)] #[must_use] - pub fn int186(&mut self) -> INT186_W<16> { + pub fn int186(&mut self) -> INT186_W { INT186_W::new(self) } #[doc = "Bits 24:31 - Interrupt 187"] #[inline(always)] #[must_use] - pub fn int187(&mut self) -> INT187_W<24> { + pub fn int187(&mut self) -> INT187_W { INT187_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 184 - 187 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr46](index.html) module"] +#[doc = "Interrupt Priority 184 - 187 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr46::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr46::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR46_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR46_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr46::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR46_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr46::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr46::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR46_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr46::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR46_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr47.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr47.rs index 4a437b0..565a527 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr47.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr47.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR47` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR47` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT188` reader - Interrupt 188"] -pub type INT188_R = crate::FieldReader; +pub type INT188_R = crate::FieldReader; #[doc = "Field `INT188` writer - Interrupt 188"] -pub type INT188_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR47_SPEC, u8, u8, 8, O>; +pub type INT188_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT189` reader - Interrupt 189"] -pub type INT189_R = crate::FieldReader; +pub type INT189_R = crate::FieldReader; #[doc = "Field `INT189` writer - Interrupt 189"] -pub type INT189_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR47_SPEC, u8, u8, 8, O>; +pub type INT189_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT190` reader - Interrupt 190"] -pub type INT190_R = crate::FieldReader; +pub type INT190_R = crate::FieldReader; #[doc = "Field `INT190` writer - Interrupt 190"] -pub type INT190_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR47_SPEC, u8, u8, 8, O>; +pub type INT190_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT191` reader - Interrupt 191"] -pub type INT191_R = crate::FieldReader; +pub type INT191_R = crate::FieldReader; #[doc = "Field `INT191` writer - Interrupt 191"] -pub type INT191_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR47_SPEC, u8, u8, 8, O>; +pub type INT191_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 188"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT191_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR47") + .field("int188", &format_args!("{}", self.int188().bits())) + .field("int189", &format_args!("{}", self.int189().bits())) + .field("int190", &format_args!("{}", self.int190().bits())) + .field("int191", &format_args!("{}", self.int191().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 188"] #[inline(always)] #[must_use] - pub fn int188(&mut self) -> INT188_W<0> { + pub fn int188(&mut self) -> INT188_W { INT188_W::new(self) } #[doc = "Bits 8:15 - Interrupt 189"] #[inline(always)] #[must_use] - pub fn int189(&mut self) -> INT189_W<8> { + pub fn int189(&mut self) -> INT189_W { INT189_W::new(self) } #[doc = "Bits 16:23 - Interrupt 190"] #[inline(always)] #[must_use] - pub fn int190(&mut self) -> INT190_W<16> { + pub fn int190(&mut self) -> INT190_W { INT190_W::new(self) } #[doc = "Bits 24:31 - Interrupt 191"] #[inline(always)] #[must_use] - pub fn int191(&mut self) -> INT191_W<24> { + pub fn int191(&mut self) -> INT191_W { INT191_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 188 - 191 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr47](index.html) module"] +#[doc = "Interrupt Priority 188 - 191 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr47::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr47::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR47_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR47_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr47::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR47_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr47::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr47::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR47_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr47::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR47_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr48.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr48.rs index a95f478..74284dd 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr48.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr48.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR48` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR48` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT192` reader - Interrupt 192"] -pub type INT192_R = crate::FieldReader; +pub type INT192_R = crate::FieldReader; #[doc = "Field `INT192` writer - Interrupt 192"] -pub type INT192_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR48_SPEC, u8, u8, 8, O>; +pub type INT192_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT193` reader - Interrupt 193"] -pub type INT193_R = crate::FieldReader; +pub type INT193_R = crate::FieldReader; #[doc = "Field `INT193` writer - Interrupt 193"] -pub type INT193_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR48_SPEC, u8, u8, 8, O>; +pub type INT193_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT194` reader - Interrupt 194"] -pub type INT194_R = crate::FieldReader; +pub type INT194_R = crate::FieldReader; #[doc = "Field `INT194` writer - Interrupt 194"] -pub type INT194_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR48_SPEC, u8, u8, 8, O>; +pub type INT194_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT195` reader - Interrupt 195"] -pub type INT195_R = crate::FieldReader; +pub type INT195_R = crate::FieldReader; #[doc = "Field `INT195` writer - Interrupt 195"] -pub type INT195_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR48_SPEC, u8, u8, 8, O>; +pub type INT195_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 192"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT195_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR48") + .field("int192", &format_args!("{}", self.int192().bits())) + .field("int193", &format_args!("{}", self.int193().bits())) + .field("int194", &format_args!("{}", self.int194().bits())) + .field("int195", &format_args!("{}", self.int195().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 192"] #[inline(always)] #[must_use] - pub fn int192(&mut self) -> INT192_W<0> { + pub fn int192(&mut self) -> INT192_W { INT192_W::new(self) } #[doc = "Bits 8:15 - Interrupt 193"] #[inline(always)] #[must_use] - pub fn int193(&mut self) -> INT193_W<8> { + pub fn int193(&mut self) -> INT193_W { INT193_W::new(self) } #[doc = "Bits 16:23 - Interrupt 194"] #[inline(always)] #[must_use] - pub fn int194(&mut self) -> INT194_W<16> { + pub fn int194(&mut self) -> INT194_W { INT194_W::new(self) } #[doc = "Bits 24:31 - Interrupt 195"] #[inline(always)] #[must_use] - pub fn int195(&mut self) -> INT195_W<24> { + pub fn int195(&mut self) -> INT195_W { INT195_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 192 - 195 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr48](index.html) module"] +#[doc = "Interrupt Priority 192 - 195 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr48::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr48::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR48_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR48_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr48::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR48_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr48::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr48::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR48_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr48::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR48_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr49.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr49.rs index 6dd8f6b..614c76c 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr49.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr49.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR49` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR49` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT196` reader - Interrupt 196"] -pub type INT196_R = crate::FieldReader; +pub type INT196_R = crate::FieldReader; #[doc = "Field `INT196` writer - Interrupt 196"] -pub type INT196_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR49_SPEC, u8, u8, 8, O>; +pub type INT196_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT197` reader - Interrupt 197"] -pub type INT197_R = crate::FieldReader; +pub type INT197_R = crate::FieldReader; #[doc = "Field `INT197` writer - Interrupt 197"] -pub type INT197_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR49_SPEC, u8, u8, 8, O>; +pub type INT197_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT198` reader - Interrupt 198"] -pub type INT198_R = crate::FieldReader; +pub type INT198_R = crate::FieldReader; #[doc = "Field `INT198` writer - Interrupt 198"] -pub type INT198_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR49_SPEC, u8, u8, 8, O>; +pub type INT198_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT199` reader - Interrupt 199"] -pub type INT199_R = crate::FieldReader; +pub type INT199_R = crate::FieldReader; #[doc = "Field `INT199` writer - Interrupt 199"] -pub type INT199_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR49_SPEC, u8, u8, 8, O>; +pub type INT199_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 196"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT199_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR49") + .field("int196", &format_args!("{}", self.int196().bits())) + .field("int197", &format_args!("{}", self.int197().bits())) + .field("int198", &format_args!("{}", self.int198().bits())) + .field("int199", &format_args!("{}", self.int199().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 196"] #[inline(always)] #[must_use] - pub fn int196(&mut self) -> INT196_W<0> { + pub fn int196(&mut self) -> INT196_W { INT196_W::new(self) } #[doc = "Bits 8:15 - Interrupt 197"] #[inline(always)] #[must_use] - pub fn int197(&mut self) -> INT197_W<8> { + pub fn int197(&mut self) -> INT197_W { INT197_W::new(self) } #[doc = "Bits 16:23 - Interrupt 198"] #[inline(always)] #[must_use] - pub fn int198(&mut self) -> INT198_W<16> { + pub fn int198(&mut self) -> INT198_W { INT198_W::new(self) } #[doc = "Bits 24:31 - Interrupt 199"] #[inline(always)] #[must_use] - pub fn int199(&mut self) -> INT199_W<24> { + pub fn int199(&mut self) -> INT199_W { INT199_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 196 - 199 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr49](index.html) module"] +#[doc = "Interrupt Priority 196 - 199 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr49::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr49::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR49_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR49_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr49::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR49_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr49::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr49::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR49_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr49::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR49_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr5.rs index 65379a1..4fb8985 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr5.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr5.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT20` reader - Interrupt 20"] -pub type INT20_R = crate::FieldReader; +pub type INT20_R = crate::FieldReader; #[doc = "Field `INT20` writer - Interrupt 20"] -pub type INT20_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR5_SPEC, u8, u8, 8, O>; +pub type INT20_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT21` reader - Interrupt 21"] -pub type INT21_R = crate::FieldReader; +pub type INT21_R = crate::FieldReader; #[doc = "Field `INT21` writer - Interrupt 21"] -pub type INT21_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR5_SPEC, u8, u8, 8, O>; +pub type INT21_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT22` reader - Interrupt 22"] -pub type INT22_R = crate::FieldReader; +pub type INT22_R = crate::FieldReader; #[doc = "Field `INT22` writer - Interrupt 22"] -pub type INT22_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR5_SPEC, u8, u8, 8, O>; +pub type INT22_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT23` reader - Interrupt 23"] -pub type INT23_R = crate::FieldReader; +pub type INT23_R = crate::FieldReader; #[doc = "Field `INT23` writer - Interrupt 23"] -pub type INT23_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR5_SPEC, u8, u8, 8, O>; +pub type INT23_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 20"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT23_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR5") + .field("int20", &format_args!("{}", self.int20().bits())) + .field("int21", &format_args!("{}", self.int21().bits())) + .field("int22", &format_args!("{}", self.int22().bits())) + .field("int23", &format_args!("{}", self.int23().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 20"] #[inline(always)] #[must_use] - pub fn int20(&mut self) -> INT20_W<0> { + pub fn int20(&mut self) -> INT20_W { INT20_W::new(self) } #[doc = "Bits 8:15 - Interrupt 21"] #[inline(always)] #[must_use] - pub fn int21(&mut self) -> INT21_W<8> { + pub fn int21(&mut self) -> INT21_W { INT21_W::new(self) } #[doc = "Bits 16:23 - Interrupt 22"] #[inline(always)] #[must_use] - pub fn int22(&mut self) -> INT22_W<16> { + pub fn int22(&mut self) -> INT22_W { INT22_W::new(self) } #[doc = "Bits 24:31 - Interrupt 23"] #[inline(always)] #[must_use] - pub fn int23(&mut self) -> INT23_W<24> { + pub fn int23(&mut self) -> INT23_W { INT23_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 20 - 23 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr5](index.html) module"] +#[doc = "Interrupt Priority 20 - 23 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR5_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr5::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr5::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr5::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr5::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr50.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr50.rs index 1f4dced..3895383 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr50.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr50.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR50` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR50` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT200` reader - Interrupt 200"] -pub type INT200_R = crate::FieldReader; +pub type INT200_R = crate::FieldReader; #[doc = "Field `INT200` writer - Interrupt 200"] -pub type INT200_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR50_SPEC, u8, u8, 8, O>; +pub type INT200_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT201` reader - Interrupt 201"] -pub type INT201_R = crate::FieldReader; +pub type INT201_R = crate::FieldReader; #[doc = "Field `INT201` writer - Interrupt 201"] -pub type INT201_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR50_SPEC, u8, u8, 8, O>; +pub type INT201_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT202` reader - Interrupt 202"] -pub type INT202_R = crate::FieldReader; +pub type INT202_R = crate::FieldReader; #[doc = "Field `INT202` writer - Interrupt 202"] -pub type INT202_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR50_SPEC, u8, u8, 8, O>; +pub type INT202_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT203` reader - Interrupt 203"] -pub type INT203_R = crate::FieldReader; +pub type INT203_R = crate::FieldReader; #[doc = "Field `INT203` writer - Interrupt 203"] -pub type INT203_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR50_SPEC, u8, u8, 8, O>; +pub type INT203_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 200"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT203_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR50") + .field("int200", &format_args!("{}", self.int200().bits())) + .field("int201", &format_args!("{}", self.int201().bits())) + .field("int202", &format_args!("{}", self.int202().bits())) + .field("int203", &format_args!("{}", self.int203().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 200"] #[inline(always)] #[must_use] - pub fn int200(&mut self) -> INT200_W<0> { + pub fn int200(&mut self) -> INT200_W { INT200_W::new(self) } #[doc = "Bits 8:15 - Interrupt 201"] #[inline(always)] #[must_use] - pub fn int201(&mut self) -> INT201_W<8> { + pub fn int201(&mut self) -> INT201_W { INT201_W::new(self) } #[doc = "Bits 16:23 - Interrupt 202"] #[inline(always)] #[must_use] - pub fn int202(&mut self) -> INT202_W<16> { + pub fn int202(&mut self) -> INT202_W { INT202_W::new(self) } #[doc = "Bits 24:31 - Interrupt 203"] #[inline(always)] #[must_use] - pub fn int203(&mut self) -> INT203_W<24> { + pub fn int203(&mut self) -> INT203_W { INT203_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 200 - 203 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr50](index.html) module"] +#[doc = "Interrupt Priority 200 - 203 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr50::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr50::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR50_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR50_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr50::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR50_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr50::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr50::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR50_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr50::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR50_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr51.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr51.rs index f274e33..5c83f40 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr51.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr51.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR51` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR51` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT204` reader - Interrupt 204"] -pub type INT204_R = crate::FieldReader; +pub type INT204_R = crate::FieldReader; #[doc = "Field `INT204` writer - Interrupt 204"] -pub type INT204_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR51_SPEC, u8, u8, 8, O>; +pub type INT204_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT205` reader - Interrupt 205"] -pub type INT205_R = crate::FieldReader; +pub type INT205_R = crate::FieldReader; #[doc = "Field `INT205` writer - Interrupt 205"] -pub type INT205_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR51_SPEC, u8, u8, 8, O>; +pub type INT205_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT206` reader - Interrupt 206"] -pub type INT206_R = crate::FieldReader; +pub type INT206_R = crate::FieldReader; #[doc = "Field `INT206` writer - Interrupt 206"] -pub type INT206_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR51_SPEC, u8, u8, 8, O>; +pub type INT206_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT207` reader - Interrupt 207"] -pub type INT207_R = crate::FieldReader; +pub type INT207_R = crate::FieldReader; #[doc = "Field `INT207` writer - Interrupt 207"] -pub type INT207_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR51_SPEC, u8, u8, 8, O>; +pub type INT207_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 204"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT207_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR51") + .field("int204", &format_args!("{}", self.int204().bits())) + .field("int205", &format_args!("{}", self.int205().bits())) + .field("int206", &format_args!("{}", self.int206().bits())) + .field("int207", &format_args!("{}", self.int207().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 204"] #[inline(always)] #[must_use] - pub fn int204(&mut self) -> INT204_W<0> { + pub fn int204(&mut self) -> INT204_W { INT204_W::new(self) } #[doc = "Bits 8:15 - Interrupt 205"] #[inline(always)] #[must_use] - pub fn int205(&mut self) -> INT205_W<8> { + pub fn int205(&mut self) -> INT205_W { INT205_W::new(self) } #[doc = "Bits 16:23 - Interrupt 206"] #[inline(always)] #[must_use] - pub fn int206(&mut self) -> INT206_W<16> { + pub fn int206(&mut self) -> INT206_W { INT206_W::new(self) } #[doc = "Bits 24:31 - Interrupt 207"] #[inline(always)] #[must_use] - pub fn int207(&mut self) -> INT207_W<24> { + pub fn int207(&mut self) -> INT207_W { INT207_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 204 - 207 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr51](index.html) module"] +#[doc = "Interrupt Priority 204 - 207 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr51::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr51::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR51_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR51_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr51::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR51_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr51::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr51::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR51_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr51::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR51_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr52.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr52.rs index 3e721b6..1b6583f 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr52.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr52.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR52` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR52` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT208` reader - Interrupt 208"] -pub type INT208_R = crate::FieldReader; +pub type INT208_R = crate::FieldReader; #[doc = "Field `INT208` writer - Interrupt 208"] -pub type INT208_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR52_SPEC, u8, u8, 8, O>; +pub type INT208_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT209` reader - Interrupt 209"] -pub type INT209_R = crate::FieldReader; +pub type INT209_R = crate::FieldReader; #[doc = "Field `INT209` writer - Interrupt 209"] -pub type INT209_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR52_SPEC, u8, u8, 8, O>; +pub type INT209_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT210` reader - Interrupt 210"] -pub type INT210_R = crate::FieldReader; +pub type INT210_R = crate::FieldReader; #[doc = "Field `INT210` writer - Interrupt 210"] -pub type INT210_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR52_SPEC, u8, u8, 8, O>; +pub type INT210_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT211` reader - Interrupt 211"] -pub type INT211_R = crate::FieldReader; +pub type INT211_R = crate::FieldReader; #[doc = "Field `INT211` writer - Interrupt 211"] -pub type INT211_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR52_SPEC, u8, u8, 8, O>; +pub type INT211_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 208"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT211_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR52") + .field("int208", &format_args!("{}", self.int208().bits())) + .field("int209", &format_args!("{}", self.int209().bits())) + .field("int210", &format_args!("{}", self.int210().bits())) + .field("int211", &format_args!("{}", self.int211().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 208"] #[inline(always)] #[must_use] - pub fn int208(&mut self) -> INT208_W<0> { + pub fn int208(&mut self) -> INT208_W { INT208_W::new(self) } #[doc = "Bits 8:15 - Interrupt 209"] #[inline(always)] #[must_use] - pub fn int209(&mut self) -> INT209_W<8> { + pub fn int209(&mut self) -> INT209_W { INT209_W::new(self) } #[doc = "Bits 16:23 - Interrupt 210"] #[inline(always)] #[must_use] - pub fn int210(&mut self) -> INT210_W<16> { + pub fn int210(&mut self) -> INT210_W { INT210_W::new(self) } #[doc = "Bits 24:31 - Interrupt 211"] #[inline(always)] #[must_use] - pub fn int211(&mut self) -> INT211_W<24> { + pub fn int211(&mut self) -> INT211_W { INT211_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 208 - 211 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr52](index.html) module"] +#[doc = "Interrupt Priority 208 - 211 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr52::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr52::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR52_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR52_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr52::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR52_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr52::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr52::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR52_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr52::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR52_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr53.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr53.rs index 53d4aad..fdfc206 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr53.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr53.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR53` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR53` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT212` reader - Interrupt 212"] -pub type INT212_R = crate::FieldReader; +pub type INT212_R = crate::FieldReader; #[doc = "Field `INT212` writer - Interrupt 212"] -pub type INT212_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR53_SPEC, u8, u8, 8, O>; +pub type INT212_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT213` reader - Interrupt 213"] -pub type INT213_R = crate::FieldReader; +pub type INT213_R = crate::FieldReader; #[doc = "Field `INT213` writer - Interrupt 213"] -pub type INT213_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR53_SPEC, u8, u8, 8, O>; +pub type INT213_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT214` reader - Interrupt 214"] -pub type INT214_R = crate::FieldReader; +pub type INT214_R = crate::FieldReader; #[doc = "Field `INT214` writer - Interrupt 214"] -pub type INT214_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR53_SPEC, u8, u8, 8, O>; +pub type INT214_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT215` reader - Interrupt 215"] -pub type INT215_R = crate::FieldReader; +pub type INT215_R = crate::FieldReader; #[doc = "Field `INT215` writer - Interrupt 215"] -pub type INT215_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR53_SPEC, u8, u8, 8, O>; +pub type INT215_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 212"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT215_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR53") + .field("int212", &format_args!("{}", self.int212().bits())) + .field("int213", &format_args!("{}", self.int213().bits())) + .field("int214", &format_args!("{}", self.int214().bits())) + .field("int215", &format_args!("{}", self.int215().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 212"] #[inline(always)] #[must_use] - pub fn int212(&mut self) -> INT212_W<0> { + pub fn int212(&mut self) -> INT212_W { INT212_W::new(self) } #[doc = "Bits 8:15 - Interrupt 213"] #[inline(always)] #[must_use] - pub fn int213(&mut self) -> INT213_W<8> { + pub fn int213(&mut self) -> INT213_W { INT213_W::new(self) } #[doc = "Bits 16:23 - Interrupt 214"] #[inline(always)] #[must_use] - pub fn int214(&mut self) -> INT214_W<16> { + pub fn int214(&mut self) -> INT214_W { INT214_W::new(self) } #[doc = "Bits 24:31 - Interrupt 215"] #[inline(always)] #[must_use] - pub fn int215(&mut self) -> INT215_W<24> { + pub fn int215(&mut self) -> INT215_W { INT215_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 212 - 215 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr53](index.html) module"] +#[doc = "Interrupt Priority 212 - 215 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr53::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr53::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR53_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR53_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr53::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR53_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr53::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr53::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR53_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr53::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR53_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr54.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr54.rs index ed4595e..d49a711 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr54.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr54.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR54` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR54` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT216` reader - Interrupt 216"] -pub type INT216_R = crate::FieldReader; +pub type INT216_R = crate::FieldReader; #[doc = "Field `INT216` writer - Interrupt 216"] -pub type INT216_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR54_SPEC, u8, u8, 8, O>; +pub type INT216_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT217` reader - Interrupt 217"] -pub type INT217_R = crate::FieldReader; +pub type INT217_R = crate::FieldReader; #[doc = "Field `INT217` writer - Interrupt 217"] -pub type INT217_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR54_SPEC, u8, u8, 8, O>; +pub type INT217_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT218` reader - Interrupt 218"] -pub type INT218_R = crate::FieldReader; +pub type INT218_R = crate::FieldReader; #[doc = "Field `INT218` writer - Interrupt 218"] -pub type INT218_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR54_SPEC, u8, u8, 8, O>; +pub type INT218_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT219` reader - Interrupt 219"] -pub type INT219_R = crate::FieldReader; +pub type INT219_R = crate::FieldReader; #[doc = "Field `INT219` writer - Interrupt 219"] -pub type INT219_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR54_SPEC, u8, u8, 8, O>; +pub type INT219_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 216"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT219_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR54") + .field("int216", &format_args!("{}", self.int216().bits())) + .field("int217", &format_args!("{}", self.int217().bits())) + .field("int218", &format_args!("{}", self.int218().bits())) + .field("int219", &format_args!("{}", self.int219().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 216"] #[inline(always)] #[must_use] - pub fn int216(&mut self) -> INT216_W<0> { + pub fn int216(&mut self) -> INT216_W { INT216_W::new(self) } #[doc = "Bits 8:15 - Interrupt 217"] #[inline(always)] #[must_use] - pub fn int217(&mut self) -> INT217_W<8> { + pub fn int217(&mut self) -> INT217_W { INT217_W::new(self) } #[doc = "Bits 16:23 - Interrupt 218"] #[inline(always)] #[must_use] - pub fn int218(&mut self) -> INT218_W<16> { + pub fn int218(&mut self) -> INT218_W { INT218_W::new(self) } #[doc = "Bits 24:31 - Interrupt 219"] #[inline(always)] #[must_use] - pub fn int219(&mut self) -> INT219_W<24> { + pub fn int219(&mut self) -> INT219_W { INT219_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 216 - 219 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr54](index.html) module"] +#[doc = "Interrupt Priority 216 - 219 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr54::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr54::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR54_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR54_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr54::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR54_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr54::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr54::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR54_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr54::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR54_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr55.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr55.rs index 42135d7..ebf3ead 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr55.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr55.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR55` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR55` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT220` reader - Interrupt 220"] -pub type INT220_R = crate::FieldReader; +pub type INT220_R = crate::FieldReader; #[doc = "Field `INT220` writer - Interrupt 220"] -pub type INT220_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR55_SPEC, u8, u8, 8, O>; +pub type INT220_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT221` reader - Interrupt 221"] -pub type INT221_R = crate::FieldReader; +pub type INT221_R = crate::FieldReader; #[doc = "Field `INT221` writer - Interrupt 221"] -pub type INT221_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR55_SPEC, u8, u8, 8, O>; +pub type INT221_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT222` reader - Interrupt 222"] -pub type INT222_R = crate::FieldReader; +pub type INT222_R = crate::FieldReader; #[doc = "Field `INT222` writer - Interrupt 222"] -pub type INT222_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR55_SPEC, u8, u8, 8, O>; +pub type INT222_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT223` reader - Interrupt 223"] -pub type INT223_R = crate::FieldReader; +pub type INT223_R = crate::FieldReader; #[doc = "Field `INT223` writer - Interrupt 223"] -pub type INT223_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR55_SPEC, u8, u8, 8, O>; +pub type INT223_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 220"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT223_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR55") + .field("int220", &format_args!("{}", self.int220().bits())) + .field("int221", &format_args!("{}", self.int221().bits())) + .field("int222", &format_args!("{}", self.int222().bits())) + .field("int223", &format_args!("{}", self.int223().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 220"] #[inline(always)] #[must_use] - pub fn int220(&mut self) -> INT220_W<0> { + pub fn int220(&mut self) -> INT220_W { INT220_W::new(self) } #[doc = "Bits 8:15 - Interrupt 221"] #[inline(always)] #[must_use] - pub fn int221(&mut self) -> INT221_W<8> { + pub fn int221(&mut self) -> INT221_W { INT221_W::new(self) } #[doc = "Bits 16:23 - Interrupt 222"] #[inline(always)] #[must_use] - pub fn int222(&mut self) -> INT222_W<16> { + pub fn int222(&mut self) -> INT222_W { INT222_W::new(self) } #[doc = "Bits 24:31 - Interrupt 223"] #[inline(always)] #[must_use] - pub fn int223(&mut self) -> INT223_W<24> { + pub fn int223(&mut self) -> INT223_W { INT223_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 220 - 223 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr55](index.html) module"] +#[doc = "Interrupt Priority 220 - 223 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr55::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr55::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR55_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR55_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr55::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR55_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr55::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr55::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR55_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr55::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR55_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr6.rs index dd002ac..d12573a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr6.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr6.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT24` reader - Interrupt 24"] -pub type INT24_R = crate::FieldReader; +pub type INT24_R = crate::FieldReader; #[doc = "Field `INT24` writer - Interrupt 24"] -pub type INT24_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR6_SPEC, u8, u8, 8, O>; +pub type INT24_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT25` reader - Interrupt 25"] -pub type INT25_R = crate::FieldReader; +pub type INT25_R = crate::FieldReader; #[doc = "Field `INT25` writer - Interrupt 25"] -pub type INT25_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR6_SPEC, u8, u8, 8, O>; +pub type INT25_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT26` reader - Interrupt 26"] -pub type INT26_R = crate::FieldReader; +pub type INT26_R = crate::FieldReader; #[doc = "Field `INT26` writer - Interrupt 26"] -pub type INT26_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR6_SPEC, u8, u8, 8, O>; +pub type INT26_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT27` reader - Interrupt 27"] -pub type INT27_R = crate::FieldReader; +pub type INT27_R = crate::FieldReader; #[doc = "Field `INT27` writer - Interrupt 27"] -pub type INT27_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR6_SPEC, u8, u8, 8, O>; +pub type INT27_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 24"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT27_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR6") + .field("int24", &format_args!("{}", self.int24().bits())) + .field("int25", &format_args!("{}", self.int25().bits())) + .field("int26", &format_args!("{}", self.int26().bits())) + .field("int27", &format_args!("{}", self.int27().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 24"] #[inline(always)] #[must_use] - pub fn int24(&mut self) -> INT24_W<0> { + pub fn int24(&mut self) -> INT24_W { INT24_W::new(self) } #[doc = "Bits 8:15 - Interrupt 25"] #[inline(always)] #[must_use] - pub fn int25(&mut self) -> INT25_W<8> { + pub fn int25(&mut self) -> INT25_W { INT25_W::new(self) } #[doc = "Bits 16:23 - Interrupt 26"] #[inline(always)] #[must_use] - pub fn int26(&mut self) -> INT26_W<16> { + pub fn int26(&mut self) -> INT26_W { INT26_W::new(self) } #[doc = "Bits 24:31 - Interrupt 27"] #[inline(always)] #[must_use] - pub fn int27(&mut self) -> INT27_W<24> { + pub fn int27(&mut self) -> INT27_W { INT27_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 24 - 27 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr6](index.html) module"] +#[doc = "Interrupt Priority 24 - 27 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR6_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr6::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr6::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr6::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr6::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr7.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr7.rs index eae5948..62a0986 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr7.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr7.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR7` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR7` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT28` reader - Interrupt 28"] -pub type INT28_R = crate::FieldReader; +pub type INT28_R = crate::FieldReader; #[doc = "Field `INT28` writer - Interrupt 28"] -pub type INT28_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR7_SPEC, u8, u8, 8, O>; +pub type INT28_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT29` reader - Interrupt 29"] -pub type INT29_R = crate::FieldReader; +pub type INT29_R = crate::FieldReader; #[doc = "Field `INT29` writer - Interrupt 29"] -pub type INT29_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR7_SPEC, u8, u8, 8, O>; +pub type INT29_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT30` reader - Interrupt 30"] -pub type INT30_R = crate::FieldReader; +pub type INT30_R = crate::FieldReader; #[doc = "Field `INT30` writer - Interrupt 30"] -pub type INT30_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR7_SPEC, u8, u8, 8, O>; +pub type INT30_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT31` reader - Interrupt 31"] -pub type INT31_R = crate::FieldReader; +pub type INT31_R = crate::FieldReader; #[doc = "Field `INT31` writer - Interrupt 31"] -pub type INT31_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR7_SPEC, u8, u8, 8, O>; +pub type INT31_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 28"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT31_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR7") + .field("int28", &format_args!("{}", self.int28().bits())) + .field("int29", &format_args!("{}", self.int29().bits())) + .field("int30", &format_args!("{}", self.int30().bits())) + .field("int31", &format_args!("{}", self.int31().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 28"] #[inline(always)] #[must_use] - pub fn int28(&mut self) -> INT28_W<0> { + pub fn int28(&mut self) -> INT28_W { INT28_W::new(self) } #[doc = "Bits 8:15 - Interrupt 29"] #[inline(always)] #[must_use] - pub fn int29(&mut self) -> INT29_W<8> { + pub fn int29(&mut self) -> INT29_W { INT29_W::new(self) } #[doc = "Bits 16:23 - Interrupt 30"] #[inline(always)] #[must_use] - pub fn int30(&mut self) -> INT30_W<16> { + pub fn int30(&mut self) -> INT30_W { INT30_W::new(self) } #[doc = "Bits 24:31 - Interrupt 31"] #[inline(always)] #[must_use] - pub fn int31(&mut self) -> INT31_W<24> { + pub fn int31(&mut self) -> INT31_W { INT31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 28 - 31 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr7](index.html) module"] +#[doc = "Interrupt Priority 28 - 31 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR7_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR7_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr7::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR7_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr7::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr7::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr7::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR7_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr8.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr8.rs index 67db183..737dc73 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr8.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr8.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR8` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR8` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT32` reader - Interrupt 32"] -pub type INT32_R = crate::FieldReader; +pub type INT32_R = crate::FieldReader; #[doc = "Field `INT32` writer - Interrupt 32"] -pub type INT32_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR8_SPEC, u8, u8, 8, O>; +pub type INT32_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT33` reader - Interrupt 33"] -pub type INT33_R = crate::FieldReader; +pub type INT33_R = crate::FieldReader; #[doc = "Field `INT33` writer - Interrupt 33"] -pub type INT33_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR8_SPEC, u8, u8, 8, O>; +pub type INT33_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT34` reader - Interrupt 34"] -pub type INT34_R = crate::FieldReader; +pub type INT34_R = crate::FieldReader; #[doc = "Field `INT34` writer - Interrupt 34"] -pub type INT34_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR8_SPEC, u8, u8, 8, O>; +pub type INT34_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT35` reader - Interrupt 35"] -pub type INT35_R = crate::FieldReader; +pub type INT35_R = crate::FieldReader; #[doc = "Field `INT35` writer - Interrupt 35"] -pub type INT35_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR8_SPEC, u8, u8, 8, O>; +pub type INT35_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 32"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT35_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR8") + .field("int32", &format_args!("{}", self.int32().bits())) + .field("int33", &format_args!("{}", self.int33().bits())) + .field("int34", &format_args!("{}", self.int34().bits())) + .field("int35", &format_args!("{}", self.int35().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 32"] #[inline(always)] #[must_use] - pub fn int32(&mut self) -> INT32_W<0> { + pub fn int32(&mut self) -> INT32_W { INT32_W::new(self) } #[doc = "Bits 8:15 - Interrupt 33"] #[inline(always)] #[must_use] - pub fn int33(&mut self) -> INT33_W<8> { + pub fn int33(&mut self) -> INT33_W { INT33_W::new(self) } #[doc = "Bits 16:23 - Interrupt 34"] #[inline(always)] #[must_use] - pub fn int34(&mut self) -> INT34_W<16> { + pub fn int34(&mut self) -> INT34_W { INT34_W::new(self) } #[doc = "Bits 24:31 - Interrupt 35"] #[inline(always)] #[must_use] - pub fn int35(&mut self) -> INT35_W<24> { + pub fn int35(&mut self) -> INT35_W { INT35_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 32 - 35 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr8](index.html) module"] +#[doc = "Interrupt Priority 32 - 35 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR8_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR8_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr8::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR8_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr8::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr8::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr8::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR8_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr9.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr9.rs index e41150a..d3f2418 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr9.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ipriorityr/gicd_ipriorityr9.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_IPRIORITYR9` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_IPRIORITYR9` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT36` reader - Interrupt 36"] -pub type INT36_R = crate::FieldReader; +pub type INT36_R = crate::FieldReader; #[doc = "Field `INT36` writer - Interrupt 36"] -pub type INT36_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR9_SPEC, u8, u8, 8, O>; +pub type INT36_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT37` reader - Interrupt 37"] -pub type INT37_R = crate::FieldReader; +pub type INT37_R = crate::FieldReader; #[doc = "Field `INT37` writer - Interrupt 37"] -pub type INT37_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR9_SPEC, u8, u8, 8, O>; +pub type INT37_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT38` reader - Interrupt 38"] -pub type INT38_R = crate::FieldReader; +pub type INT38_R = crate::FieldReader; #[doc = "Field `INT38` writer - Interrupt 38"] -pub type INT38_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR9_SPEC, u8, u8, 8, O>; +pub type INT38_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT39` reader - Interrupt 39"] -pub type INT39_R = crate::FieldReader; +pub type INT39_R = crate::FieldReader; #[doc = "Field `INT39` writer - Interrupt 39"] -pub type INT39_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_IPRIORITYR9_SPEC, u8, u8, 8, O>; +pub type INT39_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 36"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT39_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_IPRIORITYR9") + .field("int36", &format_args!("{}", self.int36().bits())) + .field("int37", &format_args!("{}", self.int37().bits())) + .field("int38", &format_args!("{}", self.int38().bits())) + .field("int39", &format_args!("{}", self.int39().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 36"] #[inline(always)] #[must_use] - pub fn int36(&mut self) -> INT36_W<0> { + pub fn int36(&mut self) -> INT36_W { INT36_W::new(self) } #[doc = "Bits 8:15 - Interrupt 37"] #[inline(always)] #[must_use] - pub fn int37(&mut self) -> INT37_W<8> { + pub fn int37(&mut self) -> INT37_W { INT37_W::new(self) } #[doc = "Bits 16:23 - Interrupt 38"] #[inline(always)] #[must_use] - pub fn int38(&mut self) -> INT38_W<16> { + pub fn int38(&mut self) -> INT38_W { INT38_W::new(self) } #[doc = "Bits 24:31 - Interrupt 39"] #[inline(always)] #[must_use] - pub fn int39(&mut self) -> INT39_W<24> { + pub fn int39(&mut self) -> INT39_W { INT39_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Priority 36 - 39 (Lower is first)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ipriorityr9](index.html) module"] +#[doc = "Interrupt Priority 36 - 39 (Lower is first)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ipriorityr9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ipriorityr9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_IPRIORITYR9_SPEC; impl crate::RegisterSpec for GICD_IPRIORITYR9_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ipriorityr9::R](R) reader structure"] -impl crate::Readable for GICD_IPRIORITYR9_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ipriorityr9::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ipriorityr9::R`](R) reader structure"] +impl crate::Readable for GICD_IPRIORITYR9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ipriorityr9::W`](W) writer structure"] impl crate::Writable for GICD_IPRIORITYR9_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver.rs index 6d1dd03..4b679ea 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct GICD_ISACTIVER { #[doc = "0x00 - Interrupt Set-Active"] pub gicd_isactiver0: GICD_ISACTIVER0, @@ -16,31 +17,38 @@ pub struct GICD_ISACTIVER { #[doc = "0x18 - Interrupt Set-Active"] pub gicd_isactiver6: GICD_ISACTIVER6, } -#[doc = "GICD_ISACTIVER0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISACTIVER0 (rw) register accessor: Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isactiver0`] +module"] pub type GICD_ISACTIVER0 = crate::Reg; #[doc = "Interrupt Set-Active"] pub mod gicd_isactiver0; -#[doc = "GICD_ISACTIVER1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISACTIVER1 (rw) register accessor: Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isactiver1`] +module"] pub type GICD_ISACTIVER1 = crate::Reg; #[doc = "Interrupt Set-Active"] pub mod gicd_isactiver1; -#[doc = "GICD_ISACTIVER2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISACTIVER2 (rw) register accessor: Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isactiver2`] +module"] pub type GICD_ISACTIVER2 = crate::Reg; #[doc = "Interrupt Set-Active"] pub mod gicd_isactiver2; -#[doc = "GICD_ISACTIVER3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISACTIVER3 (rw) register accessor: Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isactiver3`] +module"] pub type GICD_ISACTIVER3 = crate::Reg; #[doc = "Interrupt Set-Active"] pub mod gicd_isactiver3; -#[doc = "GICD_ISACTIVER4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISACTIVER4 (rw) register accessor: Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isactiver4`] +module"] pub type GICD_ISACTIVER4 = crate::Reg; #[doc = "Interrupt Set-Active"] pub mod gicd_isactiver4; -#[doc = "GICD_ISACTIVER5 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISACTIVER5 (rw) register accessor: Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isactiver5`] +module"] pub type GICD_ISACTIVER5 = crate::Reg; #[doc = "Interrupt Set-Active"] pub mod gicd_isactiver5; -#[doc = "GICD_ISACTIVER6 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISACTIVER6 (rw) register accessor: Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isactiver6`] +module"] pub type GICD_ISACTIVER6 = crate::Reg; #[doc = "Interrupt Set-Active"] pub mod gicd_isactiver6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver0.rs index ba46247..f32fe51 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver0.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ISACTIVER0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISACTIVER0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT0` reader - Interrupt 0"] -pub type INT0_R = crate::BitReader; +pub type INT0_R = crate::BitReader; #[doc = "Field `INT0` writer - Interrupt 0"] -pub type INT0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT1` reader - Interrupt 1"] -pub type INT1_R = crate::BitReader; +pub type INT1_R = crate::BitReader; #[doc = "Field `INT1` writer - Interrupt 1"] -pub type INT1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT2` reader - Interrupt 2"] -pub type INT2_R = crate::BitReader; +pub type INT2_R = crate::BitReader; #[doc = "Field `INT2` writer - Interrupt 2"] -pub type INT2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT3` reader - Interrupt 3"] -pub type INT3_R = crate::BitReader; +pub type INT3_R = crate::BitReader; #[doc = "Field `INT3` writer - Interrupt 3"] -pub type INT3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT4` reader - Interrupt 4"] -pub type INT4_R = crate::BitReader; +pub type INT4_R = crate::BitReader; #[doc = "Field `INT4` writer - Interrupt 4"] -pub type INT4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT5` reader - Interrupt 5"] -pub type INT5_R = crate::BitReader; +pub type INT5_R = crate::BitReader; #[doc = "Field `INT5` writer - Interrupt 5"] -pub type INT5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT6` reader - Interrupt 6"] -pub type INT6_R = crate::BitReader; +pub type INT6_R = crate::BitReader; #[doc = "Field `INT6` writer - Interrupt 6"] -pub type INT6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT7` reader - Interrupt 7"] -pub type INT7_R = crate::BitReader; +pub type INT7_R = crate::BitReader; #[doc = "Field `INT7` writer - Interrupt 7"] -pub type INT7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT7_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT8` reader - Interrupt 8"] -pub type INT8_R = crate::BitReader; +pub type INT8_R = crate::BitReader; #[doc = "Field `INT8` writer - Interrupt 8"] -pub type INT8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT8_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT9` reader - Interrupt 9"] -pub type INT9_R = crate::BitReader; +pub type INT9_R = crate::BitReader; #[doc = "Field `INT9` writer - Interrupt 9"] -pub type INT9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT9_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT10` reader - Interrupt 10"] -pub type INT10_R = crate::BitReader; +pub type INT10_R = crate::BitReader; #[doc = "Field `INT10` writer - Interrupt 10"] -pub type INT10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT10_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT11` reader - Interrupt 11"] -pub type INT11_R = crate::BitReader; +pub type INT11_R = crate::BitReader; #[doc = "Field `INT11` writer - Interrupt 11"] -pub type INT11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT11_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT12` reader - Interrupt 12"] -pub type INT12_R = crate::BitReader; +pub type INT12_R = crate::BitReader; #[doc = "Field `INT12` writer - Interrupt 12"] -pub type INT12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT12_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT13` reader - Interrupt 13"] -pub type INT13_R = crate::BitReader; +pub type INT13_R = crate::BitReader; #[doc = "Field `INT13` writer - Interrupt 13"] -pub type INT13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT13_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT14` reader - Interrupt 14"] -pub type INT14_R = crate::BitReader; +pub type INT14_R = crate::BitReader; #[doc = "Field `INT14` writer - Interrupt 14"] -pub type INT14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT14_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT15` reader - Interrupt 15"] -pub type INT15_R = crate::BitReader; +pub type INT15_R = crate::BitReader; #[doc = "Field `INT15` writer - Interrupt 15"] -pub type INT15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT15_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT16` reader - Interrupt 16"] -pub type INT16_R = crate::BitReader; +pub type INT16_R = crate::BitReader; #[doc = "Field `INT16` writer - Interrupt 16"] -pub type INT16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT16_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT17` reader - Interrupt 17"] -pub type INT17_R = crate::BitReader; +pub type INT17_R = crate::BitReader; #[doc = "Field `INT17` writer - Interrupt 17"] -pub type INT17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT17_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT18` reader - Interrupt 18"] -pub type INT18_R = crate::BitReader; +pub type INT18_R = crate::BitReader; #[doc = "Field `INT18` writer - Interrupt 18"] -pub type INT18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT18_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT19` reader - Interrupt 19"] -pub type INT19_R = crate::BitReader; +pub type INT19_R = crate::BitReader; #[doc = "Field `INT19` writer - Interrupt 19"] -pub type INT19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT19_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT20` reader - Interrupt 20"] -pub type INT20_R = crate::BitReader; +pub type INT20_R = crate::BitReader; #[doc = "Field `INT20` writer - Interrupt 20"] -pub type INT20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT20_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT21` reader - Interrupt 21"] -pub type INT21_R = crate::BitReader; +pub type INT21_R = crate::BitReader; #[doc = "Field `INT21` writer - Interrupt 21"] -pub type INT21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT21_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT22` reader - Interrupt 22"] -pub type INT22_R = crate::BitReader; +pub type INT22_R = crate::BitReader; #[doc = "Field `INT22` writer - Interrupt 22"] -pub type INT22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT22_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT23` reader - Interrupt 23"] -pub type INT23_R = crate::BitReader; +pub type INT23_R = crate::BitReader; #[doc = "Field `INT23` writer - Interrupt 23"] -pub type INT23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT23_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT24` reader - Interrupt 24"] -pub type INT24_R = crate::BitReader; +pub type INT24_R = crate::BitReader; #[doc = "Field `INT24` writer - Interrupt 24"] -pub type INT24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT24_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT25` reader - Interrupt 25"] -pub type INT25_R = crate::BitReader; +pub type INT25_R = crate::BitReader; #[doc = "Field `INT25` writer - Interrupt 25"] -pub type INT25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT25_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT26` reader - Interrupt 26"] -pub type INT26_R = crate::BitReader; +pub type INT26_R = crate::BitReader; #[doc = "Field `INT26` writer - Interrupt 26"] -pub type INT26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT26_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT27` reader - Interrupt 27"] -pub type INT27_R = crate::BitReader; +pub type INT27_R = crate::BitReader; #[doc = "Field `INT27` writer - Interrupt 27"] -pub type INT27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT27_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT28` reader - Interrupt 28"] -pub type INT28_R = crate::BitReader; +pub type INT28_R = crate::BitReader; #[doc = "Field `INT28` writer - Interrupt 28"] -pub type INT28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT28_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT29` reader - Interrupt 29"] -pub type INT29_R = crate::BitReader; +pub type INT29_R = crate::BitReader; #[doc = "Field `INT29` writer - Interrupt 29"] -pub type INT29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT29_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT30` reader - Interrupt 30"] -pub type INT30_R = crate::BitReader; +pub type INT30_R = crate::BitReader; #[doc = "Field `INT30` writer - Interrupt 30"] -pub type INT30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT30_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT31` reader - Interrupt 31"] -pub type INT31_R = crate::BitReader; +pub type INT31_R = crate::BitReader; #[doc = "Field `INT31` writer - Interrupt 31"] -pub type INT31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER0_SPEC, bool, O>; +pub type INT31_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISACTIVER0") + .field("int0", &format_args!("{}", self.int0().bit())) + .field("int1", &format_args!("{}", self.int1().bit())) + .field("int2", &format_args!("{}", self.int2().bit())) + .field("int3", &format_args!("{}", self.int3().bit())) + .field("int4", &format_args!("{}", self.int4().bit())) + .field("int5", &format_args!("{}", self.int5().bit())) + .field("int6", &format_args!("{}", self.int6().bit())) + .field("int7", &format_args!("{}", self.int7().bit())) + .field("int8", &format_args!("{}", self.int8().bit())) + .field("int9", &format_args!("{}", self.int9().bit())) + .field("int10", &format_args!("{}", self.int10().bit())) + .field("int11", &format_args!("{}", self.int11().bit())) + .field("int12", &format_args!("{}", self.int12().bit())) + .field("int13", &format_args!("{}", self.int13().bit())) + .field("int14", &format_args!("{}", self.int14().bit())) + .field("int15", &format_args!("{}", self.int15().bit())) + .field("int16", &format_args!("{}", self.int16().bit())) + .field("int17", &format_args!("{}", self.int17().bit())) + .field("int18", &format_args!("{}", self.int18().bit())) + .field("int19", &format_args!("{}", self.int19().bit())) + .field("int20", &format_args!("{}", self.int20().bit())) + .field("int21", &format_args!("{}", self.int21().bit())) + .field("int22", &format_args!("{}", self.int22().bit())) + .field("int23", &format_args!("{}", self.int23().bit())) + .field("int24", &format_args!("{}", self.int24().bit())) + .field("int25", &format_args!("{}", self.int25().bit())) + .field("int26", &format_args!("{}", self.int26().bit())) + .field("int27", &format_args!("{}", self.int27().bit())) + .field("int28", &format_args!("{}", self.int28().bit())) + .field("int29", &format_args!("{}", self.int29().bit())) + .field("int30", &format_args!("{}", self.int30().bit())) + .field("int31", &format_args!("{}", self.int31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] #[must_use] - pub fn int0(&mut self) -> INT0_W<0> { + pub fn int0(&mut self) -> INT0_W { INT0_W::new(self) } #[doc = "Bit 1 - Interrupt 1"] #[inline(always)] #[must_use] - pub fn int1(&mut self) -> INT1_W<1> { + pub fn int1(&mut self) -> INT1_W { INT1_W::new(self) } #[doc = "Bit 2 - Interrupt 2"] #[inline(always)] #[must_use] - pub fn int2(&mut self) -> INT2_W<2> { + pub fn int2(&mut self) -> INT2_W { INT2_W::new(self) } #[doc = "Bit 3 - Interrupt 3"] #[inline(always)] #[must_use] - pub fn int3(&mut self) -> INT3_W<3> { + pub fn int3(&mut self) -> INT3_W { INT3_W::new(self) } #[doc = "Bit 4 - Interrupt 4"] #[inline(always)] #[must_use] - pub fn int4(&mut self) -> INT4_W<4> { + pub fn int4(&mut self) -> INT4_W { INT4_W::new(self) } #[doc = "Bit 5 - Interrupt 5"] #[inline(always)] #[must_use] - pub fn int5(&mut self) -> INT5_W<5> { + pub fn int5(&mut self) -> INT5_W { INT5_W::new(self) } #[doc = "Bit 6 - Interrupt 6"] #[inline(always)] #[must_use] - pub fn int6(&mut self) -> INT6_W<6> { + pub fn int6(&mut self) -> INT6_W { INT6_W::new(self) } #[doc = "Bit 7 - Interrupt 7"] #[inline(always)] #[must_use] - pub fn int7(&mut self) -> INT7_W<7> { + pub fn int7(&mut self) -> INT7_W { INT7_W::new(self) } #[doc = "Bit 8 - Interrupt 8"] #[inline(always)] #[must_use] - pub fn int8(&mut self) -> INT8_W<8> { + pub fn int8(&mut self) -> INT8_W { INT8_W::new(self) } #[doc = "Bit 9 - Interrupt 9"] #[inline(always)] #[must_use] - pub fn int9(&mut self) -> INT9_W<9> { + pub fn int9(&mut self) -> INT9_W { INT9_W::new(self) } #[doc = "Bit 10 - Interrupt 10"] #[inline(always)] #[must_use] - pub fn int10(&mut self) -> INT10_W<10> { + pub fn int10(&mut self) -> INT10_W { INT10_W::new(self) } #[doc = "Bit 11 - Interrupt 11"] #[inline(always)] #[must_use] - pub fn int11(&mut self) -> INT11_W<11> { + pub fn int11(&mut self) -> INT11_W { INT11_W::new(self) } #[doc = "Bit 12 - Interrupt 12"] #[inline(always)] #[must_use] - pub fn int12(&mut self) -> INT12_W<12> { + pub fn int12(&mut self) -> INT12_W { INT12_W::new(self) } #[doc = "Bit 13 - Interrupt 13"] #[inline(always)] #[must_use] - pub fn int13(&mut self) -> INT13_W<13> { + pub fn int13(&mut self) -> INT13_W { INT13_W::new(self) } #[doc = "Bit 14 - Interrupt 14"] #[inline(always)] #[must_use] - pub fn int14(&mut self) -> INT14_W<14> { + pub fn int14(&mut self) -> INT14_W { INT14_W::new(self) } #[doc = "Bit 15 - Interrupt 15"] #[inline(always)] #[must_use] - pub fn int15(&mut self) -> INT15_W<15> { + pub fn int15(&mut self) -> INT15_W { INT15_W::new(self) } #[doc = "Bit 16 - Interrupt 16"] #[inline(always)] #[must_use] - pub fn int16(&mut self) -> INT16_W<16> { + pub fn int16(&mut self) -> INT16_W { INT16_W::new(self) } #[doc = "Bit 17 - Interrupt 17"] #[inline(always)] #[must_use] - pub fn int17(&mut self) -> INT17_W<17> { + pub fn int17(&mut self) -> INT17_W { INT17_W::new(self) } #[doc = "Bit 18 - Interrupt 18"] #[inline(always)] #[must_use] - pub fn int18(&mut self) -> INT18_W<18> { + pub fn int18(&mut self) -> INT18_W { INT18_W::new(self) } #[doc = "Bit 19 - Interrupt 19"] #[inline(always)] #[must_use] - pub fn int19(&mut self) -> INT19_W<19> { + pub fn int19(&mut self) -> INT19_W { INT19_W::new(self) } #[doc = "Bit 20 - Interrupt 20"] #[inline(always)] #[must_use] - pub fn int20(&mut self) -> INT20_W<20> { + pub fn int20(&mut self) -> INT20_W { INT20_W::new(self) } #[doc = "Bit 21 - Interrupt 21"] #[inline(always)] #[must_use] - pub fn int21(&mut self) -> INT21_W<21> { + pub fn int21(&mut self) -> INT21_W { INT21_W::new(self) } #[doc = "Bit 22 - Interrupt 22"] #[inline(always)] #[must_use] - pub fn int22(&mut self) -> INT22_W<22> { + pub fn int22(&mut self) -> INT22_W { INT22_W::new(self) } #[doc = "Bit 23 - Interrupt 23"] #[inline(always)] #[must_use] - pub fn int23(&mut self) -> INT23_W<23> { + pub fn int23(&mut self) -> INT23_W { INT23_W::new(self) } #[doc = "Bit 24 - Interrupt 24"] #[inline(always)] #[must_use] - pub fn int24(&mut self) -> INT24_W<24> { + pub fn int24(&mut self) -> INT24_W { INT24_W::new(self) } #[doc = "Bit 25 - Interrupt 25"] #[inline(always)] #[must_use] - pub fn int25(&mut self) -> INT25_W<25> { + pub fn int25(&mut self) -> INT25_W { INT25_W::new(self) } #[doc = "Bit 26 - Interrupt 26"] #[inline(always)] #[must_use] - pub fn int26(&mut self) -> INT26_W<26> { + pub fn int26(&mut self) -> INT26_W { INT26_W::new(self) } #[doc = "Bit 27 - Interrupt 27"] #[inline(always)] #[must_use] - pub fn int27(&mut self) -> INT27_W<27> { + pub fn int27(&mut self) -> INT27_W { INT27_W::new(self) } #[doc = "Bit 28 - Interrupt 28"] #[inline(always)] #[must_use] - pub fn int28(&mut self) -> INT28_W<28> { + pub fn int28(&mut self) -> INT28_W { INT28_W::new(self) } #[doc = "Bit 29 - Interrupt 29"] #[inline(always)] #[must_use] - pub fn int29(&mut self) -> INT29_W<29> { + pub fn int29(&mut self) -> INT29_W { INT29_W::new(self) } #[doc = "Bit 30 - Interrupt 30"] #[inline(always)] #[must_use] - pub fn int30(&mut self) -> INT30_W<30> { + pub fn int30(&mut self) -> INT30_W { INT30_W::new(self) } #[doc = "Bit 31 - Interrupt 31"] #[inline(always)] #[must_use] - pub fn int31(&mut self) -> INT31_W<31> { + pub fn int31(&mut self) -> INT31_W { INT31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver0](index.html) module"] +#[doc = "Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISACTIVER0_SPEC; impl crate::RegisterSpec for GICD_ISACTIVER0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isactiver0::R](R) reader structure"] -impl crate::Readable for GICD_ISACTIVER0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isactiver0::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isactiver0::R`](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isactiver0::W`](W) writer structure"] impl crate::Writable for GICD_ISACTIVER0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver1.rs index f5242d6..55f7697 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver1.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver1.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ISACTIVER1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISACTIVER1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT32` reader - Interrupt 32"] -pub type INT32_R = crate::BitReader; +pub type INT32_R = crate::BitReader; #[doc = "Field `INT32` writer - Interrupt 32"] -pub type INT32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT32_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT33` reader - Interrupt 33"] -pub type INT33_R = crate::BitReader; +pub type INT33_R = crate::BitReader; #[doc = "Field `INT33` writer - Interrupt 33"] -pub type INT33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT33_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT34` reader - Interrupt 34"] -pub type INT34_R = crate::BitReader; +pub type INT34_R = crate::BitReader; #[doc = "Field `INT34` writer - Interrupt 34"] -pub type INT34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT34_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT35` reader - Interrupt 35"] -pub type INT35_R = crate::BitReader; +pub type INT35_R = crate::BitReader; #[doc = "Field `INT35` writer - Interrupt 35"] -pub type INT35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT35_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT36` reader - Interrupt 36"] -pub type INT36_R = crate::BitReader; +pub type INT36_R = crate::BitReader; #[doc = "Field `INT36` writer - Interrupt 36"] -pub type INT36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT36_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT37` reader - Interrupt 37"] -pub type INT37_R = crate::BitReader; +pub type INT37_R = crate::BitReader; #[doc = "Field `INT37` writer - Interrupt 37"] -pub type INT37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT37_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT38` reader - Interrupt 38"] -pub type INT38_R = crate::BitReader; +pub type INT38_R = crate::BitReader; #[doc = "Field `INT38` writer - Interrupt 38"] -pub type INT38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT38_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT39` reader - Interrupt 39"] -pub type INT39_R = crate::BitReader; +pub type INT39_R = crate::BitReader; #[doc = "Field `INT39` writer - Interrupt 39"] -pub type INT39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT39_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT40` reader - Interrupt 40"] -pub type INT40_R = crate::BitReader; +pub type INT40_R = crate::BitReader; #[doc = "Field `INT40` writer - Interrupt 40"] -pub type INT40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT40_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT41` reader - Interrupt 41"] -pub type INT41_R = crate::BitReader; +pub type INT41_R = crate::BitReader; #[doc = "Field `INT41` writer - Interrupt 41"] -pub type INT41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT41_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT42` reader - Interrupt 42"] -pub type INT42_R = crate::BitReader; +pub type INT42_R = crate::BitReader; #[doc = "Field `INT42` writer - Interrupt 42"] -pub type INT42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT42_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT43` reader - Interrupt 43"] -pub type INT43_R = crate::BitReader; +pub type INT43_R = crate::BitReader; #[doc = "Field `INT43` writer - Interrupt 43"] -pub type INT43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT43_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT44` reader - Interrupt 44"] -pub type INT44_R = crate::BitReader; +pub type INT44_R = crate::BitReader; #[doc = "Field `INT44` writer - Interrupt 44"] -pub type INT44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT44_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT45` reader - Interrupt 45"] -pub type INT45_R = crate::BitReader; +pub type INT45_R = crate::BitReader; #[doc = "Field `INT45` writer - Interrupt 45"] -pub type INT45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT45_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT46` reader - Interrupt 46"] -pub type INT46_R = crate::BitReader; +pub type INT46_R = crate::BitReader; #[doc = "Field `INT46` writer - Interrupt 46"] -pub type INT46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT46_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT47` reader - Interrupt 47"] -pub type INT47_R = crate::BitReader; +pub type INT47_R = crate::BitReader; #[doc = "Field `INT47` writer - Interrupt 47"] -pub type INT47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT47_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT48` reader - Interrupt 48"] -pub type INT48_R = crate::BitReader; +pub type INT48_R = crate::BitReader; #[doc = "Field `INT48` writer - Interrupt 48"] -pub type INT48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT48_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT49` reader - Interrupt 49"] -pub type INT49_R = crate::BitReader; +pub type INT49_R = crate::BitReader; #[doc = "Field `INT49` writer - Interrupt 49"] -pub type INT49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT49_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT50` reader - Interrupt 50"] -pub type INT50_R = crate::BitReader; +pub type INT50_R = crate::BitReader; #[doc = "Field `INT50` writer - Interrupt 50"] -pub type INT50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT50_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT51` reader - Interrupt 51"] -pub type INT51_R = crate::BitReader; +pub type INT51_R = crate::BitReader; #[doc = "Field `INT51` writer - Interrupt 51"] -pub type INT51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT51_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT52` reader - Interrupt 52"] -pub type INT52_R = crate::BitReader; +pub type INT52_R = crate::BitReader; #[doc = "Field `INT52` writer - Interrupt 52"] -pub type INT52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT52_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT53` reader - Interrupt 53"] -pub type INT53_R = crate::BitReader; +pub type INT53_R = crate::BitReader; #[doc = "Field `INT53` writer - Interrupt 53"] -pub type INT53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT53_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT54` reader - Interrupt 54"] -pub type INT54_R = crate::BitReader; +pub type INT54_R = crate::BitReader; #[doc = "Field `INT54` writer - Interrupt 54"] -pub type INT54_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT54_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT55` reader - Interrupt 55"] -pub type INT55_R = crate::BitReader; +pub type INT55_R = crate::BitReader; #[doc = "Field `INT55` writer - Interrupt 55"] -pub type INT55_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT55_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT56` reader - Interrupt 56"] -pub type INT56_R = crate::BitReader; +pub type INT56_R = crate::BitReader; #[doc = "Field `INT56` writer - Interrupt 56"] -pub type INT56_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT56_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT57` reader - Interrupt 57"] -pub type INT57_R = crate::BitReader; +pub type INT57_R = crate::BitReader; #[doc = "Field `INT57` writer - Interrupt 57"] -pub type INT57_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT57_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT58` reader - Interrupt 58"] -pub type INT58_R = crate::BitReader; +pub type INT58_R = crate::BitReader; #[doc = "Field `INT58` writer - Interrupt 58"] -pub type INT58_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT58_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT59` reader - Interrupt 59"] -pub type INT59_R = crate::BitReader; +pub type INT59_R = crate::BitReader; #[doc = "Field `INT59` writer - Interrupt 59"] -pub type INT59_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT59_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT60` reader - Interrupt 60"] -pub type INT60_R = crate::BitReader; +pub type INT60_R = crate::BitReader; #[doc = "Field `INT60` writer - Interrupt 60"] -pub type INT60_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT60_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT61` reader - Interrupt 61"] -pub type INT61_R = crate::BitReader; +pub type INT61_R = crate::BitReader; #[doc = "Field `INT61` writer - Interrupt 61"] -pub type INT61_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT61_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT62` reader - Interrupt 62"] -pub type INT62_R = crate::BitReader; +pub type INT62_R = crate::BitReader; #[doc = "Field `INT62` writer - Interrupt 62"] -pub type INT62_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT62_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT63` reader - Interrupt 63"] -pub type INT63_R = crate::BitReader; +pub type INT63_R = crate::BitReader; #[doc = "Field `INT63` writer - Interrupt 63"] -pub type INT63_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER1_SPEC, bool, O>; +pub type INT63_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT63_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISACTIVER1") + .field("int32", &format_args!("{}", self.int32().bit())) + .field("int33", &format_args!("{}", self.int33().bit())) + .field("int34", &format_args!("{}", self.int34().bit())) + .field("int35", &format_args!("{}", self.int35().bit())) + .field("int36", &format_args!("{}", self.int36().bit())) + .field("int37", &format_args!("{}", self.int37().bit())) + .field("int38", &format_args!("{}", self.int38().bit())) + .field("int39", &format_args!("{}", self.int39().bit())) + .field("int40", &format_args!("{}", self.int40().bit())) + .field("int41", &format_args!("{}", self.int41().bit())) + .field("int42", &format_args!("{}", self.int42().bit())) + .field("int43", &format_args!("{}", self.int43().bit())) + .field("int44", &format_args!("{}", self.int44().bit())) + .field("int45", &format_args!("{}", self.int45().bit())) + .field("int46", &format_args!("{}", self.int46().bit())) + .field("int47", &format_args!("{}", self.int47().bit())) + .field("int48", &format_args!("{}", self.int48().bit())) + .field("int49", &format_args!("{}", self.int49().bit())) + .field("int50", &format_args!("{}", self.int50().bit())) + .field("int51", &format_args!("{}", self.int51().bit())) + .field("int52", &format_args!("{}", self.int52().bit())) + .field("int53", &format_args!("{}", self.int53().bit())) + .field("int54", &format_args!("{}", self.int54().bit())) + .field("int55", &format_args!("{}", self.int55().bit())) + .field("int56", &format_args!("{}", self.int56().bit())) + .field("int57", &format_args!("{}", self.int57().bit())) + .field("int58", &format_args!("{}", self.int58().bit())) + .field("int59", &format_args!("{}", self.int59().bit())) + .field("int60", &format_args!("{}", self.int60().bit())) + .field("int61", &format_args!("{}", self.int61().bit())) + .field("int62", &format_args!("{}", self.int62().bit())) + .field("int63", &format_args!("{}", self.int63().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] #[must_use] - pub fn int32(&mut self) -> INT32_W<0> { + pub fn int32(&mut self) -> INT32_W { INT32_W::new(self) } #[doc = "Bit 1 - Interrupt 33"] #[inline(always)] #[must_use] - pub fn int33(&mut self) -> INT33_W<1> { + pub fn int33(&mut self) -> INT33_W { INT33_W::new(self) } #[doc = "Bit 2 - Interrupt 34"] #[inline(always)] #[must_use] - pub fn int34(&mut self) -> INT34_W<2> { + pub fn int34(&mut self) -> INT34_W { INT34_W::new(self) } #[doc = "Bit 3 - Interrupt 35"] #[inline(always)] #[must_use] - pub fn int35(&mut self) -> INT35_W<3> { + pub fn int35(&mut self) -> INT35_W { INT35_W::new(self) } #[doc = "Bit 4 - Interrupt 36"] #[inline(always)] #[must_use] - pub fn int36(&mut self) -> INT36_W<4> { + pub fn int36(&mut self) -> INT36_W { INT36_W::new(self) } #[doc = "Bit 5 - Interrupt 37"] #[inline(always)] #[must_use] - pub fn int37(&mut self) -> INT37_W<5> { + pub fn int37(&mut self) -> INT37_W { INT37_W::new(self) } #[doc = "Bit 6 - Interrupt 38"] #[inline(always)] #[must_use] - pub fn int38(&mut self) -> INT38_W<6> { + pub fn int38(&mut self) -> INT38_W { INT38_W::new(self) } #[doc = "Bit 7 - Interrupt 39"] #[inline(always)] #[must_use] - pub fn int39(&mut self) -> INT39_W<7> { + pub fn int39(&mut self) -> INT39_W { INT39_W::new(self) } #[doc = "Bit 8 - Interrupt 40"] #[inline(always)] #[must_use] - pub fn int40(&mut self) -> INT40_W<8> { + pub fn int40(&mut self) -> INT40_W { INT40_W::new(self) } #[doc = "Bit 9 - Interrupt 41"] #[inline(always)] #[must_use] - pub fn int41(&mut self) -> INT41_W<9> { + pub fn int41(&mut self) -> INT41_W { INT41_W::new(self) } #[doc = "Bit 10 - Interrupt 42"] #[inline(always)] #[must_use] - pub fn int42(&mut self) -> INT42_W<10> { + pub fn int42(&mut self) -> INT42_W { INT42_W::new(self) } #[doc = "Bit 11 - Interrupt 43"] #[inline(always)] #[must_use] - pub fn int43(&mut self) -> INT43_W<11> { + pub fn int43(&mut self) -> INT43_W { INT43_W::new(self) } #[doc = "Bit 12 - Interrupt 44"] #[inline(always)] #[must_use] - pub fn int44(&mut self) -> INT44_W<12> { + pub fn int44(&mut self) -> INT44_W { INT44_W::new(self) } #[doc = "Bit 13 - Interrupt 45"] #[inline(always)] #[must_use] - pub fn int45(&mut self) -> INT45_W<13> { + pub fn int45(&mut self) -> INT45_W { INT45_W::new(self) } #[doc = "Bit 14 - Interrupt 46"] #[inline(always)] #[must_use] - pub fn int46(&mut self) -> INT46_W<14> { + pub fn int46(&mut self) -> INT46_W { INT46_W::new(self) } #[doc = "Bit 15 - Interrupt 47"] #[inline(always)] #[must_use] - pub fn int47(&mut self) -> INT47_W<15> { + pub fn int47(&mut self) -> INT47_W { INT47_W::new(self) } #[doc = "Bit 16 - Interrupt 48"] #[inline(always)] #[must_use] - pub fn int48(&mut self) -> INT48_W<16> { + pub fn int48(&mut self) -> INT48_W { INT48_W::new(self) } #[doc = "Bit 17 - Interrupt 49"] #[inline(always)] #[must_use] - pub fn int49(&mut self) -> INT49_W<17> { + pub fn int49(&mut self) -> INT49_W { INT49_W::new(self) } #[doc = "Bit 18 - Interrupt 50"] #[inline(always)] #[must_use] - pub fn int50(&mut self) -> INT50_W<18> { + pub fn int50(&mut self) -> INT50_W { INT50_W::new(self) } #[doc = "Bit 19 - Interrupt 51"] #[inline(always)] #[must_use] - pub fn int51(&mut self) -> INT51_W<19> { + pub fn int51(&mut self) -> INT51_W { INT51_W::new(self) } #[doc = "Bit 20 - Interrupt 52"] #[inline(always)] #[must_use] - pub fn int52(&mut self) -> INT52_W<20> { + pub fn int52(&mut self) -> INT52_W { INT52_W::new(self) } #[doc = "Bit 21 - Interrupt 53"] #[inline(always)] #[must_use] - pub fn int53(&mut self) -> INT53_W<21> { + pub fn int53(&mut self) -> INT53_W { INT53_W::new(self) } #[doc = "Bit 22 - Interrupt 54"] #[inline(always)] #[must_use] - pub fn int54(&mut self) -> INT54_W<22> { + pub fn int54(&mut self) -> INT54_W { INT54_W::new(self) } #[doc = "Bit 23 - Interrupt 55"] #[inline(always)] #[must_use] - pub fn int55(&mut self) -> INT55_W<23> { + pub fn int55(&mut self) -> INT55_W { INT55_W::new(self) } #[doc = "Bit 24 - Interrupt 56"] #[inline(always)] #[must_use] - pub fn int56(&mut self) -> INT56_W<24> { + pub fn int56(&mut self) -> INT56_W { INT56_W::new(self) } #[doc = "Bit 25 - Interrupt 57"] #[inline(always)] #[must_use] - pub fn int57(&mut self) -> INT57_W<25> { + pub fn int57(&mut self) -> INT57_W { INT57_W::new(self) } #[doc = "Bit 26 - Interrupt 58"] #[inline(always)] #[must_use] - pub fn int58(&mut self) -> INT58_W<26> { + pub fn int58(&mut self) -> INT58_W { INT58_W::new(self) } #[doc = "Bit 27 - Interrupt 59"] #[inline(always)] #[must_use] - pub fn int59(&mut self) -> INT59_W<27> { + pub fn int59(&mut self) -> INT59_W { INT59_W::new(self) } #[doc = "Bit 28 - Interrupt 60"] #[inline(always)] #[must_use] - pub fn int60(&mut self) -> INT60_W<28> { + pub fn int60(&mut self) -> INT60_W { INT60_W::new(self) } #[doc = "Bit 29 - Interrupt 61"] #[inline(always)] #[must_use] - pub fn int61(&mut self) -> INT61_W<29> { + pub fn int61(&mut self) -> INT61_W { INT61_W::new(self) } #[doc = "Bit 30 - Interrupt 62"] #[inline(always)] #[must_use] - pub fn int62(&mut self) -> INT62_W<30> { + pub fn int62(&mut self) -> INT62_W { INT62_W::new(self) } #[doc = "Bit 31 - Interrupt 63"] #[inline(always)] #[must_use] - pub fn int63(&mut self) -> INT63_W<31> { + pub fn int63(&mut self) -> INT63_W { INT63_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver1](index.html) module"] +#[doc = "Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISACTIVER1_SPEC; impl crate::RegisterSpec for GICD_ISACTIVER1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isactiver1::R](R) reader structure"] -impl crate::Readable for GICD_ISACTIVER1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isactiver1::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isactiver1::R`](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isactiver1::W`](W) writer structure"] impl crate::Writable for GICD_ISACTIVER1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver2.rs index 79def40..85f88b2 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver2.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver2.rs @@ -1,171 +1,135 @@ #[doc = "Register `GICD_ISACTIVER2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISACTIVER2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI0` reader - Software interrupt 0"] -pub type SWI0_R = crate::BitReader; +pub type SWI0_R = crate::BitReader; #[doc = "Field `SWI0` writer - Software interrupt 0"] -pub type SWI0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type SWI0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI1` reader - Software interrupt 1"] -pub type SWI1_R = crate::BitReader; +pub type SWI1_R = crate::BitReader; #[doc = "Field `SWI1` writer - Software interrupt 1"] -pub type SWI1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type SWI1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI2` reader - Software interrupt 2"] -pub type SWI2_R = crate::BitReader; +pub type SWI2_R = crate::BitReader; #[doc = "Field `SWI2` writer - Software interrupt 2"] -pub type SWI2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type SWI2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI3` reader - Software interrupt 3"] -pub type SWI3_R = crate::BitReader; +pub type SWI3_R = crate::BitReader; #[doc = "Field `SWI3` writer - Software interrupt 3"] -pub type SWI3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type SWI3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI4` reader - Software interrupt 4"] -pub type SWI4_R = crate::BitReader; +pub type SWI4_R = crate::BitReader; #[doc = "Field `SWI4` writer - Software interrupt 4"] -pub type SWI4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type SWI4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI5` reader - Software interrupt 5"] -pub type SWI5_R = crate::BitReader; +pub type SWI5_R = crate::BitReader; #[doc = "Field `SWI5` writer - Software interrupt 5"] -pub type SWI5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type SWI5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI6` reader - Software interrupt 6"] -pub type SWI6_R = crate::BitReader; +pub type SWI6_R = crate::BitReader; #[doc = "Field `SWI6` writer - Software interrupt 6"] -pub type SWI6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type SWI6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI7` reader - Software interrupt 7"] -pub type SWI7_R = crate::BitReader; +pub type SWI7_R = crate::BitReader; #[doc = "Field `SWI7` writer - Software interrupt 7"] -pub type SWI7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type SWI7_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT80` reader - Interrupt 80"] -pub type INT80_R = crate::BitReader; +pub type INT80_R = crate::BitReader; #[doc = "Field `INT80` writer - Interrupt 80"] -pub type INT80_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT80_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT81` reader - Interrupt 81"] -pub type INT81_R = crate::BitReader; +pub type INT81_R = crate::BitReader; #[doc = "Field `INT81` writer - Interrupt 81"] -pub type INT81_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT81_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT82` reader - Interrupt 82"] -pub type INT82_R = crate::BitReader; +pub type INT82_R = crate::BitReader; #[doc = "Field `INT82` writer - Interrupt 82"] -pub type INT82_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT82_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT83` reader - Interrupt 83"] -pub type INT83_R = crate::BitReader; +pub type INT83_R = crate::BitReader; #[doc = "Field `INT83` writer - Interrupt 83"] -pub type INT83_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT83_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT84` reader - Interrupt 84"] -pub type INT84_R = crate::BitReader; +pub type INT84_R = crate::BitReader; #[doc = "Field `INT84` writer - Interrupt 84"] -pub type INT84_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT84_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT85` reader - Interrupt 85"] -pub type INT85_R = crate::BitReader; +pub type INT85_R = crate::BitReader; #[doc = "Field `INT85` writer - Interrupt 85"] -pub type INT85_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT85_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT86` reader - Interrupt 86"] -pub type INT86_R = crate::BitReader; +pub type INT86_R = crate::BitReader; #[doc = "Field `INT86` writer - Interrupt 86"] -pub type INT86_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT86_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT87` reader - Interrupt 87"] -pub type INT87_R = crate::BitReader; +pub type INT87_R = crate::BitReader; #[doc = "Field `INT87` writer - Interrupt 87"] -pub type INT87_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT87_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT88` reader - Interrupt 88"] -pub type INT88_R = crate::BitReader; +pub type INT88_R = crate::BitReader; #[doc = "Field `INT88` writer - Interrupt 88"] -pub type INT88_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT88_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT89` reader - Interrupt 89"] -pub type INT89_R = crate::BitReader; +pub type INT89_R = crate::BitReader; #[doc = "Field `INT89` writer - Interrupt 89"] -pub type INT89_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT89_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT90` reader - Interrupt 90"] -pub type INT90_R = crate::BitReader; +pub type INT90_R = crate::BitReader; #[doc = "Field `INT90` writer - Interrupt 90"] -pub type INT90_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT90_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT91` reader - Interrupt 91"] -pub type INT91_R = crate::BitReader; +pub type INT91_R = crate::BitReader; #[doc = "Field `INT91` writer - Interrupt 91"] -pub type INT91_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT91_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT92` reader - Interrupt 92"] -pub type INT92_R = crate::BitReader; +pub type INT92_R = crate::BitReader; #[doc = "Field `INT92` writer - Interrupt 92"] -pub type INT92_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT92_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT93` reader - Interrupt 93"] -pub type INT93_R = crate::BitReader; +pub type INT93_R = crate::BitReader; #[doc = "Field `INT93` writer - Interrupt 93"] -pub type INT93_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT93_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT94` reader - Interrupt 94"] -pub type INT94_R = crate::BitReader; +pub type INT94_R = crate::BitReader; #[doc = "Field `INT94` writer - Interrupt 94"] -pub type INT94_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT94_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT95` reader - Interrupt 95"] -pub type INT95_R = crate::BitReader; +pub type INT95_R = crate::BitReader; #[doc = "Field `INT95` writer - Interrupt 95"] -pub type INT95_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER2_SPEC, bool, O>; +pub type INT95_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -328,218 +292,268 @@ impl R { INT95_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISACTIVER2") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .field("swi0", &format_args!("{}", self.swi0().bit())) + .field("swi1", &format_args!("{}", self.swi1().bit())) + .field("swi2", &format_args!("{}", self.swi2().bit())) + .field("swi3", &format_args!("{}", self.swi3().bit())) + .field("swi4", &format_args!("{}", self.swi4().bit())) + .field("swi5", &format_args!("{}", self.swi5().bit())) + .field("swi6", &format_args!("{}", self.swi6().bit())) + .field("swi7", &format_args!("{}", self.swi7().bit())) + .field("int80", &format_args!("{}", self.int80().bit())) + .field("int81", &format_args!("{}", self.int81().bit())) + .field("int82", &format_args!("{}", self.int82().bit())) + .field("int83", &format_args!("{}", self.int83().bit())) + .field("int84", &format_args!("{}", self.int84().bit())) + .field("int85", &format_args!("{}", self.int85().bit())) + .field("int86", &format_args!("{}", self.int86().bit())) + .field("int87", &format_args!("{}", self.int87().bit())) + .field("int88", &format_args!("{}", self.int88().bit())) + .field("int89", &format_args!("{}", self.int89().bit())) + .field("int90", &format_args!("{}", self.int90().bit())) + .field("int91", &format_args!("{}", self.int91().bit())) + .field("int92", &format_args!("{}", self.int92().bit())) + .field("int93", &format_args!("{}", self.int93().bit())) + .field("int94", &format_args!("{}", self.int94().bit())) + .field("int95", &format_args!("{}", self.int95().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } #[doc = "Bit 8 - Software interrupt 0"] #[inline(always)] #[must_use] - pub fn swi0(&mut self) -> SWI0_W<8> { + pub fn swi0(&mut self) -> SWI0_W { SWI0_W::new(self) } #[doc = "Bit 9 - Software interrupt 1"] #[inline(always)] #[must_use] - pub fn swi1(&mut self) -> SWI1_W<9> { + pub fn swi1(&mut self) -> SWI1_W { SWI1_W::new(self) } #[doc = "Bit 10 - Software interrupt 2"] #[inline(always)] #[must_use] - pub fn swi2(&mut self) -> SWI2_W<10> { + pub fn swi2(&mut self) -> SWI2_W { SWI2_W::new(self) } #[doc = "Bit 11 - Software interrupt 3"] #[inline(always)] #[must_use] - pub fn swi3(&mut self) -> SWI3_W<11> { + pub fn swi3(&mut self) -> SWI3_W { SWI3_W::new(self) } #[doc = "Bit 12 - Software interrupt 4"] #[inline(always)] #[must_use] - pub fn swi4(&mut self) -> SWI4_W<12> { + pub fn swi4(&mut self) -> SWI4_W { SWI4_W::new(self) } #[doc = "Bit 13 - Software interrupt 5"] #[inline(always)] #[must_use] - pub fn swi5(&mut self) -> SWI5_W<13> { + pub fn swi5(&mut self) -> SWI5_W { SWI5_W::new(self) } #[doc = "Bit 14 - Software interrupt 6"] #[inline(always)] #[must_use] - pub fn swi6(&mut self) -> SWI6_W<14> { + pub fn swi6(&mut self) -> SWI6_W { SWI6_W::new(self) } #[doc = "Bit 15 - Software interrupt 7"] #[inline(always)] #[must_use] - pub fn swi7(&mut self) -> SWI7_W<15> { + pub fn swi7(&mut self) -> SWI7_W { SWI7_W::new(self) } #[doc = "Bit 16 - Interrupt 80"] #[inline(always)] #[must_use] - pub fn int80(&mut self) -> INT80_W<16> { + pub fn int80(&mut self) -> INT80_W { INT80_W::new(self) } #[doc = "Bit 17 - Interrupt 81"] #[inline(always)] #[must_use] - pub fn int81(&mut self) -> INT81_W<17> { + pub fn int81(&mut self) -> INT81_W { INT81_W::new(self) } #[doc = "Bit 18 - Interrupt 82"] #[inline(always)] #[must_use] - pub fn int82(&mut self) -> INT82_W<18> { + pub fn int82(&mut self) -> INT82_W { INT82_W::new(self) } #[doc = "Bit 19 - Interrupt 83"] #[inline(always)] #[must_use] - pub fn int83(&mut self) -> INT83_W<19> { + pub fn int83(&mut self) -> INT83_W { INT83_W::new(self) } #[doc = "Bit 20 - Interrupt 84"] #[inline(always)] #[must_use] - pub fn int84(&mut self) -> INT84_W<20> { + pub fn int84(&mut self) -> INT84_W { INT84_W::new(self) } #[doc = "Bit 21 - Interrupt 85"] #[inline(always)] #[must_use] - pub fn int85(&mut self) -> INT85_W<21> { + pub fn int85(&mut self) -> INT85_W { INT85_W::new(self) } #[doc = "Bit 22 - Interrupt 86"] #[inline(always)] #[must_use] - pub fn int86(&mut self) -> INT86_W<22> { + pub fn int86(&mut self) -> INT86_W { INT86_W::new(self) } #[doc = "Bit 23 - Interrupt 87"] #[inline(always)] #[must_use] - pub fn int87(&mut self) -> INT87_W<23> { + pub fn int87(&mut self) -> INT87_W { INT87_W::new(self) } #[doc = "Bit 24 - Interrupt 88"] #[inline(always)] #[must_use] - pub fn int88(&mut self) -> INT88_W<24> { + pub fn int88(&mut self) -> INT88_W { INT88_W::new(self) } #[doc = "Bit 25 - Interrupt 89"] #[inline(always)] #[must_use] - pub fn int89(&mut self) -> INT89_W<25> { + pub fn int89(&mut self) -> INT89_W { INT89_W::new(self) } #[doc = "Bit 26 - Interrupt 90"] #[inline(always)] #[must_use] - pub fn int90(&mut self) -> INT90_W<26> { + pub fn int90(&mut self) -> INT90_W { INT90_W::new(self) } #[doc = "Bit 27 - Interrupt 91"] #[inline(always)] #[must_use] - pub fn int91(&mut self) -> INT91_W<27> { + pub fn int91(&mut self) -> INT91_W { INT91_W::new(self) } #[doc = "Bit 28 - Interrupt 92"] #[inline(always)] #[must_use] - pub fn int92(&mut self) -> INT92_W<28> { + pub fn int92(&mut self) -> INT92_W { INT92_W::new(self) } #[doc = "Bit 29 - Interrupt 93"] #[inline(always)] #[must_use] - pub fn int93(&mut self) -> INT93_W<29> { + pub fn int93(&mut self) -> INT93_W { INT93_W::new(self) } #[doc = "Bit 30 - Interrupt 94"] #[inline(always)] #[must_use] - pub fn int94(&mut self) -> INT94_W<30> { + pub fn int94(&mut self) -> INT94_W { INT94_W::new(self) } #[doc = "Bit 31 - Interrupt 95"] #[inline(always)] #[must_use] - pub fn int95(&mut self) -> INT95_W<31> { + pub fn int95(&mut self) -> INT95_W { INT95_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver2](index.html) module"] +#[doc = "Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISACTIVER2_SPEC; impl crate::RegisterSpec for GICD_ISACTIVER2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isactiver2::R](R) reader structure"] -impl crate::Readable for GICD_ISACTIVER2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isactiver2::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isactiver2::R`](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isactiver2::W`](W) writer structure"] impl crate::Writable for GICD_ISACTIVER2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver3.rs index 6632953..0cb087a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver3.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver3.rs @@ -1,171 +1,135 @@ #[doc = "Register `GICD_ISACTIVER3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISACTIVER3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER3_SPEC, bool, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -328,218 +292,274 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISACTIVER3") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bit 1 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<1> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bit 2 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<2> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bit 3 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<3> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } #[doc = "Bit 4 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<4> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bit 5 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<5> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bit 6 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<6> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bit 7 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<7> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } #[doc = "Bit 8 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<8> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bit 9 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<9> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 10 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<10> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bit 11 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } #[doc = "Bit 12 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bit 13 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bit 14 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bit 15 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } #[doc = "Bit 16 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<16> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bit 17 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<17> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 18 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<18> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 19 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<19> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 20 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<20> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 21 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<21> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 22 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<22> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 23 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } #[doc = "Bit 24 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bit 25 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<25> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bit 26 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<26> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bit 27 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<27> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } #[doc = "Bit 28 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<28> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<29> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bit 30 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<30> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bit 31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<31> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver3](index.html) module"] +#[doc = "Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISACTIVER3_SPEC; impl crate::RegisterSpec for GICD_ISACTIVER3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isactiver3::R](R) reader structure"] -impl crate::Readable for GICD_ISACTIVER3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isactiver3::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isactiver3::R`](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isactiver3::W`](W) writer structure"] impl crate::Writable for GICD_ISACTIVER3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver4.rs index dbbe1e6..961a4d1 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver4.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver4.rs @@ -1,173 +1,135 @@ #[doc = "Register `GICD_ISACTIVER4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISACTIVER4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type UART_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISACTIVER4_SPEC, bool, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -330,218 +292,280 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISACTIVER4") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bit 1 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<1> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bit 2 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<2> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bit 3 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<3> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } #[doc = "Bit 4 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<4> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bit 5 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bit 6 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bit 7 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } #[doc = "Bit 8 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bit 9 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bit 10 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bit 11 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } #[doc = "Bit 12 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<12> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bit 13 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bit 15 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<15> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } #[doc = "Bit 16 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<16> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bit 17 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bit 18 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bit 19 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } #[doc = "Bit 20 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bit 21 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<21> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bit 22 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<22> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bit 23 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } #[doc = "Bit 24 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<24> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bit 25 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<25> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bit 26 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bit 27 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<27> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } #[doc = "Bit 28 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<28> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bit 29 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<29> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bit 30 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<30> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bit 31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver4](index.html) module"] +#[doc = "Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISACTIVER4_SPEC; impl crate::RegisterSpec for GICD_ISACTIVER4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isactiver4::R](R) reader structure"] -impl crate::Readable for GICD_ISACTIVER4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isactiver4::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isactiver4::R`](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isactiver4::W`](W) writer structure"] impl crate::Writable for GICD_ISACTIVER4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver5.rs index 0e275c0..0dbf3ab 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver5.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver5.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ISACTIVER5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISACTIVER5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT160` reader - Interrupt 160"] -pub type INT160_R = crate::BitReader; +pub type INT160_R = crate::BitReader; #[doc = "Field `INT160` writer - Interrupt 160"] -pub type INT160_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT160_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT161` reader - Interrupt 161"] -pub type INT161_R = crate::BitReader; +pub type INT161_R = crate::BitReader; #[doc = "Field `INT161` writer - Interrupt 161"] -pub type INT161_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT161_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT162` reader - Interrupt 162"] -pub type INT162_R = crate::BitReader; +pub type INT162_R = crate::BitReader; #[doc = "Field `INT162` writer - Interrupt 162"] -pub type INT162_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT162_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT163` reader - Interrupt 163"] -pub type INT163_R = crate::BitReader; +pub type INT163_R = crate::BitReader; #[doc = "Field `INT163` writer - Interrupt 163"] -pub type INT163_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT163_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT164` reader - Interrupt 164"] -pub type INT164_R = crate::BitReader; +pub type INT164_R = crate::BitReader; #[doc = "Field `INT164` writer - Interrupt 164"] -pub type INT164_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT164_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT165` reader - Interrupt 165"] -pub type INT165_R = crate::BitReader; +pub type INT165_R = crate::BitReader; #[doc = "Field `INT165` writer - Interrupt 165"] -pub type INT165_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT165_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT166` reader - Interrupt 166"] -pub type INT166_R = crate::BitReader; +pub type INT166_R = crate::BitReader; #[doc = "Field `INT166` writer - Interrupt 166"] -pub type INT166_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT166_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT167` reader - Interrupt 167"] -pub type INT167_R = crate::BitReader; +pub type INT167_R = crate::BitReader; #[doc = "Field `INT167` writer - Interrupt 167"] -pub type INT167_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT167_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT168` reader - Interrupt 168"] -pub type INT168_R = crate::BitReader; +pub type INT168_R = crate::BitReader; #[doc = "Field `INT168` writer - Interrupt 168"] -pub type INT168_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT168_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT169` reader - Interrupt 169"] -pub type INT169_R = crate::BitReader; +pub type INT169_R = crate::BitReader; #[doc = "Field `INT169` writer - Interrupt 169"] -pub type INT169_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT169_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT170` reader - Interrupt 170"] -pub type INT170_R = crate::BitReader; +pub type INT170_R = crate::BitReader; #[doc = "Field `INT170` writer - Interrupt 170"] -pub type INT170_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT170_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT171` reader - Interrupt 171"] -pub type INT171_R = crate::BitReader; +pub type INT171_R = crate::BitReader; #[doc = "Field `INT171` writer - Interrupt 171"] -pub type INT171_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT171_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT172` reader - Interrupt 172"] -pub type INT172_R = crate::BitReader; +pub type INT172_R = crate::BitReader; #[doc = "Field `INT172` writer - Interrupt 172"] -pub type INT172_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT172_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT173` reader - Interrupt 173"] -pub type INT173_R = crate::BitReader; +pub type INT173_R = crate::BitReader; #[doc = "Field `INT173` writer - Interrupt 173"] -pub type INT173_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT173_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT174` reader - Interrupt 174"] -pub type INT174_R = crate::BitReader; +pub type INT174_R = crate::BitReader; #[doc = "Field `INT174` writer - Interrupt 174"] -pub type INT174_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT174_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT175` reader - Interrupt 175"] -pub type INT175_R = crate::BitReader; +pub type INT175_R = crate::BitReader; #[doc = "Field `INT175` writer - Interrupt 175"] -pub type INT175_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT175_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT176` reader - Interrupt 176"] -pub type INT176_R = crate::BitReader; +pub type INT176_R = crate::BitReader; #[doc = "Field `INT176` writer - Interrupt 176"] -pub type INT176_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT176_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT177` reader - Interrupt 177"] -pub type INT177_R = crate::BitReader; +pub type INT177_R = crate::BitReader; #[doc = "Field `INT177` writer - Interrupt 177"] -pub type INT177_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT177_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT178` reader - Interrupt 178"] -pub type INT178_R = crate::BitReader; +pub type INT178_R = crate::BitReader; #[doc = "Field `INT178` writer - Interrupt 178"] -pub type INT178_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT178_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT179` reader - Interrupt 179"] -pub type INT179_R = crate::BitReader; +pub type INT179_R = crate::BitReader; #[doc = "Field `INT179` writer - Interrupt 179"] -pub type INT179_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT179_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT180` reader - Interrupt 180"] -pub type INT180_R = crate::BitReader; +pub type INT180_R = crate::BitReader; #[doc = "Field `INT180` writer - Interrupt 180"] -pub type INT180_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT180_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT181` reader - Interrupt 181"] -pub type INT181_R = crate::BitReader; +pub type INT181_R = crate::BitReader; #[doc = "Field `INT181` writer - Interrupt 181"] -pub type INT181_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT181_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT182` reader - Interrupt 182"] -pub type INT182_R = crate::BitReader; +pub type INT182_R = crate::BitReader; #[doc = "Field `INT182` writer - Interrupt 182"] -pub type INT182_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT182_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT183` reader - Interrupt 183"] -pub type INT183_R = crate::BitReader; +pub type INT183_R = crate::BitReader; #[doc = "Field `INT183` writer - Interrupt 183"] -pub type INT183_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT183_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT184` reader - Interrupt 184"] -pub type INT184_R = crate::BitReader; +pub type INT184_R = crate::BitReader; #[doc = "Field `INT184` writer - Interrupt 184"] -pub type INT184_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT184_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT185` reader - Interrupt 185"] -pub type INT185_R = crate::BitReader; +pub type INT185_R = crate::BitReader; #[doc = "Field `INT185` writer - Interrupt 185"] -pub type INT185_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT185_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT186` reader - Interrupt 186"] -pub type INT186_R = crate::BitReader; +pub type INT186_R = crate::BitReader; #[doc = "Field `INT186` writer - Interrupt 186"] -pub type INT186_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT186_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT187` reader - Interrupt 187"] -pub type INT187_R = crate::BitReader; +pub type INT187_R = crate::BitReader; #[doc = "Field `INT187` writer - Interrupt 187"] -pub type INT187_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT187_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT188` reader - Interrupt 188"] -pub type INT188_R = crate::BitReader; +pub type INT188_R = crate::BitReader; #[doc = "Field `INT188` writer - Interrupt 188"] -pub type INT188_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT188_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT189` reader - Interrupt 189"] -pub type INT189_R = crate::BitReader; +pub type INT189_R = crate::BitReader; #[doc = "Field `INT189` writer - Interrupt 189"] -pub type INT189_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT189_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT190` reader - Interrupt 190"] -pub type INT190_R = crate::BitReader; +pub type INT190_R = crate::BitReader; #[doc = "Field `INT190` writer - Interrupt 190"] -pub type INT190_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT190_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT191` reader - Interrupt 191"] -pub type INT191_R = crate::BitReader; +pub type INT191_R = crate::BitReader; #[doc = "Field `INT191` writer - Interrupt 191"] -pub type INT191_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER5_SPEC, bool, O>; +pub type INT191_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT191_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISACTIVER5") + .field("int160", &format_args!("{}", self.int160().bit())) + .field("int161", &format_args!("{}", self.int161().bit())) + .field("int162", &format_args!("{}", self.int162().bit())) + .field("int163", &format_args!("{}", self.int163().bit())) + .field("int164", &format_args!("{}", self.int164().bit())) + .field("int165", &format_args!("{}", self.int165().bit())) + .field("int166", &format_args!("{}", self.int166().bit())) + .field("int167", &format_args!("{}", self.int167().bit())) + .field("int168", &format_args!("{}", self.int168().bit())) + .field("int169", &format_args!("{}", self.int169().bit())) + .field("int170", &format_args!("{}", self.int170().bit())) + .field("int171", &format_args!("{}", self.int171().bit())) + .field("int172", &format_args!("{}", self.int172().bit())) + .field("int173", &format_args!("{}", self.int173().bit())) + .field("int174", &format_args!("{}", self.int174().bit())) + .field("int175", &format_args!("{}", self.int175().bit())) + .field("int176", &format_args!("{}", self.int176().bit())) + .field("int177", &format_args!("{}", self.int177().bit())) + .field("int178", &format_args!("{}", self.int178().bit())) + .field("int179", &format_args!("{}", self.int179().bit())) + .field("int180", &format_args!("{}", self.int180().bit())) + .field("int181", &format_args!("{}", self.int181().bit())) + .field("int182", &format_args!("{}", self.int182().bit())) + .field("int183", &format_args!("{}", self.int183().bit())) + .field("int184", &format_args!("{}", self.int184().bit())) + .field("int185", &format_args!("{}", self.int185().bit())) + .field("int186", &format_args!("{}", self.int186().bit())) + .field("int187", &format_args!("{}", self.int187().bit())) + .field("int188", &format_args!("{}", self.int188().bit())) + .field("int189", &format_args!("{}", self.int189().bit())) + .field("int190", &format_args!("{}", self.int190().bit())) + .field("int191", &format_args!("{}", self.int191().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] #[must_use] - pub fn int160(&mut self) -> INT160_W<0> { + pub fn int160(&mut self) -> INT160_W { INT160_W::new(self) } #[doc = "Bit 1 - Interrupt 161"] #[inline(always)] #[must_use] - pub fn int161(&mut self) -> INT161_W<1> { + pub fn int161(&mut self) -> INT161_W { INT161_W::new(self) } #[doc = "Bit 2 - Interrupt 162"] #[inline(always)] #[must_use] - pub fn int162(&mut self) -> INT162_W<2> { + pub fn int162(&mut self) -> INT162_W { INT162_W::new(self) } #[doc = "Bit 3 - Interrupt 163"] #[inline(always)] #[must_use] - pub fn int163(&mut self) -> INT163_W<3> { + pub fn int163(&mut self) -> INT163_W { INT163_W::new(self) } #[doc = "Bit 4 - Interrupt 164"] #[inline(always)] #[must_use] - pub fn int164(&mut self) -> INT164_W<4> { + pub fn int164(&mut self) -> INT164_W { INT164_W::new(self) } #[doc = "Bit 5 - Interrupt 165"] #[inline(always)] #[must_use] - pub fn int165(&mut self) -> INT165_W<5> { + pub fn int165(&mut self) -> INT165_W { INT165_W::new(self) } #[doc = "Bit 6 - Interrupt 166"] #[inline(always)] #[must_use] - pub fn int166(&mut self) -> INT166_W<6> { + pub fn int166(&mut self) -> INT166_W { INT166_W::new(self) } #[doc = "Bit 7 - Interrupt 167"] #[inline(always)] #[must_use] - pub fn int167(&mut self) -> INT167_W<7> { + pub fn int167(&mut self) -> INT167_W { INT167_W::new(self) } #[doc = "Bit 8 - Interrupt 168"] #[inline(always)] #[must_use] - pub fn int168(&mut self) -> INT168_W<8> { + pub fn int168(&mut self) -> INT168_W { INT168_W::new(self) } #[doc = "Bit 9 - Interrupt 169"] #[inline(always)] #[must_use] - pub fn int169(&mut self) -> INT169_W<9> { + pub fn int169(&mut self) -> INT169_W { INT169_W::new(self) } #[doc = "Bit 10 - Interrupt 170"] #[inline(always)] #[must_use] - pub fn int170(&mut self) -> INT170_W<10> { + pub fn int170(&mut self) -> INT170_W { INT170_W::new(self) } #[doc = "Bit 11 - Interrupt 171"] #[inline(always)] #[must_use] - pub fn int171(&mut self) -> INT171_W<11> { + pub fn int171(&mut self) -> INT171_W { INT171_W::new(self) } #[doc = "Bit 12 - Interrupt 172"] #[inline(always)] #[must_use] - pub fn int172(&mut self) -> INT172_W<12> { + pub fn int172(&mut self) -> INT172_W { INT172_W::new(self) } #[doc = "Bit 13 - Interrupt 173"] #[inline(always)] #[must_use] - pub fn int173(&mut self) -> INT173_W<13> { + pub fn int173(&mut self) -> INT173_W { INT173_W::new(self) } #[doc = "Bit 14 - Interrupt 174"] #[inline(always)] #[must_use] - pub fn int174(&mut self) -> INT174_W<14> { + pub fn int174(&mut self) -> INT174_W { INT174_W::new(self) } #[doc = "Bit 15 - Interrupt 175"] #[inline(always)] #[must_use] - pub fn int175(&mut self) -> INT175_W<15> { + pub fn int175(&mut self) -> INT175_W { INT175_W::new(self) } #[doc = "Bit 16 - Interrupt 176"] #[inline(always)] #[must_use] - pub fn int176(&mut self) -> INT176_W<16> { + pub fn int176(&mut self) -> INT176_W { INT176_W::new(self) } #[doc = "Bit 17 - Interrupt 177"] #[inline(always)] #[must_use] - pub fn int177(&mut self) -> INT177_W<17> { + pub fn int177(&mut self) -> INT177_W { INT177_W::new(self) } #[doc = "Bit 18 - Interrupt 178"] #[inline(always)] #[must_use] - pub fn int178(&mut self) -> INT178_W<18> { + pub fn int178(&mut self) -> INT178_W { INT178_W::new(self) } #[doc = "Bit 19 - Interrupt 179"] #[inline(always)] #[must_use] - pub fn int179(&mut self) -> INT179_W<19> { + pub fn int179(&mut self) -> INT179_W { INT179_W::new(self) } #[doc = "Bit 20 - Interrupt 180"] #[inline(always)] #[must_use] - pub fn int180(&mut self) -> INT180_W<20> { + pub fn int180(&mut self) -> INT180_W { INT180_W::new(self) } #[doc = "Bit 21 - Interrupt 181"] #[inline(always)] #[must_use] - pub fn int181(&mut self) -> INT181_W<21> { + pub fn int181(&mut self) -> INT181_W { INT181_W::new(self) } #[doc = "Bit 22 - Interrupt 182"] #[inline(always)] #[must_use] - pub fn int182(&mut self) -> INT182_W<22> { + pub fn int182(&mut self) -> INT182_W { INT182_W::new(self) } #[doc = "Bit 23 - Interrupt 183"] #[inline(always)] #[must_use] - pub fn int183(&mut self) -> INT183_W<23> { + pub fn int183(&mut self) -> INT183_W { INT183_W::new(self) } #[doc = "Bit 24 - Interrupt 184"] #[inline(always)] #[must_use] - pub fn int184(&mut self) -> INT184_W<24> { + pub fn int184(&mut self) -> INT184_W { INT184_W::new(self) } #[doc = "Bit 25 - Interrupt 185"] #[inline(always)] #[must_use] - pub fn int185(&mut self) -> INT185_W<25> { + pub fn int185(&mut self) -> INT185_W { INT185_W::new(self) } #[doc = "Bit 26 - Interrupt 186"] #[inline(always)] #[must_use] - pub fn int186(&mut self) -> INT186_W<26> { + pub fn int186(&mut self) -> INT186_W { INT186_W::new(self) } #[doc = "Bit 27 - Interrupt 187"] #[inline(always)] #[must_use] - pub fn int187(&mut self) -> INT187_W<27> { + pub fn int187(&mut self) -> INT187_W { INT187_W::new(self) } #[doc = "Bit 28 - Interrupt 188"] #[inline(always)] #[must_use] - pub fn int188(&mut self) -> INT188_W<28> { + pub fn int188(&mut self) -> INT188_W { INT188_W::new(self) } #[doc = "Bit 29 - Interrupt 189"] #[inline(always)] #[must_use] - pub fn int189(&mut self) -> INT189_W<29> { + pub fn int189(&mut self) -> INT189_W { INT189_W::new(self) } #[doc = "Bit 30 - Interrupt 190"] #[inline(always)] #[must_use] - pub fn int190(&mut self) -> INT190_W<30> { + pub fn int190(&mut self) -> INT190_W { INT190_W::new(self) } #[doc = "Bit 31 - Interrupt 191"] #[inline(always)] #[must_use] - pub fn int191(&mut self) -> INT191_W<31> { + pub fn int191(&mut self) -> INT191_W { INT191_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver5](index.html) module"] +#[doc = "Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISACTIVER5_SPEC; impl crate::RegisterSpec for GICD_ISACTIVER5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isactiver5::R](R) reader structure"] -impl crate::Readable for GICD_ISACTIVER5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isactiver5::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isactiver5::R`](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isactiver5::W`](W) writer structure"] impl crate::Writable for GICD_ISACTIVER5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver6.rs index e048a3a..721b7d5 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver6.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isactiver/gicd_isactiver6.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ISACTIVER6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISACTIVER6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT192` reader - Interrupt 192"] -pub type INT192_R = crate::BitReader; +pub type INT192_R = crate::BitReader; #[doc = "Field `INT192` writer - Interrupt 192"] -pub type INT192_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT192_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT193` reader - Interrupt 193"] -pub type INT193_R = crate::BitReader; +pub type INT193_R = crate::BitReader; #[doc = "Field `INT193` writer - Interrupt 193"] -pub type INT193_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT193_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT194` reader - Interrupt 194"] -pub type INT194_R = crate::BitReader; +pub type INT194_R = crate::BitReader; #[doc = "Field `INT194` writer - Interrupt 194"] -pub type INT194_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT194_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT195` reader - Interrupt 195"] -pub type INT195_R = crate::BitReader; +pub type INT195_R = crate::BitReader; #[doc = "Field `INT195` writer - Interrupt 195"] -pub type INT195_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT195_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT196` reader - Interrupt 196"] -pub type INT196_R = crate::BitReader; +pub type INT196_R = crate::BitReader; #[doc = "Field `INT196` writer - Interrupt 196"] -pub type INT196_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT196_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT197` reader - Interrupt 197"] -pub type INT197_R = crate::BitReader; +pub type INT197_R = crate::BitReader; #[doc = "Field `INT197` writer - Interrupt 197"] -pub type INT197_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT197_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT198` reader - Interrupt 198"] -pub type INT198_R = crate::BitReader; +pub type INT198_R = crate::BitReader; #[doc = "Field `INT198` writer - Interrupt 198"] -pub type INT198_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT198_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT199` reader - Interrupt 199"] -pub type INT199_R = crate::BitReader; +pub type INT199_R = crate::BitReader; #[doc = "Field `INT199` writer - Interrupt 199"] -pub type INT199_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT199_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT200` reader - Interrupt 200"] -pub type INT200_R = crate::BitReader; +pub type INT200_R = crate::BitReader; #[doc = "Field `INT200` writer - Interrupt 200"] -pub type INT200_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT200_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT201` reader - Interrupt 201"] -pub type INT201_R = crate::BitReader; +pub type INT201_R = crate::BitReader; #[doc = "Field `INT201` writer - Interrupt 201"] -pub type INT201_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT201_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT202` reader - Interrupt 202"] -pub type INT202_R = crate::BitReader; +pub type INT202_R = crate::BitReader; #[doc = "Field `INT202` writer - Interrupt 202"] -pub type INT202_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT202_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT203` reader - Interrupt 203"] -pub type INT203_R = crate::BitReader; +pub type INT203_R = crate::BitReader; #[doc = "Field `INT203` writer - Interrupt 203"] -pub type INT203_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT203_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT204` reader - Interrupt 204"] -pub type INT204_R = crate::BitReader; +pub type INT204_R = crate::BitReader; #[doc = "Field `INT204` writer - Interrupt 204"] -pub type INT204_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT204_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT205` reader - Interrupt 205"] -pub type INT205_R = crate::BitReader; +pub type INT205_R = crate::BitReader; #[doc = "Field `INT205` writer - Interrupt 205"] -pub type INT205_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT205_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT206` reader - Interrupt 206"] -pub type INT206_R = crate::BitReader; +pub type INT206_R = crate::BitReader; #[doc = "Field `INT206` writer - Interrupt 206"] -pub type INT206_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT206_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT207` reader - Interrupt 207"] -pub type INT207_R = crate::BitReader; +pub type INT207_R = crate::BitReader; #[doc = "Field `INT207` writer - Interrupt 207"] -pub type INT207_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT207_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT208` reader - Interrupt 208"] -pub type INT208_R = crate::BitReader; +pub type INT208_R = crate::BitReader; #[doc = "Field `INT208` writer - Interrupt 208"] -pub type INT208_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT208_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT209` reader - Interrupt 209"] -pub type INT209_R = crate::BitReader; +pub type INT209_R = crate::BitReader; #[doc = "Field `INT209` writer - Interrupt 209"] -pub type INT209_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT209_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT210` reader - Interrupt 210"] -pub type INT210_R = crate::BitReader; +pub type INT210_R = crate::BitReader; #[doc = "Field `INT210` writer - Interrupt 210"] -pub type INT210_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT210_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT211` reader - Interrupt 211"] -pub type INT211_R = crate::BitReader; +pub type INT211_R = crate::BitReader; #[doc = "Field `INT211` writer - Interrupt 211"] -pub type INT211_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT211_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT212` reader - Interrupt 212"] -pub type INT212_R = crate::BitReader; +pub type INT212_R = crate::BitReader; #[doc = "Field `INT212` writer - Interrupt 212"] -pub type INT212_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT212_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT213` reader - Interrupt 213"] -pub type INT213_R = crate::BitReader; +pub type INT213_R = crate::BitReader; #[doc = "Field `INT213` writer - Interrupt 213"] -pub type INT213_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT213_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT214` reader - Interrupt 214"] -pub type INT214_R = crate::BitReader; +pub type INT214_R = crate::BitReader; #[doc = "Field `INT214` writer - Interrupt 214"] -pub type INT214_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT214_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT215` reader - Interrupt 215"] -pub type INT215_R = crate::BitReader; +pub type INT215_R = crate::BitReader; #[doc = "Field `INT215` writer - Interrupt 215"] -pub type INT215_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT215_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT216` reader - Interrupt 216"] -pub type INT216_R = crate::BitReader; +pub type INT216_R = crate::BitReader; #[doc = "Field `INT216` writer - Interrupt 216"] -pub type INT216_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT216_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT217` reader - Interrupt 217"] -pub type INT217_R = crate::BitReader; +pub type INT217_R = crate::BitReader; #[doc = "Field `INT217` writer - Interrupt 217"] -pub type INT217_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT217_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT218` reader - Interrupt 218"] -pub type INT218_R = crate::BitReader; +pub type INT218_R = crate::BitReader; #[doc = "Field `INT218` writer - Interrupt 218"] -pub type INT218_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT218_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT219` reader - Interrupt 219"] -pub type INT219_R = crate::BitReader; +pub type INT219_R = crate::BitReader; #[doc = "Field `INT219` writer - Interrupt 219"] -pub type INT219_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT219_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT220` reader - Interrupt 220"] -pub type INT220_R = crate::BitReader; +pub type INT220_R = crate::BitReader; #[doc = "Field `INT220` writer - Interrupt 220"] -pub type INT220_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT220_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT221` reader - Interrupt 221"] -pub type INT221_R = crate::BitReader; +pub type INT221_R = crate::BitReader; #[doc = "Field `INT221` writer - Interrupt 221"] -pub type INT221_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT221_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT222` reader - Interrupt 222"] -pub type INT222_R = crate::BitReader; +pub type INT222_R = crate::BitReader; #[doc = "Field `INT222` writer - Interrupt 222"] -pub type INT222_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT222_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT223` reader - Interrupt 223"] -pub type INT223_R = crate::BitReader; +pub type INT223_R = crate::BitReader; #[doc = "Field `INT223` writer - Interrupt 223"] -pub type INT223_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISACTIVER6_SPEC, bool, O>; +pub type INT223_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT223_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISACTIVER6") + .field("int192", &format_args!("{}", self.int192().bit())) + .field("int193", &format_args!("{}", self.int193().bit())) + .field("int194", &format_args!("{}", self.int194().bit())) + .field("int195", &format_args!("{}", self.int195().bit())) + .field("int196", &format_args!("{}", self.int196().bit())) + .field("int197", &format_args!("{}", self.int197().bit())) + .field("int198", &format_args!("{}", self.int198().bit())) + .field("int199", &format_args!("{}", self.int199().bit())) + .field("int200", &format_args!("{}", self.int200().bit())) + .field("int201", &format_args!("{}", self.int201().bit())) + .field("int202", &format_args!("{}", self.int202().bit())) + .field("int203", &format_args!("{}", self.int203().bit())) + .field("int204", &format_args!("{}", self.int204().bit())) + .field("int205", &format_args!("{}", self.int205().bit())) + .field("int206", &format_args!("{}", self.int206().bit())) + .field("int207", &format_args!("{}", self.int207().bit())) + .field("int208", &format_args!("{}", self.int208().bit())) + .field("int209", &format_args!("{}", self.int209().bit())) + .field("int210", &format_args!("{}", self.int210().bit())) + .field("int211", &format_args!("{}", self.int211().bit())) + .field("int212", &format_args!("{}", self.int212().bit())) + .field("int213", &format_args!("{}", self.int213().bit())) + .field("int214", &format_args!("{}", self.int214().bit())) + .field("int215", &format_args!("{}", self.int215().bit())) + .field("int216", &format_args!("{}", self.int216().bit())) + .field("int217", &format_args!("{}", self.int217().bit())) + .field("int218", &format_args!("{}", self.int218().bit())) + .field("int219", &format_args!("{}", self.int219().bit())) + .field("int220", &format_args!("{}", self.int220().bit())) + .field("int221", &format_args!("{}", self.int221().bit())) + .field("int222", &format_args!("{}", self.int222().bit())) + .field("int223", &format_args!("{}", self.int223().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] #[must_use] - pub fn int192(&mut self) -> INT192_W<0> { + pub fn int192(&mut self) -> INT192_W { INT192_W::new(self) } #[doc = "Bit 1 - Interrupt 193"] #[inline(always)] #[must_use] - pub fn int193(&mut self) -> INT193_W<1> { + pub fn int193(&mut self) -> INT193_W { INT193_W::new(self) } #[doc = "Bit 2 - Interrupt 194"] #[inline(always)] #[must_use] - pub fn int194(&mut self) -> INT194_W<2> { + pub fn int194(&mut self) -> INT194_W { INT194_W::new(self) } #[doc = "Bit 3 - Interrupt 195"] #[inline(always)] #[must_use] - pub fn int195(&mut self) -> INT195_W<3> { + pub fn int195(&mut self) -> INT195_W { INT195_W::new(self) } #[doc = "Bit 4 - Interrupt 196"] #[inline(always)] #[must_use] - pub fn int196(&mut self) -> INT196_W<4> { + pub fn int196(&mut self) -> INT196_W { INT196_W::new(self) } #[doc = "Bit 5 - Interrupt 197"] #[inline(always)] #[must_use] - pub fn int197(&mut self) -> INT197_W<5> { + pub fn int197(&mut self) -> INT197_W { INT197_W::new(self) } #[doc = "Bit 6 - Interrupt 198"] #[inline(always)] #[must_use] - pub fn int198(&mut self) -> INT198_W<6> { + pub fn int198(&mut self) -> INT198_W { INT198_W::new(self) } #[doc = "Bit 7 - Interrupt 199"] #[inline(always)] #[must_use] - pub fn int199(&mut self) -> INT199_W<7> { + pub fn int199(&mut self) -> INT199_W { INT199_W::new(self) } #[doc = "Bit 8 - Interrupt 200"] #[inline(always)] #[must_use] - pub fn int200(&mut self) -> INT200_W<8> { + pub fn int200(&mut self) -> INT200_W { INT200_W::new(self) } #[doc = "Bit 9 - Interrupt 201"] #[inline(always)] #[must_use] - pub fn int201(&mut self) -> INT201_W<9> { + pub fn int201(&mut self) -> INT201_W { INT201_W::new(self) } #[doc = "Bit 10 - Interrupt 202"] #[inline(always)] #[must_use] - pub fn int202(&mut self) -> INT202_W<10> { + pub fn int202(&mut self) -> INT202_W { INT202_W::new(self) } #[doc = "Bit 11 - Interrupt 203"] #[inline(always)] #[must_use] - pub fn int203(&mut self) -> INT203_W<11> { + pub fn int203(&mut self) -> INT203_W { INT203_W::new(self) } #[doc = "Bit 12 - Interrupt 204"] #[inline(always)] #[must_use] - pub fn int204(&mut self) -> INT204_W<12> { + pub fn int204(&mut self) -> INT204_W { INT204_W::new(self) } #[doc = "Bit 13 - Interrupt 205"] #[inline(always)] #[must_use] - pub fn int205(&mut self) -> INT205_W<13> { + pub fn int205(&mut self) -> INT205_W { INT205_W::new(self) } #[doc = "Bit 14 - Interrupt 206"] #[inline(always)] #[must_use] - pub fn int206(&mut self) -> INT206_W<14> { + pub fn int206(&mut self) -> INT206_W { INT206_W::new(self) } #[doc = "Bit 15 - Interrupt 207"] #[inline(always)] #[must_use] - pub fn int207(&mut self) -> INT207_W<15> { + pub fn int207(&mut self) -> INT207_W { INT207_W::new(self) } #[doc = "Bit 16 - Interrupt 208"] #[inline(always)] #[must_use] - pub fn int208(&mut self) -> INT208_W<16> { + pub fn int208(&mut self) -> INT208_W { INT208_W::new(self) } #[doc = "Bit 17 - Interrupt 209"] #[inline(always)] #[must_use] - pub fn int209(&mut self) -> INT209_W<17> { + pub fn int209(&mut self) -> INT209_W { INT209_W::new(self) } #[doc = "Bit 18 - Interrupt 210"] #[inline(always)] #[must_use] - pub fn int210(&mut self) -> INT210_W<18> { + pub fn int210(&mut self) -> INT210_W { INT210_W::new(self) } #[doc = "Bit 19 - Interrupt 211"] #[inline(always)] #[must_use] - pub fn int211(&mut self) -> INT211_W<19> { + pub fn int211(&mut self) -> INT211_W { INT211_W::new(self) } #[doc = "Bit 20 - Interrupt 212"] #[inline(always)] #[must_use] - pub fn int212(&mut self) -> INT212_W<20> { + pub fn int212(&mut self) -> INT212_W { INT212_W::new(self) } #[doc = "Bit 21 - Interrupt 213"] #[inline(always)] #[must_use] - pub fn int213(&mut self) -> INT213_W<21> { + pub fn int213(&mut self) -> INT213_W { INT213_W::new(self) } #[doc = "Bit 22 - Interrupt 214"] #[inline(always)] #[must_use] - pub fn int214(&mut self) -> INT214_W<22> { + pub fn int214(&mut self) -> INT214_W { INT214_W::new(self) } #[doc = "Bit 23 - Interrupt 215"] #[inline(always)] #[must_use] - pub fn int215(&mut self) -> INT215_W<23> { + pub fn int215(&mut self) -> INT215_W { INT215_W::new(self) } #[doc = "Bit 24 - Interrupt 216"] #[inline(always)] #[must_use] - pub fn int216(&mut self) -> INT216_W<24> { + pub fn int216(&mut self) -> INT216_W { INT216_W::new(self) } #[doc = "Bit 25 - Interrupt 217"] #[inline(always)] #[must_use] - pub fn int217(&mut self) -> INT217_W<25> { + pub fn int217(&mut self) -> INT217_W { INT217_W::new(self) } #[doc = "Bit 26 - Interrupt 218"] #[inline(always)] #[must_use] - pub fn int218(&mut self) -> INT218_W<26> { + pub fn int218(&mut self) -> INT218_W { INT218_W::new(self) } #[doc = "Bit 27 - Interrupt 219"] #[inline(always)] #[must_use] - pub fn int219(&mut self) -> INT219_W<27> { + pub fn int219(&mut self) -> INT219_W { INT219_W::new(self) } #[doc = "Bit 28 - Interrupt 220"] #[inline(always)] #[must_use] - pub fn int220(&mut self) -> INT220_W<28> { + pub fn int220(&mut self) -> INT220_W { INT220_W::new(self) } #[doc = "Bit 29 - Interrupt 221"] #[inline(always)] #[must_use] - pub fn int221(&mut self) -> INT221_W<29> { + pub fn int221(&mut self) -> INT221_W { INT221_W::new(self) } #[doc = "Bit 30 - Interrupt 222"] #[inline(always)] #[must_use] - pub fn int222(&mut self) -> INT222_W<30> { + pub fn int222(&mut self) -> INT222_W { INT222_W::new(self) } #[doc = "Bit 31 - Interrupt 223"] #[inline(always)] #[must_use] - pub fn int223(&mut self) -> INT223_W<31> { + pub fn int223(&mut self) -> INT223_W { INT223_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Active\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isactiver6](index.html) module"] +#[doc = "Interrupt Set-Active\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isactiver6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isactiver6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISACTIVER6_SPEC; impl crate::RegisterSpec for GICD_ISACTIVER6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isactiver6::R](R) reader structure"] -impl crate::Readable for GICD_ISACTIVER6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isactiver6::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isactiver6::R`](R) reader structure"] +impl crate::Readable for GICD_ISACTIVER6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isactiver6::W`](W) writer structure"] impl crate::Writable for GICD_ISACTIVER6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler.rs index b7b571a..5216faf 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct GICD_ISENABLER { #[doc = "0x00 - Interrupt Set-Enable"] pub gicd_isenabler0: GICD_ISENABLER0, @@ -16,31 +17,38 @@ pub struct GICD_ISENABLER { #[doc = "0x18 - Interrupt Set-Enable"] pub gicd_isenabler6: GICD_ISENABLER6, } -#[doc = "GICD_ISENABLER0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISENABLER0 (rw) register accessor: Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isenabler0`] +module"] pub type GICD_ISENABLER0 = crate::Reg; #[doc = "Interrupt Set-Enable"] pub mod gicd_isenabler0; -#[doc = "GICD_ISENABLER1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISENABLER1 (rw) register accessor: Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isenabler1`] +module"] pub type GICD_ISENABLER1 = crate::Reg; #[doc = "Interrupt Set-Enable"] pub mod gicd_isenabler1; -#[doc = "GICD_ISENABLER2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISENABLER2 (rw) register accessor: Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isenabler2`] +module"] pub type GICD_ISENABLER2 = crate::Reg; #[doc = "Interrupt Set-Enable"] pub mod gicd_isenabler2; -#[doc = "GICD_ISENABLER3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISENABLER3 (rw) register accessor: Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isenabler3`] +module"] pub type GICD_ISENABLER3 = crate::Reg; #[doc = "Interrupt Set-Enable"] pub mod gicd_isenabler3; -#[doc = "GICD_ISENABLER4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISENABLER4 (rw) register accessor: Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isenabler4`] +module"] pub type GICD_ISENABLER4 = crate::Reg; #[doc = "Interrupt Set-Enable"] pub mod gicd_isenabler4; -#[doc = "GICD_ISENABLER5 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISENABLER5 (rw) register accessor: Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isenabler5`] +module"] pub type GICD_ISENABLER5 = crate::Reg; #[doc = "Interrupt Set-Enable"] pub mod gicd_isenabler5; -#[doc = "GICD_ISENABLER6 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISENABLER6 (rw) register accessor: Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_isenabler6`] +module"] pub type GICD_ISENABLER6 = crate::Reg; #[doc = "Interrupt Set-Enable"] pub mod gicd_isenabler6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler0.rs index 339c946..9b50ed8 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler0.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ISENABLER0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISENABLER0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT0` reader - Interrupt 0"] -pub type INT0_R = crate::BitReader; +pub type INT0_R = crate::BitReader; #[doc = "Field `INT0` writer - Interrupt 0"] -pub type INT0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT1` reader - Interrupt 1"] -pub type INT1_R = crate::BitReader; +pub type INT1_R = crate::BitReader; #[doc = "Field `INT1` writer - Interrupt 1"] -pub type INT1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT2` reader - Interrupt 2"] -pub type INT2_R = crate::BitReader; +pub type INT2_R = crate::BitReader; #[doc = "Field `INT2` writer - Interrupt 2"] -pub type INT2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT3` reader - Interrupt 3"] -pub type INT3_R = crate::BitReader; +pub type INT3_R = crate::BitReader; #[doc = "Field `INT3` writer - Interrupt 3"] -pub type INT3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT4` reader - Interrupt 4"] -pub type INT4_R = crate::BitReader; +pub type INT4_R = crate::BitReader; #[doc = "Field `INT4` writer - Interrupt 4"] -pub type INT4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT5` reader - Interrupt 5"] -pub type INT5_R = crate::BitReader; +pub type INT5_R = crate::BitReader; #[doc = "Field `INT5` writer - Interrupt 5"] -pub type INT5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT6` reader - Interrupt 6"] -pub type INT6_R = crate::BitReader; +pub type INT6_R = crate::BitReader; #[doc = "Field `INT6` writer - Interrupt 6"] -pub type INT6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT7` reader - Interrupt 7"] -pub type INT7_R = crate::BitReader; +pub type INT7_R = crate::BitReader; #[doc = "Field `INT7` writer - Interrupt 7"] -pub type INT7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT7_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT8` reader - Interrupt 8"] -pub type INT8_R = crate::BitReader; +pub type INT8_R = crate::BitReader; #[doc = "Field `INT8` writer - Interrupt 8"] -pub type INT8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT8_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT9` reader - Interrupt 9"] -pub type INT9_R = crate::BitReader; +pub type INT9_R = crate::BitReader; #[doc = "Field `INT9` writer - Interrupt 9"] -pub type INT9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT9_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT10` reader - Interrupt 10"] -pub type INT10_R = crate::BitReader; +pub type INT10_R = crate::BitReader; #[doc = "Field `INT10` writer - Interrupt 10"] -pub type INT10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT10_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT11` reader - Interrupt 11"] -pub type INT11_R = crate::BitReader; +pub type INT11_R = crate::BitReader; #[doc = "Field `INT11` writer - Interrupt 11"] -pub type INT11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT11_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT12` reader - Interrupt 12"] -pub type INT12_R = crate::BitReader; +pub type INT12_R = crate::BitReader; #[doc = "Field `INT12` writer - Interrupt 12"] -pub type INT12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT12_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT13` reader - Interrupt 13"] -pub type INT13_R = crate::BitReader; +pub type INT13_R = crate::BitReader; #[doc = "Field `INT13` writer - Interrupt 13"] -pub type INT13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT13_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT14` reader - Interrupt 14"] -pub type INT14_R = crate::BitReader; +pub type INT14_R = crate::BitReader; #[doc = "Field `INT14` writer - Interrupt 14"] -pub type INT14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT14_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT15` reader - Interrupt 15"] -pub type INT15_R = crate::BitReader; +pub type INT15_R = crate::BitReader; #[doc = "Field `INT15` writer - Interrupt 15"] -pub type INT15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT15_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT16` reader - Interrupt 16"] -pub type INT16_R = crate::BitReader; +pub type INT16_R = crate::BitReader; #[doc = "Field `INT16` writer - Interrupt 16"] -pub type INT16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT16_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT17` reader - Interrupt 17"] -pub type INT17_R = crate::BitReader; +pub type INT17_R = crate::BitReader; #[doc = "Field `INT17` writer - Interrupt 17"] -pub type INT17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT17_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT18` reader - Interrupt 18"] -pub type INT18_R = crate::BitReader; +pub type INT18_R = crate::BitReader; #[doc = "Field `INT18` writer - Interrupt 18"] -pub type INT18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT18_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT19` reader - Interrupt 19"] -pub type INT19_R = crate::BitReader; +pub type INT19_R = crate::BitReader; #[doc = "Field `INT19` writer - Interrupt 19"] -pub type INT19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT19_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT20` reader - Interrupt 20"] -pub type INT20_R = crate::BitReader; +pub type INT20_R = crate::BitReader; #[doc = "Field `INT20` writer - Interrupt 20"] -pub type INT20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT20_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT21` reader - Interrupt 21"] -pub type INT21_R = crate::BitReader; +pub type INT21_R = crate::BitReader; #[doc = "Field `INT21` writer - Interrupt 21"] -pub type INT21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT21_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT22` reader - Interrupt 22"] -pub type INT22_R = crate::BitReader; +pub type INT22_R = crate::BitReader; #[doc = "Field `INT22` writer - Interrupt 22"] -pub type INT22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT22_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT23` reader - Interrupt 23"] -pub type INT23_R = crate::BitReader; +pub type INT23_R = crate::BitReader; #[doc = "Field `INT23` writer - Interrupt 23"] -pub type INT23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT23_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT24` reader - Interrupt 24"] -pub type INT24_R = crate::BitReader; +pub type INT24_R = crate::BitReader; #[doc = "Field `INT24` writer - Interrupt 24"] -pub type INT24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT24_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT25` reader - Interrupt 25"] -pub type INT25_R = crate::BitReader; +pub type INT25_R = crate::BitReader; #[doc = "Field `INT25` writer - Interrupt 25"] -pub type INT25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT25_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT26` reader - Interrupt 26"] -pub type INT26_R = crate::BitReader; +pub type INT26_R = crate::BitReader; #[doc = "Field `INT26` writer - Interrupt 26"] -pub type INT26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT26_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT27` reader - Interrupt 27"] -pub type INT27_R = crate::BitReader; +pub type INT27_R = crate::BitReader; #[doc = "Field `INT27` writer - Interrupt 27"] -pub type INT27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT27_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT28` reader - Interrupt 28"] -pub type INT28_R = crate::BitReader; +pub type INT28_R = crate::BitReader; #[doc = "Field `INT28` writer - Interrupt 28"] -pub type INT28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT28_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT29` reader - Interrupt 29"] -pub type INT29_R = crate::BitReader; +pub type INT29_R = crate::BitReader; #[doc = "Field `INT29` writer - Interrupt 29"] -pub type INT29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT29_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT30` reader - Interrupt 30"] -pub type INT30_R = crate::BitReader; +pub type INT30_R = crate::BitReader; #[doc = "Field `INT30` writer - Interrupt 30"] -pub type INT30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT30_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT31` reader - Interrupt 31"] -pub type INT31_R = crate::BitReader; +pub type INT31_R = crate::BitReader; #[doc = "Field `INT31` writer - Interrupt 31"] -pub type INT31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER0_SPEC, bool, O>; +pub type INT31_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISENABLER0") + .field("int0", &format_args!("{}", self.int0().bit())) + .field("int1", &format_args!("{}", self.int1().bit())) + .field("int2", &format_args!("{}", self.int2().bit())) + .field("int3", &format_args!("{}", self.int3().bit())) + .field("int4", &format_args!("{}", self.int4().bit())) + .field("int5", &format_args!("{}", self.int5().bit())) + .field("int6", &format_args!("{}", self.int6().bit())) + .field("int7", &format_args!("{}", self.int7().bit())) + .field("int8", &format_args!("{}", self.int8().bit())) + .field("int9", &format_args!("{}", self.int9().bit())) + .field("int10", &format_args!("{}", self.int10().bit())) + .field("int11", &format_args!("{}", self.int11().bit())) + .field("int12", &format_args!("{}", self.int12().bit())) + .field("int13", &format_args!("{}", self.int13().bit())) + .field("int14", &format_args!("{}", self.int14().bit())) + .field("int15", &format_args!("{}", self.int15().bit())) + .field("int16", &format_args!("{}", self.int16().bit())) + .field("int17", &format_args!("{}", self.int17().bit())) + .field("int18", &format_args!("{}", self.int18().bit())) + .field("int19", &format_args!("{}", self.int19().bit())) + .field("int20", &format_args!("{}", self.int20().bit())) + .field("int21", &format_args!("{}", self.int21().bit())) + .field("int22", &format_args!("{}", self.int22().bit())) + .field("int23", &format_args!("{}", self.int23().bit())) + .field("int24", &format_args!("{}", self.int24().bit())) + .field("int25", &format_args!("{}", self.int25().bit())) + .field("int26", &format_args!("{}", self.int26().bit())) + .field("int27", &format_args!("{}", self.int27().bit())) + .field("int28", &format_args!("{}", self.int28().bit())) + .field("int29", &format_args!("{}", self.int29().bit())) + .field("int30", &format_args!("{}", self.int30().bit())) + .field("int31", &format_args!("{}", self.int31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] #[must_use] - pub fn int0(&mut self) -> INT0_W<0> { + pub fn int0(&mut self) -> INT0_W { INT0_W::new(self) } #[doc = "Bit 1 - Interrupt 1"] #[inline(always)] #[must_use] - pub fn int1(&mut self) -> INT1_W<1> { + pub fn int1(&mut self) -> INT1_W { INT1_W::new(self) } #[doc = "Bit 2 - Interrupt 2"] #[inline(always)] #[must_use] - pub fn int2(&mut self) -> INT2_W<2> { + pub fn int2(&mut self) -> INT2_W { INT2_W::new(self) } #[doc = "Bit 3 - Interrupt 3"] #[inline(always)] #[must_use] - pub fn int3(&mut self) -> INT3_W<3> { + pub fn int3(&mut self) -> INT3_W { INT3_W::new(self) } #[doc = "Bit 4 - Interrupt 4"] #[inline(always)] #[must_use] - pub fn int4(&mut self) -> INT4_W<4> { + pub fn int4(&mut self) -> INT4_W { INT4_W::new(self) } #[doc = "Bit 5 - Interrupt 5"] #[inline(always)] #[must_use] - pub fn int5(&mut self) -> INT5_W<5> { + pub fn int5(&mut self) -> INT5_W { INT5_W::new(self) } #[doc = "Bit 6 - Interrupt 6"] #[inline(always)] #[must_use] - pub fn int6(&mut self) -> INT6_W<6> { + pub fn int6(&mut self) -> INT6_W { INT6_W::new(self) } #[doc = "Bit 7 - Interrupt 7"] #[inline(always)] #[must_use] - pub fn int7(&mut self) -> INT7_W<7> { + pub fn int7(&mut self) -> INT7_W { INT7_W::new(self) } #[doc = "Bit 8 - Interrupt 8"] #[inline(always)] #[must_use] - pub fn int8(&mut self) -> INT8_W<8> { + pub fn int8(&mut self) -> INT8_W { INT8_W::new(self) } #[doc = "Bit 9 - Interrupt 9"] #[inline(always)] #[must_use] - pub fn int9(&mut self) -> INT9_W<9> { + pub fn int9(&mut self) -> INT9_W { INT9_W::new(self) } #[doc = "Bit 10 - Interrupt 10"] #[inline(always)] #[must_use] - pub fn int10(&mut self) -> INT10_W<10> { + pub fn int10(&mut self) -> INT10_W { INT10_W::new(self) } #[doc = "Bit 11 - Interrupt 11"] #[inline(always)] #[must_use] - pub fn int11(&mut self) -> INT11_W<11> { + pub fn int11(&mut self) -> INT11_W { INT11_W::new(self) } #[doc = "Bit 12 - Interrupt 12"] #[inline(always)] #[must_use] - pub fn int12(&mut self) -> INT12_W<12> { + pub fn int12(&mut self) -> INT12_W { INT12_W::new(self) } #[doc = "Bit 13 - Interrupt 13"] #[inline(always)] #[must_use] - pub fn int13(&mut self) -> INT13_W<13> { + pub fn int13(&mut self) -> INT13_W { INT13_W::new(self) } #[doc = "Bit 14 - Interrupt 14"] #[inline(always)] #[must_use] - pub fn int14(&mut self) -> INT14_W<14> { + pub fn int14(&mut self) -> INT14_W { INT14_W::new(self) } #[doc = "Bit 15 - Interrupt 15"] #[inline(always)] #[must_use] - pub fn int15(&mut self) -> INT15_W<15> { + pub fn int15(&mut self) -> INT15_W { INT15_W::new(self) } #[doc = "Bit 16 - Interrupt 16"] #[inline(always)] #[must_use] - pub fn int16(&mut self) -> INT16_W<16> { + pub fn int16(&mut self) -> INT16_W { INT16_W::new(self) } #[doc = "Bit 17 - Interrupt 17"] #[inline(always)] #[must_use] - pub fn int17(&mut self) -> INT17_W<17> { + pub fn int17(&mut self) -> INT17_W { INT17_W::new(self) } #[doc = "Bit 18 - Interrupt 18"] #[inline(always)] #[must_use] - pub fn int18(&mut self) -> INT18_W<18> { + pub fn int18(&mut self) -> INT18_W { INT18_W::new(self) } #[doc = "Bit 19 - Interrupt 19"] #[inline(always)] #[must_use] - pub fn int19(&mut self) -> INT19_W<19> { + pub fn int19(&mut self) -> INT19_W { INT19_W::new(self) } #[doc = "Bit 20 - Interrupt 20"] #[inline(always)] #[must_use] - pub fn int20(&mut self) -> INT20_W<20> { + pub fn int20(&mut self) -> INT20_W { INT20_W::new(self) } #[doc = "Bit 21 - Interrupt 21"] #[inline(always)] #[must_use] - pub fn int21(&mut self) -> INT21_W<21> { + pub fn int21(&mut self) -> INT21_W { INT21_W::new(self) } #[doc = "Bit 22 - Interrupt 22"] #[inline(always)] #[must_use] - pub fn int22(&mut self) -> INT22_W<22> { + pub fn int22(&mut self) -> INT22_W { INT22_W::new(self) } #[doc = "Bit 23 - Interrupt 23"] #[inline(always)] #[must_use] - pub fn int23(&mut self) -> INT23_W<23> { + pub fn int23(&mut self) -> INT23_W { INT23_W::new(self) } #[doc = "Bit 24 - Interrupt 24"] #[inline(always)] #[must_use] - pub fn int24(&mut self) -> INT24_W<24> { + pub fn int24(&mut self) -> INT24_W { INT24_W::new(self) } #[doc = "Bit 25 - Interrupt 25"] #[inline(always)] #[must_use] - pub fn int25(&mut self) -> INT25_W<25> { + pub fn int25(&mut self) -> INT25_W { INT25_W::new(self) } #[doc = "Bit 26 - Interrupt 26"] #[inline(always)] #[must_use] - pub fn int26(&mut self) -> INT26_W<26> { + pub fn int26(&mut self) -> INT26_W { INT26_W::new(self) } #[doc = "Bit 27 - Interrupt 27"] #[inline(always)] #[must_use] - pub fn int27(&mut self) -> INT27_W<27> { + pub fn int27(&mut self) -> INT27_W { INT27_W::new(self) } #[doc = "Bit 28 - Interrupt 28"] #[inline(always)] #[must_use] - pub fn int28(&mut self) -> INT28_W<28> { + pub fn int28(&mut self) -> INT28_W { INT28_W::new(self) } #[doc = "Bit 29 - Interrupt 29"] #[inline(always)] #[must_use] - pub fn int29(&mut self) -> INT29_W<29> { + pub fn int29(&mut self) -> INT29_W { INT29_W::new(self) } #[doc = "Bit 30 - Interrupt 30"] #[inline(always)] #[must_use] - pub fn int30(&mut self) -> INT30_W<30> { + pub fn int30(&mut self) -> INT30_W { INT30_W::new(self) } #[doc = "Bit 31 - Interrupt 31"] #[inline(always)] #[must_use] - pub fn int31(&mut self) -> INT31_W<31> { + pub fn int31(&mut self) -> INT31_W { INT31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler0](index.html) module"] +#[doc = "Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISENABLER0_SPEC; impl crate::RegisterSpec for GICD_ISENABLER0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isenabler0::R](R) reader structure"] -impl crate::Readable for GICD_ISENABLER0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isenabler0::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isenabler0::R`](R) reader structure"] +impl crate::Readable for GICD_ISENABLER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isenabler0::W`](W) writer structure"] impl crate::Writable for GICD_ISENABLER0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler1.rs index 77e0e02..fca12dc 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler1.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler1.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ISENABLER1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISENABLER1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT32` reader - Interrupt 32"] -pub type INT32_R = crate::BitReader; +pub type INT32_R = crate::BitReader; #[doc = "Field `INT32` writer - Interrupt 32"] -pub type INT32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT32_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT33` reader - Interrupt 33"] -pub type INT33_R = crate::BitReader; +pub type INT33_R = crate::BitReader; #[doc = "Field `INT33` writer - Interrupt 33"] -pub type INT33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT33_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT34` reader - Interrupt 34"] -pub type INT34_R = crate::BitReader; +pub type INT34_R = crate::BitReader; #[doc = "Field `INT34` writer - Interrupt 34"] -pub type INT34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT34_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT35` reader - Interrupt 35"] -pub type INT35_R = crate::BitReader; +pub type INT35_R = crate::BitReader; #[doc = "Field `INT35` writer - Interrupt 35"] -pub type INT35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT35_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT36` reader - Interrupt 36"] -pub type INT36_R = crate::BitReader; +pub type INT36_R = crate::BitReader; #[doc = "Field `INT36` writer - Interrupt 36"] -pub type INT36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT36_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT37` reader - Interrupt 37"] -pub type INT37_R = crate::BitReader; +pub type INT37_R = crate::BitReader; #[doc = "Field `INT37` writer - Interrupt 37"] -pub type INT37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT37_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT38` reader - Interrupt 38"] -pub type INT38_R = crate::BitReader; +pub type INT38_R = crate::BitReader; #[doc = "Field `INT38` writer - Interrupt 38"] -pub type INT38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT38_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT39` reader - Interrupt 39"] -pub type INT39_R = crate::BitReader; +pub type INT39_R = crate::BitReader; #[doc = "Field `INT39` writer - Interrupt 39"] -pub type INT39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT39_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT40` reader - Interrupt 40"] -pub type INT40_R = crate::BitReader; +pub type INT40_R = crate::BitReader; #[doc = "Field `INT40` writer - Interrupt 40"] -pub type INT40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT40_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT41` reader - Interrupt 41"] -pub type INT41_R = crate::BitReader; +pub type INT41_R = crate::BitReader; #[doc = "Field `INT41` writer - Interrupt 41"] -pub type INT41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT41_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT42` reader - Interrupt 42"] -pub type INT42_R = crate::BitReader; +pub type INT42_R = crate::BitReader; #[doc = "Field `INT42` writer - Interrupt 42"] -pub type INT42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT42_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT43` reader - Interrupt 43"] -pub type INT43_R = crate::BitReader; +pub type INT43_R = crate::BitReader; #[doc = "Field `INT43` writer - Interrupt 43"] -pub type INT43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT43_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT44` reader - Interrupt 44"] -pub type INT44_R = crate::BitReader; +pub type INT44_R = crate::BitReader; #[doc = "Field `INT44` writer - Interrupt 44"] -pub type INT44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT44_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT45` reader - Interrupt 45"] -pub type INT45_R = crate::BitReader; +pub type INT45_R = crate::BitReader; #[doc = "Field `INT45` writer - Interrupt 45"] -pub type INT45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT45_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT46` reader - Interrupt 46"] -pub type INT46_R = crate::BitReader; +pub type INT46_R = crate::BitReader; #[doc = "Field `INT46` writer - Interrupt 46"] -pub type INT46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT46_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT47` reader - Interrupt 47"] -pub type INT47_R = crate::BitReader; +pub type INT47_R = crate::BitReader; #[doc = "Field `INT47` writer - Interrupt 47"] -pub type INT47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT47_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT48` reader - Interrupt 48"] -pub type INT48_R = crate::BitReader; +pub type INT48_R = crate::BitReader; #[doc = "Field `INT48` writer - Interrupt 48"] -pub type INT48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT48_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT49` reader - Interrupt 49"] -pub type INT49_R = crate::BitReader; +pub type INT49_R = crate::BitReader; #[doc = "Field `INT49` writer - Interrupt 49"] -pub type INT49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT49_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT50` reader - Interrupt 50"] -pub type INT50_R = crate::BitReader; +pub type INT50_R = crate::BitReader; #[doc = "Field `INT50` writer - Interrupt 50"] -pub type INT50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT50_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT51` reader - Interrupt 51"] -pub type INT51_R = crate::BitReader; +pub type INT51_R = crate::BitReader; #[doc = "Field `INT51` writer - Interrupt 51"] -pub type INT51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT51_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT52` reader - Interrupt 52"] -pub type INT52_R = crate::BitReader; +pub type INT52_R = crate::BitReader; #[doc = "Field `INT52` writer - Interrupt 52"] -pub type INT52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT52_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT53` reader - Interrupt 53"] -pub type INT53_R = crate::BitReader; +pub type INT53_R = crate::BitReader; #[doc = "Field `INT53` writer - Interrupt 53"] -pub type INT53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT53_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT54` reader - Interrupt 54"] -pub type INT54_R = crate::BitReader; +pub type INT54_R = crate::BitReader; #[doc = "Field `INT54` writer - Interrupt 54"] -pub type INT54_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT54_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT55` reader - Interrupt 55"] -pub type INT55_R = crate::BitReader; +pub type INT55_R = crate::BitReader; #[doc = "Field `INT55` writer - Interrupt 55"] -pub type INT55_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT55_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT56` reader - Interrupt 56"] -pub type INT56_R = crate::BitReader; +pub type INT56_R = crate::BitReader; #[doc = "Field `INT56` writer - Interrupt 56"] -pub type INT56_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT56_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT57` reader - Interrupt 57"] -pub type INT57_R = crate::BitReader; +pub type INT57_R = crate::BitReader; #[doc = "Field `INT57` writer - Interrupt 57"] -pub type INT57_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT57_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT58` reader - Interrupt 58"] -pub type INT58_R = crate::BitReader; +pub type INT58_R = crate::BitReader; #[doc = "Field `INT58` writer - Interrupt 58"] -pub type INT58_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT58_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT59` reader - Interrupt 59"] -pub type INT59_R = crate::BitReader; +pub type INT59_R = crate::BitReader; #[doc = "Field `INT59` writer - Interrupt 59"] -pub type INT59_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT59_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT60` reader - Interrupt 60"] -pub type INT60_R = crate::BitReader; +pub type INT60_R = crate::BitReader; #[doc = "Field `INT60` writer - Interrupt 60"] -pub type INT60_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT60_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT61` reader - Interrupt 61"] -pub type INT61_R = crate::BitReader; +pub type INT61_R = crate::BitReader; #[doc = "Field `INT61` writer - Interrupt 61"] -pub type INT61_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT61_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT62` reader - Interrupt 62"] -pub type INT62_R = crate::BitReader; +pub type INT62_R = crate::BitReader; #[doc = "Field `INT62` writer - Interrupt 62"] -pub type INT62_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT62_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT63` reader - Interrupt 63"] -pub type INT63_R = crate::BitReader; +pub type INT63_R = crate::BitReader; #[doc = "Field `INT63` writer - Interrupt 63"] -pub type INT63_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER1_SPEC, bool, O>; +pub type INT63_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT63_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISENABLER1") + .field("int32", &format_args!("{}", self.int32().bit())) + .field("int33", &format_args!("{}", self.int33().bit())) + .field("int34", &format_args!("{}", self.int34().bit())) + .field("int35", &format_args!("{}", self.int35().bit())) + .field("int36", &format_args!("{}", self.int36().bit())) + .field("int37", &format_args!("{}", self.int37().bit())) + .field("int38", &format_args!("{}", self.int38().bit())) + .field("int39", &format_args!("{}", self.int39().bit())) + .field("int40", &format_args!("{}", self.int40().bit())) + .field("int41", &format_args!("{}", self.int41().bit())) + .field("int42", &format_args!("{}", self.int42().bit())) + .field("int43", &format_args!("{}", self.int43().bit())) + .field("int44", &format_args!("{}", self.int44().bit())) + .field("int45", &format_args!("{}", self.int45().bit())) + .field("int46", &format_args!("{}", self.int46().bit())) + .field("int47", &format_args!("{}", self.int47().bit())) + .field("int48", &format_args!("{}", self.int48().bit())) + .field("int49", &format_args!("{}", self.int49().bit())) + .field("int50", &format_args!("{}", self.int50().bit())) + .field("int51", &format_args!("{}", self.int51().bit())) + .field("int52", &format_args!("{}", self.int52().bit())) + .field("int53", &format_args!("{}", self.int53().bit())) + .field("int54", &format_args!("{}", self.int54().bit())) + .field("int55", &format_args!("{}", self.int55().bit())) + .field("int56", &format_args!("{}", self.int56().bit())) + .field("int57", &format_args!("{}", self.int57().bit())) + .field("int58", &format_args!("{}", self.int58().bit())) + .field("int59", &format_args!("{}", self.int59().bit())) + .field("int60", &format_args!("{}", self.int60().bit())) + .field("int61", &format_args!("{}", self.int61().bit())) + .field("int62", &format_args!("{}", self.int62().bit())) + .field("int63", &format_args!("{}", self.int63().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] #[must_use] - pub fn int32(&mut self) -> INT32_W<0> { + pub fn int32(&mut self) -> INT32_W { INT32_W::new(self) } #[doc = "Bit 1 - Interrupt 33"] #[inline(always)] #[must_use] - pub fn int33(&mut self) -> INT33_W<1> { + pub fn int33(&mut self) -> INT33_W { INT33_W::new(self) } #[doc = "Bit 2 - Interrupt 34"] #[inline(always)] #[must_use] - pub fn int34(&mut self) -> INT34_W<2> { + pub fn int34(&mut self) -> INT34_W { INT34_W::new(self) } #[doc = "Bit 3 - Interrupt 35"] #[inline(always)] #[must_use] - pub fn int35(&mut self) -> INT35_W<3> { + pub fn int35(&mut self) -> INT35_W { INT35_W::new(self) } #[doc = "Bit 4 - Interrupt 36"] #[inline(always)] #[must_use] - pub fn int36(&mut self) -> INT36_W<4> { + pub fn int36(&mut self) -> INT36_W { INT36_W::new(self) } #[doc = "Bit 5 - Interrupt 37"] #[inline(always)] #[must_use] - pub fn int37(&mut self) -> INT37_W<5> { + pub fn int37(&mut self) -> INT37_W { INT37_W::new(self) } #[doc = "Bit 6 - Interrupt 38"] #[inline(always)] #[must_use] - pub fn int38(&mut self) -> INT38_W<6> { + pub fn int38(&mut self) -> INT38_W { INT38_W::new(self) } #[doc = "Bit 7 - Interrupt 39"] #[inline(always)] #[must_use] - pub fn int39(&mut self) -> INT39_W<7> { + pub fn int39(&mut self) -> INT39_W { INT39_W::new(self) } #[doc = "Bit 8 - Interrupt 40"] #[inline(always)] #[must_use] - pub fn int40(&mut self) -> INT40_W<8> { + pub fn int40(&mut self) -> INT40_W { INT40_W::new(self) } #[doc = "Bit 9 - Interrupt 41"] #[inline(always)] #[must_use] - pub fn int41(&mut self) -> INT41_W<9> { + pub fn int41(&mut self) -> INT41_W { INT41_W::new(self) } #[doc = "Bit 10 - Interrupt 42"] #[inline(always)] #[must_use] - pub fn int42(&mut self) -> INT42_W<10> { + pub fn int42(&mut self) -> INT42_W { INT42_W::new(self) } #[doc = "Bit 11 - Interrupt 43"] #[inline(always)] #[must_use] - pub fn int43(&mut self) -> INT43_W<11> { + pub fn int43(&mut self) -> INT43_W { INT43_W::new(self) } #[doc = "Bit 12 - Interrupt 44"] #[inline(always)] #[must_use] - pub fn int44(&mut self) -> INT44_W<12> { + pub fn int44(&mut self) -> INT44_W { INT44_W::new(self) } #[doc = "Bit 13 - Interrupt 45"] #[inline(always)] #[must_use] - pub fn int45(&mut self) -> INT45_W<13> { + pub fn int45(&mut self) -> INT45_W { INT45_W::new(self) } #[doc = "Bit 14 - Interrupt 46"] #[inline(always)] #[must_use] - pub fn int46(&mut self) -> INT46_W<14> { + pub fn int46(&mut self) -> INT46_W { INT46_W::new(self) } #[doc = "Bit 15 - Interrupt 47"] #[inline(always)] #[must_use] - pub fn int47(&mut self) -> INT47_W<15> { + pub fn int47(&mut self) -> INT47_W { INT47_W::new(self) } #[doc = "Bit 16 - Interrupt 48"] #[inline(always)] #[must_use] - pub fn int48(&mut self) -> INT48_W<16> { + pub fn int48(&mut self) -> INT48_W { INT48_W::new(self) } #[doc = "Bit 17 - Interrupt 49"] #[inline(always)] #[must_use] - pub fn int49(&mut self) -> INT49_W<17> { + pub fn int49(&mut self) -> INT49_W { INT49_W::new(self) } #[doc = "Bit 18 - Interrupt 50"] #[inline(always)] #[must_use] - pub fn int50(&mut self) -> INT50_W<18> { + pub fn int50(&mut self) -> INT50_W { INT50_W::new(self) } #[doc = "Bit 19 - Interrupt 51"] #[inline(always)] #[must_use] - pub fn int51(&mut self) -> INT51_W<19> { + pub fn int51(&mut self) -> INT51_W { INT51_W::new(self) } #[doc = "Bit 20 - Interrupt 52"] #[inline(always)] #[must_use] - pub fn int52(&mut self) -> INT52_W<20> { + pub fn int52(&mut self) -> INT52_W { INT52_W::new(self) } #[doc = "Bit 21 - Interrupt 53"] #[inline(always)] #[must_use] - pub fn int53(&mut self) -> INT53_W<21> { + pub fn int53(&mut self) -> INT53_W { INT53_W::new(self) } #[doc = "Bit 22 - Interrupt 54"] #[inline(always)] #[must_use] - pub fn int54(&mut self) -> INT54_W<22> { + pub fn int54(&mut self) -> INT54_W { INT54_W::new(self) } #[doc = "Bit 23 - Interrupt 55"] #[inline(always)] #[must_use] - pub fn int55(&mut self) -> INT55_W<23> { + pub fn int55(&mut self) -> INT55_W { INT55_W::new(self) } #[doc = "Bit 24 - Interrupt 56"] #[inline(always)] #[must_use] - pub fn int56(&mut self) -> INT56_W<24> { + pub fn int56(&mut self) -> INT56_W { INT56_W::new(self) } #[doc = "Bit 25 - Interrupt 57"] #[inline(always)] #[must_use] - pub fn int57(&mut self) -> INT57_W<25> { + pub fn int57(&mut self) -> INT57_W { INT57_W::new(self) } #[doc = "Bit 26 - Interrupt 58"] #[inline(always)] #[must_use] - pub fn int58(&mut self) -> INT58_W<26> { + pub fn int58(&mut self) -> INT58_W { INT58_W::new(self) } #[doc = "Bit 27 - Interrupt 59"] #[inline(always)] #[must_use] - pub fn int59(&mut self) -> INT59_W<27> { + pub fn int59(&mut self) -> INT59_W { INT59_W::new(self) } #[doc = "Bit 28 - Interrupt 60"] #[inline(always)] #[must_use] - pub fn int60(&mut self) -> INT60_W<28> { + pub fn int60(&mut self) -> INT60_W { INT60_W::new(self) } #[doc = "Bit 29 - Interrupt 61"] #[inline(always)] #[must_use] - pub fn int61(&mut self) -> INT61_W<29> { + pub fn int61(&mut self) -> INT61_W { INT61_W::new(self) } #[doc = "Bit 30 - Interrupt 62"] #[inline(always)] #[must_use] - pub fn int62(&mut self) -> INT62_W<30> { + pub fn int62(&mut self) -> INT62_W { INT62_W::new(self) } #[doc = "Bit 31 - Interrupt 63"] #[inline(always)] #[must_use] - pub fn int63(&mut self) -> INT63_W<31> { + pub fn int63(&mut self) -> INT63_W { INT63_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler1](index.html) module"] +#[doc = "Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISENABLER1_SPEC; impl crate::RegisterSpec for GICD_ISENABLER1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isenabler1::R](R) reader structure"] -impl crate::Readable for GICD_ISENABLER1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isenabler1::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isenabler1::R`](R) reader structure"] +impl crate::Readable for GICD_ISENABLER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isenabler1::W`](W) writer structure"] impl crate::Writable for GICD_ISENABLER1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler2.rs index 154b7f7..913251f 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler2.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler2.rs @@ -1,171 +1,135 @@ #[doc = "Register `GICD_ISENABLER2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISENABLER2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI0` reader - Software interrupt 0"] -pub type SWI0_R = crate::BitReader; +pub type SWI0_R = crate::BitReader; #[doc = "Field `SWI0` writer - Software interrupt 0"] -pub type SWI0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type SWI0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI1` reader - Software interrupt 1"] -pub type SWI1_R = crate::BitReader; +pub type SWI1_R = crate::BitReader; #[doc = "Field `SWI1` writer - Software interrupt 1"] -pub type SWI1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type SWI1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI2` reader - Software interrupt 2"] -pub type SWI2_R = crate::BitReader; +pub type SWI2_R = crate::BitReader; #[doc = "Field `SWI2` writer - Software interrupt 2"] -pub type SWI2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type SWI2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI3` reader - Software interrupt 3"] -pub type SWI3_R = crate::BitReader; +pub type SWI3_R = crate::BitReader; #[doc = "Field `SWI3` writer - Software interrupt 3"] -pub type SWI3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type SWI3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI4` reader - Software interrupt 4"] -pub type SWI4_R = crate::BitReader; +pub type SWI4_R = crate::BitReader; #[doc = "Field `SWI4` writer - Software interrupt 4"] -pub type SWI4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type SWI4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI5` reader - Software interrupt 5"] -pub type SWI5_R = crate::BitReader; +pub type SWI5_R = crate::BitReader; #[doc = "Field `SWI5` writer - Software interrupt 5"] -pub type SWI5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type SWI5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI6` reader - Software interrupt 6"] -pub type SWI6_R = crate::BitReader; +pub type SWI6_R = crate::BitReader; #[doc = "Field `SWI6` writer - Software interrupt 6"] -pub type SWI6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type SWI6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI7` reader - Software interrupt 7"] -pub type SWI7_R = crate::BitReader; +pub type SWI7_R = crate::BitReader; #[doc = "Field `SWI7` writer - Software interrupt 7"] -pub type SWI7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type SWI7_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT80` reader - Interrupt 80"] -pub type INT80_R = crate::BitReader; +pub type INT80_R = crate::BitReader; #[doc = "Field `INT80` writer - Interrupt 80"] -pub type INT80_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT80_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT81` reader - Interrupt 81"] -pub type INT81_R = crate::BitReader; +pub type INT81_R = crate::BitReader; #[doc = "Field `INT81` writer - Interrupt 81"] -pub type INT81_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT81_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT82` reader - Interrupt 82"] -pub type INT82_R = crate::BitReader; +pub type INT82_R = crate::BitReader; #[doc = "Field `INT82` writer - Interrupt 82"] -pub type INT82_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT82_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT83` reader - Interrupt 83"] -pub type INT83_R = crate::BitReader; +pub type INT83_R = crate::BitReader; #[doc = "Field `INT83` writer - Interrupt 83"] -pub type INT83_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT83_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT84` reader - Interrupt 84"] -pub type INT84_R = crate::BitReader; +pub type INT84_R = crate::BitReader; #[doc = "Field `INT84` writer - Interrupt 84"] -pub type INT84_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT84_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT85` reader - Interrupt 85"] -pub type INT85_R = crate::BitReader; +pub type INT85_R = crate::BitReader; #[doc = "Field `INT85` writer - Interrupt 85"] -pub type INT85_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT85_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT86` reader - Interrupt 86"] -pub type INT86_R = crate::BitReader; +pub type INT86_R = crate::BitReader; #[doc = "Field `INT86` writer - Interrupt 86"] -pub type INT86_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT86_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT87` reader - Interrupt 87"] -pub type INT87_R = crate::BitReader; +pub type INT87_R = crate::BitReader; #[doc = "Field `INT87` writer - Interrupt 87"] -pub type INT87_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT87_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT88` reader - Interrupt 88"] -pub type INT88_R = crate::BitReader; +pub type INT88_R = crate::BitReader; #[doc = "Field `INT88` writer - Interrupt 88"] -pub type INT88_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT88_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT89` reader - Interrupt 89"] -pub type INT89_R = crate::BitReader; +pub type INT89_R = crate::BitReader; #[doc = "Field `INT89` writer - Interrupt 89"] -pub type INT89_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT89_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT90` reader - Interrupt 90"] -pub type INT90_R = crate::BitReader; +pub type INT90_R = crate::BitReader; #[doc = "Field `INT90` writer - Interrupt 90"] -pub type INT90_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT90_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT91` reader - Interrupt 91"] -pub type INT91_R = crate::BitReader; +pub type INT91_R = crate::BitReader; #[doc = "Field `INT91` writer - Interrupt 91"] -pub type INT91_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT91_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT92` reader - Interrupt 92"] -pub type INT92_R = crate::BitReader; +pub type INT92_R = crate::BitReader; #[doc = "Field `INT92` writer - Interrupt 92"] -pub type INT92_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT92_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT93` reader - Interrupt 93"] -pub type INT93_R = crate::BitReader; +pub type INT93_R = crate::BitReader; #[doc = "Field `INT93` writer - Interrupt 93"] -pub type INT93_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT93_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT94` reader - Interrupt 94"] -pub type INT94_R = crate::BitReader; +pub type INT94_R = crate::BitReader; #[doc = "Field `INT94` writer - Interrupt 94"] -pub type INT94_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT94_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT95` reader - Interrupt 95"] -pub type INT95_R = crate::BitReader; +pub type INT95_R = crate::BitReader; #[doc = "Field `INT95` writer - Interrupt 95"] -pub type INT95_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER2_SPEC, bool, O>; +pub type INT95_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -328,218 +292,268 @@ impl R { INT95_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISENABLER2") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .field("swi0", &format_args!("{}", self.swi0().bit())) + .field("swi1", &format_args!("{}", self.swi1().bit())) + .field("swi2", &format_args!("{}", self.swi2().bit())) + .field("swi3", &format_args!("{}", self.swi3().bit())) + .field("swi4", &format_args!("{}", self.swi4().bit())) + .field("swi5", &format_args!("{}", self.swi5().bit())) + .field("swi6", &format_args!("{}", self.swi6().bit())) + .field("swi7", &format_args!("{}", self.swi7().bit())) + .field("int80", &format_args!("{}", self.int80().bit())) + .field("int81", &format_args!("{}", self.int81().bit())) + .field("int82", &format_args!("{}", self.int82().bit())) + .field("int83", &format_args!("{}", self.int83().bit())) + .field("int84", &format_args!("{}", self.int84().bit())) + .field("int85", &format_args!("{}", self.int85().bit())) + .field("int86", &format_args!("{}", self.int86().bit())) + .field("int87", &format_args!("{}", self.int87().bit())) + .field("int88", &format_args!("{}", self.int88().bit())) + .field("int89", &format_args!("{}", self.int89().bit())) + .field("int90", &format_args!("{}", self.int90().bit())) + .field("int91", &format_args!("{}", self.int91().bit())) + .field("int92", &format_args!("{}", self.int92().bit())) + .field("int93", &format_args!("{}", self.int93().bit())) + .field("int94", &format_args!("{}", self.int94().bit())) + .field("int95", &format_args!("{}", self.int95().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } #[doc = "Bit 8 - Software interrupt 0"] #[inline(always)] #[must_use] - pub fn swi0(&mut self) -> SWI0_W<8> { + pub fn swi0(&mut self) -> SWI0_W { SWI0_W::new(self) } #[doc = "Bit 9 - Software interrupt 1"] #[inline(always)] #[must_use] - pub fn swi1(&mut self) -> SWI1_W<9> { + pub fn swi1(&mut self) -> SWI1_W { SWI1_W::new(self) } #[doc = "Bit 10 - Software interrupt 2"] #[inline(always)] #[must_use] - pub fn swi2(&mut self) -> SWI2_W<10> { + pub fn swi2(&mut self) -> SWI2_W { SWI2_W::new(self) } #[doc = "Bit 11 - Software interrupt 3"] #[inline(always)] #[must_use] - pub fn swi3(&mut self) -> SWI3_W<11> { + pub fn swi3(&mut self) -> SWI3_W { SWI3_W::new(self) } #[doc = "Bit 12 - Software interrupt 4"] #[inline(always)] #[must_use] - pub fn swi4(&mut self) -> SWI4_W<12> { + pub fn swi4(&mut self) -> SWI4_W { SWI4_W::new(self) } #[doc = "Bit 13 - Software interrupt 5"] #[inline(always)] #[must_use] - pub fn swi5(&mut self) -> SWI5_W<13> { + pub fn swi5(&mut self) -> SWI5_W { SWI5_W::new(self) } #[doc = "Bit 14 - Software interrupt 6"] #[inline(always)] #[must_use] - pub fn swi6(&mut self) -> SWI6_W<14> { + pub fn swi6(&mut self) -> SWI6_W { SWI6_W::new(self) } #[doc = "Bit 15 - Software interrupt 7"] #[inline(always)] #[must_use] - pub fn swi7(&mut self) -> SWI7_W<15> { + pub fn swi7(&mut self) -> SWI7_W { SWI7_W::new(self) } #[doc = "Bit 16 - Interrupt 80"] #[inline(always)] #[must_use] - pub fn int80(&mut self) -> INT80_W<16> { + pub fn int80(&mut self) -> INT80_W { INT80_W::new(self) } #[doc = "Bit 17 - Interrupt 81"] #[inline(always)] #[must_use] - pub fn int81(&mut self) -> INT81_W<17> { + pub fn int81(&mut self) -> INT81_W { INT81_W::new(self) } #[doc = "Bit 18 - Interrupt 82"] #[inline(always)] #[must_use] - pub fn int82(&mut self) -> INT82_W<18> { + pub fn int82(&mut self) -> INT82_W { INT82_W::new(self) } #[doc = "Bit 19 - Interrupt 83"] #[inline(always)] #[must_use] - pub fn int83(&mut self) -> INT83_W<19> { + pub fn int83(&mut self) -> INT83_W { INT83_W::new(self) } #[doc = "Bit 20 - Interrupt 84"] #[inline(always)] #[must_use] - pub fn int84(&mut self) -> INT84_W<20> { + pub fn int84(&mut self) -> INT84_W { INT84_W::new(self) } #[doc = "Bit 21 - Interrupt 85"] #[inline(always)] #[must_use] - pub fn int85(&mut self) -> INT85_W<21> { + pub fn int85(&mut self) -> INT85_W { INT85_W::new(self) } #[doc = "Bit 22 - Interrupt 86"] #[inline(always)] #[must_use] - pub fn int86(&mut self) -> INT86_W<22> { + pub fn int86(&mut self) -> INT86_W { INT86_W::new(self) } #[doc = "Bit 23 - Interrupt 87"] #[inline(always)] #[must_use] - pub fn int87(&mut self) -> INT87_W<23> { + pub fn int87(&mut self) -> INT87_W { INT87_W::new(self) } #[doc = "Bit 24 - Interrupt 88"] #[inline(always)] #[must_use] - pub fn int88(&mut self) -> INT88_W<24> { + pub fn int88(&mut self) -> INT88_W { INT88_W::new(self) } #[doc = "Bit 25 - Interrupt 89"] #[inline(always)] #[must_use] - pub fn int89(&mut self) -> INT89_W<25> { + pub fn int89(&mut self) -> INT89_W { INT89_W::new(self) } #[doc = "Bit 26 - Interrupt 90"] #[inline(always)] #[must_use] - pub fn int90(&mut self) -> INT90_W<26> { + pub fn int90(&mut self) -> INT90_W { INT90_W::new(self) } #[doc = "Bit 27 - Interrupt 91"] #[inline(always)] #[must_use] - pub fn int91(&mut self) -> INT91_W<27> { + pub fn int91(&mut self) -> INT91_W { INT91_W::new(self) } #[doc = "Bit 28 - Interrupt 92"] #[inline(always)] #[must_use] - pub fn int92(&mut self) -> INT92_W<28> { + pub fn int92(&mut self) -> INT92_W { INT92_W::new(self) } #[doc = "Bit 29 - Interrupt 93"] #[inline(always)] #[must_use] - pub fn int93(&mut self) -> INT93_W<29> { + pub fn int93(&mut self) -> INT93_W { INT93_W::new(self) } #[doc = "Bit 30 - Interrupt 94"] #[inline(always)] #[must_use] - pub fn int94(&mut self) -> INT94_W<30> { + pub fn int94(&mut self) -> INT94_W { INT94_W::new(self) } #[doc = "Bit 31 - Interrupt 95"] #[inline(always)] #[must_use] - pub fn int95(&mut self) -> INT95_W<31> { + pub fn int95(&mut self) -> INT95_W { INT95_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler2](index.html) module"] +#[doc = "Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISENABLER2_SPEC; impl crate::RegisterSpec for GICD_ISENABLER2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isenabler2::R](R) reader structure"] -impl crate::Readable for GICD_ISENABLER2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isenabler2::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isenabler2::R`](R) reader structure"] +impl crate::Readable for GICD_ISENABLER2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isenabler2::W`](W) writer structure"] impl crate::Writable for GICD_ISENABLER2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler3.rs index a0f74d5..9adc818 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler3.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler3.rs @@ -1,171 +1,135 @@ #[doc = "Register `GICD_ISENABLER3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISENABLER3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER3_SPEC, bool, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -328,218 +292,274 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISENABLER3") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bit 1 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<1> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bit 2 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<2> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bit 3 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<3> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } #[doc = "Bit 4 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<4> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bit 5 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<5> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bit 6 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<6> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bit 7 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<7> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } #[doc = "Bit 8 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<8> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bit 9 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<9> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 10 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<10> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bit 11 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } #[doc = "Bit 12 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bit 13 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bit 14 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bit 15 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } #[doc = "Bit 16 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<16> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bit 17 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<17> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 18 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<18> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 19 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<19> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 20 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<20> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 21 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<21> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 22 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<22> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 23 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } #[doc = "Bit 24 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bit 25 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<25> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bit 26 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<26> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bit 27 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<27> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } #[doc = "Bit 28 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<28> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<29> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bit 30 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<30> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bit 31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<31> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler3](index.html) module"] +#[doc = "Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISENABLER3_SPEC; impl crate::RegisterSpec for GICD_ISENABLER3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isenabler3::R](R) reader structure"] -impl crate::Readable for GICD_ISENABLER3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isenabler3::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isenabler3::R`](R) reader structure"] +impl crate::Readable for GICD_ISENABLER3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isenabler3::W`](W) writer structure"] impl crate::Writable for GICD_ISENABLER3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler4.rs index 8df3d2a..d943476 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler4.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler4.rs @@ -1,173 +1,135 @@ #[doc = "Register `GICD_ISENABLER4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISENABLER4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type UART_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISENABLER4_SPEC, bool, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -330,218 +292,280 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISENABLER4") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bit 1 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<1> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bit 2 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<2> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bit 3 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<3> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } #[doc = "Bit 4 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<4> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bit 5 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bit 6 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bit 7 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } #[doc = "Bit 8 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bit 9 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bit 10 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bit 11 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } #[doc = "Bit 12 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<12> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bit 13 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bit 15 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<15> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } #[doc = "Bit 16 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<16> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bit 17 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bit 18 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bit 19 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } #[doc = "Bit 20 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bit 21 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<21> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bit 22 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<22> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bit 23 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } #[doc = "Bit 24 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<24> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bit 25 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<25> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bit 26 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bit 27 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<27> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } #[doc = "Bit 28 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<28> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bit 29 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<29> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bit 30 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<30> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bit 31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler4](index.html) module"] +#[doc = "Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISENABLER4_SPEC; impl crate::RegisterSpec for GICD_ISENABLER4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isenabler4::R](R) reader structure"] -impl crate::Readable for GICD_ISENABLER4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isenabler4::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isenabler4::R`](R) reader structure"] +impl crate::Readable for GICD_ISENABLER4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isenabler4::W`](W) writer structure"] impl crate::Writable for GICD_ISENABLER4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler5.rs index 70f96b0..f149b4a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler5.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler5.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ISENABLER5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISENABLER5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT160` reader - Interrupt 160"] -pub type INT160_R = crate::BitReader; +pub type INT160_R = crate::BitReader; #[doc = "Field `INT160` writer - Interrupt 160"] -pub type INT160_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT160_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT161` reader - Interrupt 161"] -pub type INT161_R = crate::BitReader; +pub type INT161_R = crate::BitReader; #[doc = "Field `INT161` writer - Interrupt 161"] -pub type INT161_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT161_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT162` reader - Interrupt 162"] -pub type INT162_R = crate::BitReader; +pub type INT162_R = crate::BitReader; #[doc = "Field `INT162` writer - Interrupt 162"] -pub type INT162_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT162_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT163` reader - Interrupt 163"] -pub type INT163_R = crate::BitReader; +pub type INT163_R = crate::BitReader; #[doc = "Field `INT163` writer - Interrupt 163"] -pub type INT163_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT163_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT164` reader - Interrupt 164"] -pub type INT164_R = crate::BitReader; +pub type INT164_R = crate::BitReader; #[doc = "Field `INT164` writer - Interrupt 164"] -pub type INT164_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT164_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT165` reader - Interrupt 165"] -pub type INT165_R = crate::BitReader; +pub type INT165_R = crate::BitReader; #[doc = "Field `INT165` writer - Interrupt 165"] -pub type INT165_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT165_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT166` reader - Interrupt 166"] -pub type INT166_R = crate::BitReader; +pub type INT166_R = crate::BitReader; #[doc = "Field `INT166` writer - Interrupt 166"] -pub type INT166_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT166_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT167` reader - Interrupt 167"] -pub type INT167_R = crate::BitReader; +pub type INT167_R = crate::BitReader; #[doc = "Field `INT167` writer - Interrupt 167"] -pub type INT167_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT167_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT168` reader - Interrupt 168"] -pub type INT168_R = crate::BitReader; +pub type INT168_R = crate::BitReader; #[doc = "Field `INT168` writer - Interrupt 168"] -pub type INT168_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT168_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT169` reader - Interrupt 169"] -pub type INT169_R = crate::BitReader; +pub type INT169_R = crate::BitReader; #[doc = "Field `INT169` writer - Interrupt 169"] -pub type INT169_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT169_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT170` reader - Interrupt 170"] -pub type INT170_R = crate::BitReader; +pub type INT170_R = crate::BitReader; #[doc = "Field `INT170` writer - Interrupt 170"] -pub type INT170_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT170_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT171` reader - Interrupt 171"] -pub type INT171_R = crate::BitReader; +pub type INT171_R = crate::BitReader; #[doc = "Field `INT171` writer - Interrupt 171"] -pub type INT171_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT171_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT172` reader - Interrupt 172"] -pub type INT172_R = crate::BitReader; +pub type INT172_R = crate::BitReader; #[doc = "Field `INT172` writer - Interrupt 172"] -pub type INT172_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT172_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT173` reader - Interrupt 173"] -pub type INT173_R = crate::BitReader; +pub type INT173_R = crate::BitReader; #[doc = "Field `INT173` writer - Interrupt 173"] -pub type INT173_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT173_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT174` reader - Interrupt 174"] -pub type INT174_R = crate::BitReader; +pub type INT174_R = crate::BitReader; #[doc = "Field `INT174` writer - Interrupt 174"] -pub type INT174_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT174_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT175` reader - Interrupt 175"] -pub type INT175_R = crate::BitReader; +pub type INT175_R = crate::BitReader; #[doc = "Field `INT175` writer - Interrupt 175"] -pub type INT175_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT175_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT176` reader - Interrupt 176"] -pub type INT176_R = crate::BitReader; +pub type INT176_R = crate::BitReader; #[doc = "Field `INT176` writer - Interrupt 176"] -pub type INT176_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT176_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT177` reader - Interrupt 177"] -pub type INT177_R = crate::BitReader; +pub type INT177_R = crate::BitReader; #[doc = "Field `INT177` writer - Interrupt 177"] -pub type INT177_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT177_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT178` reader - Interrupt 178"] -pub type INT178_R = crate::BitReader; +pub type INT178_R = crate::BitReader; #[doc = "Field `INT178` writer - Interrupt 178"] -pub type INT178_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT178_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT179` reader - Interrupt 179"] -pub type INT179_R = crate::BitReader; +pub type INT179_R = crate::BitReader; #[doc = "Field `INT179` writer - Interrupt 179"] -pub type INT179_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT179_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT180` reader - Interrupt 180"] -pub type INT180_R = crate::BitReader; +pub type INT180_R = crate::BitReader; #[doc = "Field `INT180` writer - Interrupt 180"] -pub type INT180_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT180_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT181` reader - Interrupt 181"] -pub type INT181_R = crate::BitReader; +pub type INT181_R = crate::BitReader; #[doc = "Field `INT181` writer - Interrupt 181"] -pub type INT181_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT181_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT182` reader - Interrupt 182"] -pub type INT182_R = crate::BitReader; +pub type INT182_R = crate::BitReader; #[doc = "Field `INT182` writer - Interrupt 182"] -pub type INT182_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT182_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT183` reader - Interrupt 183"] -pub type INT183_R = crate::BitReader; +pub type INT183_R = crate::BitReader; #[doc = "Field `INT183` writer - Interrupt 183"] -pub type INT183_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT183_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT184` reader - Interrupt 184"] -pub type INT184_R = crate::BitReader; +pub type INT184_R = crate::BitReader; #[doc = "Field `INT184` writer - Interrupt 184"] -pub type INT184_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT184_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT185` reader - Interrupt 185"] -pub type INT185_R = crate::BitReader; +pub type INT185_R = crate::BitReader; #[doc = "Field `INT185` writer - Interrupt 185"] -pub type INT185_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT185_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT186` reader - Interrupt 186"] -pub type INT186_R = crate::BitReader; +pub type INT186_R = crate::BitReader; #[doc = "Field `INT186` writer - Interrupt 186"] -pub type INT186_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT186_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT187` reader - Interrupt 187"] -pub type INT187_R = crate::BitReader; +pub type INT187_R = crate::BitReader; #[doc = "Field `INT187` writer - Interrupt 187"] -pub type INT187_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT187_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT188` reader - Interrupt 188"] -pub type INT188_R = crate::BitReader; +pub type INT188_R = crate::BitReader; #[doc = "Field `INT188` writer - Interrupt 188"] -pub type INT188_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT188_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT189` reader - Interrupt 189"] -pub type INT189_R = crate::BitReader; +pub type INT189_R = crate::BitReader; #[doc = "Field `INT189` writer - Interrupt 189"] -pub type INT189_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT189_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT190` reader - Interrupt 190"] -pub type INT190_R = crate::BitReader; +pub type INT190_R = crate::BitReader; #[doc = "Field `INT190` writer - Interrupt 190"] -pub type INT190_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT190_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT191` reader - Interrupt 191"] -pub type INT191_R = crate::BitReader; +pub type INT191_R = crate::BitReader; #[doc = "Field `INT191` writer - Interrupt 191"] -pub type INT191_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER5_SPEC, bool, O>; +pub type INT191_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT191_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISENABLER5") + .field("int160", &format_args!("{}", self.int160().bit())) + .field("int161", &format_args!("{}", self.int161().bit())) + .field("int162", &format_args!("{}", self.int162().bit())) + .field("int163", &format_args!("{}", self.int163().bit())) + .field("int164", &format_args!("{}", self.int164().bit())) + .field("int165", &format_args!("{}", self.int165().bit())) + .field("int166", &format_args!("{}", self.int166().bit())) + .field("int167", &format_args!("{}", self.int167().bit())) + .field("int168", &format_args!("{}", self.int168().bit())) + .field("int169", &format_args!("{}", self.int169().bit())) + .field("int170", &format_args!("{}", self.int170().bit())) + .field("int171", &format_args!("{}", self.int171().bit())) + .field("int172", &format_args!("{}", self.int172().bit())) + .field("int173", &format_args!("{}", self.int173().bit())) + .field("int174", &format_args!("{}", self.int174().bit())) + .field("int175", &format_args!("{}", self.int175().bit())) + .field("int176", &format_args!("{}", self.int176().bit())) + .field("int177", &format_args!("{}", self.int177().bit())) + .field("int178", &format_args!("{}", self.int178().bit())) + .field("int179", &format_args!("{}", self.int179().bit())) + .field("int180", &format_args!("{}", self.int180().bit())) + .field("int181", &format_args!("{}", self.int181().bit())) + .field("int182", &format_args!("{}", self.int182().bit())) + .field("int183", &format_args!("{}", self.int183().bit())) + .field("int184", &format_args!("{}", self.int184().bit())) + .field("int185", &format_args!("{}", self.int185().bit())) + .field("int186", &format_args!("{}", self.int186().bit())) + .field("int187", &format_args!("{}", self.int187().bit())) + .field("int188", &format_args!("{}", self.int188().bit())) + .field("int189", &format_args!("{}", self.int189().bit())) + .field("int190", &format_args!("{}", self.int190().bit())) + .field("int191", &format_args!("{}", self.int191().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] #[must_use] - pub fn int160(&mut self) -> INT160_W<0> { + pub fn int160(&mut self) -> INT160_W { INT160_W::new(self) } #[doc = "Bit 1 - Interrupt 161"] #[inline(always)] #[must_use] - pub fn int161(&mut self) -> INT161_W<1> { + pub fn int161(&mut self) -> INT161_W { INT161_W::new(self) } #[doc = "Bit 2 - Interrupt 162"] #[inline(always)] #[must_use] - pub fn int162(&mut self) -> INT162_W<2> { + pub fn int162(&mut self) -> INT162_W { INT162_W::new(self) } #[doc = "Bit 3 - Interrupt 163"] #[inline(always)] #[must_use] - pub fn int163(&mut self) -> INT163_W<3> { + pub fn int163(&mut self) -> INT163_W { INT163_W::new(self) } #[doc = "Bit 4 - Interrupt 164"] #[inline(always)] #[must_use] - pub fn int164(&mut self) -> INT164_W<4> { + pub fn int164(&mut self) -> INT164_W { INT164_W::new(self) } #[doc = "Bit 5 - Interrupt 165"] #[inline(always)] #[must_use] - pub fn int165(&mut self) -> INT165_W<5> { + pub fn int165(&mut self) -> INT165_W { INT165_W::new(self) } #[doc = "Bit 6 - Interrupt 166"] #[inline(always)] #[must_use] - pub fn int166(&mut self) -> INT166_W<6> { + pub fn int166(&mut self) -> INT166_W { INT166_W::new(self) } #[doc = "Bit 7 - Interrupt 167"] #[inline(always)] #[must_use] - pub fn int167(&mut self) -> INT167_W<7> { + pub fn int167(&mut self) -> INT167_W { INT167_W::new(self) } #[doc = "Bit 8 - Interrupt 168"] #[inline(always)] #[must_use] - pub fn int168(&mut self) -> INT168_W<8> { + pub fn int168(&mut self) -> INT168_W { INT168_W::new(self) } #[doc = "Bit 9 - Interrupt 169"] #[inline(always)] #[must_use] - pub fn int169(&mut self) -> INT169_W<9> { + pub fn int169(&mut self) -> INT169_W { INT169_W::new(self) } #[doc = "Bit 10 - Interrupt 170"] #[inline(always)] #[must_use] - pub fn int170(&mut self) -> INT170_W<10> { + pub fn int170(&mut self) -> INT170_W { INT170_W::new(self) } #[doc = "Bit 11 - Interrupt 171"] #[inline(always)] #[must_use] - pub fn int171(&mut self) -> INT171_W<11> { + pub fn int171(&mut self) -> INT171_W { INT171_W::new(self) } #[doc = "Bit 12 - Interrupt 172"] #[inline(always)] #[must_use] - pub fn int172(&mut self) -> INT172_W<12> { + pub fn int172(&mut self) -> INT172_W { INT172_W::new(self) } #[doc = "Bit 13 - Interrupt 173"] #[inline(always)] #[must_use] - pub fn int173(&mut self) -> INT173_W<13> { + pub fn int173(&mut self) -> INT173_W { INT173_W::new(self) } #[doc = "Bit 14 - Interrupt 174"] #[inline(always)] #[must_use] - pub fn int174(&mut self) -> INT174_W<14> { + pub fn int174(&mut self) -> INT174_W { INT174_W::new(self) } #[doc = "Bit 15 - Interrupt 175"] #[inline(always)] #[must_use] - pub fn int175(&mut self) -> INT175_W<15> { + pub fn int175(&mut self) -> INT175_W { INT175_W::new(self) } #[doc = "Bit 16 - Interrupt 176"] #[inline(always)] #[must_use] - pub fn int176(&mut self) -> INT176_W<16> { + pub fn int176(&mut self) -> INT176_W { INT176_W::new(self) } #[doc = "Bit 17 - Interrupt 177"] #[inline(always)] #[must_use] - pub fn int177(&mut self) -> INT177_W<17> { + pub fn int177(&mut self) -> INT177_W { INT177_W::new(self) } #[doc = "Bit 18 - Interrupt 178"] #[inline(always)] #[must_use] - pub fn int178(&mut self) -> INT178_W<18> { + pub fn int178(&mut self) -> INT178_W { INT178_W::new(self) } #[doc = "Bit 19 - Interrupt 179"] #[inline(always)] #[must_use] - pub fn int179(&mut self) -> INT179_W<19> { + pub fn int179(&mut self) -> INT179_W { INT179_W::new(self) } #[doc = "Bit 20 - Interrupt 180"] #[inline(always)] #[must_use] - pub fn int180(&mut self) -> INT180_W<20> { + pub fn int180(&mut self) -> INT180_W { INT180_W::new(self) } #[doc = "Bit 21 - Interrupt 181"] #[inline(always)] #[must_use] - pub fn int181(&mut self) -> INT181_W<21> { + pub fn int181(&mut self) -> INT181_W { INT181_W::new(self) } #[doc = "Bit 22 - Interrupt 182"] #[inline(always)] #[must_use] - pub fn int182(&mut self) -> INT182_W<22> { + pub fn int182(&mut self) -> INT182_W { INT182_W::new(self) } #[doc = "Bit 23 - Interrupt 183"] #[inline(always)] #[must_use] - pub fn int183(&mut self) -> INT183_W<23> { + pub fn int183(&mut self) -> INT183_W { INT183_W::new(self) } #[doc = "Bit 24 - Interrupt 184"] #[inline(always)] #[must_use] - pub fn int184(&mut self) -> INT184_W<24> { + pub fn int184(&mut self) -> INT184_W { INT184_W::new(self) } #[doc = "Bit 25 - Interrupt 185"] #[inline(always)] #[must_use] - pub fn int185(&mut self) -> INT185_W<25> { + pub fn int185(&mut self) -> INT185_W { INT185_W::new(self) } #[doc = "Bit 26 - Interrupt 186"] #[inline(always)] #[must_use] - pub fn int186(&mut self) -> INT186_W<26> { + pub fn int186(&mut self) -> INT186_W { INT186_W::new(self) } #[doc = "Bit 27 - Interrupt 187"] #[inline(always)] #[must_use] - pub fn int187(&mut self) -> INT187_W<27> { + pub fn int187(&mut self) -> INT187_W { INT187_W::new(self) } #[doc = "Bit 28 - Interrupt 188"] #[inline(always)] #[must_use] - pub fn int188(&mut self) -> INT188_W<28> { + pub fn int188(&mut self) -> INT188_W { INT188_W::new(self) } #[doc = "Bit 29 - Interrupt 189"] #[inline(always)] #[must_use] - pub fn int189(&mut self) -> INT189_W<29> { + pub fn int189(&mut self) -> INT189_W { INT189_W::new(self) } #[doc = "Bit 30 - Interrupt 190"] #[inline(always)] #[must_use] - pub fn int190(&mut self) -> INT190_W<30> { + pub fn int190(&mut self) -> INT190_W { INT190_W::new(self) } #[doc = "Bit 31 - Interrupt 191"] #[inline(always)] #[must_use] - pub fn int191(&mut self) -> INT191_W<31> { + pub fn int191(&mut self) -> INT191_W { INT191_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler5](index.html) module"] +#[doc = "Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISENABLER5_SPEC; impl crate::RegisterSpec for GICD_ISENABLER5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isenabler5::R](R) reader structure"] -impl crate::Readable for GICD_ISENABLER5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isenabler5::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isenabler5::R`](R) reader structure"] +impl crate::Readable for GICD_ISENABLER5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isenabler5::W`](W) writer structure"] impl crate::Writable for GICD_ISENABLER5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler6.rs index 3d95a3a..6076662 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler6.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_isenabler/gicd_isenabler6.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ISENABLER6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISENABLER6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT192` reader - Interrupt 192"] -pub type INT192_R = crate::BitReader; +pub type INT192_R = crate::BitReader; #[doc = "Field `INT192` writer - Interrupt 192"] -pub type INT192_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT192_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT193` reader - Interrupt 193"] -pub type INT193_R = crate::BitReader; +pub type INT193_R = crate::BitReader; #[doc = "Field `INT193` writer - Interrupt 193"] -pub type INT193_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT193_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT194` reader - Interrupt 194"] -pub type INT194_R = crate::BitReader; +pub type INT194_R = crate::BitReader; #[doc = "Field `INT194` writer - Interrupt 194"] -pub type INT194_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT194_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT195` reader - Interrupt 195"] -pub type INT195_R = crate::BitReader; +pub type INT195_R = crate::BitReader; #[doc = "Field `INT195` writer - Interrupt 195"] -pub type INT195_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT195_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT196` reader - Interrupt 196"] -pub type INT196_R = crate::BitReader; +pub type INT196_R = crate::BitReader; #[doc = "Field `INT196` writer - Interrupt 196"] -pub type INT196_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT196_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT197` reader - Interrupt 197"] -pub type INT197_R = crate::BitReader; +pub type INT197_R = crate::BitReader; #[doc = "Field `INT197` writer - Interrupt 197"] -pub type INT197_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT197_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT198` reader - Interrupt 198"] -pub type INT198_R = crate::BitReader; +pub type INT198_R = crate::BitReader; #[doc = "Field `INT198` writer - Interrupt 198"] -pub type INT198_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT198_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT199` reader - Interrupt 199"] -pub type INT199_R = crate::BitReader; +pub type INT199_R = crate::BitReader; #[doc = "Field `INT199` writer - Interrupt 199"] -pub type INT199_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT199_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT200` reader - Interrupt 200"] -pub type INT200_R = crate::BitReader; +pub type INT200_R = crate::BitReader; #[doc = "Field `INT200` writer - Interrupt 200"] -pub type INT200_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT200_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT201` reader - Interrupt 201"] -pub type INT201_R = crate::BitReader; +pub type INT201_R = crate::BitReader; #[doc = "Field `INT201` writer - Interrupt 201"] -pub type INT201_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT201_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT202` reader - Interrupt 202"] -pub type INT202_R = crate::BitReader; +pub type INT202_R = crate::BitReader; #[doc = "Field `INT202` writer - Interrupt 202"] -pub type INT202_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT202_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT203` reader - Interrupt 203"] -pub type INT203_R = crate::BitReader; +pub type INT203_R = crate::BitReader; #[doc = "Field `INT203` writer - Interrupt 203"] -pub type INT203_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT203_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT204` reader - Interrupt 204"] -pub type INT204_R = crate::BitReader; +pub type INT204_R = crate::BitReader; #[doc = "Field `INT204` writer - Interrupt 204"] -pub type INT204_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT204_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT205` reader - Interrupt 205"] -pub type INT205_R = crate::BitReader; +pub type INT205_R = crate::BitReader; #[doc = "Field `INT205` writer - Interrupt 205"] -pub type INT205_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT205_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT206` reader - Interrupt 206"] -pub type INT206_R = crate::BitReader; +pub type INT206_R = crate::BitReader; #[doc = "Field `INT206` writer - Interrupt 206"] -pub type INT206_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT206_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT207` reader - Interrupt 207"] -pub type INT207_R = crate::BitReader; +pub type INT207_R = crate::BitReader; #[doc = "Field `INT207` writer - Interrupt 207"] -pub type INT207_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT207_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT208` reader - Interrupt 208"] -pub type INT208_R = crate::BitReader; +pub type INT208_R = crate::BitReader; #[doc = "Field `INT208` writer - Interrupt 208"] -pub type INT208_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT208_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT209` reader - Interrupt 209"] -pub type INT209_R = crate::BitReader; +pub type INT209_R = crate::BitReader; #[doc = "Field `INT209` writer - Interrupt 209"] -pub type INT209_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT209_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT210` reader - Interrupt 210"] -pub type INT210_R = crate::BitReader; +pub type INT210_R = crate::BitReader; #[doc = "Field `INT210` writer - Interrupt 210"] -pub type INT210_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT210_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT211` reader - Interrupt 211"] -pub type INT211_R = crate::BitReader; +pub type INT211_R = crate::BitReader; #[doc = "Field `INT211` writer - Interrupt 211"] -pub type INT211_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT211_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT212` reader - Interrupt 212"] -pub type INT212_R = crate::BitReader; +pub type INT212_R = crate::BitReader; #[doc = "Field `INT212` writer - Interrupt 212"] -pub type INT212_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT212_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT213` reader - Interrupt 213"] -pub type INT213_R = crate::BitReader; +pub type INT213_R = crate::BitReader; #[doc = "Field `INT213` writer - Interrupt 213"] -pub type INT213_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT213_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT214` reader - Interrupt 214"] -pub type INT214_R = crate::BitReader; +pub type INT214_R = crate::BitReader; #[doc = "Field `INT214` writer - Interrupt 214"] -pub type INT214_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT214_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT215` reader - Interrupt 215"] -pub type INT215_R = crate::BitReader; +pub type INT215_R = crate::BitReader; #[doc = "Field `INT215` writer - Interrupt 215"] -pub type INT215_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT215_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT216` reader - Interrupt 216"] -pub type INT216_R = crate::BitReader; +pub type INT216_R = crate::BitReader; #[doc = "Field `INT216` writer - Interrupt 216"] -pub type INT216_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT216_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT217` reader - Interrupt 217"] -pub type INT217_R = crate::BitReader; +pub type INT217_R = crate::BitReader; #[doc = "Field `INT217` writer - Interrupt 217"] -pub type INT217_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT217_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT218` reader - Interrupt 218"] -pub type INT218_R = crate::BitReader; +pub type INT218_R = crate::BitReader; #[doc = "Field `INT218` writer - Interrupt 218"] -pub type INT218_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT218_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT219` reader - Interrupt 219"] -pub type INT219_R = crate::BitReader; +pub type INT219_R = crate::BitReader; #[doc = "Field `INT219` writer - Interrupt 219"] -pub type INT219_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT219_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT220` reader - Interrupt 220"] -pub type INT220_R = crate::BitReader; +pub type INT220_R = crate::BitReader; #[doc = "Field `INT220` writer - Interrupt 220"] -pub type INT220_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT220_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT221` reader - Interrupt 221"] -pub type INT221_R = crate::BitReader; +pub type INT221_R = crate::BitReader; #[doc = "Field `INT221` writer - Interrupt 221"] -pub type INT221_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT221_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT222` reader - Interrupt 222"] -pub type INT222_R = crate::BitReader; +pub type INT222_R = crate::BitReader; #[doc = "Field `INT222` writer - Interrupt 222"] -pub type INT222_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT222_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT223` reader - Interrupt 223"] -pub type INT223_R = crate::BitReader; +pub type INT223_R = crate::BitReader; #[doc = "Field `INT223` writer - Interrupt 223"] -pub type INT223_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISENABLER6_SPEC, bool, O>; +pub type INT223_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT223_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISENABLER6") + .field("int192", &format_args!("{}", self.int192().bit())) + .field("int193", &format_args!("{}", self.int193().bit())) + .field("int194", &format_args!("{}", self.int194().bit())) + .field("int195", &format_args!("{}", self.int195().bit())) + .field("int196", &format_args!("{}", self.int196().bit())) + .field("int197", &format_args!("{}", self.int197().bit())) + .field("int198", &format_args!("{}", self.int198().bit())) + .field("int199", &format_args!("{}", self.int199().bit())) + .field("int200", &format_args!("{}", self.int200().bit())) + .field("int201", &format_args!("{}", self.int201().bit())) + .field("int202", &format_args!("{}", self.int202().bit())) + .field("int203", &format_args!("{}", self.int203().bit())) + .field("int204", &format_args!("{}", self.int204().bit())) + .field("int205", &format_args!("{}", self.int205().bit())) + .field("int206", &format_args!("{}", self.int206().bit())) + .field("int207", &format_args!("{}", self.int207().bit())) + .field("int208", &format_args!("{}", self.int208().bit())) + .field("int209", &format_args!("{}", self.int209().bit())) + .field("int210", &format_args!("{}", self.int210().bit())) + .field("int211", &format_args!("{}", self.int211().bit())) + .field("int212", &format_args!("{}", self.int212().bit())) + .field("int213", &format_args!("{}", self.int213().bit())) + .field("int214", &format_args!("{}", self.int214().bit())) + .field("int215", &format_args!("{}", self.int215().bit())) + .field("int216", &format_args!("{}", self.int216().bit())) + .field("int217", &format_args!("{}", self.int217().bit())) + .field("int218", &format_args!("{}", self.int218().bit())) + .field("int219", &format_args!("{}", self.int219().bit())) + .field("int220", &format_args!("{}", self.int220().bit())) + .field("int221", &format_args!("{}", self.int221().bit())) + .field("int222", &format_args!("{}", self.int222().bit())) + .field("int223", &format_args!("{}", self.int223().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] #[must_use] - pub fn int192(&mut self) -> INT192_W<0> { + pub fn int192(&mut self) -> INT192_W { INT192_W::new(self) } #[doc = "Bit 1 - Interrupt 193"] #[inline(always)] #[must_use] - pub fn int193(&mut self) -> INT193_W<1> { + pub fn int193(&mut self) -> INT193_W { INT193_W::new(self) } #[doc = "Bit 2 - Interrupt 194"] #[inline(always)] #[must_use] - pub fn int194(&mut self) -> INT194_W<2> { + pub fn int194(&mut self) -> INT194_W { INT194_W::new(self) } #[doc = "Bit 3 - Interrupt 195"] #[inline(always)] #[must_use] - pub fn int195(&mut self) -> INT195_W<3> { + pub fn int195(&mut self) -> INT195_W { INT195_W::new(self) } #[doc = "Bit 4 - Interrupt 196"] #[inline(always)] #[must_use] - pub fn int196(&mut self) -> INT196_W<4> { + pub fn int196(&mut self) -> INT196_W { INT196_W::new(self) } #[doc = "Bit 5 - Interrupt 197"] #[inline(always)] #[must_use] - pub fn int197(&mut self) -> INT197_W<5> { + pub fn int197(&mut self) -> INT197_W { INT197_W::new(self) } #[doc = "Bit 6 - Interrupt 198"] #[inline(always)] #[must_use] - pub fn int198(&mut self) -> INT198_W<6> { + pub fn int198(&mut self) -> INT198_W { INT198_W::new(self) } #[doc = "Bit 7 - Interrupt 199"] #[inline(always)] #[must_use] - pub fn int199(&mut self) -> INT199_W<7> { + pub fn int199(&mut self) -> INT199_W { INT199_W::new(self) } #[doc = "Bit 8 - Interrupt 200"] #[inline(always)] #[must_use] - pub fn int200(&mut self) -> INT200_W<8> { + pub fn int200(&mut self) -> INT200_W { INT200_W::new(self) } #[doc = "Bit 9 - Interrupt 201"] #[inline(always)] #[must_use] - pub fn int201(&mut self) -> INT201_W<9> { + pub fn int201(&mut self) -> INT201_W { INT201_W::new(self) } #[doc = "Bit 10 - Interrupt 202"] #[inline(always)] #[must_use] - pub fn int202(&mut self) -> INT202_W<10> { + pub fn int202(&mut self) -> INT202_W { INT202_W::new(self) } #[doc = "Bit 11 - Interrupt 203"] #[inline(always)] #[must_use] - pub fn int203(&mut self) -> INT203_W<11> { + pub fn int203(&mut self) -> INT203_W { INT203_W::new(self) } #[doc = "Bit 12 - Interrupt 204"] #[inline(always)] #[must_use] - pub fn int204(&mut self) -> INT204_W<12> { + pub fn int204(&mut self) -> INT204_W { INT204_W::new(self) } #[doc = "Bit 13 - Interrupt 205"] #[inline(always)] #[must_use] - pub fn int205(&mut self) -> INT205_W<13> { + pub fn int205(&mut self) -> INT205_W { INT205_W::new(self) } #[doc = "Bit 14 - Interrupt 206"] #[inline(always)] #[must_use] - pub fn int206(&mut self) -> INT206_W<14> { + pub fn int206(&mut self) -> INT206_W { INT206_W::new(self) } #[doc = "Bit 15 - Interrupt 207"] #[inline(always)] #[must_use] - pub fn int207(&mut self) -> INT207_W<15> { + pub fn int207(&mut self) -> INT207_W { INT207_W::new(self) } #[doc = "Bit 16 - Interrupt 208"] #[inline(always)] #[must_use] - pub fn int208(&mut self) -> INT208_W<16> { + pub fn int208(&mut self) -> INT208_W { INT208_W::new(self) } #[doc = "Bit 17 - Interrupt 209"] #[inline(always)] #[must_use] - pub fn int209(&mut self) -> INT209_W<17> { + pub fn int209(&mut self) -> INT209_W { INT209_W::new(self) } #[doc = "Bit 18 - Interrupt 210"] #[inline(always)] #[must_use] - pub fn int210(&mut self) -> INT210_W<18> { + pub fn int210(&mut self) -> INT210_W { INT210_W::new(self) } #[doc = "Bit 19 - Interrupt 211"] #[inline(always)] #[must_use] - pub fn int211(&mut self) -> INT211_W<19> { + pub fn int211(&mut self) -> INT211_W { INT211_W::new(self) } #[doc = "Bit 20 - Interrupt 212"] #[inline(always)] #[must_use] - pub fn int212(&mut self) -> INT212_W<20> { + pub fn int212(&mut self) -> INT212_W { INT212_W::new(self) } #[doc = "Bit 21 - Interrupt 213"] #[inline(always)] #[must_use] - pub fn int213(&mut self) -> INT213_W<21> { + pub fn int213(&mut self) -> INT213_W { INT213_W::new(self) } #[doc = "Bit 22 - Interrupt 214"] #[inline(always)] #[must_use] - pub fn int214(&mut self) -> INT214_W<22> { + pub fn int214(&mut self) -> INT214_W { INT214_W::new(self) } #[doc = "Bit 23 - Interrupt 215"] #[inline(always)] #[must_use] - pub fn int215(&mut self) -> INT215_W<23> { + pub fn int215(&mut self) -> INT215_W { INT215_W::new(self) } #[doc = "Bit 24 - Interrupt 216"] #[inline(always)] #[must_use] - pub fn int216(&mut self) -> INT216_W<24> { + pub fn int216(&mut self) -> INT216_W { INT216_W::new(self) } #[doc = "Bit 25 - Interrupt 217"] #[inline(always)] #[must_use] - pub fn int217(&mut self) -> INT217_W<25> { + pub fn int217(&mut self) -> INT217_W { INT217_W::new(self) } #[doc = "Bit 26 - Interrupt 218"] #[inline(always)] #[must_use] - pub fn int218(&mut self) -> INT218_W<26> { + pub fn int218(&mut self) -> INT218_W { INT218_W::new(self) } #[doc = "Bit 27 - Interrupt 219"] #[inline(always)] #[must_use] - pub fn int219(&mut self) -> INT219_W<27> { + pub fn int219(&mut self) -> INT219_W { INT219_W::new(self) } #[doc = "Bit 28 - Interrupt 220"] #[inline(always)] #[must_use] - pub fn int220(&mut self) -> INT220_W<28> { + pub fn int220(&mut self) -> INT220_W { INT220_W::new(self) } #[doc = "Bit 29 - Interrupt 221"] #[inline(always)] #[must_use] - pub fn int221(&mut self) -> INT221_W<29> { + pub fn int221(&mut self) -> INT221_W { INT221_W::new(self) } #[doc = "Bit 30 - Interrupt 222"] #[inline(always)] #[must_use] - pub fn int222(&mut self) -> INT222_W<30> { + pub fn int222(&mut self) -> INT222_W { INT222_W::new(self) } #[doc = "Bit 31 - Interrupt 223"] #[inline(always)] #[must_use] - pub fn int223(&mut self) -> INT223_W<31> { + pub fn int223(&mut self) -> INT223_W { INT223_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_isenabler6](index.html) module"] +#[doc = "Interrupt Set-Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_isenabler6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_isenabler6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISENABLER6_SPEC; impl crate::RegisterSpec for GICD_ISENABLER6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_isenabler6::R](R) reader structure"] -impl crate::Readable for GICD_ISENABLER6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_isenabler6::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_isenabler6::R`](R) reader structure"] +impl crate::Readable for GICD_ISENABLER6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_isenabler6::W`](W) writer structure"] impl crate::Writable for GICD_ISENABLER6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr.rs index 72a608b..33eb696 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct GICD_ISPENDR { #[doc = "0x00 - Interrupt Set-Pending"] pub gicd_ispendr0: GICD_ISPENDR0, @@ -16,31 +17,38 @@ pub struct GICD_ISPENDR { #[doc = "0x18 - Interrupt Set-Pending"] pub gicd_ispendr6: GICD_ISPENDR6, } -#[doc = "GICD_ISPENDR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISPENDR0 (rw) register accessor: Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ispendr0`] +module"] pub type GICD_ISPENDR0 = crate::Reg; #[doc = "Interrupt Set-Pending"] pub mod gicd_ispendr0; -#[doc = "GICD_ISPENDR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISPENDR1 (rw) register accessor: Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ispendr1`] +module"] pub type GICD_ISPENDR1 = crate::Reg; #[doc = "Interrupt Set-Pending"] pub mod gicd_ispendr1; -#[doc = "GICD_ISPENDR2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISPENDR2 (rw) register accessor: Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ispendr2`] +module"] pub type GICD_ISPENDR2 = crate::Reg; #[doc = "Interrupt Set-Pending"] pub mod gicd_ispendr2; -#[doc = "GICD_ISPENDR3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISPENDR3 (rw) register accessor: Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ispendr3`] +module"] pub type GICD_ISPENDR3 = crate::Reg; #[doc = "Interrupt Set-Pending"] pub mod gicd_ispendr3; -#[doc = "GICD_ISPENDR4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISPENDR4 (rw) register accessor: Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ispendr4`] +module"] pub type GICD_ISPENDR4 = crate::Reg; #[doc = "Interrupt Set-Pending"] pub mod gicd_ispendr4; -#[doc = "GICD_ISPENDR5 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISPENDR5 (rw) register accessor: Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ispendr5`] +module"] pub type GICD_ISPENDR5 = crate::Reg; #[doc = "Interrupt Set-Pending"] pub mod gicd_ispendr5; -#[doc = "GICD_ISPENDR6 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ISPENDR6 (rw) register accessor: Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_ispendr6`] +module"] pub type GICD_ISPENDR6 = crate::Reg; #[doc = "Interrupt Set-Pending"] pub mod gicd_ispendr6; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr0.rs index d8bdd51..bd095e3 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr0.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ISPENDR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISPENDR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT0` reader - Interrupt 0"] -pub type INT0_R = crate::BitReader; +pub type INT0_R = crate::BitReader; #[doc = "Field `INT0` writer - Interrupt 0"] -pub type INT0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT1` reader - Interrupt 1"] -pub type INT1_R = crate::BitReader; +pub type INT1_R = crate::BitReader; #[doc = "Field `INT1` writer - Interrupt 1"] -pub type INT1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT2` reader - Interrupt 2"] -pub type INT2_R = crate::BitReader; +pub type INT2_R = crate::BitReader; #[doc = "Field `INT2` writer - Interrupt 2"] -pub type INT2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT3` reader - Interrupt 3"] -pub type INT3_R = crate::BitReader; +pub type INT3_R = crate::BitReader; #[doc = "Field `INT3` writer - Interrupt 3"] -pub type INT3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT4` reader - Interrupt 4"] -pub type INT4_R = crate::BitReader; +pub type INT4_R = crate::BitReader; #[doc = "Field `INT4` writer - Interrupt 4"] -pub type INT4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT5` reader - Interrupt 5"] -pub type INT5_R = crate::BitReader; +pub type INT5_R = crate::BitReader; #[doc = "Field `INT5` writer - Interrupt 5"] -pub type INT5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT6` reader - Interrupt 6"] -pub type INT6_R = crate::BitReader; +pub type INT6_R = crate::BitReader; #[doc = "Field `INT6` writer - Interrupt 6"] -pub type INT6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT7` reader - Interrupt 7"] -pub type INT7_R = crate::BitReader; +pub type INT7_R = crate::BitReader; #[doc = "Field `INT7` writer - Interrupt 7"] -pub type INT7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT7_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT8` reader - Interrupt 8"] -pub type INT8_R = crate::BitReader; +pub type INT8_R = crate::BitReader; #[doc = "Field `INT8` writer - Interrupt 8"] -pub type INT8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT8_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT9` reader - Interrupt 9"] -pub type INT9_R = crate::BitReader; +pub type INT9_R = crate::BitReader; #[doc = "Field `INT9` writer - Interrupt 9"] -pub type INT9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT9_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT10` reader - Interrupt 10"] -pub type INT10_R = crate::BitReader; +pub type INT10_R = crate::BitReader; #[doc = "Field `INT10` writer - Interrupt 10"] -pub type INT10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT10_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT11` reader - Interrupt 11"] -pub type INT11_R = crate::BitReader; +pub type INT11_R = crate::BitReader; #[doc = "Field `INT11` writer - Interrupt 11"] -pub type INT11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT11_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT12` reader - Interrupt 12"] -pub type INT12_R = crate::BitReader; +pub type INT12_R = crate::BitReader; #[doc = "Field `INT12` writer - Interrupt 12"] -pub type INT12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT12_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT13` reader - Interrupt 13"] -pub type INT13_R = crate::BitReader; +pub type INT13_R = crate::BitReader; #[doc = "Field `INT13` writer - Interrupt 13"] -pub type INT13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT13_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT14` reader - Interrupt 14"] -pub type INT14_R = crate::BitReader; +pub type INT14_R = crate::BitReader; #[doc = "Field `INT14` writer - Interrupt 14"] -pub type INT14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT14_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT15` reader - Interrupt 15"] -pub type INT15_R = crate::BitReader; +pub type INT15_R = crate::BitReader; #[doc = "Field `INT15` writer - Interrupt 15"] -pub type INT15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT15_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT16` reader - Interrupt 16"] -pub type INT16_R = crate::BitReader; +pub type INT16_R = crate::BitReader; #[doc = "Field `INT16` writer - Interrupt 16"] -pub type INT16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT16_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT17` reader - Interrupt 17"] -pub type INT17_R = crate::BitReader; +pub type INT17_R = crate::BitReader; #[doc = "Field `INT17` writer - Interrupt 17"] -pub type INT17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT17_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT18` reader - Interrupt 18"] -pub type INT18_R = crate::BitReader; +pub type INT18_R = crate::BitReader; #[doc = "Field `INT18` writer - Interrupt 18"] -pub type INT18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT18_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT19` reader - Interrupt 19"] -pub type INT19_R = crate::BitReader; +pub type INT19_R = crate::BitReader; #[doc = "Field `INT19` writer - Interrupt 19"] -pub type INT19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT19_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT20` reader - Interrupt 20"] -pub type INT20_R = crate::BitReader; +pub type INT20_R = crate::BitReader; #[doc = "Field `INT20` writer - Interrupt 20"] -pub type INT20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT20_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT21` reader - Interrupt 21"] -pub type INT21_R = crate::BitReader; +pub type INT21_R = crate::BitReader; #[doc = "Field `INT21` writer - Interrupt 21"] -pub type INT21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT21_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT22` reader - Interrupt 22"] -pub type INT22_R = crate::BitReader; +pub type INT22_R = crate::BitReader; #[doc = "Field `INT22` writer - Interrupt 22"] -pub type INT22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT22_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT23` reader - Interrupt 23"] -pub type INT23_R = crate::BitReader; +pub type INT23_R = crate::BitReader; #[doc = "Field `INT23` writer - Interrupt 23"] -pub type INT23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT23_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT24` reader - Interrupt 24"] -pub type INT24_R = crate::BitReader; +pub type INT24_R = crate::BitReader; #[doc = "Field `INT24` writer - Interrupt 24"] -pub type INT24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT24_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT25` reader - Interrupt 25"] -pub type INT25_R = crate::BitReader; +pub type INT25_R = crate::BitReader; #[doc = "Field `INT25` writer - Interrupt 25"] -pub type INT25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT25_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT26` reader - Interrupt 26"] -pub type INT26_R = crate::BitReader; +pub type INT26_R = crate::BitReader; #[doc = "Field `INT26` writer - Interrupt 26"] -pub type INT26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT26_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT27` reader - Interrupt 27"] -pub type INT27_R = crate::BitReader; +pub type INT27_R = crate::BitReader; #[doc = "Field `INT27` writer - Interrupt 27"] -pub type INT27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT27_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT28` reader - Interrupt 28"] -pub type INT28_R = crate::BitReader; +pub type INT28_R = crate::BitReader; #[doc = "Field `INT28` writer - Interrupt 28"] -pub type INT28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT28_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT29` reader - Interrupt 29"] -pub type INT29_R = crate::BitReader; +pub type INT29_R = crate::BitReader; #[doc = "Field `INT29` writer - Interrupt 29"] -pub type INT29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT29_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT30` reader - Interrupt 30"] -pub type INT30_R = crate::BitReader; +pub type INT30_R = crate::BitReader; #[doc = "Field `INT30` writer - Interrupt 30"] -pub type INT30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT30_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT31` reader - Interrupt 31"] -pub type INT31_R = crate::BitReader; +pub type INT31_R = crate::BitReader; #[doc = "Field `INT31` writer - Interrupt 31"] -pub type INT31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR0_SPEC, bool, O>; +pub type INT31_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISPENDR0") + .field("int0", &format_args!("{}", self.int0().bit())) + .field("int1", &format_args!("{}", self.int1().bit())) + .field("int2", &format_args!("{}", self.int2().bit())) + .field("int3", &format_args!("{}", self.int3().bit())) + .field("int4", &format_args!("{}", self.int4().bit())) + .field("int5", &format_args!("{}", self.int5().bit())) + .field("int6", &format_args!("{}", self.int6().bit())) + .field("int7", &format_args!("{}", self.int7().bit())) + .field("int8", &format_args!("{}", self.int8().bit())) + .field("int9", &format_args!("{}", self.int9().bit())) + .field("int10", &format_args!("{}", self.int10().bit())) + .field("int11", &format_args!("{}", self.int11().bit())) + .field("int12", &format_args!("{}", self.int12().bit())) + .field("int13", &format_args!("{}", self.int13().bit())) + .field("int14", &format_args!("{}", self.int14().bit())) + .field("int15", &format_args!("{}", self.int15().bit())) + .field("int16", &format_args!("{}", self.int16().bit())) + .field("int17", &format_args!("{}", self.int17().bit())) + .field("int18", &format_args!("{}", self.int18().bit())) + .field("int19", &format_args!("{}", self.int19().bit())) + .field("int20", &format_args!("{}", self.int20().bit())) + .field("int21", &format_args!("{}", self.int21().bit())) + .field("int22", &format_args!("{}", self.int22().bit())) + .field("int23", &format_args!("{}", self.int23().bit())) + .field("int24", &format_args!("{}", self.int24().bit())) + .field("int25", &format_args!("{}", self.int25().bit())) + .field("int26", &format_args!("{}", self.int26().bit())) + .field("int27", &format_args!("{}", self.int27().bit())) + .field("int28", &format_args!("{}", self.int28().bit())) + .field("int29", &format_args!("{}", self.int29().bit())) + .field("int30", &format_args!("{}", self.int30().bit())) + .field("int31", &format_args!("{}", self.int31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] #[must_use] - pub fn int0(&mut self) -> INT0_W<0> { + pub fn int0(&mut self) -> INT0_W { INT0_W::new(self) } #[doc = "Bit 1 - Interrupt 1"] #[inline(always)] #[must_use] - pub fn int1(&mut self) -> INT1_W<1> { + pub fn int1(&mut self) -> INT1_W { INT1_W::new(self) } #[doc = "Bit 2 - Interrupt 2"] #[inline(always)] #[must_use] - pub fn int2(&mut self) -> INT2_W<2> { + pub fn int2(&mut self) -> INT2_W { INT2_W::new(self) } #[doc = "Bit 3 - Interrupt 3"] #[inline(always)] #[must_use] - pub fn int3(&mut self) -> INT3_W<3> { + pub fn int3(&mut self) -> INT3_W { INT3_W::new(self) } #[doc = "Bit 4 - Interrupt 4"] #[inline(always)] #[must_use] - pub fn int4(&mut self) -> INT4_W<4> { + pub fn int4(&mut self) -> INT4_W { INT4_W::new(self) } #[doc = "Bit 5 - Interrupt 5"] #[inline(always)] #[must_use] - pub fn int5(&mut self) -> INT5_W<5> { + pub fn int5(&mut self) -> INT5_W { INT5_W::new(self) } #[doc = "Bit 6 - Interrupt 6"] #[inline(always)] #[must_use] - pub fn int6(&mut self) -> INT6_W<6> { + pub fn int6(&mut self) -> INT6_W { INT6_W::new(self) } #[doc = "Bit 7 - Interrupt 7"] #[inline(always)] #[must_use] - pub fn int7(&mut self) -> INT7_W<7> { + pub fn int7(&mut self) -> INT7_W { INT7_W::new(self) } #[doc = "Bit 8 - Interrupt 8"] #[inline(always)] #[must_use] - pub fn int8(&mut self) -> INT8_W<8> { + pub fn int8(&mut self) -> INT8_W { INT8_W::new(self) } #[doc = "Bit 9 - Interrupt 9"] #[inline(always)] #[must_use] - pub fn int9(&mut self) -> INT9_W<9> { + pub fn int9(&mut self) -> INT9_W { INT9_W::new(self) } #[doc = "Bit 10 - Interrupt 10"] #[inline(always)] #[must_use] - pub fn int10(&mut self) -> INT10_W<10> { + pub fn int10(&mut self) -> INT10_W { INT10_W::new(self) } #[doc = "Bit 11 - Interrupt 11"] #[inline(always)] #[must_use] - pub fn int11(&mut self) -> INT11_W<11> { + pub fn int11(&mut self) -> INT11_W { INT11_W::new(self) } #[doc = "Bit 12 - Interrupt 12"] #[inline(always)] #[must_use] - pub fn int12(&mut self) -> INT12_W<12> { + pub fn int12(&mut self) -> INT12_W { INT12_W::new(self) } #[doc = "Bit 13 - Interrupt 13"] #[inline(always)] #[must_use] - pub fn int13(&mut self) -> INT13_W<13> { + pub fn int13(&mut self) -> INT13_W { INT13_W::new(self) } #[doc = "Bit 14 - Interrupt 14"] #[inline(always)] #[must_use] - pub fn int14(&mut self) -> INT14_W<14> { + pub fn int14(&mut self) -> INT14_W { INT14_W::new(self) } #[doc = "Bit 15 - Interrupt 15"] #[inline(always)] #[must_use] - pub fn int15(&mut self) -> INT15_W<15> { + pub fn int15(&mut self) -> INT15_W { INT15_W::new(self) } #[doc = "Bit 16 - Interrupt 16"] #[inline(always)] #[must_use] - pub fn int16(&mut self) -> INT16_W<16> { + pub fn int16(&mut self) -> INT16_W { INT16_W::new(self) } #[doc = "Bit 17 - Interrupt 17"] #[inline(always)] #[must_use] - pub fn int17(&mut self) -> INT17_W<17> { + pub fn int17(&mut self) -> INT17_W { INT17_W::new(self) } #[doc = "Bit 18 - Interrupt 18"] #[inline(always)] #[must_use] - pub fn int18(&mut self) -> INT18_W<18> { + pub fn int18(&mut self) -> INT18_W { INT18_W::new(self) } #[doc = "Bit 19 - Interrupt 19"] #[inline(always)] #[must_use] - pub fn int19(&mut self) -> INT19_W<19> { + pub fn int19(&mut self) -> INT19_W { INT19_W::new(self) } #[doc = "Bit 20 - Interrupt 20"] #[inline(always)] #[must_use] - pub fn int20(&mut self) -> INT20_W<20> { + pub fn int20(&mut self) -> INT20_W { INT20_W::new(self) } #[doc = "Bit 21 - Interrupt 21"] #[inline(always)] #[must_use] - pub fn int21(&mut self) -> INT21_W<21> { + pub fn int21(&mut self) -> INT21_W { INT21_W::new(self) } #[doc = "Bit 22 - Interrupt 22"] #[inline(always)] #[must_use] - pub fn int22(&mut self) -> INT22_W<22> { + pub fn int22(&mut self) -> INT22_W { INT22_W::new(self) } #[doc = "Bit 23 - Interrupt 23"] #[inline(always)] #[must_use] - pub fn int23(&mut self) -> INT23_W<23> { + pub fn int23(&mut self) -> INT23_W { INT23_W::new(self) } #[doc = "Bit 24 - Interrupt 24"] #[inline(always)] #[must_use] - pub fn int24(&mut self) -> INT24_W<24> { + pub fn int24(&mut self) -> INT24_W { INT24_W::new(self) } #[doc = "Bit 25 - Interrupt 25"] #[inline(always)] #[must_use] - pub fn int25(&mut self) -> INT25_W<25> { + pub fn int25(&mut self) -> INT25_W { INT25_W::new(self) } #[doc = "Bit 26 - Interrupt 26"] #[inline(always)] #[must_use] - pub fn int26(&mut self) -> INT26_W<26> { + pub fn int26(&mut self) -> INT26_W { INT26_W::new(self) } #[doc = "Bit 27 - Interrupt 27"] #[inline(always)] #[must_use] - pub fn int27(&mut self) -> INT27_W<27> { + pub fn int27(&mut self) -> INT27_W { INT27_W::new(self) } #[doc = "Bit 28 - Interrupt 28"] #[inline(always)] #[must_use] - pub fn int28(&mut self) -> INT28_W<28> { + pub fn int28(&mut self) -> INT28_W { INT28_W::new(self) } #[doc = "Bit 29 - Interrupt 29"] #[inline(always)] #[must_use] - pub fn int29(&mut self) -> INT29_W<29> { + pub fn int29(&mut self) -> INT29_W { INT29_W::new(self) } #[doc = "Bit 30 - Interrupt 30"] #[inline(always)] #[must_use] - pub fn int30(&mut self) -> INT30_W<30> { + pub fn int30(&mut self) -> INT30_W { INT30_W::new(self) } #[doc = "Bit 31 - Interrupt 31"] #[inline(always)] #[must_use] - pub fn int31(&mut self) -> INT31_W<31> { + pub fn int31(&mut self) -> INT31_W { INT31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr0](index.html) module"] +#[doc = "Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISPENDR0_SPEC; impl crate::RegisterSpec for GICD_ISPENDR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ispendr0::R](R) reader structure"] -impl crate::Readable for GICD_ISPENDR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ispendr0::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ispendr0::R`](R) reader structure"] +impl crate::Readable for GICD_ISPENDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ispendr0::W`](W) writer structure"] impl crate::Writable for GICD_ISPENDR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr1.rs index 115b2fa..1bf7599 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr1.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr1.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ISPENDR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISPENDR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT32` reader - Interrupt 32"] -pub type INT32_R = crate::BitReader; +pub type INT32_R = crate::BitReader; #[doc = "Field `INT32` writer - Interrupt 32"] -pub type INT32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT32_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT33` reader - Interrupt 33"] -pub type INT33_R = crate::BitReader; +pub type INT33_R = crate::BitReader; #[doc = "Field `INT33` writer - Interrupt 33"] -pub type INT33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT33_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT34` reader - Interrupt 34"] -pub type INT34_R = crate::BitReader; +pub type INT34_R = crate::BitReader; #[doc = "Field `INT34` writer - Interrupt 34"] -pub type INT34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT34_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT35` reader - Interrupt 35"] -pub type INT35_R = crate::BitReader; +pub type INT35_R = crate::BitReader; #[doc = "Field `INT35` writer - Interrupt 35"] -pub type INT35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT35_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT36` reader - Interrupt 36"] -pub type INT36_R = crate::BitReader; +pub type INT36_R = crate::BitReader; #[doc = "Field `INT36` writer - Interrupt 36"] -pub type INT36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT36_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT37` reader - Interrupt 37"] -pub type INT37_R = crate::BitReader; +pub type INT37_R = crate::BitReader; #[doc = "Field `INT37` writer - Interrupt 37"] -pub type INT37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT37_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT38` reader - Interrupt 38"] -pub type INT38_R = crate::BitReader; +pub type INT38_R = crate::BitReader; #[doc = "Field `INT38` writer - Interrupt 38"] -pub type INT38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT38_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT39` reader - Interrupt 39"] -pub type INT39_R = crate::BitReader; +pub type INT39_R = crate::BitReader; #[doc = "Field `INT39` writer - Interrupt 39"] -pub type INT39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT39_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT40` reader - Interrupt 40"] -pub type INT40_R = crate::BitReader; +pub type INT40_R = crate::BitReader; #[doc = "Field `INT40` writer - Interrupt 40"] -pub type INT40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT40_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT41` reader - Interrupt 41"] -pub type INT41_R = crate::BitReader; +pub type INT41_R = crate::BitReader; #[doc = "Field `INT41` writer - Interrupt 41"] -pub type INT41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT41_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT42` reader - Interrupt 42"] -pub type INT42_R = crate::BitReader; +pub type INT42_R = crate::BitReader; #[doc = "Field `INT42` writer - Interrupt 42"] -pub type INT42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT42_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT43` reader - Interrupt 43"] -pub type INT43_R = crate::BitReader; +pub type INT43_R = crate::BitReader; #[doc = "Field `INT43` writer - Interrupt 43"] -pub type INT43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT43_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT44` reader - Interrupt 44"] -pub type INT44_R = crate::BitReader; +pub type INT44_R = crate::BitReader; #[doc = "Field `INT44` writer - Interrupt 44"] -pub type INT44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT44_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT45` reader - Interrupt 45"] -pub type INT45_R = crate::BitReader; +pub type INT45_R = crate::BitReader; #[doc = "Field `INT45` writer - Interrupt 45"] -pub type INT45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT45_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT46` reader - Interrupt 46"] -pub type INT46_R = crate::BitReader; +pub type INT46_R = crate::BitReader; #[doc = "Field `INT46` writer - Interrupt 46"] -pub type INT46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT46_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT47` reader - Interrupt 47"] -pub type INT47_R = crate::BitReader; +pub type INT47_R = crate::BitReader; #[doc = "Field `INT47` writer - Interrupt 47"] -pub type INT47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT47_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT48` reader - Interrupt 48"] -pub type INT48_R = crate::BitReader; +pub type INT48_R = crate::BitReader; #[doc = "Field `INT48` writer - Interrupt 48"] -pub type INT48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT48_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT49` reader - Interrupt 49"] -pub type INT49_R = crate::BitReader; +pub type INT49_R = crate::BitReader; #[doc = "Field `INT49` writer - Interrupt 49"] -pub type INT49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT49_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT50` reader - Interrupt 50"] -pub type INT50_R = crate::BitReader; +pub type INT50_R = crate::BitReader; #[doc = "Field `INT50` writer - Interrupt 50"] -pub type INT50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT50_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT51` reader - Interrupt 51"] -pub type INT51_R = crate::BitReader; +pub type INT51_R = crate::BitReader; #[doc = "Field `INT51` writer - Interrupt 51"] -pub type INT51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT51_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT52` reader - Interrupt 52"] -pub type INT52_R = crate::BitReader; +pub type INT52_R = crate::BitReader; #[doc = "Field `INT52` writer - Interrupt 52"] -pub type INT52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT52_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT53` reader - Interrupt 53"] -pub type INT53_R = crate::BitReader; +pub type INT53_R = crate::BitReader; #[doc = "Field `INT53` writer - Interrupt 53"] -pub type INT53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT53_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT54` reader - Interrupt 54"] -pub type INT54_R = crate::BitReader; +pub type INT54_R = crate::BitReader; #[doc = "Field `INT54` writer - Interrupt 54"] -pub type INT54_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT54_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT55` reader - Interrupt 55"] -pub type INT55_R = crate::BitReader; +pub type INT55_R = crate::BitReader; #[doc = "Field `INT55` writer - Interrupt 55"] -pub type INT55_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT55_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT56` reader - Interrupt 56"] -pub type INT56_R = crate::BitReader; +pub type INT56_R = crate::BitReader; #[doc = "Field `INT56` writer - Interrupt 56"] -pub type INT56_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT56_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT57` reader - Interrupt 57"] -pub type INT57_R = crate::BitReader; +pub type INT57_R = crate::BitReader; #[doc = "Field `INT57` writer - Interrupt 57"] -pub type INT57_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT57_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT58` reader - Interrupt 58"] -pub type INT58_R = crate::BitReader; +pub type INT58_R = crate::BitReader; #[doc = "Field `INT58` writer - Interrupt 58"] -pub type INT58_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT58_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT59` reader - Interrupt 59"] -pub type INT59_R = crate::BitReader; +pub type INT59_R = crate::BitReader; #[doc = "Field `INT59` writer - Interrupt 59"] -pub type INT59_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT59_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT60` reader - Interrupt 60"] -pub type INT60_R = crate::BitReader; +pub type INT60_R = crate::BitReader; #[doc = "Field `INT60` writer - Interrupt 60"] -pub type INT60_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT60_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT61` reader - Interrupt 61"] -pub type INT61_R = crate::BitReader; +pub type INT61_R = crate::BitReader; #[doc = "Field `INT61` writer - Interrupt 61"] -pub type INT61_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT61_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT62` reader - Interrupt 62"] -pub type INT62_R = crate::BitReader; +pub type INT62_R = crate::BitReader; #[doc = "Field `INT62` writer - Interrupt 62"] -pub type INT62_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT62_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT63` reader - Interrupt 63"] -pub type INT63_R = crate::BitReader; +pub type INT63_R = crate::BitReader; #[doc = "Field `INT63` writer - Interrupt 63"] -pub type INT63_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR1_SPEC, bool, O>; +pub type INT63_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT63_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISPENDR1") + .field("int32", &format_args!("{}", self.int32().bit())) + .field("int33", &format_args!("{}", self.int33().bit())) + .field("int34", &format_args!("{}", self.int34().bit())) + .field("int35", &format_args!("{}", self.int35().bit())) + .field("int36", &format_args!("{}", self.int36().bit())) + .field("int37", &format_args!("{}", self.int37().bit())) + .field("int38", &format_args!("{}", self.int38().bit())) + .field("int39", &format_args!("{}", self.int39().bit())) + .field("int40", &format_args!("{}", self.int40().bit())) + .field("int41", &format_args!("{}", self.int41().bit())) + .field("int42", &format_args!("{}", self.int42().bit())) + .field("int43", &format_args!("{}", self.int43().bit())) + .field("int44", &format_args!("{}", self.int44().bit())) + .field("int45", &format_args!("{}", self.int45().bit())) + .field("int46", &format_args!("{}", self.int46().bit())) + .field("int47", &format_args!("{}", self.int47().bit())) + .field("int48", &format_args!("{}", self.int48().bit())) + .field("int49", &format_args!("{}", self.int49().bit())) + .field("int50", &format_args!("{}", self.int50().bit())) + .field("int51", &format_args!("{}", self.int51().bit())) + .field("int52", &format_args!("{}", self.int52().bit())) + .field("int53", &format_args!("{}", self.int53().bit())) + .field("int54", &format_args!("{}", self.int54().bit())) + .field("int55", &format_args!("{}", self.int55().bit())) + .field("int56", &format_args!("{}", self.int56().bit())) + .field("int57", &format_args!("{}", self.int57().bit())) + .field("int58", &format_args!("{}", self.int58().bit())) + .field("int59", &format_args!("{}", self.int59().bit())) + .field("int60", &format_args!("{}", self.int60().bit())) + .field("int61", &format_args!("{}", self.int61().bit())) + .field("int62", &format_args!("{}", self.int62().bit())) + .field("int63", &format_args!("{}", self.int63().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] #[must_use] - pub fn int32(&mut self) -> INT32_W<0> { + pub fn int32(&mut self) -> INT32_W { INT32_W::new(self) } #[doc = "Bit 1 - Interrupt 33"] #[inline(always)] #[must_use] - pub fn int33(&mut self) -> INT33_W<1> { + pub fn int33(&mut self) -> INT33_W { INT33_W::new(self) } #[doc = "Bit 2 - Interrupt 34"] #[inline(always)] #[must_use] - pub fn int34(&mut self) -> INT34_W<2> { + pub fn int34(&mut self) -> INT34_W { INT34_W::new(self) } #[doc = "Bit 3 - Interrupt 35"] #[inline(always)] #[must_use] - pub fn int35(&mut self) -> INT35_W<3> { + pub fn int35(&mut self) -> INT35_W { INT35_W::new(self) } #[doc = "Bit 4 - Interrupt 36"] #[inline(always)] #[must_use] - pub fn int36(&mut self) -> INT36_W<4> { + pub fn int36(&mut self) -> INT36_W { INT36_W::new(self) } #[doc = "Bit 5 - Interrupt 37"] #[inline(always)] #[must_use] - pub fn int37(&mut self) -> INT37_W<5> { + pub fn int37(&mut self) -> INT37_W { INT37_W::new(self) } #[doc = "Bit 6 - Interrupt 38"] #[inline(always)] #[must_use] - pub fn int38(&mut self) -> INT38_W<6> { + pub fn int38(&mut self) -> INT38_W { INT38_W::new(self) } #[doc = "Bit 7 - Interrupt 39"] #[inline(always)] #[must_use] - pub fn int39(&mut self) -> INT39_W<7> { + pub fn int39(&mut self) -> INT39_W { INT39_W::new(self) } #[doc = "Bit 8 - Interrupt 40"] #[inline(always)] #[must_use] - pub fn int40(&mut self) -> INT40_W<8> { + pub fn int40(&mut self) -> INT40_W { INT40_W::new(self) } #[doc = "Bit 9 - Interrupt 41"] #[inline(always)] #[must_use] - pub fn int41(&mut self) -> INT41_W<9> { + pub fn int41(&mut self) -> INT41_W { INT41_W::new(self) } #[doc = "Bit 10 - Interrupt 42"] #[inline(always)] #[must_use] - pub fn int42(&mut self) -> INT42_W<10> { + pub fn int42(&mut self) -> INT42_W { INT42_W::new(self) } #[doc = "Bit 11 - Interrupt 43"] #[inline(always)] #[must_use] - pub fn int43(&mut self) -> INT43_W<11> { + pub fn int43(&mut self) -> INT43_W { INT43_W::new(self) } #[doc = "Bit 12 - Interrupt 44"] #[inline(always)] #[must_use] - pub fn int44(&mut self) -> INT44_W<12> { + pub fn int44(&mut self) -> INT44_W { INT44_W::new(self) } #[doc = "Bit 13 - Interrupt 45"] #[inline(always)] #[must_use] - pub fn int45(&mut self) -> INT45_W<13> { + pub fn int45(&mut self) -> INT45_W { INT45_W::new(self) } #[doc = "Bit 14 - Interrupt 46"] #[inline(always)] #[must_use] - pub fn int46(&mut self) -> INT46_W<14> { + pub fn int46(&mut self) -> INT46_W { INT46_W::new(self) } #[doc = "Bit 15 - Interrupt 47"] #[inline(always)] #[must_use] - pub fn int47(&mut self) -> INT47_W<15> { + pub fn int47(&mut self) -> INT47_W { INT47_W::new(self) } #[doc = "Bit 16 - Interrupt 48"] #[inline(always)] #[must_use] - pub fn int48(&mut self) -> INT48_W<16> { + pub fn int48(&mut self) -> INT48_W { INT48_W::new(self) } #[doc = "Bit 17 - Interrupt 49"] #[inline(always)] #[must_use] - pub fn int49(&mut self) -> INT49_W<17> { + pub fn int49(&mut self) -> INT49_W { INT49_W::new(self) } #[doc = "Bit 18 - Interrupt 50"] #[inline(always)] #[must_use] - pub fn int50(&mut self) -> INT50_W<18> { + pub fn int50(&mut self) -> INT50_W { INT50_W::new(self) } #[doc = "Bit 19 - Interrupt 51"] #[inline(always)] #[must_use] - pub fn int51(&mut self) -> INT51_W<19> { + pub fn int51(&mut self) -> INT51_W { INT51_W::new(self) } #[doc = "Bit 20 - Interrupt 52"] #[inline(always)] #[must_use] - pub fn int52(&mut self) -> INT52_W<20> { + pub fn int52(&mut self) -> INT52_W { INT52_W::new(self) } #[doc = "Bit 21 - Interrupt 53"] #[inline(always)] #[must_use] - pub fn int53(&mut self) -> INT53_W<21> { + pub fn int53(&mut self) -> INT53_W { INT53_W::new(self) } #[doc = "Bit 22 - Interrupt 54"] #[inline(always)] #[must_use] - pub fn int54(&mut self) -> INT54_W<22> { + pub fn int54(&mut self) -> INT54_W { INT54_W::new(self) } #[doc = "Bit 23 - Interrupt 55"] #[inline(always)] #[must_use] - pub fn int55(&mut self) -> INT55_W<23> { + pub fn int55(&mut self) -> INT55_W { INT55_W::new(self) } #[doc = "Bit 24 - Interrupt 56"] #[inline(always)] #[must_use] - pub fn int56(&mut self) -> INT56_W<24> { + pub fn int56(&mut self) -> INT56_W { INT56_W::new(self) } #[doc = "Bit 25 - Interrupt 57"] #[inline(always)] #[must_use] - pub fn int57(&mut self) -> INT57_W<25> { + pub fn int57(&mut self) -> INT57_W { INT57_W::new(self) } #[doc = "Bit 26 - Interrupt 58"] #[inline(always)] #[must_use] - pub fn int58(&mut self) -> INT58_W<26> { + pub fn int58(&mut self) -> INT58_W { INT58_W::new(self) } #[doc = "Bit 27 - Interrupt 59"] #[inline(always)] #[must_use] - pub fn int59(&mut self) -> INT59_W<27> { + pub fn int59(&mut self) -> INT59_W { INT59_W::new(self) } #[doc = "Bit 28 - Interrupt 60"] #[inline(always)] #[must_use] - pub fn int60(&mut self) -> INT60_W<28> { + pub fn int60(&mut self) -> INT60_W { INT60_W::new(self) } #[doc = "Bit 29 - Interrupt 61"] #[inline(always)] #[must_use] - pub fn int61(&mut self) -> INT61_W<29> { + pub fn int61(&mut self) -> INT61_W { INT61_W::new(self) } #[doc = "Bit 30 - Interrupt 62"] #[inline(always)] #[must_use] - pub fn int62(&mut self) -> INT62_W<30> { + pub fn int62(&mut self) -> INT62_W { INT62_W::new(self) } #[doc = "Bit 31 - Interrupt 63"] #[inline(always)] #[must_use] - pub fn int63(&mut self) -> INT63_W<31> { + pub fn int63(&mut self) -> INT63_W { INT63_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr1](index.html) module"] +#[doc = "Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISPENDR1_SPEC; impl crate::RegisterSpec for GICD_ISPENDR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ispendr1::R](R) reader structure"] -impl crate::Readable for GICD_ISPENDR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ispendr1::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ispendr1::R`](R) reader structure"] +impl crate::Readable for GICD_ISPENDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ispendr1::W`](W) writer structure"] impl crate::Writable for GICD_ISPENDR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr2.rs index 0b297a9..8a316b5 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr2.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr2.rs @@ -1,169 +1,135 @@ #[doc = "Register `GICD_ISPENDR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISPENDR2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI0` reader - Software interrupt 0"] -pub type SWI0_R = crate::BitReader; +pub type SWI0_R = crate::BitReader; #[doc = "Field `SWI0` writer - Software interrupt 0"] -pub type SWI0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type SWI0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI1` reader - Software interrupt 1"] -pub type SWI1_R = crate::BitReader; +pub type SWI1_R = crate::BitReader; #[doc = "Field `SWI1` writer - Software interrupt 1"] -pub type SWI1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type SWI1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI2` reader - Software interrupt 2"] -pub type SWI2_R = crate::BitReader; +pub type SWI2_R = crate::BitReader; #[doc = "Field `SWI2` writer - Software interrupt 2"] -pub type SWI2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type SWI2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI3` reader - Software interrupt 3"] -pub type SWI3_R = crate::BitReader; +pub type SWI3_R = crate::BitReader; #[doc = "Field `SWI3` writer - Software interrupt 3"] -pub type SWI3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type SWI3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI4` reader - Software interrupt 4"] -pub type SWI4_R = crate::BitReader; +pub type SWI4_R = crate::BitReader; #[doc = "Field `SWI4` writer - Software interrupt 4"] -pub type SWI4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type SWI4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI5` reader - Software interrupt 5"] -pub type SWI5_R = crate::BitReader; +pub type SWI5_R = crate::BitReader; #[doc = "Field `SWI5` writer - Software interrupt 5"] -pub type SWI5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type SWI5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI6` reader - Software interrupt 6"] -pub type SWI6_R = crate::BitReader; +pub type SWI6_R = crate::BitReader; #[doc = "Field `SWI6` writer - Software interrupt 6"] -pub type SWI6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type SWI6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SWI7` reader - Software interrupt 7"] -pub type SWI7_R = crate::BitReader; +pub type SWI7_R = crate::BitReader; #[doc = "Field `SWI7` writer - Software interrupt 7"] -pub type SWI7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type SWI7_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT80` reader - Interrupt 80"] -pub type INT80_R = crate::BitReader; +pub type INT80_R = crate::BitReader; #[doc = "Field `INT80` writer - Interrupt 80"] -pub type INT80_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT80_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT81` reader - Interrupt 81"] -pub type INT81_R = crate::BitReader; +pub type INT81_R = crate::BitReader; #[doc = "Field `INT81` writer - Interrupt 81"] -pub type INT81_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT81_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT82` reader - Interrupt 82"] -pub type INT82_R = crate::BitReader; +pub type INT82_R = crate::BitReader; #[doc = "Field `INT82` writer - Interrupt 82"] -pub type INT82_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT82_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT83` reader - Interrupt 83"] -pub type INT83_R = crate::BitReader; +pub type INT83_R = crate::BitReader; #[doc = "Field `INT83` writer - Interrupt 83"] -pub type INT83_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT83_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT84` reader - Interrupt 84"] -pub type INT84_R = crate::BitReader; +pub type INT84_R = crate::BitReader; #[doc = "Field `INT84` writer - Interrupt 84"] -pub type INT84_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT84_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT85` reader - Interrupt 85"] -pub type INT85_R = crate::BitReader; +pub type INT85_R = crate::BitReader; #[doc = "Field `INT85` writer - Interrupt 85"] -pub type INT85_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT85_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT86` reader - Interrupt 86"] -pub type INT86_R = crate::BitReader; +pub type INT86_R = crate::BitReader; #[doc = "Field `INT86` writer - Interrupt 86"] -pub type INT86_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT86_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT87` reader - Interrupt 87"] -pub type INT87_R = crate::BitReader; +pub type INT87_R = crate::BitReader; #[doc = "Field `INT87` writer - Interrupt 87"] -pub type INT87_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT87_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT88` reader - Interrupt 88"] -pub type INT88_R = crate::BitReader; +pub type INT88_R = crate::BitReader; #[doc = "Field `INT88` writer - Interrupt 88"] -pub type INT88_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT88_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT89` reader - Interrupt 89"] -pub type INT89_R = crate::BitReader; +pub type INT89_R = crate::BitReader; #[doc = "Field `INT89` writer - Interrupt 89"] -pub type INT89_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT89_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT90` reader - Interrupt 90"] -pub type INT90_R = crate::BitReader; +pub type INT90_R = crate::BitReader; #[doc = "Field `INT90` writer - Interrupt 90"] -pub type INT90_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT90_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT91` reader - Interrupt 91"] -pub type INT91_R = crate::BitReader; +pub type INT91_R = crate::BitReader; #[doc = "Field `INT91` writer - Interrupt 91"] -pub type INT91_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT91_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT92` reader - Interrupt 92"] -pub type INT92_R = crate::BitReader; +pub type INT92_R = crate::BitReader; #[doc = "Field `INT92` writer - Interrupt 92"] -pub type INT92_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT92_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT93` reader - Interrupt 93"] -pub type INT93_R = crate::BitReader; +pub type INT93_R = crate::BitReader; #[doc = "Field `INT93` writer - Interrupt 93"] -pub type INT93_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT93_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT94` reader - Interrupt 94"] -pub type INT94_R = crate::BitReader; +pub type INT94_R = crate::BitReader; #[doc = "Field `INT94` writer - Interrupt 94"] -pub type INT94_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT94_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT95` reader - Interrupt 95"] -pub type INT95_R = crate::BitReader; +pub type INT95_R = crate::BitReader; #[doc = "Field `INT95` writer - Interrupt 95"] -pub type INT95_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR2_SPEC, bool, O>; +pub type INT95_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -326,218 +292,268 @@ impl R { INT95_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISPENDR2") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .field("swi0", &format_args!("{}", self.swi0().bit())) + .field("swi1", &format_args!("{}", self.swi1().bit())) + .field("swi2", &format_args!("{}", self.swi2().bit())) + .field("swi3", &format_args!("{}", self.swi3().bit())) + .field("swi4", &format_args!("{}", self.swi4().bit())) + .field("swi5", &format_args!("{}", self.swi5().bit())) + .field("swi6", &format_args!("{}", self.swi6().bit())) + .field("swi7", &format_args!("{}", self.swi7().bit())) + .field("int80", &format_args!("{}", self.int80().bit())) + .field("int81", &format_args!("{}", self.int81().bit())) + .field("int82", &format_args!("{}", self.int82().bit())) + .field("int83", &format_args!("{}", self.int83().bit())) + .field("int84", &format_args!("{}", self.int84().bit())) + .field("int85", &format_args!("{}", self.int85().bit())) + .field("int86", &format_args!("{}", self.int86().bit())) + .field("int87", &format_args!("{}", self.int87().bit())) + .field("int88", &format_args!("{}", self.int88().bit())) + .field("int89", &format_args!("{}", self.int89().bit())) + .field("int90", &format_args!("{}", self.int90().bit())) + .field("int91", &format_args!("{}", self.int91().bit())) + .field("int92", &format_args!("{}", self.int92().bit())) + .field("int93", &format_args!("{}", self.int93().bit())) + .field("int94", &format_args!("{}", self.int94().bit())) + .field("int95", &format_args!("{}", self.int95().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } #[doc = "Bit 8 - Software interrupt 0"] #[inline(always)] #[must_use] - pub fn swi0(&mut self) -> SWI0_W<8> { + pub fn swi0(&mut self) -> SWI0_W { SWI0_W::new(self) } #[doc = "Bit 9 - Software interrupt 1"] #[inline(always)] #[must_use] - pub fn swi1(&mut self) -> SWI1_W<9> { + pub fn swi1(&mut self) -> SWI1_W { SWI1_W::new(self) } #[doc = "Bit 10 - Software interrupt 2"] #[inline(always)] #[must_use] - pub fn swi2(&mut self) -> SWI2_W<10> { + pub fn swi2(&mut self) -> SWI2_W { SWI2_W::new(self) } #[doc = "Bit 11 - Software interrupt 3"] #[inline(always)] #[must_use] - pub fn swi3(&mut self) -> SWI3_W<11> { + pub fn swi3(&mut self) -> SWI3_W { SWI3_W::new(self) } #[doc = "Bit 12 - Software interrupt 4"] #[inline(always)] #[must_use] - pub fn swi4(&mut self) -> SWI4_W<12> { + pub fn swi4(&mut self) -> SWI4_W { SWI4_W::new(self) } #[doc = "Bit 13 - Software interrupt 5"] #[inline(always)] #[must_use] - pub fn swi5(&mut self) -> SWI5_W<13> { + pub fn swi5(&mut self) -> SWI5_W { SWI5_W::new(self) } #[doc = "Bit 14 - Software interrupt 6"] #[inline(always)] #[must_use] - pub fn swi6(&mut self) -> SWI6_W<14> { + pub fn swi6(&mut self) -> SWI6_W { SWI6_W::new(self) } #[doc = "Bit 15 - Software interrupt 7"] #[inline(always)] #[must_use] - pub fn swi7(&mut self) -> SWI7_W<15> { + pub fn swi7(&mut self) -> SWI7_W { SWI7_W::new(self) } #[doc = "Bit 16 - Interrupt 80"] #[inline(always)] #[must_use] - pub fn int80(&mut self) -> INT80_W<16> { + pub fn int80(&mut self) -> INT80_W { INT80_W::new(self) } #[doc = "Bit 17 - Interrupt 81"] #[inline(always)] #[must_use] - pub fn int81(&mut self) -> INT81_W<17> { + pub fn int81(&mut self) -> INT81_W { INT81_W::new(self) } #[doc = "Bit 18 - Interrupt 82"] #[inline(always)] #[must_use] - pub fn int82(&mut self) -> INT82_W<18> { + pub fn int82(&mut self) -> INT82_W { INT82_W::new(self) } #[doc = "Bit 19 - Interrupt 83"] #[inline(always)] #[must_use] - pub fn int83(&mut self) -> INT83_W<19> { + pub fn int83(&mut self) -> INT83_W { INT83_W::new(self) } #[doc = "Bit 20 - Interrupt 84"] #[inline(always)] #[must_use] - pub fn int84(&mut self) -> INT84_W<20> { + pub fn int84(&mut self) -> INT84_W { INT84_W::new(self) } #[doc = "Bit 21 - Interrupt 85"] #[inline(always)] #[must_use] - pub fn int85(&mut self) -> INT85_W<21> { + pub fn int85(&mut self) -> INT85_W { INT85_W::new(self) } #[doc = "Bit 22 - Interrupt 86"] #[inline(always)] #[must_use] - pub fn int86(&mut self) -> INT86_W<22> { + pub fn int86(&mut self) -> INT86_W { INT86_W::new(self) } #[doc = "Bit 23 - Interrupt 87"] #[inline(always)] #[must_use] - pub fn int87(&mut self) -> INT87_W<23> { + pub fn int87(&mut self) -> INT87_W { INT87_W::new(self) } #[doc = "Bit 24 - Interrupt 88"] #[inline(always)] #[must_use] - pub fn int88(&mut self) -> INT88_W<24> { + pub fn int88(&mut self) -> INT88_W { INT88_W::new(self) } #[doc = "Bit 25 - Interrupt 89"] #[inline(always)] #[must_use] - pub fn int89(&mut self) -> INT89_W<25> { + pub fn int89(&mut self) -> INT89_W { INT89_W::new(self) } #[doc = "Bit 26 - Interrupt 90"] #[inline(always)] #[must_use] - pub fn int90(&mut self) -> INT90_W<26> { + pub fn int90(&mut self) -> INT90_W { INT90_W::new(self) } #[doc = "Bit 27 - Interrupt 91"] #[inline(always)] #[must_use] - pub fn int91(&mut self) -> INT91_W<27> { + pub fn int91(&mut self) -> INT91_W { INT91_W::new(self) } #[doc = "Bit 28 - Interrupt 92"] #[inline(always)] #[must_use] - pub fn int92(&mut self) -> INT92_W<28> { + pub fn int92(&mut self) -> INT92_W { INT92_W::new(self) } #[doc = "Bit 29 - Interrupt 93"] #[inline(always)] #[must_use] - pub fn int93(&mut self) -> INT93_W<29> { + pub fn int93(&mut self) -> INT93_W { INT93_W::new(self) } #[doc = "Bit 30 - Interrupt 94"] #[inline(always)] #[must_use] - pub fn int94(&mut self) -> INT94_W<30> { + pub fn int94(&mut self) -> INT94_W { INT94_W::new(self) } #[doc = "Bit 31 - Interrupt 95"] #[inline(always)] #[must_use] - pub fn int95(&mut self) -> INT95_W<31> { + pub fn int95(&mut self) -> INT95_W { INT95_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr2](index.html) module"] +#[doc = "Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISPENDR2_SPEC; impl crate::RegisterSpec for GICD_ISPENDR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ispendr2::R](R) reader structure"] -impl crate::Readable for GICD_ISPENDR2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ispendr2::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ispendr2::R`](R) reader structure"] +impl crate::Readable for GICD_ISPENDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ispendr2::W`](W) writer structure"] impl crate::Writable for GICD_ISPENDR2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr3.rs index 57a445c..f739a4a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr3.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr3.rs @@ -1,171 +1,135 @@ #[doc = "Register `GICD_ISPENDR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISPENDR3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR3_SPEC, bool, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -328,218 +292,274 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISPENDR3") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bit 1 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<1> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bit 2 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<2> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bit 3 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<3> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } #[doc = "Bit 4 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<4> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bit 5 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<5> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bit 6 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<6> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bit 7 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<7> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } #[doc = "Bit 8 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<8> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bit 9 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<9> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 10 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<10> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bit 11 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } #[doc = "Bit 12 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bit 13 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bit 14 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bit 15 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } #[doc = "Bit 16 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<16> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bit 17 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<17> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 18 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<18> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 19 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<19> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 20 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<20> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 21 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<21> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 22 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<22> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 23 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } #[doc = "Bit 24 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bit 25 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<25> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bit 26 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<26> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bit 27 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<27> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } #[doc = "Bit 28 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<28> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<29> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bit 30 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<30> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bit 31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<31> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr3](index.html) module"] +#[doc = "Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISPENDR3_SPEC; impl crate::RegisterSpec for GICD_ISPENDR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ispendr3::R](R) reader structure"] -impl crate::Readable for GICD_ISPENDR3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ispendr3::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ispendr3::R`](R) reader structure"] +impl crate::Readable for GICD_ISPENDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ispendr3::W`](W) writer structure"] impl crate::Writable for GICD_ISPENDR3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr4.rs index bd4613e..5c84121 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr4.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr4.rs @@ -1,173 +1,135 @@ #[doc = "Register `GICD_ISPENDR4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISPENDR4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type UART_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, GICD_ISPENDR4_SPEC, bool, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -330,218 +292,280 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISPENDR4") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bit 1 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<1> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bit 2 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<2> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bit 3 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<3> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } #[doc = "Bit 4 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<4> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bit 5 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bit 6 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bit 7 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } #[doc = "Bit 8 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bit 9 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bit 10 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bit 11 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } #[doc = "Bit 12 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<12> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bit 13 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bit 15 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<15> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } #[doc = "Bit 16 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<16> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bit 17 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bit 18 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bit 19 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } #[doc = "Bit 20 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bit 21 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<21> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bit 22 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<22> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bit 23 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } #[doc = "Bit 24 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<24> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bit 25 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<25> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bit 26 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bit 27 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<27> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } #[doc = "Bit 28 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<28> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bit 29 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<29> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bit 30 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<30> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bit 31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr4](index.html) module"] +#[doc = "Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISPENDR4_SPEC; impl crate::RegisterSpec for GICD_ISPENDR4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ispendr4::R](R) reader structure"] -impl crate::Readable for GICD_ISPENDR4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ispendr4::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ispendr4::R`](R) reader structure"] +impl crate::Readable for GICD_ISPENDR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ispendr4::W`](W) writer structure"] impl crate::Writable for GICD_ISPENDR4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr5.rs index 09a9a25..d8ca879 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr5.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr5.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ISPENDR5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISPENDR5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT160` reader - Interrupt 160"] -pub type INT160_R = crate::BitReader; +pub type INT160_R = crate::BitReader; #[doc = "Field `INT160` writer - Interrupt 160"] -pub type INT160_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT160_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT161` reader - Interrupt 161"] -pub type INT161_R = crate::BitReader; +pub type INT161_R = crate::BitReader; #[doc = "Field `INT161` writer - Interrupt 161"] -pub type INT161_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT161_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT162` reader - Interrupt 162"] -pub type INT162_R = crate::BitReader; +pub type INT162_R = crate::BitReader; #[doc = "Field `INT162` writer - Interrupt 162"] -pub type INT162_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT162_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT163` reader - Interrupt 163"] -pub type INT163_R = crate::BitReader; +pub type INT163_R = crate::BitReader; #[doc = "Field `INT163` writer - Interrupt 163"] -pub type INT163_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT163_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT164` reader - Interrupt 164"] -pub type INT164_R = crate::BitReader; +pub type INT164_R = crate::BitReader; #[doc = "Field `INT164` writer - Interrupt 164"] -pub type INT164_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT164_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT165` reader - Interrupt 165"] -pub type INT165_R = crate::BitReader; +pub type INT165_R = crate::BitReader; #[doc = "Field `INT165` writer - Interrupt 165"] -pub type INT165_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT165_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT166` reader - Interrupt 166"] -pub type INT166_R = crate::BitReader; +pub type INT166_R = crate::BitReader; #[doc = "Field `INT166` writer - Interrupt 166"] -pub type INT166_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT166_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT167` reader - Interrupt 167"] -pub type INT167_R = crate::BitReader; +pub type INT167_R = crate::BitReader; #[doc = "Field `INT167` writer - Interrupt 167"] -pub type INT167_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT167_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT168` reader - Interrupt 168"] -pub type INT168_R = crate::BitReader; +pub type INT168_R = crate::BitReader; #[doc = "Field `INT168` writer - Interrupt 168"] -pub type INT168_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT168_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT169` reader - Interrupt 169"] -pub type INT169_R = crate::BitReader; +pub type INT169_R = crate::BitReader; #[doc = "Field `INT169` writer - Interrupt 169"] -pub type INT169_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT169_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT170` reader - Interrupt 170"] -pub type INT170_R = crate::BitReader; +pub type INT170_R = crate::BitReader; #[doc = "Field `INT170` writer - Interrupt 170"] -pub type INT170_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT170_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT171` reader - Interrupt 171"] -pub type INT171_R = crate::BitReader; +pub type INT171_R = crate::BitReader; #[doc = "Field `INT171` writer - Interrupt 171"] -pub type INT171_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT171_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT172` reader - Interrupt 172"] -pub type INT172_R = crate::BitReader; +pub type INT172_R = crate::BitReader; #[doc = "Field `INT172` writer - Interrupt 172"] -pub type INT172_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT172_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT173` reader - Interrupt 173"] -pub type INT173_R = crate::BitReader; +pub type INT173_R = crate::BitReader; #[doc = "Field `INT173` writer - Interrupt 173"] -pub type INT173_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT173_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT174` reader - Interrupt 174"] -pub type INT174_R = crate::BitReader; +pub type INT174_R = crate::BitReader; #[doc = "Field `INT174` writer - Interrupt 174"] -pub type INT174_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT174_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT175` reader - Interrupt 175"] -pub type INT175_R = crate::BitReader; +pub type INT175_R = crate::BitReader; #[doc = "Field `INT175` writer - Interrupt 175"] -pub type INT175_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT175_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT176` reader - Interrupt 176"] -pub type INT176_R = crate::BitReader; +pub type INT176_R = crate::BitReader; #[doc = "Field `INT176` writer - Interrupt 176"] -pub type INT176_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT176_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT177` reader - Interrupt 177"] -pub type INT177_R = crate::BitReader; +pub type INT177_R = crate::BitReader; #[doc = "Field `INT177` writer - Interrupt 177"] -pub type INT177_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT177_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT178` reader - Interrupt 178"] -pub type INT178_R = crate::BitReader; +pub type INT178_R = crate::BitReader; #[doc = "Field `INT178` writer - Interrupt 178"] -pub type INT178_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT178_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT179` reader - Interrupt 179"] -pub type INT179_R = crate::BitReader; +pub type INT179_R = crate::BitReader; #[doc = "Field `INT179` writer - Interrupt 179"] -pub type INT179_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT179_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT180` reader - Interrupt 180"] -pub type INT180_R = crate::BitReader; +pub type INT180_R = crate::BitReader; #[doc = "Field `INT180` writer - Interrupt 180"] -pub type INT180_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT180_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT181` reader - Interrupt 181"] -pub type INT181_R = crate::BitReader; +pub type INT181_R = crate::BitReader; #[doc = "Field `INT181` writer - Interrupt 181"] -pub type INT181_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT181_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT182` reader - Interrupt 182"] -pub type INT182_R = crate::BitReader; +pub type INT182_R = crate::BitReader; #[doc = "Field `INT182` writer - Interrupt 182"] -pub type INT182_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT182_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT183` reader - Interrupt 183"] -pub type INT183_R = crate::BitReader; +pub type INT183_R = crate::BitReader; #[doc = "Field `INT183` writer - Interrupt 183"] -pub type INT183_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT183_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT184` reader - Interrupt 184"] -pub type INT184_R = crate::BitReader; +pub type INT184_R = crate::BitReader; #[doc = "Field `INT184` writer - Interrupt 184"] -pub type INT184_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT184_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT185` reader - Interrupt 185"] -pub type INT185_R = crate::BitReader; +pub type INT185_R = crate::BitReader; #[doc = "Field `INT185` writer - Interrupt 185"] -pub type INT185_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT185_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT186` reader - Interrupt 186"] -pub type INT186_R = crate::BitReader; +pub type INT186_R = crate::BitReader; #[doc = "Field `INT186` writer - Interrupt 186"] -pub type INT186_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT186_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT187` reader - Interrupt 187"] -pub type INT187_R = crate::BitReader; +pub type INT187_R = crate::BitReader; #[doc = "Field `INT187` writer - Interrupt 187"] -pub type INT187_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT187_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT188` reader - Interrupt 188"] -pub type INT188_R = crate::BitReader; +pub type INT188_R = crate::BitReader; #[doc = "Field `INT188` writer - Interrupt 188"] -pub type INT188_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT188_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT189` reader - Interrupt 189"] -pub type INT189_R = crate::BitReader; +pub type INT189_R = crate::BitReader; #[doc = "Field `INT189` writer - Interrupt 189"] -pub type INT189_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT189_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT190` reader - Interrupt 190"] -pub type INT190_R = crate::BitReader; +pub type INT190_R = crate::BitReader; #[doc = "Field `INT190` writer - Interrupt 190"] -pub type INT190_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT190_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT191` reader - Interrupt 191"] -pub type INT191_R = crate::BitReader; +pub type INT191_R = crate::BitReader; #[doc = "Field `INT191` writer - Interrupt 191"] -pub type INT191_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR5_SPEC, bool, O>; +pub type INT191_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT191_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISPENDR5") + .field("int160", &format_args!("{}", self.int160().bit())) + .field("int161", &format_args!("{}", self.int161().bit())) + .field("int162", &format_args!("{}", self.int162().bit())) + .field("int163", &format_args!("{}", self.int163().bit())) + .field("int164", &format_args!("{}", self.int164().bit())) + .field("int165", &format_args!("{}", self.int165().bit())) + .field("int166", &format_args!("{}", self.int166().bit())) + .field("int167", &format_args!("{}", self.int167().bit())) + .field("int168", &format_args!("{}", self.int168().bit())) + .field("int169", &format_args!("{}", self.int169().bit())) + .field("int170", &format_args!("{}", self.int170().bit())) + .field("int171", &format_args!("{}", self.int171().bit())) + .field("int172", &format_args!("{}", self.int172().bit())) + .field("int173", &format_args!("{}", self.int173().bit())) + .field("int174", &format_args!("{}", self.int174().bit())) + .field("int175", &format_args!("{}", self.int175().bit())) + .field("int176", &format_args!("{}", self.int176().bit())) + .field("int177", &format_args!("{}", self.int177().bit())) + .field("int178", &format_args!("{}", self.int178().bit())) + .field("int179", &format_args!("{}", self.int179().bit())) + .field("int180", &format_args!("{}", self.int180().bit())) + .field("int181", &format_args!("{}", self.int181().bit())) + .field("int182", &format_args!("{}", self.int182().bit())) + .field("int183", &format_args!("{}", self.int183().bit())) + .field("int184", &format_args!("{}", self.int184().bit())) + .field("int185", &format_args!("{}", self.int185().bit())) + .field("int186", &format_args!("{}", self.int186().bit())) + .field("int187", &format_args!("{}", self.int187().bit())) + .field("int188", &format_args!("{}", self.int188().bit())) + .field("int189", &format_args!("{}", self.int189().bit())) + .field("int190", &format_args!("{}", self.int190().bit())) + .field("int191", &format_args!("{}", self.int191().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 160"] #[inline(always)] #[must_use] - pub fn int160(&mut self) -> INT160_W<0> { + pub fn int160(&mut self) -> INT160_W { INT160_W::new(self) } #[doc = "Bit 1 - Interrupt 161"] #[inline(always)] #[must_use] - pub fn int161(&mut self) -> INT161_W<1> { + pub fn int161(&mut self) -> INT161_W { INT161_W::new(self) } #[doc = "Bit 2 - Interrupt 162"] #[inline(always)] #[must_use] - pub fn int162(&mut self) -> INT162_W<2> { + pub fn int162(&mut self) -> INT162_W { INT162_W::new(self) } #[doc = "Bit 3 - Interrupt 163"] #[inline(always)] #[must_use] - pub fn int163(&mut self) -> INT163_W<3> { + pub fn int163(&mut self) -> INT163_W { INT163_W::new(self) } #[doc = "Bit 4 - Interrupt 164"] #[inline(always)] #[must_use] - pub fn int164(&mut self) -> INT164_W<4> { + pub fn int164(&mut self) -> INT164_W { INT164_W::new(self) } #[doc = "Bit 5 - Interrupt 165"] #[inline(always)] #[must_use] - pub fn int165(&mut self) -> INT165_W<5> { + pub fn int165(&mut self) -> INT165_W { INT165_W::new(self) } #[doc = "Bit 6 - Interrupt 166"] #[inline(always)] #[must_use] - pub fn int166(&mut self) -> INT166_W<6> { + pub fn int166(&mut self) -> INT166_W { INT166_W::new(self) } #[doc = "Bit 7 - Interrupt 167"] #[inline(always)] #[must_use] - pub fn int167(&mut self) -> INT167_W<7> { + pub fn int167(&mut self) -> INT167_W { INT167_W::new(self) } #[doc = "Bit 8 - Interrupt 168"] #[inline(always)] #[must_use] - pub fn int168(&mut self) -> INT168_W<8> { + pub fn int168(&mut self) -> INT168_W { INT168_W::new(self) } #[doc = "Bit 9 - Interrupt 169"] #[inline(always)] #[must_use] - pub fn int169(&mut self) -> INT169_W<9> { + pub fn int169(&mut self) -> INT169_W { INT169_W::new(self) } #[doc = "Bit 10 - Interrupt 170"] #[inline(always)] #[must_use] - pub fn int170(&mut self) -> INT170_W<10> { + pub fn int170(&mut self) -> INT170_W { INT170_W::new(self) } #[doc = "Bit 11 - Interrupt 171"] #[inline(always)] #[must_use] - pub fn int171(&mut self) -> INT171_W<11> { + pub fn int171(&mut self) -> INT171_W { INT171_W::new(self) } #[doc = "Bit 12 - Interrupt 172"] #[inline(always)] #[must_use] - pub fn int172(&mut self) -> INT172_W<12> { + pub fn int172(&mut self) -> INT172_W { INT172_W::new(self) } #[doc = "Bit 13 - Interrupt 173"] #[inline(always)] #[must_use] - pub fn int173(&mut self) -> INT173_W<13> { + pub fn int173(&mut self) -> INT173_W { INT173_W::new(self) } #[doc = "Bit 14 - Interrupt 174"] #[inline(always)] #[must_use] - pub fn int174(&mut self) -> INT174_W<14> { + pub fn int174(&mut self) -> INT174_W { INT174_W::new(self) } #[doc = "Bit 15 - Interrupt 175"] #[inline(always)] #[must_use] - pub fn int175(&mut self) -> INT175_W<15> { + pub fn int175(&mut self) -> INT175_W { INT175_W::new(self) } #[doc = "Bit 16 - Interrupt 176"] #[inline(always)] #[must_use] - pub fn int176(&mut self) -> INT176_W<16> { + pub fn int176(&mut self) -> INT176_W { INT176_W::new(self) } #[doc = "Bit 17 - Interrupt 177"] #[inline(always)] #[must_use] - pub fn int177(&mut self) -> INT177_W<17> { + pub fn int177(&mut self) -> INT177_W { INT177_W::new(self) } #[doc = "Bit 18 - Interrupt 178"] #[inline(always)] #[must_use] - pub fn int178(&mut self) -> INT178_W<18> { + pub fn int178(&mut self) -> INT178_W { INT178_W::new(self) } #[doc = "Bit 19 - Interrupt 179"] #[inline(always)] #[must_use] - pub fn int179(&mut self) -> INT179_W<19> { + pub fn int179(&mut self) -> INT179_W { INT179_W::new(self) } #[doc = "Bit 20 - Interrupt 180"] #[inline(always)] #[must_use] - pub fn int180(&mut self) -> INT180_W<20> { + pub fn int180(&mut self) -> INT180_W { INT180_W::new(self) } #[doc = "Bit 21 - Interrupt 181"] #[inline(always)] #[must_use] - pub fn int181(&mut self) -> INT181_W<21> { + pub fn int181(&mut self) -> INT181_W { INT181_W::new(self) } #[doc = "Bit 22 - Interrupt 182"] #[inline(always)] #[must_use] - pub fn int182(&mut self) -> INT182_W<22> { + pub fn int182(&mut self) -> INT182_W { INT182_W::new(self) } #[doc = "Bit 23 - Interrupt 183"] #[inline(always)] #[must_use] - pub fn int183(&mut self) -> INT183_W<23> { + pub fn int183(&mut self) -> INT183_W { INT183_W::new(self) } #[doc = "Bit 24 - Interrupt 184"] #[inline(always)] #[must_use] - pub fn int184(&mut self) -> INT184_W<24> { + pub fn int184(&mut self) -> INT184_W { INT184_W::new(self) } #[doc = "Bit 25 - Interrupt 185"] #[inline(always)] #[must_use] - pub fn int185(&mut self) -> INT185_W<25> { + pub fn int185(&mut self) -> INT185_W { INT185_W::new(self) } #[doc = "Bit 26 - Interrupt 186"] #[inline(always)] #[must_use] - pub fn int186(&mut self) -> INT186_W<26> { + pub fn int186(&mut self) -> INT186_W { INT186_W::new(self) } #[doc = "Bit 27 - Interrupt 187"] #[inline(always)] #[must_use] - pub fn int187(&mut self) -> INT187_W<27> { + pub fn int187(&mut self) -> INT187_W { INT187_W::new(self) } #[doc = "Bit 28 - Interrupt 188"] #[inline(always)] #[must_use] - pub fn int188(&mut self) -> INT188_W<28> { + pub fn int188(&mut self) -> INT188_W { INT188_W::new(self) } #[doc = "Bit 29 - Interrupt 189"] #[inline(always)] #[must_use] - pub fn int189(&mut self) -> INT189_W<29> { + pub fn int189(&mut self) -> INT189_W { INT189_W::new(self) } #[doc = "Bit 30 - Interrupt 190"] #[inline(always)] #[must_use] - pub fn int190(&mut self) -> INT190_W<30> { + pub fn int190(&mut self) -> INT190_W { INT190_W::new(self) } #[doc = "Bit 31 - Interrupt 191"] #[inline(always)] #[must_use] - pub fn int191(&mut self) -> INT191_W<31> { + pub fn int191(&mut self) -> INT191_W { INT191_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr5](index.html) module"] +#[doc = "Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISPENDR5_SPEC; impl crate::RegisterSpec for GICD_ISPENDR5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ispendr5::R](R) reader structure"] -impl crate::Readable for GICD_ISPENDR5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ispendr5::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ispendr5::R`](R) reader structure"] +impl crate::Readable for GICD_ISPENDR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ispendr5::W`](W) writer structure"] impl crate::Writable for GICD_ISPENDR5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr6.rs index 61d1a24..56da067 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr6.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ispendr/gicd_ispendr6.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_ISPENDR6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ISPENDR6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT192` reader - Interrupt 192"] -pub type INT192_R = crate::BitReader; +pub type INT192_R = crate::BitReader; #[doc = "Field `INT192` writer - Interrupt 192"] -pub type INT192_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT192_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT193` reader - Interrupt 193"] -pub type INT193_R = crate::BitReader; +pub type INT193_R = crate::BitReader; #[doc = "Field `INT193` writer - Interrupt 193"] -pub type INT193_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT193_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT194` reader - Interrupt 194"] -pub type INT194_R = crate::BitReader; +pub type INT194_R = crate::BitReader; #[doc = "Field `INT194` writer - Interrupt 194"] -pub type INT194_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT194_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT195` reader - Interrupt 195"] -pub type INT195_R = crate::BitReader; +pub type INT195_R = crate::BitReader; #[doc = "Field `INT195` writer - Interrupt 195"] -pub type INT195_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT195_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT196` reader - Interrupt 196"] -pub type INT196_R = crate::BitReader; +pub type INT196_R = crate::BitReader; #[doc = "Field `INT196` writer - Interrupt 196"] -pub type INT196_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT196_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT197` reader - Interrupt 197"] -pub type INT197_R = crate::BitReader; +pub type INT197_R = crate::BitReader; #[doc = "Field `INT197` writer - Interrupt 197"] -pub type INT197_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT197_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT198` reader - Interrupt 198"] -pub type INT198_R = crate::BitReader; +pub type INT198_R = crate::BitReader; #[doc = "Field `INT198` writer - Interrupt 198"] -pub type INT198_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT198_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT199` reader - Interrupt 199"] -pub type INT199_R = crate::BitReader; +pub type INT199_R = crate::BitReader; #[doc = "Field `INT199` writer - Interrupt 199"] -pub type INT199_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT199_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT200` reader - Interrupt 200"] -pub type INT200_R = crate::BitReader; +pub type INT200_R = crate::BitReader; #[doc = "Field `INT200` writer - Interrupt 200"] -pub type INT200_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT200_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT201` reader - Interrupt 201"] -pub type INT201_R = crate::BitReader; +pub type INT201_R = crate::BitReader; #[doc = "Field `INT201` writer - Interrupt 201"] -pub type INT201_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT201_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT202` reader - Interrupt 202"] -pub type INT202_R = crate::BitReader; +pub type INT202_R = crate::BitReader; #[doc = "Field `INT202` writer - Interrupt 202"] -pub type INT202_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT202_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT203` reader - Interrupt 203"] -pub type INT203_R = crate::BitReader; +pub type INT203_R = crate::BitReader; #[doc = "Field `INT203` writer - Interrupt 203"] -pub type INT203_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT203_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT204` reader - Interrupt 204"] -pub type INT204_R = crate::BitReader; +pub type INT204_R = crate::BitReader; #[doc = "Field `INT204` writer - Interrupt 204"] -pub type INT204_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT204_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT205` reader - Interrupt 205"] -pub type INT205_R = crate::BitReader; +pub type INT205_R = crate::BitReader; #[doc = "Field `INT205` writer - Interrupt 205"] -pub type INT205_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT205_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT206` reader - Interrupt 206"] -pub type INT206_R = crate::BitReader; +pub type INT206_R = crate::BitReader; #[doc = "Field `INT206` writer - Interrupt 206"] -pub type INT206_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT206_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT207` reader - Interrupt 207"] -pub type INT207_R = crate::BitReader; +pub type INT207_R = crate::BitReader; #[doc = "Field `INT207` writer - Interrupt 207"] -pub type INT207_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT207_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT208` reader - Interrupt 208"] -pub type INT208_R = crate::BitReader; +pub type INT208_R = crate::BitReader; #[doc = "Field `INT208` writer - Interrupt 208"] -pub type INT208_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT208_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT209` reader - Interrupt 209"] -pub type INT209_R = crate::BitReader; +pub type INT209_R = crate::BitReader; #[doc = "Field `INT209` writer - Interrupt 209"] -pub type INT209_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT209_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT210` reader - Interrupt 210"] -pub type INT210_R = crate::BitReader; +pub type INT210_R = crate::BitReader; #[doc = "Field `INT210` writer - Interrupt 210"] -pub type INT210_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT210_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT211` reader - Interrupt 211"] -pub type INT211_R = crate::BitReader; +pub type INT211_R = crate::BitReader; #[doc = "Field `INT211` writer - Interrupt 211"] -pub type INT211_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT211_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT212` reader - Interrupt 212"] -pub type INT212_R = crate::BitReader; +pub type INT212_R = crate::BitReader; #[doc = "Field `INT212` writer - Interrupt 212"] -pub type INT212_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT212_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT213` reader - Interrupt 213"] -pub type INT213_R = crate::BitReader; +pub type INT213_R = crate::BitReader; #[doc = "Field `INT213` writer - Interrupt 213"] -pub type INT213_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT213_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT214` reader - Interrupt 214"] -pub type INT214_R = crate::BitReader; +pub type INT214_R = crate::BitReader; #[doc = "Field `INT214` writer - Interrupt 214"] -pub type INT214_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT214_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT215` reader - Interrupt 215"] -pub type INT215_R = crate::BitReader; +pub type INT215_R = crate::BitReader; #[doc = "Field `INT215` writer - Interrupt 215"] -pub type INT215_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT215_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT216` reader - Interrupt 216"] -pub type INT216_R = crate::BitReader; +pub type INT216_R = crate::BitReader; #[doc = "Field `INT216` writer - Interrupt 216"] -pub type INT216_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT216_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT217` reader - Interrupt 217"] -pub type INT217_R = crate::BitReader; +pub type INT217_R = crate::BitReader; #[doc = "Field `INT217` writer - Interrupt 217"] -pub type INT217_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT217_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT218` reader - Interrupt 218"] -pub type INT218_R = crate::BitReader; +pub type INT218_R = crate::BitReader; #[doc = "Field `INT218` writer - Interrupt 218"] -pub type INT218_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT218_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT219` reader - Interrupt 219"] -pub type INT219_R = crate::BitReader; +pub type INT219_R = crate::BitReader; #[doc = "Field `INT219` writer - Interrupt 219"] -pub type INT219_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT219_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT220` reader - Interrupt 220"] -pub type INT220_R = crate::BitReader; +pub type INT220_R = crate::BitReader; #[doc = "Field `INT220` writer - Interrupt 220"] -pub type INT220_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT220_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT221` reader - Interrupt 221"] -pub type INT221_R = crate::BitReader; +pub type INT221_R = crate::BitReader; #[doc = "Field `INT221` writer - Interrupt 221"] -pub type INT221_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT221_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT222` reader - Interrupt 222"] -pub type INT222_R = crate::BitReader; +pub type INT222_R = crate::BitReader; #[doc = "Field `INT222` writer - Interrupt 222"] -pub type INT222_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT222_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT223` reader - Interrupt 223"] -pub type INT223_R = crate::BitReader; +pub type INT223_R = crate::BitReader; #[doc = "Field `INT223` writer - Interrupt 223"] -pub type INT223_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GICD_ISPENDR6_SPEC, bool, O>; +pub type INT223_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT223_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ISPENDR6") + .field("int192", &format_args!("{}", self.int192().bit())) + .field("int193", &format_args!("{}", self.int193().bit())) + .field("int194", &format_args!("{}", self.int194().bit())) + .field("int195", &format_args!("{}", self.int195().bit())) + .field("int196", &format_args!("{}", self.int196().bit())) + .field("int197", &format_args!("{}", self.int197().bit())) + .field("int198", &format_args!("{}", self.int198().bit())) + .field("int199", &format_args!("{}", self.int199().bit())) + .field("int200", &format_args!("{}", self.int200().bit())) + .field("int201", &format_args!("{}", self.int201().bit())) + .field("int202", &format_args!("{}", self.int202().bit())) + .field("int203", &format_args!("{}", self.int203().bit())) + .field("int204", &format_args!("{}", self.int204().bit())) + .field("int205", &format_args!("{}", self.int205().bit())) + .field("int206", &format_args!("{}", self.int206().bit())) + .field("int207", &format_args!("{}", self.int207().bit())) + .field("int208", &format_args!("{}", self.int208().bit())) + .field("int209", &format_args!("{}", self.int209().bit())) + .field("int210", &format_args!("{}", self.int210().bit())) + .field("int211", &format_args!("{}", self.int211().bit())) + .field("int212", &format_args!("{}", self.int212().bit())) + .field("int213", &format_args!("{}", self.int213().bit())) + .field("int214", &format_args!("{}", self.int214().bit())) + .field("int215", &format_args!("{}", self.int215().bit())) + .field("int216", &format_args!("{}", self.int216().bit())) + .field("int217", &format_args!("{}", self.int217().bit())) + .field("int218", &format_args!("{}", self.int218().bit())) + .field("int219", &format_args!("{}", self.int219().bit())) + .field("int220", &format_args!("{}", self.int220().bit())) + .field("int221", &format_args!("{}", self.int221().bit())) + .field("int222", &format_args!("{}", self.int222().bit())) + .field("int223", &format_args!("{}", self.int223().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 192"] #[inline(always)] #[must_use] - pub fn int192(&mut self) -> INT192_W<0> { + pub fn int192(&mut self) -> INT192_W { INT192_W::new(self) } #[doc = "Bit 1 - Interrupt 193"] #[inline(always)] #[must_use] - pub fn int193(&mut self) -> INT193_W<1> { + pub fn int193(&mut self) -> INT193_W { INT193_W::new(self) } #[doc = "Bit 2 - Interrupt 194"] #[inline(always)] #[must_use] - pub fn int194(&mut self) -> INT194_W<2> { + pub fn int194(&mut self) -> INT194_W { INT194_W::new(self) } #[doc = "Bit 3 - Interrupt 195"] #[inline(always)] #[must_use] - pub fn int195(&mut self) -> INT195_W<3> { + pub fn int195(&mut self) -> INT195_W { INT195_W::new(self) } #[doc = "Bit 4 - Interrupt 196"] #[inline(always)] #[must_use] - pub fn int196(&mut self) -> INT196_W<4> { + pub fn int196(&mut self) -> INT196_W { INT196_W::new(self) } #[doc = "Bit 5 - Interrupt 197"] #[inline(always)] #[must_use] - pub fn int197(&mut self) -> INT197_W<5> { + pub fn int197(&mut self) -> INT197_W { INT197_W::new(self) } #[doc = "Bit 6 - Interrupt 198"] #[inline(always)] #[must_use] - pub fn int198(&mut self) -> INT198_W<6> { + pub fn int198(&mut self) -> INT198_W { INT198_W::new(self) } #[doc = "Bit 7 - Interrupt 199"] #[inline(always)] #[must_use] - pub fn int199(&mut self) -> INT199_W<7> { + pub fn int199(&mut self) -> INT199_W { INT199_W::new(self) } #[doc = "Bit 8 - Interrupt 200"] #[inline(always)] #[must_use] - pub fn int200(&mut self) -> INT200_W<8> { + pub fn int200(&mut self) -> INT200_W { INT200_W::new(self) } #[doc = "Bit 9 - Interrupt 201"] #[inline(always)] #[must_use] - pub fn int201(&mut self) -> INT201_W<9> { + pub fn int201(&mut self) -> INT201_W { INT201_W::new(self) } #[doc = "Bit 10 - Interrupt 202"] #[inline(always)] #[must_use] - pub fn int202(&mut self) -> INT202_W<10> { + pub fn int202(&mut self) -> INT202_W { INT202_W::new(self) } #[doc = "Bit 11 - Interrupt 203"] #[inline(always)] #[must_use] - pub fn int203(&mut self) -> INT203_W<11> { + pub fn int203(&mut self) -> INT203_W { INT203_W::new(self) } #[doc = "Bit 12 - Interrupt 204"] #[inline(always)] #[must_use] - pub fn int204(&mut self) -> INT204_W<12> { + pub fn int204(&mut self) -> INT204_W { INT204_W::new(self) } #[doc = "Bit 13 - Interrupt 205"] #[inline(always)] #[must_use] - pub fn int205(&mut self) -> INT205_W<13> { + pub fn int205(&mut self) -> INT205_W { INT205_W::new(self) } #[doc = "Bit 14 - Interrupt 206"] #[inline(always)] #[must_use] - pub fn int206(&mut self) -> INT206_W<14> { + pub fn int206(&mut self) -> INT206_W { INT206_W::new(self) } #[doc = "Bit 15 - Interrupt 207"] #[inline(always)] #[must_use] - pub fn int207(&mut self) -> INT207_W<15> { + pub fn int207(&mut self) -> INT207_W { INT207_W::new(self) } #[doc = "Bit 16 - Interrupt 208"] #[inline(always)] #[must_use] - pub fn int208(&mut self) -> INT208_W<16> { + pub fn int208(&mut self) -> INT208_W { INT208_W::new(self) } #[doc = "Bit 17 - Interrupt 209"] #[inline(always)] #[must_use] - pub fn int209(&mut self) -> INT209_W<17> { + pub fn int209(&mut self) -> INT209_W { INT209_W::new(self) } #[doc = "Bit 18 - Interrupt 210"] #[inline(always)] #[must_use] - pub fn int210(&mut self) -> INT210_W<18> { + pub fn int210(&mut self) -> INT210_W { INT210_W::new(self) } #[doc = "Bit 19 - Interrupt 211"] #[inline(always)] #[must_use] - pub fn int211(&mut self) -> INT211_W<19> { + pub fn int211(&mut self) -> INT211_W { INT211_W::new(self) } #[doc = "Bit 20 - Interrupt 212"] #[inline(always)] #[must_use] - pub fn int212(&mut self) -> INT212_W<20> { + pub fn int212(&mut self) -> INT212_W { INT212_W::new(self) } #[doc = "Bit 21 - Interrupt 213"] #[inline(always)] #[must_use] - pub fn int213(&mut self) -> INT213_W<21> { + pub fn int213(&mut self) -> INT213_W { INT213_W::new(self) } #[doc = "Bit 22 - Interrupt 214"] #[inline(always)] #[must_use] - pub fn int214(&mut self) -> INT214_W<22> { + pub fn int214(&mut self) -> INT214_W { INT214_W::new(self) } #[doc = "Bit 23 - Interrupt 215"] #[inline(always)] #[must_use] - pub fn int215(&mut self) -> INT215_W<23> { + pub fn int215(&mut self) -> INT215_W { INT215_W::new(self) } #[doc = "Bit 24 - Interrupt 216"] #[inline(always)] #[must_use] - pub fn int216(&mut self) -> INT216_W<24> { + pub fn int216(&mut self) -> INT216_W { INT216_W::new(self) } #[doc = "Bit 25 - Interrupt 217"] #[inline(always)] #[must_use] - pub fn int217(&mut self) -> INT217_W<25> { + pub fn int217(&mut self) -> INT217_W { INT217_W::new(self) } #[doc = "Bit 26 - Interrupt 218"] #[inline(always)] #[must_use] - pub fn int218(&mut self) -> INT218_W<26> { + pub fn int218(&mut self) -> INT218_W { INT218_W::new(self) } #[doc = "Bit 27 - Interrupt 219"] #[inline(always)] #[must_use] - pub fn int219(&mut self) -> INT219_W<27> { + pub fn int219(&mut self) -> INT219_W { INT219_W::new(self) } #[doc = "Bit 28 - Interrupt 220"] #[inline(always)] #[must_use] - pub fn int220(&mut self) -> INT220_W<28> { + pub fn int220(&mut self) -> INT220_W { INT220_W::new(self) } #[doc = "Bit 29 - Interrupt 221"] #[inline(always)] #[must_use] - pub fn int221(&mut self) -> INT221_W<29> { + pub fn int221(&mut self) -> INT221_W { INT221_W::new(self) } #[doc = "Bit 30 - Interrupt 222"] #[inline(always)] #[must_use] - pub fn int222(&mut self) -> INT222_W<30> { + pub fn int222(&mut self) -> INT222_W { INT222_W::new(self) } #[doc = "Bit 31 - Interrupt 223"] #[inline(always)] #[must_use] - pub fn int223(&mut self) -> INT223_W<31> { + pub fn int223(&mut self) -> INT223_W { INT223_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Set-Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ispendr6](index.html) module"] +#[doc = "Interrupt Set-Pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ispendr6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ispendr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ISPENDR6_SPEC; impl crate::RegisterSpec for GICD_ISPENDR6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ispendr6::R](R) reader structure"] -impl crate::Readable for GICD_ISPENDR6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ispendr6::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ispendr6::R`](R) reader structure"] +impl crate::Readable for GICD_ISPENDR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ispendr6::W`](W) writer structure"] impl crate::Writable for GICD_ISPENDR6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr.rs index 22fe1fe..f4550d4 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct GICD_ITARGETSR { #[doc = "0x00 - Interrupt Processor Target 0 - 3"] pub gicd_itargetsr0: GICD_ITARGETSR0, @@ -114,227 +115,283 @@ pub struct GICD_ITARGETSR { #[doc = "0xdc - Interrupt Processor Target 220 - 223"] pub gicd_itargetsr55: GICD_ITARGETSR55, } -#[doc = "GICD_ITARGETSR0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR0 (rw) register accessor: Interrupt Processor Target 0 - 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr0`] +module"] pub type GICD_ITARGETSR0 = crate::Reg; #[doc = "Interrupt Processor Target 0 - 3"] pub mod gicd_itargetsr0; -#[doc = "GICD_ITARGETSR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR1 (rw) register accessor: Interrupt Processor Target 4 - 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr1`] +module"] pub type GICD_ITARGETSR1 = crate::Reg; #[doc = "Interrupt Processor Target 4 - 7"] pub mod gicd_itargetsr1; -#[doc = "GICD_ITARGETSR2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR2 (rw) register accessor: Interrupt Processor Target 8 - 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr2`] +module"] pub type GICD_ITARGETSR2 = crate::Reg; #[doc = "Interrupt Processor Target 8 - 11"] pub mod gicd_itargetsr2; -#[doc = "GICD_ITARGETSR3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR3 (rw) register accessor: Interrupt Processor Target 12 - 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr3`] +module"] pub type GICD_ITARGETSR3 = crate::Reg; #[doc = "Interrupt Processor Target 12 - 15"] pub mod gicd_itargetsr3; -#[doc = "GICD_ITARGETSR4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR4 (rw) register accessor: Interrupt Processor Target 16 - 19\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr4`] +module"] pub type GICD_ITARGETSR4 = crate::Reg; #[doc = "Interrupt Processor Target 16 - 19"] pub mod gicd_itargetsr4; -#[doc = "GICD_ITARGETSR5 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR5 (rw) register accessor: Interrupt Processor Target 20 - 23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr5`] +module"] pub type GICD_ITARGETSR5 = crate::Reg; #[doc = "Interrupt Processor Target 20 - 23"] pub mod gicd_itargetsr5; -#[doc = "GICD_ITARGETSR6 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR6 (rw) register accessor: Interrupt Processor Target 24 - 27\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr6`] +module"] pub type GICD_ITARGETSR6 = crate::Reg; #[doc = "Interrupt Processor Target 24 - 27"] pub mod gicd_itargetsr6; -#[doc = "GICD_ITARGETSR7 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR7 (rw) register accessor: Interrupt Processor Target 28 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr7`] +module"] pub type GICD_ITARGETSR7 = crate::Reg; #[doc = "Interrupt Processor Target 28 - 31"] pub mod gicd_itargetsr7; -#[doc = "GICD_ITARGETSR8 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR8 (rw) register accessor: Interrupt Processor Target 32 - 35\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr8`] +module"] pub type GICD_ITARGETSR8 = crate::Reg; #[doc = "Interrupt Processor Target 32 - 35"] pub mod gicd_itargetsr8; -#[doc = "GICD_ITARGETSR9 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR9 (rw) register accessor: Interrupt Processor Target 36 - 39\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr9`] +module"] pub type GICD_ITARGETSR9 = crate::Reg; #[doc = "Interrupt Processor Target 36 - 39"] pub mod gicd_itargetsr9; -#[doc = "GICD_ITARGETSR10 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR10 (rw) register accessor: Interrupt Processor Target 40 - 43\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr10`] +module"] pub type GICD_ITARGETSR10 = crate::Reg; #[doc = "Interrupt Processor Target 40 - 43"] pub mod gicd_itargetsr10; -#[doc = "GICD_ITARGETSR11 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR11 (rw) register accessor: Interrupt Processor Target 44 - 47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr11`] +module"] pub type GICD_ITARGETSR11 = crate::Reg; #[doc = "Interrupt Processor Target 44 - 47"] pub mod gicd_itargetsr11; -#[doc = "GICD_ITARGETSR12 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR12 (rw) register accessor: Interrupt Processor Target 48 - 51\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr12`] +module"] pub type GICD_ITARGETSR12 = crate::Reg; #[doc = "Interrupt Processor Target 48 - 51"] pub mod gicd_itargetsr12; -#[doc = "GICD_ITARGETSR13 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR13 (rw) register accessor: Interrupt Processor Target 52 - 55\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr13`] +module"] pub type GICD_ITARGETSR13 = crate::Reg; #[doc = "Interrupt Processor Target 52 - 55"] pub mod gicd_itargetsr13; -#[doc = "GICD_ITARGETSR14 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR14 (rw) register accessor: Interrupt Processor Target 56 - 59\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr14`] +module"] pub type GICD_ITARGETSR14 = crate::Reg; #[doc = "Interrupt Processor Target 56 - 59"] pub mod gicd_itargetsr14; -#[doc = "GICD_ITARGETSR15 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR15 (rw) register accessor: Interrupt Processor Target 60 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr15`] +module"] pub type GICD_ITARGETSR15 = crate::Reg; #[doc = "Interrupt Processor Target 60 - 63"] pub mod gicd_itargetsr15; -#[doc = "GICD_ITARGETSR16 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR16 (rw) register accessor: Interrupt Processor Target 64 - 67\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr16`] +module"] pub type GICD_ITARGETSR16 = crate::Reg; #[doc = "Interrupt Processor Target 64 - 67"] pub mod gicd_itargetsr16; -#[doc = "GICD_ITARGETSR17 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR17 (rw) register accessor: Interrupt Processor Target 68 - 71\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr17::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr17::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr17`] +module"] pub type GICD_ITARGETSR17 = crate::Reg; #[doc = "Interrupt Processor Target 68 - 71"] pub mod gicd_itargetsr17; -#[doc = "GICD_ITARGETSR18 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR18 (rw) register accessor: Interrupt Processor Target 72 - 75\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr18::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr18::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr18`] +module"] pub type GICD_ITARGETSR18 = crate::Reg; #[doc = "Interrupt Processor Target 72 - 75"] pub mod gicd_itargetsr18; -#[doc = "GICD_ITARGETSR19 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR19 (rw) register accessor: Interrupt Processor Target 76 - 79\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr19::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr19`] +module"] pub type GICD_ITARGETSR19 = crate::Reg; #[doc = "Interrupt Processor Target 76 - 79"] pub mod gicd_itargetsr19; -#[doc = "GICD_ITARGETSR20 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR20 (rw) register accessor: Interrupt Processor Target 80 - 83\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr20`] +module"] pub type GICD_ITARGETSR20 = crate::Reg; #[doc = "Interrupt Processor Target 80 - 83"] pub mod gicd_itargetsr20; -#[doc = "GICD_ITARGETSR21 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR21 (rw) register accessor: Interrupt Processor Target 84 - 87\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr21::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr21::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr21`] +module"] pub type GICD_ITARGETSR21 = crate::Reg; #[doc = "Interrupt Processor Target 84 - 87"] pub mod gicd_itargetsr21; -#[doc = "GICD_ITARGETSR22 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR22 (rw) register accessor: Interrupt Processor Target 88 - 91\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr22::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr22::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr22`] +module"] pub type GICD_ITARGETSR22 = crate::Reg; #[doc = "Interrupt Processor Target 88 - 91"] pub mod gicd_itargetsr22; -#[doc = "GICD_ITARGETSR23 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR23 (rw) register accessor: Interrupt Processor Target 92 - 95\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr23::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr23`] +module"] pub type GICD_ITARGETSR23 = crate::Reg; #[doc = "Interrupt Processor Target 92 - 95"] pub mod gicd_itargetsr23; -#[doc = "GICD_ITARGETSR24 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR24 (rw) register accessor: Interrupt Processor Target 96 - 99\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr24`] +module"] pub type GICD_ITARGETSR24 = crate::Reg; #[doc = "Interrupt Processor Target 96 - 99"] pub mod gicd_itargetsr24; -#[doc = "GICD_ITARGETSR25 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR25 (rw) register accessor: Interrupt Processor Target 100 - 103\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr25::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr25::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr25`] +module"] pub type GICD_ITARGETSR25 = crate::Reg; #[doc = "Interrupt Processor Target 100 - 103"] pub mod gicd_itargetsr25; -#[doc = "GICD_ITARGETSR26 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR26 (rw) register accessor: Interrupt Processor Target 104 - 107\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr26::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr26::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr26`] +module"] pub type GICD_ITARGETSR26 = crate::Reg; #[doc = "Interrupt Processor Target 104 - 107"] pub mod gicd_itargetsr26; -#[doc = "GICD_ITARGETSR27 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR27 (rw) register accessor: Interrupt Processor Target 108 - 111\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr27::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr27`] +module"] pub type GICD_ITARGETSR27 = crate::Reg; #[doc = "Interrupt Processor Target 108 - 111"] pub mod gicd_itargetsr27; -#[doc = "GICD_ITARGETSR28 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR28 (rw) register accessor: Interrupt Processor Target 112 - 115\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr28::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr28`] +module"] pub type GICD_ITARGETSR28 = crate::Reg; #[doc = "Interrupt Processor Target 112 - 115"] pub mod gicd_itargetsr28; -#[doc = "GICD_ITARGETSR29 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR29 (rw) register accessor: Interrupt Processor Target 116 - 119\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr29::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr29::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr29`] +module"] pub type GICD_ITARGETSR29 = crate::Reg; #[doc = "Interrupt Processor Target 116 - 119"] pub mod gicd_itargetsr29; -#[doc = "GICD_ITARGETSR30 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR30 (rw) register accessor: Interrupt Processor Target 120 - 123\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr30::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr30::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr30`] +module"] pub type GICD_ITARGETSR30 = crate::Reg; #[doc = "Interrupt Processor Target 120 - 123"] pub mod gicd_itargetsr30; -#[doc = "GICD_ITARGETSR31 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR31 (rw) register accessor: Interrupt Processor Target 124 - 127\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr31::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr31`] +module"] pub type GICD_ITARGETSR31 = crate::Reg; #[doc = "Interrupt Processor Target 124 - 127"] pub mod gicd_itargetsr31; -#[doc = "GICD_ITARGETSR32 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR32 (rw) register accessor: Interrupt Processor Target 128 - 131\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr32::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr32`] +module"] pub type GICD_ITARGETSR32 = crate::Reg; #[doc = "Interrupt Processor Target 128 - 131"] pub mod gicd_itargetsr32; -#[doc = "GICD_ITARGETSR33 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR33 (rw) register accessor: Interrupt Processor Target 132 - 135\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr33::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr33::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr33`] +module"] pub type GICD_ITARGETSR33 = crate::Reg; #[doc = "Interrupt Processor Target 132 - 135"] pub mod gicd_itargetsr33; -#[doc = "GICD_ITARGETSR34 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR34 (rw) register accessor: Interrupt Processor Target 136 - 139\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr34::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr34::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr34`] +module"] pub type GICD_ITARGETSR34 = crate::Reg; #[doc = "Interrupt Processor Target 136 - 139"] pub mod gicd_itargetsr34; -#[doc = "GICD_ITARGETSR35 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR35 (rw) register accessor: Interrupt Processor Target 140 - 143\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr35::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr35`] +module"] pub type GICD_ITARGETSR35 = crate::Reg; #[doc = "Interrupt Processor Target 140 - 143"] pub mod gicd_itargetsr35; -#[doc = "GICD_ITARGETSR36 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR36 (rw) register accessor: Interrupt Processor Target 144 - 147\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr36::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr36`] +module"] pub type GICD_ITARGETSR36 = crate::Reg; #[doc = "Interrupt Processor Target 144 - 147"] pub mod gicd_itargetsr36; -#[doc = "GICD_ITARGETSR37 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR37 (rw) register accessor: Interrupt Processor Target 148 - 151\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr37::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr37::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr37`] +module"] pub type GICD_ITARGETSR37 = crate::Reg; #[doc = "Interrupt Processor Target 148 - 151"] pub mod gicd_itargetsr37; -#[doc = "GICD_ITARGETSR38 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR38 (rw) register accessor: Interrupt Processor Target 152 - 155\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr38::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr38::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr38`] +module"] pub type GICD_ITARGETSR38 = crate::Reg; #[doc = "Interrupt Processor Target 152 - 155"] pub mod gicd_itargetsr38; -#[doc = "GICD_ITARGETSR39 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR39 (rw) register accessor: Interrupt Processor Target 156 - 159\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr39::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr39`] +module"] pub type GICD_ITARGETSR39 = crate::Reg; #[doc = "Interrupt Processor Target 156 - 159"] pub mod gicd_itargetsr39; -#[doc = "GICD_ITARGETSR40 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR40 (rw) register accessor: Interrupt Processor Target 160 - 163\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr40::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr40`] +module"] pub type GICD_ITARGETSR40 = crate::Reg; #[doc = "Interrupt Processor Target 160 - 163"] pub mod gicd_itargetsr40; -#[doc = "GICD_ITARGETSR41 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR41 (rw) register accessor: Interrupt Processor Target 164 - 167\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr41::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr41::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr41`] +module"] pub type GICD_ITARGETSR41 = crate::Reg; #[doc = "Interrupt Processor Target 164 - 167"] pub mod gicd_itargetsr41; -#[doc = "GICD_ITARGETSR42 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR42 (rw) register accessor: Interrupt Processor Target 168 - 171\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr42::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr42::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr42`] +module"] pub type GICD_ITARGETSR42 = crate::Reg; #[doc = "Interrupt Processor Target 168 - 171"] pub mod gicd_itargetsr42; -#[doc = "GICD_ITARGETSR43 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR43 (rw) register accessor: Interrupt Processor Target 172 - 175\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr43::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr43`] +module"] pub type GICD_ITARGETSR43 = crate::Reg; #[doc = "Interrupt Processor Target 172 - 175"] pub mod gicd_itargetsr43; -#[doc = "GICD_ITARGETSR44 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR44 (rw) register accessor: Interrupt Processor Target 176 - 179\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr44::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr44`] +module"] pub type GICD_ITARGETSR44 = crate::Reg; #[doc = "Interrupt Processor Target 176 - 179"] pub mod gicd_itargetsr44; -#[doc = "GICD_ITARGETSR45 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR45 (rw) register accessor: Interrupt Processor Target 180 - 183\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr45::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr45::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr45`] +module"] pub type GICD_ITARGETSR45 = crate::Reg; #[doc = "Interrupt Processor Target 180 - 183"] pub mod gicd_itargetsr45; -#[doc = "GICD_ITARGETSR46 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR46 (rw) register accessor: Interrupt Processor Target 184 - 187\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr46::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr46::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr46`] +module"] pub type GICD_ITARGETSR46 = crate::Reg; #[doc = "Interrupt Processor Target 184 - 187"] pub mod gicd_itargetsr46; -#[doc = "GICD_ITARGETSR47 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR47 (rw) register accessor: Interrupt Processor Target 188 - 191\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr47::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr47`] +module"] pub type GICD_ITARGETSR47 = crate::Reg; #[doc = "Interrupt Processor Target 188 - 191"] pub mod gicd_itargetsr47; -#[doc = "GICD_ITARGETSR48 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR48 (rw) register accessor: Interrupt Processor Target 192 - 195\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr48`] +module"] pub type GICD_ITARGETSR48 = crate::Reg; #[doc = "Interrupt Processor Target 192 - 195"] pub mod gicd_itargetsr48; -#[doc = "GICD_ITARGETSR49 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR49 (rw) register accessor: Interrupt Processor Target 196 - 199\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr49::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr49::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr49`] +module"] pub type GICD_ITARGETSR49 = crate::Reg; #[doc = "Interrupt Processor Target 196 - 199"] pub mod gicd_itargetsr49; -#[doc = "GICD_ITARGETSR50 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR50 (rw) register accessor: Interrupt Processor Target 200 - 203\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr50::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr50::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr50`] +module"] pub type GICD_ITARGETSR50 = crate::Reg; #[doc = "Interrupt Processor Target 200 - 203"] pub mod gicd_itargetsr50; -#[doc = "GICD_ITARGETSR51 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR51 (rw) register accessor: Interrupt Processor Target 204 - 207\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr51::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr51`] +module"] pub type GICD_ITARGETSR51 = crate::Reg; #[doc = "Interrupt Processor Target 204 - 207"] pub mod gicd_itargetsr51; -#[doc = "GICD_ITARGETSR52 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR52 (rw) register accessor: Interrupt Processor Target 208 - 211\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr52::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr52`] +module"] pub type GICD_ITARGETSR52 = crate::Reg; #[doc = "Interrupt Processor Target 208 - 211"] pub mod gicd_itargetsr52; -#[doc = "GICD_ITARGETSR53 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR53 (rw) register accessor: Interrupt Processor Target 212 - 215\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr53::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr53::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr53`] +module"] pub type GICD_ITARGETSR53 = crate::Reg; #[doc = "Interrupt Processor Target 212 - 215"] pub mod gicd_itargetsr53; -#[doc = "GICD_ITARGETSR54 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR54 (rw) register accessor: Interrupt Processor Target 216 - 219\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr54::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr54::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr54`] +module"] pub type GICD_ITARGETSR54 = crate::Reg; #[doc = "Interrupt Processor Target 216 - 219"] pub mod gicd_itargetsr54; -#[doc = "GICD_ITARGETSR55 (rw) register accessor: an alias for `Reg`"] +#[doc = "GICD_ITARGETSR55 (rw) register accessor: Interrupt Processor Target 220 - 223\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr55::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gicd_itargetsr55`] +module"] pub type GICD_ITARGETSR55 = crate::Reg; #[doc = "Interrupt Processor Target 220 - 223"] pub mod gicd_itargetsr55; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr0.rs index 5ff6216..3397ff6 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr0.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr0.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_ITARGETSR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT0` reader - Interrupt 0"] -pub type INT0_R = crate::FieldReader; +pub type INT0_R = crate::FieldReader; #[doc = "Field `INT0` writer - Interrupt 0"] -pub type INT0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR0_SPEC, u8, u8, 8, O>; +pub type INT0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT1` reader - Interrupt 1"] -pub type INT1_R = crate::FieldReader; +pub type INT1_R = crate::FieldReader; #[doc = "Field `INT1` writer - Interrupt 1"] -pub type INT1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR0_SPEC, u8, u8, 8, O>; +pub type INT1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT2` reader - Interrupt 2"] -pub type INT2_R = crate::FieldReader; +pub type INT2_R = crate::FieldReader; #[doc = "Field `INT2` writer - Interrupt 2"] -pub type INT2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR0_SPEC, u8, u8, 8, O>; +pub type INT2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT3` reader - Interrupt 3"] -pub type INT3_R = crate::FieldReader; +pub type INT3_R = crate::FieldReader; #[doc = "Field `INT3` writer - Interrupt 3"] -pub type INT3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR0_SPEC, u8, u8, 8, O>; +pub type INT3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 0"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { INT3_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR0") + .field("int0", &format_args!("{}", self.int0().bits())) + .field("int1", &format_args!("{}", self.int1().bits())) + .field("int2", &format_args!("{}", self.int2().bits())) + .field("int3", &format_args!("{}", self.int3().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 0"] #[inline(always)] #[must_use] - pub fn int0(&mut self) -> INT0_W<0> { + pub fn int0(&mut self) -> INT0_W { INT0_W::new(self) } #[doc = "Bits 8:15 - Interrupt 1"] #[inline(always)] #[must_use] - pub fn int1(&mut self) -> INT1_W<8> { + pub fn int1(&mut self) -> INT1_W { INT1_W::new(self) } #[doc = "Bits 16:23 - Interrupt 2"] #[inline(always)] #[must_use] - pub fn int2(&mut self) -> INT2_W<16> { + pub fn int2(&mut self) -> INT2_W { INT2_W::new(self) } #[doc = "Bits 24:31 - Interrupt 3"] #[inline(always)] #[must_use] - pub fn int3(&mut self) -> INT3_W<24> { + pub fn int3(&mut self) -> INT3_W { INT3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 0 - 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr0](index.html) module"] +#[doc = "Interrupt Processor Target 0 - 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR0_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr0::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr0::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr0::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr0::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr1.rs index b2e62dd..c59f832 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr1.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr1.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_ITARGETSR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT4` reader - Interrupt 4"] -pub type INT4_R = crate::FieldReader; +pub type INT4_R = crate::FieldReader; #[doc = "Field `INT4` writer - Interrupt 4"] -pub type INT4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR1_SPEC, u8, u8, 8, O>; +pub type INT4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT5` reader - Interrupt 5"] -pub type INT5_R = crate::FieldReader; +pub type INT5_R = crate::FieldReader; #[doc = "Field `INT5` writer - Interrupt 5"] -pub type INT5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR1_SPEC, u8, u8, 8, O>; +pub type INT5_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT6` reader - Interrupt 6"] -pub type INT6_R = crate::FieldReader; +pub type INT6_R = crate::FieldReader; #[doc = "Field `INT6` writer - Interrupt 6"] -pub type INT6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR1_SPEC, u8, u8, 8, O>; +pub type INT6_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT7` reader - Interrupt 7"] -pub type INT7_R = crate::FieldReader; +pub type INT7_R = crate::FieldReader; #[doc = "Field `INT7` writer - Interrupt 7"] -pub type INT7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR1_SPEC, u8, u8, 8, O>; +pub type INT7_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 4"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { INT7_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR1") + .field("int4", &format_args!("{}", self.int4().bits())) + .field("int5", &format_args!("{}", self.int5().bits())) + .field("int6", &format_args!("{}", self.int6().bits())) + .field("int7", &format_args!("{}", self.int7().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 4"] #[inline(always)] #[must_use] - pub fn int4(&mut self) -> INT4_W<0> { + pub fn int4(&mut self) -> INT4_W { INT4_W::new(self) } #[doc = "Bits 8:15 - Interrupt 5"] #[inline(always)] #[must_use] - pub fn int5(&mut self) -> INT5_W<8> { + pub fn int5(&mut self) -> INT5_W { INT5_W::new(self) } #[doc = "Bits 16:23 - Interrupt 6"] #[inline(always)] #[must_use] - pub fn int6(&mut self) -> INT6_W<16> { + pub fn int6(&mut self) -> INT6_W { INT6_W::new(self) } #[doc = "Bits 24:31 - Interrupt 7"] #[inline(always)] #[must_use] - pub fn int7(&mut self) -> INT7_W<24> { + pub fn int7(&mut self) -> INT7_W { INT7_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 4 - 7\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr1](index.html) module"] +#[doc = "Interrupt Processor Target 4 - 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR1_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr1::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr1::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr1::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr1::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr10.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr10.rs index c1a701c..f24a72b 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr10.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr10.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR10` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR10` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT40` reader - Interrupt 40"] -pub type INT40_R = crate::FieldReader; +pub type INT40_R = crate::FieldReader; #[doc = "Field `INT40` writer - Interrupt 40"] -pub type INT40_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR10_SPEC, u8, u8, 8, O>; +pub type INT40_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT41` reader - Interrupt 41"] -pub type INT41_R = crate::FieldReader; +pub type INT41_R = crate::FieldReader; #[doc = "Field `INT41` writer - Interrupt 41"] -pub type INT41_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR10_SPEC, u8, u8, 8, O>; +pub type INT41_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT42` reader - Interrupt 42"] -pub type INT42_R = crate::FieldReader; +pub type INT42_R = crate::FieldReader; #[doc = "Field `INT42` writer - Interrupt 42"] -pub type INT42_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR10_SPEC, u8, u8, 8, O>; +pub type INT42_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT43` reader - Interrupt 43"] -pub type INT43_R = crate::FieldReader; +pub type INT43_R = crate::FieldReader; #[doc = "Field `INT43` writer - Interrupt 43"] -pub type INT43_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR10_SPEC, u8, u8, 8, O>; +pub type INT43_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 40"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT43_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR10") + .field("int40", &format_args!("{}", self.int40().bits())) + .field("int41", &format_args!("{}", self.int41().bits())) + .field("int42", &format_args!("{}", self.int42().bits())) + .field("int43", &format_args!("{}", self.int43().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 40"] #[inline(always)] #[must_use] - pub fn int40(&mut self) -> INT40_W<0> { + pub fn int40(&mut self) -> INT40_W { INT40_W::new(self) } #[doc = "Bits 8:15 - Interrupt 41"] #[inline(always)] #[must_use] - pub fn int41(&mut self) -> INT41_W<8> { + pub fn int41(&mut self) -> INT41_W { INT41_W::new(self) } #[doc = "Bits 16:23 - Interrupt 42"] #[inline(always)] #[must_use] - pub fn int42(&mut self) -> INT42_W<16> { + pub fn int42(&mut self) -> INT42_W { INT42_W::new(self) } #[doc = "Bits 24:31 - Interrupt 43"] #[inline(always)] #[must_use] - pub fn int43(&mut self) -> INT43_W<24> { + pub fn int43(&mut self) -> INT43_W { INT43_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 40 - 43\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr10](index.html) module"] +#[doc = "Interrupt Processor Target 40 - 43\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR10_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR10_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr10::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR10_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr10::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr10::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr10::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR10_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr11.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr11.rs index a5378bb..c9888e1 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr11.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr11.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR11` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR11` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT44` reader - Interrupt 44"] -pub type INT44_R = crate::FieldReader; +pub type INT44_R = crate::FieldReader; #[doc = "Field `INT44` writer - Interrupt 44"] -pub type INT44_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR11_SPEC, u8, u8, 8, O>; +pub type INT44_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT45` reader - Interrupt 45"] -pub type INT45_R = crate::FieldReader; +pub type INT45_R = crate::FieldReader; #[doc = "Field `INT45` writer - Interrupt 45"] -pub type INT45_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR11_SPEC, u8, u8, 8, O>; +pub type INT45_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT46` reader - Interrupt 46"] -pub type INT46_R = crate::FieldReader; +pub type INT46_R = crate::FieldReader; #[doc = "Field `INT46` writer - Interrupt 46"] -pub type INT46_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR11_SPEC, u8, u8, 8, O>; +pub type INT46_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT47` reader - Interrupt 47"] -pub type INT47_R = crate::FieldReader; +pub type INT47_R = crate::FieldReader; #[doc = "Field `INT47` writer - Interrupt 47"] -pub type INT47_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR11_SPEC, u8, u8, 8, O>; +pub type INT47_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 44"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT47_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR11") + .field("int44", &format_args!("{}", self.int44().bits())) + .field("int45", &format_args!("{}", self.int45().bits())) + .field("int46", &format_args!("{}", self.int46().bits())) + .field("int47", &format_args!("{}", self.int47().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 44"] #[inline(always)] #[must_use] - pub fn int44(&mut self) -> INT44_W<0> { + pub fn int44(&mut self) -> INT44_W { INT44_W::new(self) } #[doc = "Bits 8:15 - Interrupt 45"] #[inline(always)] #[must_use] - pub fn int45(&mut self) -> INT45_W<8> { + pub fn int45(&mut self) -> INT45_W { INT45_W::new(self) } #[doc = "Bits 16:23 - Interrupt 46"] #[inline(always)] #[must_use] - pub fn int46(&mut self) -> INT46_W<16> { + pub fn int46(&mut self) -> INT46_W { INT46_W::new(self) } #[doc = "Bits 24:31 - Interrupt 47"] #[inline(always)] #[must_use] - pub fn int47(&mut self) -> INT47_W<24> { + pub fn int47(&mut self) -> INT47_W { INT47_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 44 - 47\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr11](index.html) module"] +#[doc = "Interrupt Processor Target 44 - 47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR11_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR11_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr11::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR11_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr11::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr11::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr11::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR11_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr12.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr12.rs index d479178..fe7df13 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr12.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr12.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR12` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR12` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT48` reader - Interrupt 48"] -pub type INT48_R = crate::FieldReader; +pub type INT48_R = crate::FieldReader; #[doc = "Field `INT48` writer - Interrupt 48"] -pub type INT48_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR12_SPEC, u8, u8, 8, O>; +pub type INT48_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT49` reader - Interrupt 49"] -pub type INT49_R = crate::FieldReader; +pub type INT49_R = crate::FieldReader; #[doc = "Field `INT49` writer - Interrupt 49"] -pub type INT49_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR12_SPEC, u8, u8, 8, O>; +pub type INT49_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT50` reader - Interrupt 50"] -pub type INT50_R = crate::FieldReader; +pub type INT50_R = crate::FieldReader; #[doc = "Field `INT50` writer - Interrupt 50"] -pub type INT50_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR12_SPEC, u8, u8, 8, O>; +pub type INT50_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT51` reader - Interrupt 51"] -pub type INT51_R = crate::FieldReader; +pub type INT51_R = crate::FieldReader; #[doc = "Field `INT51` writer - Interrupt 51"] -pub type INT51_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR12_SPEC, u8, u8, 8, O>; +pub type INT51_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 48"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT51_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR12") + .field("int48", &format_args!("{}", self.int48().bits())) + .field("int49", &format_args!("{}", self.int49().bits())) + .field("int50", &format_args!("{}", self.int50().bits())) + .field("int51", &format_args!("{}", self.int51().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 48"] #[inline(always)] #[must_use] - pub fn int48(&mut self) -> INT48_W<0> { + pub fn int48(&mut self) -> INT48_W { INT48_W::new(self) } #[doc = "Bits 8:15 - Interrupt 49"] #[inline(always)] #[must_use] - pub fn int49(&mut self) -> INT49_W<8> { + pub fn int49(&mut self) -> INT49_W { INT49_W::new(self) } #[doc = "Bits 16:23 - Interrupt 50"] #[inline(always)] #[must_use] - pub fn int50(&mut self) -> INT50_W<16> { + pub fn int50(&mut self) -> INT50_W { INT50_W::new(self) } #[doc = "Bits 24:31 - Interrupt 51"] #[inline(always)] #[must_use] - pub fn int51(&mut self) -> INT51_W<24> { + pub fn int51(&mut self) -> INT51_W { INT51_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 48 - 51\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr12](index.html) module"] +#[doc = "Interrupt Processor Target 48 - 51\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR12_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR12_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr12::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR12_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr12::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr12::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr12::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR12_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr13.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr13.rs index 0917102..69db0f9 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr13.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr13.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR13` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR13` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT52` reader - Interrupt 52"] -pub type INT52_R = crate::FieldReader; +pub type INT52_R = crate::FieldReader; #[doc = "Field `INT52` writer - Interrupt 52"] -pub type INT52_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR13_SPEC, u8, u8, 8, O>; +pub type INT52_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT53` reader - Interrupt 53"] -pub type INT53_R = crate::FieldReader; +pub type INT53_R = crate::FieldReader; #[doc = "Field `INT53` writer - Interrupt 53"] -pub type INT53_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR13_SPEC, u8, u8, 8, O>; +pub type INT53_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT54` reader - Interrupt 54"] -pub type INT54_R = crate::FieldReader; +pub type INT54_R = crate::FieldReader; #[doc = "Field `INT54` writer - Interrupt 54"] -pub type INT54_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR13_SPEC, u8, u8, 8, O>; +pub type INT54_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT55` reader - Interrupt 55"] -pub type INT55_R = crate::FieldReader; +pub type INT55_R = crate::FieldReader; #[doc = "Field `INT55` writer - Interrupt 55"] -pub type INT55_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR13_SPEC, u8, u8, 8, O>; +pub type INT55_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 52"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT55_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR13") + .field("int52", &format_args!("{}", self.int52().bits())) + .field("int53", &format_args!("{}", self.int53().bits())) + .field("int54", &format_args!("{}", self.int54().bits())) + .field("int55", &format_args!("{}", self.int55().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 52"] #[inline(always)] #[must_use] - pub fn int52(&mut self) -> INT52_W<0> { + pub fn int52(&mut self) -> INT52_W { INT52_W::new(self) } #[doc = "Bits 8:15 - Interrupt 53"] #[inline(always)] #[must_use] - pub fn int53(&mut self) -> INT53_W<8> { + pub fn int53(&mut self) -> INT53_W { INT53_W::new(self) } #[doc = "Bits 16:23 - Interrupt 54"] #[inline(always)] #[must_use] - pub fn int54(&mut self) -> INT54_W<16> { + pub fn int54(&mut self) -> INT54_W { INT54_W::new(self) } #[doc = "Bits 24:31 - Interrupt 55"] #[inline(always)] #[must_use] - pub fn int55(&mut self) -> INT55_W<24> { + pub fn int55(&mut self) -> INT55_W { INT55_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 52 - 55\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr13](index.html) module"] +#[doc = "Interrupt Processor Target 52 - 55\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR13_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR13_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr13::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR13_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr13::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr13::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr13::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR13_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr14.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr14.rs index a8677c1..dadd760 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr14.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr14.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR14` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR14` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT56` reader - Interrupt 56"] -pub type INT56_R = crate::FieldReader; +pub type INT56_R = crate::FieldReader; #[doc = "Field `INT56` writer - Interrupt 56"] -pub type INT56_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR14_SPEC, u8, u8, 8, O>; +pub type INT56_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT57` reader - Interrupt 57"] -pub type INT57_R = crate::FieldReader; +pub type INT57_R = crate::FieldReader; #[doc = "Field `INT57` writer - Interrupt 57"] -pub type INT57_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR14_SPEC, u8, u8, 8, O>; +pub type INT57_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT58` reader - Interrupt 58"] -pub type INT58_R = crate::FieldReader; +pub type INT58_R = crate::FieldReader; #[doc = "Field `INT58` writer - Interrupt 58"] -pub type INT58_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR14_SPEC, u8, u8, 8, O>; +pub type INT58_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT59` reader - Interrupt 59"] -pub type INT59_R = crate::FieldReader; +pub type INT59_R = crate::FieldReader; #[doc = "Field `INT59` writer - Interrupt 59"] -pub type INT59_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR14_SPEC, u8, u8, 8, O>; +pub type INT59_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 56"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT59_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR14") + .field("int56", &format_args!("{}", self.int56().bits())) + .field("int57", &format_args!("{}", self.int57().bits())) + .field("int58", &format_args!("{}", self.int58().bits())) + .field("int59", &format_args!("{}", self.int59().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 56"] #[inline(always)] #[must_use] - pub fn int56(&mut self) -> INT56_W<0> { + pub fn int56(&mut self) -> INT56_W { INT56_W::new(self) } #[doc = "Bits 8:15 - Interrupt 57"] #[inline(always)] #[must_use] - pub fn int57(&mut self) -> INT57_W<8> { + pub fn int57(&mut self) -> INT57_W { INT57_W::new(self) } #[doc = "Bits 16:23 - Interrupt 58"] #[inline(always)] #[must_use] - pub fn int58(&mut self) -> INT58_W<16> { + pub fn int58(&mut self) -> INT58_W { INT58_W::new(self) } #[doc = "Bits 24:31 - Interrupt 59"] #[inline(always)] #[must_use] - pub fn int59(&mut self) -> INT59_W<24> { + pub fn int59(&mut self) -> INT59_W { INT59_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 56 - 59\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr14](index.html) module"] +#[doc = "Interrupt Processor Target 56 - 59\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR14_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR14_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr14::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR14_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr14::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr14::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr14::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR14_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr15.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr15.rs index 9733ca2..040245f 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr15.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr15.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR15` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR15` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT60` reader - Interrupt 60"] -pub type INT60_R = crate::FieldReader; +pub type INT60_R = crate::FieldReader; #[doc = "Field `INT60` writer - Interrupt 60"] -pub type INT60_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR15_SPEC, u8, u8, 8, O>; +pub type INT60_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT61` reader - Interrupt 61"] -pub type INT61_R = crate::FieldReader; +pub type INT61_R = crate::FieldReader; #[doc = "Field `INT61` writer - Interrupt 61"] -pub type INT61_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR15_SPEC, u8, u8, 8, O>; +pub type INT61_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT62` reader - Interrupt 62"] -pub type INT62_R = crate::FieldReader; +pub type INT62_R = crate::FieldReader; #[doc = "Field `INT62` writer - Interrupt 62"] -pub type INT62_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR15_SPEC, u8, u8, 8, O>; +pub type INT62_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT63` reader - Interrupt 63"] -pub type INT63_R = crate::FieldReader; +pub type INT63_R = crate::FieldReader; #[doc = "Field `INT63` writer - Interrupt 63"] -pub type INT63_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR15_SPEC, u8, u8, 8, O>; +pub type INT63_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 60"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT63_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR15") + .field("int60", &format_args!("{}", self.int60().bits())) + .field("int61", &format_args!("{}", self.int61().bits())) + .field("int62", &format_args!("{}", self.int62().bits())) + .field("int63", &format_args!("{}", self.int63().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 60"] #[inline(always)] #[must_use] - pub fn int60(&mut self) -> INT60_W<0> { + pub fn int60(&mut self) -> INT60_W { INT60_W::new(self) } #[doc = "Bits 8:15 - Interrupt 61"] #[inline(always)] #[must_use] - pub fn int61(&mut self) -> INT61_W<8> { + pub fn int61(&mut self) -> INT61_W { INT61_W::new(self) } #[doc = "Bits 16:23 - Interrupt 62"] #[inline(always)] #[must_use] - pub fn int62(&mut self) -> INT62_W<16> { + pub fn int62(&mut self) -> INT62_W { INT62_W::new(self) } #[doc = "Bits 24:31 - Interrupt 63"] #[inline(always)] #[must_use] - pub fn int63(&mut self) -> INT63_W<24> { + pub fn int63(&mut self) -> INT63_W { INT63_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 60 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr15](index.html) module"] +#[doc = "Interrupt Processor Target 60 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR15_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR15_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr15::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR15_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr15::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr15::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr15::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR15_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr16.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr16.rs index 3382e16..b269778 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr16.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr16.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR16` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR16` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::FieldReader; +pub type TIMER_R = crate::FieldReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR16_SPEC, u8, u8, 8, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::FieldReader; +pub type MAILBOX_R = crate::FieldReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR16_SPEC, u8, u8, 8, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::FieldReader; +pub type DOORBELL0_R = crate::FieldReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR16_SPEC, u8, u8, 8, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::FieldReader; +pub type DOORBELL1_R = crate::FieldReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR16_SPEC, u8, u8, 8, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - ARMC Timer"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { DOORBELL1_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR16") + .field("timer", &format_args!("{}", self.timer().bits())) + .field("mailbox", &format_args!("{}", self.mailbox().bits())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bits())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bits 8:15 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<8> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bits 16:23 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<16> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bits 24:31 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<24> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 64 - 67\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr16](index.html) module"] +#[doc = "Interrupt Processor Target 64 - 67\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr16::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr16::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR16_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR16_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr16::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR16_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr16::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr16::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR16_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr16::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR16_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr17.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr17.rs index b077d1f..46adba9 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr17.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr17.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR17` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR17` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::FieldReader; +pub type VPU0_HALTED_R = crate::FieldReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR17_SPEC, u8, u8, 8, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::FieldReader; +pub type VPU1_HALTED_R = crate::FieldReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR17_SPEC, u8, u8, 8, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::FieldReader; +pub type ARM_ADDRESS_ERROR_R = crate::FieldReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR17_SPEC, u8, u8, 8, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::FieldReader; +pub type ARM_AXI_ERROR_R = crate::FieldReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR17_SPEC, u8, u8, 8, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - VPU0 halted"] #[inline(always)] @@ -76,50 +40,78 @@ impl R { ARM_AXI_ERROR_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR17") + .field( + "vpu0_halted", + &format_args!("{}", self.vpu0_halted().bits()), + ) + .field( + "vpu1_halted", + &format_args!("{}", self.vpu1_halted().bits()), + ) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bits()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<0> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bits 8:15 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<8> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bits 16:23 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<16> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bits 24:31 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<24> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 68 - 71\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr17](index.html) module"] +#[doc = "Interrupt Processor Target 68 - 71\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr17::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr17::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR17_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR17_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr17::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR17_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr17::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr17::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR17_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr17::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR17_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr18.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr18.rs index 50ca471..b6aa1cd 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr18.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr18.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_ITARGETSR18` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR18` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SWI0` reader - Software interrupt 0"] -pub type SWI0_R = crate::FieldReader; +pub type SWI0_R = crate::FieldReader; #[doc = "Field `SWI0` writer - Software interrupt 0"] -pub type SWI0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR18_SPEC, u8, u8, 8, O>; +pub type SWI0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SWI1` reader - Software interrupt 1"] -pub type SWI1_R = crate::FieldReader; +pub type SWI1_R = crate::FieldReader; #[doc = "Field `SWI1` writer - Software interrupt 1"] -pub type SWI1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR18_SPEC, u8, u8, 8, O>; +pub type SWI1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SWI2` reader - Software interrupt 2"] -pub type SWI2_R = crate::FieldReader; +pub type SWI2_R = crate::FieldReader; #[doc = "Field `SWI2` writer - Software interrupt 2"] -pub type SWI2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR18_SPEC, u8, u8, 8, O>; +pub type SWI2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SWI3` reader - Software interrupt 3"] -pub type SWI3_R = crate::FieldReader; +pub type SWI3_R = crate::FieldReader; #[doc = "Field `SWI3` writer - Software interrupt 3"] -pub type SWI3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR18_SPEC, u8, u8, 8, O>; +pub type SWI3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Software interrupt 0"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { SWI3_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR18") + .field("swi0", &format_args!("{}", self.swi0().bits())) + .field("swi1", &format_args!("{}", self.swi1().bits())) + .field("swi2", &format_args!("{}", self.swi2().bits())) + .field("swi3", &format_args!("{}", self.swi3().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Software interrupt 0"] #[inline(always)] #[must_use] - pub fn swi0(&mut self) -> SWI0_W<0> { + pub fn swi0(&mut self) -> SWI0_W { SWI0_W::new(self) } #[doc = "Bits 8:15 - Software interrupt 1"] #[inline(always)] #[must_use] - pub fn swi1(&mut self) -> SWI1_W<8> { + pub fn swi1(&mut self) -> SWI1_W { SWI1_W::new(self) } #[doc = "Bits 16:23 - Software interrupt 2"] #[inline(always)] #[must_use] - pub fn swi2(&mut self) -> SWI2_W<16> { + pub fn swi2(&mut self) -> SWI2_W { SWI2_W::new(self) } #[doc = "Bits 24:31 - Software interrupt 3"] #[inline(always)] #[must_use] - pub fn swi3(&mut self) -> SWI3_W<24> { + pub fn swi3(&mut self) -> SWI3_W { SWI3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 72 - 75\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr18](index.html) module"] +#[doc = "Interrupt Processor Target 72 - 75\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr18::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr18::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR18_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR18_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr18::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR18_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr18::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr18::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR18_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr18::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR18_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr19.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr19.rs index 5616822..ba3a1fb 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr19.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr19.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_ITARGETSR19` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR19` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SWI4` reader - Software interrupt 4"] -pub type SWI4_R = crate::FieldReader; +pub type SWI4_R = crate::FieldReader; #[doc = "Field `SWI4` writer - Software interrupt 4"] -pub type SWI4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR19_SPEC, u8, u8, 8, O>; +pub type SWI4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SWI5` reader - Software interrupt 5"] -pub type SWI5_R = crate::FieldReader; +pub type SWI5_R = crate::FieldReader; #[doc = "Field `SWI5` writer - Software interrupt 5"] -pub type SWI5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR19_SPEC, u8, u8, 8, O>; +pub type SWI5_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SWI6` reader - Software interrupt 6"] -pub type SWI6_R = crate::FieldReader; +pub type SWI6_R = crate::FieldReader; #[doc = "Field `SWI6` writer - Software interrupt 6"] -pub type SWI6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR19_SPEC, u8, u8, 8, O>; +pub type SWI6_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SWI7` reader - Software interrupt 7"] -pub type SWI7_R = crate::FieldReader; +pub type SWI7_R = crate::FieldReader; #[doc = "Field `SWI7` writer - Software interrupt 7"] -pub type SWI7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR19_SPEC, u8, u8, 8, O>; +pub type SWI7_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Software interrupt 4"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { SWI7_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR19") + .field("swi4", &format_args!("{}", self.swi4().bits())) + .field("swi5", &format_args!("{}", self.swi5().bits())) + .field("swi6", &format_args!("{}", self.swi6().bits())) + .field("swi7", &format_args!("{}", self.swi7().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Software interrupt 4"] #[inline(always)] #[must_use] - pub fn swi4(&mut self) -> SWI4_W<0> { + pub fn swi4(&mut self) -> SWI4_W { SWI4_W::new(self) } #[doc = "Bits 8:15 - Software interrupt 5"] #[inline(always)] #[must_use] - pub fn swi5(&mut self) -> SWI5_W<8> { + pub fn swi5(&mut self) -> SWI5_W { SWI5_W::new(self) } #[doc = "Bits 16:23 - Software interrupt 6"] #[inline(always)] #[must_use] - pub fn swi6(&mut self) -> SWI6_W<16> { + pub fn swi6(&mut self) -> SWI6_W { SWI6_W::new(self) } #[doc = "Bits 24:31 - Software interrupt 7"] #[inline(always)] #[must_use] - pub fn swi7(&mut self) -> SWI7_W<24> { + pub fn swi7(&mut self) -> SWI7_W { SWI7_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 76 - 79\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr19](index.html) module"] +#[doc = "Interrupt Processor Target 76 - 79\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr19::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr19::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR19_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR19_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr19::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR19_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr19::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr19::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR19_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr19::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR19_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr2.rs index a651c0b..e250597 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr2.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr2.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_ITARGETSR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT8` reader - Interrupt 8"] -pub type INT8_R = crate::FieldReader; +pub type INT8_R = crate::FieldReader; #[doc = "Field `INT8` writer - Interrupt 8"] -pub type INT8_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR2_SPEC, u8, u8, 8, O>; +pub type INT8_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT9` reader - Interrupt 9"] -pub type INT9_R = crate::FieldReader; +pub type INT9_R = crate::FieldReader; #[doc = "Field `INT9` writer - Interrupt 9"] -pub type INT9_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR2_SPEC, u8, u8, 8, O>; +pub type INT9_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT10` reader - Interrupt 10"] -pub type INT10_R = crate::FieldReader; +pub type INT10_R = crate::FieldReader; #[doc = "Field `INT10` writer - Interrupt 10"] -pub type INT10_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR2_SPEC, u8, u8, 8, O>; +pub type INT10_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT11` reader - Interrupt 11"] -pub type INT11_R = crate::FieldReader; +pub type INT11_R = crate::FieldReader; #[doc = "Field `INT11` writer - Interrupt 11"] -pub type INT11_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR2_SPEC, u8, u8, 8, O>; +pub type INT11_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 8"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { INT11_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR2") + .field("int8", &format_args!("{}", self.int8().bits())) + .field("int9", &format_args!("{}", self.int9().bits())) + .field("int10", &format_args!("{}", self.int10().bits())) + .field("int11", &format_args!("{}", self.int11().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 8"] #[inline(always)] #[must_use] - pub fn int8(&mut self) -> INT8_W<0> { + pub fn int8(&mut self) -> INT8_W { INT8_W::new(self) } #[doc = "Bits 8:15 - Interrupt 9"] #[inline(always)] #[must_use] - pub fn int9(&mut self) -> INT9_W<8> { + pub fn int9(&mut self) -> INT9_W { INT9_W::new(self) } #[doc = "Bits 16:23 - Interrupt 10"] #[inline(always)] #[must_use] - pub fn int10(&mut self) -> INT10_W<16> { + pub fn int10(&mut self) -> INT10_W { INT10_W::new(self) } #[doc = "Bits 24:31 - Interrupt 11"] #[inline(always)] #[must_use] - pub fn int11(&mut self) -> INT11_W<24> { + pub fn int11(&mut self) -> INT11_W { INT11_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 8 - 11\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr2](index.html) module"] +#[doc = "Interrupt Processor Target 8 - 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR2_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr2::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr2::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr2::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr2::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr20.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr20.rs index ad5ec09..a4c1242 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr20.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr20.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR20` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR20` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT80` reader - Interrupt 80"] -pub type INT80_R = crate::FieldReader; +pub type INT80_R = crate::FieldReader; #[doc = "Field `INT80` writer - Interrupt 80"] -pub type INT80_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR20_SPEC, u8, u8, 8, O>; +pub type INT80_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT81` reader - Interrupt 81"] -pub type INT81_R = crate::FieldReader; +pub type INT81_R = crate::FieldReader; #[doc = "Field `INT81` writer - Interrupt 81"] -pub type INT81_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR20_SPEC, u8, u8, 8, O>; +pub type INT81_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT82` reader - Interrupt 82"] -pub type INT82_R = crate::FieldReader; +pub type INT82_R = crate::FieldReader; #[doc = "Field `INT82` writer - Interrupt 82"] -pub type INT82_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR20_SPEC, u8, u8, 8, O>; +pub type INT82_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT83` reader - Interrupt 83"] -pub type INT83_R = crate::FieldReader; +pub type INT83_R = crate::FieldReader; #[doc = "Field `INT83` writer - Interrupt 83"] -pub type INT83_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR20_SPEC, u8, u8, 8, O>; +pub type INT83_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 80"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT83_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR20") + .field("int80", &format_args!("{}", self.int80().bits())) + .field("int81", &format_args!("{}", self.int81().bits())) + .field("int82", &format_args!("{}", self.int82().bits())) + .field("int83", &format_args!("{}", self.int83().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 80"] #[inline(always)] #[must_use] - pub fn int80(&mut self) -> INT80_W<0> { + pub fn int80(&mut self) -> INT80_W { INT80_W::new(self) } #[doc = "Bits 8:15 - Interrupt 81"] #[inline(always)] #[must_use] - pub fn int81(&mut self) -> INT81_W<8> { + pub fn int81(&mut self) -> INT81_W { INT81_W::new(self) } #[doc = "Bits 16:23 - Interrupt 82"] #[inline(always)] #[must_use] - pub fn int82(&mut self) -> INT82_W<16> { + pub fn int82(&mut self) -> INT82_W { INT82_W::new(self) } #[doc = "Bits 24:31 - Interrupt 83"] #[inline(always)] #[must_use] - pub fn int83(&mut self) -> INT83_W<24> { + pub fn int83(&mut self) -> INT83_W { INT83_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 80 - 83\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr20](index.html) module"] +#[doc = "Interrupt Processor Target 80 - 83\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr20::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr20::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR20_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR20_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr20::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR20_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr20::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr20::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR20_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr20::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR20_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr21.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr21.rs index 2e201ff..9cd76bb 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr21.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr21.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR21` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR21` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT84` reader - Interrupt 84"] -pub type INT84_R = crate::FieldReader; +pub type INT84_R = crate::FieldReader; #[doc = "Field `INT84` writer - Interrupt 84"] -pub type INT84_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR21_SPEC, u8, u8, 8, O>; +pub type INT84_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT85` reader - Interrupt 85"] -pub type INT85_R = crate::FieldReader; +pub type INT85_R = crate::FieldReader; #[doc = "Field `INT85` writer - Interrupt 85"] -pub type INT85_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR21_SPEC, u8, u8, 8, O>; +pub type INT85_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT86` reader - Interrupt 86"] -pub type INT86_R = crate::FieldReader; +pub type INT86_R = crate::FieldReader; #[doc = "Field `INT86` writer - Interrupt 86"] -pub type INT86_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR21_SPEC, u8, u8, 8, O>; +pub type INT86_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT87` reader - Interrupt 87"] -pub type INT87_R = crate::FieldReader; +pub type INT87_R = crate::FieldReader; #[doc = "Field `INT87` writer - Interrupt 87"] -pub type INT87_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR21_SPEC, u8, u8, 8, O>; +pub type INT87_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 84"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT87_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR21") + .field("int84", &format_args!("{}", self.int84().bits())) + .field("int85", &format_args!("{}", self.int85().bits())) + .field("int86", &format_args!("{}", self.int86().bits())) + .field("int87", &format_args!("{}", self.int87().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 84"] #[inline(always)] #[must_use] - pub fn int84(&mut self) -> INT84_W<0> { + pub fn int84(&mut self) -> INT84_W { INT84_W::new(self) } #[doc = "Bits 8:15 - Interrupt 85"] #[inline(always)] #[must_use] - pub fn int85(&mut self) -> INT85_W<8> { + pub fn int85(&mut self) -> INT85_W { INT85_W::new(self) } #[doc = "Bits 16:23 - Interrupt 86"] #[inline(always)] #[must_use] - pub fn int86(&mut self) -> INT86_W<16> { + pub fn int86(&mut self) -> INT86_W { INT86_W::new(self) } #[doc = "Bits 24:31 - Interrupt 87"] #[inline(always)] #[must_use] - pub fn int87(&mut self) -> INT87_W<24> { + pub fn int87(&mut self) -> INT87_W { INT87_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 84 - 87\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr21](index.html) module"] +#[doc = "Interrupt Processor Target 84 - 87\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr21::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr21::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR21_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR21_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr21::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR21_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr21::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr21::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR21_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr21::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR21_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr22.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr22.rs index 1169a9c..682a1a5 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr22.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr22.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR22` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR22` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT88` reader - Interrupt 88"] -pub type INT88_R = crate::FieldReader; +pub type INT88_R = crate::FieldReader; #[doc = "Field `INT88` writer - Interrupt 88"] -pub type INT88_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR22_SPEC, u8, u8, 8, O>; +pub type INT88_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT89` reader - Interrupt 89"] -pub type INT89_R = crate::FieldReader; +pub type INT89_R = crate::FieldReader; #[doc = "Field `INT89` writer - Interrupt 89"] -pub type INT89_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR22_SPEC, u8, u8, 8, O>; +pub type INT89_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT90` reader - Interrupt 90"] -pub type INT90_R = crate::FieldReader; +pub type INT90_R = crate::FieldReader; #[doc = "Field `INT90` writer - Interrupt 90"] -pub type INT90_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR22_SPEC, u8, u8, 8, O>; +pub type INT90_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT91` reader - Interrupt 91"] -pub type INT91_R = crate::FieldReader; +pub type INT91_R = crate::FieldReader; #[doc = "Field `INT91` writer - Interrupt 91"] -pub type INT91_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR22_SPEC, u8, u8, 8, O>; +pub type INT91_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 88"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT91_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR22") + .field("int88", &format_args!("{}", self.int88().bits())) + .field("int89", &format_args!("{}", self.int89().bits())) + .field("int90", &format_args!("{}", self.int90().bits())) + .field("int91", &format_args!("{}", self.int91().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 88"] #[inline(always)] #[must_use] - pub fn int88(&mut self) -> INT88_W<0> { + pub fn int88(&mut self) -> INT88_W { INT88_W::new(self) } #[doc = "Bits 8:15 - Interrupt 89"] #[inline(always)] #[must_use] - pub fn int89(&mut self) -> INT89_W<8> { + pub fn int89(&mut self) -> INT89_W { INT89_W::new(self) } #[doc = "Bits 16:23 - Interrupt 90"] #[inline(always)] #[must_use] - pub fn int90(&mut self) -> INT90_W<16> { + pub fn int90(&mut self) -> INT90_W { INT90_W::new(self) } #[doc = "Bits 24:31 - Interrupt 91"] #[inline(always)] #[must_use] - pub fn int91(&mut self) -> INT91_W<24> { + pub fn int91(&mut self) -> INT91_W { INT91_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 88 - 91\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr22](index.html) module"] +#[doc = "Interrupt Processor Target 88 - 91\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr22::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr22::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR22_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR22_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr22::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR22_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr22::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr22::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR22_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr22::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR22_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr23.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr23.rs index 4035137..a7e602a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr23.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr23.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR23` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR23` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT92` reader - Interrupt 92"] -pub type INT92_R = crate::FieldReader; +pub type INT92_R = crate::FieldReader; #[doc = "Field `INT92` writer - Interrupt 92"] -pub type INT92_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR23_SPEC, u8, u8, 8, O>; +pub type INT92_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT93` reader - Interrupt 93"] -pub type INT93_R = crate::FieldReader; +pub type INT93_R = crate::FieldReader; #[doc = "Field `INT93` writer - Interrupt 93"] -pub type INT93_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR23_SPEC, u8, u8, 8, O>; +pub type INT93_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT94` reader - Interrupt 94"] -pub type INT94_R = crate::FieldReader; +pub type INT94_R = crate::FieldReader; #[doc = "Field `INT94` writer - Interrupt 94"] -pub type INT94_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR23_SPEC, u8, u8, 8, O>; +pub type INT94_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT95` reader - Interrupt 95"] -pub type INT95_R = crate::FieldReader; +pub type INT95_R = crate::FieldReader; #[doc = "Field `INT95` writer - Interrupt 95"] -pub type INT95_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR23_SPEC, u8, u8, 8, O>; +pub type INT95_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 92"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT95_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR23") + .field("int92", &format_args!("{}", self.int92().bits())) + .field("int93", &format_args!("{}", self.int93().bits())) + .field("int94", &format_args!("{}", self.int94().bits())) + .field("int95", &format_args!("{}", self.int95().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 92"] #[inline(always)] #[must_use] - pub fn int92(&mut self) -> INT92_W<0> { + pub fn int92(&mut self) -> INT92_W { INT92_W::new(self) } #[doc = "Bits 8:15 - Interrupt 93"] #[inline(always)] #[must_use] - pub fn int93(&mut self) -> INT93_W<8> { + pub fn int93(&mut self) -> INT93_W { INT93_W::new(self) } #[doc = "Bits 16:23 - Interrupt 94"] #[inline(always)] #[must_use] - pub fn int94(&mut self) -> INT94_W<16> { + pub fn int94(&mut self) -> INT94_W { INT94_W::new(self) } #[doc = "Bits 24:31 - Interrupt 95"] #[inline(always)] #[must_use] - pub fn int95(&mut self) -> INT95_W<24> { + pub fn int95(&mut self) -> INT95_W { INT95_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 92 - 95\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr23](index.html) module"] +#[doc = "Interrupt Processor Target 92 - 95\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr23::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr23::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR23_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR23_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr23::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR23_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr23::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr23::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR23_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr23::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR23_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr24.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr24.rs index e177a8f..69df3b8 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr24.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr24.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR24` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR24` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::FieldReader; +pub type TIMER_0_R = crate::FieldReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR24_SPEC, u8, u8, 8, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::FieldReader; +pub type TIMER_1_R = crate::FieldReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR24_SPEC, u8, u8, 8, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::FieldReader; +pub type TIMER_2_R = crate::FieldReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR24_SPEC, u8, u8, 8, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::FieldReader; +pub type TIMER_3_R = crate::FieldReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR24_SPEC, u8, u8, 8, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Timer 0"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { TIMER_3_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR24") + .field("timer_0", &format_args!("{}", self.timer_0().bits())) + .field("timer_1", &format_args!("{}", self.timer_1().bits())) + .field("timer_2", &format_args!("{}", self.timer_2().bits())) + .field("timer_3", &format_args!("{}", self.timer_3().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bits 8:15 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<8> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bits 16:23 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<16> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bits 24:31 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<24> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 96 - 99\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr24](index.html) module"] +#[doc = "Interrupt Processor Target 96 - 99\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr24::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr24::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR24_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR24_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr24::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR24_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr24::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr24::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR24_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr24::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR24_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr25.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr25.rs index 7d792a5..79f7321 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr25.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr25.rs @@ -1,58 +1,23 @@ #[doc = "Register `GICD_ITARGETSR25` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR25` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::FieldReader; +pub type H264_0_R = crate::FieldReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR25_SPEC, u8, u8, 8, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::FieldReader; +pub type H264_1_R = crate::FieldReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR25_SPEC, u8, u8, 8, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::FieldReader; +pub type H264_2_R = crate::FieldReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR25_SPEC, u8, u8, 8, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::FieldReader; +pub type JPEG_R = crate::FieldReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR25_SPEC, u8, u8, 8, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - H264 0"] #[inline(always)] @@ -75,50 +40,66 @@ impl R { JPEG_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR25") + .field("h264_0", &format_args!("{}", self.h264_0().bits())) + .field("h264_1", &format_args!("{}", self.h264_1().bits())) + .field("h264_2", &format_args!("{}", self.h264_2().bits())) + .field("jpeg", &format_args!("{}", self.jpeg().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<0> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bits 8:15 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<8> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bits 16:23 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<16> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bits 24:31 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<24> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 100 - 103\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr25](index.html) module"] +#[doc = "Interrupt Processor Target 100 - 103\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr25::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr25::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR25_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR25_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr25::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR25_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr25::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr25::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR25_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr25::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR25_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr26.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr26.rs index 3b5ee68..5e618ff 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr26.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr26.rs @@ -1,56 +1,23 @@ #[doc = "Register `GICD_ITARGETSR26` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR26` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::FieldReader; +pub type ISP_R = crate::FieldReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR26_SPEC, u8, u8, 8, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::FieldReader; +pub type USB_R = crate::FieldReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR26_SPEC, u8, u8, 8, O>; +pub type USB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::FieldReader; +pub type V3D_R = crate::FieldReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR26_SPEC, u8, u8, 8, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::FieldReader; +pub type TRANSPOSER_R = crate::FieldReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR26_SPEC, u8, u8, 8, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - ISP"] #[inline(always)] @@ -73,50 +40,66 @@ impl R { TRANSPOSER_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR26") + .field("isp", &format_args!("{}", self.isp().bits())) + .field("usb", &format_args!("{}", self.usb().bits())) + .field("v3d", &format_args!("{}", self.v3d().bits())) + .field("transposer", &format_args!("{}", self.transposer().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<0> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bits 8:15 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<8> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bits 16:23 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<16> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bits 24:31 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<24> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 104 - 107\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr26](index.html) module"] +#[doc = "Interrupt Processor Target 104 - 107\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr26::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr26::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR26_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR26_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr26::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR26_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr26::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr26::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR26_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr26::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR26_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr27.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr27.rs index 6b66f35..e026659 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr27.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr27.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR27` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR27` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::FieldReader; +pub type MULTICORE_SYNC_0_R = crate::FieldReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR27_SPEC, u8, u8, 8, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::FieldReader; +pub type MULTICORE_SYNC_1_R = crate::FieldReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR27_SPEC, u8, u8, 8, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::FieldReader; +pub type MULTICORE_SYNC_2_R = crate::FieldReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR27_SPEC, u8, u8, 8, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::FieldReader; +pub type MULTICORE_SYNC_3_R = crate::FieldReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR27_SPEC, u8, u8, 8, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Multicore Sync 0"] #[inline(always)] @@ -76,50 +40,78 @@ impl R { MULTICORE_SYNC_3_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR27") + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bits()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bits()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bits()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<0> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bits 8:15 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<8> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bits 16:23 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<16> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bits 24:31 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<24> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 108 - 111\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr27](index.html) module"] +#[doc = "Interrupt Processor Target 108 - 111\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr27::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr27::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR27_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR27_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr27::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR27_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr27::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr27::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR27_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr27::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR27_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr28.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr28.rs index 929f551..a6fab06 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr28.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr28.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR28` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR28` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::FieldReader; +pub type DMA_0_R = crate::FieldReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR28_SPEC, u8, u8, 8, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::FieldReader; +pub type DMA_1_R = crate::FieldReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR28_SPEC, u8, u8, 8, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::FieldReader; +pub type DMA_2_R = crate::FieldReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR28_SPEC, u8, u8, 8, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::FieldReader; +pub type DMA_3_R = crate::FieldReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR28_SPEC, u8, u8, 8, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - DMA 0"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { DMA_3_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR28") + .field("dma_0", &format_args!("{}", self.dma_0().bits())) + .field("dma_1", &format_args!("{}", self.dma_1().bits())) + .field("dma_2", &format_args!("{}", self.dma_2().bits())) + .field("dma_3", &format_args!("{}", self.dma_3().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<0> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bits 8:15 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<8> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bits 16:23 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<16> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bits 24:31 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<24> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 112 - 115\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr28](index.html) module"] +#[doc = "Interrupt Processor Target 112 - 115\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr28::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr28::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR28_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR28_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr28::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR28_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr28::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr28::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR28_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr28::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR28_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr29.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr29.rs index a7e7047..77e09cb 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr29.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr29.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR29` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR29` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::FieldReader; +pub type DMA_4_R = crate::FieldReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR29_SPEC, u8, u8, 8, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::FieldReader; +pub type DMA_5_R = crate::FieldReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR29_SPEC, u8, u8, 8, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::FieldReader; +pub type DMA_6_R = crate::FieldReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR29_SPEC, u8, u8, 8, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::FieldReader; +pub type DMA_7_8_R = crate::FieldReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR29_SPEC, u8, u8, 8, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - DMA 4"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { DMA_7_8_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR29") + .field("dma_4", &format_args!("{}", self.dma_4().bits())) + .field("dma_5", &format_args!("{}", self.dma_5().bits())) + .field("dma_6", &format_args!("{}", self.dma_6().bits())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<0> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bits 8:15 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<8> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bits 16:23 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<16> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bits 24:31 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<24> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 116 - 119\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr29](index.html) module"] +#[doc = "Interrupt Processor Target 116 - 119\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr29::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr29::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR29_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR29_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr29::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR29_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr29::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr29::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR29_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr29::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR29_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr3.rs index 2836e5c..0622d98 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr3.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr3.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_ITARGETSR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT12` reader - Interrupt 12"] -pub type INT12_R = crate::FieldReader; +pub type INT12_R = crate::FieldReader; #[doc = "Field `INT12` writer - Interrupt 12"] -pub type INT12_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR3_SPEC, u8, u8, 8, O>; +pub type INT12_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT13` reader - Interrupt 13"] -pub type INT13_R = crate::FieldReader; +pub type INT13_R = crate::FieldReader; #[doc = "Field `INT13` writer - Interrupt 13"] -pub type INT13_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR3_SPEC, u8, u8, 8, O>; +pub type INT13_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT14` reader - Interrupt 14"] -pub type INT14_R = crate::FieldReader; +pub type INT14_R = crate::FieldReader; #[doc = "Field `INT14` writer - Interrupt 14"] -pub type INT14_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR3_SPEC, u8, u8, 8, O>; +pub type INT14_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT15` reader - Interrupt 15"] -pub type INT15_R = crate::FieldReader; +pub type INT15_R = crate::FieldReader; #[doc = "Field `INT15` writer - Interrupt 15"] -pub type INT15_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR3_SPEC, u8, u8, 8, O>; +pub type INT15_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 12"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { INT15_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR3") + .field("int12", &format_args!("{}", self.int12().bits())) + .field("int13", &format_args!("{}", self.int13().bits())) + .field("int14", &format_args!("{}", self.int14().bits())) + .field("int15", &format_args!("{}", self.int15().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 12"] #[inline(always)] #[must_use] - pub fn int12(&mut self) -> INT12_W<0> { + pub fn int12(&mut self) -> INT12_W { INT12_W::new(self) } #[doc = "Bits 8:15 - Interrupt 13"] #[inline(always)] #[must_use] - pub fn int13(&mut self) -> INT13_W<8> { + pub fn int13(&mut self) -> INT13_W { INT13_W::new(self) } #[doc = "Bits 16:23 - Interrupt 14"] #[inline(always)] #[must_use] - pub fn int14(&mut self) -> INT14_W<16> { + pub fn int14(&mut self) -> INT14_W { INT14_W::new(self) } #[doc = "Bits 24:31 - Interrupt 15"] #[inline(always)] #[must_use] - pub fn int15(&mut self) -> INT15_W<24> { + pub fn int15(&mut self) -> INT15_W { INT15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 12 - 15\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr3](index.html) module"] +#[doc = "Interrupt Processor Target 12 - 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR3_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr3::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr3::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr3::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr3::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr30.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr30.rs index 1a9adc4..fdae147 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr30.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr30.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR30` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR30` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::FieldReader; +pub type DMA_9_10_R = crate::FieldReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR30_SPEC, u8, u8, 8, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::FieldReader; +pub type DMA_11_R = crate::FieldReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR30_SPEC, u8, u8, 8, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::FieldReader; +pub type DMA_12_R = crate::FieldReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR30_SPEC, u8, u8, 8, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::FieldReader; +pub type DMA_13_R = crate::FieldReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR30_SPEC, u8, u8, 8, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - OR of DMA 9 and 10"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { DMA_13_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR30") + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bits())) + .field("dma_11", &format_args!("{}", self.dma_11().bits())) + .field("dma_12", &format_args!("{}", self.dma_12().bits())) + .field("dma_13", &format_args!("{}", self.dma_13().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<0> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bits 8:15 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<8> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bits 16:23 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<16> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bits 24:31 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<24> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 120 - 123\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr30](index.html) module"] +#[doc = "Interrupt Processor Target 120 - 123\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr30::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr30::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR30_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR30_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr30::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR30_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr30::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr30::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR30_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr30::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR30_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr31.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr31.rs index 7fec65c..784e82a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr31.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr31.rs @@ -1,57 +1,23 @@ #[doc = "Register `GICD_ITARGETSR31` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR31` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::FieldReader; +pub type DMA_14_R = crate::FieldReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR31_SPEC, u8, u8, 8, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::FieldReader; +pub type AUX_R = crate::FieldReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR31_SPEC, u8, u8, 8, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::FieldReader; +pub type ARM_R = crate::FieldReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR31_SPEC, u8, u8, 8, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::FieldReader; +pub type DMA_15_R = crate::FieldReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR31_SPEC, u8, u8, 8, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - DMA 14"] #[inline(always)] @@ -74,50 +40,66 @@ impl R { DMA_15_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR31") + .field("dma_14", &format_args!("{}", self.dma_14().bits())) + .field("aux", &format_args!("{}", self.aux().bits())) + .field("arm", &format_args!("{}", self.arm().bits())) + .field("dma_15", &format_args!("{}", self.dma_15().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<0> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bits 8:15 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<8> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bits 16:23 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<16> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bits 24:31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<24> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 124 - 127\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr31](index.html) module"] +#[doc = "Interrupt Processor Target 124 - 127\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr31::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr31::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR31_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR31_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr31::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR31_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr31::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr31::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR31_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr31::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR31_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr32.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr32.rs index 6f07c87..9c9ca2a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr32.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr32.rs @@ -1,57 +1,23 @@ #[doc = "Register `GICD_ITARGETSR32` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR32` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::FieldReader; +pub type HDMI_CEC_R = crate::FieldReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR32_SPEC, u8, u8, 8, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::FieldReader; +pub type HVS_R = crate::FieldReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR32_SPEC, u8, u8, 8, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::FieldReader; +pub type RPIVID_R = crate::FieldReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR32_SPEC, u8, u8, 8, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::FieldReader; +pub type SDC_R = crate::FieldReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR32_SPEC, u8, u8, 8, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - HDMI CEC"] #[inline(always)] @@ -74,50 +40,66 @@ impl R { SDC_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR32") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bits())) + .field("hvs", &format_args!("{}", self.hvs().bits())) + .field("rpivid", &format_args!("{}", self.rpivid().bits())) + .field("sdc", &format_args!("{}", self.sdc().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bits 8:15 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<8> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bits 16:23 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<16> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bits 24:31 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<24> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 128 - 131\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr32](index.html) module"] +#[doc = "Interrupt Processor Target 128 - 131\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr32::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr32::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR32_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR32_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr32::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR32_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr32::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr32::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR32_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr32::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR32_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr33.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr33.rs index cc64645..655c559 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr33.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr33.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR33` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR33` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::FieldReader; +pub type DSI_0_R = crate::FieldReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR33_SPEC, u8, u8, 8, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::FieldReader; +pub type PIXEL_VALVE_2_R = crate::FieldReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR33_SPEC, u8, u8, 8, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::FieldReader; +pub type CAMERA_0_R = crate::FieldReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR33_SPEC, u8, u8, 8, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::FieldReader; +pub type CAMERA_1_R = crate::FieldReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR33_SPEC, u8, u8, 8, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - DSI 0"] #[inline(always)] @@ -76,50 +40,69 @@ impl R { CAMERA_1_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR33") + .field("dsi_0", &format_args!("{}", self.dsi_0().bits())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bits()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bits())) + .field("camera_1", &format_args!("{}", self.camera_1().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<0> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bits 8:15 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<8> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bits 16:23 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<16> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bits 24:31 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<24> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 132 - 135\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr33](index.html) module"] +#[doc = "Interrupt Processor Target 132 - 135\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr33::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr33::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR33_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR33_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr33::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR33_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr33::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr33::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR33_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr33::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR33_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr34.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr34.rs index 36c544c..d52fe55 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr34.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr34.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR34` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR34` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::FieldReader; +pub type HDMI_0_R = crate::FieldReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR34_SPEC, u8, u8, 8, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::FieldReader; +pub type HDMI_1_R = crate::FieldReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR34_SPEC, u8, u8, 8, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::FieldReader; +pub type PIXEL_VALVE_3_R = crate::FieldReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR34_SPEC, u8, u8, 8, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::FieldReader; +pub type SPI_BSC_SLAVE_R = crate::FieldReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR34_SPEC, u8, u8, 8, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - HDMI 0"] #[inline(always)] @@ -76,50 +40,72 @@ impl R { SPI_BSC_SLAVE_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR34") + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bits())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bits())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bits()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<0> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bits 8:15 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<8> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bits 16:23 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<16> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bits 24:31 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<24> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 136 - 139\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr34](index.html) module"] +#[doc = "Interrupt Processor Target 136 - 139\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr34::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr34::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR34_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR34_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr34::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR34_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr34::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr34::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR34_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr34::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR34_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr35.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr35.rs index c97c808..7f3f731 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr35.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr35.rs @@ -1,58 +1,23 @@ #[doc = "Register `GICD_ITARGETSR35` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR35` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::FieldReader; +pub type DSI_1_R = crate::FieldReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR35_SPEC, u8, u8, 8, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::FieldReader; +pub type PIXEL_VALVE_0_R = crate::FieldReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR35_SPEC, u8, u8, 8, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::FieldReader; +pub type PIXEL_VALVE_1_2_R = crate::FieldReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR35_SPEC, u8, u8, 8, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::FieldReader; +pub type CPR_R = crate::FieldReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR35_SPEC, u8, u8, 8, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - DSI 1"] #[inline(always)] @@ -75,50 +40,72 @@ impl R { CPR_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR35") + .field("dsi_1", &format_args!("{}", self.dsi_1().bits())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bits()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bits()), + ) + .field("cpr", &format_args!("{}", self.cpr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<0> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bits 8:15 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<8> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bits 16:23 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<16> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bits 24:31 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<24> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 140 - 143\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr35](index.html) module"] +#[doc = "Interrupt Processor Target 140 - 143\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr35::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr35::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR35_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR35_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr35::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR35_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr35::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr35::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR35_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr35::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR35_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr36.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr36.rs index bab42ff..f77fdb6 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr36.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr36.rs @@ -1,58 +1,23 @@ #[doc = "Register `GICD_ITARGETSR36` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR36` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::FieldReader; +pub type SMI_R = crate::FieldReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR36_SPEC, u8, u8, 8, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::FieldReader; +pub type GPIO_0_R = crate::FieldReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR36_SPEC, u8, u8, 8, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::FieldReader; +pub type GPIO_1_R = crate::FieldReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR36_SPEC, u8, u8, 8, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::FieldReader; +pub type GPIO_2_R = crate::FieldReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR36_SPEC, u8, u8, 8, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - SMI"] #[inline(always)] @@ -75,50 +40,66 @@ impl R { GPIO_2_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR36") + .field("smi", &format_args!("{}", self.smi().bits())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bits())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bits())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<0> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bits 8:15 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<8> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bits 16:23 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<16> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bits 24:31 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<24> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 144 - 147\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr36](index.html) module"] +#[doc = "Interrupt Processor Target 144 - 147\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr36::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr36::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR36_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR36_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr36::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR36_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr36::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr36::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR36_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr36::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR36_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr37.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr37.rs index 0142d8e..513c923 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr37.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr37.rs @@ -1,57 +1,23 @@ #[doc = "Register `GICD_ITARGETSR37` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR37` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::FieldReader; +pub type GPIO_3_R = crate::FieldReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR37_SPEC, u8, u8, 8, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::FieldReader; +pub type I2C_R = crate::FieldReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR37_SPEC, u8, u8, 8, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::FieldReader; +pub type SPI_R = crate::FieldReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR37_SPEC, u8, u8, 8, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::FieldReader; +pub type PCM_I2S_R = crate::FieldReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR37_SPEC, u8, u8, 8, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - GPIO 3"] #[inline(always)] @@ -74,50 +40,66 @@ impl R { PCM_I2S_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR37") + .field("gpio_3", &format_args!("{}", self.gpio_3().bits())) + .field("i2c", &format_args!("{}", self.i2c().bits())) + .field("spi", &format_args!("{}", self.spi().bits())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<0> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bits 8:15 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<8> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bits 16:23 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<16> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bits 24:31 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<24> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 148 - 151\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr37](index.html) module"] +#[doc = "Interrupt Processor Target 148 - 151\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr37::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr37::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR37_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR37_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr37::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR37_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr37::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr37::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR37_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr37::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR37_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr38.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr38.rs index 9cb7a0d..7e9fc43 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr38.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr38.rs @@ -1,57 +1,23 @@ #[doc = "Register `GICD_ITARGETSR38` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR38` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::FieldReader; +pub type SDHOST_R = crate::FieldReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR38_SPEC, u8, u8, 8, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::FieldReader; +pub type UART_R = crate::FieldReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR38_SPEC, u8, u8, 8, O>; +pub type UART_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::FieldReader; +pub type ETH_PCIE_R = crate::FieldReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR38_SPEC, u8, u8, 8, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::FieldReader; +pub type VEC_R = crate::FieldReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR38_SPEC, u8, u8, 8, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - SDHOST"] #[inline(always)] @@ -74,50 +40,66 @@ impl R { VEC_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR38") + .field("sdhost", &format_args!("{}", self.sdhost().bits())) + .field("uart", &format_args!("{}", self.uart().bits())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bits())) + .field("vec", &format_args!("{}", self.vec().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<0> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bits 8:15 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<8> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bits 16:23 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<16> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bits 24:31 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<24> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 152 - 155\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr38](index.html) module"] +#[doc = "Interrupt Processor Target 152 - 155\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr38::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr38::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR38_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR38_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr38::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR38_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr38::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr38::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR38_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr38::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR38_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr39.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr39.rs index a63e3b8..7ea4832 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr39.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr39.rs @@ -1,56 +1,23 @@ #[doc = "Register `GICD_ITARGETSR39` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR39` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::FieldReader; +pub type CPG_R = crate::FieldReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR39_SPEC, u8, u8, 8, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::FieldReader; +pub type RNG_R = crate::FieldReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR39_SPEC, u8, u8, 8, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::FieldReader; +pub type EMMC_R = crate::FieldReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR39_SPEC, u8, u8, 8, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::FieldReader; +pub type ETH_PCIE_SECURE_R = crate::FieldReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR39_SPEC, u8, u8, 8, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - CPG"] #[inline(always)] @@ -73,50 +40,69 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR39") + .field("cpg", &format_args!("{}", self.cpg().bits())) + .field("rng", &format_args!("{}", self.rng().bits())) + .field("emmc", &format_args!("{}", self.emmc().bits())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<0> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bits 8:15 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<8> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bits 16:23 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<16> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bits 24:31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<24> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 156 - 159\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr39](index.html) module"] +#[doc = "Interrupt Processor Target 156 - 159\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr39::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr39::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR39_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR39_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr39::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR39_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr39::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr39::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR39_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr39::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR39_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr4.rs index 1c16cfd..b852a7f 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr4.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr4.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_ITARGETSR4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT16` reader - Interrupt 16"] -pub type INT16_R = crate::FieldReader; +pub type INT16_R = crate::FieldReader; #[doc = "Field `INT16` writer - Interrupt 16"] -pub type INT16_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR4_SPEC, u8, u8, 8, O>; +pub type INT16_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT17` reader - Interrupt 17"] -pub type INT17_R = crate::FieldReader; +pub type INT17_R = crate::FieldReader; #[doc = "Field `INT17` writer - Interrupt 17"] -pub type INT17_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR4_SPEC, u8, u8, 8, O>; +pub type INT17_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT18` reader - Interrupt 18"] -pub type INT18_R = crate::FieldReader; +pub type INT18_R = crate::FieldReader; #[doc = "Field `INT18` writer - Interrupt 18"] -pub type INT18_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR4_SPEC, u8, u8, 8, O>; +pub type INT18_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT19` reader - Interrupt 19"] -pub type INT19_R = crate::FieldReader; +pub type INT19_R = crate::FieldReader; #[doc = "Field `INT19` writer - Interrupt 19"] -pub type INT19_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR4_SPEC, u8, u8, 8, O>; +pub type INT19_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 16"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { INT19_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR4") + .field("int16", &format_args!("{}", self.int16().bits())) + .field("int17", &format_args!("{}", self.int17().bits())) + .field("int18", &format_args!("{}", self.int18().bits())) + .field("int19", &format_args!("{}", self.int19().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 16"] #[inline(always)] #[must_use] - pub fn int16(&mut self) -> INT16_W<0> { + pub fn int16(&mut self) -> INT16_W { INT16_W::new(self) } #[doc = "Bits 8:15 - Interrupt 17"] #[inline(always)] #[must_use] - pub fn int17(&mut self) -> INT17_W<8> { + pub fn int17(&mut self) -> INT17_W { INT17_W::new(self) } #[doc = "Bits 16:23 - Interrupt 18"] #[inline(always)] #[must_use] - pub fn int18(&mut self) -> INT18_W<16> { + pub fn int18(&mut self) -> INT18_W { INT18_W::new(self) } #[doc = "Bits 24:31 - Interrupt 19"] #[inline(always)] #[must_use] - pub fn int19(&mut self) -> INT19_W<24> { + pub fn int19(&mut self) -> INT19_W { INT19_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 16 - 19\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr4](index.html) module"] +#[doc = "Interrupt Processor Target 16 - 19\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR4_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr4::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr4::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr4::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr4::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr40.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr40.rs index 405eeb4..1390830 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr40.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr40.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR40` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR40` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT160` reader - Interrupt 160"] -pub type INT160_R = crate::FieldReader; +pub type INT160_R = crate::FieldReader; #[doc = "Field `INT160` writer - Interrupt 160"] -pub type INT160_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR40_SPEC, u8, u8, 8, O>; +pub type INT160_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT161` reader - Interrupt 161"] -pub type INT161_R = crate::FieldReader; +pub type INT161_R = crate::FieldReader; #[doc = "Field `INT161` writer - Interrupt 161"] -pub type INT161_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR40_SPEC, u8, u8, 8, O>; +pub type INT161_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT162` reader - Interrupt 162"] -pub type INT162_R = crate::FieldReader; +pub type INT162_R = crate::FieldReader; #[doc = "Field `INT162` writer - Interrupt 162"] -pub type INT162_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR40_SPEC, u8, u8, 8, O>; +pub type INT162_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT163` reader - Interrupt 163"] -pub type INT163_R = crate::FieldReader; +pub type INT163_R = crate::FieldReader; #[doc = "Field `INT163` writer - Interrupt 163"] -pub type INT163_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR40_SPEC, u8, u8, 8, O>; +pub type INT163_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 160"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT163_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR40") + .field("int160", &format_args!("{}", self.int160().bits())) + .field("int161", &format_args!("{}", self.int161().bits())) + .field("int162", &format_args!("{}", self.int162().bits())) + .field("int163", &format_args!("{}", self.int163().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 160"] #[inline(always)] #[must_use] - pub fn int160(&mut self) -> INT160_W<0> { + pub fn int160(&mut self) -> INT160_W { INT160_W::new(self) } #[doc = "Bits 8:15 - Interrupt 161"] #[inline(always)] #[must_use] - pub fn int161(&mut self) -> INT161_W<8> { + pub fn int161(&mut self) -> INT161_W { INT161_W::new(self) } #[doc = "Bits 16:23 - Interrupt 162"] #[inline(always)] #[must_use] - pub fn int162(&mut self) -> INT162_W<16> { + pub fn int162(&mut self) -> INT162_W { INT162_W::new(self) } #[doc = "Bits 24:31 - Interrupt 163"] #[inline(always)] #[must_use] - pub fn int163(&mut self) -> INT163_W<24> { + pub fn int163(&mut self) -> INT163_W { INT163_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 160 - 163\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr40](index.html) module"] +#[doc = "Interrupt Processor Target 160 - 163\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr40::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr40::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR40_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR40_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr40::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR40_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr40::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr40::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR40_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr40::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR40_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr41.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr41.rs index 4cf2746..45af0b2 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr41.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr41.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR41` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR41` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT164` reader - Interrupt 164"] -pub type INT164_R = crate::FieldReader; +pub type INT164_R = crate::FieldReader; #[doc = "Field `INT164` writer - Interrupt 164"] -pub type INT164_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR41_SPEC, u8, u8, 8, O>; +pub type INT164_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT165` reader - Interrupt 165"] -pub type INT165_R = crate::FieldReader; +pub type INT165_R = crate::FieldReader; #[doc = "Field `INT165` writer - Interrupt 165"] -pub type INT165_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR41_SPEC, u8, u8, 8, O>; +pub type INT165_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT166` reader - Interrupt 166"] -pub type INT166_R = crate::FieldReader; +pub type INT166_R = crate::FieldReader; #[doc = "Field `INT166` writer - Interrupt 166"] -pub type INT166_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR41_SPEC, u8, u8, 8, O>; +pub type INT166_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT167` reader - Interrupt 167"] -pub type INT167_R = crate::FieldReader; +pub type INT167_R = crate::FieldReader; #[doc = "Field `INT167` writer - Interrupt 167"] -pub type INT167_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR41_SPEC, u8, u8, 8, O>; +pub type INT167_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 164"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT167_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR41") + .field("int164", &format_args!("{}", self.int164().bits())) + .field("int165", &format_args!("{}", self.int165().bits())) + .field("int166", &format_args!("{}", self.int166().bits())) + .field("int167", &format_args!("{}", self.int167().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 164"] #[inline(always)] #[must_use] - pub fn int164(&mut self) -> INT164_W<0> { + pub fn int164(&mut self) -> INT164_W { INT164_W::new(self) } #[doc = "Bits 8:15 - Interrupt 165"] #[inline(always)] #[must_use] - pub fn int165(&mut self) -> INT165_W<8> { + pub fn int165(&mut self) -> INT165_W { INT165_W::new(self) } #[doc = "Bits 16:23 - Interrupt 166"] #[inline(always)] #[must_use] - pub fn int166(&mut self) -> INT166_W<16> { + pub fn int166(&mut self) -> INT166_W { INT166_W::new(self) } #[doc = "Bits 24:31 - Interrupt 167"] #[inline(always)] #[must_use] - pub fn int167(&mut self) -> INT167_W<24> { + pub fn int167(&mut self) -> INT167_W { INT167_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 164 - 167\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr41](index.html) module"] +#[doc = "Interrupt Processor Target 164 - 167\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr41::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr41::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR41_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR41_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr41::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR41_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr41::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr41::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR41_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr41::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR41_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr42.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr42.rs index 7aafb04..9dc320c 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr42.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr42.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR42` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR42` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT168` reader - Interrupt 168"] -pub type INT168_R = crate::FieldReader; +pub type INT168_R = crate::FieldReader; #[doc = "Field `INT168` writer - Interrupt 168"] -pub type INT168_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR42_SPEC, u8, u8, 8, O>; +pub type INT168_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT169` reader - Interrupt 169"] -pub type INT169_R = crate::FieldReader; +pub type INT169_R = crate::FieldReader; #[doc = "Field `INT169` writer - Interrupt 169"] -pub type INT169_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR42_SPEC, u8, u8, 8, O>; +pub type INT169_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT170` reader - Interrupt 170"] -pub type INT170_R = crate::FieldReader; +pub type INT170_R = crate::FieldReader; #[doc = "Field `INT170` writer - Interrupt 170"] -pub type INT170_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR42_SPEC, u8, u8, 8, O>; +pub type INT170_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT171` reader - Interrupt 171"] -pub type INT171_R = crate::FieldReader; +pub type INT171_R = crate::FieldReader; #[doc = "Field `INT171` writer - Interrupt 171"] -pub type INT171_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR42_SPEC, u8, u8, 8, O>; +pub type INT171_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 168"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT171_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR42") + .field("int168", &format_args!("{}", self.int168().bits())) + .field("int169", &format_args!("{}", self.int169().bits())) + .field("int170", &format_args!("{}", self.int170().bits())) + .field("int171", &format_args!("{}", self.int171().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 168"] #[inline(always)] #[must_use] - pub fn int168(&mut self) -> INT168_W<0> { + pub fn int168(&mut self) -> INT168_W { INT168_W::new(self) } #[doc = "Bits 8:15 - Interrupt 169"] #[inline(always)] #[must_use] - pub fn int169(&mut self) -> INT169_W<8> { + pub fn int169(&mut self) -> INT169_W { INT169_W::new(self) } #[doc = "Bits 16:23 - Interrupt 170"] #[inline(always)] #[must_use] - pub fn int170(&mut self) -> INT170_W<16> { + pub fn int170(&mut self) -> INT170_W { INT170_W::new(self) } #[doc = "Bits 24:31 - Interrupt 171"] #[inline(always)] #[must_use] - pub fn int171(&mut self) -> INT171_W<24> { + pub fn int171(&mut self) -> INT171_W { INT171_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 168 - 171\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr42](index.html) module"] +#[doc = "Interrupt Processor Target 168 - 171\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr42::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr42::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR42_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR42_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr42::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR42_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr42::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr42::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR42_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr42::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR42_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr43.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr43.rs index 9544198..7699124 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr43.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr43.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR43` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR43` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT172` reader - Interrupt 172"] -pub type INT172_R = crate::FieldReader; +pub type INT172_R = crate::FieldReader; #[doc = "Field `INT172` writer - Interrupt 172"] -pub type INT172_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR43_SPEC, u8, u8, 8, O>; +pub type INT172_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT173` reader - Interrupt 173"] -pub type INT173_R = crate::FieldReader; +pub type INT173_R = crate::FieldReader; #[doc = "Field `INT173` writer - Interrupt 173"] -pub type INT173_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR43_SPEC, u8, u8, 8, O>; +pub type INT173_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT174` reader - Interrupt 174"] -pub type INT174_R = crate::FieldReader; +pub type INT174_R = crate::FieldReader; #[doc = "Field `INT174` writer - Interrupt 174"] -pub type INT174_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR43_SPEC, u8, u8, 8, O>; +pub type INT174_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT175` reader - Interrupt 175"] -pub type INT175_R = crate::FieldReader; +pub type INT175_R = crate::FieldReader; #[doc = "Field `INT175` writer - Interrupt 175"] -pub type INT175_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR43_SPEC, u8, u8, 8, O>; +pub type INT175_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 172"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT175_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR43") + .field("int172", &format_args!("{}", self.int172().bits())) + .field("int173", &format_args!("{}", self.int173().bits())) + .field("int174", &format_args!("{}", self.int174().bits())) + .field("int175", &format_args!("{}", self.int175().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 172"] #[inline(always)] #[must_use] - pub fn int172(&mut self) -> INT172_W<0> { + pub fn int172(&mut self) -> INT172_W { INT172_W::new(self) } #[doc = "Bits 8:15 - Interrupt 173"] #[inline(always)] #[must_use] - pub fn int173(&mut self) -> INT173_W<8> { + pub fn int173(&mut self) -> INT173_W { INT173_W::new(self) } #[doc = "Bits 16:23 - Interrupt 174"] #[inline(always)] #[must_use] - pub fn int174(&mut self) -> INT174_W<16> { + pub fn int174(&mut self) -> INT174_W { INT174_W::new(self) } #[doc = "Bits 24:31 - Interrupt 175"] #[inline(always)] #[must_use] - pub fn int175(&mut self) -> INT175_W<24> { + pub fn int175(&mut self) -> INT175_W { INT175_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 172 - 175\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr43](index.html) module"] +#[doc = "Interrupt Processor Target 172 - 175\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr43::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr43::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR43_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR43_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr43::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR43_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr43::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr43::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR43_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr43::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR43_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr44.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr44.rs index fb06269..72f5c65 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr44.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr44.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR44` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR44` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT176` reader - Interrupt 176"] -pub type INT176_R = crate::FieldReader; +pub type INT176_R = crate::FieldReader; #[doc = "Field `INT176` writer - Interrupt 176"] -pub type INT176_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR44_SPEC, u8, u8, 8, O>; +pub type INT176_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT177` reader - Interrupt 177"] -pub type INT177_R = crate::FieldReader; +pub type INT177_R = crate::FieldReader; #[doc = "Field `INT177` writer - Interrupt 177"] -pub type INT177_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR44_SPEC, u8, u8, 8, O>; +pub type INT177_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT178` reader - Interrupt 178"] -pub type INT178_R = crate::FieldReader; +pub type INT178_R = crate::FieldReader; #[doc = "Field `INT178` writer - Interrupt 178"] -pub type INT178_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR44_SPEC, u8, u8, 8, O>; +pub type INT178_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT179` reader - Interrupt 179"] -pub type INT179_R = crate::FieldReader; +pub type INT179_R = crate::FieldReader; #[doc = "Field `INT179` writer - Interrupt 179"] -pub type INT179_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR44_SPEC, u8, u8, 8, O>; +pub type INT179_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 176"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT179_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR44") + .field("int176", &format_args!("{}", self.int176().bits())) + .field("int177", &format_args!("{}", self.int177().bits())) + .field("int178", &format_args!("{}", self.int178().bits())) + .field("int179", &format_args!("{}", self.int179().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 176"] #[inline(always)] #[must_use] - pub fn int176(&mut self) -> INT176_W<0> { + pub fn int176(&mut self) -> INT176_W { INT176_W::new(self) } #[doc = "Bits 8:15 - Interrupt 177"] #[inline(always)] #[must_use] - pub fn int177(&mut self) -> INT177_W<8> { + pub fn int177(&mut self) -> INT177_W { INT177_W::new(self) } #[doc = "Bits 16:23 - Interrupt 178"] #[inline(always)] #[must_use] - pub fn int178(&mut self) -> INT178_W<16> { + pub fn int178(&mut self) -> INT178_W { INT178_W::new(self) } #[doc = "Bits 24:31 - Interrupt 179"] #[inline(always)] #[must_use] - pub fn int179(&mut self) -> INT179_W<24> { + pub fn int179(&mut self) -> INT179_W { INT179_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 176 - 179\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr44](index.html) module"] +#[doc = "Interrupt Processor Target 176 - 179\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr44::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr44::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR44_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR44_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr44::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR44_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr44::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr44::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR44_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr44::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR44_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr45.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr45.rs index 38d0d32..4e77f6a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr45.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr45.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR45` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR45` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT180` reader - Interrupt 180"] -pub type INT180_R = crate::FieldReader; +pub type INT180_R = crate::FieldReader; #[doc = "Field `INT180` writer - Interrupt 180"] -pub type INT180_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR45_SPEC, u8, u8, 8, O>; +pub type INT180_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT181` reader - Interrupt 181"] -pub type INT181_R = crate::FieldReader; +pub type INT181_R = crate::FieldReader; #[doc = "Field `INT181` writer - Interrupt 181"] -pub type INT181_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR45_SPEC, u8, u8, 8, O>; +pub type INT181_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT182` reader - Interrupt 182"] -pub type INT182_R = crate::FieldReader; +pub type INT182_R = crate::FieldReader; #[doc = "Field `INT182` writer - Interrupt 182"] -pub type INT182_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR45_SPEC, u8, u8, 8, O>; +pub type INT182_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT183` reader - Interrupt 183"] -pub type INT183_R = crate::FieldReader; +pub type INT183_R = crate::FieldReader; #[doc = "Field `INT183` writer - Interrupt 183"] -pub type INT183_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR45_SPEC, u8, u8, 8, O>; +pub type INT183_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 180"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT183_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR45") + .field("int180", &format_args!("{}", self.int180().bits())) + .field("int181", &format_args!("{}", self.int181().bits())) + .field("int182", &format_args!("{}", self.int182().bits())) + .field("int183", &format_args!("{}", self.int183().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 180"] #[inline(always)] #[must_use] - pub fn int180(&mut self) -> INT180_W<0> { + pub fn int180(&mut self) -> INT180_W { INT180_W::new(self) } #[doc = "Bits 8:15 - Interrupt 181"] #[inline(always)] #[must_use] - pub fn int181(&mut self) -> INT181_W<8> { + pub fn int181(&mut self) -> INT181_W { INT181_W::new(self) } #[doc = "Bits 16:23 - Interrupt 182"] #[inline(always)] #[must_use] - pub fn int182(&mut self) -> INT182_W<16> { + pub fn int182(&mut self) -> INT182_W { INT182_W::new(self) } #[doc = "Bits 24:31 - Interrupt 183"] #[inline(always)] #[must_use] - pub fn int183(&mut self) -> INT183_W<24> { + pub fn int183(&mut self) -> INT183_W { INT183_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 180 - 183\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr45](index.html) module"] +#[doc = "Interrupt Processor Target 180 - 183\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr45::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr45::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR45_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR45_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr45::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR45_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr45::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr45::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR45_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr45::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR45_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr46.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr46.rs index 2bbf68c..e698c81 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr46.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr46.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR46` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR46` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT184` reader - Interrupt 184"] -pub type INT184_R = crate::FieldReader; +pub type INT184_R = crate::FieldReader; #[doc = "Field `INT184` writer - Interrupt 184"] -pub type INT184_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR46_SPEC, u8, u8, 8, O>; +pub type INT184_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT185` reader - Interrupt 185"] -pub type INT185_R = crate::FieldReader; +pub type INT185_R = crate::FieldReader; #[doc = "Field `INT185` writer - Interrupt 185"] -pub type INT185_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR46_SPEC, u8, u8, 8, O>; +pub type INT185_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT186` reader - Interrupt 186"] -pub type INT186_R = crate::FieldReader; +pub type INT186_R = crate::FieldReader; #[doc = "Field `INT186` writer - Interrupt 186"] -pub type INT186_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR46_SPEC, u8, u8, 8, O>; +pub type INT186_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT187` reader - Interrupt 187"] -pub type INT187_R = crate::FieldReader; +pub type INT187_R = crate::FieldReader; #[doc = "Field `INT187` writer - Interrupt 187"] -pub type INT187_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR46_SPEC, u8, u8, 8, O>; +pub type INT187_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 184"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT187_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR46") + .field("int184", &format_args!("{}", self.int184().bits())) + .field("int185", &format_args!("{}", self.int185().bits())) + .field("int186", &format_args!("{}", self.int186().bits())) + .field("int187", &format_args!("{}", self.int187().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 184"] #[inline(always)] #[must_use] - pub fn int184(&mut self) -> INT184_W<0> { + pub fn int184(&mut self) -> INT184_W { INT184_W::new(self) } #[doc = "Bits 8:15 - Interrupt 185"] #[inline(always)] #[must_use] - pub fn int185(&mut self) -> INT185_W<8> { + pub fn int185(&mut self) -> INT185_W { INT185_W::new(self) } #[doc = "Bits 16:23 - Interrupt 186"] #[inline(always)] #[must_use] - pub fn int186(&mut self) -> INT186_W<16> { + pub fn int186(&mut self) -> INT186_W { INT186_W::new(self) } #[doc = "Bits 24:31 - Interrupt 187"] #[inline(always)] #[must_use] - pub fn int187(&mut self) -> INT187_W<24> { + pub fn int187(&mut self) -> INT187_W { INT187_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 184 - 187\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr46](index.html) module"] +#[doc = "Interrupt Processor Target 184 - 187\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr46::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr46::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR46_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR46_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr46::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR46_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr46::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr46::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR46_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr46::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR46_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr47.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr47.rs index ae06a37..635bbe5 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr47.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr47.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR47` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR47` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT188` reader - Interrupt 188"] -pub type INT188_R = crate::FieldReader; +pub type INT188_R = crate::FieldReader; #[doc = "Field `INT188` writer - Interrupt 188"] -pub type INT188_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR47_SPEC, u8, u8, 8, O>; +pub type INT188_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT189` reader - Interrupt 189"] -pub type INT189_R = crate::FieldReader; +pub type INT189_R = crate::FieldReader; #[doc = "Field `INT189` writer - Interrupt 189"] -pub type INT189_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR47_SPEC, u8, u8, 8, O>; +pub type INT189_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT190` reader - Interrupt 190"] -pub type INT190_R = crate::FieldReader; +pub type INT190_R = crate::FieldReader; #[doc = "Field `INT190` writer - Interrupt 190"] -pub type INT190_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR47_SPEC, u8, u8, 8, O>; +pub type INT190_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT191` reader - Interrupt 191"] -pub type INT191_R = crate::FieldReader; +pub type INT191_R = crate::FieldReader; #[doc = "Field `INT191` writer - Interrupt 191"] -pub type INT191_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR47_SPEC, u8, u8, 8, O>; +pub type INT191_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 188"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT191_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR47") + .field("int188", &format_args!("{}", self.int188().bits())) + .field("int189", &format_args!("{}", self.int189().bits())) + .field("int190", &format_args!("{}", self.int190().bits())) + .field("int191", &format_args!("{}", self.int191().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 188"] #[inline(always)] #[must_use] - pub fn int188(&mut self) -> INT188_W<0> { + pub fn int188(&mut self) -> INT188_W { INT188_W::new(self) } #[doc = "Bits 8:15 - Interrupt 189"] #[inline(always)] #[must_use] - pub fn int189(&mut self) -> INT189_W<8> { + pub fn int189(&mut self) -> INT189_W { INT189_W::new(self) } #[doc = "Bits 16:23 - Interrupt 190"] #[inline(always)] #[must_use] - pub fn int190(&mut self) -> INT190_W<16> { + pub fn int190(&mut self) -> INT190_W { INT190_W::new(self) } #[doc = "Bits 24:31 - Interrupt 191"] #[inline(always)] #[must_use] - pub fn int191(&mut self) -> INT191_W<24> { + pub fn int191(&mut self) -> INT191_W { INT191_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 188 - 191\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr47](index.html) module"] +#[doc = "Interrupt Processor Target 188 - 191\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr47::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr47::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR47_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR47_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr47::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR47_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr47::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr47::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR47_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr47::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR47_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr48.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr48.rs index aa5a789..81d71d9 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr48.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr48.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR48` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR48` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT192` reader - Interrupt 192"] -pub type INT192_R = crate::FieldReader; +pub type INT192_R = crate::FieldReader; #[doc = "Field `INT192` writer - Interrupt 192"] -pub type INT192_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR48_SPEC, u8, u8, 8, O>; +pub type INT192_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT193` reader - Interrupt 193"] -pub type INT193_R = crate::FieldReader; +pub type INT193_R = crate::FieldReader; #[doc = "Field `INT193` writer - Interrupt 193"] -pub type INT193_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR48_SPEC, u8, u8, 8, O>; +pub type INT193_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT194` reader - Interrupt 194"] -pub type INT194_R = crate::FieldReader; +pub type INT194_R = crate::FieldReader; #[doc = "Field `INT194` writer - Interrupt 194"] -pub type INT194_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR48_SPEC, u8, u8, 8, O>; +pub type INT194_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT195` reader - Interrupt 195"] -pub type INT195_R = crate::FieldReader; +pub type INT195_R = crate::FieldReader; #[doc = "Field `INT195` writer - Interrupt 195"] -pub type INT195_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR48_SPEC, u8, u8, 8, O>; +pub type INT195_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 192"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT195_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR48") + .field("int192", &format_args!("{}", self.int192().bits())) + .field("int193", &format_args!("{}", self.int193().bits())) + .field("int194", &format_args!("{}", self.int194().bits())) + .field("int195", &format_args!("{}", self.int195().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 192"] #[inline(always)] #[must_use] - pub fn int192(&mut self) -> INT192_W<0> { + pub fn int192(&mut self) -> INT192_W { INT192_W::new(self) } #[doc = "Bits 8:15 - Interrupt 193"] #[inline(always)] #[must_use] - pub fn int193(&mut self) -> INT193_W<8> { + pub fn int193(&mut self) -> INT193_W { INT193_W::new(self) } #[doc = "Bits 16:23 - Interrupt 194"] #[inline(always)] #[must_use] - pub fn int194(&mut self) -> INT194_W<16> { + pub fn int194(&mut self) -> INT194_W { INT194_W::new(self) } #[doc = "Bits 24:31 - Interrupt 195"] #[inline(always)] #[must_use] - pub fn int195(&mut self) -> INT195_W<24> { + pub fn int195(&mut self) -> INT195_W { INT195_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 192 - 195\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr48](index.html) module"] +#[doc = "Interrupt Processor Target 192 - 195\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr48::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr48::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR48_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR48_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr48::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR48_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr48::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr48::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR48_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr48::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR48_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr49.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr49.rs index 521fdd6..1aaf425 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr49.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr49.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR49` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR49` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT196` reader - Interrupt 196"] -pub type INT196_R = crate::FieldReader; +pub type INT196_R = crate::FieldReader; #[doc = "Field `INT196` writer - Interrupt 196"] -pub type INT196_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR49_SPEC, u8, u8, 8, O>; +pub type INT196_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT197` reader - Interrupt 197"] -pub type INT197_R = crate::FieldReader; +pub type INT197_R = crate::FieldReader; #[doc = "Field `INT197` writer - Interrupt 197"] -pub type INT197_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR49_SPEC, u8, u8, 8, O>; +pub type INT197_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT198` reader - Interrupt 198"] -pub type INT198_R = crate::FieldReader; +pub type INT198_R = crate::FieldReader; #[doc = "Field `INT198` writer - Interrupt 198"] -pub type INT198_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR49_SPEC, u8, u8, 8, O>; +pub type INT198_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT199` reader - Interrupt 199"] -pub type INT199_R = crate::FieldReader; +pub type INT199_R = crate::FieldReader; #[doc = "Field `INT199` writer - Interrupt 199"] -pub type INT199_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR49_SPEC, u8, u8, 8, O>; +pub type INT199_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 196"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT199_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR49") + .field("int196", &format_args!("{}", self.int196().bits())) + .field("int197", &format_args!("{}", self.int197().bits())) + .field("int198", &format_args!("{}", self.int198().bits())) + .field("int199", &format_args!("{}", self.int199().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 196"] #[inline(always)] #[must_use] - pub fn int196(&mut self) -> INT196_W<0> { + pub fn int196(&mut self) -> INT196_W { INT196_W::new(self) } #[doc = "Bits 8:15 - Interrupt 197"] #[inline(always)] #[must_use] - pub fn int197(&mut self) -> INT197_W<8> { + pub fn int197(&mut self) -> INT197_W { INT197_W::new(self) } #[doc = "Bits 16:23 - Interrupt 198"] #[inline(always)] #[must_use] - pub fn int198(&mut self) -> INT198_W<16> { + pub fn int198(&mut self) -> INT198_W { INT198_W::new(self) } #[doc = "Bits 24:31 - Interrupt 199"] #[inline(always)] #[must_use] - pub fn int199(&mut self) -> INT199_W<24> { + pub fn int199(&mut self) -> INT199_W { INT199_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 196 - 199\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr49](index.html) module"] +#[doc = "Interrupt Processor Target 196 - 199\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr49::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr49::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR49_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR49_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr49::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR49_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr49::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr49::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR49_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr49::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR49_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr5.rs index 4392dd7..f1c6b39 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr5.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr5.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_ITARGETSR5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT20` reader - Interrupt 20"] -pub type INT20_R = crate::FieldReader; +pub type INT20_R = crate::FieldReader; #[doc = "Field `INT20` writer - Interrupt 20"] -pub type INT20_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR5_SPEC, u8, u8, 8, O>; +pub type INT20_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT21` reader - Interrupt 21"] -pub type INT21_R = crate::FieldReader; +pub type INT21_R = crate::FieldReader; #[doc = "Field `INT21` writer - Interrupt 21"] -pub type INT21_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR5_SPEC, u8, u8, 8, O>; +pub type INT21_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT22` reader - Interrupt 22"] -pub type INT22_R = crate::FieldReader; +pub type INT22_R = crate::FieldReader; #[doc = "Field `INT22` writer - Interrupt 22"] -pub type INT22_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR5_SPEC, u8, u8, 8, O>; +pub type INT22_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT23` reader - Interrupt 23"] -pub type INT23_R = crate::FieldReader; +pub type INT23_R = crate::FieldReader; #[doc = "Field `INT23` writer - Interrupt 23"] -pub type INT23_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR5_SPEC, u8, u8, 8, O>; +pub type INT23_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 20"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { INT23_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR5") + .field("int20", &format_args!("{}", self.int20().bits())) + .field("int21", &format_args!("{}", self.int21().bits())) + .field("int22", &format_args!("{}", self.int22().bits())) + .field("int23", &format_args!("{}", self.int23().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 20"] #[inline(always)] #[must_use] - pub fn int20(&mut self) -> INT20_W<0> { + pub fn int20(&mut self) -> INT20_W { INT20_W::new(self) } #[doc = "Bits 8:15 - Interrupt 21"] #[inline(always)] #[must_use] - pub fn int21(&mut self) -> INT21_W<8> { + pub fn int21(&mut self) -> INT21_W { INT21_W::new(self) } #[doc = "Bits 16:23 - Interrupt 22"] #[inline(always)] #[must_use] - pub fn int22(&mut self) -> INT22_W<16> { + pub fn int22(&mut self) -> INT22_W { INT22_W::new(self) } #[doc = "Bits 24:31 - Interrupt 23"] #[inline(always)] #[must_use] - pub fn int23(&mut self) -> INT23_W<24> { + pub fn int23(&mut self) -> INT23_W { INT23_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 20 - 23\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr5](index.html) module"] +#[doc = "Interrupt Processor Target 20 - 23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR5_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr5::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr5::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr5::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr5::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr50.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr50.rs index 50c0b1c..00e5d50 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr50.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr50.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR50` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR50` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT200` reader - Interrupt 200"] -pub type INT200_R = crate::FieldReader; +pub type INT200_R = crate::FieldReader; #[doc = "Field `INT200` writer - Interrupt 200"] -pub type INT200_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR50_SPEC, u8, u8, 8, O>; +pub type INT200_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT201` reader - Interrupt 201"] -pub type INT201_R = crate::FieldReader; +pub type INT201_R = crate::FieldReader; #[doc = "Field `INT201` writer - Interrupt 201"] -pub type INT201_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR50_SPEC, u8, u8, 8, O>; +pub type INT201_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT202` reader - Interrupt 202"] -pub type INT202_R = crate::FieldReader; +pub type INT202_R = crate::FieldReader; #[doc = "Field `INT202` writer - Interrupt 202"] -pub type INT202_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR50_SPEC, u8, u8, 8, O>; +pub type INT202_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT203` reader - Interrupt 203"] -pub type INT203_R = crate::FieldReader; +pub type INT203_R = crate::FieldReader; #[doc = "Field `INT203` writer - Interrupt 203"] -pub type INT203_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR50_SPEC, u8, u8, 8, O>; +pub type INT203_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 200"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT203_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR50") + .field("int200", &format_args!("{}", self.int200().bits())) + .field("int201", &format_args!("{}", self.int201().bits())) + .field("int202", &format_args!("{}", self.int202().bits())) + .field("int203", &format_args!("{}", self.int203().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 200"] #[inline(always)] #[must_use] - pub fn int200(&mut self) -> INT200_W<0> { + pub fn int200(&mut self) -> INT200_W { INT200_W::new(self) } #[doc = "Bits 8:15 - Interrupt 201"] #[inline(always)] #[must_use] - pub fn int201(&mut self) -> INT201_W<8> { + pub fn int201(&mut self) -> INT201_W { INT201_W::new(self) } #[doc = "Bits 16:23 - Interrupt 202"] #[inline(always)] #[must_use] - pub fn int202(&mut self) -> INT202_W<16> { + pub fn int202(&mut self) -> INT202_W { INT202_W::new(self) } #[doc = "Bits 24:31 - Interrupt 203"] #[inline(always)] #[must_use] - pub fn int203(&mut self) -> INT203_W<24> { + pub fn int203(&mut self) -> INT203_W { INT203_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 200 - 203\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr50](index.html) module"] +#[doc = "Interrupt Processor Target 200 - 203\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr50::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr50::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR50_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR50_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr50::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR50_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr50::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr50::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR50_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr50::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR50_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr51.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr51.rs index 4fc2ee2..dc25b0a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr51.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr51.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR51` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR51` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT204` reader - Interrupt 204"] -pub type INT204_R = crate::FieldReader; +pub type INT204_R = crate::FieldReader; #[doc = "Field `INT204` writer - Interrupt 204"] -pub type INT204_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR51_SPEC, u8, u8, 8, O>; +pub type INT204_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT205` reader - Interrupt 205"] -pub type INT205_R = crate::FieldReader; +pub type INT205_R = crate::FieldReader; #[doc = "Field `INT205` writer - Interrupt 205"] -pub type INT205_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR51_SPEC, u8, u8, 8, O>; +pub type INT205_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT206` reader - Interrupt 206"] -pub type INT206_R = crate::FieldReader; +pub type INT206_R = crate::FieldReader; #[doc = "Field `INT206` writer - Interrupt 206"] -pub type INT206_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR51_SPEC, u8, u8, 8, O>; +pub type INT206_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT207` reader - Interrupt 207"] -pub type INT207_R = crate::FieldReader; +pub type INT207_R = crate::FieldReader; #[doc = "Field `INT207` writer - Interrupt 207"] -pub type INT207_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR51_SPEC, u8, u8, 8, O>; +pub type INT207_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 204"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT207_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR51") + .field("int204", &format_args!("{}", self.int204().bits())) + .field("int205", &format_args!("{}", self.int205().bits())) + .field("int206", &format_args!("{}", self.int206().bits())) + .field("int207", &format_args!("{}", self.int207().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 204"] #[inline(always)] #[must_use] - pub fn int204(&mut self) -> INT204_W<0> { + pub fn int204(&mut self) -> INT204_W { INT204_W::new(self) } #[doc = "Bits 8:15 - Interrupt 205"] #[inline(always)] #[must_use] - pub fn int205(&mut self) -> INT205_W<8> { + pub fn int205(&mut self) -> INT205_W { INT205_W::new(self) } #[doc = "Bits 16:23 - Interrupt 206"] #[inline(always)] #[must_use] - pub fn int206(&mut self) -> INT206_W<16> { + pub fn int206(&mut self) -> INT206_W { INT206_W::new(self) } #[doc = "Bits 24:31 - Interrupt 207"] #[inline(always)] #[must_use] - pub fn int207(&mut self) -> INT207_W<24> { + pub fn int207(&mut self) -> INT207_W { INT207_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 204 - 207\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr51](index.html) module"] +#[doc = "Interrupt Processor Target 204 - 207\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr51::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr51::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR51_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR51_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr51::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR51_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr51::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr51::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR51_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr51::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR51_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr52.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr52.rs index aee42d1..798ef1b 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr52.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr52.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR52` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR52` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT208` reader - Interrupt 208"] -pub type INT208_R = crate::FieldReader; +pub type INT208_R = crate::FieldReader; #[doc = "Field `INT208` writer - Interrupt 208"] -pub type INT208_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR52_SPEC, u8, u8, 8, O>; +pub type INT208_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT209` reader - Interrupt 209"] -pub type INT209_R = crate::FieldReader; +pub type INT209_R = crate::FieldReader; #[doc = "Field `INT209` writer - Interrupt 209"] -pub type INT209_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR52_SPEC, u8, u8, 8, O>; +pub type INT209_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT210` reader - Interrupt 210"] -pub type INT210_R = crate::FieldReader; +pub type INT210_R = crate::FieldReader; #[doc = "Field `INT210` writer - Interrupt 210"] -pub type INT210_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR52_SPEC, u8, u8, 8, O>; +pub type INT210_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT211` reader - Interrupt 211"] -pub type INT211_R = crate::FieldReader; +pub type INT211_R = crate::FieldReader; #[doc = "Field `INT211` writer - Interrupt 211"] -pub type INT211_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR52_SPEC, u8, u8, 8, O>; +pub type INT211_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 208"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT211_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR52") + .field("int208", &format_args!("{}", self.int208().bits())) + .field("int209", &format_args!("{}", self.int209().bits())) + .field("int210", &format_args!("{}", self.int210().bits())) + .field("int211", &format_args!("{}", self.int211().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 208"] #[inline(always)] #[must_use] - pub fn int208(&mut self) -> INT208_W<0> { + pub fn int208(&mut self) -> INT208_W { INT208_W::new(self) } #[doc = "Bits 8:15 - Interrupt 209"] #[inline(always)] #[must_use] - pub fn int209(&mut self) -> INT209_W<8> { + pub fn int209(&mut self) -> INT209_W { INT209_W::new(self) } #[doc = "Bits 16:23 - Interrupt 210"] #[inline(always)] #[must_use] - pub fn int210(&mut self) -> INT210_W<16> { + pub fn int210(&mut self) -> INT210_W { INT210_W::new(self) } #[doc = "Bits 24:31 - Interrupt 211"] #[inline(always)] #[must_use] - pub fn int211(&mut self) -> INT211_W<24> { + pub fn int211(&mut self) -> INT211_W { INT211_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 208 - 211\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr52](index.html) module"] +#[doc = "Interrupt Processor Target 208 - 211\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr52::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr52::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR52_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR52_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr52::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR52_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr52::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr52::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR52_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr52::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR52_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr53.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr53.rs index 5923b06..38ea4b0 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr53.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr53.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR53` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR53` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT212` reader - Interrupt 212"] -pub type INT212_R = crate::FieldReader; +pub type INT212_R = crate::FieldReader; #[doc = "Field `INT212` writer - Interrupt 212"] -pub type INT212_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR53_SPEC, u8, u8, 8, O>; +pub type INT212_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT213` reader - Interrupt 213"] -pub type INT213_R = crate::FieldReader; +pub type INT213_R = crate::FieldReader; #[doc = "Field `INT213` writer - Interrupt 213"] -pub type INT213_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR53_SPEC, u8, u8, 8, O>; +pub type INT213_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT214` reader - Interrupt 214"] -pub type INT214_R = crate::FieldReader; +pub type INT214_R = crate::FieldReader; #[doc = "Field `INT214` writer - Interrupt 214"] -pub type INT214_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR53_SPEC, u8, u8, 8, O>; +pub type INT214_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT215` reader - Interrupt 215"] -pub type INT215_R = crate::FieldReader; +pub type INT215_R = crate::FieldReader; #[doc = "Field `INT215` writer - Interrupt 215"] -pub type INT215_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR53_SPEC, u8, u8, 8, O>; +pub type INT215_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 212"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT215_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR53") + .field("int212", &format_args!("{}", self.int212().bits())) + .field("int213", &format_args!("{}", self.int213().bits())) + .field("int214", &format_args!("{}", self.int214().bits())) + .field("int215", &format_args!("{}", self.int215().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 212"] #[inline(always)] #[must_use] - pub fn int212(&mut self) -> INT212_W<0> { + pub fn int212(&mut self) -> INT212_W { INT212_W::new(self) } #[doc = "Bits 8:15 - Interrupt 213"] #[inline(always)] #[must_use] - pub fn int213(&mut self) -> INT213_W<8> { + pub fn int213(&mut self) -> INT213_W { INT213_W::new(self) } #[doc = "Bits 16:23 - Interrupt 214"] #[inline(always)] #[must_use] - pub fn int214(&mut self) -> INT214_W<16> { + pub fn int214(&mut self) -> INT214_W { INT214_W::new(self) } #[doc = "Bits 24:31 - Interrupt 215"] #[inline(always)] #[must_use] - pub fn int215(&mut self) -> INT215_W<24> { + pub fn int215(&mut self) -> INT215_W { INT215_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 212 - 215\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr53](index.html) module"] +#[doc = "Interrupt Processor Target 212 - 215\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr53::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr53::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR53_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR53_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr53::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR53_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr53::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr53::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR53_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr53::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR53_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr54.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr54.rs index c0a5719..8cbfb77 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr54.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr54.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR54` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR54` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT216` reader - Interrupt 216"] -pub type INT216_R = crate::FieldReader; +pub type INT216_R = crate::FieldReader; #[doc = "Field `INT216` writer - Interrupt 216"] -pub type INT216_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR54_SPEC, u8, u8, 8, O>; +pub type INT216_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT217` reader - Interrupt 217"] -pub type INT217_R = crate::FieldReader; +pub type INT217_R = crate::FieldReader; #[doc = "Field `INT217` writer - Interrupt 217"] -pub type INT217_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR54_SPEC, u8, u8, 8, O>; +pub type INT217_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT218` reader - Interrupt 218"] -pub type INT218_R = crate::FieldReader; +pub type INT218_R = crate::FieldReader; #[doc = "Field `INT218` writer - Interrupt 218"] -pub type INT218_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR54_SPEC, u8, u8, 8, O>; +pub type INT218_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT219` reader - Interrupt 219"] -pub type INT219_R = crate::FieldReader; +pub type INT219_R = crate::FieldReader; #[doc = "Field `INT219` writer - Interrupt 219"] -pub type INT219_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR54_SPEC, u8, u8, 8, O>; +pub type INT219_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 216"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT219_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR54") + .field("int216", &format_args!("{}", self.int216().bits())) + .field("int217", &format_args!("{}", self.int217().bits())) + .field("int218", &format_args!("{}", self.int218().bits())) + .field("int219", &format_args!("{}", self.int219().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 216"] #[inline(always)] #[must_use] - pub fn int216(&mut self) -> INT216_W<0> { + pub fn int216(&mut self) -> INT216_W { INT216_W::new(self) } #[doc = "Bits 8:15 - Interrupt 217"] #[inline(always)] #[must_use] - pub fn int217(&mut self) -> INT217_W<8> { + pub fn int217(&mut self) -> INT217_W { INT217_W::new(self) } #[doc = "Bits 16:23 - Interrupt 218"] #[inline(always)] #[must_use] - pub fn int218(&mut self) -> INT218_W<16> { + pub fn int218(&mut self) -> INT218_W { INT218_W::new(self) } #[doc = "Bits 24:31 - Interrupt 219"] #[inline(always)] #[must_use] - pub fn int219(&mut self) -> INT219_W<24> { + pub fn int219(&mut self) -> INT219_W { INT219_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 216 - 219\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr54](index.html) module"] +#[doc = "Interrupt Processor Target 216 - 219\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr54::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr54::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR54_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR54_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr54::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR54_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr54::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr54::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR54_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr54::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR54_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr55.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr55.rs index ea2e0a5..3bc371b 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr55.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr55.rs @@ -1,59 +1,23 @@ #[doc = "Register `GICD_ITARGETSR55` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR55` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT220` reader - Interrupt 220"] -pub type INT220_R = crate::FieldReader; +pub type INT220_R = crate::FieldReader; #[doc = "Field `INT220` writer - Interrupt 220"] -pub type INT220_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR55_SPEC, u8, u8, 8, O>; +pub type INT220_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT221` reader - Interrupt 221"] -pub type INT221_R = crate::FieldReader; +pub type INT221_R = crate::FieldReader; #[doc = "Field `INT221` writer - Interrupt 221"] -pub type INT221_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR55_SPEC, u8, u8, 8, O>; +pub type INT221_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT222` reader - Interrupt 222"] -pub type INT222_R = crate::FieldReader; +pub type INT222_R = crate::FieldReader; #[doc = "Field `INT222` writer - Interrupt 222"] -pub type INT222_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR55_SPEC, u8, u8, 8, O>; +pub type INT222_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT223` reader - Interrupt 223"] -pub type INT223_R = crate::FieldReader; +pub type INT223_R = crate::FieldReader; #[doc = "Field `INT223` writer - Interrupt 223"] -pub type INT223_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GICD_ITARGETSR55_SPEC, u8, u8, 8, O>; +pub type INT223_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 220"] #[inline(always)] @@ -76,50 +40,66 @@ impl R { INT223_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR55") + .field("int220", &format_args!("{}", self.int220().bits())) + .field("int221", &format_args!("{}", self.int221().bits())) + .field("int222", &format_args!("{}", self.int222().bits())) + .field("int223", &format_args!("{}", self.int223().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 220"] #[inline(always)] #[must_use] - pub fn int220(&mut self) -> INT220_W<0> { + pub fn int220(&mut self) -> INT220_W { INT220_W::new(self) } #[doc = "Bits 8:15 - Interrupt 221"] #[inline(always)] #[must_use] - pub fn int221(&mut self) -> INT221_W<8> { + pub fn int221(&mut self) -> INT221_W { INT221_W::new(self) } #[doc = "Bits 16:23 - Interrupt 222"] #[inline(always)] #[must_use] - pub fn int222(&mut self) -> INT222_W<16> { + pub fn int222(&mut self) -> INT222_W { INT222_W::new(self) } #[doc = "Bits 24:31 - Interrupt 223"] #[inline(always)] #[must_use] - pub fn int223(&mut self) -> INT223_W<24> { + pub fn int223(&mut self) -> INT223_W { INT223_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 220 - 223\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr55](index.html) module"] +#[doc = "Interrupt Processor Target 220 - 223\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr55::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr55::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR55_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR55_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr55::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR55_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr55::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr55::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR55_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr55::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR55_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr6.rs index b0feb60..6c84128 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr6.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr6.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_ITARGETSR6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT24` reader - Interrupt 24"] -pub type INT24_R = crate::FieldReader; +pub type INT24_R = crate::FieldReader; #[doc = "Field `INT24` writer - Interrupt 24"] -pub type INT24_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR6_SPEC, u8, u8, 8, O>; +pub type INT24_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT25` reader - Interrupt 25"] -pub type INT25_R = crate::FieldReader; +pub type INT25_R = crate::FieldReader; #[doc = "Field `INT25` writer - Interrupt 25"] -pub type INT25_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR6_SPEC, u8, u8, 8, O>; +pub type INT25_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT26` reader - Interrupt 26"] -pub type INT26_R = crate::FieldReader; +pub type INT26_R = crate::FieldReader; #[doc = "Field `INT26` writer - Interrupt 26"] -pub type INT26_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR6_SPEC, u8, u8, 8, O>; +pub type INT26_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT27` reader - Interrupt 27"] -pub type INT27_R = crate::FieldReader; +pub type INT27_R = crate::FieldReader; #[doc = "Field `INT27` writer - Interrupt 27"] -pub type INT27_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR6_SPEC, u8, u8, 8, O>; +pub type INT27_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 24"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { INT27_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR6") + .field("int24", &format_args!("{}", self.int24().bits())) + .field("int25", &format_args!("{}", self.int25().bits())) + .field("int26", &format_args!("{}", self.int26().bits())) + .field("int27", &format_args!("{}", self.int27().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 24"] #[inline(always)] #[must_use] - pub fn int24(&mut self) -> INT24_W<0> { + pub fn int24(&mut self) -> INT24_W { INT24_W::new(self) } #[doc = "Bits 8:15 - Interrupt 25"] #[inline(always)] #[must_use] - pub fn int25(&mut self) -> INT25_W<8> { + pub fn int25(&mut self) -> INT25_W { INT25_W::new(self) } #[doc = "Bits 16:23 - Interrupt 26"] #[inline(always)] #[must_use] - pub fn int26(&mut self) -> INT26_W<16> { + pub fn int26(&mut self) -> INT26_W { INT26_W::new(self) } #[doc = "Bits 24:31 - Interrupt 27"] #[inline(always)] #[must_use] - pub fn int27(&mut self) -> INT27_W<24> { + pub fn int27(&mut self) -> INT27_W { INT27_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 24 - 27\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr6](index.html) module"] +#[doc = "Interrupt Processor Target 24 - 27\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR6_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr6::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr6::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr6::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr6::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr7.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr7.rs index e53083c..1f50911 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr7.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr7.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_ITARGETSR7` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR7` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT28` reader - Interrupt 28"] -pub type INT28_R = crate::FieldReader; +pub type INT28_R = crate::FieldReader; #[doc = "Field `INT28` writer - Interrupt 28"] -pub type INT28_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR7_SPEC, u8, u8, 8, O>; +pub type INT28_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT29` reader - Interrupt 29"] -pub type INT29_R = crate::FieldReader; +pub type INT29_R = crate::FieldReader; #[doc = "Field `INT29` writer - Interrupt 29"] -pub type INT29_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR7_SPEC, u8, u8, 8, O>; +pub type INT29_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT30` reader - Interrupt 30"] -pub type INT30_R = crate::FieldReader; +pub type INT30_R = crate::FieldReader; #[doc = "Field `INT30` writer - Interrupt 30"] -pub type INT30_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR7_SPEC, u8, u8, 8, O>; +pub type INT30_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT31` reader - Interrupt 31"] -pub type INT31_R = crate::FieldReader; +pub type INT31_R = crate::FieldReader; #[doc = "Field `INT31` writer - Interrupt 31"] -pub type INT31_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR7_SPEC, u8, u8, 8, O>; +pub type INT31_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 28"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { INT31_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR7") + .field("int28", &format_args!("{}", self.int28().bits())) + .field("int29", &format_args!("{}", self.int29().bits())) + .field("int30", &format_args!("{}", self.int30().bits())) + .field("int31", &format_args!("{}", self.int31().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 28"] #[inline(always)] #[must_use] - pub fn int28(&mut self) -> INT28_W<0> { + pub fn int28(&mut self) -> INT28_W { INT28_W::new(self) } #[doc = "Bits 8:15 - Interrupt 29"] #[inline(always)] #[must_use] - pub fn int29(&mut self) -> INT29_W<8> { + pub fn int29(&mut self) -> INT29_W { INT29_W::new(self) } #[doc = "Bits 16:23 - Interrupt 30"] #[inline(always)] #[must_use] - pub fn int30(&mut self) -> INT30_W<16> { + pub fn int30(&mut self) -> INT30_W { INT30_W::new(self) } #[doc = "Bits 24:31 - Interrupt 31"] #[inline(always)] #[must_use] - pub fn int31(&mut self) -> INT31_W<24> { + pub fn int31(&mut self) -> INT31_W { INT31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 28 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr7](index.html) module"] +#[doc = "Interrupt Processor Target 28 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR7_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR7_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr7::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR7_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr7::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr7::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr7::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR7_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr8.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr8.rs index 80c1bed..a0035ef 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr8.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr8.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_ITARGETSR8` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR8` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT32` reader - Interrupt 32"] -pub type INT32_R = crate::FieldReader; +pub type INT32_R = crate::FieldReader; #[doc = "Field `INT32` writer - Interrupt 32"] -pub type INT32_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR8_SPEC, u8, u8, 8, O>; +pub type INT32_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT33` reader - Interrupt 33"] -pub type INT33_R = crate::FieldReader; +pub type INT33_R = crate::FieldReader; #[doc = "Field `INT33` writer - Interrupt 33"] -pub type INT33_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR8_SPEC, u8, u8, 8, O>; +pub type INT33_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT34` reader - Interrupt 34"] -pub type INT34_R = crate::FieldReader; +pub type INT34_R = crate::FieldReader; #[doc = "Field `INT34` writer - Interrupt 34"] -pub type INT34_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR8_SPEC, u8, u8, 8, O>; +pub type INT34_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT35` reader - Interrupt 35"] -pub type INT35_R = crate::FieldReader; +pub type INT35_R = crate::FieldReader; #[doc = "Field `INT35` writer - Interrupt 35"] -pub type INT35_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR8_SPEC, u8, u8, 8, O>; +pub type INT35_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 32"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { INT35_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR8") + .field("int32", &format_args!("{}", self.int32().bits())) + .field("int33", &format_args!("{}", self.int33().bits())) + .field("int34", &format_args!("{}", self.int34().bits())) + .field("int35", &format_args!("{}", self.int35().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 32"] #[inline(always)] #[must_use] - pub fn int32(&mut self) -> INT32_W<0> { + pub fn int32(&mut self) -> INT32_W { INT32_W::new(self) } #[doc = "Bits 8:15 - Interrupt 33"] #[inline(always)] #[must_use] - pub fn int33(&mut self) -> INT33_W<8> { + pub fn int33(&mut self) -> INT33_W { INT33_W::new(self) } #[doc = "Bits 16:23 - Interrupt 34"] #[inline(always)] #[must_use] - pub fn int34(&mut self) -> INT34_W<16> { + pub fn int34(&mut self) -> INT34_W { INT34_W::new(self) } #[doc = "Bits 24:31 - Interrupt 35"] #[inline(always)] #[must_use] - pub fn int35(&mut self) -> INT35_W<24> { + pub fn int35(&mut self) -> INT35_W { INT35_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 32 - 35\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr8](index.html) module"] +#[doc = "Interrupt Processor Target 32 - 35\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR8_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR8_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr8::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR8_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr8::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr8::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr8::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR8_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr9.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr9.rs index 07224dd..eb4345f 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr9.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_itargetsr/gicd_itargetsr9.rs @@ -1,55 +1,23 @@ #[doc = "Register `GICD_ITARGETSR9` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_ITARGETSR9` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT36` reader - Interrupt 36"] -pub type INT36_R = crate::FieldReader; +pub type INT36_R = crate::FieldReader; #[doc = "Field `INT36` writer - Interrupt 36"] -pub type INT36_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR9_SPEC, u8, u8, 8, O>; +pub type INT36_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT37` reader - Interrupt 37"] -pub type INT37_R = crate::FieldReader; +pub type INT37_R = crate::FieldReader; #[doc = "Field `INT37` writer - Interrupt 37"] -pub type INT37_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR9_SPEC, u8, u8, 8, O>; +pub type INT37_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT38` reader - Interrupt 38"] -pub type INT38_R = crate::FieldReader; +pub type INT38_R = crate::FieldReader; #[doc = "Field `INT38` writer - Interrupt 38"] -pub type INT38_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR9_SPEC, u8, u8, 8, O>; +pub type INT38_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INT39` reader - Interrupt 39"] -pub type INT39_R = crate::FieldReader; +pub type INT39_R = crate::FieldReader; #[doc = "Field `INT39` writer - Interrupt 39"] -pub type INT39_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GICD_ITARGETSR9_SPEC, u8, u8, 8, O>; +pub type INT39_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Interrupt 36"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { INT39_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_ITARGETSR9") + .field("int36", &format_args!("{}", self.int36().bits())) + .field("int37", &format_args!("{}", self.int37().bits())) + .field("int38", &format_args!("{}", self.int38().bits())) + .field("int39", &format_args!("{}", self.int39().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Interrupt 36"] #[inline(always)] #[must_use] - pub fn int36(&mut self) -> INT36_W<0> { + pub fn int36(&mut self) -> INT36_W { INT36_W::new(self) } #[doc = "Bits 8:15 - Interrupt 37"] #[inline(always)] #[must_use] - pub fn int37(&mut self) -> INT37_W<8> { + pub fn int37(&mut self) -> INT37_W { INT37_W::new(self) } #[doc = "Bits 16:23 - Interrupt 38"] #[inline(always)] #[must_use] - pub fn int38(&mut self) -> INT38_W<16> { + pub fn int38(&mut self) -> INT38_W { INT38_W::new(self) } #[doc = "Bits 24:31 - Interrupt 39"] #[inline(always)] #[must_use] - pub fn int39(&mut self) -> INT39_W<24> { + pub fn int39(&mut self) -> INT39_W { INT39_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Processor Target 36 - 39\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_itargetsr9](index.html) module"] +#[doc = "Interrupt Processor Target 36 - 39\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_itargetsr9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_itargetsr9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_ITARGETSR9_SPEC; impl crate::RegisterSpec for GICD_ITARGETSR9_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_itargetsr9::R](R) reader structure"] -impl crate::Readable for GICD_ITARGETSR9_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_itargetsr9::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_itargetsr9::R`](R) reader structure"] +impl crate::Readable for GICD_ITARGETSR9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_itargetsr9::W`](W) writer structure"] impl crate::Writable for GICD_ITARGETSR9_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr0.rs index 475a66f..82cd0ed 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr0.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr0.rs @@ -1,20 +1,7 @@ #[doc = "Register `GICD_PIDR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GICD_PIDR0` reader - Peripheral ID 0"] -pub type GICD_PIDR0_R = crate::FieldReader; +pub type GICD_PIDR0_R = crate::FieldReader; #[doc = "Peripheral ID 0\n\nValue on reset: 144"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -28,16 +15,19 @@ impl From for u32 { variant as _ } } +impl crate::FieldSpec for GICD_PIDR0_A { + type Ux = u32; +} impl GICD_PIDR0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 144 => Some(GICD_PIDR0_A::VALID), _ => None, } } - #[doc = "Checks if the value of the field is `VALID`"] + #[doc = "Valid"] #[inline(always)] pub fn is_valid(&self) -> bool { *self == GICD_PIDR0_A::VALID @@ -50,15 +40,25 @@ impl R { GICD_PIDR0_R::new(self.bits) } } -#[doc = "Peripheral ID 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr0](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_PIDR0") + .field("gicd_pidr0", &format_args!("{}", self.gicd_pidr0().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Peripheral ID 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_PIDR0_SPEC; impl crate::RegisterSpec for GICD_PIDR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_pidr0::R](R) reader structure"] -impl crate::Readable for GICD_PIDR0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_pidr0::R`](R) reader structure"] +impl crate::Readable for GICD_PIDR0_SPEC {} #[doc = "`reset()` method sets GICD_PIDR0 to value 0x90"] impl crate::Resettable for GICD_PIDR0_SPEC { const RESET_VALUE: Self::Ux = 0x90; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr1.rs index 5bab832..fb54acb 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr1.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr1.rs @@ -1,20 +1,7 @@ #[doc = "Register `GICD_PIDR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GICD_PIDR1` reader - Peripheral ID 1"] -pub type GICD_PIDR1_R = crate::FieldReader; +pub type GICD_PIDR1_R = crate::FieldReader; #[doc = "Peripheral ID 1\n\nValue on reset: 180"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -28,16 +15,19 @@ impl From for u32 { variant as _ } } +impl crate::FieldSpec for GICD_PIDR1_A { + type Ux = u32; +} impl GICD_PIDR1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 180 => Some(GICD_PIDR1_A::VALID), _ => None, } } - #[doc = "Checks if the value of the field is `VALID`"] + #[doc = "Valid"] #[inline(always)] pub fn is_valid(&self) -> bool { *self == GICD_PIDR1_A::VALID @@ -50,15 +40,25 @@ impl R { GICD_PIDR1_R::new(self.bits) } } -#[doc = "Peripheral ID 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr1](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_PIDR1") + .field("gicd_pidr1", &format_args!("{}", self.gicd_pidr1().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Peripheral ID 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_PIDR1_SPEC; impl crate::RegisterSpec for GICD_PIDR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_pidr1::R](R) reader structure"] -impl crate::Readable for GICD_PIDR1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_pidr1::R`](R) reader structure"] +impl crate::Readable for GICD_PIDR1_SPEC {} #[doc = "`reset()` method sets GICD_PIDR1 to value 0xb4"] impl crate::Resettable for GICD_PIDR1_SPEC { const RESET_VALUE: Self::Ux = 0xb4; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr2.rs index 9dd9594..0732af6 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr2.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr2.rs @@ -1,20 +1,7 @@ #[doc = "Register `GICD_PIDR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GICD_PIDR2` reader - Peripheral ID 2"] -pub type GICD_PIDR2_R = crate::FieldReader; +pub type GICD_PIDR2_R = crate::FieldReader; #[doc = "Peripheral ID 2\n\nValue on reset: 43"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -28,16 +15,19 @@ impl From for u32 { variant as _ } } +impl crate::FieldSpec for GICD_PIDR2_A { + type Ux = u32; +} impl GICD_PIDR2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 43 => Some(GICD_PIDR2_A::VALID), _ => None, } } - #[doc = "Checks if the value of the field is `VALID`"] + #[doc = "Valid"] #[inline(always)] pub fn is_valid(&self) -> bool { *self == GICD_PIDR2_A::VALID @@ -50,15 +40,25 @@ impl R { GICD_PIDR2_R::new(self.bits) } } -#[doc = "Peripheral ID 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr2](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_PIDR2") + .field("gicd_pidr2", &format_args!("{}", self.gicd_pidr2().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Peripheral ID 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_PIDR2_SPEC; impl crate::RegisterSpec for GICD_PIDR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_pidr2::R](R) reader structure"] -impl crate::Readable for GICD_PIDR2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_pidr2::R`](R) reader structure"] +impl crate::Readable for GICD_PIDR2_SPEC {} #[doc = "`reset()` method sets GICD_PIDR2 to value 0x2b"] impl crate::Resettable for GICD_PIDR2_SPEC { const RESET_VALUE: Self::Ux = 0x2b; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr3.rs index 500d9eb..fc6c9ee 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr3.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr3.rs @@ -1,20 +1,7 @@ #[doc = "Register `GICD_PIDR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GICD_PIDR3` reader - Peripheral ID 3"] -pub type GICD_PIDR3_R = crate::FieldReader; +pub type GICD_PIDR3_R = crate::FieldReader; #[doc = "Peripheral ID 3\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -28,16 +15,19 @@ impl From for u32 { variant as _ } } +impl crate::FieldSpec for GICD_PIDR3_A { + type Ux = u32; +} impl GICD_PIDR3_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(GICD_PIDR3_A::VALID), _ => None, } } - #[doc = "Checks if the value of the field is `VALID`"] + #[doc = "Valid"] #[inline(always)] pub fn is_valid(&self) -> bool { *self == GICD_PIDR3_A::VALID @@ -50,15 +40,25 @@ impl R { GICD_PIDR3_R::new(self.bits) } } -#[doc = "Peripheral ID 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr3](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_PIDR3") + .field("gicd_pidr3", &format_args!("{}", self.gicd_pidr3().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Peripheral ID 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_PIDR3_SPEC; impl crate::RegisterSpec for GICD_PIDR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_pidr3::R](R) reader structure"] -impl crate::Readable for GICD_PIDR3_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_pidr3::R`](R) reader structure"] +impl crate::Readable for GICD_PIDR3_SPEC {} #[doc = "`reset()` method sets GICD_PIDR3 to value 0"] impl crate::Resettable for GICD_PIDR3_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr4.rs index 9b4d3a3..485a1b8 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr4.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr4.rs @@ -1,20 +1,7 @@ #[doc = "Register `GICD_PIDR4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GICD_PIDR4` reader - Peripheral ID 4"] -pub type GICD_PIDR4_R = crate::FieldReader; +pub type GICD_PIDR4_R = crate::FieldReader; #[doc = "Peripheral ID 4\n\nValue on reset: 4"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -28,16 +15,19 @@ impl From for u32 { variant as _ } } +impl crate::FieldSpec for GICD_PIDR4_A { + type Ux = u32; +} impl GICD_PIDR4_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 4 => Some(GICD_PIDR4_A::VALID), _ => None, } } - #[doc = "Checks if the value of the field is `VALID`"] + #[doc = "Valid"] #[inline(always)] pub fn is_valid(&self) -> bool { *self == GICD_PIDR4_A::VALID @@ -50,15 +40,25 @@ impl R { GICD_PIDR4_R::new(self.bits) } } -#[doc = "Peripheral ID 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr4](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_PIDR4") + .field("gicd_pidr4", &format_args!("{}", self.gicd_pidr4().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Peripheral ID 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_PIDR4_SPEC; impl crate::RegisterSpec for GICD_PIDR4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_pidr4::R](R) reader structure"] -impl crate::Readable for GICD_PIDR4_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_pidr4::R`](R) reader structure"] +impl crate::Readable for GICD_PIDR4_SPEC {} #[doc = "`reset()` method sets GICD_PIDR4 to value 0x04"] impl crate::Resettable for GICD_PIDR4_SPEC { const RESET_VALUE: Self::Ux = 0x04; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr5.rs index a0c4716..4e4cc2d 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr5.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr5.rs @@ -1,20 +1,7 @@ #[doc = "Register `GICD_PIDR5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GICD_PIDR5` reader - Peripheral ID 5"] -pub type GICD_PIDR5_R = crate::FieldReader; +pub type GICD_PIDR5_R = crate::FieldReader; #[doc = "Peripheral ID 5\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -28,16 +15,19 @@ impl From for u32 { variant as _ } } +impl crate::FieldSpec for GICD_PIDR5_A { + type Ux = u32; +} impl GICD_PIDR5_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(GICD_PIDR5_A::VALID), _ => None, } } - #[doc = "Checks if the value of the field is `VALID`"] + #[doc = "Valid"] #[inline(always)] pub fn is_valid(&self) -> bool { *self == GICD_PIDR5_A::VALID @@ -50,15 +40,25 @@ impl R { GICD_PIDR5_R::new(self.bits) } } -#[doc = "Peripheral ID 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr5](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_PIDR5") + .field("gicd_pidr5", &format_args!("{}", self.gicd_pidr5().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Peripheral ID 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_PIDR5_SPEC; impl crate::RegisterSpec for GICD_PIDR5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_pidr5::R](R) reader structure"] -impl crate::Readable for GICD_PIDR5_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_pidr5::R`](R) reader structure"] +impl crate::Readable for GICD_PIDR5_SPEC {} #[doc = "`reset()` method sets GICD_PIDR5 to value 0"] impl crate::Resettable for GICD_PIDR5_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr6.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr6.rs index 6f706f8..38fbd6a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr6.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr6.rs @@ -1,20 +1,7 @@ #[doc = "Register `GICD_PIDR6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GICD_PIDR6` reader - Peripheral ID 6"] -pub type GICD_PIDR6_R = crate::FieldReader; +pub type GICD_PIDR6_R = crate::FieldReader; #[doc = "Peripheral ID 6\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -28,16 +15,19 @@ impl From for u32 { variant as _ } } +impl crate::FieldSpec for GICD_PIDR6_A { + type Ux = u32; +} impl GICD_PIDR6_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(GICD_PIDR6_A::VALID), _ => None, } } - #[doc = "Checks if the value of the field is `VALID`"] + #[doc = "Valid"] #[inline(always)] pub fn is_valid(&self) -> bool { *self == GICD_PIDR6_A::VALID @@ -50,15 +40,25 @@ impl R { GICD_PIDR6_R::new(self.bits) } } -#[doc = "Peripheral ID 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr6](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_PIDR6") + .field("gicd_pidr6", &format_args!("{}", self.gicd_pidr6().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Peripheral ID 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_PIDR6_SPEC; impl crate::RegisterSpec for GICD_PIDR6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_pidr6::R](R) reader structure"] -impl crate::Readable for GICD_PIDR6_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_pidr6::R`](R) reader structure"] +impl crate::Readable for GICD_PIDR6_SPEC {} #[doc = "`reset()` method sets GICD_PIDR6 to value 0"] impl crate::Resettable for GICD_PIDR6_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr7.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr7.rs index 6be8720..7a77f8b 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_pidr7.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_pidr7.rs @@ -1,20 +1,7 @@ #[doc = "Register `GICD_PIDR7` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `GICD_PIDR7` reader - Peripheral ID 7"] -pub type GICD_PIDR7_R = crate::FieldReader; +pub type GICD_PIDR7_R = crate::FieldReader; #[doc = "Peripheral ID 7\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -28,16 +15,19 @@ impl From for u32 { variant as _ } } +impl crate::FieldSpec for GICD_PIDR7_A { + type Ux = u32; +} impl GICD_PIDR7_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(GICD_PIDR7_A::VALID), _ => None, } } - #[doc = "Checks if the value of the field is `VALID`"] + #[doc = "Valid"] #[inline(always)] pub fn is_valid(&self) -> bool { *self == GICD_PIDR7_A::VALID @@ -50,15 +40,25 @@ impl R { GICD_PIDR7_R::new(self.bits) } } -#[doc = "Peripheral ID 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_pidr7](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_PIDR7") + .field("gicd_pidr7", &format_args!("{}", self.gicd_pidr7().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Peripheral ID 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_pidr7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_PIDR7_SPEC; impl crate::RegisterSpec for GICD_PIDR7_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_pidr7::R](R) reader structure"] -impl crate::Readable for GICD_PIDR7_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_pidr7::R`](R) reader structure"] +impl crate::Readable for GICD_PIDR7_SPEC {} #[doc = "`reset()` method sets GICD_PIDR7 to value 0"] impl crate::Resettable for GICD_PIDR7_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_ppisr.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_ppisr.rs index 1c98035..7ea883c 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_ppisr.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_ppisr.rs @@ -1,67 +1,35 @@ #[doc = "Register `GICD_PPISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_PPISR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ID25` reader - Virtual maintenance interrupt"] -pub type ID25_R = crate::BitReader; +pub type ID25_R = crate::BitReader; #[doc = "Field `ID25` writer - Virtual maintenance interrupt"] -pub type ID25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +pub type ID25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID26` reader - Hypervisor timer event"] -pub type ID26_R = crate::BitReader; +pub type ID26_R = crate::BitReader; #[doc = "Field `ID26` writer - Hypervisor timer event"] -pub type ID26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +pub type ID26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID27` reader - Virtual timer event"] -pub type ID27_R = crate::BitReader; +pub type ID27_R = crate::BitReader; #[doc = "Field `ID27` writer - Virtual timer event"] -pub type ID27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +pub type ID27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID28` reader - nLEGACYFIQ signal"] -pub type ID28_R = crate::BitReader; +pub type ID28_R = crate::BitReader; #[doc = "Field `ID28` writer - nLEGACYFIQ signal"] -pub type ID28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +pub type ID28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID29` reader - Secure physical timer event"] -pub type ID29_R = crate::BitReader; +pub type ID29_R = crate::BitReader; #[doc = "Field `ID29` writer - Secure physical timer event"] -pub type ID29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +pub type ID29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID30` reader - Non-secure physical timer event"] -pub type ID30_R = crate::BitReader; +pub type ID30_R = crate::BitReader; #[doc = "Field `ID30` writer - Non-secure physical timer event"] -pub type ID30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +pub type ID30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID31` reader - nLEGACYIRQ signal"] -pub type ID31_R = crate::BitReader; +pub type ID31_R = crate::BitReader; #[doc = "Field `ID31` writer - nLEGACYIRQ signal"] -pub type ID31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_PPISR_SPEC, bool, O>; +pub type ID31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 9 - Virtual maintenance interrupt"] #[inline(always)] @@ -99,68 +67,87 @@ impl R { ID31_R::new(((self.bits >> 15) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_PPISR") + .field("id31", &format_args!("{}", self.id31().bit())) + .field("id30", &format_args!("{}", self.id30().bit())) + .field("id29", &format_args!("{}", self.id29().bit())) + .field("id28", &format_args!("{}", self.id28().bit())) + .field("id27", &format_args!("{}", self.id27().bit())) + .field("id26", &format_args!("{}", self.id26().bit())) + .field("id25", &format_args!("{}", self.id25().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 9 - Virtual maintenance interrupt"] #[inline(always)] #[must_use] - pub fn id25(&mut self) -> ID25_W<9> { + pub fn id25(&mut self) -> ID25_W { ID25_W::new(self) } #[doc = "Bit 10 - Hypervisor timer event"] #[inline(always)] #[must_use] - pub fn id26(&mut self) -> ID26_W<10> { + pub fn id26(&mut self) -> ID26_W { ID26_W::new(self) } #[doc = "Bit 11 - Virtual timer event"] #[inline(always)] #[must_use] - pub fn id27(&mut self) -> ID27_W<11> { + pub fn id27(&mut self) -> ID27_W { ID27_W::new(self) } #[doc = "Bit 12 - nLEGACYFIQ signal"] #[inline(always)] #[must_use] - pub fn id28(&mut self) -> ID28_W<12> { + pub fn id28(&mut self) -> ID28_W { ID28_W::new(self) } #[doc = "Bit 13 - Secure physical timer event"] #[inline(always)] #[must_use] - pub fn id29(&mut self) -> ID29_W<13> { + pub fn id29(&mut self) -> ID29_W { ID29_W::new(self) } #[doc = "Bit 14 - Non-secure physical timer event"] #[inline(always)] #[must_use] - pub fn id30(&mut self) -> ID30_W<14> { + pub fn id30(&mut self) -> ID30_W { ID30_W::new(self) } #[doc = "Bit 15 - nLEGACYIRQ signal"] #[inline(always)] #[must_use] - pub fn id31(&mut self) -> ID31_W<15> { + pub fn id31(&mut self) -> ID31_W { ID31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Private Peripheral Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_ppisr](index.html) module"] +#[doc = "Private Peripheral Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_ppisr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_ppisr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_PPISR_SPEC; impl crate::RegisterSpec for GICD_PPISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_ppisr::R](R) reader structure"] -impl crate::Readable for GICD_PPISR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_ppisr::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_ppisr::R`](R) reader structure"] +impl crate::Readable for GICD_PPISR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_ppisr::W`](W) writer structure"] impl crate::Writable for GICD_PPISR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_sgir.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_sgir.rs index fc59dc1..afac8fc 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_sgir.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_sgir.rs @@ -1,40 +1,29 @@ #[doc = "Register `GICD_SGIR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +pub type W = crate::W; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Software Generated Interrupt Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_sgir](index.html) module"] +#[doc = "Software Generated Interrupt Register\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_sgir::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_SGIR_SPEC; impl crate::RegisterSpec for GICD_SGIR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gicd_sgir::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gicd_sgir::W`](W) writer structure"] impl crate::Writable for GICD_SGIR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spendsgirn.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spendsgirn.rs index 25310c6..b926118 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_spendsgirn.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spendsgirn.rs @@ -1,59 +1,38 @@ #[doc = "Register `GICD_SPENDSGIRn` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_SPENDSGIRn` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SGI Set-Pending Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spendsgirn](index.html) module"] +#[doc = "SGI Set-Pending Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spendsgirn::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spendsgirn::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_SPENDSGIRN_SPEC; impl crate::RegisterSpec for GICD_SPENDSGIRN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_spendsgirn::R](R) reader structure"] -impl crate::Readable for GICD_SPENDSGIRN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_spendsgirn::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_spendsgirn::R`](R) reader structure"] +impl crate::Readable for GICD_SPENDSGIRN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_spendsgirn::W`](W) writer structure"] impl crate::Writable for GICD_SPENDSGIRN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr0.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr0.rs index 24de248..5a4eb65 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr0.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_SPISR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_SPISR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SPI32` reader - Shared interrupt 32"] -pub type SPI32_R = crate::BitReader; +pub type SPI32_R = crate::BitReader; #[doc = "Field `SPI32` writer - Shared interrupt 32"] -pub type SPI32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI33` reader - Shared interrupt 33"] -pub type SPI33_R = crate::BitReader; +pub type SPI33_R = crate::BitReader; #[doc = "Field `SPI33` writer - Shared interrupt 33"] -pub type SPI33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI34` reader - Shared interrupt 34"] -pub type SPI34_R = crate::BitReader; +pub type SPI34_R = crate::BitReader; #[doc = "Field `SPI34` writer - Shared interrupt 34"] -pub type SPI34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI35` reader - Shared interrupt 35"] -pub type SPI35_R = crate::BitReader; +pub type SPI35_R = crate::BitReader; #[doc = "Field `SPI35` writer - Shared interrupt 35"] -pub type SPI35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI36` reader - Shared interrupt 36"] -pub type SPI36_R = crate::BitReader; +pub type SPI36_R = crate::BitReader; #[doc = "Field `SPI36` writer - Shared interrupt 36"] -pub type SPI36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI37` reader - Shared interrupt 37"] -pub type SPI37_R = crate::BitReader; +pub type SPI37_R = crate::BitReader; #[doc = "Field `SPI37` writer - Shared interrupt 37"] -pub type SPI37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI38` reader - Shared interrupt 38"] -pub type SPI38_R = crate::BitReader; +pub type SPI38_R = crate::BitReader; #[doc = "Field `SPI38` writer - Shared interrupt 38"] -pub type SPI38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI39` reader - Shared interrupt 39"] -pub type SPI39_R = crate::BitReader; +pub type SPI39_R = crate::BitReader; #[doc = "Field `SPI39` writer - Shared interrupt 39"] -pub type SPI39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI40` reader - Shared interrupt 40"] -pub type SPI40_R = crate::BitReader; +pub type SPI40_R = crate::BitReader; #[doc = "Field `SPI40` writer - Shared interrupt 40"] -pub type SPI40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI41` reader - Shared interrupt 41"] -pub type SPI41_R = crate::BitReader; +pub type SPI41_R = crate::BitReader; #[doc = "Field `SPI41` writer - Shared interrupt 41"] -pub type SPI41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI42` reader - Shared interrupt 42"] -pub type SPI42_R = crate::BitReader; +pub type SPI42_R = crate::BitReader; #[doc = "Field `SPI42` writer - Shared interrupt 42"] -pub type SPI42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI43` reader - Shared interrupt 43"] -pub type SPI43_R = crate::BitReader; +pub type SPI43_R = crate::BitReader; #[doc = "Field `SPI43` writer - Shared interrupt 43"] -pub type SPI43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI44` reader - Shared interrupt 44"] -pub type SPI44_R = crate::BitReader; +pub type SPI44_R = crate::BitReader; #[doc = "Field `SPI44` writer - Shared interrupt 44"] -pub type SPI44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI45` reader - Shared interrupt 45"] -pub type SPI45_R = crate::BitReader; +pub type SPI45_R = crate::BitReader; #[doc = "Field `SPI45` writer - Shared interrupt 45"] -pub type SPI45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI46` reader - Shared interrupt 46"] -pub type SPI46_R = crate::BitReader; +pub type SPI46_R = crate::BitReader; #[doc = "Field `SPI46` writer - Shared interrupt 46"] -pub type SPI46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI47` reader - Shared interrupt 47"] -pub type SPI47_R = crate::BitReader; +pub type SPI47_R = crate::BitReader; #[doc = "Field `SPI47` writer - Shared interrupt 47"] -pub type SPI47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI48` reader - Shared interrupt 48"] -pub type SPI48_R = crate::BitReader; +pub type SPI48_R = crate::BitReader; #[doc = "Field `SPI48` writer - Shared interrupt 48"] -pub type SPI48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI49` reader - Shared interrupt 49"] -pub type SPI49_R = crate::BitReader; +pub type SPI49_R = crate::BitReader; #[doc = "Field `SPI49` writer - Shared interrupt 49"] -pub type SPI49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI50` reader - Shared interrupt 50"] -pub type SPI50_R = crate::BitReader; +pub type SPI50_R = crate::BitReader; #[doc = "Field `SPI50` writer - Shared interrupt 50"] -pub type SPI50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI51` reader - Shared interrupt 51"] -pub type SPI51_R = crate::BitReader; +pub type SPI51_R = crate::BitReader; #[doc = "Field `SPI51` writer - Shared interrupt 51"] -pub type SPI51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI52` reader - Shared interrupt 52"] -pub type SPI52_R = crate::BitReader; +pub type SPI52_R = crate::BitReader; #[doc = "Field `SPI52` writer - Shared interrupt 52"] -pub type SPI52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI53` reader - Shared interrupt 53"] -pub type SPI53_R = crate::BitReader; +pub type SPI53_R = crate::BitReader; #[doc = "Field `SPI53` writer - Shared interrupt 53"] -pub type SPI53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI54` reader - Shared interrupt 54"] -pub type SPI54_R = crate::BitReader; +pub type SPI54_R = crate::BitReader; #[doc = "Field `SPI54` writer - Shared interrupt 54"] -pub type SPI54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI54_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI55` reader - Shared interrupt 55"] -pub type SPI55_R = crate::BitReader; +pub type SPI55_R = crate::BitReader; #[doc = "Field `SPI55` writer - Shared interrupt 55"] -pub type SPI55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI55_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI56` reader - Shared interrupt 56"] -pub type SPI56_R = crate::BitReader; +pub type SPI56_R = crate::BitReader; #[doc = "Field `SPI56` writer - Shared interrupt 56"] -pub type SPI56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI57` reader - Shared interrupt 57"] -pub type SPI57_R = crate::BitReader; +pub type SPI57_R = crate::BitReader; #[doc = "Field `SPI57` writer - Shared interrupt 57"] -pub type SPI57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI58` reader - Shared interrupt 58"] -pub type SPI58_R = crate::BitReader; +pub type SPI58_R = crate::BitReader; #[doc = "Field `SPI58` writer - Shared interrupt 58"] -pub type SPI58_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI58_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI59` reader - Shared interrupt 59"] -pub type SPI59_R = crate::BitReader; +pub type SPI59_R = crate::BitReader; #[doc = "Field `SPI59` writer - Shared interrupt 59"] -pub type SPI59_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI59_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI60` reader - Shared interrupt 60"] -pub type SPI60_R = crate::BitReader; +pub type SPI60_R = crate::BitReader; #[doc = "Field `SPI60` writer - Shared interrupt 60"] -pub type SPI60_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI60_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI61` reader - Shared interrupt 61"] -pub type SPI61_R = crate::BitReader; +pub type SPI61_R = crate::BitReader; #[doc = "Field `SPI61` writer - Shared interrupt 61"] -pub type SPI61_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI61_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI62` reader - Shared interrupt 62"] -pub type SPI62_R = crate::BitReader; +pub type SPI62_R = crate::BitReader; #[doc = "Field `SPI62` writer - Shared interrupt 62"] -pub type SPI62_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI62_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI63` reader - Shared interrupt 63"] -pub type SPI63_R = crate::BitReader; +pub type SPI63_R = crate::BitReader; #[doc = "Field `SPI63` writer - Shared interrupt 63"] -pub type SPI63_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR0_SPEC, bool, O>; +pub type SPI63_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Shared interrupt 32"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { SPI63_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_SPISR0") + .field("spi32", &format_args!("{}", self.spi32().bit())) + .field("spi33", &format_args!("{}", self.spi33().bit())) + .field("spi34", &format_args!("{}", self.spi34().bit())) + .field("spi35", &format_args!("{}", self.spi35().bit())) + .field("spi36", &format_args!("{}", self.spi36().bit())) + .field("spi37", &format_args!("{}", self.spi37().bit())) + .field("spi38", &format_args!("{}", self.spi38().bit())) + .field("spi39", &format_args!("{}", self.spi39().bit())) + .field("spi40", &format_args!("{}", self.spi40().bit())) + .field("spi41", &format_args!("{}", self.spi41().bit())) + .field("spi42", &format_args!("{}", self.spi42().bit())) + .field("spi43", &format_args!("{}", self.spi43().bit())) + .field("spi44", &format_args!("{}", self.spi44().bit())) + .field("spi45", &format_args!("{}", self.spi45().bit())) + .field("spi46", &format_args!("{}", self.spi46().bit())) + .field("spi47", &format_args!("{}", self.spi47().bit())) + .field("spi48", &format_args!("{}", self.spi48().bit())) + .field("spi49", &format_args!("{}", self.spi49().bit())) + .field("spi50", &format_args!("{}", self.spi50().bit())) + .field("spi51", &format_args!("{}", self.spi51().bit())) + .field("spi52", &format_args!("{}", self.spi52().bit())) + .field("spi53", &format_args!("{}", self.spi53().bit())) + .field("spi54", &format_args!("{}", self.spi54().bit())) + .field("spi55", &format_args!("{}", self.spi55().bit())) + .field("spi56", &format_args!("{}", self.spi56().bit())) + .field("spi57", &format_args!("{}", self.spi57().bit())) + .field("spi58", &format_args!("{}", self.spi58().bit())) + .field("spi59", &format_args!("{}", self.spi59().bit())) + .field("spi60", &format_args!("{}", self.spi60().bit())) + .field("spi61", &format_args!("{}", self.spi61().bit())) + .field("spi62", &format_args!("{}", self.spi62().bit())) + .field("spi63", &format_args!("{}", self.spi63().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Shared interrupt 32"] #[inline(always)] #[must_use] - pub fn spi32(&mut self) -> SPI32_W<0> { + pub fn spi32(&mut self) -> SPI32_W { SPI32_W::new(self) } #[doc = "Bit 1 - Shared interrupt 33"] #[inline(always)] #[must_use] - pub fn spi33(&mut self) -> SPI33_W<1> { + pub fn spi33(&mut self) -> SPI33_W { SPI33_W::new(self) } #[doc = "Bit 2 - Shared interrupt 34"] #[inline(always)] #[must_use] - pub fn spi34(&mut self) -> SPI34_W<2> { + pub fn spi34(&mut self) -> SPI34_W { SPI34_W::new(self) } #[doc = "Bit 3 - Shared interrupt 35"] #[inline(always)] #[must_use] - pub fn spi35(&mut self) -> SPI35_W<3> { + pub fn spi35(&mut self) -> SPI35_W { SPI35_W::new(self) } #[doc = "Bit 4 - Shared interrupt 36"] #[inline(always)] #[must_use] - pub fn spi36(&mut self) -> SPI36_W<4> { + pub fn spi36(&mut self) -> SPI36_W { SPI36_W::new(self) } #[doc = "Bit 5 - Shared interrupt 37"] #[inline(always)] #[must_use] - pub fn spi37(&mut self) -> SPI37_W<5> { + pub fn spi37(&mut self) -> SPI37_W { SPI37_W::new(self) } #[doc = "Bit 6 - Shared interrupt 38"] #[inline(always)] #[must_use] - pub fn spi38(&mut self) -> SPI38_W<6> { + pub fn spi38(&mut self) -> SPI38_W { SPI38_W::new(self) } #[doc = "Bit 7 - Shared interrupt 39"] #[inline(always)] #[must_use] - pub fn spi39(&mut self) -> SPI39_W<7> { + pub fn spi39(&mut self) -> SPI39_W { SPI39_W::new(self) } #[doc = "Bit 8 - Shared interrupt 40"] #[inline(always)] #[must_use] - pub fn spi40(&mut self) -> SPI40_W<8> { + pub fn spi40(&mut self) -> SPI40_W { SPI40_W::new(self) } #[doc = "Bit 9 - Shared interrupt 41"] #[inline(always)] #[must_use] - pub fn spi41(&mut self) -> SPI41_W<9> { + pub fn spi41(&mut self) -> SPI41_W { SPI41_W::new(self) } #[doc = "Bit 10 - Shared interrupt 42"] #[inline(always)] #[must_use] - pub fn spi42(&mut self) -> SPI42_W<10> { + pub fn spi42(&mut self) -> SPI42_W { SPI42_W::new(self) } #[doc = "Bit 11 - Shared interrupt 43"] #[inline(always)] #[must_use] - pub fn spi43(&mut self) -> SPI43_W<11> { + pub fn spi43(&mut self) -> SPI43_W { SPI43_W::new(self) } #[doc = "Bit 12 - Shared interrupt 44"] #[inline(always)] #[must_use] - pub fn spi44(&mut self) -> SPI44_W<12> { + pub fn spi44(&mut self) -> SPI44_W { SPI44_W::new(self) } #[doc = "Bit 13 - Shared interrupt 45"] #[inline(always)] #[must_use] - pub fn spi45(&mut self) -> SPI45_W<13> { + pub fn spi45(&mut self) -> SPI45_W { SPI45_W::new(self) } #[doc = "Bit 14 - Shared interrupt 46"] #[inline(always)] #[must_use] - pub fn spi46(&mut self) -> SPI46_W<14> { + pub fn spi46(&mut self) -> SPI46_W { SPI46_W::new(self) } #[doc = "Bit 15 - Shared interrupt 47"] #[inline(always)] #[must_use] - pub fn spi47(&mut self) -> SPI47_W<15> { + pub fn spi47(&mut self) -> SPI47_W { SPI47_W::new(self) } #[doc = "Bit 16 - Shared interrupt 48"] #[inline(always)] #[must_use] - pub fn spi48(&mut self) -> SPI48_W<16> { + pub fn spi48(&mut self) -> SPI48_W { SPI48_W::new(self) } #[doc = "Bit 17 - Shared interrupt 49"] #[inline(always)] #[must_use] - pub fn spi49(&mut self) -> SPI49_W<17> { + pub fn spi49(&mut self) -> SPI49_W { SPI49_W::new(self) } #[doc = "Bit 18 - Shared interrupt 50"] #[inline(always)] #[must_use] - pub fn spi50(&mut self) -> SPI50_W<18> { + pub fn spi50(&mut self) -> SPI50_W { SPI50_W::new(self) } #[doc = "Bit 19 - Shared interrupt 51"] #[inline(always)] #[must_use] - pub fn spi51(&mut self) -> SPI51_W<19> { + pub fn spi51(&mut self) -> SPI51_W { SPI51_W::new(self) } #[doc = "Bit 20 - Shared interrupt 52"] #[inline(always)] #[must_use] - pub fn spi52(&mut self) -> SPI52_W<20> { + pub fn spi52(&mut self) -> SPI52_W { SPI52_W::new(self) } #[doc = "Bit 21 - Shared interrupt 53"] #[inline(always)] #[must_use] - pub fn spi53(&mut self) -> SPI53_W<21> { + pub fn spi53(&mut self) -> SPI53_W { SPI53_W::new(self) } #[doc = "Bit 22 - Shared interrupt 54"] #[inline(always)] #[must_use] - pub fn spi54(&mut self) -> SPI54_W<22> { + pub fn spi54(&mut self) -> SPI54_W { SPI54_W::new(self) } #[doc = "Bit 23 - Shared interrupt 55"] #[inline(always)] #[must_use] - pub fn spi55(&mut self) -> SPI55_W<23> { + pub fn spi55(&mut self) -> SPI55_W { SPI55_W::new(self) } #[doc = "Bit 24 - Shared interrupt 56"] #[inline(always)] #[must_use] - pub fn spi56(&mut self) -> SPI56_W<24> { + pub fn spi56(&mut self) -> SPI56_W { SPI56_W::new(self) } #[doc = "Bit 25 - Shared interrupt 57"] #[inline(always)] #[must_use] - pub fn spi57(&mut self) -> SPI57_W<25> { + pub fn spi57(&mut self) -> SPI57_W { SPI57_W::new(self) } #[doc = "Bit 26 - Shared interrupt 58"] #[inline(always)] #[must_use] - pub fn spi58(&mut self) -> SPI58_W<26> { + pub fn spi58(&mut self) -> SPI58_W { SPI58_W::new(self) } #[doc = "Bit 27 - Shared interrupt 59"] #[inline(always)] #[must_use] - pub fn spi59(&mut self) -> SPI59_W<27> { + pub fn spi59(&mut self) -> SPI59_W { SPI59_W::new(self) } #[doc = "Bit 28 - Shared interrupt 60"] #[inline(always)] #[must_use] - pub fn spi60(&mut self) -> SPI60_W<28> { + pub fn spi60(&mut self) -> SPI60_W { SPI60_W::new(self) } #[doc = "Bit 29 - Shared interrupt 61"] #[inline(always)] #[must_use] - pub fn spi61(&mut self) -> SPI61_W<29> { + pub fn spi61(&mut self) -> SPI61_W { SPI61_W::new(self) } #[doc = "Bit 30 - Shared interrupt 62"] #[inline(always)] #[must_use] - pub fn spi62(&mut self) -> SPI62_W<30> { + pub fn spi62(&mut self) -> SPI62_W { SPI62_W::new(self) } #[doc = "Bit 31 - Shared interrupt 63"] #[inline(always)] #[must_use] - pub fn spi63(&mut self) -> SPI63_W<31> { + pub fn spi63(&mut self) -> SPI63_W { SPI63_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Shared Peripheral Interrupt Status Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spisr0](index.html) module"] +#[doc = "Shared Peripheral Interrupt Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spisr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spisr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_SPISR0_SPEC; impl crate::RegisterSpec for GICD_SPISR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_spisr0::R](R) reader structure"] -impl crate::Readable for GICD_SPISR0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_spisr0::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_spisr0::R`](R) reader structure"] +impl crate::Readable for GICD_SPISR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_spisr0::W`](W) writer structure"] impl crate::Writable for GICD_SPISR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr1.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr1.rs index 5a14b66..132f983 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr1.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr1.rs @@ -1,168 +1,135 @@ #[doc = "Register `GICD_SPISR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_SPISR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI0` reader - Software interrupt 0"] -pub type SWI0_R = crate::BitReader; +pub type SWI0_R = crate::BitReader; #[doc = "Field `SWI0` writer - Software interrupt 0"] -pub type SWI0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SWI0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI1` reader - Software interrupt 1"] -pub type SWI1_R = crate::BitReader; +pub type SWI1_R = crate::BitReader; #[doc = "Field `SWI1` writer - Software interrupt 1"] -pub type SWI1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SWI1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI2` reader - Software interrupt 2"] -pub type SWI2_R = crate::BitReader; +pub type SWI2_R = crate::BitReader; #[doc = "Field `SWI2` writer - Software interrupt 2"] -pub type SWI2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SWI2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI3` reader - Software interrupt 3"] -pub type SWI3_R = crate::BitReader; +pub type SWI3_R = crate::BitReader; #[doc = "Field `SWI3` writer - Software interrupt 3"] -pub type SWI3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SWI3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI4` reader - Software interrupt 4"] -pub type SWI4_R = crate::BitReader; +pub type SWI4_R = crate::BitReader; #[doc = "Field `SWI4` writer - Software interrupt 4"] -pub type SWI4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SWI4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI5` reader - Software interrupt 5"] -pub type SWI5_R = crate::BitReader; +pub type SWI5_R = crate::BitReader; #[doc = "Field `SWI5` writer - Software interrupt 5"] -pub type SWI5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SWI5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI6` reader - Software interrupt 6"] -pub type SWI6_R = crate::BitReader; +pub type SWI6_R = crate::BitReader; #[doc = "Field `SWI6` writer - Software interrupt 6"] -pub type SWI6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SWI6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWI7` reader - Software interrupt 7"] -pub type SWI7_R = crate::BitReader; +pub type SWI7_R = crate::BitReader; #[doc = "Field `SWI7` writer - Software interrupt 7"] -pub type SWI7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SWI7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI80` reader - Shared interrupt 80"] -pub type SPI80_R = crate::BitReader; +pub type SPI80_R = crate::BitReader; #[doc = "Field `SPI80` writer - Shared interrupt 80"] -pub type SPI80_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI80_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI81` reader - Shared interrupt 81"] -pub type SPI81_R = crate::BitReader; +pub type SPI81_R = crate::BitReader; #[doc = "Field `SPI81` writer - Shared interrupt 81"] -pub type SPI81_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI81_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI82` reader - Shared interrupt 82"] -pub type SPI82_R = crate::BitReader; +pub type SPI82_R = crate::BitReader; #[doc = "Field `SPI82` writer - Shared interrupt 82"] -pub type SPI82_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI82_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI83` reader - Shared interrupt 83"] -pub type SPI83_R = crate::BitReader; +pub type SPI83_R = crate::BitReader; #[doc = "Field `SPI83` writer - Shared interrupt 83"] -pub type SPI83_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI83_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI84` reader - Shared interrupt 84"] -pub type SPI84_R = crate::BitReader; +pub type SPI84_R = crate::BitReader; #[doc = "Field `SPI84` writer - Shared interrupt 84"] -pub type SPI84_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI84_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI85` reader - Shared interrupt 85"] -pub type SPI85_R = crate::BitReader; +pub type SPI85_R = crate::BitReader; #[doc = "Field `SPI85` writer - Shared interrupt 85"] -pub type SPI85_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI85_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI86` reader - Shared interrupt 86"] -pub type SPI86_R = crate::BitReader; +pub type SPI86_R = crate::BitReader; #[doc = "Field `SPI86` writer - Shared interrupt 86"] -pub type SPI86_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI86_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI87` reader - Shared interrupt 87"] -pub type SPI87_R = crate::BitReader; +pub type SPI87_R = crate::BitReader; #[doc = "Field `SPI87` writer - Shared interrupt 87"] -pub type SPI87_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI87_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI88` reader - Shared interrupt 88"] -pub type SPI88_R = crate::BitReader; +pub type SPI88_R = crate::BitReader; #[doc = "Field `SPI88` writer - Shared interrupt 88"] -pub type SPI88_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI88_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI89` reader - Shared interrupt 89"] -pub type SPI89_R = crate::BitReader; +pub type SPI89_R = crate::BitReader; #[doc = "Field `SPI89` writer - Shared interrupt 89"] -pub type SPI89_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI89_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI90` reader - Shared interrupt 90"] -pub type SPI90_R = crate::BitReader; +pub type SPI90_R = crate::BitReader; #[doc = "Field `SPI90` writer - Shared interrupt 90"] -pub type SPI90_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI90_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI91` reader - Shared interrupt 91"] -pub type SPI91_R = crate::BitReader; +pub type SPI91_R = crate::BitReader; #[doc = "Field `SPI91` writer - Shared interrupt 91"] -pub type SPI91_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI91_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI92` reader - Shared interrupt 92"] -pub type SPI92_R = crate::BitReader; +pub type SPI92_R = crate::BitReader; #[doc = "Field `SPI92` writer - Shared interrupt 92"] -pub type SPI92_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI92_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI93` reader - Shared interrupt 93"] -pub type SPI93_R = crate::BitReader; +pub type SPI93_R = crate::BitReader; #[doc = "Field `SPI93` writer - Shared interrupt 93"] -pub type SPI93_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI93_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI94` reader - Shared interrupt 94"] -pub type SPI94_R = crate::BitReader; +pub type SPI94_R = crate::BitReader; #[doc = "Field `SPI94` writer - Shared interrupt 94"] -pub type SPI94_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI94_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI95` reader - Shared interrupt 95"] -pub type SPI95_R = crate::BitReader; +pub type SPI95_R = crate::BitReader; #[doc = "Field `SPI95` writer - Shared interrupt 95"] -pub type SPI95_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR1_SPEC, bool, O>; +pub type SPI95_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -325,218 +292,268 @@ impl R { SPI95_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_SPISR1") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .field("swi0", &format_args!("{}", self.swi0().bit())) + .field("swi1", &format_args!("{}", self.swi1().bit())) + .field("swi2", &format_args!("{}", self.swi2().bit())) + .field("swi3", &format_args!("{}", self.swi3().bit())) + .field("swi4", &format_args!("{}", self.swi4().bit())) + .field("swi5", &format_args!("{}", self.swi5().bit())) + .field("swi6", &format_args!("{}", self.swi6().bit())) + .field("swi7", &format_args!("{}", self.swi7().bit())) + .field("spi80", &format_args!("{}", self.spi80().bit())) + .field("spi81", &format_args!("{}", self.spi81().bit())) + .field("spi82", &format_args!("{}", self.spi82().bit())) + .field("spi83", &format_args!("{}", self.spi83().bit())) + .field("spi84", &format_args!("{}", self.spi84().bit())) + .field("spi85", &format_args!("{}", self.spi85().bit())) + .field("spi86", &format_args!("{}", self.spi86().bit())) + .field("spi87", &format_args!("{}", self.spi87().bit())) + .field("spi88", &format_args!("{}", self.spi88().bit())) + .field("spi89", &format_args!("{}", self.spi89().bit())) + .field("spi90", &format_args!("{}", self.spi90().bit())) + .field("spi91", &format_args!("{}", self.spi91().bit())) + .field("spi92", &format_args!("{}", self.spi92().bit())) + .field("spi93", &format_args!("{}", self.spi93().bit())) + .field("spi94", &format_args!("{}", self.spi94().bit())) + .field("spi95", &format_args!("{}", self.spi95().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } #[doc = "Bit 8 - Software interrupt 0"] #[inline(always)] #[must_use] - pub fn swi0(&mut self) -> SWI0_W<8> { + pub fn swi0(&mut self) -> SWI0_W { SWI0_W::new(self) } #[doc = "Bit 9 - Software interrupt 1"] #[inline(always)] #[must_use] - pub fn swi1(&mut self) -> SWI1_W<9> { + pub fn swi1(&mut self) -> SWI1_W { SWI1_W::new(self) } #[doc = "Bit 10 - Software interrupt 2"] #[inline(always)] #[must_use] - pub fn swi2(&mut self) -> SWI2_W<10> { + pub fn swi2(&mut self) -> SWI2_W { SWI2_W::new(self) } #[doc = "Bit 11 - Software interrupt 3"] #[inline(always)] #[must_use] - pub fn swi3(&mut self) -> SWI3_W<11> { + pub fn swi3(&mut self) -> SWI3_W { SWI3_W::new(self) } #[doc = "Bit 12 - Software interrupt 4"] #[inline(always)] #[must_use] - pub fn swi4(&mut self) -> SWI4_W<12> { + pub fn swi4(&mut self) -> SWI4_W { SWI4_W::new(self) } #[doc = "Bit 13 - Software interrupt 5"] #[inline(always)] #[must_use] - pub fn swi5(&mut self) -> SWI5_W<13> { + pub fn swi5(&mut self) -> SWI5_W { SWI5_W::new(self) } #[doc = "Bit 14 - Software interrupt 6"] #[inline(always)] #[must_use] - pub fn swi6(&mut self) -> SWI6_W<14> { + pub fn swi6(&mut self) -> SWI6_W { SWI6_W::new(self) } #[doc = "Bit 15 - Software interrupt 7"] #[inline(always)] #[must_use] - pub fn swi7(&mut self) -> SWI7_W<15> { + pub fn swi7(&mut self) -> SWI7_W { SWI7_W::new(self) } #[doc = "Bit 16 - Shared interrupt 80"] #[inline(always)] #[must_use] - pub fn spi80(&mut self) -> SPI80_W<16> { + pub fn spi80(&mut self) -> SPI80_W { SPI80_W::new(self) } #[doc = "Bit 17 - Shared interrupt 81"] #[inline(always)] #[must_use] - pub fn spi81(&mut self) -> SPI81_W<17> { + pub fn spi81(&mut self) -> SPI81_W { SPI81_W::new(self) } #[doc = "Bit 18 - Shared interrupt 82"] #[inline(always)] #[must_use] - pub fn spi82(&mut self) -> SPI82_W<18> { + pub fn spi82(&mut self) -> SPI82_W { SPI82_W::new(self) } #[doc = "Bit 19 - Shared interrupt 83"] #[inline(always)] #[must_use] - pub fn spi83(&mut self) -> SPI83_W<19> { + pub fn spi83(&mut self) -> SPI83_W { SPI83_W::new(self) } #[doc = "Bit 20 - Shared interrupt 84"] #[inline(always)] #[must_use] - pub fn spi84(&mut self) -> SPI84_W<20> { + pub fn spi84(&mut self) -> SPI84_W { SPI84_W::new(self) } #[doc = "Bit 21 - Shared interrupt 85"] #[inline(always)] #[must_use] - pub fn spi85(&mut self) -> SPI85_W<21> { + pub fn spi85(&mut self) -> SPI85_W { SPI85_W::new(self) } #[doc = "Bit 22 - Shared interrupt 86"] #[inline(always)] #[must_use] - pub fn spi86(&mut self) -> SPI86_W<22> { + pub fn spi86(&mut self) -> SPI86_W { SPI86_W::new(self) } #[doc = "Bit 23 - Shared interrupt 87"] #[inline(always)] #[must_use] - pub fn spi87(&mut self) -> SPI87_W<23> { + pub fn spi87(&mut self) -> SPI87_W { SPI87_W::new(self) } #[doc = "Bit 24 - Shared interrupt 88"] #[inline(always)] #[must_use] - pub fn spi88(&mut self) -> SPI88_W<24> { + pub fn spi88(&mut self) -> SPI88_W { SPI88_W::new(self) } #[doc = "Bit 25 - Shared interrupt 89"] #[inline(always)] #[must_use] - pub fn spi89(&mut self) -> SPI89_W<25> { + pub fn spi89(&mut self) -> SPI89_W { SPI89_W::new(self) } #[doc = "Bit 26 - Shared interrupt 90"] #[inline(always)] #[must_use] - pub fn spi90(&mut self) -> SPI90_W<26> { + pub fn spi90(&mut self) -> SPI90_W { SPI90_W::new(self) } #[doc = "Bit 27 - Shared interrupt 91"] #[inline(always)] #[must_use] - pub fn spi91(&mut self) -> SPI91_W<27> { + pub fn spi91(&mut self) -> SPI91_W { SPI91_W::new(self) } #[doc = "Bit 28 - Shared interrupt 92"] #[inline(always)] #[must_use] - pub fn spi92(&mut self) -> SPI92_W<28> { + pub fn spi92(&mut self) -> SPI92_W { SPI92_W::new(self) } #[doc = "Bit 29 - Shared interrupt 93"] #[inline(always)] #[must_use] - pub fn spi93(&mut self) -> SPI93_W<29> { + pub fn spi93(&mut self) -> SPI93_W { SPI93_W::new(self) } #[doc = "Bit 30 - Shared interrupt 94"] #[inline(always)] #[must_use] - pub fn spi94(&mut self) -> SPI94_W<30> { + pub fn spi94(&mut self) -> SPI94_W { SPI94_W::new(self) } #[doc = "Bit 31 - Shared interrupt 95"] #[inline(always)] #[must_use] - pub fn spi95(&mut self) -> SPI95_W<31> { + pub fn spi95(&mut self) -> SPI95_W { SPI95_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Shared Peripheral Interrupt Status Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spisr1](index.html) module"] +#[doc = "Shared Peripheral Interrupt Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spisr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spisr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_SPISR1_SPEC; impl crate::RegisterSpec for GICD_SPISR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_spisr1::R](R) reader structure"] -impl crate::Readable for GICD_SPISR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_spisr1::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_spisr1::R`](R) reader structure"] +impl crate::Readable for GICD_SPISR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_spisr1::W`](W) writer structure"] impl crate::Writable for GICD_SPISR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr2.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr2.rs index ba4b79d..cf50471 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr2.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr2.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_SPISR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_SPISR2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR2_SPEC, bool, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -324,218 +292,274 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_SPISR2") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bit 1 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<1> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bit 2 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<2> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bit 3 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<3> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } #[doc = "Bit 4 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<4> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bit 5 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<5> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bit 6 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<6> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bit 7 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<7> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } #[doc = "Bit 8 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<8> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bit 9 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<9> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 10 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<10> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bit 11 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } #[doc = "Bit 12 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bit 13 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bit 14 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bit 15 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } #[doc = "Bit 16 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<16> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bit 17 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<17> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 18 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<18> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 19 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<19> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 20 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<20> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 21 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<21> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 22 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<22> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 23 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } #[doc = "Bit 24 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bit 25 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<25> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bit 26 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<26> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bit 27 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<27> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } #[doc = "Bit 28 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<28> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<29> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bit 30 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<30> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bit 31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<31> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Shared Peripheral Interrupt Status Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spisr2](index.html) module"] +#[doc = "Shared Peripheral Interrupt Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spisr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spisr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_SPISR2_SPEC; impl crate::RegisterSpec for GICD_SPISR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_spisr2::R](R) reader structure"] -impl crate::Readable for GICD_SPISR2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_spisr2::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_spisr2::R`](R) reader structure"] +impl crate::Readable for GICD_SPISR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_spisr2::W`](W) writer structure"] impl crate::Writable for GICD_SPISR2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr3.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr3.rs index 18ccfd0..3dcb77a 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr3.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr3.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_SPISR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_SPISR3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type UART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR3_SPEC, bool, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -324,218 +292,280 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_SPISR3") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bit 1 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<1> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bit 2 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<2> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bit 3 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<3> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } #[doc = "Bit 4 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<4> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bit 5 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bit 6 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bit 7 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } #[doc = "Bit 8 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bit 9 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bit 10 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bit 11 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } #[doc = "Bit 12 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<12> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bit 13 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bit 15 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<15> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } #[doc = "Bit 16 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<16> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bit 17 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bit 18 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bit 19 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } #[doc = "Bit 20 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bit 21 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<21> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bit 22 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<22> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bit 23 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } #[doc = "Bit 24 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<24> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bit 25 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<25> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bit 26 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bit 27 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<27> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } #[doc = "Bit 28 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<28> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bit 29 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<29> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bit 30 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<30> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bit 31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Shared Peripheral Interrupt Status Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spisr3](index.html) module"] +#[doc = "Shared Peripheral Interrupt Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spisr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spisr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_SPISR3_SPEC; impl crate::RegisterSpec for GICD_SPISR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_spisr3::R](R) reader structure"] -impl crate::Readable for GICD_SPISR3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_spisr3::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_spisr3::R`](R) reader structure"] +impl crate::Readable for GICD_SPISR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_spisr3::W`](W) writer structure"] impl crate::Writable for GICD_SPISR3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr4.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr4.rs index 5ffc919..cd31bdc 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr4.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr4.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_SPISR4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_SPISR4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SPI160` reader - Shared interrupt 160"] -pub type SPI160_R = crate::BitReader; +pub type SPI160_R = crate::BitReader; #[doc = "Field `SPI160` writer - Shared interrupt 160"] -pub type SPI160_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI160_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI161` reader - Shared interrupt 161"] -pub type SPI161_R = crate::BitReader; +pub type SPI161_R = crate::BitReader; #[doc = "Field `SPI161` writer - Shared interrupt 161"] -pub type SPI161_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI161_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI162` reader - Shared interrupt 162"] -pub type SPI162_R = crate::BitReader; +pub type SPI162_R = crate::BitReader; #[doc = "Field `SPI162` writer - Shared interrupt 162"] -pub type SPI162_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI162_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI163` reader - Shared interrupt 163"] -pub type SPI163_R = crate::BitReader; +pub type SPI163_R = crate::BitReader; #[doc = "Field `SPI163` writer - Shared interrupt 163"] -pub type SPI163_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI163_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI164` reader - Shared interrupt 164"] -pub type SPI164_R = crate::BitReader; +pub type SPI164_R = crate::BitReader; #[doc = "Field `SPI164` writer - Shared interrupt 164"] -pub type SPI164_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI164_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI165` reader - Shared interrupt 165"] -pub type SPI165_R = crate::BitReader; +pub type SPI165_R = crate::BitReader; #[doc = "Field `SPI165` writer - Shared interrupt 165"] -pub type SPI165_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI165_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI166` reader - Shared interrupt 166"] -pub type SPI166_R = crate::BitReader; +pub type SPI166_R = crate::BitReader; #[doc = "Field `SPI166` writer - Shared interrupt 166"] -pub type SPI166_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI166_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI167` reader - Shared interrupt 167"] -pub type SPI167_R = crate::BitReader; +pub type SPI167_R = crate::BitReader; #[doc = "Field `SPI167` writer - Shared interrupt 167"] -pub type SPI167_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI167_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI168` reader - Shared interrupt 168"] -pub type SPI168_R = crate::BitReader; +pub type SPI168_R = crate::BitReader; #[doc = "Field `SPI168` writer - Shared interrupt 168"] -pub type SPI168_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI168_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI169` reader - Shared interrupt 169"] -pub type SPI169_R = crate::BitReader; +pub type SPI169_R = crate::BitReader; #[doc = "Field `SPI169` writer - Shared interrupt 169"] -pub type SPI169_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI169_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI170` reader - Shared interrupt 170"] -pub type SPI170_R = crate::BitReader; +pub type SPI170_R = crate::BitReader; #[doc = "Field `SPI170` writer - Shared interrupt 170"] -pub type SPI170_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI170_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI171` reader - Shared interrupt 171"] -pub type SPI171_R = crate::BitReader; +pub type SPI171_R = crate::BitReader; #[doc = "Field `SPI171` writer - Shared interrupt 171"] -pub type SPI171_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI171_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI172` reader - Shared interrupt 172"] -pub type SPI172_R = crate::BitReader; +pub type SPI172_R = crate::BitReader; #[doc = "Field `SPI172` writer - Shared interrupt 172"] -pub type SPI172_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI172_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI173` reader - Shared interrupt 173"] -pub type SPI173_R = crate::BitReader; +pub type SPI173_R = crate::BitReader; #[doc = "Field `SPI173` writer - Shared interrupt 173"] -pub type SPI173_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI173_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI174` reader - Shared interrupt 174"] -pub type SPI174_R = crate::BitReader; +pub type SPI174_R = crate::BitReader; #[doc = "Field `SPI174` writer - Shared interrupt 174"] -pub type SPI174_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI174_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI175` reader - Shared interrupt 175"] -pub type SPI175_R = crate::BitReader; +pub type SPI175_R = crate::BitReader; #[doc = "Field `SPI175` writer - Shared interrupt 175"] -pub type SPI175_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI175_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI176` reader - Shared interrupt 176"] -pub type SPI176_R = crate::BitReader; +pub type SPI176_R = crate::BitReader; #[doc = "Field `SPI176` writer - Shared interrupt 176"] -pub type SPI176_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI176_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI177` reader - Shared interrupt 177"] -pub type SPI177_R = crate::BitReader; +pub type SPI177_R = crate::BitReader; #[doc = "Field `SPI177` writer - Shared interrupt 177"] -pub type SPI177_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI177_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI178` reader - Shared interrupt 178"] -pub type SPI178_R = crate::BitReader; +pub type SPI178_R = crate::BitReader; #[doc = "Field `SPI178` writer - Shared interrupt 178"] -pub type SPI178_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI178_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI179` reader - Shared interrupt 179"] -pub type SPI179_R = crate::BitReader; +pub type SPI179_R = crate::BitReader; #[doc = "Field `SPI179` writer - Shared interrupt 179"] -pub type SPI179_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI179_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI180` reader - Shared interrupt 180"] -pub type SPI180_R = crate::BitReader; +pub type SPI180_R = crate::BitReader; #[doc = "Field `SPI180` writer - Shared interrupt 180"] -pub type SPI180_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI180_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI181` reader - Shared interrupt 181"] -pub type SPI181_R = crate::BitReader; +pub type SPI181_R = crate::BitReader; #[doc = "Field `SPI181` writer - Shared interrupt 181"] -pub type SPI181_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI181_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI182` reader - Shared interrupt 182"] -pub type SPI182_R = crate::BitReader; +pub type SPI182_R = crate::BitReader; #[doc = "Field `SPI182` writer - Shared interrupt 182"] -pub type SPI182_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI182_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI183` reader - Shared interrupt 183"] -pub type SPI183_R = crate::BitReader; +pub type SPI183_R = crate::BitReader; #[doc = "Field `SPI183` writer - Shared interrupt 183"] -pub type SPI183_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI183_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI184` reader - Shared interrupt 184"] -pub type SPI184_R = crate::BitReader; +pub type SPI184_R = crate::BitReader; #[doc = "Field `SPI184` writer - Shared interrupt 184"] -pub type SPI184_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI184_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI185` reader - Shared interrupt 185"] -pub type SPI185_R = crate::BitReader; +pub type SPI185_R = crate::BitReader; #[doc = "Field `SPI185` writer - Shared interrupt 185"] -pub type SPI185_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI185_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI186` reader - Shared interrupt 186"] -pub type SPI186_R = crate::BitReader; +pub type SPI186_R = crate::BitReader; #[doc = "Field `SPI186` writer - Shared interrupt 186"] -pub type SPI186_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI186_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI187` reader - Shared interrupt 187"] -pub type SPI187_R = crate::BitReader; +pub type SPI187_R = crate::BitReader; #[doc = "Field `SPI187` writer - Shared interrupt 187"] -pub type SPI187_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI187_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI188` reader - Shared interrupt 188"] -pub type SPI188_R = crate::BitReader; +pub type SPI188_R = crate::BitReader; #[doc = "Field `SPI188` writer - Shared interrupt 188"] -pub type SPI188_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI188_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI189` reader - Shared interrupt 189"] -pub type SPI189_R = crate::BitReader; +pub type SPI189_R = crate::BitReader; #[doc = "Field `SPI189` writer - Shared interrupt 189"] -pub type SPI189_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI189_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI190` reader - Shared interrupt 190"] -pub type SPI190_R = crate::BitReader; +pub type SPI190_R = crate::BitReader; #[doc = "Field `SPI190` writer - Shared interrupt 190"] -pub type SPI190_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI190_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI191` reader - Shared interrupt 191"] -pub type SPI191_R = crate::BitReader; +pub type SPI191_R = crate::BitReader; #[doc = "Field `SPI191` writer - Shared interrupt 191"] -pub type SPI191_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR4_SPEC, bool, O>; +pub type SPI191_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Shared interrupt 160"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { SPI191_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_SPISR4") + .field("spi160", &format_args!("{}", self.spi160().bit())) + .field("spi161", &format_args!("{}", self.spi161().bit())) + .field("spi162", &format_args!("{}", self.spi162().bit())) + .field("spi163", &format_args!("{}", self.spi163().bit())) + .field("spi164", &format_args!("{}", self.spi164().bit())) + .field("spi165", &format_args!("{}", self.spi165().bit())) + .field("spi166", &format_args!("{}", self.spi166().bit())) + .field("spi167", &format_args!("{}", self.spi167().bit())) + .field("spi168", &format_args!("{}", self.spi168().bit())) + .field("spi169", &format_args!("{}", self.spi169().bit())) + .field("spi170", &format_args!("{}", self.spi170().bit())) + .field("spi171", &format_args!("{}", self.spi171().bit())) + .field("spi172", &format_args!("{}", self.spi172().bit())) + .field("spi173", &format_args!("{}", self.spi173().bit())) + .field("spi174", &format_args!("{}", self.spi174().bit())) + .field("spi175", &format_args!("{}", self.spi175().bit())) + .field("spi176", &format_args!("{}", self.spi176().bit())) + .field("spi177", &format_args!("{}", self.spi177().bit())) + .field("spi178", &format_args!("{}", self.spi178().bit())) + .field("spi179", &format_args!("{}", self.spi179().bit())) + .field("spi180", &format_args!("{}", self.spi180().bit())) + .field("spi181", &format_args!("{}", self.spi181().bit())) + .field("spi182", &format_args!("{}", self.spi182().bit())) + .field("spi183", &format_args!("{}", self.spi183().bit())) + .field("spi184", &format_args!("{}", self.spi184().bit())) + .field("spi185", &format_args!("{}", self.spi185().bit())) + .field("spi186", &format_args!("{}", self.spi186().bit())) + .field("spi187", &format_args!("{}", self.spi187().bit())) + .field("spi188", &format_args!("{}", self.spi188().bit())) + .field("spi189", &format_args!("{}", self.spi189().bit())) + .field("spi190", &format_args!("{}", self.spi190().bit())) + .field("spi191", &format_args!("{}", self.spi191().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Shared interrupt 160"] #[inline(always)] #[must_use] - pub fn spi160(&mut self) -> SPI160_W<0> { + pub fn spi160(&mut self) -> SPI160_W { SPI160_W::new(self) } #[doc = "Bit 1 - Shared interrupt 161"] #[inline(always)] #[must_use] - pub fn spi161(&mut self) -> SPI161_W<1> { + pub fn spi161(&mut self) -> SPI161_W { SPI161_W::new(self) } #[doc = "Bit 2 - Shared interrupt 162"] #[inline(always)] #[must_use] - pub fn spi162(&mut self) -> SPI162_W<2> { + pub fn spi162(&mut self) -> SPI162_W { SPI162_W::new(self) } #[doc = "Bit 3 - Shared interrupt 163"] #[inline(always)] #[must_use] - pub fn spi163(&mut self) -> SPI163_W<3> { + pub fn spi163(&mut self) -> SPI163_W { SPI163_W::new(self) } #[doc = "Bit 4 - Shared interrupt 164"] #[inline(always)] #[must_use] - pub fn spi164(&mut self) -> SPI164_W<4> { + pub fn spi164(&mut self) -> SPI164_W { SPI164_W::new(self) } #[doc = "Bit 5 - Shared interrupt 165"] #[inline(always)] #[must_use] - pub fn spi165(&mut self) -> SPI165_W<5> { + pub fn spi165(&mut self) -> SPI165_W { SPI165_W::new(self) } #[doc = "Bit 6 - Shared interrupt 166"] #[inline(always)] #[must_use] - pub fn spi166(&mut self) -> SPI166_W<6> { + pub fn spi166(&mut self) -> SPI166_W { SPI166_W::new(self) } #[doc = "Bit 7 - Shared interrupt 167"] #[inline(always)] #[must_use] - pub fn spi167(&mut self) -> SPI167_W<7> { + pub fn spi167(&mut self) -> SPI167_W { SPI167_W::new(self) } #[doc = "Bit 8 - Shared interrupt 168"] #[inline(always)] #[must_use] - pub fn spi168(&mut self) -> SPI168_W<8> { + pub fn spi168(&mut self) -> SPI168_W { SPI168_W::new(self) } #[doc = "Bit 9 - Shared interrupt 169"] #[inline(always)] #[must_use] - pub fn spi169(&mut self) -> SPI169_W<9> { + pub fn spi169(&mut self) -> SPI169_W { SPI169_W::new(self) } #[doc = "Bit 10 - Shared interrupt 170"] #[inline(always)] #[must_use] - pub fn spi170(&mut self) -> SPI170_W<10> { + pub fn spi170(&mut self) -> SPI170_W { SPI170_W::new(self) } #[doc = "Bit 11 - Shared interrupt 171"] #[inline(always)] #[must_use] - pub fn spi171(&mut self) -> SPI171_W<11> { + pub fn spi171(&mut self) -> SPI171_W { SPI171_W::new(self) } #[doc = "Bit 12 - Shared interrupt 172"] #[inline(always)] #[must_use] - pub fn spi172(&mut self) -> SPI172_W<12> { + pub fn spi172(&mut self) -> SPI172_W { SPI172_W::new(self) } #[doc = "Bit 13 - Shared interrupt 173"] #[inline(always)] #[must_use] - pub fn spi173(&mut self) -> SPI173_W<13> { + pub fn spi173(&mut self) -> SPI173_W { SPI173_W::new(self) } #[doc = "Bit 14 - Shared interrupt 174"] #[inline(always)] #[must_use] - pub fn spi174(&mut self) -> SPI174_W<14> { + pub fn spi174(&mut self) -> SPI174_W { SPI174_W::new(self) } #[doc = "Bit 15 - Shared interrupt 175"] #[inline(always)] #[must_use] - pub fn spi175(&mut self) -> SPI175_W<15> { + pub fn spi175(&mut self) -> SPI175_W { SPI175_W::new(self) } #[doc = "Bit 16 - Shared interrupt 176"] #[inline(always)] #[must_use] - pub fn spi176(&mut self) -> SPI176_W<16> { + pub fn spi176(&mut self) -> SPI176_W { SPI176_W::new(self) } #[doc = "Bit 17 - Shared interrupt 177"] #[inline(always)] #[must_use] - pub fn spi177(&mut self) -> SPI177_W<17> { + pub fn spi177(&mut self) -> SPI177_W { SPI177_W::new(self) } #[doc = "Bit 18 - Shared interrupt 178"] #[inline(always)] #[must_use] - pub fn spi178(&mut self) -> SPI178_W<18> { + pub fn spi178(&mut self) -> SPI178_W { SPI178_W::new(self) } #[doc = "Bit 19 - Shared interrupt 179"] #[inline(always)] #[must_use] - pub fn spi179(&mut self) -> SPI179_W<19> { + pub fn spi179(&mut self) -> SPI179_W { SPI179_W::new(self) } #[doc = "Bit 20 - Shared interrupt 180"] #[inline(always)] #[must_use] - pub fn spi180(&mut self) -> SPI180_W<20> { + pub fn spi180(&mut self) -> SPI180_W { SPI180_W::new(self) } #[doc = "Bit 21 - Shared interrupt 181"] #[inline(always)] #[must_use] - pub fn spi181(&mut self) -> SPI181_W<21> { + pub fn spi181(&mut self) -> SPI181_W { SPI181_W::new(self) } #[doc = "Bit 22 - Shared interrupt 182"] #[inline(always)] #[must_use] - pub fn spi182(&mut self) -> SPI182_W<22> { + pub fn spi182(&mut self) -> SPI182_W { SPI182_W::new(self) } #[doc = "Bit 23 - Shared interrupt 183"] #[inline(always)] #[must_use] - pub fn spi183(&mut self) -> SPI183_W<23> { + pub fn spi183(&mut self) -> SPI183_W { SPI183_W::new(self) } #[doc = "Bit 24 - Shared interrupt 184"] #[inline(always)] #[must_use] - pub fn spi184(&mut self) -> SPI184_W<24> { + pub fn spi184(&mut self) -> SPI184_W { SPI184_W::new(self) } #[doc = "Bit 25 - Shared interrupt 185"] #[inline(always)] #[must_use] - pub fn spi185(&mut self) -> SPI185_W<25> { + pub fn spi185(&mut self) -> SPI185_W { SPI185_W::new(self) } #[doc = "Bit 26 - Shared interrupt 186"] #[inline(always)] #[must_use] - pub fn spi186(&mut self) -> SPI186_W<26> { + pub fn spi186(&mut self) -> SPI186_W { SPI186_W::new(self) } #[doc = "Bit 27 - Shared interrupt 187"] #[inline(always)] #[must_use] - pub fn spi187(&mut self) -> SPI187_W<27> { + pub fn spi187(&mut self) -> SPI187_W { SPI187_W::new(self) } #[doc = "Bit 28 - Shared interrupt 188"] #[inline(always)] #[must_use] - pub fn spi188(&mut self) -> SPI188_W<28> { + pub fn spi188(&mut self) -> SPI188_W { SPI188_W::new(self) } #[doc = "Bit 29 - Shared interrupt 189"] #[inline(always)] #[must_use] - pub fn spi189(&mut self) -> SPI189_W<29> { + pub fn spi189(&mut self) -> SPI189_W { SPI189_W::new(self) } #[doc = "Bit 30 - Shared interrupt 190"] #[inline(always)] #[must_use] - pub fn spi190(&mut self) -> SPI190_W<30> { + pub fn spi190(&mut self) -> SPI190_W { SPI190_W::new(self) } #[doc = "Bit 31 - Shared interrupt 191"] #[inline(always)] #[must_use] - pub fn spi191(&mut self) -> SPI191_W<31> { + pub fn spi191(&mut self) -> SPI191_W { SPI191_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Shared Peripheral Interrupt Status Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spisr4](index.html) module"] +#[doc = "Shared Peripheral Interrupt Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spisr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spisr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_SPISR4_SPEC; impl crate::RegisterSpec for GICD_SPISR4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_spisr4::R](R) reader structure"] -impl crate::Readable for GICD_SPISR4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_spisr4::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_spisr4::R`](R) reader structure"] +impl crate::Readable for GICD_SPISR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_spisr4::W`](W) writer structure"] impl crate::Writable for GICD_SPISR4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr5.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr5.rs index efb5a72..c907dbc 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_spisr5.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_spisr5.rs @@ -1,167 +1,135 @@ #[doc = "Register `GICD_SPISR5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GICD_SPISR5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SPI192` reader - Shared interrupt 192"] -pub type SPI192_R = crate::BitReader; +pub type SPI192_R = crate::BitReader; #[doc = "Field `SPI192` writer - Shared interrupt 192"] -pub type SPI192_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI192_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI193` reader - Shared interrupt 193"] -pub type SPI193_R = crate::BitReader; +pub type SPI193_R = crate::BitReader; #[doc = "Field `SPI193` writer - Shared interrupt 193"] -pub type SPI193_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI193_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI194` reader - Shared interrupt 194"] -pub type SPI194_R = crate::BitReader; +pub type SPI194_R = crate::BitReader; #[doc = "Field `SPI194` writer - Shared interrupt 194"] -pub type SPI194_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI194_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI195` reader - Shared interrupt 195"] -pub type SPI195_R = crate::BitReader; +pub type SPI195_R = crate::BitReader; #[doc = "Field `SPI195` writer - Shared interrupt 195"] -pub type SPI195_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI195_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI196` reader - Shared interrupt 196"] -pub type SPI196_R = crate::BitReader; +pub type SPI196_R = crate::BitReader; #[doc = "Field `SPI196` writer - Shared interrupt 196"] -pub type SPI196_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI196_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI197` reader - Shared interrupt 197"] -pub type SPI197_R = crate::BitReader; +pub type SPI197_R = crate::BitReader; #[doc = "Field `SPI197` writer - Shared interrupt 197"] -pub type SPI197_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI197_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI198` reader - Shared interrupt 198"] -pub type SPI198_R = crate::BitReader; +pub type SPI198_R = crate::BitReader; #[doc = "Field `SPI198` writer - Shared interrupt 198"] -pub type SPI198_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI198_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI199` reader - Shared interrupt 199"] -pub type SPI199_R = crate::BitReader; +pub type SPI199_R = crate::BitReader; #[doc = "Field `SPI199` writer - Shared interrupt 199"] -pub type SPI199_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI199_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI200` reader - Shared interrupt 200"] -pub type SPI200_R = crate::BitReader; +pub type SPI200_R = crate::BitReader; #[doc = "Field `SPI200` writer - Shared interrupt 200"] -pub type SPI200_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI200_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI201` reader - Shared interrupt 201"] -pub type SPI201_R = crate::BitReader; +pub type SPI201_R = crate::BitReader; #[doc = "Field `SPI201` writer - Shared interrupt 201"] -pub type SPI201_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI201_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI202` reader - Shared interrupt 202"] -pub type SPI202_R = crate::BitReader; +pub type SPI202_R = crate::BitReader; #[doc = "Field `SPI202` writer - Shared interrupt 202"] -pub type SPI202_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI202_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI203` reader - Shared interrupt 203"] -pub type SPI203_R = crate::BitReader; +pub type SPI203_R = crate::BitReader; #[doc = "Field `SPI203` writer - Shared interrupt 203"] -pub type SPI203_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI203_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI204` reader - Shared interrupt 204"] -pub type SPI204_R = crate::BitReader; +pub type SPI204_R = crate::BitReader; #[doc = "Field `SPI204` writer - Shared interrupt 204"] -pub type SPI204_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI204_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI205` reader - Shared interrupt 205"] -pub type SPI205_R = crate::BitReader; +pub type SPI205_R = crate::BitReader; #[doc = "Field `SPI205` writer - Shared interrupt 205"] -pub type SPI205_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI205_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI206` reader - Shared interrupt 206"] -pub type SPI206_R = crate::BitReader; +pub type SPI206_R = crate::BitReader; #[doc = "Field `SPI206` writer - Shared interrupt 206"] -pub type SPI206_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI206_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI207` reader - Shared interrupt 207"] -pub type SPI207_R = crate::BitReader; +pub type SPI207_R = crate::BitReader; #[doc = "Field `SPI207` writer - Shared interrupt 207"] -pub type SPI207_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI207_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI208` reader - Shared interrupt 208"] -pub type SPI208_R = crate::BitReader; +pub type SPI208_R = crate::BitReader; #[doc = "Field `SPI208` writer - Shared interrupt 208"] -pub type SPI208_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI208_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI209` reader - Shared interrupt 209"] -pub type SPI209_R = crate::BitReader; +pub type SPI209_R = crate::BitReader; #[doc = "Field `SPI209` writer - Shared interrupt 209"] -pub type SPI209_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI209_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI210` reader - Shared interrupt 210"] -pub type SPI210_R = crate::BitReader; +pub type SPI210_R = crate::BitReader; #[doc = "Field `SPI210` writer - Shared interrupt 210"] -pub type SPI210_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI210_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI211` reader - Shared interrupt 211"] -pub type SPI211_R = crate::BitReader; +pub type SPI211_R = crate::BitReader; #[doc = "Field `SPI211` writer - Shared interrupt 211"] -pub type SPI211_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI211_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI212` reader - Shared interrupt 212"] -pub type SPI212_R = crate::BitReader; +pub type SPI212_R = crate::BitReader; #[doc = "Field `SPI212` writer - Shared interrupt 212"] -pub type SPI212_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI212_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI213` reader - Shared interrupt 213"] -pub type SPI213_R = crate::BitReader; +pub type SPI213_R = crate::BitReader; #[doc = "Field `SPI213` writer - Shared interrupt 213"] -pub type SPI213_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI213_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI214` reader - Shared interrupt 214"] -pub type SPI214_R = crate::BitReader; +pub type SPI214_R = crate::BitReader; #[doc = "Field `SPI214` writer - Shared interrupt 214"] -pub type SPI214_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI214_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI215` reader - Shared interrupt 215"] -pub type SPI215_R = crate::BitReader; +pub type SPI215_R = crate::BitReader; #[doc = "Field `SPI215` writer - Shared interrupt 215"] -pub type SPI215_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI215_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI216` reader - Shared interrupt 216"] -pub type SPI216_R = crate::BitReader; +pub type SPI216_R = crate::BitReader; #[doc = "Field `SPI216` writer - Shared interrupt 216"] -pub type SPI216_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI216_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI217` reader - Shared interrupt 217"] -pub type SPI217_R = crate::BitReader; +pub type SPI217_R = crate::BitReader; #[doc = "Field `SPI217` writer - Shared interrupt 217"] -pub type SPI217_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI217_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI218` reader - Shared interrupt 218"] -pub type SPI218_R = crate::BitReader; +pub type SPI218_R = crate::BitReader; #[doc = "Field `SPI218` writer - Shared interrupt 218"] -pub type SPI218_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI218_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI219` reader - Shared interrupt 219"] -pub type SPI219_R = crate::BitReader; +pub type SPI219_R = crate::BitReader; #[doc = "Field `SPI219` writer - Shared interrupt 219"] -pub type SPI219_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI219_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI220` reader - Shared interrupt 220"] -pub type SPI220_R = crate::BitReader; +pub type SPI220_R = crate::BitReader; #[doc = "Field `SPI220` writer - Shared interrupt 220"] -pub type SPI220_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI220_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI221` reader - Shared interrupt 221"] -pub type SPI221_R = crate::BitReader; +pub type SPI221_R = crate::BitReader; #[doc = "Field `SPI221` writer - Shared interrupt 221"] -pub type SPI221_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI221_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI222` reader - Shared interrupt 222"] -pub type SPI222_R = crate::BitReader; +pub type SPI222_R = crate::BitReader; #[doc = "Field `SPI222` writer - Shared interrupt 222"] -pub type SPI222_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI222_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI223` reader - Shared interrupt 223"] -pub type SPI223_R = crate::BitReader; +pub type SPI223_R = crate::BitReader; #[doc = "Field `SPI223` writer - Shared interrupt 223"] -pub type SPI223_W<'a, const O: u8> = crate::BitWriter<'a, u32, GICD_SPISR5_SPEC, bool, O>; +pub type SPI223_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Shared interrupt 192"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { SPI223_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_SPISR5") + .field("spi192", &format_args!("{}", self.spi192().bit())) + .field("spi193", &format_args!("{}", self.spi193().bit())) + .field("spi194", &format_args!("{}", self.spi194().bit())) + .field("spi195", &format_args!("{}", self.spi195().bit())) + .field("spi196", &format_args!("{}", self.spi196().bit())) + .field("spi197", &format_args!("{}", self.spi197().bit())) + .field("spi198", &format_args!("{}", self.spi198().bit())) + .field("spi199", &format_args!("{}", self.spi199().bit())) + .field("spi200", &format_args!("{}", self.spi200().bit())) + .field("spi201", &format_args!("{}", self.spi201().bit())) + .field("spi202", &format_args!("{}", self.spi202().bit())) + .field("spi203", &format_args!("{}", self.spi203().bit())) + .field("spi204", &format_args!("{}", self.spi204().bit())) + .field("spi205", &format_args!("{}", self.spi205().bit())) + .field("spi206", &format_args!("{}", self.spi206().bit())) + .field("spi207", &format_args!("{}", self.spi207().bit())) + .field("spi208", &format_args!("{}", self.spi208().bit())) + .field("spi209", &format_args!("{}", self.spi209().bit())) + .field("spi210", &format_args!("{}", self.spi210().bit())) + .field("spi211", &format_args!("{}", self.spi211().bit())) + .field("spi212", &format_args!("{}", self.spi212().bit())) + .field("spi213", &format_args!("{}", self.spi213().bit())) + .field("spi214", &format_args!("{}", self.spi214().bit())) + .field("spi215", &format_args!("{}", self.spi215().bit())) + .field("spi216", &format_args!("{}", self.spi216().bit())) + .field("spi217", &format_args!("{}", self.spi217().bit())) + .field("spi218", &format_args!("{}", self.spi218().bit())) + .field("spi219", &format_args!("{}", self.spi219().bit())) + .field("spi220", &format_args!("{}", self.spi220().bit())) + .field("spi221", &format_args!("{}", self.spi221().bit())) + .field("spi222", &format_args!("{}", self.spi222().bit())) + .field("spi223", &format_args!("{}", self.spi223().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Shared interrupt 192"] #[inline(always)] #[must_use] - pub fn spi192(&mut self) -> SPI192_W<0> { + pub fn spi192(&mut self) -> SPI192_W { SPI192_W::new(self) } #[doc = "Bit 1 - Shared interrupt 193"] #[inline(always)] #[must_use] - pub fn spi193(&mut self) -> SPI193_W<1> { + pub fn spi193(&mut self) -> SPI193_W { SPI193_W::new(self) } #[doc = "Bit 2 - Shared interrupt 194"] #[inline(always)] #[must_use] - pub fn spi194(&mut self) -> SPI194_W<2> { + pub fn spi194(&mut self) -> SPI194_W { SPI194_W::new(self) } #[doc = "Bit 3 - Shared interrupt 195"] #[inline(always)] #[must_use] - pub fn spi195(&mut self) -> SPI195_W<3> { + pub fn spi195(&mut self) -> SPI195_W { SPI195_W::new(self) } #[doc = "Bit 4 - Shared interrupt 196"] #[inline(always)] #[must_use] - pub fn spi196(&mut self) -> SPI196_W<4> { + pub fn spi196(&mut self) -> SPI196_W { SPI196_W::new(self) } #[doc = "Bit 5 - Shared interrupt 197"] #[inline(always)] #[must_use] - pub fn spi197(&mut self) -> SPI197_W<5> { + pub fn spi197(&mut self) -> SPI197_W { SPI197_W::new(self) } #[doc = "Bit 6 - Shared interrupt 198"] #[inline(always)] #[must_use] - pub fn spi198(&mut self) -> SPI198_W<6> { + pub fn spi198(&mut self) -> SPI198_W { SPI198_W::new(self) } #[doc = "Bit 7 - Shared interrupt 199"] #[inline(always)] #[must_use] - pub fn spi199(&mut self) -> SPI199_W<7> { + pub fn spi199(&mut self) -> SPI199_W { SPI199_W::new(self) } #[doc = "Bit 8 - Shared interrupt 200"] #[inline(always)] #[must_use] - pub fn spi200(&mut self) -> SPI200_W<8> { + pub fn spi200(&mut self) -> SPI200_W { SPI200_W::new(self) } #[doc = "Bit 9 - Shared interrupt 201"] #[inline(always)] #[must_use] - pub fn spi201(&mut self) -> SPI201_W<9> { + pub fn spi201(&mut self) -> SPI201_W { SPI201_W::new(self) } #[doc = "Bit 10 - Shared interrupt 202"] #[inline(always)] #[must_use] - pub fn spi202(&mut self) -> SPI202_W<10> { + pub fn spi202(&mut self) -> SPI202_W { SPI202_W::new(self) } #[doc = "Bit 11 - Shared interrupt 203"] #[inline(always)] #[must_use] - pub fn spi203(&mut self) -> SPI203_W<11> { + pub fn spi203(&mut self) -> SPI203_W { SPI203_W::new(self) } #[doc = "Bit 12 - Shared interrupt 204"] #[inline(always)] #[must_use] - pub fn spi204(&mut self) -> SPI204_W<12> { + pub fn spi204(&mut self) -> SPI204_W { SPI204_W::new(self) } #[doc = "Bit 13 - Shared interrupt 205"] #[inline(always)] #[must_use] - pub fn spi205(&mut self) -> SPI205_W<13> { + pub fn spi205(&mut self) -> SPI205_W { SPI205_W::new(self) } #[doc = "Bit 14 - Shared interrupt 206"] #[inline(always)] #[must_use] - pub fn spi206(&mut self) -> SPI206_W<14> { + pub fn spi206(&mut self) -> SPI206_W { SPI206_W::new(self) } #[doc = "Bit 15 - Shared interrupt 207"] #[inline(always)] #[must_use] - pub fn spi207(&mut self) -> SPI207_W<15> { + pub fn spi207(&mut self) -> SPI207_W { SPI207_W::new(self) } #[doc = "Bit 16 - Shared interrupt 208"] #[inline(always)] #[must_use] - pub fn spi208(&mut self) -> SPI208_W<16> { + pub fn spi208(&mut self) -> SPI208_W { SPI208_W::new(self) } #[doc = "Bit 17 - Shared interrupt 209"] #[inline(always)] #[must_use] - pub fn spi209(&mut self) -> SPI209_W<17> { + pub fn spi209(&mut self) -> SPI209_W { SPI209_W::new(self) } #[doc = "Bit 18 - Shared interrupt 210"] #[inline(always)] #[must_use] - pub fn spi210(&mut self) -> SPI210_W<18> { + pub fn spi210(&mut self) -> SPI210_W { SPI210_W::new(self) } #[doc = "Bit 19 - Shared interrupt 211"] #[inline(always)] #[must_use] - pub fn spi211(&mut self) -> SPI211_W<19> { + pub fn spi211(&mut self) -> SPI211_W { SPI211_W::new(self) } #[doc = "Bit 20 - Shared interrupt 212"] #[inline(always)] #[must_use] - pub fn spi212(&mut self) -> SPI212_W<20> { + pub fn spi212(&mut self) -> SPI212_W { SPI212_W::new(self) } #[doc = "Bit 21 - Shared interrupt 213"] #[inline(always)] #[must_use] - pub fn spi213(&mut self) -> SPI213_W<21> { + pub fn spi213(&mut self) -> SPI213_W { SPI213_W::new(self) } #[doc = "Bit 22 - Shared interrupt 214"] #[inline(always)] #[must_use] - pub fn spi214(&mut self) -> SPI214_W<22> { + pub fn spi214(&mut self) -> SPI214_W { SPI214_W::new(self) } #[doc = "Bit 23 - Shared interrupt 215"] #[inline(always)] #[must_use] - pub fn spi215(&mut self) -> SPI215_W<23> { + pub fn spi215(&mut self) -> SPI215_W { SPI215_W::new(self) } #[doc = "Bit 24 - Shared interrupt 216"] #[inline(always)] #[must_use] - pub fn spi216(&mut self) -> SPI216_W<24> { + pub fn spi216(&mut self) -> SPI216_W { SPI216_W::new(self) } #[doc = "Bit 25 - Shared interrupt 217"] #[inline(always)] #[must_use] - pub fn spi217(&mut self) -> SPI217_W<25> { + pub fn spi217(&mut self) -> SPI217_W { SPI217_W::new(self) } #[doc = "Bit 26 - Shared interrupt 218"] #[inline(always)] #[must_use] - pub fn spi218(&mut self) -> SPI218_W<26> { + pub fn spi218(&mut self) -> SPI218_W { SPI218_W::new(self) } #[doc = "Bit 27 - Shared interrupt 219"] #[inline(always)] #[must_use] - pub fn spi219(&mut self) -> SPI219_W<27> { + pub fn spi219(&mut self) -> SPI219_W { SPI219_W::new(self) } #[doc = "Bit 28 - Shared interrupt 220"] #[inline(always)] #[must_use] - pub fn spi220(&mut self) -> SPI220_W<28> { + pub fn spi220(&mut self) -> SPI220_W { SPI220_W::new(self) } #[doc = "Bit 29 - Shared interrupt 221"] #[inline(always)] #[must_use] - pub fn spi221(&mut self) -> SPI221_W<29> { + pub fn spi221(&mut self) -> SPI221_W { SPI221_W::new(self) } #[doc = "Bit 30 - Shared interrupt 222"] #[inline(always)] #[must_use] - pub fn spi222(&mut self) -> SPI222_W<30> { + pub fn spi222(&mut self) -> SPI222_W { SPI222_W::new(self) } #[doc = "Bit 31 - Shared interrupt 223"] #[inline(always)] #[must_use] - pub fn spi223(&mut self) -> SPI223_W<31> { + pub fn spi223(&mut self) -> SPI223_W { SPI223_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Shared Peripheral Interrupt Status Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_spisr5](index.html) module"] +#[doc = "Shared Peripheral Interrupt Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_spisr5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gicd_spisr5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_SPISR5_SPEC; impl crate::RegisterSpec for GICD_SPISR5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_spisr5::R](R) reader structure"] -impl crate::Readable for GICD_SPISR5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gicd_spisr5::W](W) writer structure"] +#[doc = "`read()` method returns [`gicd_spisr5::R`](R) reader structure"] +impl crate::Readable for GICD_SPISR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gicd_spisr5::W`](W) writer structure"] impl crate::Writable for GICD_SPISR5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gic_dist/gicd_typer.rs b/crates/bcm2711-lpa/src/gic_dist/gicd_typer.rs index 6e6c6c3..ecbf265 100644 --- a/crates/bcm2711-lpa/src/gic_dist/gicd_typer.rs +++ b/crates/bcm2711-lpa/src/gic_dist/gicd_typer.rs @@ -1,26 +1,13 @@ #[doc = "Register `GICD_TYPER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `IT_LINES_NUMBER` reader - Interrupt line number"] -pub type IT_LINES_NUMBER_R = crate::FieldReader; +pub type IT_LINES_NUMBER_R = crate::FieldReader; #[doc = "Field `CPU_NUMBER` reader - CPU number"] -pub type CPU_NUMBER_R = crate::FieldReader; +pub type CPU_NUMBER_R = crate::FieldReader; #[doc = "Field `SECURITY_EXTENSION` reader - Security extension implemented"] -pub type SECURITY_EXTENSION_R = crate::BitReader; +pub type SECURITY_EXTENSION_R = crate::BitReader; #[doc = "Field `LSPI` reader - Lockable SPI count"] -pub type LSPI_R = crate::FieldReader; +pub type LSPI_R = crate::FieldReader; impl R { #[doc = "Bits 0:4 - Interrupt line number"] #[inline(always)] @@ -43,15 +30,34 @@ impl R { LSPI_R::new(((self.bits >> 11) & 0x0f) as u8) } } -#[doc = "Interrupt Controller Type Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gicd_typer](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GICD_TYPER") + .field( + "it_lines_number", + &format_args!("{}", self.it_lines_number().bits()), + ) + .field("cpu_number", &format_args!("{}", self.cpu_number().bits())) + .field( + "security_extension", + &format_args!("{}", self.security_extension().bit()), + ) + .field("lspi", &format_args!("{}", self.lspi().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Interrupt Controller Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gicd_typer::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GICD_TYPER_SPEC; impl crate::RegisterSpec for GICD_TYPER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gicd_typer::R](R) reader structure"] -impl crate::Readable for GICD_TYPER_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gicd_typer::R`](R) reader structure"] +impl crate::Readable for GICD_TYPER_SPEC {} #[doc = "`reset()` method sets GICD_TYPER to value 0"] impl crate::Resettable for GICD_TYPER_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/gpio.rs b/crates/bcm2711-lpa/src/gpio.rs index e643036..270dc41 100644 --- a/crates/bcm2711-lpa/src/gpio.rs +++ b/crates/bcm2711-lpa/src/gpio.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - GPIO Function Select 0"] pub gpfsel0: GPFSEL0, @@ -76,130 +77,161 @@ pub struct RegisterBlock { #[doc = "0xf0 - GPIO Pull-up / Pull-down Register 3"] pub gpio_pup_pdn_cntrl_reg3: GPIO_PUP_PDN_CNTRL_REG3, } -#[doc = "GPFSEL0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL0 (rw) register accessor: GPIO Function Select 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel0`] +module"] pub type GPFSEL0 = crate::Reg; #[doc = "GPIO Function Select 0"] pub mod gpfsel0; -#[doc = "GPFSEL1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL1 (rw) register accessor: GPIO Function Select 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel1`] +module"] pub type GPFSEL1 = crate::Reg; #[doc = "GPIO Function Select 1"] pub mod gpfsel1; -#[doc = "GPFSEL2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL2 (rw) register accessor: GPIO Function Select 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel2`] +module"] pub type GPFSEL2 = crate::Reg; #[doc = "GPIO Function Select 2"] pub mod gpfsel2; -#[doc = "GPFSEL3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL3 (rw) register accessor: GPIO Function Select 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel3`] +module"] pub type GPFSEL3 = crate::Reg; #[doc = "GPIO Function Select 3"] pub mod gpfsel3; -#[doc = "GPFSEL4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL4 (rw) register accessor: GPIO Function Select 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel4`] +module"] pub type GPFSEL4 = crate::Reg; #[doc = "GPIO Function Select 4"] pub mod gpfsel4; -#[doc = "GPFSEL5 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL5 (rw) register accessor: GPIO Function Select 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel5`] +module"] pub type GPFSEL5 = crate::Reg; #[doc = "GPIO Function Select 5"] pub mod gpfsel5; -#[doc = "GPSET0 (w) register accessor: an alias for `Reg`"] +#[doc = "GPSET0 (w) register accessor: GPIO Pin Output Set 0\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpset0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpset0`] +module"] pub type GPSET0 = crate::Reg; #[doc = "GPIO Pin Output Set 0"] pub mod gpset0; -#[doc = "GPSET1 (w) register accessor: an alias for `Reg`"] +#[doc = "GPSET1 (w) register accessor: GPIO Pin Output Set 1\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpset1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpset1`] +module"] pub type GPSET1 = crate::Reg; #[doc = "GPIO Pin Output Set 1"] pub mod gpset1; -#[doc = "GPCLR0 (w) register accessor: an alias for `Reg`"] +#[doc = "GPCLR0 (w) register accessor: GPIO Pin Output Clear 0\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpclr0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr0`] +module"] pub type GPCLR0 = crate::Reg; #[doc = "GPIO Pin Output Clear 0"] pub mod gpclr0; -#[doc = "GPCLR1 (w) register accessor: an alias for `Reg`"] +#[doc = "GPCLR1 (w) register accessor: GPIO Pin Output Clear 1\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpclr1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr1`] +module"] pub type GPCLR1 = crate::Reg; #[doc = "GPIO Pin Output Clear 1"] pub mod gpclr1; -#[doc = "GPLEV0 (r) register accessor: an alias for `Reg`"] +#[doc = "GPLEV0 (r) register accessor: GPIO Pin Level 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplev0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gplev0`] +module"] pub type GPLEV0 = crate::Reg; #[doc = "GPIO Pin Level 0"] pub mod gplev0; -#[doc = "GPLEV1 (r) register accessor: an alias for `Reg`"] +#[doc = "GPLEV1 (r) register accessor: GPIO Pin Level 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplev1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gplev1`] +module"] pub type GPLEV1 = crate::Reg; #[doc = "GPIO Pin Level 1"] pub mod gplev1; -#[doc = "GPEDS0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPEDS0 (rw) register accessor: GPIO Pin Event Detect Status 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpeds0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpeds0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpeds0`] +module"] pub type GPEDS0 = crate::Reg; #[doc = "GPIO Pin Event Detect Status 0"] pub mod gpeds0; -#[doc = "GPEDS1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPEDS1 (rw) register accessor: GPIO Pin Event Detect Status 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpeds1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpeds1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpeds1`] +module"] pub type GPEDS1 = crate::Reg; #[doc = "GPIO Pin Event Detect Status 1"] pub mod gpeds1; -#[doc = "GPREN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPREN0 (rw) register accessor: GPIO Pin Rising Edge Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpren0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpren0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpren0`] +module"] pub type GPREN0 = crate::Reg; #[doc = "GPIO Pin Rising Edge Detect Enable 0"] pub mod gpren0; -#[doc = "GPREN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPREN1 (rw) register accessor: GPIO Pin Rising Edge Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpren1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpren1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpren1`] +module"] pub type GPREN1 = crate::Reg; #[doc = "GPIO Pin Rising Edge Detect Enable 1"] pub mod gpren1; -#[doc = "GPFEN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFEN0 (rw) register accessor: GPIO Pin Falling Edge Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfen0`] +module"] pub type GPFEN0 = crate::Reg; #[doc = "GPIO Pin Falling Edge Detect Enable 0"] pub mod gpfen0; -#[doc = "GPFEN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFEN1 (rw) register accessor: GPIO Pin Falling Edge Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfen1`] +module"] pub type GPFEN1 = crate::Reg; #[doc = "GPIO Pin Falling Edge Detect Enable 1"] pub mod gpfen1; -#[doc = "GPHEN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPHEN0 (rw) register accessor: GPIO Pin High Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gphen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gphen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gphen0`] +module"] pub type GPHEN0 = crate::Reg; #[doc = "GPIO Pin High Detect Enable 0"] pub mod gphen0; -#[doc = "GPHEN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPHEN1 (rw) register accessor: GPIO Pin High Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gphen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gphen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gphen1`] +module"] pub type GPHEN1 = crate::Reg; #[doc = "GPIO Pin High Detect Enable 1"] pub mod gphen1; -#[doc = "GPLEN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPLEN0 (rw) register accessor: GPIO Pin Low Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gplen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gplen0`] +module"] pub type GPLEN0 = crate::Reg; #[doc = "GPIO Pin Low Detect Enable 0"] pub mod gplen0; -#[doc = "GPLEN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPLEN1 (rw) register accessor: GPIO Pin Low Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gplen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gplen1`] +module"] pub type GPLEN1 = crate::Reg; #[doc = "GPIO Pin Low Detect Enable 1"] pub mod gplen1; -#[doc = "GPAREN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPAREN0 (rw) register accessor: GPIO Pin Async. Rising Edge Detect 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gparen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gparen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gparen0`] +module"] pub type GPAREN0 = crate::Reg; #[doc = "GPIO Pin Async. Rising Edge Detect 0"] pub mod gparen0; -#[doc = "GPAREN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPAREN1 (rw) register accessor: GPIO Pin Async. Rising Edge Detect 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gparen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gparen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gparen1`] +module"] pub type GPAREN1 = crate::Reg; #[doc = "GPIO Pin Async. Rising Edge Detect 1"] pub mod gparen1; -#[doc = "GPAFEN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPAFEN0 (rw) register accessor: GPIO Pin Async. Falling Edge Detect 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpafen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpafen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpafen0`] +module"] pub type GPAFEN0 = crate::Reg; #[doc = "GPIO Pin Async. Falling Edge Detect 0"] pub mod gpafen0; -#[doc = "GPAFEN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPAFEN1 (rw) register accessor: GPIO Pin Async. Falling Edge Detect 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpafen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpafen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpafen1`] +module"] pub type GPAFEN1 = crate::Reg; #[doc = "GPIO Pin Async. Falling Edge Detect 1"] pub mod gpafen1; -#[doc = "EXTRA_MUX (rw) register accessor: an alias for `Reg`"] +#[doc = "EXTRA_MUX (rw) register accessor: Undocumented multiplexing bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extra_mux::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`extra_mux::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@extra_mux`] +module"] pub type EXTRA_MUX = crate::Reg; #[doc = "Undocumented multiplexing bits"] pub mod extra_mux; -#[doc = "GPIO_PUP_PDN_CNTRL_REG0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_PUP_PDN_CNTRL_REG0 (rw) register accessor: GPIO Pull-up / Pull-down Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pup_pdn_cntrl_reg0`] +module"] pub type GPIO_PUP_PDN_CNTRL_REG0 = crate::Reg; #[doc = "GPIO Pull-up / Pull-down Register 0"] pub mod gpio_pup_pdn_cntrl_reg0; -#[doc = "GPIO_PUP_PDN_CNTRL_REG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_PUP_PDN_CNTRL_REG1 (rw) register accessor: GPIO Pull-up / Pull-down Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pup_pdn_cntrl_reg1`] +module"] pub type GPIO_PUP_PDN_CNTRL_REG1 = crate::Reg; #[doc = "GPIO Pull-up / Pull-down Register 1"] pub mod gpio_pup_pdn_cntrl_reg1; -#[doc = "GPIO_PUP_PDN_CNTRL_REG2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_PUP_PDN_CNTRL_REG2 (rw) register accessor: GPIO Pull-up / Pull-down Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pup_pdn_cntrl_reg2`] +module"] pub type GPIO_PUP_PDN_CNTRL_REG2 = crate::Reg; #[doc = "GPIO Pull-up / Pull-down Register 2"] pub mod gpio_pup_pdn_cntrl_reg2; -#[doc = "GPIO_PUP_PDN_CNTRL_REG3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_PUP_PDN_CNTRL_REG3 (rw) register accessor: GPIO Pull-up / Pull-down Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pup_pdn_cntrl_reg3`] +module"] pub type GPIO_PUP_PDN_CNTRL_REG3 = crate::Reg; #[doc = "GPIO Pull-up / Pull-down Register 3"] diff --git a/crates/bcm2711-lpa/src/gpio/extra_mux.rs b/crates/bcm2711-lpa/src/gpio/extra_mux.rs index a35ba4f..bac06d5 100644 --- a/crates/bcm2711-lpa/src/gpio/extra_mux.rs +++ b/crates/bcm2711-lpa/src/gpio/extra_mux.rs @@ -1,39 +1,7 @@ #[doc = "Register `EXTRA_MUX` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EXTRA_MUX` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SDIO` reader - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] pub type SDIO_R = crate::BitReader; #[doc = "Switch peripheral connection to undocumented SDIO pins used on Pi 4"] @@ -53,34 +21,37 @@ impl From for bool { impl SDIO_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SDIO_A { + pub const fn variant(&self) -> SDIO_A { match self.bits { false => SDIO_A::SDHOST, true => SDIO_A::ARASAN, } } - #[doc = "Checks if the value of the field is `SDHOST`"] + #[doc = "Connect the newer SD host"] #[inline(always)] pub fn is_sdhost(&self) -> bool { *self == SDIO_A::SDHOST } - #[doc = "Checks if the value of the field is `ARASAN`"] + #[doc = "Connect Arasan SD/EMMC host"] #[inline(always)] pub fn is_arasan(&self) -> bool { *self == SDIO_A::ARASAN } } #[doc = "Field `SDIO` writer - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] -pub type SDIO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTRA_MUX_SPEC, SDIO_A, O>; -impl<'a, const O: u8> SDIO_W<'a, O> { +pub type SDIO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SDIO_A>; +impl<'a, REG, const O: u8> SDIO_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Connect the newer SD host"] #[inline(always)] - pub fn sdhost(self) -> &'a mut W { + pub fn sdhost(self) -> &'a mut crate::W { self.variant(SDIO_A::SDHOST) } #[doc = "Connect Arasan SD/EMMC host"] #[inline(always)] - pub fn arasan(self) -> &'a mut W { + pub fn arasan(self) -> &'a mut crate::W { self.variant(SDIO_A::ARASAN) } } @@ -91,32 +62,45 @@ impl R { SDIO_R::new(((self.bits >> 1) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXTRA_MUX") + .field("sdio", &format_args!("{}", self.sdio().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] #[inline(always)] #[must_use] - pub fn sdio(&mut self) -> SDIO_W<1> { + pub fn sdio(&mut self) -> SDIO_W { SDIO_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Undocumented multiplexing bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extra_mux](index.html) module"] +#[doc = "Undocumented multiplexing bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extra_mux::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`extra_mux::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EXTRA_MUX_SPEC; impl crate::RegisterSpec for EXTRA_MUX_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [extra_mux::R](R) reader structure"] -impl crate::Readable for EXTRA_MUX_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [extra_mux::W](W) writer structure"] +#[doc = "`read()` method returns [`extra_mux::R`](R) reader structure"] +impl crate::Readable for EXTRA_MUX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`extra_mux::W`](W) writer structure"] impl crate::Writable for EXTRA_MUX_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpafen0.rs b/crates/bcm2711-lpa/src/gpio/gpafen0.rs index 5c84fd8..44bf785 100644 --- a/crates/bcm2711-lpa/src/gpio/gpafen0.rs +++ b/crates/bcm2711-lpa/src/gpio/gpafen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPAFEN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPAFEN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AFEN0` reader - Async falling enabled 0"] -pub type AFEN0_R = crate::BitReader; +pub type AFEN0_R = crate::BitReader; #[doc = "Field `AFEN0` writer - Async falling enabled 0"] -pub type AFEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN1` reader - Async falling enabled 1"] -pub type AFEN1_R = crate::BitReader; +pub type AFEN1_R = crate::BitReader; #[doc = "Field `AFEN1` writer - Async falling enabled 1"] -pub type AFEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN2` reader - Async falling enabled 2"] -pub type AFEN2_R = crate::BitReader; +pub type AFEN2_R = crate::BitReader; #[doc = "Field `AFEN2` writer - Async falling enabled 2"] -pub type AFEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN3` reader - Async falling enabled 3"] -pub type AFEN3_R = crate::BitReader; +pub type AFEN3_R = crate::BitReader; #[doc = "Field `AFEN3` writer - Async falling enabled 3"] -pub type AFEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN4` reader - Async falling enabled 4"] -pub type AFEN4_R = crate::BitReader; +pub type AFEN4_R = crate::BitReader; #[doc = "Field `AFEN4` writer - Async falling enabled 4"] -pub type AFEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN5` reader - Async falling enabled 5"] -pub type AFEN5_R = crate::BitReader; +pub type AFEN5_R = crate::BitReader; #[doc = "Field `AFEN5` writer - Async falling enabled 5"] -pub type AFEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN6` reader - Async falling enabled 6"] -pub type AFEN6_R = crate::BitReader; +pub type AFEN6_R = crate::BitReader; #[doc = "Field `AFEN6` writer - Async falling enabled 6"] -pub type AFEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN7` reader - Async falling enabled 7"] -pub type AFEN7_R = crate::BitReader; +pub type AFEN7_R = crate::BitReader; #[doc = "Field `AFEN7` writer - Async falling enabled 7"] -pub type AFEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN8` reader - Async falling enabled 8"] -pub type AFEN8_R = crate::BitReader; +pub type AFEN8_R = crate::BitReader; #[doc = "Field `AFEN8` writer - Async falling enabled 8"] -pub type AFEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN9` reader - Async falling enabled 9"] -pub type AFEN9_R = crate::BitReader; +pub type AFEN9_R = crate::BitReader; #[doc = "Field `AFEN9` writer - Async falling enabled 9"] -pub type AFEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN10` reader - Async falling enabled 10"] -pub type AFEN10_R = crate::BitReader; +pub type AFEN10_R = crate::BitReader; #[doc = "Field `AFEN10` writer - Async falling enabled 10"] -pub type AFEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN11` reader - Async falling enabled 11"] -pub type AFEN11_R = crate::BitReader; +pub type AFEN11_R = crate::BitReader; #[doc = "Field `AFEN11` writer - Async falling enabled 11"] -pub type AFEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN12` reader - Async falling enabled 12"] -pub type AFEN12_R = crate::BitReader; +pub type AFEN12_R = crate::BitReader; #[doc = "Field `AFEN12` writer - Async falling enabled 12"] -pub type AFEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN13` reader - Async falling enabled 13"] -pub type AFEN13_R = crate::BitReader; +pub type AFEN13_R = crate::BitReader; #[doc = "Field `AFEN13` writer - Async falling enabled 13"] -pub type AFEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN14` reader - Async falling enabled 14"] -pub type AFEN14_R = crate::BitReader; +pub type AFEN14_R = crate::BitReader; #[doc = "Field `AFEN14` writer - Async falling enabled 14"] -pub type AFEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN15` reader - Async falling enabled 15"] -pub type AFEN15_R = crate::BitReader; +pub type AFEN15_R = crate::BitReader; #[doc = "Field `AFEN15` writer - Async falling enabled 15"] -pub type AFEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN16` reader - Async falling enabled 16"] -pub type AFEN16_R = crate::BitReader; +pub type AFEN16_R = crate::BitReader; #[doc = "Field `AFEN16` writer - Async falling enabled 16"] -pub type AFEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN17` reader - Async falling enabled 17"] -pub type AFEN17_R = crate::BitReader; +pub type AFEN17_R = crate::BitReader; #[doc = "Field `AFEN17` writer - Async falling enabled 17"] -pub type AFEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN18` reader - Async falling enabled 18"] -pub type AFEN18_R = crate::BitReader; +pub type AFEN18_R = crate::BitReader; #[doc = "Field `AFEN18` writer - Async falling enabled 18"] -pub type AFEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN19` reader - Async falling enabled 19"] -pub type AFEN19_R = crate::BitReader; +pub type AFEN19_R = crate::BitReader; #[doc = "Field `AFEN19` writer - Async falling enabled 19"] -pub type AFEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN20` reader - Async falling enabled 20"] -pub type AFEN20_R = crate::BitReader; +pub type AFEN20_R = crate::BitReader; #[doc = "Field `AFEN20` writer - Async falling enabled 20"] -pub type AFEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN21` reader - Async falling enabled 21"] -pub type AFEN21_R = crate::BitReader; +pub type AFEN21_R = crate::BitReader; #[doc = "Field `AFEN21` writer - Async falling enabled 21"] -pub type AFEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN22` reader - Async falling enabled 22"] -pub type AFEN22_R = crate::BitReader; +pub type AFEN22_R = crate::BitReader; #[doc = "Field `AFEN22` writer - Async falling enabled 22"] -pub type AFEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN23` reader - Async falling enabled 23"] -pub type AFEN23_R = crate::BitReader; +pub type AFEN23_R = crate::BitReader; #[doc = "Field `AFEN23` writer - Async falling enabled 23"] -pub type AFEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN24` reader - Async falling enabled 24"] -pub type AFEN24_R = crate::BitReader; +pub type AFEN24_R = crate::BitReader; #[doc = "Field `AFEN24` writer - Async falling enabled 24"] -pub type AFEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN25` reader - Async falling enabled 25"] -pub type AFEN25_R = crate::BitReader; +pub type AFEN25_R = crate::BitReader; #[doc = "Field `AFEN25` writer - Async falling enabled 25"] -pub type AFEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN26` reader - Async falling enabled 26"] -pub type AFEN26_R = crate::BitReader; +pub type AFEN26_R = crate::BitReader; #[doc = "Field `AFEN26` writer - Async falling enabled 26"] -pub type AFEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN27` reader - Async falling enabled 27"] -pub type AFEN27_R = crate::BitReader; +pub type AFEN27_R = crate::BitReader; #[doc = "Field `AFEN27` writer - Async falling enabled 27"] -pub type AFEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN28` reader - Async falling enabled 28"] -pub type AFEN28_R = crate::BitReader; +pub type AFEN28_R = crate::BitReader; #[doc = "Field `AFEN28` writer - Async falling enabled 28"] -pub type AFEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN29` reader - Async falling enabled 29"] -pub type AFEN29_R = crate::BitReader; +pub type AFEN29_R = crate::BitReader; #[doc = "Field `AFEN29` writer - Async falling enabled 29"] -pub type AFEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN30` reader - Async falling enabled 30"] -pub type AFEN30_R = crate::BitReader; +pub type AFEN30_R = crate::BitReader; #[doc = "Field `AFEN30` writer - Async falling enabled 30"] -pub type AFEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN31` reader - Async falling enabled 31"] -pub type AFEN31_R = crate::BitReader; +pub type AFEN31_R = crate::BitReader; #[doc = "Field `AFEN31` writer - Async falling enabled 31"] -pub type AFEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Async falling enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { AFEN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPAFEN0") + .field("afen0", &format_args!("{}", self.afen0().bit())) + .field("afen1", &format_args!("{}", self.afen1().bit())) + .field("afen2", &format_args!("{}", self.afen2().bit())) + .field("afen3", &format_args!("{}", self.afen3().bit())) + .field("afen4", &format_args!("{}", self.afen4().bit())) + .field("afen5", &format_args!("{}", self.afen5().bit())) + .field("afen6", &format_args!("{}", self.afen6().bit())) + .field("afen7", &format_args!("{}", self.afen7().bit())) + .field("afen8", &format_args!("{}", self.afen8().bit())) + .field("afen9", &format_args!("{}", self.afen9().bit())) + .field("afen10", &format_args!("{}", self.afen10().bit())) + .field("afen11", &format_args!("{}", self.afen11().bit())) + .field("afen12", &format_args!("{}", self.afen12().bit())) + .field("afen13", &format_args!("{}", self.afen13().bit())) + .field("afen14", &format_args!("{}", self.afen14().bit())) + .field("afen15", &format_args!("{}", self.afen15().bit())) + .field("afen16", &format_args!("{}", self.afen16().bit())) + .field("afen17", &format_args!("{}", self.afen17().bit())) + .field("afen18", &format_args!("{}", self.afen18().bit())) + .field("afen19", &format_args!("{}", self.afen19().bit())) + .field("afen20", &format_args!("{}", self.afen20().bit())) + .field("afen21", &format_args!("{}", self.afen21().bit())) + .field("afen22", &format_args!("{}", self.afen22().bit())) + .field("afen23", &format_args!("{}", self.afen23().bit())) + .field("afen24", &format_args!("{}", self.afen24().bit())) + .field("afen25", &format_args!("{}", self.afen25().bit())) + .field("afen26", &format_args!("{}", self.afen26().bit())) + .field("afen27", &format_args!("{}", self.afen27().bit())) + .field("afen28", &format_args!("{}", self.afen28().bit())) + .field("afen29", &format_args!("{}", self.afen29().bit())) + .field("afen30", &format_args!("{}", self.afen30().bit())) + .field("afen31", &format_args!("{}", self.afen31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Async falling enabled 0"] #[inline(always)] #[must_use] - pub fn afen0(&mut self) -> AFEN0_W<0> { + pub fn afen0(&mut self) -> AFEN0_W { AFEN0_W::new(self) } #[doc = "Bit 1 - Async falling enabled 1"] #[inline(always)] #[must_use] - pub fn afen1(&mut self) -> AFEN1_W<1> { + pub fn afen1(&mut self) -> AFEN1_W { AFEN1_W::new(self) } #[doc = "Bit 2 - Async falling enabled 2"] #[inline(always)] #[must_use] - pub fn afen2(&mut self) -> AFEN2_W<2> { + pub fn afen2(&mut self) -> AFEN2_W { AFEN2_W::new(self) } #[doc = "Bit 3 - Async falling enabled 3"] #[inline(always)] #[must_use] - pub fn afen3(&mut self) -> AFEN3_W<3> { + pub fn afen3(&mut self) -> AFEN3_W { AFEN3_W::new(self) } #[doc = "Bit 4 - Async falling enabled 4"] #[inline(always)] #[must_use] - pub fn afen4(&mut self) -> AFEN4_W<4> { + pub fn afen4(&mut self) -> AFEN4_W { AFEN4_W::new(self) } #[doc = "Bit 5 - Async falling enabled 5"] #[inline(always)] #[must_use] - pub fn afen5(&mut self) -> AFEN5_W<5> { + pub fn afen5(&mut self) -> AFEN5_W { AFEN5_W::new(self) } #[doc = "Bit 6 - Async falling enabled 6"] #[inline(always)] #[must_use] - pub fn afen6(&mut self) -> AFEN6_W<6> { + pub fn afen6(&mut self) -> AFEN6_W { AFEN6_W::new(self) } #[doc = "Bit 7 - Async falling enabled 7"] #[inline(always)] #[must_use] - pub fn afen7(&mut self) -> AFEN7_W<7> { + pub fn afen7(&mut self) -> AFEN7_W { AFEN7_W::new(self) } #[doc = "Bit 8 - Async falling enabled 8"] #[inline(always)] #[must_use] - pub fn afen8(&mut self) -> AFEN8_W<8> { + pub fn afen8(&mut self) -> AFEN8_W { AFEN8_W::new(self) } #[doc = "Bit 9 - Async falling enabled 9"] #[inline(always)] #[must_use] - pub fn afen9(&mut self) -> AFEN9_W<9> { + pub fn afen9(&mut self) -> AFEN9_W { AFEN9_W::new(self) } #[doc = "Bit 10 - Async falling enabled 10"] #[inline(always)] #[must_use] - pub fn afen10(&mut self) -> AFEN10_W<10> { + pub fn afen10(&mut self) -> AFEN10_W { AFEN10_W::new(self) } #[doc = "Bit 11 - Async falling enabled 11"] #[inline(always)] #[must_use] - pub fn afen11(&mut self) -> AFEN11_W<11> { + pub fn afen11(&mut self) -> AFEN11_W { AFEN11_W::new(self) } #[doc = "Bit 12 - Async falling enabled 12"] #[inline(always)] #[must_use] - pub fn afen12(&mut self) -> AFEN12_W<12> { + pub fn afen12(&mut self) -> AFEN12_W { AFEN12_W::new(self) } #[doc = "Bit 13 - Async falling enabled 13"] #[inline(always)] #[must_use] - pub fn afen13(&mut self) -> AFEN13_W<13> { + pub fn afen13(&mut self) -> AFEN13_W { AFEN13_W::new(self) } #[doc = "Bit 14 - Async falling enabled 14"] #[inline(always)] #[must_use] - pub fn afen14(&mut self) -> AFEN14_W<14> { + pub fn afen14(&mut self) -> AFEN14_W { AFEN14_W::new(self) } #[doc = "Bit 15 - Async falling enabled 15"] #[inline(always)] #[must_use] - pub fn afen15(&mut self) -> AFEN15_W<15> { + pub fn afen15(&mut self) -> AFEN15_W { AFEN15_W::new(self) } #[doc = "Bit 16 - Async falling enabled 16"] #[inline(always)] #[must_use] - pub fn afen16(&mut self) -> AFEN16_W<16> { + pub fn afen16(&mut self) -> AFEN16_W { AFEN16_W::new(self) } #[doc = "Bit 17 - Async falling enabled 17"] #[inline(always)] #[must_use] - pub fn afen17(&mut self) -> AFEN17_W<17> { + pub fn afen17(&mut self) -> AFEN17_W { AFEN17_W::new(self) } #[doc = "Bit 18 - Async falling enabled 18"] #[inline(always)] #[must_use] - pub fn afen18(&mut self) -> AFEN18_W<18> { + pub fn afen18(&mut self) -> AFEN18_W { AFEN18_W::new(self) } #[doc = "Bit 19 - Async falling enabled 19"] #[inline(always)] #[must_use] - pub fn afen19(&mut self) -> AFEN19_W<19> { + pub fn afen19(&mut self) -> AFEN19_W { AFEN19_W::new(self) } #[doc = "Bit 20 - Async falling enabled 20"] #[inline(always)] #[must_use] - pub fn afen20(&mut self) -> AFEN20_W<20> { + pub fn afen20(&mut self) -> AFEN20_W { AFEN20_W::new(self) } #[doc = "Bit 21 - Async falling enabled 21"] #[inline(always)] #[must_use] - pub fn afen21(&mut self) -> AFEN21_W<21> { + pub fn afen21(&mut self) -> AFEN21_W { AFEN21_W::new(self) } #[doc = "Bit 22 - Async falling enabled 22"] #[inline(always)] #[must_use] - pub fn afen22(&mut self) -> AFEN22_W<22> { + pub fn afen22(&mut self) -> AFEN22_W { AFEN22_W::new(self) } #[doc = "Bit 23 - Async falling enabled 23"] #[inline(always)] #[must_use] - pub fn afen23(&mut self) -> AFEN23_W<23> { + pub fn afen23(&mut self) -> AFEN23_W { AFEN23_W::new(self) } #[doc = "Bit 24 - Async falling enabled 24"] #[inline(always)] #[must_use] - pub fn afen24(&mut self) -> AFEN24_W<24> { + pub fn afen24(&mut self) -> AFEN24_W { AFEN24_W::new(self) } #[doc = "Bit 25 - Async falling enabled 25"] #[inline(always)] #[must_use] - pub fn afen25(&mut self) -> AFEN25_W<25> { + pub fn afen25(&mut self) -> AFEN25_W { AFEN25_W::new(self) } #[doc = "Bit 26 - Async falling enabled 26"] #[inline(always)] #[must_use] - pub fn afen26(&mut self) -> AFEN26_W<26> { + pub fn afen26(&mut self) -> AFEN26_W { AFEN26_W::new(self) } #[doc = "Bit 27 - Async falling enabled 27"] #[inline(always)] #[must_use] - pub fn afen27(&mut self) -> AFEN27_W<27> { + pub fn afen27(&mut self) -> AFEN27_W { AFEN27_W::new(self) } #[doc = "Bit 28 - Async falling enabled 28"] #[inline(always)] #[must_use] - pub fn afen28(&mut self) -> AFEN28_W<28> { + pub fn afen28(&mut self) -> AFEN28_W { AFEN28_W::new(self) } #[doc = "Bit 29 - Async falling enabled 29"] #[inline(always)] #[must_use] - pub fn afen29(&mut self) -> AFEN29_W<29> { + pub fn afen29(&mut self) -> AFEN29_W { AFEN29_W::new(self) } #[doc = "Bit 30 - Async falling enabled 30"] #[inline(always)] #[must_use] - pub fn afen30(&mut self) -> AFEN30_W<30> { + pub fn afen30(&mut self) -> AFEN30_W { AFEN30_W::new(self) } #[doc = "Bit 31 - Async falling enabled 31"] #[inline(always)] #[must_use] - pub fn afen31(&mut self) -> AFEN31_W<31> { + pub fn afen31(&mut self) -> AFEN31_W { AFEN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Async. Falling Edge Detect 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpafen0](index.html) module"] +#[doc = "GPIO Pin Async. Falling Edge Detect 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpafen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpafen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPAFEN0_SPEC; impl crate::RegisterSpec for GPAFEN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpafen0::R](R) reader structure"] -impl crate::Readable for GPAFEN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpafen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpafen0::R`](R) reader structure"] +impl crate::Readable for GPAFEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpafen0::W`](W) writer structure"] impl crate::Writable for GPAFEN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpafen1.rs b/crates/bcm2711-lpa/src/gpio/gpafen1.rs index 68f50fe..5c3b732 100644 --- a/crates/bcm2711-lpa/src/gpio/gpafen1.rs +++ b/crates/bcm2711-lpa/src/gpio/gpafen1.rs @@ -1,143 +1,111 @@ #[doc = "Register `GPAFEN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPAFEN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AFEN32` reader - Async falling enabled 32"] -pub type AFEN32_R = crate::BitReader; +pub type AFEN32_R = crate::BitReader; #[doc = "Field `AFEN32` writer - Async falling enabled 32"] -pub type AFEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN33` reader - Async falling enabled 33"] -pub type AFEN33_R = crate::BitReader; +pub type AFEN33_R = crate::BitReader; #[doc = "Field `AFEN33` writer - Async falling enabled 33"] -pub type AFEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN34` reader - Async falling enabled 34"] -pub type AFEN34_R = crate::BitReader; +pub type AFEN34_R = crate::BitReader; #[doc = "Field `AFEN34` writer - Async falling enabled 34"] -pub type AFEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN35` reader - Async falling enabled 35"] -pub type AFEN35_R = crate::BitReader; +pub type AFEN35_R = crate::BitReader; #[doc = "Field `AFEN35` writer - Async falling enabled 35"] -pub type AFEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN36` reader - Async falling enabled 36"] -pub type AFEN36_R = crate::BitReader; +pub type AFEN36_R = crate::BitReader; #[doc = "Field `AFEN36` writer - Async falling enabled 36"] -pub type AFEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN37` reader - Async falling enabled 37"] -pub type AFEN37_R = crate::BitReader; +pub type AFEN37_R = crate::BitReader; #[doc = "Field `AFEN37` writer - Async falling enabled 37"] -pub type AFEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN38` reader - Async falling enabled 38"] -pub type AFEN38_R = crate::BitReader; +pub type AFEN38_R = crate::BitReader; #[doc = "Field `AFEN38` writer - Async falling enabled 38"] -pub type AFEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN39` reader - Async falling enabled 39"] -pub type AFEN39_R = crate::BitReader; +pub type AFEN39_R = crate::BitReader; #[doc = "Field `AFEN39` writer - Async falling enabled 39"] -pub type AFEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN40` reader - Async falling enabled 40"] -pub type AFEN40_R = crate::BitReader; +pub type AFEN40_R = crate::BitReader; #[doc = "Field `AFEN40` writer - Async falling enabled 40"] -pub type AFEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN41` reader - Async falling enabled 41"] -pub type AFEN41_R = crate::BitReader; +pub type AFEN41_R = crate::BitReader; #[doc = "Field `AFEN41` writer - Async falling enabled 41"] -pub type AFEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN42` reader - Async falling enabled 42"] -pub type AFEN42_R = crate::BitReader; +pub type AFEN42_R = crate::BitReader; #[doc = "Field `AFEN42` writer - Async falling enabled 42"] -pub type AFEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN43` reader - Async falling enabled 43"] -pub type AFEN43_R = crate::BitReader; +pub type AFEN43_R = crate::BitReader; #[doc = "Field `AFEN43` writer - Async falling enabled 43"] -pub type AFEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN44` reader - Async falling enabled 44"] -pub type AFEN44_R = crate::BitReader; +pub type AFEN44_R = crate::BitReader; #[doc = "Field `AFEN44` writer - Async falling enabled 44"] -pub type AFEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN45` reader - Async falling enabled 45"] -pub type AFEN45_R = crate::BitReader; +pub type AFEN45_R = crate::BitReader; #[doc = "Field `AFEN45` writer - Async falling enabled 45"] -pub type AFEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN46` reader - Async falling enabled 46"] -pub type AFEN46_R = crate::BitReader; +pub type AFEN46_R = crate::BitReader; #[doc = "Field `AFEN46` writer - Async falling enabled 46"] -pub type AFEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN47` reader - Async falling enabled 47"] -pub type AFEN47_R = crate::BitReader; +pub type AFEN47_R = crate::BitReader; #[doc = "Field `AFEN47` writer - Async falling enabled 47"] -pub type AFEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN48` reader - Async falling enabled 48"] -pub type AFEN48_R = crate::BitReader; +pub type AFEN48_R = crate::BitReader; #[doc = "Field `AFEN48` writer - Async falling enabled 48"] -pub type AFEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN49` reader - Async falling enabled 49"] -pub type AFEN49_R = crate::BitReader; +pub type AFEN49_R = crate::BitReader; #[doc = "Field `AFEN49` writer - Async falling enabled 49"] -pub type AFEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN50` reader - Async falling enabled 50"] -pub type AFEN50_R = crate::BitReader; +pub type AFEN50_R = crate::BitReader; #[doc = "Field `AFEN50` writer - Async falling enabled 50"] -pub type AFEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN51` reader - Async falling enabled 51"] -pub type AFEN51_R = crate::BitReader; +pub type AFEN51_R = crate::BitReader; #[doc = "Field `AFEN51` writer - Async falling enabled 51"] -pub type AFEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN52` reader - Async falling enabled 52"] -pub type AFEN52_R = crate::BitReader; +pub type AFEN52_R = crate::BitReader; #[doc = "Field `AFEN52` writer - Async falling enabled 52"] -pub type AFEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN53` reader - Async falling enabled 53"] -pub type AFEN53_R = crate::BitReader; +pub type AFEN53_R = crate::BitReader; #[doc = "Field `AFEN53` writer - Async falling enabled 53"] -pub type AFEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN54` reader - Async falling enabled 54"] -pub type AFEN54_R = crate::BitReader; +pub type AFEN54_R = crate::BitReader; #[doc = "Field `AFEN54` writer - Async falling enabled 54"] -pub type AFEN54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN54_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN55` reader - Async falling enabled 55"] -pub type AFEN55_R = crate::BitReader; +pub type AFEN55_R = crate::BitReader; #[doc = "Field `AFEN55` writer - Async falling enabled 55"] -pub type AFEN55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN55_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN56` reader - Async falling enabled 56"] -pub type AFEN56_R = crate::BitReader; +pub type AFEN56_R = crate::BitReader; #[doc = "Field `AFEN56` writer - Async falling enabled 56"] -pub type AFEN56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN57` reader - Async falling enabled 57"] -pub type AFEN57_R = crate::BitReader; +pub type AFEN57_R = crate::BitReader; #[doc = "Field `AFEN57` writer - Async falling enabled 57"] -pub type AFEN57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Async falling enabled 32"] #[inline(always)] @@ -270,182 +238,220 @@ impl R { AFEN57_R::new(((self.bits >> 25) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPAFEN1") + .field("afen32", &format_args!("{}", self.afen32().bit())) + .field("afen33", &format_args!("{}", self.afen33().bit())) + .field("afen34", &format_args!("{}", self.afen34().bit())) + .field("afen35", &format_args!("{}", self.afen35().bit())) + .field("afen36", &format_args!("{}", self.afen36().bit())) + .field("afen37", &format_args!("{}", self.afen37().bit())) + .field("afen38", &format_args!("{}", self.afen38().bit())) + .field("afen39", &format_args!("{}", self.afen39().bit())) + .field("afen40", &format_args!("{}", self.afen40().bit())) + .field("afen41", &format_args!("{}", self.afen41().bit())) + .field("afen42", &format_args!("{}", self.afen42().bit())) + .field("afen43", &format_args!("{}", self.afen43().bit())) + .field("afen44", &format_args!("{}", self.afen44().bit())) + .field("afen45", &format_args!("{}", self.afen45().bit())) + .field("afen46", &format_args!("{}", self.afen46().bit())) + .field("afen47", &format_args!("{}", self.afen47().bit())) + .field("afen48", &format_args!("{}", self.afen48().bit())) + .field("afen49", &format_args!("{}", self.afen49().bit())) + .field("afen50", &format_args!("{}", self.afen50().bit())) + .field("afen51", &format_args!("{}", self.afen51().bit())) + .field("afen52", &format_args!("{}", self.afen52().bit())) + .field("afen53", &format_args!("{}", self.afen53().bit())) + .field("afen54", &format_args!("{}", self.afen54().bit())) + .field("afen55", &format_args!("{}", self.afen55().bit())) + .field("afen56", &format_args!("{}", self.afen56().bit())) + .field("afen57", &format_args!("{}", self.afen57().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Async falling enabled 32"] #[inline(always)] #[must_use] - pub fn afen32(&mut self) -> AFEN32_W<0> { + pub fn afen32(&mut self) -> AFEN32_W { AFEN32_W::new(self) } #[doc = "Bit 1 - Async falling enabled 33"] #[inline(always)] #[must_use] - pub fn afen33(&mut self) -> AFEN33_W<1> { + pub fn afen33(&mut self) -> AFEN33_W { AFEN33_W::new(self) } #[doc = "Bit 2 - Async falling enabled 34"] #[inline(always)] #[must_use] - pub fn afen34(&mut self) -> AFEN34_W<2> { + pub fn afen34(&mut self) -> AFEN34_W { AFEN34_W::new(self) } #[doc = "Bit 3 - Async falling enabled 35"] #[inline(always)] #[must_use] - pub fn afen35(&mut self) -> AFEN35_W<3> { + pub fn afen35(&mut self) -> AFEN35_W { AFEN35_W::new(self) } #[doc = "Bit 4 - Async falling enabled 36"] #[inline(always)] #[must_use] - pub fn afen36(&mut self) -> AFEN36_W<4> { + pub fn afen36(&mut self) -> AFEN36_W { AFEN36_W::new(self) } #[doc = "Bit 5 - Async falling enabled 37"] #[inline(always)] #[must_use] - pub fn afen37(&mut self) -> AFEN37_W<5> { + pub fn afen37(&mut self) -> AFEN37_W { AFEN37_W::new(self) } #[doc = "Bit 6 - Async falling enabled 38"] #[inline(always)] #[must_use] - pub fn afen38(&mut self) -> AFEN38_W<6> { + pub fn afen38(&mut self) -> AFEN38_W { AFEN38_W::new(self) } #[doc = "Bit 7 - Async falling enabled 39"] #[inline(always)] #[must_use] - pub fn afen39(&mut self) -> AFEN39_W<7> { + pub fn afen39(&mut self) -> AFEN39_W { AFEN39_W::new(self) } #[doc = "Bit 8 - Async falling enabled 40"] #[inline(always)] #[must_use] - pub fn afen40(&mut self) -> AFEN40_W<8> { + pub fn afen40(&mut self) -> AFEN40_W { AFEN40_W::new(self) } #[doc = "Bit 9 - Async falling enabled 41"] #[inline(always)] #[must_use] - pub fn afen41(&mut self) -> AFEN41_W<9> { + pub fn afen41(&mut self) -> AFEN41_W { AFEN41_W::new(self) } #[doc = "Bit 10 - Async falling enabled 42"] #[inline(always)] #[must_use] - pub fn afen42(&mut self) -> AFEN42_W<10> { + pub fn afen42(&mut self) -> AFEN42_W { AFEN42_W::new(self) } #[doc = "Bit 11 - Async falling enabled 43"] #[inline(always)] #[must_use] - pub fn afen43(&mut self) -> AFEN43_W<11> { + pub fn afen43(&mut self) -> AFEN43_W { AFEN43_W::new(self) } #[doc = "Bit 12 - Async falling enabled 44"] #[inline(always)] #[must_use] - pub fn afen44(&mut self) -> AFEN44_W<12> { + pub fn afen44(&mut self) -> AFEN44_W { AFEN44_W::new(self) } #[doc = "Bit 13 - Async falling enabled 45"] #[inline(always)] #[must_use] - pub fn afen45(&mut self) -> AFEN45_W<13> { + pub fn afen45(&mut self) -> AFEN45_W { AFEN45_W::new(self) } #[doc = "Bit 14 - Async falling enabled 46"] #[inline(always)] #[must_use] - pub fn afen46(&mut self) -> AFEN46_W<14> { + pub fn afen46(&mut self) -> AFEN46_W { AFEN46_W::new(self) } #[doc = "Bit 15 - Async falling enabled 47"] #[inline(always)] #[must_use] - pub fn afen47(&mut self) -> AFEN47_W<15> { + pub fn afen47(&mut self) -> AFEN47_W { AFEN47_W::new(self) } #[doc = "Bit 16 - Async falling enabled 48"] #[inline(always)] #[must_use] - pub fn afen48(&mut self) -> AFEN48_W<16> { + pub fn afen48(&mut self) -> AFEN48_W { AFEN48_W::new(self) } #[doc = "Bit 17 - Async falling enabled 49"] #[inline(always)] #[must_use] - pub fn afen49(&mut self) -> AFEN49_W<17> { + pub fn afen49(&mut self) -> AFEN49_W { AFEN49_W::new(self) } #[doc = "Bit 18 - Async falling enabled 50"] #[inline(always)] #[must_use] - pub fn afen50(&mut self) -> AFEN50_W<18> { + pub fn afen50(&mut self) -> AFEN50_W { AFEN50_W::new(self) } #[doc = "Bit 19 - Async falling enabled 51"] #[inline(always)] #[must_use] - pub fn afen51(&mut self) -> AFEN51_W<19> { + pub fn afen51(&mut self) -> AFEN51_W { AFEN51_W::new(self) } #[doc = "Bit 20 - Async falling enabled 52"] #[inline(always)] #[must_use] - pub fn afen52(&mut self) -> AFEN52_W<20> { + pub fn afen52(&mut self) -> AFEN52_W { AFEN52_W::new(self) } #[doc = "Bit 21 - Async falling enabled 53"] #[inline(always)] #[must_use] - pub fn afen53(&mut self) -> AFEN53_W<21> { + pub fn afen53(&mut self) -> AFEN53_W { AFEN53_W::new(self) } #[doc = "Bit 22 - Async falling enabled 54"] #[inline(always)] #[must_use] - pub fn afen54(&mut self) -> AFEN54_W<22> { + pub fn afen54(&mut self) -> AFEN54_W { AFEN54_W::new(self) } #[doc = "Bit 23 - Async falling enabled 55"] #[inline(always)] #[must_use] - pub fn afen55(&mut self) -> AFEN55_W<23> { + pub fn afen55(&mut self) -> AFEN55_W { AFEN55_W::new(self) } #[doc = "Bit 24 - Async falling enabled 56"] #[inline(always)] #[must_use] - pub fn afen56(&mut self) -> AFEN56_W<24> { + pub fn afen56(&mut self) -> AFEN56_W { AFEN56_W::new(self) } #[doc = "Bit 25 - Async falling enabled 57"] #[inline(always)] #[must_use] - pub fn afen57(&mut self) -> AFEN57_W<25> { + pub fn afen57(&mut self) -> AFEN57_W { AFEN57_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Async. Falling Edge Detect 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpafen1](index.html) module"] +#[doc = "GPIO Pin Async. Falling Edge Detect 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpafen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpafen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPAFEN1_SPEC; impl crate::RegisterSpec for GPAFEN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpafen1::R](R) reader structure"] -impl crate::Readable for GPAFEN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpafen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpafen1::R`](R) reader structure"] +impl crate::Readable for GPAFEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpafen1::W`](W) writer structure"] impl crate::Writable for GPAFEN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gparen0.rs b/crates/bcm2711-lpa/src/gpio/gparen0.rs index f4ef746..ac719d0 100644 --- a/crates/bcm2711-lpa/src/gpio/gparen0.rs +++ b/crates/bcm2711-lpa/src/gpio/gparen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPAREN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPAREN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AREN0` reader - Async rising enabled 0"] -pub type AREN0_R = crate::BitReader; +pub type AREN0_R = crate::BitReader; #[doc = "Field `AREN0` writer - Async rising enabled 0"] -pub type AREN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN1` reader - Async rising enabled 1"] -pub type AREN1_R = crate::BitReader; +pub type AREN1_R = crate::BitReader; #[doc = "Field `AREN1` writer - Async rising enabled 1"] -pub type AREN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN2` reader - Async rising enabled 2"] -pub type AREN2_R = crate::BitReader; +pub type AREN2_R = crate::BitReader; #[doc = "Field `AREN2` writer - Async rising enabled 2"] -pub type AREN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN3` reader - Async rising enabled 3"] -pub type AREN3_R = crate::BitReader; +pub type AREN3_R = crate::BitReader; #[doc = "Field `AREN3` writer - Async rising enabled 3"] -pub type AREN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN4` reader - Async rising enabled 4"] -pub type AREN4_R = crate::BitReader; +pub type AREN4_R = crate::BitReader; #[doc = "Field `AREN4` writer - Async rising enabled 4"] -pub type AREN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN5` reader - Async rising enabled 5"] -pub type AREN5_R = crate::BitReader; +pub type AREN5_R = crate::BitReader; #[doc = "Field `AREN5` writer - Async rising enabled 5"] -pub type AREN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN6` reader - Async rising enabled 6"] -pub type AREN6_R = crate::BitReader; +pub type AREN6_R = crate::BitReader; #[doc = "Field `AREN6` writer - Async rising enabled 6"] -pub type AREN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN7` reader - Async rising enabled 7"] -pub type AREN7_R = crate::BitReader; +pub type AREN7_R = crate::BitReader; #[doc = "Field `AREN7` writer - Async rising enabled 7"] -pub type AREN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN8` reader - Async rising enabled 8"] -pub type AREN8_R = crate::BitReader; +pub type AREN8_R = crate::BitReader; #[doc = "Field `AREN8` writer - Async rising enabled 8"] -pub type AREN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN9` reader - Async rising enabled 9"] -pub type AREN9_R = crate::BitReader; +pub type AREN9_R = crate::BitReader; #[doc = "Field `AREN9` writer - Async rising enabled 9"] -pub type AREN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN10` reader - Async rising enabled 10"] -pub type AREN10_R = crate::BitReader; +pub type AREN10_R = crate::BitReader; #[doc = "Field `AREN10` writer - Async rising enabled 10"] -pub type AREN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN11` reader - Async rising enabled 11"] -pub type AREN11_R = crate::BitReader; +pub type AREN11_R = crate::BitReader; #[doc = "Field `AREN11` writer - Async rising enabled 11"] -pub type AREN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN12` reader - Async rising enabled 12"] -pub type AREN12_R = crate::BitReader; +pub type AREN12_R = crate::BitReader; #[doc = "Field `AREN12` writer - Async rising enabled 12"] -pub type AREN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN13` reader - Async rising enabled 13"] -pub type AREN13_R = crate::BitReader; +pub type AREN13_R = crate::BitReader; #[doc = "Field `AREN13` writer - Async rising enabled 13"] -pub type AREN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN14` reader - Async rising enabled 14"] -pub type AREN14_R = crate::BitReader; +pub type AREN14_R = crate::BitReader; #[doc = "Field `AREN14` writer - Async rising enabled 14"] -pub type AREN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN15` reader - Async rising enabled 15"] -pub type AREN15_R = crate::BitReader; +pub type AREN15_R = crate::BitReader; #[doc = "Field `AREN15` writer - Async rising enabled 15"] -pub type AREN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN16` reader - Async rising enabled 16"] -pub type AREN16_R = crate::BitReader; +pub type AREN16_R = crate::BitReader; #[doc = "Field `AREN16` writer - Async rising enabled 16"] -pub type AREN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN17` reader - Async rising enabled 17"] -pub type AREN17_R = crate::BitReader; +pub type AREN17_R = crate::BitReader; #[doc = "Field `AREN17` writer - Async rising enabled 17"] -pub type AREN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN18` reader - Async rising enabled 18"] -pub type AREN18_R = crate::BitReader; +pub type AREN18_R = crate::BitReader; #[doc = "Field `AREN18` writer - Async rising enabled 18"] -pub type AREN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN19` reader - Async rising enabled 19"] -pub type AREN19_R = crate::BitReader; +pub type AREN19_R = crate::BitReader; #[doc = "Field `AREN19` writer - Async rising enabled 19"] -pub type AREN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN20` reader - Async rising enabled 20"] -pub type AREN20_R = crate::BitReader; +pub type AREN20_R = crate::BitReader; #[doc = "Field `AREN20` writer - Async rising enabled 20"] -pub type AREN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN21` reader - Async rising enabled 21"] -pub type AREN21_R = crate::BitReader; +pub type AREN21_R = crate::BitReader; #[doc = "Field `AREN21` writer - Async rising enabled 21"] -pub type AREN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN22` reader - Async rising enabled 22"] -pub type AREN22_R = crate::BitReader; +pub type AREN22_R = crate::BitReader; #[doc = "Field `AREN22` writer - Async rising enabled 22"] -pub type AREN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN23` reader - Async rising enabled 23"] -pub type AREN23_R = crate::BitReader; +pub type AREN23_R = crate::BitReader; #[doc = "Field `AREN23` writer - Async rising enabled 23"] -pub type AREN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN24` reader - Async rising enabled 24"] -pub type AREN24_R = crate::BitReader; +pub type AREN24_R = crate::BitReader; #[doc = "Field `AREN24` writer - Async rising enabled 24"] -pub type AREN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN25` reader - Async rising enabled 25"] -pub type AREN25_R = crate::BitReader; +pub type AREN25_R = crate::BitReader; #[doc = "Field `AREN25` writer - Async rising enabled 25"] -pub type AREN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN26` reader - Async rising enabled 26"] -pub type AREN26_R = crate::BitReader; +pub type AREN26_R = crate::BitReader; #[doc = "Field `AREN26` writer - Async rising enabled 26"] -pub type AREN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN27` reader - Async rising enabled 27"] -pub type AREN27_R = crate::BitReader; +pub type AREN27_R = crate::BitReader; #[doc = "Field `AREN27` writer - Async rising enabled 27"] -pub type AREN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN28` reader - Async rising enabled 28"] -pub type AREN28_R = crate::BitReader; +pub type AREN28_R = crate::BitReader; #[doc = "Field `AREN28` writer - Async rising enabled 28"] -pub type AREN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN29` reader - Async rising enabled 29"] -pub type AREN29_R = crate::BitReader; +pub type AREN29_R = crate::BitReader; #[doc = "Field `AREN29` writer - Async rising enabled 29"] -pub type AREN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN30` reader - Async rising enabled 30"] -pub type AREN30_R = crate::BitReader; +pub type AREN30_R = crate::BitReader; #[doc = "Field `AREN30` writer - Async rising enabled 30"] -pub type AREN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN31` reader - Async rising enabled 31"] -pub type AREN31_R = crate::BitReader; +pub type AREN31_R = crate::BitReader; #[doc = "Field `AREN31` writer - Async rising enabled 31"] -pub type AREN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Async rising enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { AREN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPAREN0") + .field("aren0", &format_args!("{}", self.aren0().bit())) + .field("aren1", &format_args!("{}", self.aren1().bit())) + .field("aren2", &format_args!("{}", self.aren2().bit())) + .field("aren3", &format_args!("{}", self.aren3().bit())) + .field("aren4", &format_args!("{}", self.aren4().bit())) + .field("aren5", &format_args!("{}", self.aren5().bit())) + .field("aren6", &format_args!("{}", self.aren6().bit())) + .field("aren7", &format_args!("{}", self.aren7().bit())) + .field("aren8", &format_args!("{}", self.aren8().bit())) + .field("aren9", &format_args!("{}", self.aren9().bit())) + .field("aren10", &format_args!("{}", self.aren10().bit())) + .field("aren11", &format_args!("{}", self.aren11().bit())) + .field("aren12", &format_args!("{}", self.aren12().bit())) + .field("aren13", &format_args!("{}", self.aren13().bit())) + .field("aren14", &format_args!("{}", self.aren14().bit())) + .field("aren15", &format_args!("{}", self.aren15().bit())) + .field("aren16", &format_args!("{}", self.aren16().bit())) + .field("aren17", &format_args!("{}", self.aren17().bit())) + .field("aren18", &format_args!("{}", self.aren18().bit())) + .field("aren19", &format_args!("{}", self.aren19().bit())) + .field("aren20", &format_args!("{}", self.aren20().bit())) + .field("aren21", &format_args!("{}", self.aren21().bit())) + .field("aren22", &format_args!("{}", self.aren22().bit())) + .field("aren23", &format_args!("{}", self.aren23().bit())) + .field("aren24", &format_args!("{}", self.aren24().bit())) + .field("aren25", &format_args!("{}", self.aren25().bit())) + .field("aren26", &format_args!("{}", self.aren26().bit())) + .field("aren27", &format_args!("{}", self.aren27().bit())) + .field("aren28", &format_args!("{}", self.aren28().bit())) + .field("aren29", &format_args!("{}", self.aren29().bit())) + .field("aren30", &format_args!("{}", self.aren30().bit())) + .field("aren31", &format_args!("{}", self.aren31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Async rising enabled 0"] #[inline(always)] #[must_use] - pub fn aren0(&mut self) -> AREN0_W<0> { + pub fn aren0(&mut self) -> AREN0_W { AREN0_W::new(self) } #[doc = "Bit 1 - Async rising enabled 1"] #[inline(always)] #[must_use] - pub fn aren1(&mut self) -> AREN1_W<1> { + pub fn aren1(&mut self) -> AREN1_W { AREN1_W::new(self) } #[doc = "Bit 2 - Async rising enabled 2"] #[inline(always)] #[must_use] - pub fn aren2(&mut self) -> AREN2_W<2> { + pub fn aren2(&mut self) -> AREN2_W { AREN2_W::new(self) } #[doc = "Bit 3 - Async rising enabled 3"] #[inline(always)] #[must_use] - pub fn aren3(&mut self) -> AREN3_W<3> { + pub fn aren3(&mut self) -> AREN3_W { AREN3_W::new(self) } #[doc = "Bit 4 - Async rising enabled 4"] #[inline(always)] #[must_use] - pub fn aren4(&mut self) -> AREN4_W<4> { + pub fn aren4(&mut self) -> AREN4_W { AREN4_W::new(self) } #[doc = "Bit 5 - Async rising enabled 5"] #[inline(always)] #[must_use] - pub fn aren5(&mut self) -> AREN5_W<5> { + pub fn aren5(&mut self) -> AREN5_W { AREN5_W::new(self) } #[doc = "Bit 6 - Async rising enabled 6"] #[inline(always)] #[must_use] - pub fn aren6(&mut self) -> AREN6_W<6> { + pub fn aren6(&mut self) -> AREN6_W { AREN6_W::new(self) } #[doc = "Bit 7 - Async rising enabled 7"] #[inline(always)] #[must_use] - pub fn aren7(&mut self) -> AREN7_W<7> { + pub fn aren7(&mut self) -> AREN7_W { AREN7_W::new(self) } #[doc = "Bit 8 - Async rising enabled 8"] #[inline(always)] #[must_use] - pub fn aren8(&mut self) -> AREN8_W<8> { + pub fn aren8(&mut self) -> AREN8_W { AREN8_W::new(self) } #[doc = "Bit 9 - Async rising enabled 9"] #[inline(always)] #[must_use] - pub fn aren9(&mut self) -> AREN9_W<9> { + pub fn aren9(&mut self) -> AREN9_W { AREN9_W::new(self) } #[doc = "Bit 10 - Async rising enabled 10"] #[inline(always)] #[must_use] - pub fn aren10(&mut self) -> AREN10_W<10> { + pub fn aren10(&mut self) -> AREN10_W { AREN10_W::new(self) } #[doc = "Bit 11 - Async rising enabled 11"] #[inline(always)] #[must_use] - pub fn aren11(&mut self) -> AREN11_W<11> { + pub fn aren11(&mut self) -> AREN11_W { AREN11_W::new(self) } #[doc = "Bit 12 - Async rising enabled 12"] #[inline(always)] #[must_use] - pub fn aren12(&mut self) -> AREN12_W<12> { + pub fn aren12(&mut self) -> AREN12_W { AREN12_W::new(self) } #[doc = "Bit 13 - Async rising enabled 13"] #[inline(always)] #[must_use] - pub fn aren13(&mut self) -> AREN13_W<13> { + pub fn aren13(&mut self) -> AREN13_W { AREN13_W::new(self) } #[doc = "Bit 14 - Async rising enabled 14"] #[inline(always)] #[must_use] - pub fn aren14(&mut self) -> AREN14_W<14> { + pub fn aren14(&mut self) -> AREN14_W { AREN14_W::new(self) } #[doc = "Bit 15 - Async rising enabled 15"] #[inline(always)] #[must_use] - pub fn aren15(&mut self) -> AREN15_W<15> { + pub fn aren15(&mut self) -> AREN15_W { AREN15_W::new(self) } #[doc = "Bit 16 - Async rising enabled 16"] #[inline(always)] #[must_use] - pub fn aren16(&mut self) -> AREN16_W<16> { + pub fn aren16(&mut self) -> AREN16_W { AREN16_W::new(self) } #[doc = "Bit 17 - Async rising enabled 17"] #[inline(always)] #[must_use] - pub fn aren17(&mut self) -> AREN17_W<17> { + pub fn aren17(&mut self) -> AREN17_W { AREN17_W::new(self) } #[doc = "Bit 18 - Async rising enabled 18"] #[inline(always)] #[must_use] - pub fn aren18(&mut self) -> AREN18_W<18> { + pub fn aren18(&mut self) -> AREN18_W { AREN18_W::new(self) } #[doc = "Bit 19 - Async rising enabled 19"] #[inline(always)] #[must_use] - pub fn aren19(&mut self) -> AREN19_W<19> { + pub fn aren19(&mut self) -> AREN19_W { AREN19_W::new(self) } #[doc = "Bit 20 - Async rising enabled 20"] #[inline(always)] #[must_use] - pub fn aren20(&mut self) -> AREN20_W<20> { + pub fn aren20(&mut self) -> AREN20_W { AREN20_W::new(self) } #[doc = "Bit 21 - Async rising enabled 21"] #[inline(always)] #[must_use] - pub fn aren21(&mut self) -> AREN21_W<21> { + pub fn aren21(&mut self) -> AREN21_W { AREN21_W::new(self) } #[doc = "Bit 22 - Async rising enabled 22"] #[inline(always)] #[must_use] - pub fn aren22(&mut self) -> AREN22_W<22> { + pub fn aren22(&mut self) -> AREN22_W { AREN22_W::new(self) } #[doc = "Bit 23 - Async rising enabled 23"] #[inline(always)] #[must_use] - pub fn aren23(&mut self) -> AREN23_W<23> { + pub fn aren23(&mut self) -> AREN23_W { AREN23_W::new(self) } #[doc = "Bit 24 - Async rising enabled 24"] #[inline(always)] #[must_use] - pub fn aren24(&mut self) -> AREN24_W<24> { + pub fn aren24(&mut self) -> AREN24_W { AREN24_W::new(self) } #[doc = "Bit 25 - Async rising enabled 25"] #[inline(always)] #[must_use] - pub fn aren25(&mut self) -> AREN25_W<25> { + pub fn aren25(&mut self) -> AREN25_W { AREN25_W::new(self) } #[doc = "Bit 26 - Async rising enabled 26"] #[inline(always)] #[must_use] - pub fn aren26(&mut self) -> AREN26_W<26> { + pub fn aren26(&mut self) -> AREN26_W { AREN26_W::new(self) } #[doc = "Bit 27 - Async rising enabled 27"] #[inline(always)] #[must_use] - pub fn aren27(&mut self) -> AREN27_W<27> { + pub fn aren27(&mut self) -> AREN27_W { AREN27_W::new(self) } #[doc = "Bit 28 - Async rising enabled 28"] #[inline(always)] #[must_use] - pub fn aren28(&mut self) -> AREN28_W<28> { + pub fn aren28(&mut self) -> AREN28_W { AREN28_W::new(self) } #[doc = "Bit 29 - Async rising enabled 29"] #[inline(always)] #[must_use] - pub fn aren29(&mut self) -> AREN29_W<29> { + pub fn aren29(&mut self) -> AREN29_W { AREN29_W::new(self) } #[doc = "Bit 30 - Async rising enabled 30"] #[inline(always)] #[must_use] - pub fn aren30(&mut self) -> AREN30_W<30> { + pub fn aren30(&mut self) -> AREN30_W { AREN30_W::new(self) } #[doc = "Bit 31 - Async rising enabled 31"] #[inline(always)] #[must_use] - pub fn aren31(&mut self) -> AREN31_W<31> { + pub fn aren31(&mut self) -> AREN31_W { AREN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Async. Rising Edge Detect 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gparen0](index.html) module"] +#[doc = "GPIO Pin Async. Rising Edge Detect 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gparen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gparen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPAREN0_SPEC; impl crate::RegisterSpec for GPAREN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gparen0::R](R) reader structure"] -impl crate::Readable for GPAREN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gparen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gparen0::R`](R) reader structure"] +impl crate::Readable for GPAREN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gparen0::W`](W) writer structure"] impl crate::Writable for GPAREN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gparen1.rs b/crates/bcm2711-lpa/src/gpio/gparen1.rs index 28863a6..fee315a 100644 --- a/crates/bcm2711-lpa/src/gpio/gparen1.rs +++ b/crates/bcm2711-lpa/src/gpio/gparen1.rs @@ -1,143 +1,111 @@ #[doc = "Register `GPAREN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPAREN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AREN32` reader - Async rising enabled 32"] -pub type AREN32_R = crate::BitReader; +pub type AREN32_R = crate::BitReader; #[doc = "Field `AREN32` writer - Async rising enabled 32"] -pub type AREN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN33` reader - Async rising enabled 33"] -pub type AREN33_R = crate::BitReader; +pub type AREN33_R = crate::BitReader; #[doc = "Field `AREN33` writer - Async rising enabled 33"] -pub type AREN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN34` reader - Async rising enabled 34"] -pub type AREN34_R = crate::BitReader; +pub type AREN34_R = crate::BitReader; #[doc = "Field `AREN34` writer - Async rising enabled 34"] -pub type AREN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN35` reader - Async rising enabled 35"] -pub type AREN35_R = crate::BitReader; +pub type AREN35_R = crate::BitReader; #[doc = "Field `AREN35` writer - Async rising enabled 35"] -pub type AREN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN36` reader - Async rising enabled 36"] -pub type AREN36_R = crate::BitReader; +pub type AREN36_R = crate::BitReader; #[doc = "Field `AREN36` writer - Async rising enabled 36"] -pub type AREN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN37` reader - Async rising enabled 37"] -pub type AREN37_R = crate::BitReader; +pub type AREN37_R = crate::BitReader; #[doc = "Field `AREN37` writer - Async rising enabled 37"] -pub type AREN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN38` reader - Async rising enabled 38"] -pub type AREN38_R = crate::BitReader; +pub type AREN38_R = crate::BitReader; #[doc = "Field `AREN38` writer - Async rising enabled 38"] -pub type AREN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN39` reader - Async rising enabled 39"] -pub type AREN39_R = crate::BitReader; +pub type AREN39_R = crate::BitReader; #[doc = "Field `AREN39` writer - Async rising enabled 39"] -pub type AREN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN40` reader - Async rising enabled 40"] -pub type AREN40_R = crate::BitReader; +pub type AREN40_R = crate::BitReader; #[doc = "Field `AREN40` writer - Async rising enabled 40"] -pub type AREN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN41` reader - Async rising enabled 41"] -pub type AREN41_R = crate::BitReader; +pub type AREN41_R = crate::BitReader; #[doc = "Field `AREN41` writer - Async rising enabled 41"] -pub type AREN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN42` reader - Async rising enabled 42"] -pub type AREN42_R = crate::BitReader; +pub type AREN42_R = crate::BitReader; #[doc = "Field `AREN42` writer - Async rising enabled 42"] -pub type AREN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN43` reader - Async rising enabled 43"] -pub type AREN43_R = crate::BitReader; +pub type AREN43_R = crate::BitReader; #[doc = "Field `AREN43` writer - Async rising enabled 43"] -pub type AREN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN44` reader - Async rising enabled 44"] -pub type AREN44_R = crate::BitReader; +pub type AREN44_R = crate::BitReader; #[doc = "Field `AREN44` writer - Async rising enabled 44"] -pub type AREN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN45` reader - Async rising enabled 45"] -pub type AREN45_R = crate::BitReader; +pub type AREN45_R = crate::BitReader; #[doc = "Field `AREN45` writer - Async rising enabled 45"] -pub type AREN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN46` reader - Async rising enabled 46"] -pub type AREN46_R = crate::BitReader; +pub type AREN46_R = crate::BitReader; #[doc = "Field `AREN46` writer - Async rising enabled 46"] -pub type AREN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN47` reader - Async rising enabled 47"] -pub type AREN47_R = crate::BitReader; +pub type AREN47_R = crate::BitReader; #[doc = "Field `AREN47` writer - Async rising enabled 47"] -pub type AREN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN48` reader - Async rising enabled 48"] -pub type AREN48_R = crate::BitReader; +pub type AREN48_R = crate::BitReader; #[doc = "Field `AREN48` writer - Async rising enabled 48"] -pub type AREN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN49` reader - Async rising enabled 49"] -pub type AREN49_R = crate::BitReader; +pub type AREN49_R = crate::BitReader; #[doc = "Field `AREN49` writer - Async rising enabled 49"] -pub type AREN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN50` reader - Async rising enabled 50"] -pub type AREN50_R = crate::BitReader; +pub type AREN50_R = crate::BitReader; #[doc = "Field `AREN50` writer - Async rising enabled 50"] -pub type AREN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN51` reader - Async rising enabled 51"] -pub type AREN51_R = crate::BitReader; +pub type AREN51_R = crate::BitReader; #[doc = "Field `AREN51` writer - Async rising enabled 51"] -pub type AREN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN52` reader - Async rising enabled 52"] -pub type AREN52_R = crate::BitReader; +pub type AREN52_R = crate::BitReader; #[doc = "Field `AREN52` writer - Async rising enabled 52"] -pub type AREN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN53` reader - Async rising enabled 53"] -pub type AREN53_R = crate::BitReader; +pub type AREN53_R = crate::BitReader; #[doc = "Field `AREN53` writer - Async rising enabled 53"] -pub type AREN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN54` reader - Async rising enabled 54"] -pub type AREN54_R = crate::BitReader; +pub type AREN54_R = crate::BitReader; #[doc = "Field `AREN54` writer - Async rising enabled 54"] -pub type AREN54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN54_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN55` reader - Async rising enabled 55"] -pub type AREN55_R = crate::BitReader; +pub type AREN55_R = crate::BitReader; #[doc = "Field `AREN55` writer - Async rising enabled 55"] -pub type AREN55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN55_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN56` reader - Async rising enabled 56"] -pub type AREN56_R = crate::BitReader; +pub type AREN56_R = crate::BitReader; #[doc = "Field `AREN56` writer - Async rising enabled 56"] -pub type AREN56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN57` reader - Async rising enabled 57"] -pub type AREN57_R = crate::BitReader; +pub type AREN57_R = crate::BitReader; #[doc = "Field `AREN57` writer - Async rising enabled 57"] -pub type AREN57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Async rising enabled 32"] #[inline(always)] @@ -270,182 +238,220 @@ impl R { AREN57_R::new(((self.bits >> 25) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPAREN1") + .field("aren32", &format_args!("{}", self.aren32().bit())) + .field("aren33", &format_args!("{}", self.aren33().bit())) + .field("aren34", &format_args!("{}", self.aren34().bit())) + .field("aren35", &format_args!("{}", self.aren35().bit())) + .field("aren36", &format_args!("{}", self.aren36().bit())) + .field("aren37", &format_args!("{}", self.aren37().bit())) + .field("aren38", &format_args!("{}", self.aren38().bit())) + .field("aren39", &format_args!("{}", self.aren39().bit())) + .field("aren40", &format_args!("{}", self.aren40().bit())) + .field("aren41", &format_args!("{}", self.aren41().bit())) + .field("aren42", &format_args!("{}", self.aren42().bit())) + .field("aren43", &format_args!("{}", self.aren43().bit())) + .field("aren44", &format_args!("{}", self.aren44().bit())) + .field("aren45", &format_args!("{}", self.aren45().bit())) + .field("aren46", &format_args!("{}", self.aren46().bit())) + .field("aren47", &format_args!("{}", self.aren47().bit())) + .field("aren48", &format_args!("{}", self.aren48().bit())) + .field("aren49", &format_args!("{}", self.aren49().bit())) + .field("aren50", &format_args!("{}", self.aren50().bit())) + .field("aren51", &format_args!("{}", self.aren51().bit())) + .field("aren52", &format_args!("{}", self.aren52().bit())) + .field("aren53", &format_args!("{}", self.aren53().bit())) + .field("aren54", &format_args!("{}", self.aren54().bit())) + .field("aren55", &format_args!("{}", self.aren55().bit())) + .field("aren56", &format_args!("{}", self.aren56().bit())) + .field("aren57", &format_args!("{}", self.aren57().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Async rising enabled 32"] #[inline(always)] #[must_use] - pub fn aren32(&mut self) -> AREN32_W<0> { + pub fn aren32(&mut self) -> AREN32_W { AREN32_W::new(self) } #[doc = "Bit 1 - Async rising enabled 33"] #[inline(always)] #[must_use] - pub fn aren33(&mut self) -> AREN33_W<1> { + pub fn aren33(&mut self) -> AREN33_W { AREN33_W::new(self) } #[doc = "Bit 2 - Async rising enabled 34"] #[inline(always)] #[must_use] - pub fn aren34(&mut self) -> AREN34_W<2> { + pub fn aren34(&mut self) -> AREN34_W { AREN34_W::new(self) } #[doc = "Bit 3 - Async rising enabled 35"] #[inline(always)] #[must_use] - pub fn aren35(&mut self) -> AREN35_W<3> { + pub fn aren35(&mut self) -> AREN35_W { AREN35_W::new(self) } #[doc = "Bit 4 - Async rising enabled 36"] #[inline(always)] #[must_use] - pub fn aren36(&mut self) -> AREN36_W<4> { + pub fn aren36(&mut self) -> AREN36_W { AREN36_W::new(self) } #[doc = "Bit 5 - Async rising enabled 37"] #[inline(always)] #[must_use] - pub fn aren37(&mut self) -> AREN37_W<5> { + pub fn aren37(&mut self) -> AREN37_W { AREN37_W::new(self) } #[doc = "Bit 6 - Async rising enabled 38"] #[inline(always)] #[must_use] - pub fn aren38(&mut self) -> AREN38_W<6> { + pub fn aren38(&mut self) -> AREN38_W { AREN38_W::new(self) } #[doc = "Bit 7 - Async rising enabled 39"] #[inline(always)] #[must_use] - pub fn aren39(&mut self) -> AREN39_W<7> { + pub fn aren39(&mut self) -> AREN39_W { AREN39_W::new(self) } #[doc = "Bit 8 - Async rising enabled 40"] #[inline(always)] #[must_use] - pub fn aren40(&mut self) -> AREN40_W<8> { + pub fn aren40(&mut self) -> AREN40_W { AREN40_W::new(self) } #[doc = "Bit 9 - Async rising enabled 41"] #[inline(always)] #[must_use] - pub fn aren41(&mut self) -> AREN41_W<9> { + pub fn aren41(&mut self) -> AREN41_W { AREN41_W::new(self) } #[doc = "Bit 10 - Async rising enabled 42"] #[inline(always)] #[must_use] - pub fn aren42(&mut self) -> AREN42_W<10> { + pub fn aren42(&mut self) -> AREN42_W { AREN42_W::new(self) } #[doc = "Bit 11 - Async rising enabled 43"] #[inline(always)] #[must_use] - pub fn aren43(&mut self) -> AREN43_W<11> { + pub fn aren43(&mut self) -> AREN43_W { AREN43_W::new(self) } #[doc = "Bit 12 - Async rising enabled 44"] #[inline(always)] #[must_use] - pub fn aren44(&mut self) -> AREN44_W<12> { + pub fn aren44(&mut self) -> AREN44_W { AREN44_W::new(self) } #[doc = "Bit 13 - Async rising enabled 45"] #[inline(always)] #[must_use] - pub fn aren45(&mut self) -> AREN45_W<13> { + pub fn aren45(&mut self) -> AREN45_W { AREN45_W::new(self) } #[doc = "Bit 14 - Async rising enabled 46"] #[inline(always)] #[must_use] - pub fn aren46(&mut self) -> AREN46_W<14> { + pub fn aren46(&mut self) -> AREN46_W { AREN46_W::new(self) } #[doc = "Bit 15 - Async rising enabled 47"] #[inline(always)] #[must_use] - pub fn aren47(&mut self) -> AREN47_W<15> { + pub fn aren47(&mut self) -> AREN47_W { AREN47_W::new(self) } #[doc = "Bit 16 - Async rising enabled 48"] #[inline(always)] #[must_use] - pub fn aren48(&mut self) -> AREN48_W<16> { + pub fn aren48(&mut self) -> AREN48_W { AREN48_W::new(self) } #[doc = "Bit 17 - Async rising enabled 49"] #[inline(always)] #[must_use] - pub fn aren49(&mut self) -> AREN49_W<17> { + pub fn aren49(&mut self) -> AREN49_W { AREN49_W::new(self) } #[doc = "Bit 18 - Async rising enabled 50"] #[inline(always)] #[must_use] - pub fn aren50(&mut self) -> AREN50_W<18> { + pub fn aren50(&mut self) -> AREN50_W { AREN50_W::new(self) } #[doc = "Bit 19 - Async rising enabled 51"] #[inline(always)] #[must_use] - pub fn aren51(&mut self) -> AREN51_W<19> { + pub fn aren51(&mut self) -> AREN51_W { AREN51_W::new(self) } #[doc = "Bit 20 - Async rising enabled 52"] #[inline(always)] #[must_use] - pub fn aren52(&mut self) -> AREN52_W<20> { + pub fn aren52(&mut self) -> AREN52_W { AREN52_W::new(self) } #[doc = "Bit 21 - Async rising enabled 53"] #[inline(always)] #[must_use] - pub fn aren53(&mut self) -> AREN53_W<21> { + pub fn aren53(&mut self) -> AREN53_W { AREN53_W::new(self) } #[doc = "Bit 22 - Async rising enabled 54"] #[inline(always)] #[must_use] - pub fn aren54(&mut self) -> AREN54_W<22> { + pub fn aren54(&mut self) -> AREN54_W { AREN54_W::new(self) } #[doc = "Bit 23 - Async rising enabled 55"] #[inline(always)] #[must_use] - pub fn aren55(&mut self) -> AREN55_W<23> { + pub fn aren55(&mut self) -> AREN55_W { AREN55_W::new(self) } #[doc = "Bit 24 - Async rising enabled 56"] #[inline(always)] #[must_use] - pub fn aren56(&mut self) -> AREN56_W<24> { + pub fn aren56(&mut self) -> AREN56_W { AREN56_W::new(self) } #[doc = "Bit 25 - Async rising enabled 57"] #[inline(always)] #[must_use] - pub fn aren57(&mut self) -> AREN57_W<25> { + pub fn aren57(&mut self) -> AREN57_W { AREN57_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Async. Rising Edge Detect 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gparen1](index.html) module"] +#[doc = "GPIO Pin Async. Rising Edge Detect 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gparen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gparen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPAREN1_SPEC; impl crate::RegisterSpec for GPAREN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gparen1::R](R) reader structure"] -impl crate::Readable for GPAREN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gparen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gparen1::R`](R) reader structure"] +impl crate::Readable for GPAREN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gparen1::W`](W) writer structure"] impl crate::Writable for GPAREN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpclr0.rs b/crates/bcm2711-lpa/src/gpio/gpclr0.rs index 1a6b2cd..210af7f 100644 --- a/crates/bcm2711-lpa/src/gpio/gpclr0.rs +++ b/crates/bcm2711-lpa/src/gpio/gpclr0.rs @@ -1,296 +1,285 @@ #[doc = "Register `GPCLR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLR0` writer - Clear 0"] -pub type CLR0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR1` writer - Clear 1"] -pub type CLR1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR2` writer - Clear 2"] -pub type CLR2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR3` writer - Clear 3"] -pub type CLR3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR4` writer - Clear 4"] -pub type CLR4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR5` writer - Clear 5"] -pub type CLR5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR6` writer - Clear 6"] -pub type CLR6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR7` writer - Clear 7"] -pub type CLR7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR8` writer - Clear 8"] -pub type CLR8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR9` writer - Clear 9"] -pub type CLR9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR9_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR10` writer - Clear 10"] -pub type CLR10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR11` writer - Clear 11"] -pub type CLR11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR12` writer - Clear 12"] -pub type CLR12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR13` writer - Clear 13"] -pub type CLR13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR14` writer - Clear 14"] -pub type CLR14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR15` writer - Clear 15"] -pub type CLR15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR16` writer - Clear 16"] -pub type CLR16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR16_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR17` writer - Clear 17"] -pub type CLR17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR17_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR18` writer - Clear 18"] -pub type CLR18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR18_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR19` writer - Clear 19"] -pub type CLR19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR19_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR20` writer - Clear 20"] -pub type CLR20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR20_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR21` writer - Clear 21"] -pub type CLR21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR21_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR22` writer - Clear 22"] -pub type CLR22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR22_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR23` writer - Clear 23"] -pub type CLR23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR23_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR24` writer - Clear 24"] -pub type CLR24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR24_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR25` writer - Clear 25"] -pub type CLR25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR25_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR26` writer - Clear 26"] -pub type CLR26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR26_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR27` writer - Clear 27"] -pub type CLR27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR27_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR28` writer - Clear 28"] -pub type CLR28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR28_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR29` writer - Clear 29"] -pub type CLR29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR29_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR30` writer - Clear 30"] -pub type CLR30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR30_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR31` writer - Clear 31"] -pub type CLR31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR31_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - Clear 0"] #[inline(always)] #[must_use] - pub fn clr0(&mut self) -> CLR0_W<0> { + pub fn clr0(&mut self) -> CLR0_W { CLR0_W::new(self) } #[doc = "Bit 1 - Clear 1"] #[inline(always)] #[must_use] - pub fn clr1(&mut self) -> CLR1_W<1> { + pub fn clr1(&mut self) -> CLR1_W { CLR1_W::new(self) } #[doc = "Bit 2 - Clear 2"] #[inline(always)] #[must_use] - pub fn clr2(&mut self) -> CLR2_W<2> { + pub fn clr2(&mut self) -> CLR2_W { CLR2_W::new(self) } #[doc = "Bit 3 - Clear 3"] #[inline(always)] #[must_use] - pub fn clr3(&mut self) -> CLR3_W<3> { + pub fn clr3(&mut self) -> CLR3_W { CLR3_W::new(self) } #[doc = "Bit 4 - Clear 4"] #[inline(always)] #[must_use] - pub fn clr4(&mut self) -> CLR4_W<4> { + pub fn clr4(&mut self) -> CLR4_W { CLR4_W::new(self) } #[doc = "Bit 5 - Clear 5"] #[inline(always)] #[must_use] - pub fn clr5(&mut self) -> CLR5_W<5> { + pub fn clr5(&mut self) -> CLR5_W { CLR5_W::new(self) } #[doc = "Bit 6 - Clear 6"] #[inline(always)] #[must_use] - pub fn clr6(&mut self) -> CLR6_W<6> { + pub fn clr6(&mut self) -> CLR6_W { CLR6_W::new(self) } #[doc = "Bit 7 - Clear 7"] #[inline(always)] #[must_use] - pub fn clr7(&mut self) -> CLR7_W<7> { + pub fn clr7(&mut self) -> CLR7_W { CLR7_W::new(self) } #[doc = "Bit 8 - Clear 8"] #[inline(always)] #[must_use] - pub fn clr8(&mut self) -> CLR8_W<8> { + pub fn clr8(&mut self) -> CLR8_W { CLR8_W::new(self) } #[doc = "Bit 9 - Clear 9"] #[inline(always)] #[must_use] - pub fn clr9(&mut self) -> CLR9_W<9> { + pub fn clr9(&mut self) -> CLR9_W { CLR9_W::new(self) } #[doc = "Bit 10 - Clear 10"] #[inline(always)] #[must_use] - pub fn clr10(&mut self) -> CLR10_W<10> { + pub fn clr10(&mut self) -> CLR10_W { CLR10_W::new(self) } #[doc = "Bit 11 - Clear 11"] #[inline(always)] #[must_use] - pub fn clr11(&mut self) -> CLR11_W<11> { + pub fn clr11(&mut self) -> CLR11_W { CLR11_W::new(self) } #[doc = "Bit 12 - Clear 12"] #[inline(always)] #[must_use] - pub fn clr12(&mut self) -> CLR12_W<12> { + pub fn clr12(&mut self) -> CLR12_W { CLR12_W::new(self) } #[doc = "Bit 13 - Clear 13"] #[inline(always)] #[must_use] - pub fn clr13(&mut self) -> CLR13_W<13> { + pub fn clr13(&mut self) -> CLR13_W { CLR13_W::new(self) } #[doc = "Bit 14 - Clear 14"] #[inline(always)] #[must_use] - pub fn clr14(&mut self) -> CLR14_W<14> { + pub fn clr14(&mut self) -> CLR14_W { CLR14_W::new(self) } #[doc = "Bit 15 - Clear 15"] #[inline(always)] #[must_use] - pub fn clr15(&mut self) -> CLR15_W<15> { + pub fn clr15(&mut self) -> CLR15_W { CLR15_W::new(self) } #[doc = "Bit 16 - Clear 16"] #[inline(always)] #[must_use] - pub fn clr16(&mut self) -> CLR16_W<16> { + pub fn clr16(&mut self) -> CLR16_W { CLR16_W::new(self) } #[doc = "Bit 17 - Clear 17"] #[inline(always)] #[must_use] - pub fn clr17(&mut self) -> CLR17_W<17> { + pub fn clr17(&mut self) -> CLR17_W { CLR17_W::new(self) } #[doc = "Bit 18 - Clear 18"] #[inline(always)] #[must_use] - pub fn clr18(&mut self) -> CLR18_W<18> { + pub fn clr18(&mut self) -> CLR18_W { CLR18_W::new(self) } #[doc = "Bit 19 - Clear 19"] #[inline(always)] #[must_use] - pub fn clr19(&mut self) -> CLR19_W<19> { + pub fn clr19(&mut self) -> CLR19_W { CLR19_W::new(self) } #[doc = "Bit 20 - Clear 20"] #[inline(always)] #[must_use] - pub fn clr20(&mut self) -> CLR20_W<20> { + pub fn clr20(&mut self) -> CLR20_W { CLR20_W::new(self) } #[doc = "Bit 21 - Clear 21"] #[inline(always)] #[must_use] - pub fn clr21(&mut self) -> CLR21_W<21> { + pub fn clr21(&mut self) -> CLR21_W { CLR21_W::new(self) } #[doc = "Bit 22 - Clear 22"] #[inline(always)] #[must_use] - pub fn clr22(&mut self) -> CLR22_W<22> { + pub fn clr22(&mut self) -> CLR22_W { CLR22_W::new(self) } #[doc = "Bit 23 - Clear 23"] #[inline(always)] #[must_use] - pub fn clr23(&mut self) -> CLR23_W<23> { + pub fn clr23(&mut self) -> CLR23_W { CLR23_W::new(self) } #[doc = "Bit 24 - Clear 24"] #[inline(always)] #[must_use] - pub fn clr24(&mut self) -> CLR24_W<24> { + pub fn clr24(&mut self) -> CLR24_W { CLR24_W::new(self) } #[doc = "Bit 25 - Clear 25"] #[inline(always)] #[must_use] - pub fn clr25(&mut self) -> CLR25_W<25> { + pub fn clr25(&mut self) -> CLR25_W { CLR25_W::new(self) } #[doc = "Bit 26 - Clear 26"] #[inline(always)] #[must_use] - pub fn clr26(&mut self) -> CLR26_W<26> { + pub fn clr26(&mut self) -> CLR26_W { CLR26_W::new(self) } #[doc = "Bit 27 - Clear 27"] #[inline(always)] #[must_use] - pub fn clr27(&mut self) -> CLR27_W<27> { + pub fn clr27(&mut self) -> CLR27_W { CLR27_W::new(self) } #[doc = "Bit 28 - Clear 28"] #[inline(always)] #[must_use] - pub fn clr28(&mut self) -> CLR28_W<28> { + pub fn clr28(&mut self) -> CLR28_W { CLR28_W::new(self) } #[doc = "Bit 29 - Clear 29"] #[inline(always)] #[must_use] - pub fn clr29(&mut self) -> CLR29_W<29> { + pub fn clr29(&mut self) -> CLR29_W { CLR29_W::new(self) } #[doc = "Bit 30 - Clear 30"] #[inline(always)] #[must_use] - pub fn clr30(&mut self) -> CLR30_W<30> { + pub fn clr30(&mut self) -> CLR30_W { CLR30_W::new(self) } #[doc = "Bit 31 - Clear 31"] #[inline(always)] #[must_use] - pub fn clr31(&mut self) -> CLR31_W<31> { + pub fn clr31(&mut self) -> CLR31_W { CLR31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Output Clear 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpclr0](index.html) module"] +#[doc = "GPIO Pin Output Clear 0\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpclr0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPCLR0_SPEC; impl crate::RegisterSpec for GPCLR0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpclr0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpclr0::W`](W) writer structure"] impl crate::Writable for GPCLR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gpio/gpclr1.rs b/crates/bcm2711-lpa/src/gpio/gpclr1.rs index 60a0085..a09a556 100644 --- a/crates/bcm2711-lpa/src/gpio/gpclr1.rs +++ b/crates/bcm2711-lpa/src/gpio/gpclr1.rs @@ -1,248 +1,237 @@ #[doc = "Register `GPCLR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLR32` writer - Clear 32"] -pub type CLR32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR32_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR33` writer - Clear 33"] -pub type CLR33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR33_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR34` writer - Clear 34"] -pub type CLR34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR34_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR35` writer - Clear 35"] -pub type CLR35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR35_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR36` writer - Clear 36"] -pub type CLR36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR36_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR37` writer - Clear 37"] -pub type CLR37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR37_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR38` writer - Clear 38"] -pub type CLR38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR38_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR39` writer - Clear 39"] -pub type CLR39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR39_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR40` writer - Clear 40"] -pub type CLR40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR40_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR41` writer - Clear 41"] -pub type CLR41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR41_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR42` writer - Clear 42"] -pub type CLR42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR42_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR43` writer - Clear 43"] -pub type CLR43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR43_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR44` writer - Clear 44"] -pub type CLR44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR44_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR45` writer - Clear 45"] -pub type CLR45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR45_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR46` writer - Clear 46"] -pub type CLR46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR46_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR47` writer - Clear 47"] -pub type CLR47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR47_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR48` writer - Clear 48"] -pub type CLR48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR48_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR49` writer - Clear 49"] -pub type CLR49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR49_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR50` writer - Clear 50"] -pub type CLR50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR50_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR51` writer - Clear 51"] -pub type CLR51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR51_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR52` writer - Clear 52"] -pub type CLR52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR52_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR53` writer - Clear 53"] -pub type CLR53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR53_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR54` writer - Clear 54"] -pub type CLR54_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR54_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR55` writer - Clear 55"] -pub type CLR55_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR55_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR56` writer - Clear 56"] -pub type CLR56_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR56_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR57` writer - Clear 57"] -pub type CLR57_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR57_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - Clear 32"] #[inline(always)] #[must_use] - pub fn clr32(&mut self) -> CLR32_W<0> { + pub fn clr32(&mut self) -> CLR32_W { CLR32_W::new(self) } #[doc = "Bit 1 - Clear 33"] #[inline(always)] #[must_use] - pub fn clr33(&mut self) -> CLR33_W<1> { + pub fn clr33(&mut self) -> CLR33_W { CLR33_W::new(self) } #[doc = "Bit 2 - Clear 34"] #[inline(always)] #[must_use] - pub fn clr34(&mut self) -> CLR34_W<2> { + pub fn clr34(&mut self) -> CLR34_W { CLR34_W::new(self) } #[doc = "Bit 3 - Clear 35"] #[inline(always)] #[must_use] - pub fn clr35(&mut self) -> CLR35_W<3> { + pub fn clr35(&mut self) -> CLR35_W { CLR35_W::new(self) } #[doc = "Bit 4 - Clear 36"] #[inline(always)] #[must_use] - pub fn clr36(&mut self) -> CLR36_W<4> { + pub fn clr36(&mut self) -> CLR36_W { CLR36_W::new(self) } #[doc = "Bit 5 - Clear 37"] #[inline(always)] #[must_use] - pub fn clr37(&mut self) -> CLR37_W<5> { + pub fn clr37(&mut self) -> CLR37_W { CLR37_W::new(self) } #[doc = "Bit 6 - Clear 38"] #[inline(always)] #[must_use] - pub fn clr38(&mut self) -> CLR38_W<6> { + pub fn clr38(&mut self) -> CLR38_W { CLR38_W::new(self) } #[doc = "Bit 7 - Clear 39"] #[inline(always)] #[must_use] - pub fn clr39(&mut self) -> CLR39_W<7> { + pub fn clr39(&mut self) -> CLR39_W { CLR39_W::new(self) } #[doc = "Bit 8 - Clear 40"] #[inline(always)] #[must_use] - pub fn clr40(&mut self) -> CLR40_W<8> { + pub fn clr40(&mut self) -> CLR40_W { CLR40_W::new(self) } #[doc = "Bit 9 - Clear 41"] #[inline(always)] #[must_use] - pub fn clr41(&mut self) -> CLR41_W<9> { + pub fn clr41(&mut self) -> CLR41_W { CLR41_W::new(self) } #[doc = "Bit 10 - Clear 42"] #[inline(always)] #[must_use] - pub fn clr42(&mut self) -> CLR42_W<10> { + pub fn clr42(&mut self) -> CLR42_W { CLR42_W::new(self) } #[doc = "Bit 11 - Clear 43"] #[inline(always)] #[must_use] - pub fn clr43(&mut self) -> CLR43_W<11> { + pub fn clr43(&mut self) -> CLR43_W { CLR43_W::new(self) } #[doc = "Bit 12 - Clear 44"] #[inline(always)] #[must_use] - pub fn clr44(&mut self) -> CLR44_W<12> { + pub fn clr44(&mut self) -> CLR44_W { CLR44_W::new(self) } #[doc = "Bit 13 - Clear 45"] #[inline(always)] #[must_use] - pub fn clr45(&mut self) -> CLR45_W<13> { + pub fn clr45(&mut self) -> CLR45_W { CLR45_W::new(self) } #[doc = "Bit 14 - Clear 46"] #[inline(always)] #[must_use] - pub fn clr46(&mut self) -> CLR46_W<14> { + pub fn clr46(&mut self) -> CLR46_W { CLR46_W::new(self) } #[doc = "Bit 15 - Clear 47"] #[inline(always)] #[must_use] - pub fn clr47(&mut self) -> CLR47_W<15> { + pub fn clr47(&mut self) -> CLR47_W { CLR47_W::new(self) } #[doc = "Bit 16 - Clear 48"] #[inline(always)] #[must_use] - pub fn clr48(&mut self) -> CLR48_W<16> { + pub fn clr48(&mut self) -> CLR48_W { CLR48_W::new(self) } #[doc = "Bit 17 - Clear 49"] #[inline(always)] #[must_use] - pub fn clr49(&mut self) -> CLR49_W<17> { + pub fn clr49(&mut self) -> CLR49_W { CLR49_W::new(self) } #[doc = "Bit 18 - Clear 50"] #[inline(always)] #[must_use] - pub fn clr50(&mut self) -> CLR50_W<18> { + pub fn clr50(&mut self) -> CLR50_W { CLR50_W::new(self) } #[doc = "Bit 19 - Clear 51"] #[inline(always)] #[must_use] - pub fn clr51(&mut self) -> CLR51_W<19> { + pub fn clr51(&mut self) -> CLR51_W { CLR51_W::new(self) } #[doc = "Bit 20 - Clear 52"] #[inline(always)] #[must_use] - pub fn clr52(&mut self) -> CLR52_W<20> { + pub fn clr52(&mut self) -> CLR52_W { CLR52_W::new(self) } #[doc = "Bit 21 - Clear 53"] #[inline(always)] #[must_use] - pub fn clr53(&mut self) -> CLR53_W<21> { + pub fn clr53(&mut self) -> CLR53_W { CLR53_W::new(self) } #[doc = "Bit 22 - Clear 54"] #[inline(always)] #[must_use] - pub fn clr54(&mut self) -> CLR54_W<22> { + pub fn clr54(&mut self) -> CLR54_W { CLR54_W::new(self) } #[doc = "Bit 23 - Clear 55"] #[inline(always)] #[must_use] - pub fn clr55(&mut self) -> CLR55_W<23> { + pub fn clr55(&mut self) -> CLR55_W { CLR55_W::new(self) } #[doc = "Bit 24 - Clear 56"] #[inline(always)] #[must_use] - pub fn clr56(&mut self) -> CLR56_W<24> { + pub fn clr56(&mut self) -> CLR56_W { CLR56_W::new(self) } #[doc = "Bit 25 - Clear 57"] #[inline(always)] #[must_use] - pub fn clr57(&mut self) -> CLR57_W<25> { + pub fn clr57(&mut self) -> CLR57_W { CLR57_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Output Clear 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpclr1](index.html) module"] +#[doc = "GPIO Pin Output Clear 1\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpclr1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPCLR1_SPEC; impl crate::RegisterSpec for GPCLR1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpclr1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpclr1::W`](W) writer structure"] impl crate::Writable for GPCLR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x03ff_ffff; } diff --git a/crates/bcm2711-lpa/src/gpio/gpeds0.rs b/crates/bcm2711-lpa/src/gpio/gpeds0.rs index 7aadf5b..caa11e1 100644 --- a/crates/bcm2711-lpa/src/gpio/gpeds0.rs +++ b/crates/bcm2711-lpa/src/gpio/gpeds0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPEDS0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPEDS0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EDS0` reader - Event detected 0"] -pub type EDS0_R = crate::BitReader; +pub type EDS0_R = crate::BitReader; #[doc = "Field `EDS0` writer - Event detected 0"] -pub type EDS0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS1` reader - Event detected 1"] -pub type EDS1_R = crate::BitReader; +pub type EDS1_R = crate::BitReader; #[doc = "Field `EDS1` writer - Event detected 1"] -pub type EDS1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS2` reader - Event detected 2"] -pub type EDS2_R = crate::BitReader; +pub type EDS2_R = crate::BitReader; #[doc = "Field `EDS2` writer - Event detected 2"] -pub type EDS2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS3` reader - Event detected 3"] -pub type EDS3_R = crate::BitReader; +pub type EDS3_R = crate::BitReader; #[doc = "Field `EDS3` writer - Event detected 3"] -pub type EDS3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS4` reader - Event detected 4"] -pub type EDS4_R = crate::BitReader; +pub type EDS4_R = crate::BitReader; #[doc = "Field `EDS4` writer - Event detected 4"] -pub type EDS4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS5` reader - Event detected 5"] -pub type EDS5_R = crate::BitReader; +pub type EDS5_R = crate::BitReader; #[doc = "Field `EDS5` writer - Event detected 5"] -pub type EDS5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS6` reader - Event detected 6"] -pub type EDS6_R = crate::BitReader; +pub type EDS6_R = crate::BitReader; #[doc = "Field `EDS6` writer - Event detected 6"] -pub type EDS6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS7` reader - Event detected 7"] -pub type EDS7_R = crate::BitReader; +pub type EDS7_R = crate::BitReader; #[doc = "Field `EDS7` writer - Event detected 7"] -pub type EDS7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS8` reader - Event detected 8"] -pub type EDS8_R = crate::BitReader; +pub type EDS8_R = crate::BitReader; #[doc = "Field `EDS8` writer - Event detected 8"] -pub type EDS8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS9` reader - Event detected 9"] -pub type EDS9_R = crate::BitReader; +pub type EDS9_R = crate::BitReader; #[doc = "Field `EDS9` writer - Event detected 9"] -pub type EDS9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS9_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS10` reader - Event detected 10"] -pub type EDS10_R = crate::BitReader; +pub type EDS10_R = crate::BitReader; #[doc = "Field `EDS10` writer - Event detected 10"] -pub type EDS10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS11` reader - Event detected 11"] -pub type EDS11_R = crate::BitReader; +pub type EDS11_R = crate::BitReader; #[doc = "Field `EDS11` writer - Event detected 11"] -pub type EDS11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS12` reader - Event detected 12"] -pub type EDS12_R = crate::BitReader; +pub type EDS12_R = crate::BitReader; #[doc = "Field `EDS12` writer - Event detected 12"] -pub type EDS12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS13` reader - Event detected 13"] -pub type EDS13_R = crate::BitReader; +pub type EDS13_R = crate::BitReader; #[doc = "Field `EDS13` writer - Event detected 13"] -pub type EDS13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS14` reader - Event detected 14"] -pub type EDS14_R = crate::BitReader; +pub type EDS14_R = crate::BitReader; #[doc = "Field `EDS14` writer - Event detected 14"] -pub type EDS14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS15` reader - Event detected 15"] -pub type EDS15_R = crate::BitReader; +pub type EDS15_R = crate::BitReader; #[doc = "Field `EDS15` writer - Event detected 15"] -pub type EDS15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS16` reader - Event detected 16"] -pub type EDS16_R = crate::BitReader; +pub type EDS16_R = crate::BitReader; #[doc = "Field `EDS16` writer - Event detected 16"] -pub type EDS16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS16_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS17` reader - Event detected 17"] -pub type EDS17_R = crate::BitReader; +pub type EDS17_R = crate::BitReader; #[doc = "Field `EDS17` writer - Event detected 17"] -pub type EDS17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS17_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS18` reader - Event detected 18"] -pub type EDS18_R = crate::BitReader; +pub type EDS18_R = crate::BitReader; #[doc = "Field `EDS18` writer - Event detected 18"] -pub type EDS18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS18_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS19` reader - Event detected 19"] -pub type EDS19_R = crate::BitReader; +pub type EDS19_R = crate::BitReader; #[doc = "Field `EDS19` writer - Event detected 19"] -pub type EDS19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS19_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS20` reader - Event detected 20"] -pub type EDS20_R = crate::BitReader; +pub type EDS20_R = crate::BitReader; #[doc = "Field `EDS20` writer - Event detected 20"] -pub type EDS20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS20_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS21` reader - Event detected 21"] -pub type EDS21_R = crate::BitReader; +pub type EDS21_R = crate::BitReader; #[doc = "Field `EDS21` writer - Event detected 21"] -pub type EDS21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS21_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS22` reader - Event detected 22"] -pub type EDS22_R = crate::BitReader; +pub type EDS22_R = crate::BitReader; #[doc = "Field `EDS22` writer - Event detected 22"] -pub type EDS22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS22_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS23` reader - Event detected 23"] -pub type EDS23_R = crate::BitReader; +pub type EDS23_R = crate::BitReader; #[doc = "Field `EDS23` writer - Event detected 23"] -pub type EDS23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS23_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS24` reader - Event detected 24"] -pub type EDS24_R = crate::BitReader; +pub type EDS24_R = crate::BitReader; #[doc = "Field `EDS24` writer - Event detected 24"] -pub type EDS24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS24_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS25` reader - Event detected 25"] -pub type EDS25_R = crate::BitReader; +pub type EDS25_R = crate::BitReader; #[doc = "Field `EDS25` writer - Event detected 25"] -pub type EDS25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS25_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS26` reader - Event detected 26"] -pub type EDS26_R = crate::BitReader; +pub type EDS26_R = crate::BitReader; #[doc = "Field `EDS26` writer - Event detected 26"] -pub type EDS26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS26_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS27` reader - Event detected 27"] -pub type EDS27_R = crate::BitReader; +pub type EDS27_R = crate::BitReader; #[doc = "Field `EDS27` writer - Event detected 27"] -pub type EDS27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS27_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS28` reader - Event detected 28"] -pub type EDS28_R = crate::BitReader; +pub type EDS28_R = crate::BitReader; #[doc = "Field `EDS28` writer - Event detected 28"] -pub type EDS28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS28_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS29` reader - Event detected 29"] -pub type EDS29_R = crate::BitReader; +pub type EDS29_R = crate::BitReader; #[doc = "Field `EDS29` writer - Event detected 29"] -pub type EDS29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS29_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS30` reader - Event detected 30"] -pub type EDS30_R = crate::BitReader; +pub type EDS30_R = crate::BitReader; #[doc = "Field `EDS30` writer - Event detected 30"] -pub type EDS30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS30_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS31` reader - Event detected 31"] -pub type EDS31_R = crate::BitReader; +pub type EDS31_R = crate::BitReader; #[doc = "Field `EDS31` writer - Event detected 31"] -pub type EDS31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS31_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Event detected 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { EDS31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPEDS0") + .field("eds0", &format_args!("{}", self.eds0().bit())) + .field("eds1", &format_args!("{}", self.eds1().bit())) + .field("eds2", &format_args!("{}", self.eds2().bit())) + .field("eds3", &format_args!("{}", self.eds3().bit())) + .field("eds4", &format_args!("{}", self.eds4().bit())) + .field("eds5", &format_args!("{}", self.eds5().bit())) + .field("eds6", &format_args!("{}", self.eds6().bit())) + .field("eds7", &format_args!("{}", self.eds7().bit())) + .field("eds8", &format_args!("{}", self.eds8().bit())) + .field("eds9", &format_args!("{}", self.eds9().bit())) + .field("eds10", &format_args!("{}", self.eds10().bit())) + .field("eds11", &format_args!("{}", self.eds11().bit())) + .field("eds12", &format_args!("{}", self.eds12().bit())) + .field("eds13", &format_args!("{}", self.eds13().bit())) + .field("eds14", &format_args!("{}", self.eds14().bit())) + .field("eds15", &format_args!("{}", self.eds15().bit())) + .field("eds16", &format_args!("{}", self.eds16().bit())) + .field("eds17", &format_args!("{}", self.eds17().bit())) + .field("eds18", &format_args!("{}", self.eds18().bit())) + .field("eds19", &format_args!("{}", self.eds19().bit())) + .field("eds20", &format_args!("{}", self.eds20().bit())) + .field("eds21", &format_args!("{}", self.eds21().bit())) + .field("eds22", &format_args!("{}", self.eds22().bit())) + .field("eds23", &format_args!("{}", self.eds23().bit())) + .field("eds24", &format_args!("{}", self.eds24().bit())) + .field("eds25", &format_args!("{}", self.eds25().bit())) + .field("eds26", &format_args!("{}", self.eds26().bit())) + .field("eds27", &format_args!("{}", self.eds27().bit())) + .field("eds28", &format_args!("{}", self.eds28().bit())) + .field("eds29", &format_args!("{}", self.eds29().bit())) + .field("eds30", &format_args!("{}", self.eds30().bit())) + .field("eds31", &format_args!("{}", self.eds31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Event detected 0"] #[inline(always)] #[must_use] - pub fn eds0(&mut self) -> EDS0_W<0> { + pub fn eds0(&mut self) -> EDS0_W { EDS0_W::new(self) } #[doc = "Bit 1 - Event detected 1"] #[inline(always)] #[must_use] - pub fn eds1(&mut self) -> EDS1_W<1> { + pub fn eds1(&mut self) -> EDS1_W { EDS1_W::new(self) } #[doc = "Bit 2 - Event detected 2"] #[inline(always)] #[must_use] - pub fn eds2(&mut self) -> EDS2_W<2> { + pub fn eds2(&mut self) -> EDS2_W { EDS2_W::new(self) } #[doc = "Bit 3 - Event detected 3"] #[inline(always)] #[must_use] - pub fn eds3(&mut self) -> EDS3_W<3> { + pub fn eds3(&mut self) -> EDS3_W { EDS3_W::new(self) } #[doc = "Bit 4 - Event detected 4"] #[inline(always)] #[must_use] - pub fn eds4(&mut self) -> EDS4_W<4> { + pub fn eds4(&mut self) -> EDS4_W { EDS4_W::new(self) } #[doc = "Bit 5 - Event detected 5"] #[inline(always)] #[must_use] - pub fn eds5(&mut self) -> EDS5_W<5> { + pub fn eds5(&mut self) -> EDS5_W { EDS5_W::new(self) } #[doc = "Bit 6 - Event detected 6"] #[inline(always)] #[must_use] - pub fn eds6(&mut self) -> EDS6_W<6> { + pub fn eds6(&mut self) -> EDS6_W { EDS6_W::new(self) } #[doc = "Bit 7 - Event detected 7"] #[inline(always)] #[must_use] - pub fn eds7(&mut self) -> EDS7_W<7> { + pub fn eds7(&mut self) -> EDS7_W { EDS7_W::new(self) } #[doc = "Bit 8 - Event detected 8"] #[inline(always)] #[must_use] - pub fn eds8(&mut self) -> EDS8_W<8> { + pub fn eds8(&mut self) -> EDS8_W { EDS8_W::new(self) } #[doc = "Bit 9 - Event detected 9"] #[inline(always)] #[must_use] - pub fn eds9(&mut self) -> EDS9_W<9> { + pub fn eds9(&mut self) -> EDS9_W { EDS9_W::new(self) } #[doc = "Bit 10 - Event detected 10"] #[inline(always)] #[must_use] - pub fn eds10(&mut self) -> EDS10_W<10> { + pub fn eds10(&mut self) -> EDS10_W { EDS10_W::new(self) } #[doc = "Bit 11 - Event detected 11"] #[inline(always)] #[must_use] - pub fn eds11(&mut self) -> EDS11_W<11> { + pub fn eds11(&mut self) -> EDS11_W { EDS11_W::new(self) } #[doc = "Bit 12 - Event detected 12"] #[inline(always)] #[must_use] - pub fn eds12(&mut self) -> EDS12_W<12> { + pub fn eds12(&mut self) -> EDS12_W { EDS12_W::new(self) } #[doc = "Bit 13 - Event detected 13"] #[inline(always)] #[must_use] - pub fn eds13(&mut self) -> EDS13_W<13> { + pub fn eds13(&mut self) -> EDS13_W { EDS13_W::new(self) } #[doc = "Bit 14 - Event detected 14"] #[inline(always)] #[must_use] - pub fn eds14(&mut self) -> EDS14_W<14> { + pub fn eds14(&mut self) -> EDS14_W { EDS14_W::new(self) } #[doc = "Bit 15 - Event detected 15"] #[inline(always)] #[must_use] - pub fn eds15(&mut self) -> EDS15_W<15> { + pub fn eds15(&mut self) -> EDS15_W { EDS15_W::new(self) } #[doc = "Bit 16 - Event detected 16"] #[inline(always)] #[must_use] - pub fn eds16(&mut self) -> EDS16_W<16> { + pub fn eds16(&mut self) -> EDS16_W { EDS16_W::new(self) } #[doc = "Bit 17 - Event detected 17"] #[inline(always)] #[must_use] - pub fn eds17(&mut self) -> EDS17_W<17> { + pub fn eds17(&mut self) -> EDS17_W { EDS17_W::new(self) } #[doc = "Bit 18 - Event detected 18"] #[inline(always)] #[must_use] - pub fn eds18(&mut self) -> EDS18_W<18> { + pub fn eds18(&mut self) -> EDS18_W { EDS18_W::new(self) } #[doc = "Bit 19 - Event detected 19"] #[inline(always)] #[must_use] - pub fn eds19(&mut self) -> EDS19_W<19> { + pub fn eds19(&mut self) -> EDS19_W { EDS19_W::new(self) } #[doc = "Bit 20 - Event detected 20"] #[inline(always)] #[must_use] - pub fn eds20(&mut self) -> EDS20_W<20> { + pub fn eds20(&mut self) -> EDS20_W { EDS20_W::new(self) } #[doc = "Bit 21 - Event detected 21"] #[inline(always)] #[must_use] - pub fn eds21(&mut self) -> EDS21_W<21> { + pub fn eds21(&mut self) -> EDS21_W { EDS21_W::new(self) } #[doc = "Bit 22 - Event detected 22"] #[inline(always)] #[must_use] - pub fn eds22(&mut self) -> EDS22_W<22> { + pub fn eds22(&mut self) -> EDS22_W { EDS22_W::new(self) } #[doc = "Bit 23 - Event detected 23"] #[inline(always)] #[must_use] - pub fn eds23(&mut self) -> EDS23_W<23> { + pub fn eds23(&mut self) -> EDS23_W { EDS23_W::new(self) } #[doc = "Bit 24 - Event detected 24"] #[inline(always)] #[must_use] - pub fn eds24(&mut self) -> EDS24_W<24> { + pub fn eds24(&mut self) -> EDS24_W { EDS24_W::new(self) } #[doc = "Bit 25 - Event detected 25"] #[inline(always)] #[must_use] - pub fn eds25(&mut self) -> EDS25_W<25> { + pub fn eds25(&mut self) -> EDS25_W { EDS25_W::new(self) } #[doc = "Bit 26 - Event detected 26"] #[inline(always)] #[must_use] - pub fn eds26(&mut self) -> EDS26_W<26> { + pub fn eds26(&mut self) -> EDS26_W { EDS26_W::new(self) } #[doc = "Bit 27 - Event detected 27"] #[inline(always)] #[must_use] - pub fn eds27(&mut self) -> EDS27_W<27> { + pub fn eds27(&mut self) -> EDS27_W { EDS27_W::new(self) } #[doc = "Bit 28 - Event detected 28"] #[inline(always)] #[must_use] - pub fn eds28(&mut self) -> EDS28_W<28> { + pub fn eds28(&mut self) -> EDS28_W { EDS28_W::new(self) } #[doc = "Bit 29 - Event detected 29"] #[inline(always)] #[must_use] - pub fn eds29(&mut self) -> EDS29_W<29> { + pub fn eds29(&mut self) -> EDS29_W { EDS29_W::new(self) } #[doc = "Bit 30 - Event detected 30"] #[inline(always)] #[must_use] - pub fn eds30(&mut self) -> EDS30_W<30> { + pub fn eds30(&mut self) -> EDS30_W { EDS30_W::new(self) } #[doc = "Bit 31 - Event detected 31"] #[inline(always)] #[must_use] - pub fn eds31(&mut self) -> EDS31_W<31> { + pub fn eds31(&mut self) -> EDS31_W { EDS31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Event Detect Status 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpeds0](index.html) module"] +#[doc = "GPIO Pin Event Detect Status 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpeds0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpeds0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPEDS0_SPEC; impl crate::RegisterSpec for GPEDS0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpeds0::R](R) reader structure"] -impl crate::Readable for GPEDS0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpeds0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpeds0::R`](R) reader structure"] +impl crate::Readable for GPEDS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpeds0::W`](W) writer structure"] impl crate::Writable for GPEDS0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gpio/gpeds1.rs b/crates/bcm2711-lpa/src/gpio/gpeds1.rs index d233308..a9f835c 100644 --- a/crates/bcm2711-lpa/src/gpio/gpeds1.rs +++ b/crates/bcm2711-lpa/src/gpio/gpeds1.rs @@ -1,143 +1,111 @@ #[doc = "Register `GPEDS1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPEDS1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EDS32` reader - Event detected 32"] -pub type EDS32_R = crate::BitReader; +pub type EDS32_R = crate::BitReader; #[doc = "Field `EDS32` writer - Event detected 32"] -pub type EDS32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS32_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS33` reader - Event detected 33"] -pub type EDS33_R = crate::BitReader; +pub type EDS33_R = crate::BitReader; #[doc = "Field `EDS33` writer - Event detected 33"] -pub type EDS33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS33_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS34` reader - Event detected 34"] -pub type EDS34_R = crate::BitReader; +pub type EDS34_R = crate::BitReader; #[doc = "Field `EDS34` writer - Event detected 34"] -pub type EDS34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS34_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS35` reader - Event detected 35"] -pub type EDS35_R = crate::BitReader; +pub type EDS35_R = crate::BitReader; #[doc = "Field `EDS35` writer - Event detected 35"] -pub type EDS35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS35_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS36` reader - Event detected 36"] -pub type EDS36_R = crate::BitReader; +pub type EDS36_R = crate::BitReader; #[doc = "Field `EDS36` writer - Event detected 36"] -pub type EDS36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS36_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS37` reader - Event detected 37"] -pub type EDS37_R = crate::BitReader; +pub type EDS37_R = crate::BitReader; #[doc = "Field `EDS37` writer - Event detected 37"] -pub type EDS37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS37_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS38` reader - Event detected 38"] -pub type EDS38_R = crate::BitReader; +pub type EDS38_R = crate::BitReader; #[doc = "Field `EDS38` writer - Event detected 38"] -pub type EDS38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS38_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS39` reader - Event detected 39"] -pub type EDS39_R = crate::BitReader; +pub type EDS39_R = crate::BitReader; #[doc = "Field `EDS39` writer - Event detected 39"] -pub type EDS39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS39_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS40` reader - Event detected 40"] -pub type EDS40_R = crate::BitReader; +pub type EDS40_R = crate::BitReader; #[doc = "Field `EDS40` writer - Event detected 40"] -pub type EDS40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS40_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS41` reader - Event detected 41"] -pub type EDS41_R = crate::BitReader; +pub type EDS41_R = crate::BitReader; #[doc = "Field `EDS41` writer - Event detected 41"] -pub type EDS41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS41_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS42` reader - Event detected 42"] -pub type EDS42_R = crate::BitReader; +pub type EDS42_R = crate::BitReader; #[doc = "Field `EDS42` writer - Event detected 42"] -pub type EDS42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS42_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS43` reader - Event detected 43"] -pub type EDS43_R = crate::BitReader; +pub type EDS43_R = crate::BitReader; #[doc = "Field `EDS43` writer - Event detected 43"] -pub type EDS43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS43_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS44` reader - Event detected 44"] -pub type EDS44_R = crate::BitReader; +pub type EDS44_R = crate::BitReader; #[doc = "Field `EDS44` writer - Event detected 44"] -pub type EDS44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS44_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS45` reader - Event detected 45"] -pub type EDS45_R = crate::BitReader; +pub type EDS45_R = crate::BitReader; #[doc = "Field `EDS45` writer - Event detected 45"] -pub type EDS45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS45_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS46` reader - Event detected 46"] -pub type EDS46_R = crate::BitReader; +pub type EDS46_R = crate::BitReader; #[doc = "Field `EDS46` writer - Event detected 46"] -pub type EDS46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS46_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS47` reader - Event detected 47"] -pub type EDS47_R = crate::BitReader; +pub type EDS47_R = crate::BitReader; #[doc = "Field `EDS47` writer - Event detected 47"] -pub type EDS47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS47_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS48` reader - Event detected 48"] -pub type EDS48_R = crate::BitReader; +pub type EDS48_R = crate::BitReader; #[doc = "Field `EDS48` writer - Event detected 48"] -pub type EDS48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS48_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS49` reader - Event detected 49"] -pub type EDS49_R = crate::BitReader; +pub type EDS49_R = crate::BitReader; #[doc = "Field `EDS49` writer - Event detected 49"] -pub type EDS49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS49_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS50` reader - Event detected 50"] -pub type EDS50_R = crate::BitReader; +pub type EDS50_R = crate::BitReader; #[doc = "Field `EDS50` writer - Event detected 50"] -pub type EDS50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS50_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS51` reader - Event detected 51"] -pub type EDS51_R = crate::BitReader; +pub type EDS51_R = crate::BitReader; #[doc = "Field `EDS51` writer - Event detected 51"] -pub type EDS51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS51_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS52` reader - Event detected 52"] -pub type EDS52_R = crate::BitReader; +pub type EDS52_R = crate::BitReader; #[doc = "Field `EDS52` writer - Event detected 52"] -pub type EDS52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS52_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS53` reader - Event detected 53"] -pub type EDS53_R = crate::BitReader; +pub type EDS53_R = crate::BitReader; #[doc = "Field `EDS53` writer - Event detected 53"] -pub type EDS53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS53_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS54` reader - Event detected 54"] -pub type EDS54_R = crate::BitReader; +pub type EDS54_R = crate::BitReader; #[doc = "Field `EDS54` writer - Event detected 54"] -pub type EDS54_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS54_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS55` reader - Event detected 55"] -pub type EDS55_R = crate::BitReader; +pub type EDS55_R = crate::BitReader; #[doc = "Field `EDS55` writer - Event detected 55"] -pub type EDS55_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS55_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS56` reader - Event detected 56"] -pub type EDS56_R = crate::BitReader; +pub type EDS56_R = crate::BitReader; #[doc = "Field `EDS56` writer - Event detected 56"] -pub type EDS56_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS56_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS57` reader - Event detected 57"] -pub type EDS57_R = crate::BitReader; +pub type EDS57_R = crate::BitReader; #[doc = "Field `EDS57` writer - Event detected 57"] -pub type EDS57_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS57_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Event detected 32"] #[inline(always)] @@ -270,182 +238,220 @@ impl R { EDS57_R::new(((self.bits >> 25) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPEDS1") + .field("eds32", &format_args!("{}", self.eds32().bit())) + .field("eds33", &format_args!("{}", self.eds33().bit())) + .field("eds34", &format_args!("{}", self.eds34().bit())) + .field("eds35", &format_args!("{}", self.eds35().bit())) + .field("eds36", &format_args!("{}", self.eds36().bit())) + .field("eds37", &format_args!("{}", self.eds37().bit())) + .field("eds38", &format_args!("{}", self.eds38().bit())) + .field("eds39", &format_args!("{}", self.eds39().bit())) + .field("eds40", &format_args!("{}", self.eds40().bit())) + .field("eds41", &format_args!("{}", self.eds41().bit())) + .field("eds42", &format_args!("{}", self.eds42().bit())) + .field("eds43", &format_args!("{}", self.eds43().bit())) + .field("eds44", &format_args!("{}", self.eds44().bit())) + .field("eds45", &format_args!("{}", self.eds45().bit())) + .field("eds46", &format_args!("{}", self.eds46().bit())) + .field("eds47", &format_args!("{}", self.eds47().bit())) + .field("eds48", &format_args!("{}", self.eds48().bit())) + .field("eds49", &format_args!("{}", self.eds49().bit())) + .field("eds50", &format_args!("{}", self.eds50().bit())) + .field("eds51", &format_args!("{}", self.eds51().bit())) + .field("eds52", &format_args!("{}", self.eds52().bit())) + .field("eds53", &format_args!("{}", self.eds53().bit())) + .field("eds54", &format_args!("{}", self.eds54().bit())) + .field("eds55", &format_args!("{}", self.eds55().bit())) + .field("eds56", &format_args!("{}", self.eds56().bit())) + .field("eds57", &format_args!("{}", self.eds57().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Event detected 32"] #[inline(always)] #[must_use] - pub fn eds32(&mut self) -> EDS32_W<0> { + pub fn eds32(&mut self) -> EDS32_W { EDS32_W::new(self) } #[doc = "Bit 1 - Event detected 33"] #[inline(always)] #[must_use] - pub fn eds33(&mut self) -> EDS33_W<1> { + pub fn eds33(&mut self) -> EDS33_W { EDS33_W::new(self) } #[doc = "Bit 2 - Event detected 34"] #[inline(always)] #[must_use] - pub fn eds34(&mut self) -> EDS34_W<2> { + pub fn eds34(&mut self) -> EDS34_W { EDS34_W::new(self) } #[doc = "Bit 3 - Event detected 35"] #[inline(always)] #[must_use] - pub fn eds35(&mut self) -> EDS35_W<3> { + pub fn eds35(&mut self) -> EDS35_W { EDS35_W::new(self) } #[doc = "Bit 4 - Event detected 36"] #[inline(always)] #[must_use] - pub fn eds36(&mut self) -> EDS36_W<4> { + pub fn eds36(&mut self) -> EDS36_W { EDS36_W::new(self) } #[doc = "Bit 5 - Event detected 37"] #[inline(always)] #[must_use] - pub fn eds37(&mut self) -> EDS37_W<5> { + pub fn eds37(&mut self) -> EDS37_W { EDS37_W::new(self) } #[doc = "Bit 6 - Event detected 38"] #[inline(always)] #[must_use] - pub fn eds38(&mut self) -> EDS38_W<6> { + pub fn eds38(&mut self) -> EDS38_W { EDS38_W::new(self) } #[doc = "Bit 7 - Event detected 39"] #[inline(always)] #[must_use] - pub fn eds39(&mut self) -> EDS39_W<7> { + pub fn eds39(&mut self) -> EDS39_W { EDS39_W::new(self) } #[doc = "Bit 8 - Event detected 40"] #[inline(always)] #[must_use] - pub fn eds40(&mut self) -> EDS40_W<8> { + pub fn eds40(&mut self) -> EDS40_W { EDS40_W::new(self) } #[doc = "Bit 9 - Event detected 41"] #[inline(always)] #[must_use] - pub fn eds41(&mut self) -> EDS41_W<9> { + pub fn eds41(&mut self) -> EDS41_W { EDS41_W::new(self) } #[doc = "Bit 10 - Event detected 42"] #[inline(always)] #[must_use] - pub fn eds42(&mut self) -> EDS42_W<10> { + pub fn eds42(&mut self) -> EDS42_W { EDS42_W::new(self) } #[doc = "Bit 11 - Event detected 43"] #[inline(always)] #[must_use] - pub fn eds43(&mut self) -> EDS43_W<11> { + pub fn eds43(&mut self) -> EDS43_W { EDS43_W::new(self) } #[doc = "Bit 12 - Event detected 44"] #[inline(always)] #[must_use] - pub fn eds44(&mut self) -> EDS44_W<12> { + pub fn eds44(&mut self) -> EDS44_W { EDS44_W::new(self) } #[doc = "Bit 13 - Event detected 45"] #[inline(always)] #[must_use] - pub fn eds45(&mut self) -> EDS45_W<13> { + pub fn eds45(&mut self) -> EDS45_W { EDS45_W::new(self) } #[doc = "Bit 14 - Event detected 46"] #[inline(always)] #[must_use] - pub fn eds46(&mut self) -> EDS46_W<14> { + pub fn eds46(&mut self) -> EDS46_W { EDS46_W::new(self) } #[doc = "Bit 15 - Event detected 47"] #[inline(always)] #[must_use] - pub fn eds47(&mut self) -> EDS47_W<15> { + pub fn eds47(&mut self) -> EDS47_W { EDS47_W::new(self) } #[doc = "Bit 16 - Event detected 48"] #[inline(always)] #[must_use] - pub fn eds48(&mut self) -> EDS48_W<16> { + pub fn eds48(&mut self) -> EDS48_W { EDS48_W::new(self) } #[doc = "Bit 17 - Event detected 49"] #[inline(always)] #[must_use] - pub fn eds49(&mut self) -> EDS49_W<17> { + pub fn eds49(&mut self) -> EDS49_W { EDS49_W::new(self) } #[doc = "Bit 18 - Event detected 50"] #[inline(always)] #[must_use] - pub fn eds50(&mut self) -> EDS50_W<18> { + pub fn eds50(&mut self) -> EDS50_W { EDS50_W::new(self) } #[doc = "Bit 19 - Event detected 51"] #[inline(always)] #[must_use] - pub fn eds51(&mut self) -> EDS51_W<19> { + pub fn eds51(&mut self) -> EDS51_W { EDS51_W::new(self) } #[doc = "Bit 20 - Event detected 52"] #[inline(always)] #[must_use] - pub fn eds52(&mut self) -> EDS52_W<20> { + pub fn eds52(&mut self) -> EDS52_W { EDS52_W::new(self) } #[doc = "Bit 21 - Event detected 53"] #[inline(always)] #[must_use] - pub fn eds53(&mut self) -> EDS53_W<21> { + pub fn eds53(&mut self) -> EDS53_W { EDS53_W::new(self) } #[doc = "Bit 22 - Event detected 54"] #[inline(always)] #[must_use] - pub fn eds54(&mut self) -> EDS54_W<22> { + pub fn eds54(&mut self) -> EDS54_W { EDS54_W::new(self) } #[doc = "Bit 23 - Event detected 55"] #[inline(always)] #[must_use] - pub fn eds55(&mut self) -> EDS55_W<23> { + pub fn eds55(&mut self) -> EDS55_W { EDS55_W::new(self) } #[doc = "Bit 24 - Event detected 56"] #[inline(always)] #[must_use] - pub fn eds56(&mut self) -> EDS56_W<24> { + pub fn eds56(&mut self) -> EDS56_W { EDS56_W::new(self) } #[doc = "Bit 25 - Event detected 57"] #[inline(always)] #[must_use] - pub fn eds57(&mut self) -> EDS57_W<25> { + pub fn eds57(&mut self) -> EDS57_W { EDS57_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Event Detect Status 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpeds1](index.html) module"] +#[doc = "GPIO Pin Event Detect Status 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpeds1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpeds1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPEDS1_SPEC; impl crate::RegisterSpec for GPEDS1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpeds1::R](R) reader structure"] -impl crate::Readable for GPEDS1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpeds1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpeds1::R`](R) reader structure"] +impl crate::Readable for GPEDS1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpeds1::W`](W) writer structure"] impl crate::Writable for GPEDS1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x03ff_ffff; } diff --git a/crates/bcm2711-lpa/src/gpio/gpfen0.rs b/crates/bcm2711-lpa/src/gpio/gpfen0.rs index 58ded22..abcf609 100644 --- a/crates/bcm2711-lpa/src/gpio/gpfen0.rs +++ b/crates/bcm2711-lpa/src/gpio/gpfen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPFEN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFEN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FEN0` reader - Falling edge enabled 0"] -pub type FEN0_R = crate::BitReader; +pub type FEN0_R = crate::BitReader; #[doc = "Field `FEN0` writer - Falling edge enabled 0"] -pub type FEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN1` reader - Falling edge enabled 1"] -pub type FEN1_R = crate::BitReader; +pub type FEN1_R = crate::BitReader; #[doc = "Field `FEN1` writer - Falling edge enabled 1"] -pub type FEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN2` reader - Falling edge enabled 2"] -pub type FEN2_R = crate::BitReader; +pub type FEN2_R = crate::BitReader; #[doc = "Field `FEN2` writer - Falling edge enabled 2"] -pub type FEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN3` reader - Falling edge enabled 3"] -pub type FEN3_R = crate::BitReader; +pub type FEN3_R = crate::BitReader; #[doc = "Field `FEN3` writer - Falling edge enabled 3"] -pub type FEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN4` reader - Falling edge enabled 4"] -pub type FEN4_R = crate::BitReader; +pub type FEN4_R = crate::BitReader; #[doc = "Field `FEN4` writer - Falling edge enabled 4"] -pub type FEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN5` reader - Falling edge enabled 5"] -pub type FEN5_R = crate::BitReader; +pub type FEN5_R = crate::BitReader; #[doc = "Field `FEN5` writer - Falling edge enabled 5"] -pub type FEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN6` reader - Falling edge enabled 6"] -pub type FEN6_R = crate::BitReader; +pub type FEN6_R = crate::BitReader; #[doc = "Field `FEN6` writer - Falling edge enabled 6"] -pub type FEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN7` reader - Falling edge enabled 7"] -pub type FEN7_R = crate::BitReader; +pub type FEN7_R = crate::BitReader; #[doc = "Field `FEN7` writer - Falling edge enabled 7"] -pub type FEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN8` reader - Falling edge enabled 8"] -pub type FEN8_R = crate::BitReader; +pub type FEN8_R = crate::BitReader; #[doc = "Field `FEN8` writer - Falling edge enabled 8"] -pub type FEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN9` reader - Falling edge enabled 9"] -pub type FEN9_R = crate::BitReader; +pub type FEN9_R = crate::BitReader; #[doc = "Field `FEN9` writer - Falling edge enabled 9"] -pub type FEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN10` reader - Falling edge enabled 10"] -pub type FEN10_R = crate::BitReader; +pub type FEN10_R = crate::BitReader; #[doc = "Field `FEN10` writer - Falling edge enabled 10"] -pub type FEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN11` reader - Falling edge enabled 11"] -pub type FEN11_R = crate::BitReader; +pub type FEN11_R = crate::BitReader; #[doc = "Field `FEN11` writer - Falling edge enabled 11"] -pub type FEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN12` reader - Falling edge enabled 12"] -pub type FEN12_R = crate::BitReader; +pub type FEN12_R = crate::BitReader; #[doc = "Field `FEN12` writer - Falling edge enabled 12"] -pub type FEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN13` reader - Falling edge enabled 13"] -pub type FEN13_R = crate::BitReader; +pub type FEN13_R = crate::BitReader; #[doc = "Field `FEN13` writer - Falling edge enabled 13"] -pub type FEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN14` reader - Falling edge enabled 14"] -pub type FEN14_R = crate::BitReader; +pub type FEN14_R = crate::BitReader; #[doc = "Field `FEN14` writer - Falling edge enabled 14"] -pub type FEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN15` reader - Falling edge enabled 15"] -pub type FEN15_R = crate::BitReader; +pub type FEN15_R = crate::BitReader; #[doc = "Field `FEN15` writer - Falling edge enabled 15"] -pub type FEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN16` reader - Falling edge enabled 16"] -pub type FEN16_R = crate::BitReader; +pub type FEN16_R = crate::BitReader; #[doc = "Field `FEN16` writer - Falling edge enabled 16"] -pub type FEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN17` reader - Falling edge enabled 17"] -pub type FEN17_R = crate::BitReader; +pub type FEN17_R = crate::BitReader; #[doc = "Field `FEN17` writer - Falling edge enabled 17"] -pub type FEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN18` reader - Falling edge enabled 18"] -pub type FEN18_R = crate::BitReader; +pub type FEN18_R = crate::BitReader; #[doc = "Field `FEN18` writer - Falling edge enabled 18"] -pub type FEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN19` reader - Falling edge enabled 19"] -pub type FEN19_R = crate::BitReader; +pub type FEN19_R = crate::BitReader; #[doc = "Field `FEN19` writer - Falling edge enabled 19"] -pub type FEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN20` reader - Falling edge enabled 20"] -pub type FEN20_R = crate::BitReader; +pub type FEN20_R = crate::BitReader; #[doc = "Field `FEN20` writer - Falling edge enabled 20"] -pub type FEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN21` reader - Falling edge enabled 21"] -pub type FEN21_R = crate::BitReader; +pub type FEN21_R = crate::BitReader; #[doc = "Field `FEN21` writer - Falling edge enabled 21"] -pub type FEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN22` reader - Falling edge enabled 22"] -pub type FEN22_R = crate::BitReader; +pub type FEN22_R = crate::BitReader; #[doc = "Field `FEN22` writer - Falling edge enabled 22"] -pub type FEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN23` reader - Falling edge enabled 23"] -pub type FEN23_R = crate::BitReader; +pub type FEN23_R = crate::BitReader; #[doc = "Field `FEN23` writer - Falling edge enabled 23"] -pub type FEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN24` reader - Falling edge enabled 24"] -pub type FEN24_R = crate::BitReader; +pub type FEN24_R = crate::BitReader; #[doc = "Field `FEN24` writer - Falling edge enabled 24"] -pub type FEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN25` reader - Falling edge enabled 25"] -pub type FEN25_R = crate::BitReader; +pub type FEN25_R = crate::BitReader; #[doc = "Field `FEN25` writer - Falling edge enabled 25"] -pub type FEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN26` reader - Falling edge enabled 26"] -pub type FEN26_R = crate::BitReader; +pub type FEN26_R = crate::BitReader; #[doc = "Field `FEN26` writer - Falling edge enabled 26"] -pub type FEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN27` reader - Falling edge enabled 27"] -pub type FEN27_R = crate::BitReader; +pub type FEN27_R = crate::BitReader; #[doc = "Field `FEN27` writer - Falling edge enabled 27"] -pub type FEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN28` reader - Falling edge enabled 28"] -pub type FEN28_R = crate::BitReader; +pub type FEN28_R = crate::BitReader; #[doc = "Field `FEN28` writer - Falling edge enabled 28"] -pub type FEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN29` reader - Falling edge enabled 29"] -pub type FEN29_R = crate::BitReader; +pub type FEN29_R = crate::BitReader; #[doc = "Field `FEN29` writer - Falling edge enabled 29"] -pub type FEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN30` reader - Falling edge enabled 30"] -pub type FEN30_R = crate::BitReader; +pub type FEN30_R = crate::BitReader; #[doc = "Field `FEN30` writer - Falling edge enabled 30"] -pub type FEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN31` reader - Falling edge enabled 31"] -pub type FEN31_R = crate::BitReader; +pub type FEN31_R = crate::BitReader; #[doc = "Field `FEN31` writer - Falling edge enabled 31"] -pub type FEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Falling edge enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { FEN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFEN0") + .field("fen0", &format_args!("{}", self.fen0().bit())) + .field("fen1", &format_args!("{}", self.fen1().bit())) + .field("fen2", &format_args!("{}", self.fen2().bit())) + .field("fen3", &format_args!("{}", self.fen3().bit())) + .field("fen4", &format_args!("{}", self.fen4().bit())) + .field("fen5", &format_args!("{}", self.fen5().bit())) + .field("fen6", &format_args!("{}", self.fen6().bit())) + .field("fen7", &format_args!("{}", self.fen7().bit())) + .field("fen8", &format_args!("{}", self.fen8().bit())) + .field("fen9", &format_args!("{}", self.fen9().bit())) + .field("fen10", &format_args!("{}", self.fen10().bit())) + .field("fen11", &format_args!("{}", self.fen11().bit())) + .field("fen12", &format_args!("{}", self.fen12().bit())) + .field("fen13", &format_args!("{}", self.fen13().bit())) + .field("fen14", &format_args!("{}", self.fen14().bit())) + .field("fen15", &format_args!("{}", self.fen15().bit())) + .field("fen16", &format_args!("{}", self.fen16().bit())) + .field("fen17", &format_args!("{}", self.fen17().bit())) + .field("fen18", &format_args!("{}", self.fen18().bit())) + .field("fen19", &format_args!("{}", self.fen19().bit())) + .field("fen20", &format_args!("{}", self.fen20().bit())) + .field("fen21", &format_args!("{}", self.fen21().bit())) + .field("fen22", &format_args!("{}", self.fen22().bit())) + .field("fen23", &format_args!("{}", self.fen23().bit())) + .field("fen24", &format_args!("{}", self.fen24().bit())) + .field("fen25", &format_args!("{}", self.fen25().bit())) + .field("fen26", &format_args!("{}", self.fen26().bit())) + .field("fen27", &format_args!("{}", self.fen27().bit())) + .field("fen28", &format_args!("{}", self.fen28().bit())) + .field("fen29", &format_args!("{}", self.fen29().bit())) + .field("fen30", &format_args!("{}", self.fen30().bit())) + .field("fen31", &format_args!("{}", self.fen31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Falling edge enabled 0"] #[inline(always)] #[must_use] - pub fn fen0(&mut self) -> FEN0_W<0> { + pub fn fen0(&mut self) -> FEN0_W { FEN0_W::new(self) } #[doc = "Bit 1 - Falling edge enabled 1"] #[inline(always)] #[must_use] - pub fn fen1(&mut self) -> FEN1_W<1> { + pub fn fen1(&mut self) -> FEN1_W { FEN1_W::new(self) } #[doc = "Bit 2 - Falling edge enabled 2"] #[inline(always)] #[must_use] - pub fn fen2(&mut self) -> FEN2_W<2> { + pub fn fen2(&mut self) -> FEN2_W { FEN2_W::new(self) } #[doc = "Bit 3 - Falling edge enabled 3"] #[inline(always)] #[must_use] - pub fn fen3(&mut self) -> FEN3_W<3> { + pub fn fen3(&mut self) -> FEN3_W { FEN3_W::new(self) } #[doc = "Bit 4 - Falling edge enabled 4"] #[inline(always)] #[must_use] - pub fn fen4(&mut self) -> FEN4_W<4> { + pub fn fen4(&mut self) -> FEN4_W { FEN4_W::new(self) } #[doc = "Bit 5 - Falling edge enabled 5"] #[inline(always)] #[must_use] - pub fn fen5(&mut self) -> FEN5_W<5> { + pub fn fen5(&mut self) -> FEN5_W { FEN5_W::new(self) } #[doc = "Bit 6 - Falling edge enabled 6"] #[inline(always)] #[must_use] - pub fn fen6(&mut self) -> FEN6_W<6> { + pub fn fen6(&mut self) -> FEN6_W { FEN6_W::new(self) } #[doc = "Bit 7 - Falling edge enabled 7"] #[inline(always)] #[must_use] - pub fn fen7(&mut self) -> FEN7_W<7> { + pub fn fen7(&mut self) -> FEN7_W { FEN7_W::new(self) } #[doc = "Bit 8 - Falling edge enabled 8"] #[inline(always)] #[must_use] - pub fn fen8(&mut self) -> FEN8_W<8> { + pub fn fen8(&mut self) -> FEN8_W { FEN8_W::new(self) } #[doc = "Bit 9 - Falling edge enabled 9"] #[inline(always)] #[must_use] - pub fn fen9(&mut self) -> FEN9_W<9> { + pub fn fen9(&mut self) -> FEN9_W { FEN9_W::new(self) } #[doc = "Bit 10 - Falling edge enabled 10"] #[inline(always)] #[must_use] - pub fn fen10(&mut self) -> FEN10_W<10> { + pub fn fen10(&mut self) -> FEN10_W { FEN10_W::new(self) } #[doc = "Bit 11 - Falling edge enabled 11"] #[inline(always)] #[must_use] - pub fn fen11(&mut self) -> FEN11_W<11> { + pub fn fen11(&mut self) -> FEN11_W { FEN11_W::new(self) } #[doc = "Bit 12 - Falling edge enabled 12"] #[inline(always)] #[must_use] - pub fn fen12(&mut self) -> FEN12_W<12> { + pub fn fen12(&mut self) -> FEN12_W { FEN12_W::new(self) } #[doc = "Bit 13 - Falling edge enabled 13"] #[inline(always)] #[must_use] - pub fn fen13(&mut self) -> FEN13_W<13> { + pub fn fen13(&mut self) -> FEN13_W { FEN13_W::new(self) } #[doc = "Bit 14 - Falling edge enabled 14"] #[inline(always)] #[must_use] - pub fn fen14(&mut self) -> FEN14_W<14> { + pub fn fen14(&mut self) -> FEN14_W { FEN14_W::new(self) } #[doc = "Bit 15 - Falling edge enabled 15"] #[inline(always)] #[must_use] - pub fn fen15(&mut self) -> FEN15_W<15> { + pub fn fen15(&mut self) -> FEN15_W { FEN15_W::new(self) } #[doc = "Bit 16 - Falling edge enabled 16"] #[inline(always)] #[must_use] - pub fn fen16(&mut self) -> FEN16_W<16> { + pub fn fen16(&mut self) -> FEN16_W { FEN16_W::new(self) } #[doc = "Bit 17 - Falling edge enabled 17"] #[inline(always)] #[must_use] - pub fn fen17(&mut self) -> FEN17_W<17> { + pub fn fen17(&mut self) -> FEN17_W { FEN17_W::new(self) } #[doc = "Bit 18 - Falling edge enabled 18"] #[inline(always)] #[must_use] - pub fn fen18(&mut self) -> FEN18_W<18> { + pub fn fen18(&mut self) -> FEN18_W { FEN18_W::new(self) } #[doc = "Bit 19 - Falling edge enabled 19"] #[inline(always)] #[must_use] - pub fn fen19(&mut self) -> FEN19_W<19> { + pub fn fen19(&mut self) -> FEN19_W { FEN19_W::new(self) } #[doc = "Bit 20 - Falling edge enabled 20"] #[inline(always)] #[must_use] - pub fn fen20(&mut self) -> FEN20_W<20> { + pub fn fen20(&mut self) -> FEN20_W { FEN20_W::new(self) } #[doc = "Bit 21 - Falling edge enabled 21"] #[inline(always)] #[must_use] - pub fn fen21(&mut self) -> FEN21_W<21> { + pub fn fen21(&mut self) -> FEN21_W { FEN21_W::new(self) } #[doc = "Bit 22 - Falling edge enabled 22"] #[inline(always)] #[must_use] - pub fn fen22(&mut self) -> FEN22_W<22> { + pub fn fen22(&mut self) -> FEN22_W { FEN22_W::new(self) } #[doc = "Bit 23 - Falling edge enabled 23"] #[inline(always)] #[must_use] - pub fn fen23(&mut self) -> FEN23_W<23> { + pub fn fen23(&mut self) -> FEN23_W { FEN23_W::new(self) } #[doc = "Bit 24 - Falling edge enabled 24"] #[inline(always)] #[must_use] - pub fn fen24(&mut self) -> FEN24_W<24> { + pub fn fen24(&mut self) -> FEN24_W { FEN24_W::new(self) } #[doc = "Bit 25 - Falling edge enabled 25"] #[inline(always)] #[must_use] - pub fn fen25(&mut self) -> FEN25_W<25> { + pub fn fen25(&mut self) -> FEN25_W { FEN25_W::new(self) } #[doc = "Bit 26 - Falling edge enabled 26"] #[inline(always)] #[must_use] - pub fn fen26(&mut self) -> FEN26_W<26> { + pub fn fen26(&mut self) -> FEN26_W { FEN26_W::new(self) } #[doc = "Bit 27 - Falling edge enabled 27"] #[inline(always)] #[must_use] - pub fn fen27(&mut self) -> FEN27_W<27> { + pub fn fen27(&mut self) -> FEN27_W { FEN27_W::new(self) } #[doc = "Bit 28 - Falling edge enabled 28"] #[inline(always)] #[must_use] - pub fn fen28(&mut self) -> FEN28_W<28> { + pub fn fen28(&mut self) -> FEN28_W { FEN28_W::new(self) } #[doc = "Bit 29 - Falling edge enabled 29"] #[inline(always)] #[must_use] - pub fn fen29(&mut self) -> FEN29_W<29> { + pub fn fen29(&mut self) -> FEN29_W { FEN29_W::new(self) } #[doc = "Bit 30 - Falling edge enabled 30"] #[inline(always)] #[must_use] - pub fn fen30(&mut self) -> FEN30_W<30> { + pub fn fen30(&mut self) -> FEN30_W { FEN30_W::new(self) } #[doc = "Bit 31 - Falling edge enabled 31"] #[inline(always)] #[must_use] - pub fn fen31(&mut self) -> FEN31_W<31> { + pub fn fen31(&mut self) -> FEN31_W { FEN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Falling Edge Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfen0](index.html) module"] +#[doc = "GPIO Pin Falling Edge Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFEN0_SPEC; impl crate::RegisterSpec for GPFEN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfen0::R](R) reader structure"] -impl crate::Readable for GPFEN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfen0::R`](R) reader structure"] +impl crate::Readable for GPFEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfen0::W`](W) writer structure"] impl crate::Writable for GPFEN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpfen1.rs b/crates/bcm2711-lpa/src/gpio/gpfen1.rs index 9d3519c..becc880 100644 --- a/crates/bcm2711-lpa/src/gpio/gpfen1.rs +++ b/crates/bcm2711-lpa/src/gpio/gpfen1.rs @@ -1,143 +1,111 @@ #[doc = "Register `GPFEN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFEN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FEN32` reader - Falling edge enabled 32"] -pub type FEN32_R = crate::BitReader; +pub type FEN32_R = crate::BitReader; #[doc = "Field `FEN32` writer - Falling edge enabled 32"] -pub type FEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN33` reader - Falling edge enabled 33"] -pub type FEN33_R = crate::BitReader; +pub type FEN33_R = crate::BitReader; #[doc = "Field `FEN33` writer - Falling edge enabled 33"] -pub type FEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN34` reader - Falling edge enabled 34"] -pub type FEN34_R = crate::BitReader; +pub type FEN34_R = crate::BitReader; #[doc = "Field `FEN34` writer - Falling edge enabled 34"] -pub type FEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN35` reader - Falling edge enabled 35"] -pub type FEN35_R = crate::BitReader; +pub type FEN35_R = crate::BitReader; #[doc = "Field `FEN35` writer - Falling edge enabled 35"] -pub type FEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN36` reader - Falling edge enabled 36"] -pub type FEN36_R = crate::BitReader; +pub type FEN36_R = crate::BitReader; #[doc = "Field `FEN36` writer - Falling edge enabled 36"] -pub type FEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN37` reader - Falling edge enabled 37"] -pub type FEN37_R = crate::BitReader; +pub type FEN37_R = crate::BitReader; #[doc = "Field `FEN37` writer - Falling edge enabled 37"] -pub type FEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN38` reader - Falling edge enabled 38"] -pub type FEN38_R = crate::BitReader; +pub type FEN38_R = crate::BitReader; #[doc = "Field `FEN38` writer - Falling edge enabled 38"] -pub type FEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN39` reader - Falling edge enabled 39"] -pub type FEN39_R = crate::BitReader; +pub type FEN39_R = crate::BitReader; #[doc = "Field `FEN39` writer - Falling edge enabled 39"] -pub type FEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN40` reader - Falling edge enabled 40"] -pub type FEN40_R = crate::BitReader; +pub type FEN40_R = crate::BitReader; #[doc = "Field `FEN40` writer - Falling edge enabled 40"] -pub type FEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN41` reader - Falling edge enabled 41"] -pub type FEN41_R = crate::BitReader; +pub type FEN41_R = crate::BitReader; #[doc = "Field `FEN41` writer - Falling edge enabled 41"] -pub type FEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN42` reader - Falling edge enabled 42"] -pub type FEN42_R = crate::BitReader; +pub type FEN42_R = crate::BitReader; #[doc = "Field `FEN42` writer - Falling edge enabled 42"] -pub type FEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN43` reader - Falling edge enabled 43"] -pub type FEN43_R = crate::BitReader; +pub type FEN43_R = crate::BitReader; #[doc = "Field `FEN43` writer - Falling edge enabled 43"] -pub type FEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN44` reader - Falling edge enabled 44"] -pub type FEN44_R = crate::BitReader; +pub type FEN44_R = crate::BitReader; #[doc = "Field `FEN44` writer - Falling edge enabled 44"] -pub type FEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN45` reader - Falling edge enabled 45"] -pub type FEN45_R = crate::BitReader; +pub type FEN45_R = crate::BitReader; #[doc = "Field `FEN45` writer - Falling edge enabled 45"] -pub type FEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN46` reader - Falling edge enabled 46"] -pub type FEN46_R = crate::BitReader; +pub type FEN46_R = crate::BitReader; #[doc = "Field `FEN46` writer - Falling edge enabled 46"] -pub type FEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN47` reader - Falling edge enabled 47"] -pub type FEN47_R = crate::BitReader; +pub type FEN47_R = crate::BitReader; #[doc = "Field `FEN47` writer - Falling edge enabled 47"] -pub type FEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN48` reader - Falling edge enabled 48"] -pub type FEN48_R = crate::BitReader; +pub type FEN48_R = crate::BitReader; #[doc = "Field `FEN48` writer - Falling edge enabled 48"] -pub type FEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN49` reader - Falling edge enabled 49"] -pub type FEN49_R = crate::BitReader; +pub type FEN49_R = crate::BitReader; #[doc = "Field `FEN49` writer - Falling edge enabled 49"] -pub type FEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN50` reader - Falling edge enabled 50"] -pub type FEN50_R = crate::BitReader; +pub type FEN50_R = crate::BitReader; #[doc = "Field `FEN50` writer - Falling edge enabled 50"] -pub type FEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN51` reader - Falling edge enabled 51"] -pub type FEN51_R = crate::BitReader; +pub type FEN51_R = crate::BitReader; #[doc = "Field `FEN51` writer - Falling edge enabled 51"] -pub type FEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN52` reader - Falling edge enabled 52"] -pub type FEN52_R = crate::BitReader; +pub type FEN52_R = crate::BitReader; #[doc = "Field `FEN52` writer - Falling edge enabled 52"] -pub type FEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN53` reader - Falling edge enabled 53"] -pub type FEN53_R = crate::BitReader; +pub type FEN53_R = crate::BitReader; #[doc = "Field `FEN53` writer - Falling edge enabled 53"] -pub type FEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN54` reader - Falling edge enabled 54"] -pub type FEN54_R = crate::BitReader; +pub type FEN54_R = crate::BitReader; #[doc = "Field `FEN54` writer - Falling edge enabled 54"] -pub type FEN54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN54_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN55` reader - Falling edge enabled 55"] -pub type FEN55_R = crate::BitReader; +pub type FEN55_R = crate::BitReader; #[doc = "Field `FEN55` writer - Falling edge enabled 55"] -pub type FEN55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN55_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN56` reader - Falling edge enabled 56"] -pub type FEN56_R = crate::BitReader; +pub type FEN56_R = crate::BitReader; #[doc = "Field `FEN56` writer - Falling edge enabled 56"] -pub type FEN56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN57` reader - Falling edge enabled 57"] -pub type FEN57_R = crate::BitReader; +pub type FEN57_R = crate::BitReader; #[doc = "Field `FEN57` writer - Falling edge enabled 57"] -pub type FEN57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Falling edge enabled 32"] #[inline(always)] @@ -270,182 +238,220 @@ impl R { FEN57_R::new(((self.bits >> 25) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFEN1") + .field("fen32", &format_args!("{}", self.fen32().bit())) + .field("fen33", &format_args!("{}", self.fen33().bit())) + .field("fen34", &format_args!("{}", self.fen34().bit())) + .field("fen35", &format_args!("{}", self.fen35().bit())) + .field("fen36", &format_args!("{}", self.fen36().bit())) + .field("fen37", &format_args!("{}", self.fen37().bit())) + .field("fen38", &format_args!("{}", self.fen38().bit())) + .field("fen39", &format_args!("{}", self.fen39().bit())) + .field("fen40", &format_args!("{}", self.fen40().bit())) + .field("fen41", &format_args!("{}", self.fen41().bit())) + .field("fen42", &format_args!("{}", self.fen42().bit())) + .field("fen43", &format_args!("{}", self.fen43().bit())) + .field("fen44", &format_args!("{}", self.fen44().bit())) + .field("fen45", &format_args!("{}", self.fen45().bit())) + .field("fen46", &format_args!("{}", self.fen46().bit())) + .field("fen47", &format_args!("{}", self.fen47().bit())) + .field("fen48", &format_args!("{}", self.fen48().bit())) + .field("fen49", &format_args!("{}", self.fen49().bit())) + .field("fen50", &format_args!("{}", self.fen50().bit())) + .field("fen51", &format_args!("{}", self.fen51().bit())) + .field("fen52", &format_args!("{}", self.fen52().bit())) + .field("fen53", &format_args!("{}", self.fen53().bit())) + .field("fen54", &format_args!("{}", self.fen54().bit())) + .field("fen55", &format_args!("{}", self.fen55().bit())) + .field("fen56", &format_args!("{}", self.fen56().bit())) + .field("fen57", &format_args!("{}", self.fen57().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Falling edge enabled 32"] #[inline(always)] #[must_use] - pub fn fen32(&mut self) -> FEN32_W<0> { + pub fn fen32(&mut self) -> FEN32_W { FEN32_W::new(self) } #[doc = "Bit 1 - Falling edge enabled 33"] #[inline(always)] #[must_use] - pub fn fen33(&mut self) -> FEN33_W<1> { + pub fn fen33(&mut self) -> FEN33_W { FEN33_W::new(self) } #[doc = "Bit 2 - Falling edge enabled 34"] #[inline(always)] #[must_use] - pub fn fen34(&mut self) -> FEN34_W<2> { + pub fn fen34(&mut self) -> FEN34_W { FEN34_W::new(self) } #[doc = "Bit 3 - Falling edge enabled 35"] #[inline(always)] #[must_use] - pub fn fen35(&mut self) -> FEN35_W<3> { + pub fn fen35(&mut self) -> FEN35_W { FEN35_W::new(self) } #[doc = "Bit 4 - Falling edge enabled 36"] #[inline(always)] #[must_use] - pub fn fen36(&mut self) -> FEN36_W<4> { + pub fn fen36(&mut self) -> FEN36_W { FEN36_W::new(self) } #[doc = "Bit 5 - Falling edge enabled 37"] #[inline(always)] #[must_use] - pub fn fen37(&mut self) -> FEN37_W<5> { + pub fn fen37(&mut self) -> FEN37_W { FEN37_W::new(self) } #[doc = "Bit 6 - Falling edge enabled 38"] #[inline(always)] #[must_use] - pub fn fen38(&mut self) -> FEN38_W<6> { + pub fn fen38(&mut self) -> FEN38_W { FEN38_W::new(self) } #[doc = "Bit 7 - Falling edge enabled 39"] #[inline(always)] #[must_use] - pub fn fen39(&mut self) -> FEN39_W<7> { + pub fn fen39(&mut self) -> FEN39_W { FEN39_W::new(self) } #[doc = "Bit 8 - Falling edge enabled 40"] #[inline(always)] #[must_use] - pub fn fen40(&mut self) -> FEN40_W<8> { + pub fn fen40(&mut self) -> FEN40_W { FEN40_W::new(self) } #[doc = "Bit 9 - Falling edge enabled 41"] #[inline(always)] #[must_use] - pub fn fen41(&mut self) -> FEN41_W<9> { + pub fn fen41(&mut self) -> FEN41_W { FEN41_W::new(self) } #[doc = "Bit 10 - Falling edge enabled 42"] #[inline(always)] #[must_use] - pub fn fen42(&mut self) -> FEN42_W<10> { + pub fn fen42(&mut self) -> FEN42_W { FEN42_W::new(self) } #[doc = "Bit 11 - Falling edge enabled 43"] #[inline(always)] #[must_use] - pub fn fen43(&mut self) -> FEN43_W<11> { + pub fn fen43(&mut self) -> FEN43_W { FEN43_W::new(self) } #[doc = "Bit 12 - Falling edge enabled 44"] #[inline(always)] #[must_use] - pub fn fen44(&mut self) -> FEN44_W<12> { + pub fn fen44(&mut self) -> FEN44_W { FEN44_W::new(self) } #[doc = "Bit 13 - Falling edge enabled 45"] #[inline(always)] #[must_use] - pub fn fen45(&mut self) -> FEN45_W<13> { + pub fn fen45(&mut self) -> FEN45_W { FEN45_W::new(self) } #[doc = "Bit 14 - Falling edge enabled 46"] #[inline(always)] #[must_use] - pub fn fen46(&mut self) -> FEN46_W<14> { + pub fn fen46(&mut self) -> FEN46_W { FEN46_W::new(self) } #[doc = "Bit 15 - Falling edge enabled 47"] #[inline(always)] #[must_use] - pub fn fen47(&mut self) -> FEN47_W<15> { + pub fn fen47(&mut self) -> FEN47_W { FEN47_W::new(self) } #[doc = "Bit 16 - Falling edge enabled 48"] #[inline(always)] #[must_use] - pub fn fen48(&mut self) -> FEN48_W<16> { + pub fn fen48(&mut self) -> FEN48_W { FEN48_W::new(self) } #[doc = "Bit 17 - Falling edge enabled 49"] #[inline(always)] #[must_use] - pub fn fen49(&mut self) -> FEN49_W<17> { + pub fn fen49(&mut self) -> FEN49_W { FEN49_W::new(self) } #[doc = "Bit 18 - Falling edge enabled 50"] #[inline(always)] #[must_use] - pub fn fen50(&mut self) -> FEN50_W<18> { + pub fn fen50(&mut self) -> FEN50_W { FEN50_W::new(self) } #[doc = "Bit 19 - Falling edge enabled 51"] #[inline(always)] #[must_use] - pub fn fen51(&mut self) -> FEN51_W<19> { + pub fn fen51(&mut self) -> FEN51_W { FEN51_W::new(self) } #[doc = "Bit 20 - Falling edge enabled 52"] #[inline(always)] #[must_use] - pub fn fen52(&mut self) -> FEN52_W<20> { + pub fn fen52(&mut self) -> FEN52_W { FEN52_W::new(self) } #[doc = "Bit 21 - Falling edge enabled 53"] #[inline(always)] #[must_use] - pub fn fen53(&mut self) -> FEN53_W<21> { + pub fn fen53(&mut self) -> FEN53_W { FEN53_W::new(self) } #[doc = "Bit 22 - Falling edge enabled 54"] #[inline(always)] #[must_use] - pub fn fen54(&mut self) -> FEN54_W<22> { + pub fn fen54(&mut self) -> FEN54_W { FEN54_W::new(self) } #[doc = "Bit 23 - Falling edge enabled 55"] #[inline(always)] #[must_use] - pub fn fen55(&mut self) -> FEN55_W<23> { + pub fn fen55(&mut self) -> FEN55_W { FEN55_W::new(self) } #[doc = "Bit 24 - Falling edge enabled 56"] #[inline(always)] #[must_use] - pub fn fen56(&mut self) -> FEN56_W<24> { + pub fn fen56(&mut self) -> FEN56_W { FEN56_W::new(self) } #[doc = "Bit 25 - Falling edge enabled 57"] #[inline(always)] #[must_use] - pub fn fen57(&mut self) -> FEN57_W<25> { + pub fn fen57(&mut self) -> FEN57_W { FEN57_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Falling Edge Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfen1](index.html) module"] +#[doc = "GPIO Pin Falling Edge Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFEN1_SPEC; impl crate::RegisterSpec for GPFEN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfen1::R](R) reader structure"] -impl crate::Readable for GPFEN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfen1::R`](R) reader structure"] +impl crate::Readable for GPFEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfen1::W`](W) writer structure"] impl crate::Writable for GPFEN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpfsel0.rs b/crates/bcm2711-lpa/src/gpio/gpfsel0.rs index 2d16733..f418e9e 100644 --- a/crates/bcm2711-lpa/src/gpio/gpfsel0.rs +++ b/crates/bcm2711-lpa/src/gpio/gpfsel0.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL0` reader - Function Select 0"] -pub type FSEL0_R = crate::FieldReader; +pub type FSEL0_R = crate::FieldReader; #[doc = "Function Select 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL0_A { + type Ux = u8; +} impl FSEL0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL0_A { + pub const fn variant(&self) -> FSEL0_A { match self.bits { 0 => FSEL0_A::INPUT, 1 => FSEL0_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL0_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL0_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL0_A::OUTPUT } - #[doc = "Checks if the value of the field is `SDA0`"] + #[doc = "Pin is connected to SDA0"] #[inline(always)] pub fn is_sda0(&self) -> bool { *self == FSEL0_A::SDA0 } - #[doc = "Checks if the value of the field is `SA5`"] + #[doc = "Pin is connected to SA5"] #[inline(always)] pub fn is_sa5(&self) -> bool { *self == FSEL0_A::SA5 } - #[doc = "Checks if the value of the field is `PCLK`"] + #[doc = "Pin is connected to PCLK"] #[inline(always)] pub fn is_pclk(&self) -> bool { *self == FSEL0_A::PCLK } - #[doc = "Checks if the value of the field is `SPI3_CE0_N`"] + #[doc = "Pin is connected to SPI3_CE0_N"] #[inline(always)] pub fn is_spi3_ce0_n(&self) -> bool { *self == FSEL0_A::SPI3_CE0_N } - #[doc = "Checks if the value of the field is `TXD2`"] + #[doc = "Pin is connected to TXD2"] #[inline(always)] pub fn is_txd2(&self) -> bool { *self == FSEL0_A::TXD2 } - #[doc = "Checks if the value of the field is `SDA6`"] + #[doc = "Pin is connected to SDA6"] #[inline(always)] pub fn is_sda6(&self) -> bool { *self == FSEL0_A::SDA6 } } #[doc = "Field `FSEL0` writer - Function Select 0"] -pub type FSEL0_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL0_A, 3, O>; -impl<'a, const O: u8> FSEL0_W<'a, O> { +pub type FSEL0_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL0_A>; +impl<'a, REG, const O: u8> FSEL0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL0_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL0_A::OUTPUT) } #[doc = "Pin is connected to SDA0"] #[inline(always)] - pub fn sda0(self) -> &'a mut W { + pub fn sda0(self) -> &'a mut crate::W { self.variant(FSEL0_A::SDA0) } #[doc = "Pin is connected to SA5"] #[inline(always)] - pub fn sa5(self) -> &'a mut W { + pub fn sa5(self) -> &'a mut crate::W { self.variant(FSEL0_A::SA5) } #[doc = "Pin is connected to PCLK"] #[inline(always)] - pub fn pclk(self) -> &'a mut W { + pub fn pclk(self) -> &'a mut crate::W { self.variant(FSEL0_A::PCLK) } #[doc = "Pin is connected to SPI3_CE0_N"] #[inline(always)] - pub fn spi3_ce0_n(self) -> &'a mut W { + pub fn spi3_ce0_n(self) -> &'a mut crate::W { self.variant(FSEL0_A::SPI3_CE0_N) } #[doc = "Pin is connected to TXD2"] #[inline(always)] - pub fn txd2(self) -> &'a mut W { + pub fn txd2(self) -> &'a mut crate::W { self.variant(FSEL0_A::TXD2) } #[doc = "Pin is connected to SDA6"] #[inline(always)] - pub fn sda6(self) -> &'a mut W { + pub fn sda6(self) -> &'a mut crate::W { self.variant(FSEL0_A::SDA6) } } #[doc = "Field `FSEL1` reader - Function Select 1"] -pub type FSEL1_R = crate::FieldReader; +pub type FSEL1_R = crate::FieldReader; #[doc = "Function Select 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL1_A { + type Ux = u8; +} impl FSEL1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL1_A { + pub const fn variant(&self) -> FSEL1_A { match self.bits { 0 => FSEL1_A::INPUT, 1 => FSEL1_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL1_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL1_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL1_A::OUTPUT } - #[doc = "Checks if the value of the field is `SCL0`"] + #[doc = "Pin is connected to SCL0"] #[inline(always)] pub fn is_scl0(&self) -> bool { *self == FSEL1_A::SCL0 } - #[doc = "Checks if the value of the field is `SA4`"] + #[doc = "Pin is connected to SA4"] #[inline(always)] pub fn is_sa4(&self) -> bool { *self == FSEL1_A::SA4 } - #[doc = "Checks if the value of the field is `DE`"] + #[doc = "Pin is connected to DE"] #[inline(always)] pub fn is_de(&self) -> bool { *self == FSEL1_A::DE } - #[doc = "Checks if the value of the field is `SPI3_MISO`"] + #[doc = "Pin is connected to SPI3_MISO"] #[inline(always)] pub fn is_spi3_miso(&self) -> bool { *self == FSEL1_A::SPI3_MISO } - #[doc = "Checks if the value of the field is `RXD2`"] + #[doc = "Pin is connected to RXD2"] #[inline(always)] pub fn is_rxd2(&self) -> bool { *self == FSEL1_A::RXD2 } - #[doc = "Checks if the value of the field is `SCL6`"] + #[doc = "Pin is connected to SCL6"] #[inline(always)] pub fn is_scl6(&self) -> bool { *self == FSEL1_A::SCL6 } } #[doc = "Field `FSEL1` writer - Function Select 1"] -pub type FSEL1_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL1_A, 3, O>; -impl<'a, const O: u8> FSEL1_W<'a, O> { +pub type FSEL1_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL1_A>; +impl<'a, REG, const O: u8> FSEL1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL1_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL1_A::OUTPUT) } #[doc = "Pin is connected to SCL0"] #[inline(always)] - pub fn scl0(self) -> &'a mut W { + pub fn scl0(self) -> &'a mut crate::W { self.variant(FSEL1_A::SCL0) } #[doc = "Pin is connected to SA4"] #[inline(always)] - pub fn sa4(self) -> &'a mut W { + pub fn sa4(self) -> &'a mut crate::W { self.variant(FSEL1_A::SA4) } #[doc = "Pin is connected to DE"] #[inline(always)] - pub fn de(self) -> &'a mut W { + pub fn de(self) -> &'a mut crate::W { self.variant(FSEL1_A::DE) } #[doc = "Pin is connected to SPI3_MISO"] #[inline(always)] - pub fn spi3_miso(self) -> &'a mut W { + pub fn spi3_miso(self) -> &'a mut crate::W { self.variant(FSEL1_A::SPI3_MISO) } #[doc = "Pin is connected to RXD2"] #[inline(always)] - pub fn rxd2(self) -> &'a mut W { + pub fn rxd2(self) -> &'a mut crate::W { self.variant(FSEL1_A::RXD2) } #[doc = "Pin is connected to SCL6"] #[inline(always)] - pub fn scl6(self) -> &'a mut W { + pub fn scl6(self) -> &'a mut crate::W { self.variant(FSEL1_A::SCL6) } } #[doc = "Field `FSEL2` reader - Function Select 2"] -pub type FSEL2_R = crate::FieldReader; +pub type FSEL2_R = crate::FieldReader; #[doc = "Function Select 2"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL2_A { + type Ux = u8; +} impl FSEL2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL2_A { + pub const fn variant(&self) -> FSEL2_A { match self.bits { 0 => FSEL2_A::INPUT, 1 => FSEL2_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL2_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL2_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL2_A::OUTPUT } - #[doc = "Checks if the value of the field is `SDA1`"] + #[doc = "Pin is connected to SDA1"] #[inline(always)] pub fn is_sda1(&self) -> bool { *self == FSEL2_A::SDA1 } - #[doc = "Checks if the value of the field is `SA3`"] + #[doc = "Pin is connected to SA3"] #[inline(always)] pub fn is_sa3(&self) -> bool { *self == FSEL2_A::SA3 } - #[doc = "Checks if the value of the field is `LCD_VSYNC`"] + #[doc = "Pin is connected to LCD_VSYNC"] #[inline(always)] pub fn is_lcd_vsync(&self) -> bool { *self == FSEL2_A::LCD_VSYNC } - #[doc = "Checks if the value of the field is `SPI3_MOSI`"] + #[doc = "Pin is connected to SPI3_MOSI"] #[inline(always)] pub fn is_spi3_mosi(&self) -> bool { *self == FSEL2_A::SPI3_MOSI } - #[doc = "Checks if the value of the field is `CTS2`"] + #[doc = "Pin is connected to CTS2"] #[inline(always)] pub fn is_cts2(&self) -> bool { *self == FSEL2_A::CTS2 } - #[doc = "Checks if the value of the field is `SDA3`"] + #[doc = "Pin is connected to SDA3"] #[inline(always)] pub fn is_sda3(&self) -> bool { *self == FSEL2_A::SDA3 } } #[doc = "Field `FSEL2` writer - Function Select 2"] -pub type FSEL2_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL2_A, 3, O>; -impl<'a, const O: u8> FSEL2_W<'a, O> { +pub type FSEL2_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL2_A>; +impl<'a, REG, const O: u8> FSEL2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL2_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL2_A::OUTPUT) } #[doc = "Pin is connected to SDA1"] #[inline(always)] - pub fn sda1(self) -> &'a mut W { + pub fn sda1(self) -> &'a mut crate::W { self.variant(FSEL2_A::SDA1) } #[doc = "Pin is connected to SA3"] #[inline(always)] - pub fn sa3(self) -> &'a mut W { + pub fn sa3(self) -> &'a mut crate::W { self.variant(FSEL2_A::SA3) } #[doc = "Pin is connected to LCD_VSYNC"] #[inline(always)] - pub fn lcd_vsync(self) -> &'a mut W { + pub fn lcd_vsync(self) -> &'a mut crate::W { self.variant(FSEL2_A::LCD_VSYNC) } #[doc = "Pin is connected to SPI3_MOSI"] #[inline(always)] - pub fn spi3_mosi(self) -> &'a mut W { + pub fn spi3_mosi(self) -> &'a mut crate::W { self.variant(FSEL2_A::SPI3_MOSI) } #[doc = "Pin is connected to CTS2"] #[inline(always)] - pub fn cts2(self) -> &'a mut W { + pub fn cts2(self) -> &'a mut crate::W { self.variant(FSEL2_A::CTS2) } #[doc = "Pin is connected to SDA3"] #[inline(always)] - pub fn sda3(self) -> &'a mut W { + pub fn sda3(self) -> &'a mut crate::W { self.variant(FSEL2_A::SDA3) } } #[doc = "Field `FSEL3` reader - Function Select 3"] -pub type FSEL3_R = crate::FieldReader; +pub type FSEL3_R = crate::FieldReader; #[doc = "Function Select 3"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL3_A { + type Ux = u8; +} impl FSEL3_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL3_A { + pub const fn variant(&self) -> FSEL3_A { match self.bits { 0 => FSEL3_A::INPUT, 1 => FSEL3_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL3_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL3_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL3_A::OUTPUT } - #[doc = "Checks if the value of the field is `SCL1`"] + #[doc = "Pin is connected to SCL1"] #[inline(always)] pub fn is_scl1(&self) -> bool { *self == FSEL3_A::SCL1 } - #[doc = "Checks if the value of the field is `SA2`"] + #[doc = "Pin is connected to SA2"] #[inline(always)] pub fn is_sa2(&self) -> bool { *self == FSEL3_A::SA2 } - #[doc = "Checks if the value of the field is `LCD_HSYNC`"] + #[doc = "Pin is connected to LCD_HSYNC"] #[inline(always)] pub fn is_lcd_hsync(&self) -> bool { *self == FSEL3_A::LCD_HSYNC } - #[doc = "Checks if the value of the field is `SPI3_SCLK`"] + #[doc = "Pin is connected to SPI3_SCLK"] #[inline(always)] pub fn is_spi3_sclk(&self) -> bool { *self == FSEL3_A::SPI3_SCLK } - #[doc = "Checks if the value of the field is `RTS2`"] + #[doc = "Pin is connected to RTS2"] #[inline(always)] pub fn is_rts2(&self) -> bool { *self == FSEL3_A::RTS2 } - #[doc = "Checks if the value of the field is `SCL3`"] + #[doc = "Pin is connected to SCL3"] #[inline(always)] pub fn is_scl3(&self) -> bool { *self == FSEL3_A::SCL3 } } #[doc = "Field `FSEL3` writer - Function Select 3"] -pub type FSEL3_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL3_A, 3, O>; -impl<'a, const O: u8> FSEL3_W<'a, O> { +pub type FSEL3_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL3_A>; +impl<'a, REG, const O: u8> FSEL3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL3_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL3_A::OUTPUT) } #[doc = "Pin is connected to SCL1"] #[inline(always)] - pub fn scl1(self) -> &'a mut W { + pub fn scl1(self) -> &'a mut crate::W { self.variant(FSEL3_A::SCL1) } #[doc = "Pin is connected to SA2"] #[inline(always)] - pub fn sa2(self) -> &'a mut W { + pub fn sa2(self) -> &'a mut crate::W { self.variant(FSEL3_A::SA2) } #[doc = "Pin is connected to LCD_HSYNC"] #[inline(always)] - pub fn lcd_hsync(self) -> &'a mut W { + pub fn lcd_hsync(self) -> &'a mut crate::W { self.variant(FSEL3_A::LCD_HSYNC) } #[doc = "Pin is connected to SPI3_SCLK"] #[inline(always)] - pub fn spi3_sclk(self) -> &'a mut W { + pub fn spi3_sclk(self) -> &'a mut crate::W { self.variant(FSEL3_A::SPI3_SCLK) } #[doc = "Pin is connected to RTS2"] #[inline(always)] - pub fn rts2(self) -> &'a mut W { + pub fn rts2(self) -> &'a mut crate::W { self.variant(FSEL3_A::RTS2) } #[doc = "Pin is connected to SCL3"] #[inline(always)] - pub fn scl3(self) -> &'a mut W { + pub fn scl3(self) -> &'a mut crate::W { self.variant(FSEL3_A::SCL3) } } #[doc = "Field `FSEL4` reader - Function Select 4"] -pub type FSEL4_R = crate::FieldReader; +pub type FSEL4_R = crate::FieldReader; #[doc = "Function Select 4"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL4_A { + type Ux = u8; +} impl FSEL4_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL4_A { + pub const fn variant(&self) -> FSEL4_A { match self.bits { 0 => FSEL4_A::INPUT, 1 => FSEL4_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL4_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL4_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL4_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK0`"] + #[doc = "Pin is connected to GPCLK0"] #[inline(always)] pub fn is_gpclk0(&self) -> bool { *self == FSEL4_A::GPCLK0 } - #[doc = "Checks if the value of the field is `SA1`"] + #[doc = "Pin is connected to SA1"] #[inline(always)] pub fn is_sa1(&self) -> bool { *self == FSEL4_A::SA1 } - #[doc = "Checks if the value of the field is `DPI_D0`"] + #[doc = "Pin is connected to DPI_D0"] #[inline(always)] pub fn is_dpi_d0(&self) -> bool { *self == FSEL4_A::DPI_D0 } - #[doc = "Checks if the value of the field is `SPI4_CE0_N`"] + #[doc = "Pin is connected to SPI4_CE0_N"] #[inline(always)] pub fn is_spi4_ce0_n(&self) -> bool { *self == FSEL4_A::SPI4_CE0_N } - #[doc = "Checks if the value of the field is `TXD3`"] + #[doc = "Pin is connected to TXD3"] #[inline(always)] pub fn is_txd3(&self) -> bool { *self == FSEL4_A::TXD3 } - #[doc = "Checks if the value of the field is `SDA3`"] + #[doc = "Pin is connected to SDA3"] #[inline(always)] pub fn is_sda3(&self) -> bool { *self == FSEL4_A::SDA3 } } #[doc = "Field `FSEL4` writer - Function Select 4"] -pub type FSEL4_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL4_A, 3, O>; -impl<'a, const O: u8> FSEL4_W<'a, O> { +pub type FSEL4_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL4_A>; +impl<'a, REG, const O: u8> FSEL4_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL4_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL4_A::OUTPUT) } #[doc = "Pin is connected to GPCLK0"] #[inline(always)] - pub fn gpclk0(self) -> &'a mut W { + pub fn gpclk0(self) -> &'a mut crate::W { self.variant(FSEL4_A::GPCLK0) } #[doc = "Pin is connected to SA1"] #[inline(always)] - pub fn sa1(self) -> &'a mut W { + pub fn sa1(self) -> &'a mut crate::W { self.variant(FSEL4_A::SA1) } #[doc = "Pin is connected to DPI_D0"] #[inline(always)] - pub fn dpi_d0(self) -> &'a mut W { + pub fn dpi_d0(self) -> &'a mut crate::W { self.variant(FSEL4_A::DPI_D0) } #[doc = "Pin is connected to SPI4_CE0_N"] #[inline(always)] - pub fn spi4_ce0_n(self) -> &'a mut W { + pub fn spi4_ce0_n(self) -> &'a mut crate::W { self.variant(FSEL4_A::SPI4_CE0_N) } #[doc = "Pin is connected to TXD3"] #[inline(always)] - pub fn txd3(self) -> &'a mut W { + pub fn txd3(self) -> &'a mut crate::W { self.variant(FSEL4_A::TXD3) } #[doc = "Pin is connected to SDA3"] #[inline(always)] - pub fn sda3(self) -> &'a mut W { + pub fn sda3(self) -> &'a mut crate::W { self.variant(FSEL4_A::SDA3) } } #[doc = "Field `FSEL5` reader - Function Select 5"] -pub type FSEL5_R = crate::FieldReader; +pub type FSEL5_R = crate::FieldReader; #[doc = "Function Select 5"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL5_A { + type Ux = u8; +} impl FSEL5_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL5_A { + pub const fn variant(&self) -> FSEL5_A { match self.bits { 0 => FSEL5_A::INPUT, 1 => FSEL5_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL5_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL5_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL5_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK1`"] + #[doc = "Pin is connected to GPCLK1"] #[inline(always)] pub fn is_gpclk1(&self) -> bool { *self == FSEL5_A::GPCLK1 } - #[doc = "Checks if the value of the field is `SA0`"] + #[doc = "Pin is connected to SA0"] #[inline(always)] pub fn is_sa0(&self) -> bool { *self == FSEL5_A::SA0 } - #[doc = "Checks if the value of the field is `DPI_D1`"] + #[doc = "Pin is connected to DPI_D1"] #[inline(always)] pub fn is_dpi_d1(&self) -> bool { *self == FSEL5_A::DPI_D1 } - #[doc = "Checks if the value of the field is `SPI4_MISO`"] + #[doc = "Pin is connected to SPI4_MISO"] #[inline(always)] pub fn is_spi4_miso(&self) -> bool { *self == FSEL5_A::SPI4_MISO } - #[doc = "Checks if the value of the field is `RXD3`"] + #[doc = "Pin is connected to RXD3"] #[inline(always)] pub fn is_rxd3(&self) -> bool { *self == FSEL5_A::RXD3 } - #[doc = "Checks if the value of the field is `SCL3`"] + #[doc = "Pin is connected to SCL3"] #[inline(always)] pub fn is_scl3(&self) -> bool { *self == FSEL5_A::SCL3 } } #[doc = "Field `FSEL5` writer - Function Select 5"] -pub type FSEL5_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL5_A, 3, O>; -impl<'a, const O: u8> FSEL5_W<'a, O> { +pub type FSEL5_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL5_A>; +impl<'a, REG, const O: u8> FSEL5_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL5_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL5_A::OUTPUT) } #[doc = "Pin is connected to GPCLK1"] #[inline(always)] - pub fn gpclk1(self) -> &'a mut W { + pub fn gpclk1(self) -> &'a mut crate::W { self.variant(FSEL5_A::GPCLK1) } #[doc = "Pin is connected to SA0"] #[inline(always)] - pub fn sa0(self) -> &'a mut W { + pub fn sa0(self) -> &'a mut crate::W { self.variant(FSEL5_A::SA0) } #[doc = "Pin is connected to DPI_D1"] #[inline(always)] - pub fn dpi_d1(self) -> &'a mut W { + pub fn dpi_d1(self) -> &'a mut crate::W { self.variant(FSEL5_A::DPI_D1) } #[doc = "Pin is connected to SPI4_MISO"] #[inline(always)] - pub fn spi4_miso(self) -> &'a mut W { + pub fn spi4_miso(self) -> &'a mut crate::W { self.variant(FSEL5_A::SPI4_MISO) } #[doc = "Pin is connected to RXD3"] #[inline(always)] - pub fn rxd3(self) -> &'a mut W { + pub fn rxd3(self) -> &'a mut crate::W { self.variant(FSEL5_A::RXD3) } #[doc = "Pin is connected to SCL3"] #[inline(always)] - pub fn scl3(self) -> &'a mut W { + pub fn scl3(self) -> &'a mut crate::W { self.variant(FSEL5_A::SCL3) } } #[doc = "Field `FSEL6` reader - Function Select 6"] -pub type FSEL6_R = crate::FieldReader; +pub type FSEL6_R = crate::FieldReader; #[doc = "Function Select 6"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL6_A { + type Ux = u8; +} impl FSEL6_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL6_A { + pub const fn variant(&self) -> FSEL6_A { match self.bits { 0 => FSEL6_A::INPUT, 1 => FSEL6_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL6_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL6_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL6_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK2`"] + #[doc = "Pin is connected to GPCLK2"] #[inline(always)] pub fn is_gpclk2(&self) -> bool { *self == FSEL6_A::GPCLK2 } - #[doc = "Checks if the value of the field is `SOE_N`"] + #[doc = "Pin is connected to SOE_N"] #[inline(always)] pub fn is_soe_n(&self) -> bool { *self == FSEL6_A::SOE_N } - #[doc = "Checks if the value of the field is `DPI_D2`"] + #[doc = "Pin is connected to DPI_D2"] #[inline(always)] pub fn is_dpi_d2(&self) -> bool { *self == FSEL6_A::DPI_D2 } - #[doc = "Checks if the value of the field is `SPI4_MOSI`"] + #[doc = "Pin is connected to SPI4_MOSI"] #[inline(always)] pub fn is_spi4_mosi(&self) -> bool { *self == FSEL6_A::SPI4_MOSI } - #[doc = "Checks if the value of the field is `CTS3`"] + #[doc = "Pin is connected to CTS3"] #[inline(always)] pub fn is_cts3(&self) -> bool { *self == FSEL6_A::CTS3 } - #[doc = "Checks if the value of the field is `SDA4`"] + #[doc = "Pin is connected to SDA4"] #[inline(always)] pub fn is_sda4(&self) -> bool { *self == FSEL6_A::SDA4 } } #[doc = "Field `FSEL6` writer - Function Select 6"] -pub type FSEL6_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL6_A, 3, O>; -impl<'a, const O: u8> FSEL6_W<'a, O> { +pub type FSEL6_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL6_A>; +impl<'a, REG, const O: u8> FSEL6_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL6_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL6_A::OUTPUT) } #[doc = "Pin is connected to GPCLK2"] #[inline(always)] - pub fn gpclk2(self) -> &'a mut W { + pub fn gpclk2(self) -> &'a mut crate::W { self.variant(FSEL6_A::GPCLK2) } #[doc = "Pin is connected to SOE_N"] #[inline(always)] - pub fn soe_n(self) -> &'a mut W { + pub fn soe_n(self) -> &'a mut crate::W { self.variant(FSEL6_A::SOE_N) } #[doc = "Pin is connected to DPI_D2"] #[inline(always)] - pub fn dpi_d2(self) -> &'a mut W { + pub fn dpi_d2(self) -> &'a mut crate::W { self.variant(FSEL6_A::DPI_D2) } #[doc = "Pin is connected to SPI4_MOSI"] #[inline(always)] - pub fn spi4_mosi(self) -> &'a mut W { + pub fn spi4_mosi(self) -> &'a mut crate::W { self.variant(FSEL6_A::SPI4_MOSI) } #[doc = "Pin is connected to CTS3"] #[inline(always)] - pub fn cts3(self) -> &'a mut W { + pub fn cts3(self) -> &'a mut crate::W { self.variant(FSEL6_A::CTS3) } #[doc = "Pin is connected to SDA4"] #[inline(always)] - pub fn sda4(self) -> &'a mut W { + pub fn sda4(self) -> &'a mut crate::W { self.variant(FSEL6_A::SDA4) } } #[doc = "Field `FSEL7` reader - Function Select 7"] -pub type FSEL7_R = crate::FieldReader; +pub type FSEL7_R = crate::FieldReader; #[doc = "Function Select 7"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL7_A { + type Ux = u8; +} impl FSEL7_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL7_A { + pub const fn variant(&self) -> FSEL7_A { match self.bits { 0 => FSEL7_A::INPUT, 1 => FSEL7_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL7_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL7_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL7_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_CE1_N`"] + #[doc = "Pin is connected to SPI0_CE1_N"] #[inline(always)] pub fn is_spi0_ce1_n(&self) -> bool { *self == FSEL7_A::SPI0_CE1_N } - #[doc = "Checks if the value of the field is `SWE_N`"] + #[doc = "Pin is connected to SWE_N"] #[inline(always)] pub fn is_swe_n(&self) -> bool { *self == FSEL7_A::SWE_N } - #[doc = "Checks if the value of the field is `DPI_D3`"] + #[doc = "Pin is connected to DPI_D3"] #[inline(always)] pub fn is_dpi_d3(&self) -> bool { *self == FSEL7_A::DPI_D3 } - #[doc = "Checks if the value of the field is `SPI4_SCLK`"] + #[doc = "Pin is connected to SPI4_SCLK"] #[inline(always)] pub fn is_spi4_sclk(&self) -> bool { *self == FSEL7_A::SPI4_SCLK } - #[doc = "Checks if the value of the field is `RTS3`"] + #[doc = "Pin is connected to RTS3"] #[inline(always)] pub fn is_rts3(&self) -> bool { *self == FSEL7_A::RTS3 } - #[doc = "Checks if the value of the field is `SCL4`"] + #[doc = "Pin is connected to SCL4"] #[inline(always)] pub fn is_scl4(&self) -> bool { *self == FSEL7_A::SCL4 } } #[doc = "Field `FSEL7` writer - Function Select 7"] -pub type FSEL7_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL7_A, 3, O>; -impl<'a, const O: u8> FSEL7_W<'a, O> { +pub type FSEL7_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL7_A>; +impl<'a, REG, const O: u8> FSEL7_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL7_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL7_A::OUTPUT) } #[doc = "Pin is connected to SPI0_CE1_N"] #[inline(always)] - pub fn spi0_ce1_n(self) -> &'a mut W { + pub fn spi0_ce1_n(self) -> &'a mut crate::W { self.variant(FSEL7_A::SPI0_CE1_N) } #[doc = "Pin is connected to SWE_N"] #[inline(always)] - pub fn swe_n(self) -> &'a mut W { + pub fn swe_n(self) -> &'a mut crate::W { self.variant(FSEL7_A::SWE_N) } #[doc = "Pin is connected to DPI_D3"] #[inline(always)] - pub fn dpi_d3(self) -> &'a mut W { + pub fn dpi_d3(self) -> &'a mut crate::W { self.variant(FSEL7_A::DPI_D3) } #[doc = "Pin is connected to SPI4_SCLK"] #[inline(always)] - pub fn spi4_sclk(self) -> &'a mut W { + pub fn spi4_sclk(self) -> &'a mut crate::W { self.variant(FSEL7_A::SPI4_SCLK) } #[doc = "Pin is connected to RTS3"] #[inline(always)] - pub fn rts3(self) -> &'a mut W { + pub fn rts3(self) -> &'a mut crate::W { self.variant(FSEL7_A::RTS3) } #[doc = "Pin is connected to SCL4"] #[inline(always)] - pub fn scl4(self) -> &'a mut W { + pub fn scl4(self) -> &'a mut crate::W { self.variant(FSEL7_A::SCL4) } } #[doc = "Field `FSEL8` reader - Function Select 8"] -pub type FSEL8_R = crate::FieldReader; +pub type FSEL8_R = crate::FieldReader; #[doc = "Function Select 8"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL8_A { + type Ux = u8; +} impl FSEL8_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL8_A { + pub const fn variant(&self) -> FSEL8_A { match self.bits { 0 => FSEL8_A::INPUT, 1 => FSEL8_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL8_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL8_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL8_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_CE0_N`"] + #[doc = "Pin is connected to SPI0_CE0_N"] #[inline(always)] pub fn is_spi0_ce0_n(&self) -> bool { *self == FSEL8_A::SPI0_CE0_N } - #[doc = "Checks if the value of the field is `SD0`"] + #[doc = "Pin is connected to SD0"] #[inline(always)] pub fn is_sd0(&self) -> bool { *self == FSEL8_A::SD0 } - #[doc = "Checks if the value of the field is `DPI_D4`"] + #[doc = "Pin is connected to DPI_D4"] #[inline(always)] pub fn is_dpi_d4(&self) -> bool { *self == FSEL8_A::DPI_D4 } - #[doc = "Checks if the value of the field is `BSCSL_CE_N`"] + #[doc = "Pin is connected to BSCSL_CE_N"] #[inline(always)] pub fn is_bscsl_ce_n(&self) -> bool { *self == FSEL8_A::BSCSL_CE_N } - #[doc = "Checks if the value of the field is `TXD4`"] + #[doc = "Pin is connected to TXD4"] #[inline(always)] pub fn is_txd4(&self) -> bool { *self == FSEL8_A::TXD4 } - #[doc = "Checks if the value of the field is `SDA4`"] + #[doc = "Pin is connected to SDA4"] #[inline(always)] pub fn is_sda4(&self) -> bool { *self == FSEL8_A::SDA4 } } #[doc = "Field `FSEL8` writer - Function Select 8"] -pub type FSEL8_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL8_A, 3, O>; -impl<'a, const O: u8> FSEL8_W<'a, O> { +pub type FSEL8_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL8_A>; +impl<'a, REG, const O: u8> FSEL8_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL8_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL8_A::OUTPUT) } #[doc = "Pin is connected to SPI0_CE0_N"] #[inline(always)] - pub fn spi0_ce0_n(self) -> &'a mut W { + pub fn spi0_ce0_n(self) -> &'a mut crate::W { self.variant(FSEL8_A::SPI0_CE0_N) } #[doc = "Pin is connected to SD0"] #[inline(always)] - pub fn sd0(self) -> &'a mut W { + pub fn sd0(self) -> &'a mut crate::W { self.variant(FSEL8_A::SD0) } #[doc = "Pin is connected to DPI_D4"] #[inline(always)] - pub fn dpi_d4(self) -> &'a mut W { + pub fn dpi_d4(self) -> &'a mut crate::W { self.variant(FSEL8_A::DPI_D4) } #[doc = "Pin is connected to BSCSL_CE_N"] #[inline(always)] - pub fn bscsl_ce_n(self) -> &'a mut W { + pub fn bscsl_ce_n(self) -> &'a mut crate::W { self.variant(FSEL8_A::BSCSL_CE_N) } #[doc = "Pin is connected to TXD4"] #[inline(always)] - pub fn txd4(self) -> &'a mut W { + pub fn txd4(self) -> &'a mut crate::W { self.variant(FSEL8_A::TXD4) } #[doc = "Pin is connected to SDA4"] #[inline(always)] - pub fn sda4(self) -> &'a mut W { + pub fn sda4(self) -> &'a mut crate::W { self.variant(FSEL8_A::SDA4) } } #[doc = "Field `FSEL9` reader - Function Select 9"] -pub type FSEL9_R = crate::FieldReader; +pub type FSEL9_R = crate::FieldReader; #[doc = "Function Select 9"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL9_A { + type Ux = u8; +} impl FSEL9_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL9_A { + pub const fn variant(&self) -> FSEL9_A { match self.bits { 0 => FSEL9_A::INPUT, 1 => FSEL9_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL9_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL9_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL9_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_MISO`"] + #[doc = "Pin is connected to SPI0_MISO"] #[inline(always)] pub fn is_spi0_miso(&self) -> bool { *self == FSEL9_A::SPI0_MISO } - #[doc = "Checks if the value of the field is `SD1`"] + #[doc = "Pin is connected to SD1"] #[inline(always)] pub fn is_sd1(&self) -> bool { *self == FSEL9_A::SD1 } - #[doc = "Checks if the value of the field is `DPI_D5`"] + #[doc = "Pin is connected to DPI_D5"] #[inline(always)] pub fn is_dpi_d5(&self) -> bool { *self == FSEL9_A::DPI_D5 } - #[doc = "Checks if the value of the field is `BSCSL_MISO`"] + #[doc = "Pin is connected to BSCSL_MISO"] #[inline(always)] pub fn is_bscsl_miso(&self) -> bool { *self == FSEL9_A::BSCSL_MISO } - #[doc = "Checks if the value of the field is `RXD4`"] + #[doc = "Pin is connected to RXD4"] #[inline(always)] pub fn is_rxd4(&self) -> bool { *self == FSEL9_A::RXD4 } - #[doc = "Checks if the value of the field is `SCL4`"] + #[doc = "Pin is connected to SCL4"] #[inline(always)] pub fn is_scl4(&self) -> bool { *self == FSEL9_A::SCL4 } } #[doc = "Field `FSEL9` writer - Function Select 9"] -pub type FSEL9_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL9_A, 3, O>; -impl<'a, const O: u8> FSEL9_W<'a, O> { +pub type FSEL9_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL9_A>; +impl<'a, REG, const O: u8> FSEL9_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL9_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL9_A::OUTPUT) } #[doc = "Pin is connected to SPI0_MISO"] #[inline(always)] - pub fn spi0_miso(self) -> &'a mut W { + pub fn spi0_miso(self) -> &'a mut crate::W { self.variant(FSEL9_A::SPI0_MISO) } #[doc = "Pin is connected to SD1"] #[inline(always)] - pub fn sd1(self) -> &'a mut W { + pub fn sd1(self) -> &'a mut crate::W { self.variant(FSEL9_A::SD1) } #[doc = "Pin is connected to DPI_D5"] #[inline(always)] - pub fn dpi_d5(self) -> &'a mut W { + pub fn dpi_d5(self) -> &'a mut crate::W { self.variant(FSEL9_A::DPI_D5) } #[doc = "Pin is connected to BSCSL_MISO"] #[inline(always)] - pub fn bscsl_miso(self) -> &'a mut W { + pub fn bscsl_miso(self) -> &'a mut crate::W { self.variant(FSEL9_A::BSCSL_MISO) } #[doc = "Pin is connected to RXD4"] #[inline(always)] - pub fn rxd4(self) -> &'a mut W { + pub fn rxd4(self) -> &'a mut crate::W { self.variant(FSEL9_A::RXD4) } #[doc = "Pin is connected to SCL4"] #[inline(always)] - pub fn scl4(self) -> &'a mut W { + pub fn scl4(self) -> &'a mut crate::W { self.variant(FSEL9_A::SCL4) } } @@ -1396,86 +1424,108 @@ impl R { FSEL9_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL0") + .field("fsel0", &format_args!("{}", self.fsel0().bits())) + .field("fsel1", &format_args!("{}", self.fsel1().bits())) + .field("fsel2", &format_args!("{}", self.fsel2().bits())) + .field("fsel3", &format_args!("{}", self.fsel3().bits())) + .field("fsel4", &format_args!("{}", self.fsel4().bits())) + .field("fsel5", &format_args!("{}", self.fsel5().bits())) + .field("fsel6", &format_args!("{}", self.fsel6().bits())) + .field("fsel7", &format_args!("{}", self.fsel7().bits())) + .field("fsel8", &format_args!("{}", self.fsel8().bits())) + .field("fsel9", &format_args!("{}", self.fsel9().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 0"] #[inline(always)] #[must_use] - pub fn fsel0(&mut self) -> FSEL0_W<0> { + pub fn fsel0(&mut self) -> FSEL0_W { FSEL0_W::new(self) } #[doc = "Bits 3:5 - Function Select 1"] #[inline(always)] #[must_use] - pub fn fsel1(&mut self) -> FSEL1_W<3> { + pub fn fsel1(&mut self) -> FSEL1_W { FSEL1_W::new(self) } #[doc = "Bits 6:8 - Function Select 2"] #[inline(always)] #[must_use] - pub fn fsel2(&mut self) -> FSEL2_W<6> { + pub fn fsel2(&mut self) -> FSEL2_W { FSEL2_W::new(self) } #[doc = "Bits 9:11 - Function Select 3"] #[inline(always)] #[must_use] - pub fn fsel3(&mut self) -> FSEL3_W<9> { + pub fn fsel3(&mut self) -> FSEL3_W { FSEL3_W::new(self) } #[doc = "Bits 12:14 - Function Select 4"] #[inline(always)] #[must_use] - pub fn fsel4(&mut self) -> FSEL4_W<12> { + pub fn fsel4(&mut self) -> FSEL4_W { FSEL4_W::new(self) } #[doc = "Bits 15:17 - Function Select 5"] #[inline(always)] #[must_use] - pub fn fsel5(&mut self) -> FSEL5_W<15> { + pub fn fsel5(&mut self) -> FSEL5_W { FSEL5_W::new(self) } #[doc = "Bits 18:20 - Function Select 6"] #[inline(always)] #[must_use] - pub fn fsel6(&mut self) -> FSEL6_W<18> { + pub fn fsel6(&mut self) -> FSEL6_W { FSEL6_W::new(self) } #[doc = "Bits 21:23 - Function Select 7"] #[inline(always)] #[must_use] - pub fn fsel7(&mut self) -> FSEL7_W<21> { + pub fn fsel7(&mut self) -> FSEL7_W { FSEL7_W::new(self) } #[doc = "Bits 24:26 - Function Select 8"] #[inline(always)] #[must_use] - pub fn fsel8(&mut self) -> FSEL8_W<24> { + pub fn fsel8(&mut self) -> FSEL8_W { FSEL8_W::new(self) } #[doc = "Bits 27:29 - Function Select 9"] #[inline(always)] #[must_use] - pub fn fsel9(&mut self) -> FSEL9_W<27> { + pub fn fsel9(&mut self) -> FSEL9_W { FSEL9_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel0](index.html) module"] +#[doc = "GPIO Function Select 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL0_SPEC; impl crate::RegisterSpec for GPFSEL0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel0::R](R) reader structure"] -impl crate::Readable for GPFSEL0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel0::R`](R) reader structure"] +impl crate::Readable for GPFSEL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel0::W`](W) writer structure"] impl crate::Writable for GPFSEL0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpfsel1.rs b/crates/bcm2711-lpa/src/gpio/gpfsel1.rs index 6d8414a..939c0b4 100644 --- a/crates/bcm2711-lpa/src/gpio/gpfsel1.rs +++ b/crates/bcm2711-lpa/src/gpio/gpfsel1.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL10` reader - Function Select 10"] -pub type FSEL10_R = crate::FieldReader; +pub type FSEL10_R = crate::FieldReader; #[doc = "Function Select 10"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL10_A { + type Ux = u8; +} impl FSEL10_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL10_A { + pub const fn variant(&self) -> FSEL10_A { match self.bits { 0 => FSEL10_A::INPUT, 1 => FSEL10_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL10_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL10_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL10_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_MOSI`"] + #[doc = "Pin is connected to SPI0_MOSI"] #[inline(always)] pub fn is_spi0_mosi(&self) -> bool { *self == FSEL10_A::SPI0_MOSI } - #[doc = "Checks if the value of the field is `SD2`"] + #[doc = "Pin is connected to SD2"] #[inline(always)] pub fn is_sd2(&self) -> bool { *self == FSEL10_A::SD2 } - #[doc = "Checks if the value of the field is `DPI_D6`"] + #[doc = "Pin is connected to DPI_D6"] #[inline(always)] pub fn is_dpi_d6(&self) -> bool { *self == FSEL10_A::DPI_D6 } - #[doc = "Checks if the value of the field is `BSCSL_MOSI`"] + #[doc = "Pin is connected to BSCSL_MOSI"] #[inline(always)] pub fn is_bscsl_mosi(&self) -> bool { *self == FSEL10_A::BSCSL_MOSI } - #[doc = "Checks if the value of the field is `CTS4`"] + #[doc = "Pin is connected to CTS4"] #[inline(always)] pub fn is_cts4(&self) -> bool { *self == FSEL10_A::CTS4 } - #[doc = "Checks if the value of the field is `SDA5`"] + #[doc = "Pin is connected to SDA5"] #[inline(always)] pub fn is_sda5(&self) -> bool { *self == FSEL10_A::SDA5 } } #[doc = "Field `FSEL10` writer - Function Select 10"] -pub type FSEL10_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL10_A, 3, O>; -impl<'a, const O: u8> FSEL10_W<'a, O> { +pub type FSEL10_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL10_A>; +impl<'a, REG, const O: u8> FSEL10_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL10_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL10_A::OUTPUT) } #[doc = "Pin is connected to SPI0_MOSI"] #[inline(always)] - pub fn spi0_mosi(self) -> &'a mut W { + pub fn spi0_mosi(self) -> &'a mut crate::W { self.variant(FSEL10_A::SPI0_MOSI) } #[doc = "Pin is connected to SD2"] #[inline(always)] - pub fn sd2(self) -> &'a mut W { + pub fn sd2(self) -> &'a mut crate::W { self.variant(FSEL10_A::SD2) } #[doc = "Pin is connected to DPI_D6"] #[inline(always)] - pub fn dpi_d6(self) -> &'a mut W { + pub fn dpi_d6(self) -> &'a mut crate::W { self.variant(FSEL10_A::DPI_D6) } #[doc = "Pin is connected to BSCSL_MOSI"] #[inline(always)] - pub fn bscsl_mosi(self) -> &'a mut W { + pub fn bscsl_mosi(self) -> &'a mut crate::W { self.variant(FSEL10_A::BSCSL_MOSI) } #[doc = "Pin is connected to CTS4"] #[inline(always)] - pub fn cts4(self) -> &'a mut W { + pub fn cts4(self) -> &'a mut crate::W { self.variant(FSEL10_A::CTS4) } #[doc = "Pin is connected to SDA5"] #[inline(always)] - pub fn sda5(self) -> &'a mut W { + pub fn sda5(self) -> &'a mut crate::W { self.variant(FSEL10_A::SDA5) } } #[doc = "Field `FSEL11` reader - Function Select 11"] -pub type FSEL11_R = crate::FieldReader; +pub type FSEL11_R = crate::FieldReader; #[doc = "Function Select 11"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL11_A { + type Ux = u8; +} impl FSEL11_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL11_A { + pub const fn variant(&self) -> FSEL11_A { match self.bits { 0 => FSEL11_A::INPUT, 1 => FSEL11_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL11_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL11_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL11_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_SCLK`"] + #[doc = "Pin is connected to SPI0_SCLK"] #[inline(always)] pub fn is_spi0_sclk(&self) -> bool { *self == FSEL11_A::SPI0_SCLK } - #[doc = "Checks if the value of the field is `SD3`"] + #[doc = "Pin is connected to SD3"] #[inline(always)] pub fn is_sd3(&self) -> bool { *self == FSEL11_A::SD3 } - #[doc = "Checks if the value of the field is `DPI_D7`"] + #[doc = "Pin is connected to DPI_D7"] #[inline(always)] pub fn is_dpi_d7(&self) -> bool { *self == FSEL11_A::DPI_D7 } - #[doc = "Checks if the value of the field is `BSCSL_SCLK`"] + #[doc = "Pin is connected to BSCSL_SCLK"] #[inline(always)] pub fn is_bscsl_sclk(&self) -> bool { *self == FSEL11_A::BSCSL_SCLK } - #[doc = "Checks if the value of the field is `RTS4`"] + #[doc = "Pin is connected to RTS4"] #[inline(always)] pub fn is_rts4(&self) -> bool { *self == FSEL11_A::RTS4 } - #[doc = "Checks if the value of the field is `SCL5`"] + #[doc = "Pin is connected to SCL5"] #[inline(always)] pub fn is_scl5(&self) -> bool { *self == FSEL11_A::SCL5 } } #[doc = "Field `FSEL11` writer - Function Select 11"] -pub type FSEL11_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL11_A, 3, O>; -impl<'a, const O: u8> FSEL11_W<'a, O> { +pub type FSEL11_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL11_A>; +impl<'a, REG, const O: u8> FSEL11_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL11_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL11_A::OUTPUT) } #[doc = "Pin is connected to SPI0_SCLK"] #[inline(always)] - pub fn spi0_sclk(self) -> &'a mut W { + pub fn spi0_sclk(self) -> &'a mut crate::W { self.variant(FSEL11_A::SPI0_SCLK) } #[doc = "Pin is connected to SD3"] #[inline(always)] - pub fn sd3(self) -> &'a mut W { + pub fn sd3(self) -> &'a mut crate::W { self.variant(FSEL11_A::SD3) } #[doc = "Pin is connected to DPI_D7"] #[inline(always)] - pub fn dpi_d7(self) -> &'a mut W { + pub fn dpi_d7(self) -> &'a mut crate::W { self.variant(FSEL11_A::DPI_D7) } #[doc = "Pin is connected to BSCSL_SCLK"] #[inline(always)] - pub fn bscsl_sclk(self) -> &'a mut W { + pub fn bscsl_sclk(self) -> &'a mut crate::W { self.variant(FSEL11_A::BSCSL_SCLK) } #[doc = "Pin is connected to RTS4"] #[inline(always)] - pub fn rts4(self) -> &'a mut W { + pub fn rts4(self) -> &'a mut crate::W { self.variant(FSEL11_A::RTS4) } #[doc = "Pin is connected to SCL5"] #[inline(always)] - pub fn scl5(self) -> &'a mut W { + pub fn scl5(self) -> &'a mut crate::W { self.variant(FSEL11_A::SCL5) } } #[doc = "Field `FSEL12` reader - Function Select 12"] -pub type FSEL12_R = crate::FieldReader; +pub type FSEL12_R = crate::FieldReader; #[doc = "Function Select 12"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL12_A { + type Ux = u8; +} impl FSEL12_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL12_A { + pub const fn variant(&self) -> FSEL12_A { match self.bits { 0 => FSEL12_A::INPUT, 1 => FSEL12_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL12_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL12_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL12_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM0_0`"] + #[doc = "Pin is connected to PWM0_0"] #[inline(always)] pub fn is_pwm0_0(&self) -> bool { *self == FSEL12_A::PWM0_0 } - #[doc = "Checks if the value of the field is `SD4`"] + #[doc = "Pin is connected to SD4"] #[inline(always)] pub fn is_sd4(&self) -> bool { *self == FSEL12_A::SD4 } - #[doc = "Checks if the value of the field is `DPI_D8`"] + #[doc = "Pin is connected to DPI_D8"] #[inline(always)] pub fn is_dpi_d8(&self) -> bool { *self == FSEL12_A::DPI_D8 } - #[doc = "Checks if the value of the field is `SPI5_CE0_N`"] + #[doc = "Pin is connected to SPI5_CE0_N"] #[inline(always)] pub fn is_spi5_ce0_n(&self) -> bool { *self == FSEL12_A::SPI5_CE0_N } - #[doc = "Checks if the value of the field is `TXD5`"] + #[doc = "Pin is connected to TXD5"] #[inline(always)] pub fn is_txd5(&self) -> bool { *self == FSEL12_A::TXD5 } - #[doc = "Checks if the value of the field is `SDA5`"] + #[doc = "Pin is connected to SDA5"] #[inline(always)] pub fn is_sda5(&self) -> bool { *self == FSEL12_A::SDA5 } } #[doc = "Field `FSEL12` writer - Function Select 12"] -pub type FSEL12_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL12_A, 3, O>; -impl<'a, const O: u8> FSEL12_W<'a, O> { +pub type FSEL12_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL12_A>; +impl<'a, REG, const O: u8> FSEL12_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL12_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL12_A::OUTPUT) } #[doc = "Pin is connected to PWM0_0"] #[inline(always)] - pub fn pwm0_0(self) -> &'a mut W { + pub fn pwm0_0(self) -> &'a mut crate::W { self.variant(FSEL12_A::PWM0_0) } #[doc = "Pin is connected to SD4"] #[inline(always)] - pub fn sd4(self) -> &'a mut W { + pub fn sd4(self) -> &'a mut crate::W { self.variant(FSEL12_A::SD4) } #[doc = "Pin is connected to DPI_D8"] #[inline(always)] - pub fn dpi_d8(self) -> &'a mut W { + pub fn dpi_d8(self) -> &'a mut crate::W { self.variant(FSEL12_A::DPI_D8) } #[doc = "Pin is connected to SPI5_CE0_N"] #[inline(always)] - pub fn spi5_ce0_n(self) -> &'a mut W { + pub fn spi5_ce0_n(self) -> &'a mut crate::W { self.variant(FSEL12_A::SPI5_CE0_N) } #[doc = "Pin is connected to TXD5"] #[inline(always)] - pub fn txd5(self) -> &'a mut W { + pub fn txd5(self) -> &'a mut crate::W { self.variant(FSEL12_A::TXD5) } #[doc = "Pin is connected to SDA5"] #[inline(always)] - pub fn sda5(self) -> &'a mut W { + pub fn sda5(self) -> &'a mut crate::W { self.variant(FSEL12_A::SDA5) } } #[doc = "Field `FSEL13` reader - Function Select 13"] -pub type FSEL13_R = crate::FieldReader; +pub type FSEL13_R = crate::FieldReader; #[doc = "Function Select 13"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL13_A { + type Ux = u8; +} impl FSEL13_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL13_A { + pub const fn variant(&self) -> FSEL13_A { match self.bits { 0 => FSEL13_A::INPUT, 1 => FSEL13_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL13_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL13_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL13_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM0_1`"] + #[doc = "Pin is connected to PWM0_1"] #[inline(always)] pub fn is_pwm0_1(&self) -> bool { *self == FSEL13_A::PWM0_1 } - #[doc = "Checks if the value of the field is `SD5`"] + #[doc = "Pin is connected to SD5"] #[inline(always)] pub fn is_sd5(&self) -> bool { *self == FSEL13_A::SD5 } - #[doc = "Checks if the value of the field is `DPI_D9`"] + #[doc = "Pin is connected to DPI_D9"] #[inline(always)] pub fn is_dpi_d9(&self) -> bool { *self == FSEL13_A::DPI_D9 } - #[doc = "Checks if the value of the field is `SPI5_MISO`"] + #[doc = "Pin is connected to SPI5_MISO"] #[inline(always)] pub fn is_spi5_miso(&self) -> bool { *self == FSEL13_A::SPI5_MISO } - #[doc = "Checks if the value of the field is `RXD5`"] + #[doc = "Pin is connected to RXD5"] #[inline(always)] pub fn is_rxd5(&self) -> bool { *self == FSEL13_A::RXD5 } - #[doc = "Checks if the value of the field is `SCL5`"] + #[doc = "Pin is connected to SCL5"] #[inline(always)] pub fn is_scl5(&self) -> bool { *self == FSEL13_A::SCL5 } } #[doc = "Field `FSEL13` writer - Function Select 13"] -pub type FSEL13_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL13_A, 3, O>; -impl<'a, const O: u8> FSEL13_W<'a, O> { +pub type FSEL13_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL13_A>; +impl<'a, REG, const O: u8> FSEL13_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL13_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL13_A::OUTPUT) } #[doc = "Pin is connected to PWM0_1"] #[inline(always)] - pub fn pwm0_1(self) -> &'a mut W { + pub fn pwm0_1(self) -> &'a mut crate::W { self.variant(FSEL13_A::PWM0_1) } #[doc = "Pin is connected to SD5"] #[inline(always)] - pub fn sd5(self) -> &'a mut W { + pub fn sd5(self) -> &'a mut crate::W { self.variant(FSEL13_A::SD5) } #[doc = "Pin is connected to DPI_D9"] #[inline(always)] - pub fn dpi_d9(self) -> &'a mut W { + pub fn dpi_d9(self) -> &'a mut crate::W { self.variant(FSEL13_A::DPI_D9) } #[doc = "Pin is connected to SPI5_MISO"] #[inline(always)] - pub fn spi5_miso(self) -> &'a mut W { + pub fn spi5_miso(self) -> &'a mut crate::W { self.variant(FSEL13_A::SPI5_MISO) } #[doc = "Pin is connected to RXD5"] #[inline(always)] - pub fn rxd5(self) -> &'a mut W { + pub fn rxd5(self) -> &'a mut crate::W { self.variant(FSEL13_A::RXD5) } #[doc = "Pin is connected to SCL5"] #[inline(always)] - pub fn scl5(self) -> &'a mut W { + pub fn scl5(self) -> &'a mut crate::W { self.variant(FSEL13_A::SCL5) } } #[doc = "Field `FSEL14` reader - Function Select 14"] -pub type FSEL14_R = crate::FieldReader; +pub type FSEL14_R = crate::FieldReader; #[doc = "Function Select 14"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL14_A { + type Ux = u8; +} impl FSEL14_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL14_A { + pub const fn variant(&self) -> FSEL14_A { match self.bits { 0 => FSEL14_A::INPUT, 1 => FSEL14_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL14_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL14_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL14_A::OUTPUT } - #[doc = "Checks if the value of the field is `TXD0`"] + #[doc = "Pin is connected to TXD0"] #[inline(always)] pub fn is_txd0(&self) -> bool { *self == FSEL14_A::TXD0 } - #[doc = "Checks if the value of the field is `SD6`"] + #[doc = "Pin is connected to SD6"] #[inline(always)] pub fn is_sd6(&self) -> bool { *self == FSEL14_A::SD6 } - #[doc = "Checks if the value of the field is `DPI_D10`"] + #[doc = "Pin is connected to DPI_D10"] #[inline(always)] pub fn is_dpi_d10(&self) -> bool { *self == FSEL14_A::DPI_D10 } - #[doc = "Checks if the value of the field is `SPI5_MOSI`"] + #[doc = "Pin is connected to SPI5_MOSI"] #[inline(always)] pub fn is_spi5_mosi(&self) -> bool { *self == FSEL14_A::SPI5_MOSI } - #[doc = "Checks if the value of the field is `CTS5`"] + #[doc = "Pin is connected to CTS5"] #[inline(always)] pub fn is_cts5(&self) -> bool { *self == FSEL14_A::CTS5 } - #[doc = "Checks if the value of the field is `TXD1`"] + #[doc = "Pin is connected to TXD1"] #[inline(always)] pub fn is_txd1(&self) -> bool { *self == FSEL14_A::TXD1 } } #[doc = "Field `FSEL14` writer - Function Select 14"] -pub type FSEL14_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL14_A, 3, O>; -impl<'a, const O: u8> FSEL14_W<'a, O> { +pub type FSEL14_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL14_A>; +impl<'a, REG, const O: u8> FSEL14_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL14_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL14_A::OUTPUT) } #[doc = "Pin is connected to TXD0"] #[inline(always)] - pub fn txd0(self) -> &'a mut W { + pub fn txd0(self) -> &'a mut crate::W { self.variant(FSEL14_A::TXD0) } #[doc = "Pin is connected to SD6"] #[inline(always)] - pub fn sd6(self) -> &'a mut W { + pub fn sd6(self) -> &'a mut crate::W { self.variant(FSEL14_A::SD6) } #[doc = "Pin is connected to DPI_D10"] #[inline(always)] - pub fn dpi_d10(self) -> &'a mut W { + pub fn dpi_d10(self) -> &'a mut crate::W { self.variant(FSEL14_A::DPI_D10) } #[doc = "Pin is connected to SPI5_MOSI"] #[inline(always)] - pub fn spi5_mosi(self) -> &'a mut W { + pub fn spi5_mosi(self) -> &'a mut crate::W { self.variant(FSEL14_A::SPI5_MOSI) } #[doc = "Pin is connected to CTS5"] #[inline(always)] - pub fn cts5(self) -> &'a mut W { + pub fn cts5(self) -> &'a mut crate::W { self.variant(FSEL14_A::CTS5) } #[doc = "Pin is connected to TXD1"] #[inline(always)] - pub fn txd1(self) -> &'a mut W { + pub fn txd1(self) -> &'a mut crate::W { self.variant(FSEL14_A::TXD1) } } #[doc = "Field `FSEL15` reader - Function Select 15"] -pub type FSEL15_R = crate::FieldReader; +pub type FSEL15_R = crate::FieldReader; #[doc = "Function Select 15"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL15_A { + type Ux = u8; +} impl FSEL15_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL15_A { + pub const fn variant(&self) -> FSEL15_A { match self.bits { 0 => FSEL15_A::INPUT, 1 => FSEL15_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL15_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL15_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL15_A::OUTPUT } - #[doc = "Checks if the value of the field is `RXD0`"] + #[doc = "Pin is connected to RXD0"] #[inline(always)] pub fn is_rxd0(&self) -> bool { *self == FSEL15_A::RXD0 } - #[doc = "Checks if the value of the field is `SD7`"] + #[doc = "Pin is connected to SD7"] #[inline(always)] pub fn is_sd7(&self) -> bool { *self == FSEL15_A::SD7 } - #[doc = "Checks if the value of the field is `DPI_D11`"] + #[doc = "Pin is connected to DPI_D11"] #[inline(always)] pub fn is_dpi_d11(&self) -> bool { *self == FSEL15_A::DPI_D11 } - #[doc = "Checks if the value of the field is `SPI5_SCLK`"] + #[doc = "Pin is connected to SPI5_SCLK"] #[inline(always)] pub fn is_spi5_sclk(&self) -> bool { *self == FSEL15_A::SPI5_SCLK } - #[doc = "Checks if the value of the field is `RTS5`"] + #[doc = "Pin is connected to RTS5"] #[inline(always)] pub fn is_rts5(&self) -> bool { *self == FSEL15_A::RTS5 } - #[doc = "Checks if the value of the field is `RXD1`"] + #[doc = "Pin is connected to RXD1"] #[inline(always)] pub fn is_rxd1(&self) -> bool { *self == FSEL15_A::RXD1 } } #[doc = "Field `FSEL15` writer - Function Select 15"] -pub type FSEL15_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL15_A, 3, O>; -impl<'a, const O: u8> FSEL15_W<'a, O> { +pub type FSEL15_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL15_A>; +impl<'a, REG, const O: u8> FSEL15_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL15_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL15_A::OUTPUT) } #[doc = "Pin is connected to RXD0"] #[inline(always)] - pub fn rxd0(self) -> &'a mut W { + pub fn rxd0(self) -> &'a mut crate::W { self.variant(FSEL15_A::RXD0) } #[doc = "Pin is connected to SD7"] #[inline(always)] - pub fn sd7(self) -> &'a mut W { + pub fn sd7(self) -> &'a mut crate::W { self.variant(FSEL15_A::SD7) } #[doc = "Pin is connected to DPI_D11"] #[inline(always)] - pub fn dpi_d11(self) -> &'a mut W { + pub fn dpi_d11(self) -> &'a mut crate::W { self.variant(FSEL15_A::DPI_D11) } #[doc = "Pin is connected to SPI5_SCLK"] #[inline(always)] - pub fn spi5_sclk(self) -> &'a mut W { + pub fn spi5_sclk(self) -> &'a mut crate::W { self.variant(FSEL15_A::SPI5_SCLK) } #[doc = "Pin is connected to RTS5"] #[inline(always)] - pub fn rts5(self) -> &'a mut W { + pub fn rts5(self) -> &'a mut crate::W { self.variant(FSEL15_A::RTS5) } #[doc = "Pin is connected to RXD1"] #[inline(always)] - pub fn rxd1(self) -> &'a mut W { + pub fn rxd1(self) -> &'a mut crate::W { self.variant(FSEL15_A::RXD1) } } #[doc = "Field `FSEL16` reader - Function Select 16"] -pub type FSEL16_R = crate::FieldReader; +pub type FSEL16_R = crate::FieldReader; #[doc = "Function Select 16"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL16_A { + type Ux = u8; +} impl FSEL16_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL16_A { + pub const fn variant(&self) -> FSEL16_A { match self.bits { 0 => FSEL16_A::INPUT, 1 => FSEL16_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL16_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL16_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL16_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL16_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD8`"] + #[doc = "Pin is connected to SD8"] #[inline(always)] pub fn is_sd8(&self) -> bool { *self == FSEL16_A::SD8 } - #[doc = "Checks if the value of the field is `DPI_D12`"] + #[doc = "Pin is connected to DPI_D12"] #[inline(always)] pub fn is_dpi_d12(&self) -> bool { *self == FSEL16_A::DPI_D12 } - #[doc = "Checks if the value of the field is `CTS0`"] + #[doc = "Pin is connected to CTS0"] #[inline(always)] pub fn is_cts0(&self) -> bool { *self == FSEL16_A::CTS0 } - #[doc = "Checks if the value of the field is `SPI1_CE2_N`"] + #[doc = "Pin is connected to SPI1_CE2_N"] #[inline(always)] pub fn is_spi1_ce2_n(&self) -> bool { *self == FSEL16_A::SPI1_CE2_N } - #[doc = "Checks if the value of the field is `CTS1`"] + #[doc = "Pin is connected to CTS1"] #[inline(always)] pub fn is_cts1(&self) -> bool { *self == FSEL16_A::CTS1 } } #[doc = "Field `FSEL16` writer - Function Select 16"] -pub type FSEL16_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL16_A, 3, O>; -impl<'a, const O: u8> FSEL16_W<'a, O> { +pub type FSEL16_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL16_A>; +impl<'a, REG, const O: u8> FSEL16_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL16_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL16_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL16_A::RESERVED0) } #[doc = "Pin is connected to SD8"] #[inline(always)] - pub fn sd8(self) -> &'a mut W { + pub fn sd8(self) -> &'a mut crate::W { self.variant(FSEL16_A::SD8) } #[doc = "Pin is connected to DPI_D12"] #[inline(always)] - pub fn dpi_d12(self) -> &'a mut W { + pub fn dpi_d12(self) -> &'a mut crate::W { self.variant(FSEL16_A::DPI_D12) } #[doc = "Pin is connected to CTS0"] #[inline(always)] - pub fn cts0(self) -> &'a mut W { + pub fn cts0(self) -> &'a mut crate::W { self.variant(FSEL16_A::CTS0) } #[doc = "Pin is connected to SPI1_CE2_N"] #[inline(always)] - pub fn spi1_ce2_n(self) -> &'a mut W { + pub fn spi1_ce2_n(self) -> &'a mut crate::W { self.variant(FSEL16_A::SPI1_CE2_N) } #[doc = "Pin is connected to CTS1"] #[inline(always)] - pub fn cts1(self) -> &'a mut W { + pub fn cts1(self) -> &'a mut crate::W { self.variant(FSEL16_A::CTS1) } } #[doc = "Field `FSEL17` reader - Function Select 17"] -pub type FSEL17_R = crate::FieldReader; +pub type FSEL17_R = crate::FieldReader; #[doc = "Function Select 17"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL17_A { + type Ux = u8; +} impl FSEL17_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL17_A { + pub const fn variant(&self) -> FSEL17_A { match self.bits { 0 => FSEL17_A::INPUT, 1 => FSEL17_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL17_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL17_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL17_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL17_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD9`"] + #[doc = "Pin is connected to SD9"] #[inline(always)] pub fn is_sd9(&self) -> bool { *self == FSEL17_A::SD9 } - #[doc = "Checks if the value of the field is `DPI_D13`"] + #[doc = "Pin is connected to DPI_D13"] #[inline(always)] pub fn is_dpi_d13(&self) -> bool { *self == FSEL17_A::DPI_D13 } - #[doc = "Checks if the value of the field is `RTS0`"] + #[doc = "Pin is connected to RTS0"] #[inline(always)] pub fn is_rts0(&self) -> bool { *self == FSEL17_A::RTS0 } - #[doc = "Checks if the value of the field is `SPI1_CE1_N`"] + #[doc = "Pin is connected to SPI1_CE1_N"] #[inline(always)] pub fn is_spi1_ce1_n(&self) -> bool { *self == FSEL17_A::SPI1_CE1_N } - #[doc = "Checks if the value of the field is `RTS1`"] + #[doc = "Pin is connected to RTS1"] #[inline(always)] pub fn is_rts1(&self) -> bool { *self == FSEL17_A::RTS1 } } #[doc = "Field `FSEL17` writer - Function Select 17"] -pub type FSEL17_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL17_A, 3, O>; -impl<'a, const O: u8> FSEL17_W<'a, O> { +pub type FSEL17_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL17_A>; +impl<'a, REG, const O: u8> FSEL17_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL17_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL17_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL17_A::RESERVED0) } #[doc = "Pin is connected to SD9"] #[inline(always)] - pub fn sd9(self) -> &'a mut W { + pub fn sd9(self) -> &'a mut crate::W { self.variant(FSEL17_A::SD9) } #[doc = "Pin is connected to DPI_D13"] #[inline(always)] - pub fn dpi_d13(self) -> &'a mut W { + pub fn dpi_d13(self) -> &'a mut crate::W { self.variant(FSEL17_A::DPI_D13) } #[doc = "Pin is connected to RTS0"] #[inline(always)] - pub fn rts0(self) -> &'a mut W { + pub fn rts0(self) -> &'a mut crate::W { self.variant(FSEL17_A::RTS0) } #[doc = "Pin is connected to SPI1_CE1_N"] #[inline(always)] - pub fn spi1_ce1_n(self) -> &'a mut W { + pub fn spi1_ce1_n(self) -> &'a mut crate::W { self.variant(FSEL17_A::SPI1_CE1_N) } #[doc = "Pin is connected to RTS1"] #[inline(always)] - pub fn rts1(self) -> &'a mut W { + pub fn rts1(self) -> &'a mut crate::W { self.variant(FSEL17_A::RTS1) } } #[doc = "Field `FSEL18` reader - Function Select 18"] -pub type FSEL18_R = crate::FieldReader; +pub type FSEL18_R = crate::FieldReader; #[doc = "Function Select 18"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL18_A { + type Ux = u8; +} impl FSEL18_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL18_A { + pub const fn variant(&self) -> FSEL18_A { match self.bits { 0 => FSEL18_A::INPUT, 1 => FSEL18_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL18_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL18_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL18_A::OUTPUT } - #[doc = "Checks if the value of the field is `PCM_CLK`"] + #[doc = "Pin is connected to PCM_CLK"] #[inline(always)] pub fn is_pcm_clk(&self) -> bool { *self == FSEL18_A::PCM_CLK } - #[doc = "Checks if the value of the field is `SD10`"] + #[doc = "Pin is connected to SD10"] #[inline(always)] pub fn is_sd10(&self) -> bool { *self == FSEL18_A::SD10 } - #[doc = "Checks if the value of the field is `DPI_D14`"] + #[doc = "Pin is connected to DPI_D14"] #[inline(always)] pub fn is_dpi_d14(&self) -> bool { *self == FSEL18_A::DPI_D14 } - #[doc = "Checks if the value of the field is `SPI6_CE0_N`"] + #[doc = "Pin is connected to SPI6_CE0_N"] #[inline(always)] pub fn is_spi6_ce0_n(&self) -> bool { *self == FSEL18_A::SPI6_CE0_N } - #[doc = "Checks if the value of the field is `SPI1_CE0_N`"] + #[doc = "Pin is connected to SPI1_CE0_N"] #[inline(always)] pub fn is_spi1_ce0_n(&self) -> bool { *self == FSEL18_A::SPI1_CE0_N } - #[doc = "Checks if the value of the field is `PWM0_0`"] + #[doc = "Pin is connected to PWM0_0"] #[inline(always)] pub fn is_pwm0_0(&self) -> bool { *self == FSEL18_A::PWM0_0 } } #[doc = "Field `FSEL18` writer - Function Select 18"] -pub type FSEL18_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL18_A, 3, O>; -impl<'a, const O: u8> FSEL18_W<'a, O> { +pub type FSEL18_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL18_A>; +impl<'a, REG, const O: u8> FSEL18_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL18_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL18_A::OUTPUT) } #[doc = "Pin is connected to PCM_CLK"] #[inline(always)] - pub fn pcm_clk(self) -> &'a mut W { + pub fn pcm_clk(self) -> &'a mut crate::W { self.variant(FSEL18_A::PCM_CLK) } #[doc = "Pin is connected to SD10"] #[inline(always)] - pub fn sd10(self) -> &'a mut W { + pub fn sd10(self) -> &'a mut crate::W { self.variant(FSEL18_A::SD10) } #[doc = "Pin is connected to DPI_D14"] #[inline(always)] - pub fn dpi_d14(self) -> &'a mut W { + pub fn dpi_d14(self) -> &'a mut crate::W { self.variant(FSEL18_A::DPI_D14) } #[doc = "Pin is connected to SPI6_CE0_N"] #[inline(always)] - pub fn spi6_ce0_n(self) -> &'a mut W { + pub fn spi6_ce0_n(self) -> &'a mut crate::W { self.variant(FSEL18_A::SPI6_CE0_N) } #[doc = "Pin is connected to SPI1_CE0_N"] #[inline(always)] - pub fn spi1_ce0_n(self) -> &'a mut W { + pub fn spi1_ce0_n(self) -> &'a mut crate::W { self.variant(FSEL18_A::SPI1_CE0_N) } #[doc = "Pin is connected to PWM0_0"] #[inline(always)] - pub fn pwm0_0(self) -> &'a mut W { + pub fn pwm0_0(self) -> &'a mut crate::W { self.variant(FSEL18_A::PWM0_0) } } #[doc = "Field `FSEL19` reader - Function Select 19"] -pub type FSEL19_R = crate::FieldReader; +pub type FSEL19_R = crate::FieldReader; #[doc = "Function Select 19"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL19_A { + type Ux = u8; +} impl FSEL19_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL19_A { + pub const fn variant(&self) -> FSEL19_A { match self.bits { 0 => FSEL19_A::INPUT, 1 => FSEL19_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL19_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL19_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL19_A::OUTPUT } - #[doc = "Checks if the value of the field is `PCM_FS`"] + #[doc = "Pin is connected to PCM_FS"] #[inline(always)] pub fn is_pcm_fs(&self) -> bool { *self == FSEL19_A::PCM_FS } - #[doc = "Checks if the value of the field is `SD11`"] + #[doc = "Pin is connected to SD11"] #[inline(always)] pub fn is_sd11(&self) -> bool { *self == FSEL19_A::SD11 } - #[doc = "Checks if the value of the field is `DPI_D15`"] + #[doc = "Pin is connected to DPI_D15"] #[inline(always)] pub fn is_dpi_d15(&self) -> bool { *self == FSEL19_A::DPI_D15 } - #[doc = "Checks if the value of the field is `SPI6_MISO`"] + #[doc = "Pin is connected to SPI6_MISO"] #[inline(always)] pub fn is_spi6_miso(&self) -> bool { *self == FSEL19_A::SPI6_MISO } - #[doc = "Checks if the value of the field is `SPI1_MISO`"] + #[doc = "Pin is connected to SPI1_MISO"] #[inline(always)] pub fn is_spi1_miso(&self) -> bool { *self == FSEL19_A::SPI1_MISO } - #[doc = "Checks if the value of the field is `PWM0_1`"] + #[doc = "Pin is connected to PWM0_1"] #[inline(always)] pub fn is_pwm0_1(&self) -> bool { *self == FSEL19_A::PWM0_1 } } #[doc = "Field `FSEL19` writer - Function Select 19"] -pub type FSEL19_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL19_A, 3, O>; -impl<'a, const O: u8> FSEL19_W<'a, O> { +pub type FSEL19_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL19_A>; +impl<'a, REG, const O: u8> FSEL19_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL19_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL19_A::OUTPUT) } #[doc = "Pin is connected to PCM_FS"] #[inline(always)] - pub fn pcm_fs(self) -> &'a mut W { + pub fn pcm_fs(self) -> &'a mut crate::W { self.variant(FSEL19_A::PCM_FS) } #[doc = "Pin is connected to SD11"] #[inline(always)] - pub fn sd11(self) -> &'a mut W { + pub fn sd11(self) -> &'a mut crate::W { self.variant(FSEL19_A::SD11) } #[doc = "Pin is connected to DPI_D15"] #[inline(always)] - pub fn dpi_d15(self) -> &'a mut W { + pub fn dpi_d15(self) -> &'a mut crate::W { self.variant(FSEL19_A::DPI_D15) } #[doc = "Pin is connected to SPI6_MISO"] #[inline(always)] - pub fn spi6_miso(self) -> &'a mut W { + pub fn spi6_miso(self) -> &'a mut crate::W { self.variant(FSEL19_A::SPI6_MISO) } #[doc = "Pin is connected to SPI1_MISO"] #[inline(always)] - pub fn spi1_miso(self) -> &'a mut W { + pub fn spi1_miso(self) -> &'a mut crate::W { self.variant(FSEL19_A::SPI1_MISO) } #[doc = "Pin is connected to PWM0_1"] #[inline(always)] - pub fn pwm0_1(self) -> &'a mut W { + pub fn pwm0_1(self) -> &'a mut crate::W { self.variant(FSEL19_A::PWM0_1) } } @@ -1396,86 +1424,108 @@ impl R { FSEL19_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL1") + .field("fsel10", &format_args!("{}", self.fsel10().bits())) + .field("fsel11", &format_args!("{}", self.fsel11().bits())) + .field("fsel12", &format_args!("{}", self.fsel12().bits())) + .field("fsel13", &format_args!("{}", self.fsel13().bits())) + .field("fsel14", &format_args!("{}", self.fsel14().bits())) + .field("fsel15", &format_args!("{}", self.fsel15().bits())) + .field("fsel16", &format_args!("{}", self.fsel16().bits())) + .field("fsel17", &format_args!("{}", self.fsel17().bits())) + .field("fsel18", &format_args!("{}", self.fsel18().bits())) + .field("fsel19", &format_args!("{}", self.fsel19().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 10"] #[inline(always)] #[must_use] - pub fn fsel10(&mut self) -> FSEL10_W<0> { + pub fn fsel10(&mut self) -> FSEL10_W { FSEL10_W::new(self) } #[doc = "Bits 3:5 - Function Select 11"] #[inline(always)] #[must_use] - pub fn fsel11(&mut self) -> FSEL11_W<3> { + pub fn fsel11(&mut self) -> FSEL11_W { FSEL11_W::new(self) } #[doc = "Bits 6:8 - Function Select 12"] #[inline(always)] #[must_use] - pub fn fsel12(&mut self) -> FSEL12_W<6> { + pub fn fsel12(&mut self) -> FSEL12_W { FSEL12_W::new(self) } #[doc = "Bits 9:11 - Function Select 13"] #[inline(always)] #[must_use] - pub fn fsel13(&mut self) -> FSEL13_W<9> { + pub fn fsel13(&mut self) -> FSEL13_W { FSEL13_W::new(self) } #[doc = "Bits 12:14 - Function Select 14"] #[inline(always)] #[must_use] - pub fn fsel14(&mut self) -> FSEL14_W<12> { + pub fn fsel14(&mut self) -> FSEL14_W { FSEL14_W::new(self) } #[doc = "Bits 15:17 - Function Select 15"] #[inline(always)] #[must_use] - pub fn fsel15(&mut self) -> FSEL15_W<15> { + pub fn fsel15(&mut self) -> FSEL15_W { FSEL15_W::new(self) } #[doc = "Bits 18:20 - Function Select 16"] #[inline(always)] #[must_use] - pub fn fsel16(&mut self) -> FSEL16_W<18> { + pub fn fsel16(&mut self) -> FSEL16_W { FSEL16_W::new(self) } #[doc = "Bits 21:23 - Function Select 17"] #[inline(always)] #[must_use] - pub fn fsel17(&mut self) -> FSEL17_W<21> { + pub fn fsel17(&mut self) -> FSEL17_W { FSEL17_W::new(self) } #[doc = "Bits 24:26 - Function Select 18"] #[inline(always)] #[must_use] - pub fn fsel18(&mut self) -> FSEL18_W<24> { + pub fn fsel18(&mut self) -> FSEL18_W { FSEL18_W::new(self) } #[doc = "Bits 27:29 - Function Select 19"] #[inline(always)] #[must_use] - pub fn fsel19(&mut self) -> FSEL19_W<27> { + pub fn fsel19(&mut self) -> FSEL19_W { FSEL19_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel1](index.html) module"] +#[doc = "GPIO Function Select 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL1_SPEC; impl crate::RegisterSpec for GPFSEL1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel1::R](R) reader structure"] -impl crate::Readable for GPFSEL1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel1::R`](R) reader structure"] +impl crate::Readable for GPFSEL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel1::W`](W) writer structure"] impl crate::Writable for GPFSEL1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpfsel2.rs b/crates/bcm2711-lpa/src/gpio/gpfsel2.rs index 1622933..a9af1e5 100644 --- a/crates/bcm2711-lpa/src/gpio/gpfsel2.rs +++ b/crates/bcm2711-lpa/src/gpio/gpfsel2.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL20` reader - Function Select 20"] -pub type FSEL20_R = crate::FieldReader; +pub type FSEL20_R = crate::FieldReader; #[doc = "Function Select 20"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL20_A { + type Ux = u8; +} impl FSEL20_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL20_A { + pub const fn variant(&self) -> FSEL20_A { match self.bits { 0 => FSEL20_A::INPUT, 1 => FSEL20_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL20_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL20_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL20_A::OUTPUT } - #[doc = "Checks if the value of the field is `PCM_DIN`"] + #[doc = "Pin is connected to PCM_DIN"] #[inline(always)] pub fn is_pcm_din(&self) -> bool { *self == FSEL20_A::PCM_DIN } - #[doc = "Checks if the value of the field is `SD12`"] + #[doc = "Pin is connected to SD12"] #[inline(always)] pub fn is_sd12(&self) -> bool { *self == FSEL20_A::SD12 } - #[doc = "Checks if the value of the field is `DPI_D16`"] + #[doc = "Pin is connected to DPI_D16"] #[inline(always)] pub fn is_dpi_d16(&self) -> bool { *self == FSEL20_A::DPI_D16 } - #[doc = "Checks if the value of the field is `SPI6_MOSI`"] + #[doc = "Pin is connected to SPI6_MOSI"] #[inline(always)] pub fn is_spi6_mosi(&self) -> bool { *self == FSEL20_A::SPI6_MOSI } - #[doc = "Checks if the value of the field is `SPI1_MOSI`"] + #[doc = "Pin is connected to SPI1_MOSI"] #[inline(always)] pub fn is_spi1_mosi(&self) -> bool { *self == FSEL20_A::SPI1_MOSI } - #[doc = "Checks if the value of the field is `GPCLK0`"] + #[doc = "Pin is connected to GPCLK0"] #[inline(always)] pub fn is_gpclk0(&self) -> bool { *self == FSEL20_A::GPCLK0 } } #[doc = "Field `FSEL20` writer - Function Select 20"] -pub type FSEL20_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL20_A, 3, O>; -impl<'a, const O: u8> FSEL20_W<'a, O> { +pub type FSEL20_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL20_A>; +impl<'a, REG, const O: u8> FSEL20_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL20_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL20_A::OUTPUT) } #[doc = "Pin is connected to PCM_DIN"] #[inline(always)] - pub fn pcm_din(self) -> &'a mut W { + pub fn pcm_din(self) -> &'a mut crate::W { self.variant(FSEL20_A::PCM_DIN) } #[doc = "Pin is connected to SD12"] #[inline(always)] - pub fn sd12(self) -> &'a mut W { + pub fn sd12(self) -> &'a mut crate::W { self.variant(FSEL20_A::SD12) } #[doc = "Pin is connected to DPI_D16"] #[inline(always)] - pub fn dpi_d16(self) -> &'a mut W { + pub fn dpi_d16(self) -> &'a mut crate::W { self.variant(FSEL20_A::DPI_D16) } #[doc = "Pin is connected to SPI6_MOSI"] #[inline(always)] - pub fn spi6_mosi(self) -> &'a mut W { + pub fn spi6_mosi(self) -> &'a mut crate::W { self.variant(FSEL20_A::SPI6_MOSI) } #[doc = "Pin is connected to SPI1_MOSI"] #[inline(always)] - pub fn spi1_mosi(self) -> &'a mut W { + pub fn spi1_mosi(self) -> &'a mut crate::W { self.variant(FSEL20_A::SPI1_MOSI) } #[doc = "Pin is connected to GPCLK0"] #[inline(always)] - pub fn gpclk0(self) -> &'a mut W { + pub fn gpclk0(self) -> &'a mut crate::W { self.variant(FSEL20_A::GPCLK0) } } #[doc = "Field `FSEL21` reader - Function Select 21"] -pub type FSEL21_R = crate::FieldReader; +pub type FSEL21_R = crate::FieldReader; #[doc = "Function Select 21"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL21_A { + type Ux = u8; +} impl FSEL21_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL21_A { + pub const fn variant(&self) -> FSEL21_A { match self.bits { 0 => FSEL21_A::INPUT, 1 => FSEL21_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL21_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL21_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL21_A::OUTPUT } - #[doc = "Checks if the value of the field is `PCM_DOUT`"] + #[doc = "Pin is connected to PCM_DOUT"] #[inline(always)] pub fn is_pcm_dout(&self) -> bool { *self == FSEL21_A::PCM_DOUT } - #[doc = "Checks if the value of the field is `SD13`"] + #[doc = "Pin is connected to SD13"] #[inline(always)] pub fn is_sd13(&self) -> bool { *self == FSEL21_A::SD13 } - #[doc = "Checks if the value of the field is `DPI_D17`"] + #[doc = "Pin is connected to DPI_D17"] #[inline(always)] pub fn is_dpi_d17(&self) -> bool { *self == FSEL21_A::DPI_D17 } - #[doc = "Checks if the value of the field is `SPI6_SCLK`"] + #[doc = "Pin is connected to SPI6_SCLK"] #[inline(always)] pub fn is_spi6_sclk(&self) -> bool { *self == FSEL21_A::SPI6_SCLK } - #[doc = "Checks if the value of the field is `SPI1_SCLK`"] + #[doc = "Pin is connected to SPI1_SCLK"] #[inline(always)] pub fn is_spi1_sclk(&self) -> bool { *self == FSEL21_A::SPI1_SCLK } - #[doc = "Checks if the value of the field is `GPCLK1`"] + #[doc = "Pin is connected to GPCLK1"] #[inline(always)] pub fn is_gpclk1(&self) -> bool { *self == FSEL21_A::GPCLK1 } } #[doc = "Field `FSEL21` writer - Function Select 21"] -pub type FSEL21_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL21_A, 3, O>; -impl<'a, const O: u8> FSEL21_W<'a, O> { +pub type FSEL21_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL21_A>; +impl<'a, REG, const O: u8> FSEL21_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL21_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL21_A::OUTPUT) } #[doc = "Pin is connected to PCM_DOUT"] #[inline(always)] - pub fn pcm_dout(self) -> &'a mut W { + pub fn pcm_dout(self) -> &'a mut crate::W { self.variant(FSEL21_A::PCM_DOUT) } #[doc = "Pin is connected to SD13"] #[inline(always)] - pub fn sd13(self) -> &'a mut W { + pub fn sd13(self) -> &'a mut crate::W { self.variant(FSEL21_A::SD13) } #[doc = "Pin is connected to DPI_D17"] #[inline(always)] - pub fn dpi_d17(self) -> &'a mut W { + pub fn dpi_d17(self) -> &'a mut crate::W { self.variant(FSEL21_A::DPI_D17) } #[doc = "Pin is connected to SPI6_SCLK"] #[inline(always)] - pub fn spi6_sclk(self) -> &'a mut W { + pub fn spi6_sclk(self) -> &'a mut crate::W { self.variant(FSEL21_A::SPI6_SCLK) } #[doc = "Pin is connected to SPI1_SCLK"] #[inline(always)] - pub fn spi1_sclk(self) -> &'a mut W { + pub fn spi1_sclk(self) -> &'a mut crate::W { self.variant(FSEL21_A::SPI1_SCLK) } #[doc = "Pin is connected to GPCLK1"] #[inline(always)] - pub fn gpclk1(self) -> &'a mut W { + pub fn gpclk1(self) -> &'a mut crate::W { self.variant(FSEL21_A::GPCLK1) } } #[doc = "Field `FSEL22` reader - Function Select 22"] -pub type FSEL22_R = crate::FieldReader; +pub type FSEL22_R = crate::FieldReader; #[doc = "Function Select 22"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL22_A { + type Ux = u8; +} impl FSEL22_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL22_A { + pub const fn variant(&self) -> FSEL22_A { match self.bits { 0 => FSEL22_A::INPUT, 1 => FSEL22_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL22_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL22_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL22_A::OUTPUT } - #[doc = "Checks if the value of the field is `SD0_CLK`"] + #[doc = "Pin is connected to SD0_CLK"] #[inline(always)] pub fn is_sd0_clk(&self) -> bool { *self == FSEL22_A::SD0_CLK } - #[doc = "Checks if the value of the field is `SD14`"] + #[doc = "Pin is connected to SD14"] #[inline(always)] pub fn is_sd14(&self) -> bool { *self == FSEL22_A::SD14 } - #[doc = "Checks if the value of the field is `DPI_D18`"] + #[doc = "Pin is connected to DPI_D18"] #[inline(always)] pub fn is_dpi_d18(&self) -> bool { *self == FSEL22_A::DPI_D18 } - #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] pub fn is_sd1_clk(&self) -> bool { *self == FSEL22_A::SD1_CLK } - #[doc = "Checks if the value of the field is `ARM_TRST`"] + #[doc = "Pin is connected to ARM_TRST"] #[inline(always)] pub fn is_arm_trst(&self) -> bool { *self == FSEL22_A::ARM_TRST } - #[doc = "Checks if the value of the field is `SDA6`"] + #[doc = "Pin is connected to SDA6"] #[inline(always)] pub fn is_sda6(&self) -> bool { *self == FSEL22_A::SDA6 } } #[doc = "Field `FSEL22` writer - Function Select 22"] -pub type FSEL22_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL22_A, 3, O>; -impl<'a, const O: u8> FSEL22_W<'a, O> { +pub type FSEL22_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL22_A>; +impl<'a, REG, const O: u8> FSEL22_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL22_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL22_A::OUTPUT) } #[doc = "Pin is connected to SD0_CLK"] #[inline(always)] - pub fn sd0_clk(self) -> &'a mut W { + pub fn sd0_clk(self) -> &'a mut crate::W { self.variant(FSEL22_A::SD0_CLK) } #[doc = "Pin is connected to SD14"] #[inline(always)] - pub fn sd14(self) -> &'a mut W { + pub fn sd14(self) -> &'a mut crate::W { self.variant(FSEL22_A::SD14) } #[doc = "Pin is connected to DPI_D18"] #[inline(always)] - pub fn dpi_d18(self) -> &'a mut W { + pub fn dpi_d18(self) -> &'a mut crate::W { self.variant(FSEL22_A::DPI_D18) } #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] - pub fn sd1_clk(self) -> &'a mut W { + pub fn sd1_clk(self) -> &'a mut crate::W { self.variant(FSEL22_A::SD1_CLK) } #[doc = "Pin is connected to ARM_TRST"] #[inline(always)] - pub fn arm_trst(self) -> &'a mut W { + pub fn arm_trst(self) -> &'a mut crate::W { self.variant(FSEL22_A::ARM_TRST) } #[doc = "Pin is connected to SDA6"] #[inline(always)] - pub fn sda6(self) -> &'a mut W { + pub fn sda6(self) -> &'a mut crate::W { self.variant(FSEL22_A::SDA6) } } #[doc = "Field `FSEL23` reader - Function Select 23"] -pub type FSEL23_R = crate::FieldReader; +pub type FSEL23_R = crate::FieldReader; #[doc = "Function Select 23"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL23_A { + type Ux = u8; +} impl FSEL23_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL23_A { + pub const fn variant(&self) -> FSEL23_A { match self.bits { 0 => FSEL23_A::INPUT, 1 => FSEL23_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL23_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL23_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL23_A::OUTPUT } - #[doc = "Checks if the value of the field is `SD0_CMD`"] + #[doc = "Pin is connected to SD0_CMD"] #[inline(always)] pub fn is_sd0_cmd(&self) -> bool { *self == FSEL23_A::SD0_CMD } - #[doc = "Checks if the value of the field is `SD15`"] + #[doc = "Pin is connected to SD15"] #[inline(always)] pub fn is_sd15(&self) -> bool { *self == FSEL23_A::SD15 } - #[doc = "Checks if the value of the field is `DPI_D19`"] + #[doc = "Pin is connected to DPI_D19"] #[inline(always)] pub fn is_dpi_d19(&self) -> bool { *self == FSEL23_A::DPI_D19 } - #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] pub fn is_sd1_cmd(&self) -> bool { *self == FSEL23_A::SD1_CMD } - #[doc = "Checks if the value of the field is `ARM_RTCK`"] + #[doc = "Pin is connected to ARM_RTCK"] #[inline(always)] pub fn is_arm_rtck(&self) -> bool { *self == FSEL23_A::ARM_RTCK } - #[doc = "Checks if the value of the field is `SCL6`"] + #[doc = "Pin is connected to SCL6"] #[inline(always)] pub fn is_scl6(&self) -> bool { *self == FSEL23_A::SCL6 } } #[doc = "Field `FSEL23` writer - Function Select 23"] -pub type FSEL23_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL23_A, 3, O>; -impl<'a, const O: u8> FSEL23_W<'a, O> { +pub type FSEL23_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL23_A>; +impl<'a, REG, const O: u8> FSEL23_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL23_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL23_A::OUTPUT) } #[doc = "Pin is connected to SD0_CMD"] #[inline(always)] - pub fn sd0_cmd(self) -> &'a mut W { + pub fn sd0_cmd(self) -> &'a mut crate::W { self.variant(FSEL23_A::SD0_CMD) } #[doc = "Pin is connected to SD15"] #[inline(always)] - pub fn sd15(self) -> &'a mut W { + pub fn sd15(self) -> &'a mut crate::W { self.variant(FSEL23_A::SD15) } #[doc = "Pin is connected to DPI_D19"] #[inline(always)] - pub fn dpi_d19(self) -> &'a mut W { + pub fn dpi_d19(self) -> &'a mut crate::W { self.variant(FSEL23_A::DPI_D19) } #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] - pub fn sd1_cmd(self) -> &'a mut W { + pub fn sd1_cmd(self) -> &'a mut crate::W { self.variant(FSEL23_A::SD1_CMD) } #[doc = "Pin is connected to ARM_RTCK"] #[inline(always)] - pub fn arm_rtck(self) -> &'a mut W { + pub fn arm_rtck(self) -> &'a mut crate::W { self.variant(FSEL23_A::ARM_RTCK) } #[doc = "Pin is connected to SCL6"] #[inline(always)] - pub fn scl6(self) -> &'a mut W { + pub fn scl6(self) -> &'a mut crate::W { self.variant(FSEL23_A::SCL6) } } #[doc = "Field `FSEL24` reader - Function Select 24"] -pub type FSEL24_R = crate::FieldReader; +pub type FSEL24_R = crate::FieldReader; #[doc = "Function Select 24"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL24_A { + type Ux = u8; +} impl FSEL24_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL24_A { + pub const fn variant(&self) -> FSEL24_A { match self.bits { 0 => FSEL24_A::INPUT, 1 => FSEL24_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL24_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL24_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL24_A::OUTPUT } - #[doc = "Checks if the value of the field is `SD0_DAT0`"] + #[doc = "Pin is connected to SD0_DAT0"] #[inline(always)] pub fn is_sd0_dat0(&self) -> bool { *self == FSEL24_A::SD0_DAT0 } - #[doc = "Checks if the value of the field is `SD16`"] + #[doc = "Pin is connected to SD16"] #[inline(always)] pub fn is_sd16(&self) -> bool { *self == FSEL24_A::SD16 } - #[doc = "Checks if the value of the field is `DPI_D20`"] + #[doc = "Pin is connected to DPI_D20"] #[inline(always)] pub fn is_dpi_d20(&self) -> bool { *self == FSEL24_A::DPI_D20 } - #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] pub fn is_sd1_dat0(&self) -> bool { *self == FSEL24_A::SD1_DAT0 } - #[doc = "Checks if the value of the field is `ARM_TDO`"] + #[doc = "Pin is connected to ARM_TDO"] #[inline(always)] pub fn is_arm_tdo(&self) -> bool { *self == FSEL24_A::ARM_TDO } - #[doc = "Checks if the value of the field is `SPI3_CE1_N`"] + #[doc = "Pin is connected to SPI3_CE1_N"] #[inline(always)] pub fn is_spi3_ce1_n(&self) -> bool { *self == FSEL24_A::SPI3_CE1_N } } #[doc = "Field `FSEL24` writer - Function Select 24"] -pub type FSEL24_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL24_A, 3, O>; -impl<'a, const O: u8> FSEL24_W<'a, O> { +pub type FSEL24_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL24_A>; +impl<'a, REG, const O: u8> FSEL24_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL24_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL24_A::OUTPUT) } #[doc = "Pin is connected to SD0_DAT0"] #[inline(always)] - pub fn sd0_dat0(self) -> &'a mut W { + pub fn sd0_dat0(self) -> &'a mut crate::W { self.variant(FSEL24_A::SD0_DAT0) } #[doc = "Pin is connected to SD16"] #[inline(always)] - pub fn sd16(self) -> &'a mut W { + pub fn sd16(self) -> &'a mut crate::W { self.variant(FSEL24_A::SD16) } #[doc = "Pin is connected to DPI_D20"] #[inline(always)] - pub fn dpi_d20(self) -> &'a mut W { + pub fn dpi_d20(self) -> &'a mut crate::W { self.variant(FSEL24_A::DPI_D20) } #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] - pub fn sd1_dat0(self) -> &'a mut W { + pub fn sd1_dat0(self) -> &'a mut crate::W { self.variant(FSEL24_A::SD1_DAT0) } #[doc = "Pin is connected to ARM_TDO"] #[inline(always)] - pub fn arm_tdo(self) -> &'a mut W { + pub fn arm_tdo(self) -> &'a mut crate::W { self.variant(FSEL24_A::ARM_TDO) } #[doc = "Pin is connected to SPI3_CE1_N"] #[inline(always)] - pub fn spi3_ce1_n(self) -> &'a mut W { + pub fn spi3_ce1_n(self) -> &'a mut crate::W { self.variant(FSEL24_A::SPI3_CE1_N) } } #[doc = "Field `FSEL25` reader - Function Select 25"] -pub type FSEL25_R = crate::FieldReader; +pub type FSEL25_R = crate::FieldReader; #[doc = "Function Select 25"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL25_A { + type Ux = u8; +} impl FSEL25_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL25_A { + pub const fn variant(&self) -> FSEL25_A { match self.bits { 0 => FSEL25_A::INPUT, 1 => FSEL25_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL25_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL25_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL25_A::OUTPUT } - #[doc = "Checks if the value of the field is `SD0_DAT1`"] + #[doc = "Pin is connected to SD0_DAT1"] #[inline(always)] pub fn is_sd0_dat1(&self) -> bool { *self == FSEL25_A::SD0_DAT1 } - #[doc = "Checks if the value of the field is `SD17`"] + #[doc = "Pin is connected to SD17"] #[inline(always)] pub fn is_sd17(&self) -> bool { *self == FSEL25_A::SD17 } - #[doc = "Checks if the value of the field is `DPI_D21`"] + #[doc = "Pin is connected to DPI_D21"] #[inline(always)] pub fn is_dpi_d21(&self) -> bool { *self == FSEL25_A::DPI_D21 } - #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] pub fn is_sd1_dat1(&self) -> bool { *self == FSEL25_A::SD1_DAT1 } - #[doc = "Checks if the value of the field is `ARM_TCK`"] + #[doc = "Pin is connected to ARM_TCK"] #[inline(always)] pub fn is_arm_tck(&self) -> bool { *self == FSEL25_A::ARM_TCK } - #[doc = "Checks if the value of the field is `SPI4_CE1_N`"] + #[doc = "Pin is connected to SPI4_CE1_N"] #[inline(always)] pub fn is_spi4_ce1_n(&self) -> bool { *self == FSEL25_A::SPI4_CE1_N } } #[doc = "Field `FSEL25` writer - Function Select 25"] -pub type FSEL25_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL25_A, 3, O>; -impl<'a, const O: u8> FSEL25_W<'a, O> { +pub type FSEL25_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL25_A>; +impl<'a, REG, const O: u8> FSEL25_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL25_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL25_A::OUTPUT) } #[doc = "Pin is connected to SD0_DAT1"] #[inline(always)] - pub fn sd0_dat1(self) -> &'a mut W { + pub fn sd0_dat1(self) -> &'a mut crate::W { self.variant(FSEL25_A::SD0_DAT1) } #[doc = "Pin is connected to SD17"] #[inline(always)] - pub fn sd17(self) -> &'a mut W { + pub fn sd17(self) -> &'a mut crate::W { self.variant(FSEL25_A::SD17) } #[doc = "Pin is connected to DPI_D21"] #[inline(always)] - pub fn dpi_d21(self) -> &'a mut W { + pub fn dpi_d21(self) -> &'a mut crate::W { self.variant(FSEL25_A::DPI_D21) } #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] - pub fn sd1_dat1(self) -> &'a mut W { + pub fn sd1_dat1(self) -> &'a mut crate::W { self.variant(FSEL25_A::SD1_DAT1) } #[doc = "Pin is connected to ARM_TCK"] #[inline(always)] - pub fn arm_tck(self) -> &'a mut W { + pub fn arm_tck(self) -> &'a mut crate::W { self.variant(FSEL25_A::ARM_TCK) } #[doc = "Pin is connected to SPI4_CE1_N"] #[inline(always)] - pub fn spi4_ce1_n(self) -> &'a mut W { + pub fn spi4_ce1_n(self) -> &'a mut crate::W { self.variant(FSEL25_A::SPI4_CE1_N) } } #[doc = "Field `FSEL26` reader - Function Select 26"] -pub type FSEL26_R = crate::FieldReader; +pub type FSEL26_R = crate::FieldReader; #[doc = "Function Select 26"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL26_A { + type Ux = u8; +} impl FSEL26_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL26_A { + pub const fn variant(&self) -> FSEL26_A { match self.bits { 0 => FSEL26_A::INPUT, 1 => FSEL26_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL26_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL26_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL26_A::OUTPUT } - #[doc = "Checks if the value of the field is `SD0_DAT2`"] + #[doc = "Pin is connected to SD0_DAT2"] #[inline(always)] pub fn is_sd0_dat2(&self) -> bool { *self == FSEL26_A::SD0_DAT2 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL26_A::RESERVED1 } - #[doc = "Checks if the value of the field is `DPI_D22`"] + #[doc = "Pin is connected to DPI_D22"] #[inline(always)] pub fn is_dpi_d22(&self) -> bool { *self == FSEL26_A::DPI_D22 } - #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] pub fn is_sd1_dat2(&self) -> bool { *self == FSEL26_A::SD1_DAT2 } - #[doc = "Checks if the value of the field is `ARM_TDI`"] + #[doc = "Pin is connected to ARM_TDI"] #[inline(always)] pub fn is_arm_tdi(&self) -> bool { *self == FSEL26_A::ARM_TDI } - #[doc = "Checks if the value of the field is `SPI5_CE1_N`"] + #[doc = "Pin is connected to SPI5_CE1_N"] #[inline(always)] pub fn is_spi5_ce1_n(&self) -> bool { *self == FSEL26_A::SPI5_CE1_N } } #[doc = "Field `FSEL26` writer - Function Select 26"] -pub type FSEL26_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL26_A, 3, O>; -impl<'a, const O: u8> FSEL26_W<'a, O> { +pub type FSEL26_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL26_A>; +impl<'a, REG, const O: u8> FSEL26_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL26_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL26_A::OUTPUT) } #[doc = "Pin is connected to SD0_DAT2"] #[inline(always)] - pub fn sd0_dat2(self) -> &'a mut W { + pub fn sd0_dat2(self) -> &'a mut crate::W { self.variant(FSEL26_A::SD0_DAT2) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL26_A::RESERVED1) } #[doc = "Pin is connected to DPI_D22"] #[inline(always)] - pub fn dpi_d22(self) -> &'a mut W { + pub fn dpi_d22(self) -> &'a mut crate::W { self.variant(FSEL26_A::DPI_D22) } #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] - pub fn sd1_dat2(self) -> &'a mut W { + pub fn sd1_dat2(self) -> &'a mut crate::W { self.variant(FSEL26_A::SD1_DAT2) } #[doc = "Pin is connected to ARM_TDI"] #[inline(always)] - pub fn arm_tdi(self) -> &'a mut W { + pub fn arm_tdi(self) -> &'a mut crate::W { self.variant(FSEL26_A::ARM_TDI) } #[doc = "Pin is connected to SPI5_CE1_N"] #[inline(always)] - pub fn spi5_ce1_n(self) -> &'a mut W { + pub fn spi5_ce1_n(self) -> &'a mut crate::W { self.variant(FSEL26_A::SPI5_CE1_N) } } #[doc = "Field `FSEL27` reader - Function Select 27"] -pub type FSEL27_R = crate::FieldReader; +pub type FSEL27_R = crate::FieldReader; #[doc = "Function Select 27"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL27_A { + type Ux = u8; +} impl FSEL27_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL27_A { + pub const fn variant(&self) -> FSEL27_A { match self.bits { 0 => FSEL27_A::INPUT, 1 => FSEL27_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL27_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL27_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL27_A::OUTPUT } - #[doc = "Checks if the value of the field is `SD0_DAT3`"] + #[doc = "Pin is connected to SD0_DAT3"] #[inline(always)] pub fn is_sd0_dat3(&self) -> bool { *self == FSEL27_A::SD0_DAT3 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL27_A::RESERVED1 } - #[doc = "Checks if the value of the field is `DPI_D23`"] + #[doc = "Pin is connected to DPI_D23"] #[inline(always)] pub fn is_dpi_d23(&self) -> bool { *self == FSEL27_A::DPI_D23 } - #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] pub fn is_sd1_dat3(&self) -> bool { *self == FSEL27_A::SD1_DAT3 } - #[doc = "Checks if the value of the field is `ARM_TMS`"] + #[doc = "Pin is connected to ARM_TMS"] #[inline(always)] pub fn is_arm_tms(&self) -> bool { *self == FSEL27_A::ARM_TMS } - #[doc = "Checks if the value of the field is `SPI6_CE1_N`"] + #[doc = "Pin is connected to SPI6_CE1_N"] #[inline(always)] pub fn is_spi6_ce1_n(&self) -> bool { *self == FSEL27_A::SPI6_CE1_N } } #[doc = "Field `FSEL27` writer - Function Select 27"] -pub type FSEL27_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL27_A, 3, O>; -impl<'a, const O: u8> FSEL27_W<'a, O> { +pub type FSEL27_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL27_A>; +impl<'a, REG, const O: u8> FSEL27_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL27_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL27_A::OUTPUT) } #[doc = "Pin is connected to SD0_DAT3"] #[inline(always)] - pub fn sd0_dat3(self) -> &'a mut W { + pub fn sd0_dat3(self) -> &'a mut crate::W { self.variant(FSEL27_A::SD0_DAT3) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL27_A::RESERVED1) } #[doc = "Pin is connected to DPI_D23"] #[inline(always)] - pub fn dpi_d23(self) -> &'a mut W { + pub fn dpi_d23(self) -> &'a mut crate::W { self.variant(FSEL27_A::DPI_D23) } #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] - pub fn sd1_dat3(self) -> &'a mut W { + pub fn sd1_dat3(self) -> &'a mut crate::W { self.variant(FSEL27_A::SD1_DAT3) } #[doc = "Pin is connected to ARM_TMS"] #[inline(always)] - pub fn arm_tms(self) -> &'a mut W { + pub fn arm_tms(self) -> &'a mut crate::W { self.variant(FSEL27_A::ARM_TMS) } #[doc = "Pin is connected to SPI6_CE1_N"] #[inline(always)] - pub fn spi6_ce1_n(self) -> &'a mut W { + pub fn spi6_ce1_n(self) -> &'a mut crate::W { self.variant(FSEL27_A::SPI6_CE1_N) } } #[doc = "Field `FSEL28` reader - Function Select 28"] -pub type FSEL28_R = crate::FieldReader; +pub type FSEL28_R = crate::FieldReader; #[doc = "Function Select 28"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL28_A { + type Ux = u8; +} impl FSEL28_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL28_A { + pub const fn variant(&self) -> FSEL28_A { match self.bits { 0 => FSEL28_A::INPUT, 1 => FSEL28_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL28_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL28_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL28_A::OUTPUT } - #[doc = "Checks if the value of the field is `SDA0`"] + #[doc = "Pin is connected to SDA0"] #[inline(always)] pub fn is_sda0(&self) -> bool { *self == FSEL28_A::SDA0 } - #[doc = "Checks if the value of the field is `SA5`"] + #[doc = "Pin is connected to SA5"] #[inline(always)] pub fn is_sa5(&self) -> bool { *self == FSEL28_A::SA5 } - #[doc = "Checks if the value of the field is `PCM_CLK`"] + #[doc = "Pin is connected to PCM_CLK"] #[inline(always)] pub fn is_pcm_clk(&self) -> bool { *self == FSEL28_A::PCM_CLK } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL28_A::RESERVED3 } - #[doc = "Checks if the value of the field is `MII_A_RX_ERR`"] + #[doc = "Pin is connected to MII_A_RX_ERR"] #[inline(always)] pub fn is_mii_a_rx_err(&self) -> bool { *self == FSEL28_A::MII_A_RX_ERR } - #[doc = "Checks if the value of the field is `RGMII_MDIO`"] + #[doc = "Pin is connected to RGMII_MDIO"] #[inline(always)] pub fn is_rgmii_mdio(&self) -> bool { *self == FSEL28_A::RGMII_MDIO } } #[doc = "Field `FSEL28` writer - Function Select 28"] -pub type FSEL28_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL28_A, 3, O>; -impl<'a, const O: u8> FSEL28_W<'a, O> { +pub type FSEL28_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL28_A>; +impl<'a, REG, const O: u8> FSEL28_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL28_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL28_A::OUTPUT) } #[doc = "Pin is connected to SDA0"] #[inline(always)] - pub fn sda0(self) -> &'a mut W { + pub fn sda0(self) -> &'a mut crate::W { self.variant(FSEL28_A::SDA0) } #[doc = "Pin is connected to SA5"] #[inline(always)] - pub fn sa5(self) -> &'a mut W { + pub fn sa5(self) -> &'a mut crate::W { self.variant(FSEL28_A::SA5) } #[doc = "Pin is connected to PCM_CLK"] #[inline(always)] - pub fn pcm_clk(self) -> &'a mut W { + pub fn pcm_clk(self) -> &'a mut crate::W { self.variant(FSEL28_A::PCM_CLK) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL28_A::RESERVED3) } #[doc = "Pin is connected to MII_A_RX_ERR"] #[inline(always)] - pub fn mii_a_rx_err(self) -> &'a mut W { + pub fn mii_a_rx_err(self) -> &'a mut crate::W { self.variant(FSEL28_A::MII_A_RX_ERR) } #[doc = "Pin is connected to RGMII_MDIO"] #[inline(always)] - pub fn rgmii_mdio(self) -> &'a mut W { + pub fn rgmii_mdio(self) -> &'a mut crate::W { self.variant(FSEL28_A::RGMII_MDIO) } } #[doc = "Field `FSEL29` reader - Function Select 29"] -pub type FSEL29_R = crate::FieldReader; +pub type FSEL29_R = crate::FieldReader; #[doc = "Function Select 29"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL29_A { + type Ux = u8; +} impl FSEL29_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL29_A { + pub const fn variant(&self) -> FSEL29_A { match self.bits { 0 => FSEL29_A::INPUT, 1 => FSEL29_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL29_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL29_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL29_A::OUTPUT } - #[doc = "Checks if the value of the field is `SCL0`"] + #[doc = "Pin is connected to SCL0"] #[inline(always)] pub fn is_scl0(&self) -> bool { *self == FSEL29_A::SCL0 } - #[doc = "Checks if the value of the field is `SA4`"] + #[doc = "Pin is connected to SA4"] #[inline(always)] pub fn is_sa4(&self) -> bool { *self == FSEL29_A::SA4 } - #[doc = "Checks if the value of the field is `PCM_FS`"] + #[doc = "Pin is connected to PCM_FS"] #[inline(always)] pub fn is_pcm_fs(&self) -> bool { *self == FSEL29_A::PCM_FS } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL29_A::RESERVED3 } - #[doc = "Checks if the value of the field is `MII_A_TX_ERR`"] + #[doc = "Pin is connected to MII_A_TX_ERR"] #[inline(always)] pub fn is_mii_a_tx_err(&self) -> bool { *self == FSEL29_A::MII_A_TX_ERR } - #[doc = "Checks if the value of the field is `RGMII_MDC`"] + #[doc = "Pin is connected to RGMII_MDC"] #[inline(always)] pub fn is_rgmii_mdc(&self) -> bool { *self == FSEL29_A::RGMII_MDC } } #[doc = "Field `FSEL29` writer - Function Select 29"] -pub type FSEL29_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL29_A, 3, O>; -impl<'a, const O: u8> FSEL29_W<'a, O> { +pub type FSEL29_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL29_A>; +impl<'a, REG, const O: u8> FSEL29_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL29_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL29_A::OUTPUT) } #[doc = "Pin is connected to SCL0"] #[inline(always)] - pub fn scl0(self) -> &'a mut W { + pub fn scl0(self) -> &'a mut crate::W { self.variant(FSEL29_A::SCL0) } #[doc = "Pin is connected to SA4"] #[inline(always)] - pub fn sa4(self) -> &'a mut W { + pub fn sa4(self) -> &'a mut crate::W { self.variant(FSEL29_A::SA4) } #[doc = "Pin is connected to PCM_FS"] #[inline(always)] - pub fn pcm_fs(self) -> &'a mut W { + pub fn pcm_fs(self) -> &'a mut crate::W { self.variant(FSEL29_A::PCM_FS) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL29_A::RESERVED3) } #[doc = "Pin is connected to MII_A_TX_ERR"] #[inline(always)] - pub fn mii_a_tx_err(self) -> &'a mut W { + pub fn mii_a_tx_err(self) -> &'a mut crate::W { self.variant(FSEL29_A::MII_A_TX_ERR) } #[doc = "Pin is connected to RGMII_MDC"] #[inline(always)] - pub fn rgmii_mdc(self) -> &'a mut W { + pub fn rgmii_mdc(self) -> &'a mut crate::W { self.variant(FSEL29_A::RGMII_MDC) } } @@ -1396,86 +1424,108 @@ impl R { FSEL29_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL2") + .field("fsel20", &format_args!("{}", self.fsel20().bits())) + .field("fsel21", &format_args!("{}", self.fsel21().bits())) + .field("fsel22", &format_args!("{}", self.fsel22().bits())) + .field("fsel23", &format_args!("{}", self.fsel23().bits())) + .field("fsel24", &format_args!("{}", self.fsel24().bits())) + .field("fsel25", &format_args!("{}", self.fsel25().bits())) + .field("fsel26", &format_args!("{}", self.fsel26().bits())) + .field("fsel27", &format_args!("{}", self.fsel27().bits())) + .field("fsel28", &format_args!("{}", self.fsel28().bits())) + .field("fsel29", &format_args!("{}", self.fsel29().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 20"] #[inline(always)] #[must_use] - pub fn fsel20(&mut self) -> FSEL20_W<0> { + pub fn fsel20(&mut self) -> FSEL20_W { FSEL20_W::new(self) } #[doc = "Bits 3:5 - Function Select 21"] #[inline(always)] #[must_use] - pub fn fsel21(&mut self) -> FSEL21_W<3> { + pub fn fsel21(&mut self) -> FSEL21_W { FSEL21_W::new(self) } #[doc = "Bits 6:8 - Function Select 22"] #[inline(always)] #[must_use] - pub fn fsel22(&mut self) -> FSEL22_W<6> { + pub fn fsel22(&mut self) -> FSEL22_W { FSEL22_W::new(self) } #[doc = "Bits 9:11 - Function Select 23"] #[inline(always)] #[must_use] - pub fn fsel23(&mut self) -> FSEL23_W<9> { + pub fn fsel23(&mut self) -> FSEL23_W { FSEL23_W::new(self) } #[doc = "Bits 12:14 - Function Select 24"] #[inline(always)] #[must_use] - pub fn fsel24(&mut self) -> FSEL24_W<12> { + pub fn fsel24(&mut self) -> FSEL24_W { FSEL24_W::new(self) } #[doc = "Bits 15:17 - Function Select 25"] #[inline(always)] #[must_use] - pub fn fsel25(&mut self) -> FSEL25_W<15> { + pub fn fsel25(&mut self) -> FSEL25_W { FSEL25_W::new(self) } #[doc = "Bits 18:20 - Function Select 26"] #[inline(always)] #[must_use] - pub fn fsel26(&mut self) -> FSEL26_W<18> { + pub fn fsel26(&mut self) -> FSEL26_W { FSEL26_W::new(self) } #[doc = "Bits 21:23 - Function Select 27"] #[inline(always)] #[must_use] - pub fn fsel27(&mut self) -> FSEL27_W<21> { + pub fn fsel27(&mut self) -> FSEL27_W { FSEL27_W::new(self) } #[doc = "Bits 24:26 - Function Select 28"] #[inline(always)] #[must_use] - pub fn fsel28(&mut self) -> FSEL28_W<24> { + pub fn fsel28(&mut self) -> FSEL28_W { FSEL28_W::new(self) } #[doc = "Bits 27:29 - Function Select 29"] #[inline(always)] #[must_use] - pub fn fsel29(&mut self) -> FSEL29_W<27> { + pub fn fsel29(&mut self) -> FSEL29_W { FSEL29_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel2](index.html) module"] +#[doc = "GPIO Function Select 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL2_SPEC; impl crate::RegisterSpec for GPFSEL2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel2::R](R) reader structure"] -impl crate::Readable for GPFSEL2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel2::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel2::R`](R) reader structure"] +impl crate::Readable for GPFSEL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel2::W`](W) writer structure"] impl crate::Writable for GPFSEL2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpfsel3.rs b/crates/bcm2711-lpa/src/gpio/gpfsel3.rs index 892eabb..a666a0b 100644 --- a/crates/bcm2711-lpa/src/gpio/gpfsel3.rs +++ b/crates/bcm2711-lpa/src/gpio/gpfsel3.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL30` reader - Function Select 30"] -pub type FSEL30_R = crate::FieldReader; +pub type FSEL30_R = crate::FieldReader; #[doc = "Function Select 30"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL30_A { + type Ux = u8; +} impl FSEL30_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL30_A { + pub const fn variant(&self) -> FSEL30_A { match self.bits { 0 => FSEL30_A::INPUT, 1 => FSEL30_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL30_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL30_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL30_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL30_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SA3`"] + #[doc = "Pin is connected to SA3"] #[inline(always)] pub fn is_sa3(&self) -> bool { *self == FSEL30_A::SA3 } - #[doc = "Checks if the value of the field is `PCM_DIN`"] + #[doc = "Pin is connected to PCM_DIN"] #[inline(always)] pub fn is_pcm_din(&self) -> bool { *self == FSEL30_A::PCM_DIN } - #[doc = "Checks if the value of the field is `CTS0`"] + #[doc = "Pin is connected to CTS0"] #[inline(always)] pub fn is_cts0(&self) -> bool { *self == FSEL30_A::CTS0 } - #[doc = "Checks if the value of the field is `MII_A_CRS`"] + #[doc = "Pin is connected to MII_A_CRS"] #[inline(always)] pub fn is_mii_a_crs(&self) -> bool { *self == FSEL30_A::MII_A_CRS } - #[doc = "Checks if the value of the field is `CTS1`"] + #[doc = "Pin is connected to CTS1"] #[inline(always)] pub fn is_cts1(&self) -> bool { *self == FSEL30_A::CTS1 } } #[doc = "Field `FSEL30` writer - Function Select 30"] -pub type FSEL30_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL30_A, 3, O>; -impl<'a, const O: u8> FSEL30_W<'a, O> { +pub type FSEL30_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL30_A>; +impl<'a, REG, const O: u8> FSEL30_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL30_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL30_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL30_A::RESERVED0) } #[doc = "Pin is connected to SA3"] #[inline(always)] - pub fn sa3(self) -> &'a mut W { + pub fn sa3(self) -> &'a mut crate::W { self.variant(FSEL30_A::SA3) } #[doc = "Pin is connected to PCM_DIN"] #[inline(always)] - pub fn pcm_din(self) -> &'a mut W { + pub fn pcm_din(self) -> &'a mut crate::W { self.variant(FSEL30_A::PCM_DIN) } #[doc = "Pin is connected to CTS0"] #[inline(always)] - pub fn cts0(self) -> &'a mut W { + pub fn cts0(self) -> &'a mut crate::W { self.variant(FSEL30_A::CTS0) } #[doc = "Pin is connected to MII_A_CRS"] #[inline(always)] - pub fn mii_a_crs(self) -> &'a mut W { + pub fn mii_a_crs(self) -> &'a mut crate::W { self.variant(FSEL30_A::MII_A_CRS) } #[doc = "Pin is connected to CTS1"] #[inline(always)] - pub fn cts1(self) -> &'a mut W { + pub fn cts1(self) -> &'a mut crate::W { self.variant(FSEL30_A::CTS1) } } #[doc = "Field `FSEL31` reader - Function Select 31"] -pub type FSEL31_R = crate::FieldReader; +pub type FSEL31_R = crate::FieldReader; #[doc = "Function Select 31"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL31_A { + type Ux = u8; +} impl FSEL31_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL31_A { + pub const fn variant(&self) -> FSEL31_A { match self.bits { 0 => FSEL31_A::INPUT, 1 => FSEL31_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL31_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL31_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL31_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL31_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SA2`"] + #[doc = "Pin is connected to SA2"] #[inline(always)] pub fn is_sa2(&self) -> bool { *self == FSEL31_A::SA2 } - #[doc = "Checks if the value of the field is `PCM_DOUT`"] + #[doc = "Pin is connected to PCM_DOUT"] #[inline(always)] pub fn is_pcm_dout(&self) -> bool { *self == FSEL31_A::PCM_DOUT } - #[doc = "Checks if the value of the field is `RTS0`"] + #[doc = "Pin is connected to RTS0"] #[inline(always)] pub fn is_rts0(&self) -> bool { *self == FSEL31_A::RTS0 } - #[doc = "Checks if the value of the field is `MII_A_COL`"] + #[doc = "Pin is connected to MII_A_COL"] #[inline(always)] pub fn is_mii_a_col(&self) -> bool { *self == FSEL31_A::MII_A_COL } - #[doc = "Checks if the value of the field is `RTS1`"] + #[doc = "Pin is connected to RTS1"] #[inline(always)] pub fn is_rts1(&self) -> bool { *self == FSEL31_A::RTS1 } } #[doc = "Field `FSEL31` writer - Function Select 31"] -pub type FSEL31_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL31_A, 3, O>; -impl<'a, const O: u8> FSEL31_W<'a, O> { +pub type FSEL31_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL31_A>; +impl<'a, REG, const O: u8> FSEL31_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL31_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL31_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL31_A::RESERVED0) } #[doc = "Pin is connected to SA2"] #[inline(always)] - pub fn sa2(self) -> &'a mut W { + pub fn sa2(self) -> &'a mut crate::W { self.variant(FSEL31_A::SA2) } #[doc = "Pin is connected to PCM_DOUT"] #[inline(always)] - pub fn pcm_dout(self) -> &'a mut W { + pub fn pcm_dout(self) -> &'a mut crate::W { self.variant(FSEL31_A::PCM_DOUT) } #[doc = "Pin is connected to RTS0"] #[inline(always)] - pub fn rts0(self) -> &'a mut W { + pub fn rts0(self) -> &'a mut crate::W { self.variant(FSEL31_A::RTS0) } #[doc = "Pin is connected to MII_A_COL"] #[inline(always)] - pub fn mii_a_col(self) -> &'a mut W { + pub fn mii_a_col(self) -> &'a mut crate::W { self.variant(FSEL31_A::MII_A_COL) } #[doc = "Pin is connected to RTS1"] #[inline(always)] - pub fn rts1(self) -> &'a mut W { + pub fn rts1(self) -> &'a mut crate::W { self.variant(FSEL31_A::RTS1) } } #[doc = "Field `FSEL32` reader - Function Select 32"] -pub type FSEL32_R = crate::FieldReader; +pub type FSEL32_R = crate::FieldReader; #[doc = "Function Select 32"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL32_A { + type Ux = u8; +} impl FSEL32_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL32_A { + pub const fn variant(&self) -> FSEL32_A { match self.bits { 0 => FSEL32_A::INPUT, 1 => FSEL32_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL32_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL32_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL32_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK0`"] + #[doc = "Pin is connected to GPCLK0"] #[inline(always)] pub fn is_gpclk0(&self) -> bool { *self == FSEL32_A::GPCLK0 } - #[doc = "Checks if the value of the field is `SA1`"] + #[doc = "Pin is connected to SA1"] #[inline(always)] pub fn is_sa1(&self) -> bool { *self == FSEL32_A::SA1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL32_A::RESERVED2 } - #[doc = "Checks if the value of the field is `TXD0`"] + #[doc = "Pin is connected to TXD0"] #[inline(always)] pub fn is_txd0(&self) -> bool { *self == FSEL32_A::TXD0 } - #[doc = "Checks if the value of the field is `SD_CARD_PRES`"] + #[doc = "Pin is connected to SD_CARD_PRES"] #[inline(always)] pub fn is_sd_card_pres(&self) -> bool { *self == FSEL32_A::SD_CARD_PRES } - #[doc = "Checks if the value of the field is `TXD1`"] + #[doc = "Pin is connected to TXD1"] #[inline(always)] pub fn is_txd1(&self) -> bool { *self == FSEL32_A::TXD1 } } #[doc = "Field `FSEL32` writer - Function Select 32"] -pub type FSEL32_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL32_A, 3, O>; -impl<'a, const O: u8> FSEL32_W<'a, O> { +pub type FSEL32_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL32_A>; +impl<'a, REG, const O: u8> FSEL32_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL32_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL32_A::OUTPUT) } #[doc = "Pin is connected to GPCLK0"] #[inline(always)] - pub fn gpclk0(self) -> &'a mut W { + pub fn gpclk0(self) -> &'a mut crate::W { self.variant(FSEL32_A::GPCLK0) } #[doc = "Pin is connected to SA1"] #[inline(always)] - pub fn sa1(self) -> &'a mut W { + pub fn sa1(self) -> &'a mut crate::W { self.variant(FSEL32_A::SA1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL32_A::RESERVED2) } #[doc = "Pin is connected to TXD0"] #[inline(always)] - pub fn txd0(self) -> &'a mut W { + pub fn txd0(self) -> &'a mut crate::W { self.variant(FSEL32_A::TXD0) } #[doc = "Pin is connected to SD_CARD_PRES"] #[inline(always)] - pub fn sd_card_pres(self) -> &'a mut W { + pub fn sd_card_pres(self) -> &'a mut crate::W { self.variant(FSEL32_A::SD_CARD_PRES) } #[doc = "Pin is connected to TXD1"] #[inline(always)] - pub fn txd1(self) -> &'a mut W { + pub fn txd1(self) -> &'a mut crate::W { self.variant(FSEL32_A::TXD1) } } #[doc = "Field `FSEL33` reader - Function Select 33"] -pub type FSEL33_R = crate::FieldReader; +pub type FSEL33_R = crate::FieldReader; #[doc = "Function Select 33"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL33_A { + type Ux = u8; +} impl FSEL33_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL33_A { + pub const fn variant(&self) -> FSEL33_A { match self.bits { 0 => FSEL33_A::INPUT, 1 => FSEL33_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL33_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL33_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL33_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL33_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SA0`"] + #[doc = "Pin is connected to SA0"] #[inline(always)] pub fn is_sa0(&self) -> bool { *self == FSEL33_A::SA0 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL33_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RXD0`"] + #[doc = "Pin is connected to RXD0"] #[inline(always)] pub fn is_rxd0(&self) -> bool { *self == FSEL33_A::RXD0 } - #[doc = "Checks if the value of the field is `SD_CARD_WRPROT`"] + #[doc = "Pin is connected to SD_CARD_WRPROT"] #[inline(always)] pub fn is_sd_card_wrprot(&self) -> bool { *self == FSEL33_A::SD_CARD_WRPROT } - #[doc = "Checks if the value of the field is `RXD1`"] + #[doc = "Pin is connected to RXD1"] #[inline(always)] pub fn is_rxd1(&self) -> bool { *self == FSEL33_A::RXD1 } } #[doc = "Field `FSEL33` writer - Function Select 33"] -pub type FSEL33_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL33_A, 3, O>; -impl<'a, const O: u8> FSEL33_W<'a, O> { +pub type FSEL33_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL33_A>; +impl<'a, REG, const O: u8> FSEL33_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL33_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL33_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL33_A::RESERVED0) } #[doc = "Pin is connected to SA0"] #[inline(always)] - pub fn sa0(self) -> &'a mut W { + pub fn sa0(self) -> &'a mut crate::W { self.variant(FSEL33_A::SA0) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL33_A::RESERVED2) } #[doc = "Pin is connected to RXD0"] #[inline(always)] - pub fn rxd0(self) -> &'a mut W { + pub fn rxd0(self) -> &'a mut crate::W { self.variant(FSEL33_A::RXD0) } #[doc = "Pin is connected to SD_CARD_WRPROT"] #[inline(always)] - pub fn sd_card_wrprot(self) -> &'a mut W { + pub fn sd_card_wrprot(self) -> &'a mut crate::W { self.variant(FSEL33_A::SD_CARD_WRPROT) } #[doc = "Pin is connected to RXD1"] #[inline(always)] - pub fn rxd1(self) -> &'a mut W { + pub fn rxd1(self) -> &'a mut crate::W { self.variant(FSEL33_A::RXD1) } } #[doc = "Field `FSEL34` reader - Function Select 34"] -pub type FSEL34_R = crate::FieldReader; +pub type FSEL34_R = crate::FieldReader; #[doc = "Function Select 34"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL34_A { + type Ux = u8; +} impl FSEL34_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL34_A { + pub const fn variant(&self) -> FSEL34_A { match self.bits { 0 => FSEL34_A::INPUT, 1 => FSEL34_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL34_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL34_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL34_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK0`"] + #[doc = "Pin is connected to GPCLK0"] #[inline(always)] pub fn is_gpclk0(&self) -> bool { *self == FSEL34_A::GPCLK0 } - #[doc = "Checks if the value of the field is `SOE_N`"] + #[doc = "Pin is connected to SOE_N"] #[inline(always)] pub fn is_soe_n(&self) -> bool { *self == FSEL34_A::SOE_N } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL34_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] pub fn is_sd1_clk(&self) -> bool { *self == FSEL34_A::SD1_CLK } - #[doc = "Checks if the value of the field is `SD_CARD_LED`"] + #[doc = "Pin is connected to SD_CARD_LED"] #[inline(always)] pub fn is_sd_card_led(&self) -> bool { *self == FSEL34_A::SD_CARD_LED } - #[doc = "Checks if the value of the field is `RGMII_IRQ`"] + #[doc = "Pin is connected to RGMII_IRQ"] #[inline(always)] pub fn is_rgmii_irq(&self) -> bool { *self == FSEL34_A::RGMII_IRQ } } #[doc = "Field `FSEL34` writer - Function Select 34"] -pub type FSEL34_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL34_A, 3, O>; -impl<'a, const O: u8> FSEL34_W<'a, O> { +pub type FSEL34_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL34_A>; +impl<'a, REG, const O: u8> FSEL34_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL34_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL34_A::OUTPUT) } #[doc = "Pin is connected to GPCLK0"] #[inline(always)] - pub fn gpclk0(self) -> &'a mut W { + pub fn gpclk0(self) -> &'a mut crate::W { self.variant(FSEL34_A::GPCLK0) } #[doc = "Pin is connected to SOE_N"] #[inline(always)] - pub fn soe_n(self) -> &'a mut W { + pub fn soe_n(self) -> &'a mut crate::W { self.variant(FSEL34_A::SOE_N) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL34_A::RESERVED2) } #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] - pub fn sd1_clk(self) -> &'a mut W { + pub fn sd1_clk(self) -> &'a mut crate::W { self.variant(FSEL34_A::SD1_CLK) } #[doc = "Pin is connected to SD_CARD_LED"] #[inline(always)] - pub fn sd_card_led(self) -> &'a mut W { + pub fn sd_card_led(self) -> &'a mut crate::W { self.variant(FSEL34_A::SD_CARD_LED) } #[doc = "Pin is connected to RGMII_IRQ"] #[inline(always)] - pub fn rgmii_irq(self) -> &'a mut W { + pub fn rgmii_irq(self) -> &'a mut crate::W { self.variant(FSEL34_A::RGMII_IRQ) } } #[doc = "Field `FSEL35` reader - Function Select 35"] -pub type FSEL35_R = crate::FieldReader; +pub type FSEL35_R = crate::FieldReader; #[doc = "Function Select 35"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL35_A { + type Ux = u8; +} impl FSEL35_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL35_A { + pub const fn variant(&self) -> FSEL35_A { match self.bits { 0 => FSEL35_A::INPUT, 1 => FSEL35_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL35_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL35_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL35_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_CE1_N`"] + #[doc = "Pin is connected to SPI0_CE1_N"] #[inline(always)] pub fn is_spi0_ce1_n(&self) -> bool { *self == FSEL35_A::SPI0_CE1_N } - #[doc = "Checks if the value of the field is `SWE_N`"] + #[doc = "Pin is connected to SWE_N"] #[inline(always)] pub fn is_swe_n(&self) -> bool { *self == FSEL35_A::SWE_N } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL35_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] pub fn is_sd1_cmd(&self) -> bool { *self == FSEL35_A::SD1_CMD } - #[doc = "Checks if the value of the field is `RGMII_START_STOP`"] + #[doc = "Pin is connected to RGMII_START_STOP"] #[inline(always)] pub fn is_rgmii_start_stop(&self) -> bool { *self == FSEL35_A::RGMII_START_STOP } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL35_A::RESERVED5 } } #[doc = "Field `FSEL35` writer - Function Select 35"] -pub type FSEL35_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL35_A, 3, O>; -impl<'a, const O: u8> FSEL35_W<'a, O> { +pub type FSEL35_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL35_A>; +impl<'a, REG, const O: u8> FSEL35_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL35_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL35_A::OUTPUT) } #[doc = "Pin is connected to SPI0_CE1_N"] #[inline(always)] - pub fn spi0_ce1_n(self) -> &'a mut W { + pub fn spi0_ce1_n(self) -> &'a mut crate::W { self.variant(FSEL35_A::SPI0_CE1_N) } #[doc = "Pin is connected to SWE_N"] #[inline(always)] - pub fn swe_n(self) -> &'a mut W { + pub fn swe_n(self) -> &'a mut crate::W { self.variant(FSEL35_A::SWE_N) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL35_A::RESERVED2) } #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] - pub fn sd1_cmd(self) -> &'a mut W { + pub fn sd1_cmd(self) -> &'a mut crate::W { self.variant(FSEL35_A::SD1_CMD) } #[doc = "Pin is connected to RGMII_START_STOP"] #[inline(always)] - pub fn rgmii_start_stop(self) -> &'a mut W { + pub fn rgmii_start_stop(self) -> &'a mut crate::W { self.variant(FSEL35_A::RGMII_START_STOP) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL35_A::RESERVED5) } } #[doc = "Field `FSEL36` reader - Function Select 36"] -pub type FSEL36_R = crate::FieldReader; +pub type FSEL36_R = crate::FieldReader; #[doc = "Function Select 36"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL36_A { + type Ux = u8; +} impl FSEL36_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL36_A { + pub const fn variant(&self) -> FSEL36_A { match self.bits { 0 => FSEL36_A::INPUT, 1 => FSEL36_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL36_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL36_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL36_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_CE0_N`"] + #[doc = "Pin is connected to SPI0_CE0_N"] #[inline(always)] pub fn is_spi0_ce0_n(&self) -> bool { *self == FSEL36_A::SPI0_CE0_N } - #[doc = "Checks if the value of the field is `SD0`"] + #[doc = "Pin is connected to SD0"] #[inline(always)] pub fn is_sd0(&self) -> bool { *self == FSEL36_A::SD0 } - #[doc = "Checks if the value of the field is `TXD0`"] + #[doc = "Pin is connected to TXD0"] #[inline(always)] pub fn is_txd0(&self) -> bool { *self == FSEL36_A::TXD0 } - #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] pub fn is_sd1_dat0(&self) -> bool { *self == FSEL36_A::SD1_DAT0 } - #[doc = "Checks if the value of the field is `RGMII_RX_OK`"] + #[doc = "Pin is connected to RGMII_RX_OK"] #[inline(always)] pub fn is_rgmii_rx_ok(&self) -> bool { *self == FSEL36_A::RGMII_RX_OK } - #[doc = "Checks if the value of the field is `MII_A_RX_ERR`"] + #[doc = "Pin is connected to MII_A_RX_ERR"] #[inline(always)] pub fn is_mii_a_rx_err(&self) -> bool { *self == FSEL36_A::MII_A_RX_ERR } } #[doc = "Field `FSEL36` writer - Function Select 36"] -pub type FSEL36_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL36_A, 3, O>; -impl<'a, const O: u8> FSEL36_W<'a, O> { +pub type FSEL36_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL36_A>; +impl<'a, REG, const O: u8> FSEL36_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL36_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL36_A::OUTPUT) } #[doc = "Pin is connected to SPI0_CE0_N"] #[inline(always)] - pub fn spi0_ce0_n(self) -> &'a mut W { + pub fn spi0_ce0_n(self) -> &'a mut crate::W { self.variant(FSEL36_A::SPI0_CE0_N) } #[doc = "Pin is connected to SD0"] #[inline(always)] - pub fn sd0(self) -> &'a mut W { + pub fn sd0(self) -> &'a mut crate::W { self.variant(FSEL36_A::SD0) } #[doc = "Pin is connected to TXD0"] #[inline(always)] - pub fn txd0(self) -> &'a mut W { + pub fn txd0(self) -> &'a mut crate::W { self.variant(FSEL36_A::TXD0) } #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] - pub fn sd1_dat0(self) -> &'a mut W { + pub fn sd1_dat0(self) -> &'a mut crate::W { self.variant(FSEL36_A::SD1_DAT0) } #[doc = "Pin is connected to RGMII_RX_OK"] #[inline(always)] - pub fn rgmii_rx_ok(self) -> &'a mut W { + pub fn rgmii_rx_ok(self) -> &'a mut crate::W { self.variant(FSEL36_A::RGMII_RX_OK) } #[doc = "Pin is connected to MII_A_RX_ERR"] #[inline(always)] - pub fn mii_a_rx_err(self) -> &'a mut W { + pub fn mii_a_rx_err(self) -> &'a mut crate::W { self.variant(FSEL36_A::MII_A_RX_ERR) } } #[doc = "Field `FSEL37` reader - Function Select 37"] -pub type FSEL37_R = crate::FieldReader; +pub type FSEL37_R = crate::FieldReader; #[doc = "Function Select 37"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL37_A { + type Ux = u8; +} impl FSEL37_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL37_A { + pub const fn variant(&self) -> FSEL37_A { match self.bits { 0 => FSEL37_A::INPUT, 1 => FSEL37_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL37_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL37_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL37_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_MISO`"] + #[doc = "Pin is connected to SPI0_MISO"] #[inline(always)] pub fn is_spi0_miso(&self) -> bool { *self == FSEL37_A::SPI0_MISO } - #[doc = "Checks if the value of the field is `SD1`"] + #[doc = "Pin is connected to SD1"] #[inline(always)] pub fn is_sd1(&self) -> bool { *self == FSEL37_A::SD1 } - #[doc = "Checks if the value of the field is `RXD0`"] + #[doc = "Pin is connected to RXD0"] #[inline(always)] pub fn is_rxd0(&self) -> bool { *self == FSEL37_A::RXD0 } - #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] pub fn is_sd1_dat1(&self) -> bool { *self == FSEL37_A::SD1_DAT1 } - #[doc = "Checks if the value of the field is `RGMII_MDIO`"] + #[doc = "Pin is connected to RGMII_MDIO"] #[inline(always)] pub fn is_rgmii_mdio(&self) -> bool { *self == FSEL37_A::RGMII_MDIO } - #[doc = "Checks if the value of the field is `MII_A_TX_ERR`"] + #[doc = "Pin is connected to MII_A_TX_ERR"] #[inline(always)] pub fn is_mii_a_tx_err(&self) -> bool { *self == FSEL37_A::MII_A_TX_ERR } } #[doc = "Field `FSEL37` writer - Function Select 37"] -pub type FSEL37_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL37_A, 3, O>; -impl<'a, const O: u8> FSEL37_W<'a, O> { +pub type FSEL37_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL37_A>; +impl<'a, REG, const O: u8> FSEL37_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL37_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL37_A::OUTPUT) } #[doc = "Pin is connected to SPI0_MISO"] #[inline(always)] - pub fn spi0_miso(self) -> &'a mut W { + pub fn spi0_miso(self) -> &'a mut crate::W { self.variant(FSEL37_A::SPI0_MISO) } #[doc = "Pin is connected to SD1"] #[inline(always)] - pub fn sd1(self) -> &'a mut W { + pub fn sd1(self) -> &'a mut crate::W { self.variant(FSEL37_A::SD1) } #[doc = "Pin is connected to RXD0"] #[inline(always)] - pub fn rxd0(self) -> &'a mut W { + pub fn rxd0(self) -> &'a mut crate::W { self.variant(FSEL37_A::RXD0) } #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] - pub fn sd1_dat1(self) -> &'a mut W { + pub fn sd1_dat1(self) -> &'a mut crate::W { self.variant(FSEL37_A::SD1_DAT1) } #[doc = "Pin is connected to RGMII_MDIO"] #[inline(always)] - pub fn rgmii_mdio(self) -> &'a mut W { + pub fn rgmii_mdio(self) -> &'a mut crate::W { self.variant(FSEL37_A::RGMII_MDIO) } #[doc = "Pin is connected to MII_A_TX_ERR"] #[inline(always)] - pub fn mii_a_tx_err(self) -> &'a mut W { + pub fn mii_a_tx_err(self) -> &'a mut crate::W { self.variant(FSEL37_A::MII_A_TX_ERR) } } #[doc = "Field `FSEL38` reader - Function Select 38"] -pub type FSEL38_R = crate::FieldReader; +pub type FSEL38_R = crate::FieldReader; #[doc = "Function Select 38"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL38_A { + type Ux = u8; +} impl FSEL38_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL38_A { + pub const fn variant(&self) -> FSEL38_A { match self.bits { 0 => FSEL38_A::INPUT, 1 => FSEL38_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL38_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL38_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL38_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_MOSI`"] + #[doc = "Pin is connected to SPI0_MOSI"] #[inline(always)] pub fn is_spi0_mosi(&self) -> bool { *self == FSEL38_A::SPI0_MOSI } - #[doc = "Checks if the value of the field is `SD2`"] + #[doc = "Pin is connected to SD2"] #[inline(always)] pub fn is_sd2(&self) -> bool { *self == FSEL38_A::SD2 } - #[doc = "Checks if the value of the field is `CTS0`"] + #[doc = "Pin is connected to CTS0"] #[inline(always)] pub fn is_cts0(&self) -> bool { *self == FSEL38_A::CTS0 } - #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] pub fn is_sd1_dat2(&self) -> bool { *self == FSEL38_A::SD1_DAT2 } - #[doc = "Checks if the value of the field is `RGMII_MDC`"] + #[doc = "Pin is connected to RGMII_MDC"] #[inline(always)] pub fn is_rgmii_mdc(&self) -> bool { *self == FSEL38_A::RGMII_MDC } - #[doc = "Checks if the value of the field is `MII_A_CRS`"] + #[doc = "Pin is connected to MII_A_CRS"] #[inline(always)] pub fn is_mii_a_crs(&self) -> bool { *self == FSEL38_A::MII_A_CRS } } #[doc = "Field `FSEL38` writer - Function Select 38"] -pub type FSEL38_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL38_A, 3, O>; -impl<'a, const O: u8> FSEL38_W<'a, O> { +pub type FSEL38_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL38_A>; +impl<'a, REG, const O: u8> FSEL38_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL38_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL38_A::OUTPUT) } #[doc = "Pin is connected to SPI0_MOSI"] #[inline(always)] - pub fn spi0_mosi(self) -> &'a mut W { + pub fn spi0_mosi(self) -> &'a mut crate::W { self.variant(FSEL38_A::SPI0_MOSI) } #[doc = "Pin is connected to SD2"] #[inline(always)] - pub fn sd2(self) -> &'a mut W { + pub fn sd2(self) -> &'a mut crate::W { self.variant(FSEL38_A::SD2) } #[doc = "Pin is connected to CTS0"] #[inline(always)] - pub fn cts0(self) -> &'a mut W { + pub fn cts0(self) -> &'a mut crate::W { self.variant(FSEL38_A::CTS0) } #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] - pub fn sd1_dat2(self) -> &'a mut W { + pub fn sd1_dat2(self) -> &'a mut crate::W { self.variant(FSEL38_A::SD1_DAT2) } #[doc = "Pin is connected to RGMII_MDC"] #[inline(always)] - pub fn rgmii_mdc(self) -> &'a mut W { + pub fn rgmii_mdc(self) -> &'a mut crate::W { self.variant(FSEL38_A::RGMII_MDC) } #[doc = "Pin is connected to MII_A_CRS"] #[inline(always)] - pub fn mii_a_crs(self) -> &'a mut W { + pub fn mii_a_crs(self) -> &'a mut crate::W { self.variant(FSEL38_A::MII_A_CRS) } } #[doc = "Field `FSEL39` reader - Function Select 39"] -pub type FSEL39_R = crate::FieldReader; +pub type FSEL39_R = crate::FieldReader; #[doc = "Function Select 39"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL39_A { + type Ux = u8; +} impl FSEL39_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL39_A { + pub const fn variant(&self) -> FSEL39_A { match self.bits { 0 => FSEL39_A::INPUT, 1 => FSEL39_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL39_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL39_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL39_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_SCLK`"] + #[doc = "Pin is connected to SPI0_SCLK"] #[inline(always)] pub fn is_spi0_sclk(&self) -> bool { *self == FSEL39_A::SPI0_SCLK } - #[doc = "Checks if the value of the field is `SD3`"] + #[doc = "Pin is connected to SD3"] #[inline(always)] pub fn is_sd3(&self) -> bool { *self == FSEL39_A::SD3 } - #[doc = "Checks if the value of the field is `RTS0`"] + #[doc = "Pin is connected to RTS0"] #[inline(always)] pub fn is_rts0(&self) -> bool { *self == FSEL39_A::RTS0 } - #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] pub fn is_sd1_dat3(&self) -> bool { *self == FSEL39_A::SD1_DAT3 } - #[doc = "Checks if the value of the field is `RGMII_IRQ`"] + #[doc = "Pin is connected to RGMII_IRQ"] #[inline(always)] pub fn is_rgmii_irq(&self) -> bool { *self == FSEL39_A::RGMII_IRQ } - #[doc = "Checks if the value of the field is `MII_A_COL`"] + #[doc = "Pin is connected to MII_A_COL"] #[inline(always)] pub fn is_mii_a_col(&self) -> bool { *self == FSEL39_A::MII_A_COL } } #[doc = "Field `FSEL39` writer - Function Select 39"] -pub type FSEL39_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL39_A, 3, O>; -impl<'a, const O: u8> FSEL39_W<'a, O> { +pub type FSEL39_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL39_A>; +impl<'a, REG, const O: u8> FSEL39_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL39_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL39_A::OUTPUT) } #[doc = "Pin is connected to SPI0_SCLK"] #[inline(always)] - pub fn spi0_sclk(self) -> &'a mut W { + pub fn spi0_sclk(self) -> &'a mut crate::W { self.variant(FSEL39_A::SPI0_SCLK) } #[doc = "Pin is connected to SD3"] #[inline(always)] - pub fn sd3(self) -> &'a mut W { + pub fn sd3(self) -> &'a mut crate::W { self.variant(FSEL39_A::SD3) } #[doc = "Pin is connected to RTS0"] #[inline(always)] - pub fn rts0(self) -> &'a mut W { + pub fn rts0(self) -> &'a mut crate::W { self.variant(FSEL39_A::RTS0) } #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] - pub fn sd1_dat3(self) -> &'a mut W { + pub fn sd1_dat3(self) -> &'a mut crate::W { self.variant(FSEL39_A::SD1_DAT3) } #[doc = "Pin is connected to RGMII_IRQ"] #[inline(always)] - pub fn rgmii_irq(self) -> &'a mut W { + pub fn rgmii_irq(self) -> &'a mut crate::W { self.variant(FSEL39_A::RGMII_IRQ) } #[doc = "Pin is connected to MII_A_COL"] #[inline(always)] - pub fn mii_a_col(self) -> &'a mut W { + pub fn mii_a_col(self) -> &'a mut crate::W { self.variant(FSEL39_A::MII_A_COL) } } @@ -1396,86 +1424,108 @@ impl R { FSEL39_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL3") + .field("fsel30", &format_args!("{}", self.fsel30().bits())) + .field("fsel31", &format_args!("{}", self.fsel31().bits())) + .field("fsel32", &format_args!("{}", self.fsel32().bits())) + .field("fsel33", &format_args!("{}", self.fsel33().bits())) + .field("fsel34", &format_args!("{}", self.fsel34().bits())) + .field("fsel35", &format_args!("{}", self.fsel35().bits())) + .field("fsel36", &format_args!("{}", self.fsel36().bits())) + .field("fsel37", &format_args!("{}", self.fsel37().bits())) + .field("fsel38", &format_args!("{}", self.fsel38().bits())) + .field("fsel39", &format_args!("{}", self.fsel39().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 30"] #[inline(always)] #[must_use] - pub fn fsel30(&mut self) -> FSEL30_W<0> { + pub fn fsel30(&mut self) -> FSEL30_W { FSEL30_W::new(self) } #[doc = "Bits 3:5 - Function Select 31"] #[inline(always)] #[must_use] - pub fn fsel31(&mut self) -> FSEL31_W<3> { + pub fn fsel31(&mut self) -> FSEL31_W { FSEL31_W::new(self) } #[doc = "Bits 6:8 - Function Select 32"] #[inline(always)] #[must_use] - pub fn fsel32(&mut self) -> FSEL32_W<6> { + pub fn fsel32(&mut self) -> FSEL32_W { FSEL32_W::new(self) } #[doc = "Bits 9:11 - Function Select 33"] #[inline(always)] #[must_use] - pub fn fsel33(&mut self) -> FSEL33_W<9> { + pub fn fsel33(&mut self) -> FSEL33_W { FSEL33_W::new(self) } #[doc = "Bits 12:14 - Function Select 34"] #[inline(always)] #[must_use] - pub fn fsel34(&mut self) -> FSEL34_W<12> { + pub fn fsel34(&mut self) -> FSEL34_W { FSEL34_W::new(self) } #[doc = "Bits 15:17 - Function Select 35"] #[inline(always)] #[must_use] - pub fn fsel35(&mut self) -> FSEL35_W<15> { + pub fn fsel35(&mut self) -> FSEL35_W { FSEL35_W::new(self) } #[doc = "Bits 18:20 - Function Select 36"] #[inline(always)] #[must_use] - pub fn fsel36(&mut self) -> FSEL36_W<18> { + pub fn fsel36(&mut self) -> FSEL36_W { FSEL36_W::new(self) } #[doc = "Bits 21:23 - Function Select 37"] #[inline(always)] #[must_use] - pub fn fsel37(&mut self) -> FSEL37_W<21> { + pub fn fsel37(&mut self) -> FSEL37_W { FSEL37_W::new(self) } #[doc = "Bits 24:26 - Function Select 38"] #[inline(always)] #[must_use] - pub fn fsel38(&mut self) -> FSEL38_W<24> { + pub fn fsel38(&mut self) -> FSEL38_W { FSEL38_W::new(self) } #[doc = "Bits 27:29 - Function Select 39"] #[inline(always)] #[must_use] - pub fn fsel39(&mut self) -> FSEL39_W<27> { + pub fn fsel39(&mut self) -> FSEL39_W { FSEL39_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel3](index.html) module"] +#[doc = "GPIO Function Select 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL3_SPEC; impl crate::RegisterSpec for GPFSEL3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel3::R](R) reader structure"] -impl crate::Readable for GPFSEL3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel3::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel3::R`](R) reader structure"] +impl crate::Readable for GPFSEL3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel3::W`](W) writer structure"] impl crate::Writable for GPFSEL3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpfsel4.rs b/crates/bcm2711-lpa/src/gpio/gpfsel4.rs index 6fc84fe..e2229db 100644 --- a/crates/bcm2711-lpa/src/gpio/gpfsel4.rs +++ b/crates/bcm2711-lpa/src/gpio/gpfsel4.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL40` reader - Function Select 40"] -pub type FSEL40_R = crate::FieldReader; +pub type FSEL40_R = crate::FieldReader; #[doc = "Function Select 40"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL40_A { + type Ux = u8; +} impl FSEL40_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL40_A { + pub const fn variant(&self) -> FSEL40_A { match self.bits { 0 => FSEL40_A::INPUT, 1 => FSEL40_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL40_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL40_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL40_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM1_0`"] + #[doc = "Pin is connected to PWM1_0"] #[inline(always)] pub fn is_pwm1_0(&self) -> bool { *self == FSEL40_A::PWM1_0 } - #[doc = "Checks if the value of the field is `SD4`"] + #[doc = "Pin is connected to SD4"] #[inline(always)] pub fn is_sd4(&self) -> bool { *self == FSEL40_A::SD4 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL40_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT4`"] + #[doc = "Pin is connected to SD1_DAT4"] #[inline(always)] pub fn is_sd1_dat4(&self) -> bool { *self == FSEL40_A::SD1_DAT4 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL40_A::RESERVED4 } - #[doc = "Checks if the value of the field is `TXD1`"] + #[doc = "Pin is connected to TXD1"] #[inline(always)] pub fn is_txd1(&self) -> bool { *self == FSEL40_A::TXD1 } } #[doc = "Field `FSEL40` writer - Function Select 40"] -pub type FSEL40_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL40_A, 3, O>; -impl<'a, const O: u8> FSEL40_W<'a, O> { +pub type FSEL40_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL40_A>; +impl<'a, REG, const O: u8> FSEL40_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL40_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL40_A::OUTPUT) } #[doc = "Pin is connected to PWM1_0"] #[inline(always)] - pub fn pwm1_0(self) -> &'a mut W { + pub fn pwm1_0(self) -> &'a mut crate::W { self.variant(FSEL40_A::PWM1_0) } #[doc = "Pin is connected to SD4"] #[inline(always)] - pub fn sd4(self) -> &'a mut W { + pub fn sd4(self) -> &'a mut crate::W { self.variant(FSEL40_A::SD4) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL40_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT4"] #[inline(always)] - pub fn sd1_dat4(self) -> &'a mut W { + pub fn sd1_dat4(self) -> &'a mut crate::W { self.variant(FSEL40_A::SD1_DAT4) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL40_A::RESERVED4) } #[doc = "Pin is connected to TXD1"] #[inline(always)] - pub fn txd1(self) -> &'a mut W { + pub fn txd1(self) -> &'a mut crate::W { self.variant(FSEL40_A::TXD1) } } #[doc = "Field `FSEL41` reader - Function Select 41"] -pub type FSEL41_R = crate::FieldReader; +pub type FSEL41_R = crate::FieldReader; #[doc = "Function Select 41"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL41_A { + type Ux = u8; +} impl FSEL41_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL41_A { + pub const fn variant(&self) -> FSEL41_A { match self.bits { 0 => FSEL41_A::INPUT, 1 => FSEL41_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL41_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL41_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL41_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM1_1`"] + #[doc = "Pin is connected to PWM1_1"] #[inline(always)] pub fn is_pwm1_1(&self) -> bool { *self == FSEL41_A::PWM1_1 } - #[doc = "Checks if the value of the field is `SD5`"] + #[doc = "Pin is connected to SD5"] #[inline(always)] pub fn is_sd5(&self) -> bool { *self == FSEL41_A::SD5 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL41_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT5`"] + #[doc = "Pin is connected to SD1_DAT5"] #[inline(always)] pub fn is_sd1_dat5(&self) -> bool { *self == FSEL41_A::SD1_DAT5 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL41_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RXD1`"] + #[doc = "Pin is connected to RXD1"] #[inline(always)] pub fn is_rxd1(&self) -> bool { *self == FSEL41_A::RXD1 } } #[doc = "Field `FSEL41` writer - Function Select 41"] -pub type FSEL41_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL41_A, 3, O>; -impl<'a, const O: u8> FSEL41_W<'a, O> { +pub type FSEL41_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL41_A>; +impl<'a, REG, const O: u8> FSEL41_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL41_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL41_A::OUTPUT) } #[doc = "Pin is connected to PWM1_1"] #[inline(always)] - pub fn pwm1_1(self) -> &'a mut W { + pub fn pwm1_1(self) -> &'a mut crate::W { self.variant(FSEL41_A::PWM1_1) } #[doc = "Pin is connected to SD5"] #[inline(always)] - pub fn sd5(self) -> &'a mut W { + pub fn sd5(self) -> &'a mut crate::W { self.variant(FSEL41_A::SD5) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL41_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT5"] #[inline(always)] - pub fn sd1_dat5(self) -> &'a mut W { + pub fn sd1_dat5(self) -> &'a mut crate::W { self.variant(FSEL41_A::SD1_DAT5) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL41_A::RESERVED4) } #[doc = "Pin is connected to RXD1"] #[inline(always)] - pub fn rxd1(self) -> &'a mut W { + pub fn rxd1(self) -> &'a mut crate::W { self.variant(FSEL41_A::RXD1) } } #[doc = "Field `FSEL42` reader - Function Select 42"] -pub type FSEL42_R = crate::FieldReader; +pub type FSEL42_R = crate::FieldReader; #[doc = "Function Select 42"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL42_A { + type Ux = u8; +} impl FSEL42_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL42_A { + pub const fn variant(&self) -> FSEL42_A { match self.bits { 0 => FSEL42_A::INPUT, 1 => FSEL42_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL42_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL42_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL42_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK1`"] + #[doc = "Pin is connected to GPCLK1"] #[inline(always)] pub fn is_gpclk1(&self) -> bool { *self == FSEL42_A::GPCLK1 } - #[doc = "Checks if the value of the field is `SD6`"] + #[doc = "Pin is connected to SD6"] #[inline(always)] pub fn is_sd6(&self) -> bool { *self == FSEL42_A::SD6 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL42_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT6`"] + #[doc = "Pin is connected to SD1_DAT6"] #[inline(always)] pub fn is_sd1_dat6(&self) -> bool { *self == FSEL42_A::SD1_DAT6 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL42_A::RESERVED4 } - #[doc = "Checks if the value of the field is `CTS1`"] + #[doc = "Pin is connected to CTS1"] #[inline(always)] pub fn is_cts1(&self) -> bool { *self == FSEL42_A::CTS1 } } #[doc = "Field `FSEL42` writer - Function Select 42"] -pub type FSEL42_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL42_A, 3, O>; -impl<'a, const O: u8> FSEL42_W<'a, O> { +pub type FSEL42_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL42_A>; +impl<'a, REG, const O: u8> FSEL42_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL42_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL42_A::OUTPUT) } #[doc = "Pin is connected to GPCLK1"] #[inline(always)] - pub fn gpclk1(self) -> &'a mut W { + pub fn gpclk1(self) -> &'a mut crate::W { self.variant(FSEL42_A::GPCLK1) } #[doc = "Pin is connected to SD6"] #[inline(always)] - pub fn sd6(self) -> &'a mut W { + pub fn sd6(self) -> &'a mut crate::W { self.variant(FSEL42_A::SD6) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL42_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT6"] #[inline(always)] - pub fn sd1_dat6(self) -> &'a mut W { + pub fn sd1_dat6(self) -> &'a mut crate::W { self.variant(FSEL42_A::SD1_DAT6) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL42_A::RESERVED4) } #[doc = "Pin is connected to CTS1"] #[inline(always)] - pub fn cts1(self) -> &'a mut W { + pub fn cts1(self) -> &'a mut crate::W { self.variant(FSEL42_A::CTS1) } } #[doc = "Field `FSEL43` reader - Function Select 43"] -pub type FSEL43_R = crate::FieldReader; +pub type FSEL43_R = crate::FieldReader; #[doc = "Function Select 43"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL43_A { + type Ux = u8; +} impl FSEL43_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL43_A { + pub const fn variant(&self) -> FSEL43_A { match self.bits { 0 => FSEL43_A::INPUT, 1 => FSEL43_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL43_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL43_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL43_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK2`"] + #[doc = "Pin is connected to GPCLK2"] #[inline(always)] pub fn is_gpclk2(&self) -> bool { *self == FSEL43_A::GPCLK2 } - #[doc = "Checks if the value of the field is `SD7`"] + #[doc = "Pin is connected to SD7"] #[inline(always)] pub fn is_sd7(&self) -> bool { *self == FSEL43_A::SD7 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL43_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT7`"] + #[doc = "Pin is connected to SD1_DAT7"] #[inline(always)] pub fn is_sd1_dat7(&self) -> bool { *self == FSEL43_A::SD1_DAT7 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL43_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RTS1`"] + #[doc = "Pin is connected to RTS1"] #[inline(always)] pub fn is_rts1(&self) -> bool { *self == FSEL43_A::RTS1 } } #[doc = "Field `FSEL43` writer - Function Select 43"] -pub type FSEL43_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL43_A, 3, O>; -impl<'a, const O: u8> FSEL43_W<'a, O> { +pub type FSEL43_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL43_A>; +impl<'a, REG, const O: u8> FSEL43_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL43_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL43_A::OUTPUT) } #[doc = "Pin is connected to GPCLK2"] #[inline(always)] - pub fn gpclk2(self) -> &'a mut W { + pub fn gpclk2(self) -> &'a mut crate::W { self.variant(FSEL43_A::GPCLK2) } #[doc = "Pin is connected to SD7"] #[inline(always)] - pub fn sd7(self) -> &'a mut W { + pub fn sd7(self) -> &'a mut crate::W { self.variant(FSEL43_A::SD7) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL43_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT7"] #[inline(always)] - pub fn sd1_dat7(self) -> &'a mut W { + pub fn sd1_dat7(self) -> &'a mut crate::W { self.variant(FSEL43_A::SD1_DAT7) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL43_A::RESERVED4) } #[doc = "Pin is connected to RTS1"] #[inline(always)] - pub fn rts1(self) -> &'a mut W { + pub fn rts1(self) -> &'a mut crate::W { self.variant(FSEL43_A::RTS1) } } #[doc = "Field `FSEL44` reader - Function Select 44"] -pub type FSEL44_R = crate::FieldReader; +pub type FSEL44_R = crate::FieldReader; #[doc = "Function Select 44"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL44_A { + type Ux = u8; +} impl FSEL44_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL44_A { + pub const fn variant(&self) -> FSEL44_A { match self.bits { 0 => FSEL44_A::INPUT, 1 => FSEL44_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL44_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL44_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL44_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK1`"] + #[doc = "Pin is connected to GPCLK1"] #[inline(always)] pub fn is_gpclk1(&self) -> bool { *self == FSEL44_A::GPCLK1 } - #[doc = "Checks if the value of the field is `SDA0`"] + #[doc = "Pin is connected to SDA0"] #[inline(always)] pub fn is_sda0(&self) -> bool { *self == FSEL44_A::SDA0 } - #[doc = "Checks if the value of the field is `SDA1`"] + #[doc = "Pin is connected to SDA1"] #[inline(always)] pub fn is_sda1(&self) -> bool { *self == FSEL44_A::SDA1 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL44_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL44_A::RESERVED4 } - #[doc = "Checks if the value of the field is `SD_CARD_VOLT`"] + #[doc = "Pin is connected to SD_CARD_VOLT"] #[inline(always)] pub fn is_sd_card_volt(&self) -> bool { *self == FSEL44_A::SD_CARD_VOLT } } #[doc = "Field `FSEL44` writer - Function Select 44"] -pub type FSEL44_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL44_A, 3, O>; -impl<'a, const O: u8> FSEL44_W<'a, O> { +pub type FSEL44_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL44_A>; +impl<'a, REG, const O: u8> FSEL44_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL44_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL44_A::OUTPUT) } #[doc = "Pin is connected to GPCLK1"] #[inline(always)] - pub fn gpclk1(self) -> &'a mut W { + pub fn gpclk1(self) -> &'a mut crate::W { self.variant(FSEL44_A::GPCLK1) } #[doc = "Pin is connected to SDA0"] #[inline(always)] - pub fn sda0(self) -> &'a mut W { + pub fn sda0(self) -> &'a mut crate::W { self.variant(FSEL44_A::SDA0) } #[doc = "Pin is connected to SDA1"] #[inline(always)] - pub fn sda1(self) -> &'a mut W { + pub fn sda1(self) -> &'a mut crate::W { self.variant(FSEL44_A::SDA1) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL44_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL44_A::RESERVED4) } #[doc = "Pin is connected to SD_CARD_VOLT"] #[inline(always)] - pub fn sd_card_volt(self) -> &'a mut W { + pub fn sd_card_volt(self) -> &'a mut crate::W { self.variant(FSEL44_A::SD_CARD_VOLT) } } #[doc = "Field `FSEL45` reader - Function Select 45"] -pub type FSEL45_R = crate::FieldReader; +pub type FSEL45_R = crate::FieldReader; #[doc = "Function Select 45"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL45_A { + type Ux = u8; +} impl FSEL45_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL45_A { + pub const fn variant(&self) -> FSEL45_A { match self.bits { 0 => FSEL45_A::INPUT, 1 => FSEL45_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL45_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL45_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL45_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM0_1`"] + #[doc = "Pin is connected to PWM0_1"] #[inline(always)] pub fn is_pwm0_1(&self) -> bool { *self == FSEL45_A::PWM0_1 } - #[doc = "Checks if the value of the field is `SCL0`"] + #[doc = "Pin is connected to SCL0"] #[inline(always)] pub fn is_scl0(&self) -> bool { *self == FSEL45_A::SCL0 } - #[doc = "Checks if the value of the field is `SCL1`"] + #[doc = "Pin is connected to SCL1"] #[inline(always)] pub fn is_scl1(&self) -> bool { *self == FSEL45_A::SCL1 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL45_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL45_A::RESERVED4 } - #[doc = "Checks if the value of the field is `SD_CARD_PWR0`"] + #[doc = "Pin is connected to SD_CARD_PWR0"] #[inline(always)] pub fn is_sd_card_pwr0(&self) -> bool { *self == FSEL45_A::SD_CARD_PWR0 } } #[doc = "Field `FSEL45` writer - Function Select 45"] -pub type FSEL45_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL45_A, 3, O>; -impl<'a, const O: u8> FSEL45_W<'a, O> { +pub type FSEL45_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL45_A>; +impl<'a, REG, const O: u8> FSEL45_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL45_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL45_A::OUTPUT) } #[doc = "Pin is connected to PWM0_1"] #[inline(always)] - pub fn pwm0_1(self) -> &'a mut W { + pub fn pwm0_1(self) -> &'a mut crate::W { self.variant(FSEL45_A::PWM0_1) } #[doc = "Pin is connected to SCL0"] #[inline(always)] - pub fn scl0(self) -> &'a mut W { + pub fn scl0(self) -> &'a mut crate::W { self.variant(FSEL45_A::SCL0) } #[doc = "Pin is connected to SCL1"] #[inline(always)] - pub fn scl1(self) -> &'a mut W { + pub fn scl1(self) -> &'a mut crate::W { self.variant(FSEL45_A::SCL1) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL45_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL45_A::RESERVED4) } #[doc = "Pin is connected to SD_CARD_PWR0"] #[inline(always)] - pub fn sd_card_pwr0(self) -> &'a mut W { + pub fn sd_card_pwr0(self) -> &'a mut crate::W { self.variant(FSEL45_A::SD_CARD_PWR0) } } #[doc = "Field `FSEL46` reader - Function Select 46"] -pub type FSEL46_R = crate::FieldReader; +pub type FSEL46_R = crate::FieldReader; #[doc = "Function Select 46"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL46_A { + type Ux = u8; +} impl FSEL46_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL46_A { + pub const fn variant(&self) -> FSEL46_A { match self.bits { 0 => FSEL46_A::INPUT, 1 => FSEL46_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL46_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL46_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL46_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL46_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL46_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL46_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL46_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL46_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL46_A::RESERVED5 } } #[doc = "Field `FSEL46` writer - Function Select 46"] -pub type FSEL46_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL46_A, 3, O>; -impl<'a, const O: u8> FSEL46_W<'a, O> { +pub type FSEL46_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL46_A>; +impl<'a, REG, const O: u8> FSEL46_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL46_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL46_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED5) } } #[doc = "Field `FSEL47` reader - Function Select 47"] -pub type FSEL47_R = crate::FieldReader; +pub type FSEL47_R = crate::FieldReader; #[doc = "Function Select 47"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL47_A { + type Ux = u8; +} impl FSEL47_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL47_A { + pub const fn variant(&self) -> FSEL47_A { match self.bits { 0 => FSEL47_A::INPUT, 1 => FSEL47_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL47_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL47_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL47_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL47_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL47_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL47_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL47_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL47_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL47_A::RESERVED5 } } #[doc = "Field `FSEL47` writer - Function Select 47"] -pub type FSEL47_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL47_A, 3, O>; -impl<'a, const O: u8> FSEL47_W<'a, O> { +pub type FSEL47_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL47_A>; +impl<'a, REG, const O: u8> FSEL47_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL47_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL47_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED5) } } #[doc = "Field `FSEL48` reader - Function Select 48"] -pub type FSEL48_R = crate::FieldReader; +pub type FSEL48_R = crate::FieldReader; #[doc = "Function Select 48"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL48_A { + type Ux = u8; +} impl FSEL48_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL48_A { + pub const fn variant(&self) -> FSEL48_A { match self.bits { 0 => FSEL48_A::INPUT, 1 => FSEL48_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL48_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL48_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL48_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL48_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL48_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL48_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] pub fn is_sd1_clk(&self) -> bool { *self == FSEL48_A::SD1_CLK } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL48_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL48_A::RESERVED5 } } #[doc = "Field `FSEL48` writer - Function Select 48"] -pub type FSEL48_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL48_A, 3, O>; -impl<'a, const O: u8> FSEL48_W<'a, O> { +pub type FSEL48_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL48_A>; +impl<'a, REG, const O: u8> FSEL48_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL48_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL48_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED2) } #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] - pub fn sd1_clk(self) -> &'a mut W { + pub fn sd1_clk(self) -> &'a mut crate::W { self.variant(FSEL48_A::SD1_CLK) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED5) } } #[doc = "Field `FSEL49` reader - Function Select 49"] -pub type FSEL49_R = crate::FieldReader; +pub type FSEL49_R = crate::FieldReader; #[doc = "Function Select 49"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL49_A { + type Ux = u8; +} impl FSEL49_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL49_A { + pub const fn variant(&self) -> FSEL49_A { match self.bits { 0 => FSEL49_A::INPUT, 1 => FSEL49_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL49_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL49_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL49_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL49_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL49_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL49_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] pub fn is_sd1_cmd(&self) -> bool { *self == FSEL49_A::SD1_CMD } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL49_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL49_A::RESERVED5 } } #[doc = "Field `FSEL49` writer - Function Select 49"] -pub type FSEL49_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL49_A, 3, O>; -impl<'a, const O: u8> FSEL49_W<'a, O> { +pub type FSEL49_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL49_A>; +impl<'a, REG, const O: u8> FSEL49_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL49_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL49_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED2) } #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] - pub fn sd1_cmd(self) -> &'a mut W { + pub fn sd1_cmd(self) -> &'a mut crate::W { self.variant(FSEL49_A::SD1_CMD) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED5) } } @@ -1396,86 +1424,108 @@ impl R { FSEL49_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL4") + .field("fsel40", &format_args!("{}", self.fsel40().bits())) + .field("fsel41", &format_args!("{}", self.fsel41().bits())) + .field("fsel42", &format_args!("{}", self.fsel42().bits())) + .field("fsel43", &format_args!("{}", self.fsel43().bits())) + .field("fsel44", &format_args!("{}", self.fsel44().bits())) + .field("fsel45", &format_args!("{}", self.fsel45().bits())) + .field("fsel46", &format_args!("{}", self.fsel46().bits())) + .field("fsel47", &format_args!("{}", self.fsel47().bits())) + .field("fsel48", &format_args!("{}", self.fsel48().bits())) + .field("fsel49", &format_args!("{}", self.fsel49().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 40"] #[inline(always)] #[must_use] - pub fn fsel40(&mut self) -> FSEL40_W<0> { + pub fn fsel40(&mut self) -> FSEL40_W { FSEL40_W::new(self) } #[doc = "Bits 3:5 - Function Select 41"] #[inline(always)] #[must_use] - pub fn fsel41(&mut self) -> FSEL41_W<3> { + pub fn fsel41(&mut self) -> FSEL41_W { FSEL41_W::new(self) } #[doc = "Bits 6:8 - Function Select 42"] #[inline(always)] #[must_use] - pub fn fsel42(&mut self) -> FSEL42_W<6> { + pub fn fsel42(&mut self) -> FSEL42_W { FSEL42_W::new(self) } #[doc = "Bits 9:11 - Function Select 43"] #[inline(always)] #[must_use] - pub fn fsel43(&mut self) -> FSEL43_W<9> { + pub fn fsel43(&mut self) -> FSEL43_W { FSEL43_W::new(self) } #[doc = "Bits 12:14 - Function Select 44"] #[inline(always)] #[must_use] - pub fn fsel44(&mut self) -> FSEL44_W<12> { + pub fn fsel44(&mut self) -> FSEL44_W { FSEL44_W::new(self) } #[doc = "Bits 15:17 - Function Select 45"] #[inline(always)] #[must_use] - pub fn fsel45(&mut self) -> FSEL45_W<15> { + pub fn fsel45(&mut self) -> FSEL45_W { FSEL45_W::new(self) } #[doc = "Bits 18:20 - Function Select 46"] #[inline(always)] #[must_use] - pub fn fsel46(&mut self) -> FSEL46_W<18> { + pub fn fsel46(&mut self) -> FSEL46_W { FSEL46_W::new(self) } #[doc = "Bits 21:23 - Function Select 47"] #[inline(always)] #[must_use] - pub fn fsel47(&mut self) -> FSEL47_W<21> { + pub fn fsel47(&mut self) -> FSEL47_W { FSEL47_W::new(self) } #[doc = "Bits 24:26 - Function Select 48"] #[inline(always)] #[must_use] - pub fn fsel48(&mut self) -> FSEL48_W<24> { + pub fn fsel48(&mut self) -> FSEL48_W { FSEL48_W::new(self) } #[doc = "Bits 27:29 - Function Select 49"] #[inline(always)] #[must_use] - pub fn fsel49(&mut self) -> FSEL49_W<27> { + pub fn fsel49(&mut self) -> FSEL49_W { FSEL49_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel4](index.html) module"] +#[doc = "GPIO Function Select 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel4::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL4_SPEC; impl crate::RegisterSpec for GPFSEL4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel4::R](R) reader structure"] -impl crate::Readable for GPFSEL4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel4::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel4::R`](R) reader structure"] +impl crate::Readable for GPFSEL4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel4::W`](W) writer structure"] impl crate::Writable for GPFSEL4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpfsel5.rs b/crates/bcm2711-lpa/src/gpio/gpfsel5.rs index 8bdd3e6..03170ba 100644 --- a/crates/bcm2711-lpa/src/gpio/gpfsel5.rs +++ b/crates/bcm2711-lpa/src/gpio/gpfsel5.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL50` reader - Function Select 50"] -pub type FSEL50_R = crate::FieldReader; +pub type FSEL50_R = crate::FieldReader; #[doc = "Function Select 50"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL50_A { + type Ux = u8; +} impl FSEL50_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL50_A { + pub const fn variant(&self) -> FSEL50_A { match self.bits { 0 => FSEL50_A::INPUT, 1 => FSEL50_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL50_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL50_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL50_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL50_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL50_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL50_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] pub fn is_sd1_dat0(&self) -> bool { *self == FSEL50_A::SD1_DAT0 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL50_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL50_A::RESERVED5 } } #[doc = "Field `FSEL50` writer - Function Select 50"] -pub type FSEL50_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL50_A, 3, O>; -impl<'a, const O: u8> FSEL50_W<'a, O> { +pub type FSEL50_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL50_A>; +impl<'a, REG, const O: u8> FSEL50_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL50_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL50_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] - pub fn sd1_dat0(self) -> &'a mut W { + pub fn sd1_dat0(self) -> &'a mut crate::W { self.variant(FSEL50_A::SD1_DAT0) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED5) } } #[doc = "Field `FSEL51` reader - Function Select 51"] -pub type FSEL51_R = crate::FieldReader; +pub type FSEL51_R = crate::FieldReader; #[doc = "Function Select 51"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL51_A { + type Ux = u8; +} impl FSEL51_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL51_A { + pub const fn variant(&self) -> FSEL51_A { match self.bits { 0 => FSEL51_A::INPUT, 1 => FSEL51_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL51_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL51_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL51_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL51_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL51_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL51_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] pub fn is_sd1_dat1(&self) -> bool { *self == FSEL51_A::SD1_DAT1 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL51_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL51_A::RESERVED5 } } #[doc = "Field `FSEL51` writer - Function Select 51"] -pub type FSEL51_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL51_A, 3, O>; -impl<'a, const O: u8> FSEL51_W<'a, O> { +pub type FSEL51_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL51_A>; +impl<'a, REG, const O: u8> FSEL51_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL51_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL51_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] - pub fn sd1_dat1(self) -> &'a mut W { + pub fn sd1_dat1(self) -> &'a mut crate::W { self.variant(FSEL51_A::SD1_DAT1) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED5) } } #[doc = "Field `FSEL52` reader - Function Select 52"] -pub type FSEL52_R = crate::FieldReader; +pub type FSEL52_R = crate::FieldReader; #[doc = "Function Select 52"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL52_A { + type Ux = u8; +} impl FSEL52_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL52_A { + pub const fn variant(&self) -> FSEL52_A { match self.bits { 0 => FSEL52_A::INPUT, 1 => FSEL52_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL52_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL52_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL52_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL52_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL52_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL52_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] pub fn is_sd1_dat2(&self) -> bool { *self == FSEL52_A::SD1_DAT2 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL52_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL52_A::RESERVED5 } } #[doc = "Field `FSEL52` writer - Function Select 52"] -pub type FSEL52_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL52_A, 3, O>; -impl<'a, const O: u8> FSEL52_W<'a, O> { +pub type FSEL52_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL52_A>; +impl<'a, REG, const O: u8> FSEL52_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL52_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL52_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] - pub fn sd1_dat2(self) -> &'a mut W { + pub fn sd1_dat2(self) -> &'a mut crate::W { self.variant(FSEL52_A::SD1_DAT2) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED5) } } #[doc = "Field `FSEL53` reader - Function Select 53"] -pub type FSEL53_R = crate::FieldReader; +pub type FSEL53_R = crate::FieldReader; #[doc = "Function Select 53"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL53_A { + type Ux = u8; +} impl FSEL53_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL53_A { + pub const fn variant(&self) -> FSEL53_A { match self.bits { 0 => FSEL53_A::INPUT, 1 => FSEL53_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL53_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL53_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL53_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL53_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL53_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL53_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] pub fn is_sd1_dat3(&self) -> bool { *self == FSEL53_A::SD1_DAT3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL53_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL53_A::RESERVED5 } } #[doc = "Field `FSEL53` writer - Function Select 53"] -pub type FSEL53_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL53_A, 3, O>; -impl<'a, const O: u8> FSEL53_W<'a, O> { +pub type FSEL53_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL53_A>; +impl<'a, REG, const O: u8> FSEL53_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL53_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL53_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] - pub fn sd1_dat3(self) -> &'a mut W { + pub fn sd1_dat3(self) -> &'a mut crate::W { self.variant(FSEL53_A::SD1_DAT3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED5) } } #[doc = "Field `FSEL54` reader - Function Select 54"] -pub type FSEL54_R = crate::FieldReader; +pub type FSEL54_R = crate::FieldReader; #[doc = "Function Select 54"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL54_A { + type Ux = u8; +} impl FSEL54_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL54_A { + pub const fn variant(&self) -> FSEL54_A { match self.bits { 0 => FSEL54_A::INPUT, 1 => FSEL54_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL54_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL54_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL54_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL54_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL54_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL54_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL54_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL54_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL54_A::RESERVED5 } } #[doc = "Field `FSEL54` writer - Function Select 54"] -pub type FSEL54_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL54_A, 3, O>; -impl<'a, const O: u8> FSEL54_W<'a, O> { +pub type FSEL54_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL54_A>; +impl<'a, REG, const O: u8> FSEL54_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL54_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL54_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL54_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL54_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL54_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL54_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL54_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL54_A::RESERVED5) } } #[doc = "Field `FSEL55` reader - Function Select 55"] -pub type FSEL55_R = crate::FieldReader; +pub type FSEL55_R = crate::FieldReader; #[doc = "Function Select 55"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL55_A { + type Ux = u8; +} impl FSEL55_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL55_A { + pub const fn variant(&self) -> FSEL55_A { match self.bits { 0 => FSEL55_A::INPUT, 1 => FSEL55_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL55_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL55_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL55_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL55_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL55_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL55_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL55_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL55_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL55_A::RESERVED5 } } #[doc = "Field `FSEL55` writer - Function Select 55"] -pub type FSEL55_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL55_A, 3, O>; -impl<'a, const O: u8> FSEL55_W<'a, O> { +pub type FSEL55_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL55_A>; +impl<'a, REG, const O: u8> FSEL55_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL55_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL55_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL55_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL55_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL55_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL55_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL55_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL55_A::RESERVED5) } } #[doc = "Field `FSEL56` reader - Function Select 56"] -pub type FSEL56_R = crate::FieldReader; +pub type FSEL56_R = crate::FieldReader; #[doc = "Function Select 56"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL56_A { + type Ux = u8; +} impl FSEL56_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL56_A { + pub const fn variant(&self) -> FSEL56_A { match self.bits { 0 => FSEL56_A::INPUT, 1 => FSEL56_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL56_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL56_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL56_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL56_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL56_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL56_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL56_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL56_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL56_A::RESERVED5 } } #[doc = "Field `FSEL56` writer - Function Select 56"] -pub type FSEL56_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL56_A, 3, O>; -impl<'a, const O: u8> FSEL56_W<'a, O> { +pub type FSEL56_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL56_A>; +impl<'a, REG, const O: u8> FSEL56_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL56_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL56_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL56_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL56_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL56_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL56_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL56_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL56_A::RESERVED5) } } #[doc = "Field `FSEL57` reader - Function Select 57"] -pub type FSEL57_R = crate::FieldReader; +pub type FSEL57_R = crate::FieldReader; #[doc = "Function Select 57"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL57_A { + type Ux = u8; +} impl FSEL57_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL57_A { + pub const fn variant(&self) -> FSEL57_A { match self.bits { 0 => FSEL57_A::INPUT, 1 => FSEL57_A::OUTPUT, @@ -996,89 +1009,92 @@ impl FSEL57_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL57_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL57_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL57_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL57_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL57_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL57_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL57_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL57_A::RESERVED5 } } #[doc = "Field `FSEL57` writer - Function Select 57"] -pub type FSEL57_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL57_A, 3, O>; -impl<'a, const O: u8> FSEL57_W<'a, O> { +pub type FSEL57_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL57_A>; +impl<'a, REG, const O: u8> FSEL57_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL57_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL57_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL57_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL57_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL57_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL57_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL57_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL57_A::RESERVED5) } } @@ -1124,74 +1140,94 @@ impl R { FSEL57_R::new(((self.bits >> 21) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL5") + .field("fsel50", &format_args!("{}", self.fsel50().bits())) + .field("fsel51", &format_args!("{}", self.fsel51().bits())) + .field("fsel52", &format_args!("{}", self.fsel52().bits())) + .field("fsel53", &format_args!("{}", self.fsel53().bits())) + .field("fsel54", &format_args!("{}", self.fsel54().bits())) + .field("fsel55", &format_args!("{}", self.fsel55().bits())) + .field("fsel56", &format_args!("{}", self.fsel56().bits())) + .field("fsel57", &format_args!("{}", self.fsel57().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 50"] #[inline(always)] #[must_use] - pub fn fsel50(&mut self) -> FSEL50_W<0> { + pub fn fsel50(&mut self) -> FSEL50_W { FSEL50_W::new(self) } #[doc = "Bits 3:5 - Function Select 51"] #[inline(always)] #[must_use] - pub fn fsel51(&mut self) -> FSEL51_W<3> { + pub fn fsel51(&mut self) -> FSEL51_W { FSEL51_W::new(self) } #[doc = "Bits 6:8 - Function Select 52"] #[inline(always)] #[must_use] - pub fn fsel52(&mut self) -> FSEL52_W<6> { + pub fn fsel52(&mut self) -> FSEL52_W { FSEL52_W::new(self) } #[doc = "Bits 9:11 - Function Select 53"] #[inline(always)] #[must_use] - pub fn fsel53(&mut self) -> FSEL53_W<9> { + pub fn fsel53(&mut self) -> FSEL53_W { FSEL53_W::new(self) } #[doc = "Bits 12:14 - Function Select 54"] #[inline(always)] #[must_use] - pub fn fsel54(&mut self) -> FSEL54_W<12> { + pub fn fsel54(&mut self) -> FSEL54_W { FSEL54_W::new(self) } #[doc = "Bits 15:17 - Function Select 55"] #[inline(always)] #[must_use] - pub fn fsel55(&mut self) -> FSEL55_W<15> { + pub fn fsel55(&mut self) -> FSEL55_W { FSEL55_W::new(self) } #[doc = "Bits 18:20 - Function Select 56"] #[inline(always)] #[must_use] - pub fn fsel56(&mut self) -> FSEL56_W<18> { + pub fn fsel56(&mut self) -> FSEL56_W { FSEL56_W::new(self) } #[doc = "Bits 21:23 - Function Select 57"] #[inline(always)] #[must_use] - pub fn fsel57(&mut self) -> FSEL57_W<21> { + pub fn fsel57(&mut self) -> FSEL57_W { FSEL57_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel5](index.html) module"] +#[doc = "GPIO Function Select 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel5::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL5_SPEC; impl crate::RegisterSpec for GPFSEL5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel5::R](R) reader structure"] -impl crate::Readable for GPFSEL5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel5::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel5::R`](R) reader structure"] +impl crate::Readable for GPFSEL5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel5::W`](W) writer structure"] impl crate::Writable for GPFSEL5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gphen0.rs b/crates/bcm2711-lpa/src/gpio/gphen0.rs index b45a414..d788bbf 100644 --- a/crates/bcm2711-lpa/src/gpio/gphen0.rs +++ b/crates/bcm2711-lpa/src/gpio/gphen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPHEN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPHEN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HEN0` reader - High detect enabled 0"] -pub type HEN0_R = crate::BitReader; +pub type HEN0_R = crate::BitReader; #[doc = "Field `HEN0` writer - High detect enabled 0"] -pub type HEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN1` reader - High detect enabled 1"] -pub type HEN1_R = crate::BitReader; +pub type HEN1_R = crate::BitReader; #[doc = "Field `HEN1` writer - High detect enabled 1"] -pub type HEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN2` reader - High detect enabled 2"] -pub type HEN2_R = crate::BitReader; +pub type HEN2_R = crate::BitReader; #[doc = "Field `HEN2` writer - High detect enabled 2"] -pub type HEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN3` reader - High detect enabled 3"] -pub type HEN3_R = crate::BitReader; +pub type HEN3_R = crate::BitReader; #[doc = "Field `HEN3` writer - High detect enabled 3"] -pub type HEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN4` reader - High detect enabled 4"] -pub type HEN4_R = crate::BitReader; +pub type HEN4_R = crate::BitReader; #[doc = "Field `HEN4` writer - High detect enabled 4"] -pub type HEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN5` reader - High detect enabled 5"] -pub type HEN5_R = crate::BitReader; +pub type HEN5_R = crate::BitReader; #[doc = "Field `HEN5` writer - High detect enabled 5"] -pub type HEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN6` reader - High detect enabled 6"] -pub type HEN6_R = crate::BitReader; +pub type HEN6_R = crate::BitReader; #[doc = "Field `HEN6` writer - High detect enabled 6"] -pub type HEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN7` reader - High detect enabled 7"] -pub type HEN7_R = crate::BitReader; +pub type HEN7_R = crate::BitReader; #[doc = "Field `HEN7` writer - High detect enabled 7"] -pub type HEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN8` reader - High detect enabled 8"] -pub type HEN8_R = crate::BitReader; +pub type HEN8_R = crate::BitReader; #[doc = "Field `HEN8` writer - High detect enabled 8"] -pub type HEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN9` reader - High detect enabled 9"] -pub type HEN9_R = crate::BitReader; +pub type HEN9_R = crate::BitReader; #[doc = "Field `HEN9` writer - High detect enabled 9"] -pub type HEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN10` reader - High detect enabled 10"] -pub type HEN10_R = crate::BitReader; +pub type HEN10_R = crate::BitReader; #[doc = "Field `HEN10` writer - High detect enabled 10"] -pub type HEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN11` reader - High detect enabled 11"] -pub type HEN11_R = crate::BitReader; +pub type HEN11_R = crate::BitReader; #[doc = "Field `HEN11` writer - High detect enabled 11"] -pub type HEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN12` reader - High detect enabled 12"] -pub type HEN12_R = crate::BitReader; +pub type HEN12_R = crate::BitReader; #[doc = "Field `HEN12` writer - High detect enabled 12"] -pub type HEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN13` reader - High detect enabled 13"] -pub type HEN13_R = crate::BitReader; +pub type HEN13_R = crate::BitReader; #[doc = "Field `HEN13` writer - High detect enabled 13"] -pub type HEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN14` reader - High detect enabled 14"] -pub type HEN14_R = crate::BitReader; +pub type HEN14_R = crate::BitReader; #[doc = "Field `HEN14` writer - High detect enabled 14"] -pub type HEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN15` reader - High detect enabled 15"] -pub type HEN15_R = crate::BitReader; +pub type HEN15_R = crate::BitReader; #[doc = "Field `HEN15` writer - High detect enabled 15"] -pub type HEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN16` reader - High detect enabled 16"] -pub type HEN16_R = crate::BitReader; +pub type HEN16_R = crate::BitReader; #[doc = "Field `HEN16` writer - High detect enabled 16"] -pub type HEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN17` reader - High detect enabled 17"] -pub type HEN17_R = crate::BitReader; +pub type HEN17_R = crate::BitReader; #[doc = "Field `HEN17` writer - High detect enabled 17"] -pub type HEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN18` reader - High detect enabled 18"] -pub type HEN18_R = crate::BitReader; +pub type HEN18_R = crate::BitReader; #[doc = "Field `HEN18` writer - High detect enabled 18"] -pub type HEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN19` reader - High detect enabled 19"] -pub type HEN19_R = crate::BitReader; +pub type HEN19_R = crate::BitReader; #[doc = "Field `HEN19` writer - High detect enabled 19"] -pub type HEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN20` reader - High detect enabled 20"] -pub type HEN20_R = crate::BitReader; +pub type HEN20_R = crate::BitReader; #[doc = "Field `HEN20` writer - High detect enabled 20"] -pub type HEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN21` reader - High detect enabled 21"] -pub type HEN21_R = crate::BitReader; +pub type HEN21_R = crate::BitReader; #[doc = "Field `HEN21` writer - High detect enabled 21"] -pub type HEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN22` reader - High detect enabled 22"] -pub type HEN22_R = crate::BitReader; +pub type HEN22_R = crate::BitReader; #[doc = "Field `HEN22` writer - High detect enabled 22"] -pub type HEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN23` reader - High detect enabled 23"] -pub type HEN23_R = crate::BitReader; +pub type HEN23_R = crate::BitReader; #[doc = "Field `HEN23` writer - High detect enabled 23"] -pub type HEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN24` reader - High detect enabled 24"] -pub type HEN24_R = crate::BitReader; +pub type HEN24_R = crate::BitReader; #[doc = "Field `HEN24` writer - High detect enabled 24"] -pub type HEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN25` reader - High detect enabled 25"] -pub type HEN25_R = crate::BitReader; +pub type HEN25_R = crate::BitReader; #[doc = "Field `HEN25` writer - High detect enabled 25"] -pub type HEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN26` reader - High detect enabled 26"] -pub type HEN26_R = crate::BitReader; +pub type HEN26_R = crate::BitReader; #[doc = "Field `HEN26` writer - High detect enabled 26"] -pub type HEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN27` reader - High detect enabled 27"] -pub type HEN27_R = crate::BitReader; +pub type HEN27_R = crate::BitReader; #[doc = "Field `HEN27` writer - High detect enabled 27"] -pub type HEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN28` reader - High detect enabled 28"] -pub type HEN28_R = crate::BitReader; +pub type HEN28_R = crate::BitReader; #[doc = "Field `HEN28` writer - High detect enabled 28"] -pub type HEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN29` reader - High detect enabled 29"] -pub type HEN29_R = crate::BitReader; +pub type HEN29_R = crate::BitReader; #[doc = "Field `HEN29` writer - High detect enabled 29"] -pub type HEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN30` reader - High detect enabled 30"] -pub type HEN30_R = crate::BitReader; +pub type HEN30_R = crate::BitReader; #[doc = "Field `HEN30` writer - High detect enabled 30"] -pub type HEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN31` reader - High detect enabled 31"] -pub type HEN31_R = crate::BitReader; +pub type HEN31_R = crate::BitReader; #[doc = "Field `HEN31` writer - High detect enabled 31"] -pub type HEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - High detect enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { HEN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPHEN0") + .field("hen0", &format_args!("{}", self.hen0().bit())) + .field("hen1", &format_args!("{}", self.hen1().bit())) + .field("hen2", &format_args!("{}", self.hen2().bit())) + .field("hen3", &format_args!("{}", self.hen3().bit())) + .field("hen4", &format_args!("{}", self.hen4().bit())) + .field("hen5", &format_args!("{}", self.hen5().bit())) + .field("hen6", &format_args!("{}", self.hen6().bit())) + .field("hen7", &format_args!("{}", self.hen7().bit())) + .field("hen8", &format_args!("{}", self.hen8().bit())) + .field("hen9", &format_args!("{}", self.hen9().bit())) + .field("hen10", &format_args!("{}", self.hen10().bit())) + .field("hen11", &format_args!("{}", self.hen11().bit())) + .field("hen12", &format_args!("{}", self.hen12().bit())) + .field("hen13", &format_args!("{}", self.hen13().bit())) + .field("hen14", &format_args!("{}", self.hen14().bit())) + .field("hen15", &format_args!("{}", self.hen15().bit())) + .field("hen16", &format_args!("{}", self.hen16().bit())) + .field("hen17", &format_args!("{}", self.hen17().bit())) + .field("hen18", &format_args!("{}", self.hen18().bit())) + .field("hen19", &format_args!("{}", self.hen19().bit())) + .field("hen20", &format_args!("{}", self.hen20().bit())) + .field("hen21", &format_args!("{}", self.hen21().bit())) + .field("hen22", &format_args!("{}", self.hen22().bit())) + .field("hen23", &format_args!("{}", self.hen23().bit())) + .field("hen24", &format_args!("{}", self.hen24().bit())) + .field("hen25", &format_args!("{}", self.hen25().bit())) + .field("hen26", &format_args!("{}", self.hen26().bit())) + .field("hen27", &format_args!("{}", self.hen27().bit())) + .field("hen28", &format_args!("{}", self.hen28().bit())) + .field("hen29", &format_args!("{}", self.hen29().bit())) + .field("hen30", &format_args!("{}", self.hen30().bit())) + .field("hen31", &format_args!("{}", self.hen31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - High detect enabled 0"] #[inline(always)] #[must_use] - pub fn hen0(&mut self) -> HEN0_W<0> { + pub fn hen0(&mut self) -> HEN0_W { HEN0_W::new(self) } #[doc = "Bit 1 - High detect enabled 1"] #[inline(always)] #[must_use] - pub fn hen1(&mut self) -> HEN1_W<1> { + pub fn hen1(&mut self) -> HEN1_W { HEN1_W::new(self) } #[doc = "Bit 2 - High detect enabled 2"] #[inline(always)] #[must_use] - pub fn hen2(&mut self) -> HEN2_W<2> { + pub fn hen2(&mut self) -> HEN2_W { HEN2_W::new(self) } #[doc = "Bit 3 - High detect enabled 3"] #[inline(always)] #[must_use] - pub fn hen3(&mut self) -> HEN3_W<3> { + pub fn hen3(&mut self) -> HEN3_W { HEN3_W::new(self) } #[doc = "Bit 4 - High detect enabled 4"] #[inline(always)] #[must_use] - pub fn hen4(&mut self) -> HEN4_W<4> { + pub fn hen4(&mut self) -> HEN4_W { HEN4_W::new(self) } #[doc = "Bit 5 - High detect enabled 5"] #[inline(always)] #[must_use] - pub fn hen5(&mut self) -> HEN5_W<5> { + pub fn hen5(&mut self) -> HEN5_W { HEN5_W::new(self) } #[doc = "Bit 6 - High detect enabled 6"] #[inline(always)] #[must_use] - pub fn hen6(&mut self) -> HEN6_W<6> { + pub fn hen6(&mut self) -> HEN6_W { HEN6_W::new(self) } #[doc = "Bit 7 - High detect enabled 7"] #[inline(always)] #[must_use] - pub fn hen7(&mut self) -> HEN7_W<7> { + pub fn hen7(&mut self) -> HEN7_W { HEN7_W::new(self) } #[doc = "Bit 8 - High detect enabled 8"] #[inline(always)] #[must_use] - pub fn hen8(&mut self) -> HEN8_W<8> { + pub fn hen8(&mut self) -> HEN8_W { HEN8_W::new(self) } #[doc = "Bit 9 - High detect enabled 9"] #[inline(always)] #[must_use] - pub fn hen9(&mut self) -> HEN9_W<9> { + pub fn hen9(&mut self) -> HEN9_W { HEN9_W::new(self) } #[doc = "Bit 10 - High detect enabled 10"] #[inline(always)] #[must_use] - pub fn hen10(&mut self) -> HEN10_W<10> { + pub fn hen10(&mut self) -> HEN10_W { HEN10_W::new(self) } #[doc = "Bit 11 - High detect enabled 11"] #[inline(always)] #[must_use] - pub fn hen11(&mut self) -> HEN11_W<11> { + pub fn hen11(&mut self) -> HEN11_W { HEN11_W::new(self) } #[doc = "Bit 12 - High detect enabled 12"] #[inline(always)] #[must_use] - pub fn hen12(&mut self) -> HEN12_W<12> { + pub fn hen12(&mut self) -> HEN12_W { HEN12_W::new(self) } #[doc = "Bit 13 - High detect enabled 13"] #[inline(always)] #[must_use] - pub fn hen13(&mut self) -> HEN13_W<13> { + pub fn hen13(&mut self) -> HEN13_W { HEN13_W::new(self) } #[doc = "Bit 14 - High detect enabled 14"] #[inline(always)] #[must_use] - pub fn hen14(&mut self) -> HEN14_W<14> { + pub fn hen14(&mut self) -> HEN14_W { HEN14_W::new(self) } #[doc = "Bit 15 - High detect enabled 15"] #[inline(always)] #[must_use] - pub fn hen15(&mut self) -> HEN15_W<15> { + pub fn hen15(&mut self) -> HEN15_W { HEN15_W::new(self) } #[doc = "Bit 16 - High detect enabled 16"] #[inline(always)] #[must_use] - pub fn hen16(&mut self) -> HEN16_W<16> { + pub fn hen16(&mut self) -> HEN16_W { HEN16_W::new(self) } #[doc = "Bit 17 - High detect enabled 17"] #[inline(always)] #[must_use] - pub fn hen17(&mut self) -> HEN17_W<17> { + pub fn hen17(&mut self) -> HEN17_W { HEN17_W::new(self) } #[doc = "Bit 18 - High detect enabled 18"] #[inline(always)] #[must_use] - pub fn hen18(&mut self) -> HEN18_W<18> { + pub fn hen18(&mut self) -> HEN18_W { HEN18_W::new(self) } #[doc = "Bit 19 - High detect enabled 19"] #[inline(always)] #[must_use] - pub fn hen19(&mut self) -> HEN19_W<19> { + pub fn hen19(&mut self) -> HEN19_W { HEN19_W::new(self) } #[doc = "Bit 20 - High detect enabled 20"] #[inline(always)] #[must_use] - pub fn hen20(&mut self) -> HEN20_W<20> { + pub fn hen20(&mut self) -> HEN20_W { HEN20_W::new(self) } #[doc = "Bit 21 - High detect enabled 21"] #[inline(always)] #[must_use] - pub fn hen21(&mut self) -> HEN21_W<21> { + pub fn hen21(&mut self) -> HEN21_W { HEN21_W::new(self) } #[doc = "Bit 22 - High detect enabled 22"] #[inline(always)] #[must_use] - pub fn hen22(&mut self) -> HEN22_W<22> { + pub fn hen22(&mut self) -> HEN22_W { HEN22_W::new(self) } #[doc = "Bit 23 - High detect enabled 23"] #[inline(always)] #[must_use] - pub fn hen23(&mut self) -> HEN23_W<23> { + pub fn hen23(&mut self) -> HEN23_W { HEN23_W::new(self) } #[doc = "Bit 24 - High detect enabled 24"] #[inline(always)] #[must_use] - pub fn hen24(&mut self) -> HEN24_W<24> { + pub fn hen24(&mut self) -> HEN24_W { HEN24_W::new(self) } #[doc = "Bit 25 - High detect enabled 25"] #[inline(always)] #[must_use] - pub fn hen25(&mut self) -> HEN25_W<25> { + pub fn hen25(&mut self) -> HEN25_W { HEN25_W::new(self) } #[doc = "Bit 26 - High detect enabled 26"] #[inline(always)] #[must_use] - pub fn hen26(&mut self) -> HEN26_W<26> { + pub fn hen26(&mut self) -> HEN26_W { HEN26_W::new(self) } #[doc = "Bit 27 - High detect enabled 27"] #[inline(always)] #[must_use] - pub fn hen27(&mut self) -> HEN27_W<27> { + pub fn hen27(&mut self) -> HEN27_W { HEN27_W::new(self) } #[doc = "Bit 28 - High detect enabled 28"] #[inline(always)] #[must_use] - pub fn hen28(&mut self) -> HEN28_W<28> { + pub fn hen28(&mut self) -> HEN28_W { HEN28_W::new(self) } #[doc = "Bit 29 - High detect enabled 29"] #[inline(always)] #[must_use] - pub fn hen29(&mut self) -> HEN29_W<29> { + pub fn hen29(&mut self) -> HEN29_W { HEN29_W::new(self) } #[doc = "Bit 30 - High detect enabled 30"] #[inline(always)] #[must_use] - pub fn hen30(&mut self) -> HEN30_W<30> { + pub fn hen30(&mut self) -> HEN30_W { HEN30_W::new(self) } #[doc = "Bit 31 - High detect enabled 31"] #[inline(always)] #[must_use] - pub fn hen31(&mut self) -> HEN31_W<31> { + pub fn hen31(&mut self) -> HEN31_W { HEN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin High Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gphen0](index.html) module"] +#[doc = "GPIO Pin High Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gphen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gphen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPHEN0_SPEC; impl crate::RegisterSpec for GPHEN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gphen0::R](R) reader structure"] -impl crate::Readable for GPHEN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gphen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gphen0::R`](R) reader structure"] +impl crate::Readable for GPHEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gphen0::W`](W) writer structure"] impl crate::Writable for GPHEN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gphen1.rs b/crates/bcm2711-lpa/src/gpio/gphen1.rs index 1c7681b..7c7c2d7 100644 --- a/crates/bcm2711-lpa/src/gpio/gphen1.rs +++ b/crates/bcm2711-lpa/src/gpio/gphen1.rs @@ -1,143 +1,111 @@ #[doc = "Register `GPHEN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPHEN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HEN32` reader - High detect enabled 32"] -pub type HEN32_R = crate::BitReader; +pub type HEN32_R = crate::BitReader; #[doc = "Field `HEN32` writer - High detect enabled 32"] -pub type HEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN33` reader - High detect enabled 33"] -pub type HEN33_R = crate::BitReader; +pub type HEN33_R = crate::BitReader; #[doc = "Field `HEN33` writer - High detect enabled 33"] -pub type HEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN34` reader - High detect enabled 34"] -pub type HEN34_R = crate::BitReader; +pub type HEN34_R = crate::BitReader; #[doc = "Field `HEN34` writer - High detect enabled 34"] -pub type HEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN35` reader - High detect enabled 35"] -pub type HEN35_R = crate::BitReader; +pub type HEN35_R = crate::BitReader; #[doc = "Field `HEN35` writer - High detect enabled 35"] -pub type HEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN36` reader - High detect enabled 36"] -pub type HEN36_R = crate::BitReader; +pub type HEN36_R = crate::BitReader; #[doc = "Field `HEN36` writer - High detect enabled 36"] -pub type HEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN37` reader - High detect enabled 37"] -pub type HEN37_R = crate::BitReader; +pub type HEN37_R = crate::BitReader; #[doc = "Field `HEN37` writer - High detect enabled 37"] -pub type HEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN38` reader - High detect enabled 38"] -pub type HEN38_R = crate::BitReader; +pub type HEN38_R = crate::BitReader; #[doc = "Field `HEN38` writer - High detect enabled 38"] -pub type HEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN39` reader - High detect enabled 39"] -pub type HEN39_R = crate::BitReader; +pub type HEN39_R = crate::BitReader; #[doc = "Field `HEN39` writer - High detect enabled 39"] -pub type HEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN40` reader - High detect enabled 40"] -pub type HEN40_R = crate::BitReader; +pub type HEN40_R = crate::BitReader; #[doc = "Field `HEN40` writer - High detect enabled 40"] -pub type HEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN41` reader - High detect enabled 41"] -pub type HEN41_R = crate::BitReader; +pub type HEN41_R = crate::BitReader; #[doc = "Field `HEN41` writer - High detect enabled 41"] -pub type HEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN42` reader - High detect enabled 42"] -pub type HEN42_R = crate::BitReader; +pub type HEN42_R = crate::BitReader; #[doc = "Field `HEN42` writer - High detect enabled 42"] -pub type HEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN43` reader - High detect enabled 43"] -pub type HEN43_R = crate::BitReader; +pub type HEN43_R = crate::BitReader; #[doc = "Field `HEN43` writer - High detect enabled 43"] -pub type HEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN44` reader - High detect enabled 44"] -pub type HEN44_R = crate::BitReader; +pub type HEN44_R = crate::BitReader; #[doc = "Field `HEN44` writer - High detect enabled 44"] -pub type HEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN45` reader - High detect enabled 45"] -pub type HEN45_R = crate::BitReader; +pub type HEN45_R = crate::BitReader; #[doc = "Field `HEN45` writer - High detect enabled 45"] -pub type HEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN46` reader - High detect enabled 46"] -pub type HEN46_R = crate::BitReader; +pub type HEN46_R = crate::BitReader; #[doc = "Field `HEN46` writer - High detect enabled 46"] -pub type HEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN47` reader - High detect enabled 47"] -pub type HEN47_R = crate::BitReader; +pub type HEN47_R = crate::BitReader; #[doc = "Field `HEN47` writer - High detect enabled 47"] -pub type HEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN48` reader - High detect enabled 48"] -pub type HEN48_R = crate::BitReader; +pub type HEN48_R = crate::BitReader; #[doc = "Field `HEN48` writer - High detect enabled 48"] -pub type HEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN49` reader - High detect enabled 49"] -pub type HEN49_R = crate::BitReader; +pub type HEN49_R = crate::BitReader; #[doc = "Field `HEN49` writer - High detect enabled 49"] -pub type HEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN50` reader - High detect enabled 50"] -pub type HEN50_R = crate::BitReader; +pub type HEN50_R = crate::BitReader; #[doc = "Field `HEN50` writer - High detect enabled 50"] -pub type HEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN51` reader - High detect enabled 51"] -pub type HEN51_R = crate::BitReader; +pub type HEN51_R = crate::BitReader; #[doc = "Field `HEN51` writer - High detect enabled 51"] -pub type HEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN52` reader - High detect enabled 52"] -pub type HEN52_R = crate::BitReader; +pub type HEN52_R = crate::BitReader; #[doc = "Field `HEN52` writer - High detect enabled 52"] -pub type HEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN53` reader - High detect enabled 53"] -pub type HEN53_R = crate::BitReader; +pub type HEN53_R = crate::BitReader; #[doc = "Field `HEN53` writer - High detect enabled 53"] -pub type HEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN54` reader - High detect enabled 54"] -pub type HEN54_R = crate::BitReader; +pub type HEN54_R = crate::BitReader; #[doc = "Field `HEN54` writer - High detect enabled 54"] -pub type HEN54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN54_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN55` reader - High detect enabled 55"] -pub type HEN55_R = crate::BitReader; +pub type HEN55_R = crate::BitReader; #[doc = "Field `HEN55` writer - High detect enabled 55"] -pub type HEN55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN55_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN56` reader - High detect enabled 56"] -pub type HEN56_R = crate::BitReader; +pub type HEN56_R = crate::BitReader; #[doc = "Field `HEN56` writer - High detect enabled 56"] -pub type HEN56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN57` reader - High detect enabled 57"] -pub type HEN57_R = crate::BitReader; +pub type HEN57_R = crate::BitReader; #[doc = "Field `HEN57` writer - High detect enabled 57"] -pub type HEN57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - High detect enabled 32"] #[inline(always)] @@ -270,182 +238,220 @@ impl R { HEN57_R::new(((self.bits >> 25) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPHEN1") + .field("hen32", &format_args!("{}", self.hen32().bit())) + .field("hen33", &format_args!("{}", self.hen33().bit())) + .field("hen34", &format_args!("{}", self.hen34().bit())) + .field("hen35", &format_args!("{}", self.hen35().bit())) + .field("hen36", &format_args!("{}", self.hen36().bit())) + .field("hen37", &format_args!("{}", self.hen37().bit())) + .field("hen38", &format_args!("{}", self.hen38().bit())) + .field("hen39", &format_args!("{}", self.hen39().bit())) + .field("hen40", &format_args!("{}", self.hen40().bit())) + .field("hen41", &format_args!("{}", self.hen41().bit())) + .field("hen42", &format_args!("{}", self.hen42().bit())) + .field("hen43", &format_args!("{}", self.hen43().bit())) + .field("hen44", &format_args!("{}", self.hen44().bit())) + .field("hen45", &format_args!("{}", self.hen45().bit())) + .field("hen46", &format_args!("{}", self.hen46().bit())) + .field("hen47", &format_args!("{}", self.hen47().bit())) + .field("hen48", &format_args!("{}", self.hen48().bit())) + .field("hen49", &format_args!("{}", self.hen49().bit())) + .field("hen50", &format_args!("{}", self.hen50().bit())) + .field("hen51", &format_args!("{}", self.hen51().bit())) + .field("hen52", &format_args!("{}", self.hen52().bit())) + .field("hen53", &format_args!("{}", self.hen53().bit())) + .field("hen54", &format_args!("{}", self.hen54().bit())) + .field("hen55", &format_args!("{}", self.hen55().bit())) + .field("hen56", &format_args!("{}", self.hen56().bit())) + .field("hen57", &format_args!("{}", self.hen57().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - High detect enabled 32"] #[inline(always)] #[must_use] - pub fn hen32(&mut self) -> HEN32_W<0> { + pub fn hen32(&mut self) -> HEN32_W { HEN32_W::new(self) } #[doc = "Bit 1 - High detect enabled 33"] #[inline(always)] #[must_use] - pub fn hen33(&mut self) -> HEN33_W<1> { + pub fn hen33(&mut self) -> HEN33_W { HEN33_W::new(self) } #[doc = "Bit 2 - High detect enabled 34"] #[inline(always)] #[must_use] - pub fn hen34(&mut self) -> HEN34_W<2> { + pub fn hen34(&mut self) -> HEN34_W { HEN34_W::new(self) } #[doc = "Bit 3 - High detect enabled 35"] #[inline(always)] #[must_use] - pub fn hen35(&mut self) -> HEN35_W<3> { + pub fn hen35(&mut self) -> HEN35_W { HEN35_W::new(self) } #[doc = "Bit 4 - High detect enabled 36"] #[inline(always)] #[must_use] - pub fn hen36(&mut self) -> HEN36_W<4> { + pub fn hen36(&mut self) -> HEN36_W { HEN36_W::new(self) } #[doc = "Bit 5 - High detect enabled 37"] #[inline(always)] #[must_use] - pub fn hen37(&mut self) -> HEN37_W<5> { + pub fn hen37(&mut self) -> HEN37_W { HEN37_W::new(self) } #[doc = "Bit 6 - High detect enabled 38"] #[inline(always)] #[must_use] - pub fn hen38(&mut self) -> HEN38_W<6> { + pub fn hen38(&mut self) -> HEN38_W { HEN38_W::new(self) } #[doc = "Bit 7 - High detect enabled 39"] #[inline(always)] #[must_use] - pub fn hen39(&mut self) -> HEN39_W<7> { + pub fn hen39(&mut self) -> HEN39_W { HEN39_W::new(self) } #[doc = "Bit 8 - High detect enabled 40"] #[inline(always)] #[must_use] - pub fn hen40(&mut self) -> HEN40_W<8> { + pub fn hen40(&mut self) -> HEN40_W { HEN40_W::new(self) } #[doc = "Bit 9 - High detect enabled 41"] #[inline(always)] #[must_use] - pub fn hen41(&mut self) -> HEN41_W<9> { + pub fn hen41(&mut self) -> HEN41_W { HEN41_W::new(self) } #[doc = "Bit 10 - High detect enabled 42"] #[inline(always)] #[must_use] - pub fn hen42(&mut self) -> HEN42_W<10> { + pub fn hen42(&mut self) -> HEN42_W { HEN42_W::new(self) } #[doc = "Bit 11 - High detect enabled 43"] #[inline(always)] #[must_use] - pub fn hen43(&mut self) -> HEN43_W<11> { + pub fn hen43(&mut self) -> HEN43_W { HEN43_W::new(self) } #[doc = "Bit 12 - High detect enabled 44"] #[inline(always)] #[must_use] - pub fn hen44(&mut self) -> HEN44_W<12> { + pub fn hen44(&mut self) -> HEN44_W { HEN44_W::new(self) } #[doc = "Bit 13 - High detect enabled 45"] #[inline(always)] #[must_use] - pub fn hen45(&mut self) -> HEN45_W<13> { + pub fn hen45(&mut self) -> HEN45_W { HEN45_W::new(self) } #[doc = "Bit 14 - High detect enabled 46"] #[inline(always)] #[must_use] - pub fn hen46(&mut self) -> HEN46_W<14> { + pub fn hen46(&mut self) -> HEN46_W { HEN46_W::new(self) } #[doc = "Bit 15 - High detect enabled 47"] #[inline(always)] #[must_use] - pub fn hen47(&mut self) -> HEN47_W<15> { + pub fn hen47(&mut self) -> HEN47_W { HEN47_W::new(self) } #[doc = "Bit 16 - High detect enabled 48"] #[inline(always)] #[must_use] - pub fn hen48(&mut self) -> HEN48_W<16> { + pub fn hen48(&mut self) -> HEN48_W { HEN48_W::new(self) } #[doc = "Bit 17 - High detect enabled 49"] #[inline(always)] #[must_use] - pub fn hen49(&mut self) -> HEN49_W<17> { + pub fn hen49(&mut self) -> HEN49_W { HEN49_W::new(self) } #[doc = "Bit 18 - High detect enabled 50"] #[inline(always)] #[must_use] - pub fn hen50(&mut self) -> HEN50_W<18> { + pub fn hen50(&mut self) -> HEN50_W { HEN50_W::new(self) } #[doc = "Bit 19 - High detect enabled 51"] #[inline(always)] #[must_use] - pub fn hen51(&mut self) -> HEN51_W<19> { + pub fn hen51(&mut self) -> HEN51_W { HEN51_W::new(self) } #[doc = "Bit 20 - High detect enabled 52"] #[inline(always)] #[must_use] - pub fn hen52(&mut self) -> HEN52_W<20> { + pub fn hen52(&mut self) -> HEN52_W { HEN52_W::new(self) } #[doc = "Bit 21 - High detect enabled 53"] #[inline(always)] #[must_use] - pub fn hen53(&mut self) -> HEN53_W<21> { + pub fn hen53(&mut self) -> HEN53_W { HEN53_W::new(self) } #[doc = "Bit 22 - High detect enabled 54"] #[inline(always)] #[must_use] - pub fn hen54(&mut self) -> HEN54_W<22> { + pub fn hen54(&mut self) -> HEN54_W { HEN54_W::new(self) } #[doc = "Bit 23 - High detect enabled 55"] #[inline(always)] #[must_use] - pub fn hen55(&mut self) -> HEN55_W<23> { + pub fn hen55(&mut self) -> HEN55_W { HEN55_W::new(self) } #[doc = "Bit 24 - High detect enabled 56"] #[inline(always)] #[must_use] - pub fn hen56(&mut self) -> HEN56_W<24> { + pub fn hen56(&mut self) -> HEN56_W { HEN56_W::new(self) } #[doc = "Bit 25 - High detect enabled 57"] #[inline(always)] #[must_use] - pub fn hen57(&mut self) -> HEN57_W<25> { + pub fn hen57(&mut self) -> HEN57_W { HEN57_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin High Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gphen1](index.html) module"] +#[doc = "GPIO Pin High Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gphen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gphen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPHEN1_SPEC; impl crate::RegisterSpec for GPHEN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gphen1::R](R) reader structure"] -impl crate::Readable for GPHEN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gphen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gphen1::R`](R) reader structure"] +impl crate::Readable for GPHEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gphen1::W`](W) writer structure"] impl crate::Writable for GPHEN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs index 12b55c2..507543e 100644 --- a/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs +++ b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_PUP_PDN_CNTRL0` reader - Resistor select for 0"] -pub type GPIO_PUP_PDN_CNTRL0_R = crate::FieldReader; +pub type GPIO_PUP_PDN_CNTRL0_R = crate::FieldReader; #[doc = "Resistor select for 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -53,10 +21,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for BP_PULL_A { + type Ux = u8; +} impl GPIO_PUP_PDN_CNTRL0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(BP_PULL_A::NONE), 1 => Some(BP_PULL_A::UP), @@ -64,39 +35,42 @@ impl GPIO_PUP_PDN_CNTRL0_R { _ => None, } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "No pull"] #[inline(always)] pub fn is_none(&self) -> bool { *self == BP_PULL_A::NONE } - #[doc = "Checks if the value of the field is `UP`"] + #[doc = "Pull up"] #[inline(always)] pub fn is_up(&self) -> bool { *self == BP_PULL_A::UP } - #[doc = "Checks if the value of the field is `DOWN`"] + #[doc = "Pull down"] #[inline(always)] pub fn is_down(&self) -> bool { *self == BP_PULL_A::DOWN } } #[doc = "Field `GPIO_PUP_PDN_CNTRL0` writer - Resistor select for 0"] -pub type GPIO_PUP_PDN_CNTRL0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG0_SPEC, u8, BP_PULL_A, 2, O>; -impl<'a, const O: u8> GPIO_PUP_PDN_CNTRL0_W<'a, O> { +pub type GPIO_PUP_PDN_CNTRL0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, BP_PULL_A>; +impl<'a, REG, const O: u8> GPIO_PUP_PDN_CNTRL0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "No pull"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(BP_PULL_A::NONE) } #[doc = "Pull up"] #[inline(always)] - pub fn up(self) -> &'a mut W { + pub fn up(self) -> &'a mut crate::W { self.variant(BP_PULL_A::UP) } #[doc = "Pull down"] #[inline(always)] - pub fn down(self) -> &'a mut W { + pub fn down(self) -> &'a mut crate::W { self.variant(BP_PULL_A::DOWN) } } @@ -242,122 +216,230 @@ impl R { GPIO_PUP_PDN_CNTRL15_R::new(((self.bits >> 30) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PUP_PDN_CNTRL_REG0") + .field( + "gpio_pup_pdn_cntrl0", + &format_args!("{}", self.gpio_pup_pdn_cntrl0().bits()), + ) + .field( + "gpio_pup_pdn_cntrl1", + &format_args!("{}", self.gpio_pup_pdn_cntrl1().bits()), + ) + .field( + "gpio_pup_pdn_cntrl2", + &format_args!("{}", self.gpio_pup_pdn_cntrl2().bits()), + ) + .field( + "gpio_pup_pdn_cntrl3", + &format_args!("{}", self.gpio_pup_pdn_cntrl3().bits()), + ) + .field( + "gpio_pup_pdn_cntrl4", + &format_args!("{}", self.gpio_pup_pdn_cntrl4().bits()), + ) + .field( + "gpio_pup_pdn_cntrl5", + &format_args!("{}", self.gpio_pup_pdn_cntrl5().bits()), + ) + .field( + "gpio_pup_pdn_cntrl6", + &format_args!("{}", self.gpio_pup_pdn_cntrl6().bits()), + ) + .field( + "gpio_pup_pdn_cntrl7", + &format_args!("{}", self.gpio_pup_pdn_cntrl7().bits()), + ) + .field( + "gpio_pup_pdn_cntrl8", + &format_args!("{}", self.gpio_pup_pdn_cntrl8().bits()), + ) + .field( + "gpio_pup_pdn_cntrl9", + &format_args!("{}", self.gpio_pup_pdn_cntrl9().bits()), + ) + .field( + "gpio_pup_pdn_cntrl10", + &format_args!("{}", self.gpio_pup_pdn_cntrl10().bits()), + ) + .field( + "gpio_pup_pdn_cntrl11", + &format_args!("{}", self.gpio_pup_pdn_cntrl11().bits()), + ) + .field( + "gpio_pup_pdn_cntrl12", + &format_args!("{}", self.gpio_pup_pdn_cntrl12().bits()), + ) + .field( + "gpio_pup_pdn_cntrl13", + &format_args!("{}", self.gpio_pup_pdn_cntrl13().bits()), + ) + .field( + "gpio_pup_pdn_cntrl14", + &format_args!("{}", self.gpio_pup_pdn_cntrl14().bits()), + ) + .field( + "gpio_pup_pdn_cntrl15", + &format_args!("{}", self.gpio_pup_pdn_cntrl15().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Resistor select for 0"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl0(&mut self) -> GPIO_PUP_PDN_CNTRL0_W<0> { + pub fn gpio_pup_pdn_cntrl0( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL0_W { GPIO_PUP_PDN_CNTRL0_W::new(self) } #[doc = "Bits 2:3 - Resistor select for 1"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl1(&mut self) -> GPIO_PUP_PDN_CNTRL1_W<2> { + pub fn gpio_pup_pdn_cntrl1( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL1_W { GPIO_PUP_PDN_CNTRL1_W::new(self) } #[doc = "Bits 4:5 - Resistor select for 2"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl2(&mut self) -> GPIO_PUP_PDN_CNTRL2_W<4> { + pub fn gpio_pup_pdn_cntrl2( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL2_W { GPIO_PUP_PDN_CNTRL2_W::new(self) } #[doc = "Bits 6:7 - Resistor select for 3"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl3(&mut self) -> GPIO_PUP_PDN_CNTRL3_W<6> { + pub fn gpio_pup_pdn_cntrl3( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL3_W { GPIO_PUP_PDN_CNTRL3_W::new(self) } #[doc = "Bits 8:9 - Resistor select for 4"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl4(&mut self) -> GPIO_PUP_PDN_CNTRL4_W<8> { + pub fn gpio_pup_pdn_cntrl4( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL4_W { GPIO_PUP_PDN_CNTRL4_W::new(self) } #[doc = "Bits 10:11 - Resistor select for 5"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl5(&mut self) -> GPIO_PUP_PDN_CNTRL5_W<10> { + pub fn gpio_pup_pdn_cntrl5( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL5_W { GPIO_PUP_PDN_CNTRL5_W::new(self) } #[doc = "Bits 12:13 - Resistor select for 6"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl6(&mut self) -> GPIO_PUP_PDN_CNTRL6_W<12> { + pub fn gpio_pup_pdn_cntrl6( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL6_W { GPIO_PUP_PDN_CNTRL6_W::new(self) } #[doc = "Bits 14:15 - Resistor select for 7"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl7(&mut self) -> GPIO_PUP_PDN_CNTRL7_W<14> { + pub fn gpio_pup_pdn_cntrl7( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL7_W { GPIO_PUP_PDN_CNTRL7_W::new(self) } #[doc = "Bits 16:17 - Resistor select for 8"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl8(&mut self) -> GPIO_PUP_PDN_CNTRL8_W<16> { + pub fn gpio_pup_pdn_cntrl8( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL8_W { GPIO_PUP_PDN_CNTRL8_W::new(self) } #[doc = "Bits 18:19 - Resistor select for 9"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl9(&mut self) -> GPIO_PUP_PDN_CNTRL9_W<18> { + pub fn gpio_pup_pdn_cntrl9( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL9_W { GPIO_PUP_PDN_CNTRL9_W::new(self) } #[doc = "Bits 20:21 - Resistor select for 10"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl10(&mut self) -> GPIO_PUP_PDN_CNTRL10_W<20> { + pub fn gpio_pup_pdn_cntrl10( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL10_W { GPIO_PUP_PDN_CNTRL10_W::new(self) } #[doc = "Bits 22:23 - Resistor select for 11"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl11(&mut self) -> GPIO_PUP_PDN_CNTRL11_W<22> { + pub fn gpio_pup_pdn_cntrl11( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL11_W { GPIO_PUP_PDN_CNTRL11_W::new(self) } #[doc = "Bits 24:25 - Resistor select for 12"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl12(&mut self) -> GPIO_PUP_PDN_CNTRL12_W<24> { + pub fn gpio_pup_pdn_cntrl12( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL12_W { GPIO_PUP_PDN_CNTRL12_W::new(self) } #[doc = "Bits 26:27 - Resistor select for 13"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl13(&mut self) -> GPIO_PUP_PDN_CNTRL13_W<26> { + pub fn gpio_pup_pdn_cntrl13( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL13_W { GPIO_PUP_PDN_CNTRL13_W::new(self) } #[doc = "Bits 28:29 - Resistor select for 14"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl14(&mut self) -> GPIO_PUP_PDN_CNTRL14_W<28> { + pub fn gpio_pup_pdn_cntrl14( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL14_W { GPIO_PUP_PDN_CNTRL14_W::new(self) } #[doc = "Bits 30:31 - Resistor select for 15"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl15(&mut self) -> GPIO_PUP_PDN_CNTRL15_W<30> { + pub fn gpio_pup_pdn_cntrl15( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL15_W { GPIO_PUP_PDN_CNTRL15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pull-up / Pull-down Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg0](index.html) module"] +#[doc = "GPIO Pull-up / Pull-down Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_PUP_PDN_CNTRL_REG0_SPEC; impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg0::R](R) reader structure"] -impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_pup_pdn_cntrl_reg0::R`](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pup_pdn_cntrl_reg0::W`](W) writer structure"] impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs index 49faec3..877b1ae 100644 --- a/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs +++ b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs @@ -1,121 +1,73 @@ #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Resistor select for 16"] pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; #[doc = "Field `GPIO_PUP_PDN_CNTRL16` reader - Resistor select for 16"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL16_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL16` writer - Resistor select for 16"] -pub type GPIO_PUP_PDN_CNTRL16_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL17` reader - Resistor select for 17"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL17_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL17` writer - Resistor select for 17"] -pub type GPIO_PUP_PDN_CNTRL17_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL18` reader - Resistor select for 18"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL18_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL18` writer - Resistor select for 18"] -pub type GPIO_PUP_PDN_CNTRL18_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL19` reader - Resistor select for 19"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL19_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL19` writer - Resistor select for 19"] -pub type GPIO_PUP_PDN_CNTRL19_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL20` reader - Resistor select for 20"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL20_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL20` writer - Resistor select for 20"] -pub type GPIO_PUP_PDN_CNTRL20_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL21` reader - Resistor select for 21"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL21_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL21` writer - Resistor select for 21"] -pub type GPIO_PUP_PDN_CNTRL21_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL22` reader - Resistor select for 22"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL22_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL22` writer - Resistor select for 22"] -pub type GPIO_PUP_PDN_CNTRL22_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL23` reader - Resistor select for 23"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL23_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL23` writer - Resistor select for 23"] -pub type GPIO_PUP_PDN_CNTRL23_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL24` reader - Resistor select for 24"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL24_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL24` writer - Resistor select for 24"] -pub type GPIO_PUP_PDN_CNTRL24_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL25` reader - Resistor select for 25"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL25_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL25` writer - Resistor select for 25"] -pub type GPIO_PUP_PDN_CNTRL25_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL26` reader - Resistor select for 26"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL26_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL26` writer - Resistor select for 26"] -pub type GPIO_PUP_PDN_CNTRL26_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL27` reader - Resistor select for 27"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL27_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL27` writer - Resistor select for 27"] -pub type GPIO_PUP_PDN_CNTRL27_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL28` reader - Resistor select for 28"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL28_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL28` writer - Resistor select for 28"] -pub type GPIO_PUP_PDN_CNTRL28_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL29` reader - Resistor select for 29"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL29_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL29` writer - Resistor select for 29"] -pub type GPIO_PUP_PDN_CNTRL29_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL30` reader - Resistor select for 30"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL30_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL30` writer - Resistor select for 30"] -pub type GPIO_PUP_PDN_CNTRL30_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL31` reader - Resistor select for 31"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL31_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL16` writer - Resistor select for 16"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL16_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL17` writer - Resistor select for 17"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL17_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL18` writer - Resistor select for 18"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL18_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL19` writer - Resistor select for 19"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL19_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL20` writer - Resistor select for 20"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL20_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL21` writer - Resistor select for 21"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL21_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL22` writer - Resistor select for 22"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL22_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL23` writer - Resistor select for 23"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL23_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL24` writer - Resistor select for 24"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL24_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL25` writer - Resistor select for 25"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL25_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL26` writer - Resistor select for 26"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL26_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL27` writer - Resistor select for 27"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL27_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL28` writer - Resistor select for 28"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL28_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL29` writer - Resistor select for 29"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL29_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL30` writer - Resistor select for 30"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL30_W; #[doc = "Field `GPIO_PUP_PDN_CNTRL31` writer - Resistor select for 31"] -pub type GPIO_PUP_PDN_CNTRL31_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL31_W; impl R { #[doc = "Bits 0:1 - Resistor select for 16"] #[inline(always)] @@ -198,122 +150,230 @@ impl R { GPIO_PUP_PDN_CNTRL31_R::new(((self.bits >> 30) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PUP_PDN_CNTRL_REG1") + .field( + "gpio_pup_pdn_cntrl16", + &format_args!("{}", self.gpio_pup_pdn_cntrl16().bits()), + ) + .field( + "gpio_pup_pdn_cntrl17", + &format_args!("{}", self.gpio_pup_pdn_cntrl17().bits()), + ) + .field( + "gpio_pup_pdn_cntrl18", + &format_args!("{}", self.gpio_pup_pdn_cntrl18().bits()), + ) + .field( + "gpio_pup_pdn_cntrl19", + &format_args!("{}", self.gpio_pup_pdn_cntrl19().bits()), + ) + .field( + "gpio_pup_pdn_cntrl20", + &format_args!("{}", self.gpio_pup_pdn_cntrl20().bits()), + ) + .field( + "gpio_pup_pdn_cntrl21", + &format_args!("{}", self.gpio_pup_pdn_cntrl21().bits()), + ) + .field( + "gpio_pup_pdn_cntrl22", + &format_args!("{}", self.gpio_pup_pdn_cntrl22().bits()), + ) + .field( + "gpio_pup_pdn_cntrl23", + &format_args!("{}", self.gpio_pup_pdn_cntrl23().bits()), + ) + .field( + "gpio_pup_pdn_cntrl24", + &format_args!("{}", self.gpio_pup_pdn_cntrl24().bits()), + ) + .field( + "gpio_pup_pdn_cntrl25", + &format_args!("{}", self.gpio_pup_pdn_cntrl25().bits()), + ) + .field( + "gpio_pup_pdn_cntrl26", + &format_args!("{}", self.gpio_pup_pdn_cntrl26().bits()), + ) + .field( + "gpio_pup_pdn_cntrl27", + &format_args!("{}", self.gpio_pup_pdn_cntrl27().bits()), + ) + .field( + "gpio_pup_pdn_cntrl28", + &format_args!("{}", self.gpio_pup_pdn_cntrl28().bits()), + ) + .field( + "gpio_pup_pdn_cntrl29", + &format_args!("{}", self.gpio_pup_pdn_cntrl29().bits()), + ) + .field( + "gpio_pup_pdn_cntrl30", + &format_args!("{}", self.gpio_pup_pdn_cntrl30().bits()), + ) + .field( + "gpio_pup_pdn_cntrl31", + &format_args!("{}", self.gpio_pup_pdn_cntrl31().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Resistor select for 16"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl16(&mut self) -> GPIO_PUP_PDN_CNTRL16_W<0> { + pub fn gpio_pup_pdn_cntrl16( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL16_W { GPIO_PUP_PDN_CNTRL16_W::new(self) } #[doc = "Bits 2:3 - Resistor select for 17"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl17(&mut self) -> GPIO_PUP_PDN_CNTRL17_W<2> { + pub fn gpio_pup_pdn_cntrl17( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL17_W { GPIO_PUP_PDN_CNTRL17_W::new(self) } #[doc = "Bits 4:5 - Resistor select for 18"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl18(&mut self) -> GPIO_PUP_PDN_CNTRL18_W<4> { + pub fn gpio_pup_pdn_cntrl18( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL18_W { GPIO_PUP_PDN_CNTRL18_W::new(self) } #[doc = "Bits 6:7 - Resistor select for 19"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl19(&mut self) -> GPIO_PUP_PDN_CNTRL19_W<6> { + pub fn gpio_pup_pdn_cntrl19( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL19_W { GPIO_PUP_PDN_CNTRL19_W::new(self) } #[doc = "Bits 8:9 - Resistor select for 20"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl20(&mut self) -> GPIO_PUP_PDN_CNTRL20_W<8> { + pub fn gpio_pup_pdn_cntrl20( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL20_W { GPIO_PUP_PDN_CNTRL20_W::new(self) } #[doc = "Bits 10:11 - Resistor select for 21"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl21(&mut self) -> GPIO_PUP_PDN_CNTRL21_W<10> { + pub fn gpio_pup_pdn_cntrl21( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL21_W { GPIO_PUP_PDN_CNTRL21_W::new(self) } #[doc = "Bits 12:13 - Resistor select for 22"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl22(&mut self) -> GPIO_PUP_PDN_CNTRL22_W<12> { + pub fn gpio_pup_pdn_cntrl22( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL22_W { GPIO_PUP_PDN_CNTRL22_W::new(self) } #[doc = "Bits 14:15 - Resistor select for 23"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl23(&mut self) -> GPIO_PUP_PDN_CNTRL23_W<14> { + pub fn gpio_pup_pdn_cntrl23( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL23_W { GPIO_PUP_PDN_CNTRL23_W::new(self) } #[doc = "Bits 16:17 - Resistor select for 24"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl24(&mut self) -> GPIO_PUP_PDN_CNTRL24_W<16> { + pub fn gpio_pup_pdn_cntrl24( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL24_W { GPIO_PUP_PDN_CNTRL24_W::new(self) } #[doc = "Bits 18:19 - Resistor select for 25"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl25(&mut self) -> GPIO_PUP_PDN_CNTRL25_W<18> { + pub fn gpio_pup_pdn_cntrl25( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL25_W { GPIO_PUP_PDN_CNTRL25_W::new(self) } #[doc = "Bits 20:21 - Resistor select for 26"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl26(&mut self) -> GPIO_PUP_PDN_CNTRL26_W<20> { + pub fn gpio_pup_pdn_cntrl26( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL26_W { GPIO_PUP_PDN_CNTRL26_W::new(self) } #[doc = "Bits 22:23 - Resistor select for 27"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl27(&mut self) -> GPIO_PUP_PDN_CNTRL27_W<22> { + pub fn gpio_pup_pdn_cntrl27( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL27_W { GPIO_PUP_PDN_CNTRL27_W::new(self) } #[doc = "Bits 24:25 - Resistor select for 28"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl28(&mut self) -> GPIO_PUP_PDN_CNTRL28_W<24> { + pub fn gpio_pup_pdn_cntrl28( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL28_W { GPIO_PUP_PDN_CNTRL28_W::new(self) } #[doc = "Bits 26:27 - Resistor select for 29"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl29(&mut self) -> GPIO_PUP_PDN_CNTRL29_W<26> { + pub fn gpio_pup_pdn_cntrl29( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL29_W { GPIO_PUP_PDN_CNTRL29_W::new(self) } #[doc = "Bits 28:29 - Resistor select for 30"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl30(&mut self) -> GPIO_PUP_PDN_CNTRL30_W<28> { + pub fn gpio_pup_pdn_cntrl30( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL30_W { GPIO_PUP_PDN_CNTRL30_W::new(self) } #[doc = "Bits 30:31 - Resistor select for 31"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl31(&mut self) -> GPIO_PUP_PDN_CNTRL31_W<30> { + pub fn gpio_pup_pdn_cntrl31( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL31_W { GPIO_PUP_PDN_CNTRL31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pull-up / Pull-down Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg1](index.html) module"] +#[doc = "GPIO Pull-up / Pull-down Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_PUP_PDN_CNTRL_REG1_SPEC; impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg1::R](R) reader structure"] -impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_pup_pdn_cntrl_reg1::R`](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pup_pdn_cntrl_reg1::W`](W) writer structure"] impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs index 67047c9..dfd838d 100644 --- a/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs +++ b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs @@ -1,121 +1,73 @@ #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Resistor select for 32"] pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; #[doc = "Field `GPIO_PUP_PDN_CNTRL32` reader - Resistor select for 32"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL32_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL32` writer - Resistor select for 32"] -pub type GPIO_PUP_PDN_CNTRL32_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL33` reader - Resistor select for 33"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL33_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL33` writer - Resistor select for 33"] -pub type GPIO_PUP_PDN_CNTRL33_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL34` reader - Resistor select for 34"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL34_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL34` writer - Resistor select for 34"] -pub type GPIO_PUP_PDN_CNTRL34_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL35` reader - Resistor select for 35"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL35_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL35` writer - Resistor select for 35"] -pub type GPIO_PUP_PDN_CNTRL35_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL36` reader - Resistor select for 36"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL36_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL36` writer - Resistor select for 36"] -pub type GPIO_PUP_PDN_CNTRL36_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL37` reader - Resistor select for 37"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL37_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL37` writer - Resistor select for 37"] -pub type GPIO_PUP_PDN_CNTRL37_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL38` reader - Resistor select for 38"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL38_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL38` writer - Resistor select for 38"] -pub type GPIO_PUP_PDN_CNTRL38_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL39` reader - Resistor select for 39"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL39_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL39` writer - Resistor select for 39"] -pub type GPIO_PUP_PDN_CNTRL39_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL40` reader - Resistor select for 40"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL40_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL40` writer - Resistor select for 40"] -pub type GPIO_PUP_PDN_CNTRL40_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL41` reader - Resistor select for 41"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL41_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL41` writer - Resistor select for 41"] -pub type GPIO_PUP_PDN_CNTRL41_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL42` reader - Resistor select for 42"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL42_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL42` writer - Resistor select for 42"] -pub type GPIO_PUP_PDN_CNTRL42_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL43` reader - Resistor select for 43"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL43_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL43` writer - Resistor select for 43"] -pub type GPIO_PUP_PDN_CNTRL43_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL44` reader - Resistor select for 44"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL44_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL44` writer - Resistor select for 44"] -pub type GPIO_PUP_PDN_CNTRL44_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL45` reader - Resistor select for 45"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL45_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL45` writer - Resistor select for 45"] -pub type GPIO_PUP_PDN_CNTRL45_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL46` reader - Resistor select for 46"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL46_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL46` writer - Resistor select for 46"] -pub type GPIO_PUP_PDN_CNTRL46_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL47` reader - Resistor select for 47"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL47_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL32` writer - Resistor select for 32"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL32_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL33` writer - Resistor select for 33"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL33_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL34` writer - Resistor select for 34"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL34_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL35` writer - Resistor select for 35"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL35_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL36` writer - Resistor select for 36"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL36_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL37` writer - Resistor select for 37"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL37_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL38` writer - Resistor select for 38"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL38_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL39` writer - Resistor select for 39"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL39_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL40` writer - Resistor select for 40"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL40_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL41` writer - Resistor select for 41"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL41_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL42` writer - Resistor select for 42"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL42_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL43` writer - Resistor select for 43"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL43_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL44` writer - Resistor select for 44"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL44_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL45` writer - Resistor select for 45"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL45_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL46` writer - Resistor select for 46"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL46_W; #[doc = "Field `GPIO_PUP_PDN_CNTRL47` writer - Resistor select for 47"] -pub type GPIO_PUP_PDN_CNTRL47_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL47_W; impl R { #[doc = "Bits 0:1 - Resistor select for 32"] #[inline(always)] @@ -198,122 +150,230 @@ impl R { GPIO_PUP_PDN_CNTRL47_R::new(((self.bits >> 30) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PUP_PDN_CNTRL_REG2") + .field( + "gpio_pup_pdn_cntrl32", + &format_args!("{}", self.gpio_pup_pdn_cntrl32().bits()), + ) + .field( + "gpio_pup_pdn_cntrl33", + &format_args!("{}", self.gpio_pup_pdn_cntrl33().bits()), + ) + .field( + "gpio_pup_pdn_cntrl34", + &format_args!("{}", self.gpio_pup_pdn_cntrl34().bits()), + ) + .field( + "gpio_pup_pdn_cntrl35", + &format_args!("{}", self.gpio_pup_pdn_cntrl35().bits()), + ) + .field( + "gpio_pup_pdn_cntrl36", + &format_args!("{}", self.gpio_pup_pdn_cntrl36().bits()), + ) + .field( + "gpio_pup_pdn_cntrl37", + &format_args!("{}", self.gpio_pup_pdn_cntrl37().bits()), + ) + .field( + "gpio_pup_pdn_cntrl38", + &format_args!("{}", self.gpio_pup_pdn_cntrl38().bits()), + ) + .field( + "gpio_pup_pdn_cntrl39", + &format_args!("{}", self.gpio_pup_pdn_cntrl39().bits()), + ) + .field( + "gpio_pup_pdn_cntrl40", + &format_args!("{}", self.gpio_pup_pdn_cntrl40().bits()), + ) + .field( + "gpio_pup_pdn_cntrl41", + &format_args!("{}", self.gpio_pup_pdn_cntrl41().bits()), + ) + .field( + "gpio_pup_pdn_cntrl42", + &format_args!("{}", self.gpio_pup_pdn_cntrl42().bits()), + ) + .field( + "gpio_pup_pdn_cntrl43", + &format_args!("{}", self.gpio_pup_pdn_cntrl43().bits()), + ) + .field( + "gpio_pup_pdn_cntrl44", + &format_args!("{}", self.gpio_pup_pdn_cntrl44().bits()), + ) + .field( + "gpio_pup_pdn_cntrl45", + &format_args!("{}", self.gpio_pup_pdn_cntrl45().bits()), + ) + .field( + "gpio_pup_pdn_cntrl46", + &format_args!("{}", self.gpio_pup_pdn_cntrl46().bits()), + ) + .field( + "gpio_pup_pdn_cntrl47", + &format_args!("{}", self.gpio_pup_pdn_cntrl47().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Resistor select for 32"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl32(&mut self) -> GPIO_PUP_PDN_CNTRL32_W<0> { + pub fn gpio_pup_pdn_cntrl32( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL32_W { GPIO_PUP_PDN_CNTRL32_W::new(self) } #[doc = "Bits 2:3 - Resistor select for 33"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl33(&mut self) -> GPIO_PUP_PDN_CNTRL33_W<2> { + pub fn gpio_pup_pdn_cntrl33( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL33_W { GPIO_PUP_PDN_CNTRL33_W::new(self) } #[doc = "Bits 4:5 - Resistor select for 34"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl34(&mut self) -> GPIO_PUP_PDN_CNTRL34_W<4> { + pub fn gpio_pup_pdn_cntrl34( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL34_W { GPIO_PUP_PDN_CNTRL34_W::new(self) } #[doc = "Bits 6:7 - Resistor select for 35"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl35(&mut self) -> GPIO_PUP_PDN_CNTRL35_W<6> { + pub fn gpio_pup_pdn_cntrl35( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL35_W { GPIO_PUP_PDN_CNTRL35_W::new(self) } #[doc = "Bits 8:9 - Resistor select for 36"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl36(&mut self) -> GPIO_PUP_PDN_CNTRL36_W<8> { + pub fn gpio_pup_pdn_cntrl36( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL36_W { GPIO_PUP_PDN_CNTRL36_W::new(self) } #[doc = "Bits 10:11 - Resistor select for 37"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl37(&mut self) -> GPIO_PUP_PDN_CNTRL37_W<10> { + pub fn gpio_pup_pdn_cntrl37( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL37_W { GPIO_PUP_PDN_CNTRL37_W::new(self) } #[doc = "Bits 12:13 - Resistor select for 38"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl38(&mut self) -> GPIO_PUP_PDN_CNTRL38_W<12> { + pub fn gpio_pup_pdn_cntrl38( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL38_W { GPIO_PUP_PDN_CNTRL38_W::new(self) } #[doc = "Bits 14:15 - Resistor select for 39"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl39(&mut self) -> GPIO_PUP_PDN_CNTRL39_W<14> { + pub fn gpio_pup_pdn_cntrl39( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL39_W { GPIO_PUP_PDN_CNTRL39_W::new(self) } #[doc = "Bits 16:17 - Resistor select for 40"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl40(&mut self) -> GPIO_PUP_PDN_CNTRL40_W<16> { + pub fn gpio_pup_pdn_cntrl40( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL40_W { GPIO_PUP_PDN_CNTRL40_W::new(self) } #[doc = "Bits 18:19 - Resistor select for 41"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl41(&mut self) -> GPIO_PUP_PDN_CNTRL41_W<18> { + pub fn gpio_pup_pdn_cntrl41( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL41_W { GPIO_PUP_PDN_CNTRL41_W::new(self) } #[doc = "Bits 20:21 - Resistor select for 42"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl42(&mut self) -> GPIO_PUP_PDN_CNTRL42_W<20> { + pub fn gpio_pup_pdn_cntrl42( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL42_W { GPIO_PUP_PDN_CNTRL42_W::new(self) } #[doc = "Bits 22:23 - Resistor select for 43"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl43(&mut self) -> GPIO_PUP_PDN_CNTRL43_W<22> { + pub fn gpio_pup_pdn_cntrl43( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL43_W { GPIO_PUP_PDN_CNTRL43_W::new(self) } #[doc = "Bits 24:25 - Resistor select for 44"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl44(&mut self) -> GPIO_PUP_PDN_CNTRL44_W<24> { + pub fn gpio_pup_pdn_cntrl44( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL44_W { GPIO_PUP_PDN_CNTRL44_W::new(self) } #[doc = "Bits 26:27 - Resistor select for 45"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl45(&mut self) -> GPIO_PUP_PDN_CNTRL45_W<26> { + pub fn gpio_pup_pdn_cntrl45( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL45_W { GPIO_PUP_PDN_CNTRL45_W::new(self) } #[doc = "Bits 28:29 - Resistor select for 46"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl46(&mut self) -> GPIO_PUP_PDN_CNTRL46_W<28> { + pub fn gpio_pup_pdn_cntrl46( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL46_W { GPIO_PUP_PDN_CNTRL46_W::new(self) } #[doc = "Bits 30:31 - Resistor select for 47"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl47(&mut self) -> GPIO_PUP_PDN_CNTRL47_W<30> { + pub fn gpio_pup_pdn_cntrl47( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL47_W { GPIO_PUP_PDN_CNTRL47_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pull-up / Pull-down Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg2](index.html) module"] +#[doc = "GPIO Pull-up / Pull-down Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_PUP_PDN_CNTRL_REG2_SPEC; impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg2::R](R) reader structure"] -impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg2::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_pup_pdn_cntrl_reg2::R`](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pup_pdn_cntrl_reg2::W`](W) writer structure"] impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs index 272c950..77954a0 100644 --- a/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs +++ b/crates/bcm2711-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs @@ -1,91 +1,49 @@ #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Resistor select for 48"] pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; #[doc = "Field `GPIO_PUP_PDN_CNTRL48` reader - Resistor select for 48"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL48_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL48` writer - Resistor select for 48"] -pub type GPIO_PUP_PDN_CNTRL48_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL49` reader - Resistor select for 49"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL49_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL49` writer - Resistor select for 49"] -pub type GPIO_PUP_PDN_CNTRL49_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL50` reader - Resistor select for 50"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL50_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL50` writer - Resistor select for 50"] -pub type GPIO_PUP_PDN_CNTRL50_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL51` reader - Resistor select for 51"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL51_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL51` writer - Resistor select for 51"] -pub type GPIO_PUP_PDN_CNTRL51_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL52` reader - Resistor select for 52"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL52_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL52` writer - Resistor select for 52"] -pub type GPIO_PUP_PDN_CNTRL52_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL53` reader - Resistor select for 53"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL53_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL53` writer - Resistor select for 53"] -pub type GPIO_PUP_PDN_CNTRL53_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL54` reader - Resistor select for 54"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL54_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL54` writer - Resistor select for 54"] -pub type GPIO_PUP_PDN_CNTRL54_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL55` reader - Resistor select for 55"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL55_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL55` writer - Resistor select for 55"] -pub type GPIO_PUP_PDN_CNTRL55_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL56` reader - Resistor select for 56"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL56_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL56` writer - Resistor select for 56"] -pub type GPIO_PUP_PDN_CNTRL56_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL57` reader - Resistor select for 57"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL57_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL48` writer - Resistor select for 48"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL48_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL49` writer - Resistor select for 49"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL49_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL50` writer - Resistor select for 50"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL50_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL51` writer - Resistor select for 51"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL51_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL52` writer - Resistor select for 52"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL52_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL53` writer - Resistor select for 53"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL53_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL54` writer - Resistor select for 54"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL54_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL55` writer - Resistor select for 55"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL55_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL56` writer - Resistor select for 56"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL56_W; #[doc = "Field `GPIO_PUP_PDN_CNTRL57` writer - Resistor select for 57"] -pub type GPIO_PUP_PDN_CNTRL57_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL57_W; impl R { #[doc = "Bits 0:1 - Resistor select for 48"] #[inline(always)] @@ -138,86 +96,158 @@ impl R { GPIO_PUP_PDN_CNTRL57_R::new(((self.bits >> 18) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PUP_PDN_CNTRL_REG3") + .field( + "gpio_pup_pdn_cntrl48", + &format_args!("{}", self.gpio_pup_pdn_cntrl48().bits()), + ) + .field( + "gpio_pup_pdn_cntrl49", + &format_args!("{}", self.gpio_pup_pdn_cntrl49().bits()), + ) + .field( + "gpio_pup_pdn_cntrl50", + &format_args!("{}", self.gpio_pup_pdn_cntrl50().bits()), + ) + .field( + "gpio_pup_pdn_cntrl51", + &format_args!("{}", self.gpio_pup_pdn_cntrl51().bits()), + ) + .field( + "gpio_pup_pdn_cntrl52", + &format_args!("{}", self.gpio_pup_pdn_cntrl52().bits()), + ) + .field( + "gpio_pup_pdn_cntrl53", + &format_args!("{}", self.gpio_pup_pdn_cntrl53().bits()), + ) + .field( + "gpio_pup_pdn_cntrl54", + &format_args!("{}", self.gpio_pup_pdn_cntrl54().bits()), + ) + .field( + "gpio_pup_pdn_cntrl55", + &format_args!("{}", self.gpio_pup_pdn_cntrl55().bits()), + ) + .field( + "gpio_pup_pdn_cntrl56", + &format_args!("{}", self.gpio_pup_pdn_cntrl56().bits()), + ) + .field( + "gpio_pup_pdn_cntrl57", + &format_args!("{}", self.gpio_pup_pdn_cntrl57().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Resistor select for 48"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl48(&mut self) -> GPIO_PUP_PDN_CNTRL48_W<0> { + pub fn gpio_pup_pdn_cntrl48( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL48_W { GPIO_PUP_PDN_CNTRL48_W::new(self) } #[doc = "Bits 2:3 - Resistor select for 49"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl49(&mut self) -> GPIO_PUP_PDN_CNTRL49_W<2> { + pub fn gpio_pup_pdn_cntrl49( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL49_W { GPIO_PUP_PDN_CNTRL49_W::new(self) } #[doc = "Bits 4:5 - Resistor select for 50"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl50(&mut self) -> GPIO_PUP_PDN_CNTRL50_W<4> { + pub fn gpio_pup_pdn_cntrl50( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL50_W { GPIO_PUP_PDN_CNTRL50_W::new(self) } #[doc = "Bits 6:7 - Resistor select for 51"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl51(&mut self) -> GPIO_PUP_PDN_CNTRL51_W<6> { + pub fn gpio_pup_pdn_cntrl51( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL51_W { GPIO_PUP_PDN_CNTRL51_W::new(self) } #[doc = "Bits 8:9 - Resistor select for 52"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl52(&mut self) -> GPIO_PUP_PDN_CNTRL52_W<8> { + pub fn gpio_pup_pdn_cntrl52( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL52_W { GPIO_PUP_PDN_CNTRL52_W::new(self) } #[doc = "Bits 10:11 - Resistor select for 53"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl53(&mut self) -> GPIO_PUP_PDN_CNTRL53_W<10> { + pub fn gpio_pup_pdn_cntrl53( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL53_W { GPIO_PUP_PDN_CNTRL53_W::new(self) } #[doc = "Bits 12:13 - Resistor select for 54"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl54(&mut self) -> GPIO_PUP_PDN_CNTRL54_W<12> { + pub fn gpio_pup_pdn_cntrl54( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL54_W { GPIO_PUP_PDN_CNTRL54_W::new(self) } #[doc = "Bits 14:15 - Resistor select for 55"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl55(&mut self) -> GPIO_PUP_PDN_CNTRL55_W<14> { + pub fn gpio_pup_pdn_cntrl55( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL55_W { GPIO_PUP_PDN_CNTRL55_W::new(self) } #[doc = "Bits 16:17 - Resistor select for 56"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl56(&mut self) -> GPIO_PUP_PDN_CNTRL56_W<16> { + pub fn gpio_pup_pdn_cntrl56( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL56_W { GPIO_PUP_PDN_CNTRL56_W::new(self) } #[doc = "Bits 18:19 - Resistor select for 57"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl57(&mut self) -> GPIO_PUP_PDN_CNTRL57_W<18> { + pub fn gpio_pup_pdn_cntrl57( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL57_W { GPIO_PUP_PDN_CNTRL57_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pull-up / Pull-down Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg3](index.html) module"] +#[doc = "GPIO Pull-up / Pull-down Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_PUP_PDN_CNTRL_REG3_SPEC; impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg3::R](R) reader structure"] -impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg3::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_pup_pdn_cntrl_reg3::R`](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pup_pdn_cntrl_reg3::W`](W) writer structure"] impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gplen0.rs b/crates/bcm2711-lpa/src/gpio/gplen0.rs index 54f51bd..bfac268 100644 --- a/crates/bcm2711-lpa/src/gpio/gplen0.rs +++ b/crates/bcm2711-lpa/src/gpio/gplen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPLEN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPLEN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LEN0` reader - Low detect enabled 0"] -pub type LEN0_R = crate::BitReader; +pub type LEN0_R = crate::BitReader; #[doc = "Field `LEN0` writer - Low detect enabled 0"] -pub type LEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN1` reader - Low detect enabled 1"] -pub type LEN1_R = crate::BitReader; +pub type LEN1_R = crate::BitReader; #[doc = "Field `LEN1` writer - Low detect enabled 1"] -pub type LEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN2` reader - Low detect enabled 2"] -pub type LEN2_R = crate::BitReader; +pub type LEN2_R = crate::BitReader; #[doc = "Field `LEN2` writer - Low detect enabled 2"] -pub type LEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN3` reader - Low detect enabled 3"] -pub type LEN3_R = crate::BitReader; +pub type LEN3_R = crate::BitReader; #[doc = "Field `LEN3` writer - Low detect enabled 3"] -pub type LEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN4` reader - Low detect enabled 4"] -pub type LEN4_R = crate::BitReader; +pub type LEN4_R = crate::BitReader; #[doc = "Field `LEN4` writer - Low detect enabled 4"] -pub type LEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN5` reader - Low detect enabled 5"] -pub type LEN5_R = crate::BitReader; +pub type LEN5_R = crate::BitReader; #[doc = "Field `LEN5` writer - Low detect enabled 5"] -pub type LEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN6` reader - Low detect enabled 6"] -pub type LEN6_R = crate::BitReader; +pub type LEN6_R = crate::BitReader; #[doc = "Field `LEN6` writer - Low detect enabled 6"] -pub type LEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN7` reader - Low detect enabled 7"] -pub type LEN7_R = crate::BitReader; +pub type LEN7_R = crate::BitReader; #[doc = "Field `LEN7` writer - Low detect enabled 7"] -pub type LEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN8` reader - Low detect enabled 8"] -pub type LEN8_R = crate::BitReader; +pub type LEN8_R = crate::BitReader; #[doc = "Field `LEN8` writer - Low detect enabled 8"] -pub type LEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN9` reader - Low detect enabled 9"] -pub type LEN9_R = crate::BitReader; +pub type LEN9_R = crate::BitReader; #[doc = "Field `LEN9` writer - Low detect enabled 9"] -pub type LEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN10` reader - Low detect enabled 10"] -pub type LEN10_R = crate::BitReader; +pub type LEN10_R = crate::BitReader; #[doc = "Field `LEN10` writer - Low detect enabled 10"] -pub type LEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN11` reader - Low detect enabled 11"] -pub type LEN11_R = crate::BitReader; +pub type LEN11_R = crate::BitReader; #[doc = "Field `LEN11` writer - Low detect enabled 11"] -pub type LEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN12` reader - Low detect enabled 12"] -pub type LEN12_R = crate::BitReader; +pub type LEN12_R = crate::BitReader; #[doc = "Field `LEN12` writer - Low detect enabled 12"] -pub type LEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN13` reader - Low detect enabled 13"] -pub type LEN13_R = crate::BitReader; +pub type LEN13_R = crate::BitReader; #[doc = "Field `LEN13` writer - Low detect enabled 13"] -pub type LEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN14` reader - Low detect enabled 14"] -pub type LEN14_R = crate::BitReader; +pub type LEN14_R = crate::BitReader; #[doc = "Field `LEN14` writer - Low detect enabled 14"] -pub type LEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN15` reader - Low detect enabled 15"] -pub type LEN15_R = crate::BitReader; +pub type LEN15_R = crate::BitReader; #[doc = "Field `LEN15` writer - Low detect enabled 15"] -pub type LEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN16` reader - Low detect enabled 16"] -pub type LEN16_R = crate::BitReader; +pub type LEN16_R = crate::BitReader; #[doc = "Field `LEN16` writer - Low detect enabled 16"] -pub type LEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN17` reader - Low detect enabled 17"] -pub type LEN17_R = crate::BitReader; +pub type LEN17_R = crate::BitReader; #[doc = "Field `LEN17` writer - Low detect enabled 17"] -pub type LEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN18` reader - Low detect enabled 18"] -pub type LEN18_R = crate::BitReader; +pub type LEN18_R = crate::BitReader; #[doc = "Field `LEN18` writer - Low detect enabled 18"] -pub type LEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN19` reader - Low detect enabled 19"] -pub type LEN19_R = crate::BitReader; +pub type LEN19_R = crate::BitReader; #[doc = "Field `LEN19` writer - Low detect enabled 19"] -pub type LEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN20` reader - Low detect enabled 20"] -pub type LEN20_R = crate::BitReader; +pub type LEN20_R = crate::BitReader; #[doc = "Field `LEN20` writer - Low detect enabled 20"] -pub type LEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN21` reader - Low detect enabled 21"] -pub type LEN21_R = crate::BitReader; +pub type LEN21_R = crate::BitReader; #[doc = "Field `LEN21` writer - Low detect enabled 21"] -pub type LEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN22` reader - Low detect enabled 22"] -pub type LEN22_R = crate::BitReader; +pub type LEN22_R = crate::BitReader; #[doc = "Field `LEN22` writer - Low detect enabled 22"] -pub type LEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN23` reader - Low detect enabled 23"] -pub type LEN23_R = crate::BitReader; +pub type LEN23_R = crate::BitReader; #[doc = "Field `LEN23` writer - Low detect enabled 23"] -pub type LEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN24` reader - Low detect enabled 24"] -pub type LEN24_R = crate::BitReader; +pub type LEN24_R = crate::BitReader; #[doc = "Field `LEN24` writer - Low detect enabled 24"] -pub type LEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN25` reader - Low detect enabled 25"] -pub type LEN25_R = crate::BitReader; +pub type LEN25_R = crate::BitReader; #[doc = "Field `LEN25` writer - Low detect enabled 25"] -pub type LEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN26` reader - Low detect enabled 26"] -pub type LEN26_R = crate::BitReader; +pub type LEN26_R = crate::BitReader; #[doc = "Field `LEN26` writer - Low detect enabled 26"] -pub type LEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN27` reader - Low detect enabled 27"] -pub type LEN27_R = crate::BitReader; +pub type LEN27_R = crate::BitReader; #[doc = "Field `LEN27` writer - Low detect enabled 27"] -pub type LEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN28` reader - Low detect enabled 28"] -pub type LEN28_R = crate::BitReader; +pub type LEN28_R = crate::BitReader; #[doc = "Field `LEN28` writer - Low detect enabled 28"] -pub type LEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN29` reader - Low detect enabled 29"] -pub type LEN29_R = crate::BitReader; +pub type LEN29_R = crate::BitReader; #[doc = "Field `LEN29` writer - Low detect enabled 29"] -pub type LEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN30` reader - Low detect enabled 30"] -pub type LEN30_R = crate::BitReader; +pub type LEN30_R = crate::BitReader; #[doc = "Field `LEN30` writer - Low detect enabled 30"] -pub type LEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN31` reader - Low detect enabled 31"] -pub type LEN31_R = crate::BitReader; +pub type LEN31_R = crate::BitReader; #[doc = "Field `LEN31` writer - Low detect enabled 31"] -pub type LEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Low detect enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { LEN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPLEN0") + .field("len0", &format_args!("{}", self.len0().bit())) + .field("len1", &format_args!("{}", self.len1().bit())) + .field("len2", &format_args!("{}", self.len2().bit())) + .field("len3", &format_args!("{}", self.len3().bit())) + .field("len4", &format_args!("{}", self.len4().bit())) + .field("len5", &format_args!("{}", self.len5().bit())) + .field("len6", &format_args!("{}", self.len6().bit())) + .field("len7", &format_args!("{}", self.len7().bit())) + .field("len8", &format_args!("{}", self.len8().bit())) + .field("len9", &format_args!("{}", self.len9().bit())) + .field("len10", &format_args!("{}", self.len10().bit())) + .field("len11", &format_args!("{}", self.len11().bit())) + .field("len12", &format_args!("{}", self.len12().bit())) + .field("len13", &format_args!("{}", self.len13().bit())) + .field("len14", &format_args!("{}", self.len14().bit())) + .field("len15", &format_args!("{}", self.len15().bit())) + .field("len16", &format_args!("{}", self.len16().bit())) + .field("len17", &format_args!("{}", self.len17().bit())) + .field("len18", &format_args!("{}", self.len18().bit())) + .field("len19", &format_args!("{}", self.len19().bit())) + .field("len20", &format_args!("{}", self.len20().bit())) + .field("len21", &format_args!("{}", self.len21().bit())) + .field("len22", &format_args!("{}", self.len22().bit())) + .field("len23", &format_args!("{}", self.len23().bit())) + .field("len24", &format_args!("{}", self.len24().bit())) + .field("len25", &format_args!("{}", self.len25().bit())) + .field("len26", &format_args!("{}", self.len26().bit())) + .field("len27", &format_args!("{}", self.len27().bit())) + .field("len28", &format_args!("{}", self.len28().bit())) + .field("len29", &format_args!("{}", self.len29().bit())) + .field("len30", &format_args!("{}", self.len30().bit())) + .field("len31", &format_args!("{}", self.len31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Low detect enabled 0"] #[inline(always)] #[must_use] - pub fn len0(&mut self) -> LEN0_W<0> { + pub fn len0(&mut self) -> LEN0_W { LEN0_W::new(self) } #[doc = "Bit 1 - Low detect enabled 1"] #[inline(always)] #[must_use] - pub fn len1(&mut self) -> LEN1_W<1> { + pub fn len1(&mut self) -> LEN1_W { LEN1_W::new(self) } #[doc = "Bit 2 - Low detect enabled 2"] #[inline(always)] #[must_use] - pub fn len2(&mut self) -> LEN2_W<2> { + pub fn len2(&mut self) -> LEN2_W { LEN2_W::new(self) } #[doc = "Bit 3 - Low detect enabled 3"] #[inline(always)] #[must_use] - pub fn len3(&mut self) -> LEN3_W<3> { + pub fn len3(&mut self) -> LEN3_W { LEN3_W::new(self) } #[doc = "Bit 4 - Low detect enabled 4"] #[inline(always)] #[must_use] - pub fn len4(&mut self) -> LEN4_W<4> { + pub fn len4(&mut self) -> LEN4_W { LEN4_W::new(self) } #[doc = "Bit 5 - Low detect enabled 5"] #[inline(always)] #[must_use] - pub fn len5(&mut self) -> LEN5_W<5> { + pub fn len5(&mut self) -> LEN5_W { LEN5_W::new(self) } #[doc = "Bit 6 - Low detect enabled 6"] #[inline(always)] #[must_use] - pub fn len6(&mut self) -> LEN6_W<6> { + pub fn len6(&mut self) -> LEN6_W { LEN6_W::new(self) } #[doc = "Bit 7 - Low detect enabled 7"] #[inline(always)] #[must_use] - pub fn len7(&mut self) -> LEN7_W<7> { + pub fn len7(&mut self) -> LEN7_W { LEN7_W::new(self) } #[doc = "Bit 8 - Low detect enabled 8"] #[inline(always)] #[must_use] - pub fn len8(&mut self) -> LEN8_W<8> { + pub fn len8(&mut self) -> LEN8_W { LEN8_W::new(self) } #[doc = "Bit 9 - Low detect enabled 9"] #[inline(always)] #[must_use] - pub fn len9(&mut self) -> LEN9_W<9> { + pub fn len9(&mut self) -> LEN9_W { LEN9_W::new(self) } #[doc = "Bit 10 - Low detect enabled 10"] #[inline(always)] #[must_use] - pub fn len10(&mut self) -> LEN10_W<10> { + pub fn len10(&mut self) -> LEN10_W { LEN10_W::new(self) } #[doc = "Bit 11 - Low detect enabled 11"] #[inline(always)] #[must_use] - pub fn len11(&mut self) -> LEN11_W<11> { + pub fn len11(&mut self) -> LEN11_W { LEN11_W::new(self) } #[doc = "Bit 12 - Low detect enabled 12"] #[inline(always)] #[must_use] - pub fn len12(&mut self) -> LEN12_W<12> { + pub fn len12(&mut self) -> LEN12_W { LEN12_W::new(self) } #[doc = "Bit 13 - Low detect enabled 13"] #[inline(always)] #[must_use] - pub fn len13(&mut self) -> LEN13_W<13> { + pub fn len13(&mut self) -> LEN13_W { LEN13_W::new(self) } #[doc = "Bit 14 - Low detect enabled 14"] #[inline(always)] #[must_use] - pub fn len14(&mut self) -> LEN14_W<14> { + pub fn len14(&mut self) -> LEN14_W { LEN14_W::new(self) } #[doc = "Bit 15 - Low detect enabled 15"] #[inline(always)] #[must_use] - pub fn len15(&mut self) -> LEN15_W<15> { + pub fn len15(&mut self) -> LEN15_W { LEN15_W::new(self) } #[doc = "Bit 16 - Low detect enabled 16"] #[inline(always)] #[must_use] - pub fn len16(&mut self) -> LEN16_W<16> { + pub fn len16(&mut self) -> LEN16_W { LEN16_W::new(self) } #[doc = "Bit 17 - Low detect enabled 17"] #[inline(always)] #[must_use] - pub fn len17(&mut self) -> LEN17_W<17> { + pub fn len17(&mut self) -> LEN17_W { LEN17_W::new(self) } #[doc = "Bit 18 - Low detect enabled 18"] #[inline(always)] #[must_use] - pub fn len18(&mut self) -> LEN18_W<18> { + pub fn len18(&mut self) -> LEN18_W { LEN18_W::new(self) } #[doc = "Bit 19 - Low detect enabled 19"] #[inline(always)] #[must_use] - pub fn len19(&mut self) -> LEN19_W<19> { + pub fn len19(&mut self) -> LEN19_W { LEN19_W::new(self) } #[doc = "Bit 20 - Low detect enabled 20"] #[inline(always)] #[must_use] - pub fn len20(&mut self) -> LEN20_W<20> { + pub fn len20(&mut self) -> LEN20_W { LEN20_W::new(self) } #[doc = "Bit 21 - Low detect enabled 21"] #[inline(always)] #[must_use] - pub fn len21(&mut self) -> LEN21_W<21> { + pub fn len21(&mut self) -> LEN21_W { LEN21_W::new(self) } #[doc = "Bit 22 - Low detect enabled 22"] #[inline(always)] #[must_use] - pub fn len22(&mut self) -> LEN22_W<22> { + pub fn len22(&mut self) -> LEN22_W { LEN22_W::new(self) } #[doc = "Bit 23 - Low detect enabled 23"] #[inline(always)] #[must_use] - pub fn len23(&mut self) -> LEN23_W<23> { + pub fn len23(&mut self) -> LEN23_W { LEN23_W::new(self) } #[doc = "Bit 24 - Low detect enabled 24"] #[inline(always)] #[must_use] - pub fn len24(&mut self) -> LEN24_W<24> { + pub fn len24(&mut self) -> LEN24_W { LEN24_W::new(self) } #[doc = "Bit 25 - Low detect enabled 25"] #[inline(always)] #[must_use] - pub fn len25(&mut self) -> LEN25_W<25> { + pub fn len25(&mut self) -> LEN25_W { LEN25_W::new(self) } #[doc = "Bit 26 - Low detect enabled 26"] #[inline(always)] #[must_use] - pub fn len26(&mut self) -> LEN26_W<26> { + pub fn len26(&mut self) -> LEN26_W { LEN26_W::new(self) } #[doc = "Bit 27 - Low detect enabled 27"] #[inline(always)] #[must_use] - pub fn len27(&mut self) -> LEN27_W<27> { + pub fn len27(&mut self) -> LEN27_W { LEN27_W::new(self) } #[doc = "Bit 28 - Low detect enabled 28"] #[inline(always)] #[must_use] - pub fn len28(&mut self) -> LEN28_W<28> { + pub fn len28(&mut self) -> LEN28_W { LEN28_W::new(self) } #[doc = "Bit 29 - Low detect enabled 29"] #[inline(always)] #[must_use] - pub fn len29(&mut self) -> LEN29_W<29> { + pub fn len29(&mut self) -> LEN29_W { LEN29_W::new(self) } #[doc = "Bit 30 - Low detect enabled 30"] #[inline(always)] #[must_use] - pub fn len30(&mut self) -> LEN30_W<30> { + pub fn len30(&mut self) -> LEN30_W { LEN30_W::new(self) } #[doc = "Bit 31 - Low detect enabled 31"] #[inline(always)] #[must_use] - pub fn len31(&mut self) -> LEN31_W<31> { + pub fn len31(&mut self) -> LEN31_W { LEN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Low Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplen0](index.html) module"] +#[doc = "GPIO Pin Low Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gplen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPLEN0_SPEC; impl crate::RegisterSpec for GPLEN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gplen0::R](R) reader structure"] -impl crate::Readable for GPLEN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gplen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gplen0::R`](R) reader structure"] +impl crate::Readable for GPLEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gplen0::W`](W) writer structure"] impl crate::Writable for GPLEN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gplen1.rs b/crates/bcm2711-lpa/src/gpio/gplen1.rs index 76fbc70..72455bd 100644 --- a/crates/bcm2711-lpa/src/gpio/gplen1.rs +++ b/crates/bcm2711-lpa/src/gpio/gplen1.rs @@ -1,143 +1,111 @@ #[doc = "Register `GPLEN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPLEN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LEN32` reader - Low detect enabled 32"] -pub type LEN32_R = crate::BitReader; +pub type LEN32_R = crate::BitReader; #[doc = "Field `LEN32` writer - Low detect enabled 32"] -pub type LEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN33` reader - Low detect enabled 33"] -pub type LEN33_R = crate::BitReader; +pub type LEN33_R = crate::BitReader; #[doc = "Field `LEN33` writer - Low detect enabled 33"] -pub type LEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN34` reader - Low detect enabled 34"] -pub type LEN34_R = crate::BitReader; +pub type LEN34_R = crate::BitReader; #[doc = "Field `LEN34` writer - Low detect enabled 34"] -pub type LEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN35` reader - Low detect enabled 35"] -pub type LEN35_R = crate::BitReader; +pub type LEN35_R = crate::BitReader; #[doc = "Field `LEN35` writer - Low detect enabled 35"] -pub type LEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN36` reader - Low detect enabled 36"] -pub type LEN36_R = crate::BitReader; +pub type LEN36_R = crate::BitReader; #[doc = "Field `LEN36` writer - Low detect enabled 36"] -pub type LEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN37` reader - Low detect enabled 37"] -pub type LEN37_R = crate::BitReader; +pub type LEN37_R = crate::BitReader; #[doc = "Field `LEN37` writer - Low detect enabled 37"] -pub type LEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN38` reader - Low detect enabled 38"] -pub type LEN38_R = crate::BitReader; +pub type LEN38_R = crate::BitReader; #[doc = "Field `LEN38` writer - Low detect enabled 38"] -pub type LEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN39` reader - Low detect enabled 39"] -pub type LEN39_R = crate::BitReader; +pub type LEN39_R = crate::BitReader; #[doc = "Field `LEN39` writer - Low detect enabled 39"] -pub type LEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN40` reader - Low detect enabled 40"] -pub type LEN40_R = crate::BitReader; +pub type LEN40_R = crate::BitReader; #[doc = "Field `LEN40` writer - Low detect enabled 40"] -pub type LEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN41` reader - Low detect enabled 41"] -pub type LEN41_R = crate::BitReader; +pub type LEN41_R = crate::BitReader; #[doc = "Field `LEN41` writer - Low detect enabled 41"] -pub type LEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN42` reader - Low detect enabled 42"] -pub type LEN42_R = crate::BitReader; +pub type LEN42_R = crate::BitReader; #[doc = "Field `LEN42` writer - Low detect enabled 42"] -pub type LEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN43` reader - Low detect enabled 43"] -pub type LEN43_R = crate::BitReader; +pub type LEN43_R = crate::BitReader; #[doc = "Field `LEN43` writer - Low detect enabled 43"] -pub type LEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN44` reader - Low detect enabled 44"] -pub type LEN44_R = crate::BitReader; +pub type LEN44_R = crate::BitReader; #[doc = "Field `LEN44` writer - Low detect enabled 44"] -pub type LEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN45` reader - Low detect enabled 45"] -pub type LEN45_R = crate::BitReader; +pub type LEN45_R = crate::BitReader; #[doc = "Field `LEN45` writer - Low detect enabled 45"] -pub type LEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN46` reader - Low detect enabled 46"] -pub type LEN46_R = crate::BitReader; +pub type LEN46_R = crate::BitReader; #[doc = "Field `LEN46` writer - Low detect enabled 46"] -pub type LEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN47` reader - Low detect enabled 47"] -pub type LEN47_R = crate::BitReader; +pub type LEN47_R = crate::BitReader; #[doc = "Field `LEN47` writer - Low detect enabled 47"] -pub type LEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN48` reader - Low detect enabled 48"] -pub type LEN48_R = crate::BitReader; +pub type LEN48_R = crate::BitReader; #[doc = "Field `LEN48` writer - Low detect enabled 48"] -pub type LEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN49` reader - Low detect enabled 49"] -pub type LEN49_R = crate::BitReader; +pub type LEN49_R = crate::BitReader; #[doc = "Field `LEN49` writer - Low detect enabled 49"] -pub type LEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN50` reader - Low detect enabled 50"] -pub type LEN50_R = crate::BitReader; +pub type LEN50_R = crate::BitReader; #[doc = "Field `LEN50` writer - Low detect enabled 50"] -pub type LEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN51` reader - Low detect enabled 51"] -pub type LEN51_R = crate::BitReader; +pub type LEN51_R = crate::BitReader; #[doc = "Field `LEN51` writer - Low detect enabled 51"] -pub type LEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN52` reader - Low detect enabled 52"] -pub type LEN52_R = crate::BitReader; +pub type LEN52_R = crate::BitReader; #[doc = "Field `LEN52` writer - Low detect enabled 52"] -pub type LEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN53` reader - Low detect enabled 53"] -pub type LEN53_R = crate::BitReader; +pub type LEN53_R = crate::BitReader; #[doc = "Field `LEN53` writer - Low detect enabled 53"] -pub type LEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN54` reader - Low detect enabled 54"] -pub type LEN54_R = crate::BitReader; +pub type LEN54_R = crate::BitReader; #[doc = "Field `LEN54` writer - Low detect enabled 54"] -pub type LEN54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN54_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN55` reader - Low detect enabled 55"] -pub type LEN55_R = crate::BitReader; +pub type LEN55_R = crate::BitReader; #[doc = "Field `LEN55` writer - Low detect enabled 55"] -pub type LEN55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN55_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN56` reader - Low detect enabled 56"] -pub type LEN56_R = crate::BitReader; +pub type LEN56_R = crate::BitReader; #[doc = "Field `LEN56` writer - Low detect enabled 56"] -pub type LEN56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN57` reader - Low detect enabled 57"] -pub type LEN57_R = crate::BitReader; +pub type LEN57_R = crate::BitReader; #[doc = "Field `LEN57` writer - Low detect enabled 57"] -pub type LEN57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Low detect enabled 32"] #[inline(always)] @@ -270,182 +238,220 @@ impl R { LEN57_R::new(((self.bits >> 25) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPLEN1") + .field("len32", &format_args!("{}", self.len32().bit())) + .field("len33", &format_args!("{}", self.len33().bit())) + .field("len34", &format_args!("{}", self.len34().bit())) + .field("len35", &format_args!("{}", self.len35().bit())) + .field("len36", &format_args!("{}", self.len36().bit())) + .field("len37", &format_args!("{}", self.len37().bit())) + .field("len38", &format_args!("{}", self.len38().bit())) + .field("len39", &format_args!("{}", self.len39().bit())) + .field("len40", &format_args!("{}", self.len40().bit())) + .field("len41", &format_args!("{}", self.len41().bit())) + .field("len42", &format_args!("{}", self.len42().bit())) + .field("len43", &format_args!("{}", self.len43().bit())) + .field("len44", &format_args!("{}", self.len44().bit())) + .field("len45", &format_args!("{}", self.len45().bit())) + .field("len46", &format_args!("{}", self.len46().bit())) + .field("len47", &format_args!("{}", self.len47().bit())) + .field("len48", &format_args!("{}", self.len48().bit())) + .field("len49", &format_args!("{}", self.len49().bit())) + .field("len50", &format_args!("{}", self.len50().bit())) + .field("len51", &format_args!("{}", self.len51().bit())) + .field("len52", &format_args!("{}", self.len52().bit())) + .field("len53", &format_args!("{}", self.len53().bit())) + .field("len54", &format_args!("{}", self.len54().bit())) + .field("len55", &format_args!("{}", self.len55().bit())) + .field("len56", &format_args!("{}", self.len56().bit())) + .field("len57", &format_args!("{}", self.len57().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Low detect enabled 32"] #[inline(always)] #[must_use] - pub fn len32(&mut self) -> LEN32_W<0> { + pub fn len32(&mut self) -> LEN32_W { LEN32_W::new(self) } #[doc = "Bit 1 - Low detect enabled 33"] #[inline(always)] #[must_use] - pub fn len33(&mut self) -> LEN33_W<1> { + pub fn len33(&mut self) -> LEN33_W { LEN33_W::new(self) } #[doc = "Bit 2 - Low detect enabled 34"] #[inline(always)] #[must_use] - pub fn len34(&mut self) -> LEN34_W<2> { + pub fn len34(&mut self) -> LEN34_W { LEN34_W::new(self) } #[doc = "Bit 3 - Low detect enabled 35"] #[inline(always)] #[must_use] - pub fn len35(&mut self) -> LEN35_W<3> { + pub fn len35(&mut self) -> LEN35_W { LEN35_W::new(self) } #[doc = "Bit 4 - Low detect enabled 36"] #[inline(always)] #[must_use] - pub fn len36(&mut self) -> LEN36_W<4> { + pub fn len36(&mut self) -> LEN36_W { LEN36_W::new(self) } #[doc = "Bit 5 - Low detect enabled 37"] #[inline(always)] #[must_use] - pub fn len37(&mut self) -> LEN37_W<5> { + pub fn len37(&mut self) -> LEN37_W { LEN37_W::new(self) } #[doc = "Bit 6 - Low detect enabled 38"] #[inline(always)] #[must_use] - pub fn len38(&mut self) -> LEN38_W<6> { + pub fn len38(&mut self) -> LEN38_W { LEN38_W::new(self) } #[doc = "Bit 7 - Low detect enabled 39"] #[inline(always)] #[must_use] - pub fn len39(&mut self) -> LEN39_W<7> { + pub fn len39(&mut self) -> LEN39_W { LEN39_W::new(self) } #[doc = "Bit 8 - Low detect enabled 40"] #[inline(always)] #[must_use] - pub fn len40(&mut self) -> LEN40_W<8> { + pub fn len40(&mut self) -> LEN40_W { LEN40_W::new(self) } #[doc = "Bit 9 - Low detect enabled 41"] #[inline(always)] #[must_use] - pub fn len41(&mut self) -> LEN41_W<9> { + pub fn len41(&mut self) -> LEN41_W { LEN41_W::new(self) } #[doc = "Bit 10 - Low detect enabled 42"] #[inline(always)] #[must_use] - pub fn len42(&mut self) -> LEN42_W<10> { + pub fn len42(&mut self) -> LEN42_W { LEN42_W::new(self) } #[doc = "Bit 11 - Low detect enabled 43"] #[inline(always)] #[must_use] - pub fn len43(&mut self) -> LEN43_W<11> { + pub fn len43(&mut self) -> LEN43_W { LEN43_W::new(self) } #[doc = "Bit 12 - Low detect enabled 44"] #[inline(always)] #[must_use] - pub fn len44(&mut self) -> LEN44_W<12> { + pub fn len44(&mut self) -> LEN44_W { LEN44_W::new(self) } #[doc = "Bit 13 - Low detect enabled 45"] #[inline(always)] #[must_use] - pub fn len45(&mut self) -> LEN45_W<13> { + pub fn len45(&mut self) -> LEN45_W { LEN45_W::new(self) } #[doc = "Bit 14 - Low detect enabled 46"] #[inline(always)] #[must_use] - pub fn len46(&mut self) -> LEN46_W<14> { + pub fn len46(&mut self) -> LEN46_W { LEN46_W::new(self) } #[doc = "Bit 15 - Low detect enabled 47"] #[inline(always)] #[must_use] - pub fn len47(&mut self) -> LEN47_W<15> { + pub fn len47(&mut self) -> LEN47_W { LEN47_W::new(self) } #[doc = "Bit 16 - Low detect enabled 48"] #[inline(always)] #[must_use] - pub fn len48(&mut self) -> LEN48_W<16> { + pub fn len48(&mut self) -> LEN48_W { LEN48_W::new(self) } #[doc = "Bit 17 - Low detect enabled 49"] #[inline(always)] #[must_use] - pub fn len49(&mut self) -> LEN49_W<17> { + pub fn len49(&mut self) -> LEN49_W { LEN49_W::new(self) } #[doc = "Bit 18 - Low detect enabled 50"] #[inline(always)] #[must_use] - pub fn len50(&mut self) -> LEN50_W<18> { + pub fn len50(&mut self) -> LEN50_W { LEN50_W::new(self) } #[doc = "Bit 19 - Low detect enabled 51"] #[inline(always)] #[must_use] - pub fn len51(&mut self) -> LEN51_W<19> { + pub fn len51(&mut self) -> LEN51_W { LEN51_W::new(self) } #[doc = "Bit 20 - Low detect enabled 52"] #[inline(always)] #[must_use] - pub fn len52(&mut self) -> LEN52_W<20> { + pub fn len52(&mut self) -> LEN52_W { LEN52_W::new(self) } #[doc = "Bit 21 - Low detect enabled 53"] #[inline(always)] #[must_use] - pub fn len53(&mut self) -> LEN53_W<21> { + pub fn len53(&mut self) -> LEN53_W { LEN53_W::new(self) } #[doc = "Bit 22 - Low detect enabled 54"] #[inline(always)] #[must_use] - pub fn len54(&mut self) -> LEN54_W<22> { + pub fn len54(&mut self) -> LEN54_W { LEN54_W::new(self) } #[doc = "Bit 23 - Low detect enabled 55"] #[inline(always)] #[must_use] - pub fn len55(&mut self) -> LEN55_W<23> { + pub fn len55(&mut self) -> LEN55_W { LEN55_W::new(self) } #[doc = "Bit 24 - Low detect enabled 56"] #[inline(always)] #[must_use] - pub fn len56(&mut self) -> LEN56_W<24> { + pub fn len56(&mut self) -> LEN56_W { LEN56_W::new(self) } #[doc = "Bit 25 - Low detect enabled 57"] #[inline(always)] #[must_use] - pub fn len57(&mut self) -> LEN57_W<25> { + pub fn len57(&mut self) -> LEN57_W { LEN57_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Low Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplen1](index.html) module"] +#[doc = "GPIO Pin Low Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gplen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPLEN1_SPEC; impl crate::RegisterSpec for GPLEN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gplen1::R](R) reader structure"] -impl crate::Readable for GPLEN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gplen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gplen1::R`](R) reader structure"] +impl crate::Readable for GPLEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gplen1::W`](W) writer structure"] impl crate::Writable for GPLEN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gplev0.rs b/crates/bcm2711-lpa/src/gpio/gplev0.rs index e6f9b94..43e1e5c 100644 --- a/crates/bcm2711-lpa/src/gpio/gplev0.rs +++ b/crates/bcm2711-lpa/src/gpio/gplev0.rs @@ -1,82 +1,69 @@ #[doc = "Register `GPLEV0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LEV0` reader - Level 0"] -pub type LEV0_R = crate::BitReader; +pub type LEV0_R = crate::BitReader; #[doc = "Field `LEV1` reader - Level 1"] -pub type LEV1_R = crate::BitReader; +pub type LEV1_R = crate::BitReader; #[doc = "Field `LEV2` reader - Level 2"] -pub type LEV2_R = crate::BitReader; +pub type LEV2_R = crate::BitReader; #[doc = "Field `LEV3` reader - Level 3"] -pub type LEV3_R = crate::BitReader; +pub type LEV3_R = crate::BitReader; #[doc = "Field `LEV4` reader - Level 4"] -pub type LEV4_R = crate::BitReader; +pub type LEV4_R = crate::BitReader; #[doc = "Field `LEV5` reader - Level 5"] -pub type LEV5_R = crate::BitReader; +pub type LEV5_R = crate::BitReader; #[doc = "Field `LEV6` reader - Level 6"] -pub type LEV6_R = crate::BitReader; +pub type LEV6_R = crate::BitReader; #[doc = "Field `LEV7` reader - Level 7"] -pub type LEV7_R = crate::BitReader; +pub type LEV7_R = crate::BitReader; #[doc = "Field `LEV8` reader - Level 8"] -pub type LEV8_R = crate::BitReader; +pub type LEV8_R = crate::BitReader; #[doc = "Field `LEV9` reader - Level 9"] -pub type LEV9_R = crate::BitReader; +pub type LEV9_R = crate::BitReader; #[doc = "Field `LEV10` reader - Level 10"] -pub type LEV10_R = crate::BitReader; +pub type LEV10_R = crate::BitReader; #[doc = "Field `LEV11` reader - Level 11"] -pub type LEV11_R = crate::BitReader; +pub type LEV11_R = crate::BitReader; #[doc = "Field `LEV12` reader - Level 12"] -pub type LEV12_R = crate::BitReader; +pub type LEV12_R = crate::BitReader; #[doc = "Field `LEV13` reader - Level 13"] -pub type LEV13_R = crate::BitReader; +pub type LEV13_R = crate::BitReader; #[doc = "Field `LEV14` reader - Level 14"] -pub type LEV14_R = crate::BitReader; +pub type LEV14_R = crate::BitReader; #[doc = "Field `LEV15` reader - Level 15"] -pub type LEV15_R = crate::BitReader; +pub type LEV15_R = crate::BitReader; #[doc = "Field `LEV16` reader - Level 16"] -pub type LEV16_R = crate::BitReader; +pub type LEV16_R = crate::BitReader; #[doc = "Field `LEV17` reader - Level 17"] -pub type LEV17_R = crate::BitReader; +pub type LEV17_R = crate::BitReader; #[doc = "Field `LEV18` reader - Level 18"] -pub type LEV18_R = crate::BitReader; +pub type LEV18_R = crate::BitReader; #[doc = "Field `LEV19` reader - Level 19"] -pub type LEV19_R = crate::BitReader; +pub type LEV19_R = crate::BitReader; #[doc = "Field `LEV20` reader - Level 20"] -pub type LEV20_R = crate::BitReader; +pub type LEV20_R = crate::BitReader; #[doc = "Field `LEV21` reader - Level 21"] -pub type LEV21_R = crate::BitReader; +pub type LEV21_R = crate::BitReader; #[doc = "Field `LEV22` reader - Level 22"] -pub type LEV22_R = crate::BitReader; +pub type LEV22_R = crate::BitReader; #[doc = "Field `LEV23` reader - Level 23"] -pub type LEV23_R = crate::BitReader; +pub type LEV23_R = crate::BitReader; #[doc = "Field `LEV24` reader - Level 24"] -pub type LEV24_R = crate::BitReader; +pub type LEV24_R = crate::BitReader; #[doc = "Field `LEV25` reader - Level 25"] -pub type LEV25_R = crate::BitReader; +pub type LEV25_R = crate::BitReader; #[doc = "Field `LEV26` reader - Level 26"] -pub type LEV26_R = crate::BitReader; +pub type LEV26_R = crate::BitReader; #[doc = "Field `LEV27` reader - Level 27"] -pub type LEV27_R = crate::BitReader; +pub type LEV27_R = crate::BitReader; #[doc = "Field `LEV28` reader - Level 28"] -pub type LEV28_R = crate::BitReader; +pub type LEV28_R = crate::BitReader; #[doc = "Field `LEV29` reader - Level 29"] -pub type LEV29_R = crate::BitReader; +pub type LEV29_R = crate::BitReader; #[doc = "Field `LEV30` reader - Level 30"] -pub type LEV30_R = crate::BitReader; +pub type LEV30_R = crate::BitReader; #[doc = "Field `LEV31` reader - Level 31"] -pub type LEV31_R = crate::BitReader; +pub type LEV31_R = crate::BitReader; impl R { #[doc = "Bit 0 - Level 0"] #[inline(always)] @@ -239,12 +226,53 @@ impl R { LEV31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "GPIO Pin Level 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplev0](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPLEV0") + .field("lev0", &format_args!("{}", self.lev0().bit())) + .field("lev1", &format_args!("{}", self.lev1().bit())) + .field("lev2", &format_args!("{}", self.lev2().bit())) + .field("lev3", &format_args!("{}", self.lev3().bit())) + .field("lev4", &format_args!("{}", self.lev4().bit())) + .field("lev5", &format_args!("{}", self.lev5().bit())) + .field("lev6", &format_args!("{}", self.lev6().bit())) + .field("lev7", &format_args!("{}", self.lev7().bit())) + .field("lev8", &format_args!("{}", self.lev8().bit())) + .field("lev9", &format_args!("{}", self.lev9().bit())) + .field("lev10", &format_args!("{}", self.lev10().bit())) + .field("lev11", &format_args!("{}", self.lev11().bit())) + .field("lev12", &format_args!("{}", self.lev12().bit())) + .field("lev13", &format_args!("{}", self.lev13().bit())) + .field("lev14", &format_args!("{}", self.lev14().bit())) + .field("lev15", &format_args!("{}", self.lev15().bit())) + .field("lev16", &format_args!("{}", self.lev16().bit())) + .field("lev17", &format_args!("{}", self.lev17().bit())) + .field("lev18", &format_args!("{}", self.lev18().bit())) + .field("lev19", &format_args!("{}", self.lev19().bit())) + .field("lev20", &format_args!("{}", self.lev20().bit())) + .field("lev21", &format_args!("{}", self.lev21().bit())) + .field("lev22", &format_args!("{}", self.lev22().bit())) + .field("lev23", &format_args!("{}", self.lev23().bit())) + .field("lev24", &format_args!("{}", self.lev24().bit())) + .field("lev25", &format_args!("{}", self.lev25().bit())) + .field("lev26", &format_args!("{}", self.lev26().bit())) + .field("lev27", &format_args!("{}", self.lev27().bit())) + .field("lev28", &format_args!("{}", self.lev28().bit())) + .field("lev29", &format_args!("{}", self.lev29().bit())) + .field("lev30", &format_args!("{}", self.lev30().bit())) + .field("lev31", &format_args!("{}", self.lev31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "GPIO Pin Level 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplev0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPLEV0_SPEC; impl crate::RegisterSpec for GPLEV0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gplev0::R](R) reader structure"] -impl crate::Readable for GPLEV0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gplev0::R`](R) reader structure"] +impl crate::Readable for GPLEV0_SPEC {} diff --git a/crates/bcm2711-lpa/src/gpio/gplev1.rs b/crates/bcm2711-lpa/src/gpio/gplev1.rs index c351377..fc828ee 100644 --- a/crates/bcm2711-lpa/src/gpio/gplev1.rs +++ b/crates/bcm2711-lpa/src/gpio/gplev1.rs @@ -1,70 +1,57 @@ #[doc = "Register `GPLEV1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LEV32` reader - Level 32"] -pub type LEV32_R = crate::BitReader; +pub type LEV32_R = crate::BitReader; #[doc = "Field `LEV33` reader - Level 33"] -pub type LEV33_R = crate::BitReader; +pub type LEV33_R = crate::BitReader; #[doc = "Field `LEV34` reader - Level 34"] -pub type LEV34_R = crate::BitReader; +pub type LEV34_R = crate::BitReader; #[doc = "Field `LEV35` reader - Level 35"] -pub type LEV35_R = crate::BitReader; +pub type LEV35_R = crate::BitReader; #[doc = "Field `LEV36` reader - Level 36"] -pub type LEV36_R = crate::BitReader; +pub type LEV36_R = crate::BitReader; #[doc = "Field `LEV37` reader - Level 37"] -pub type LEV37_R = crate::BitReader; +pub type LEV37_R = crate::BitReader; #[doc = "Field `LEV38` reader - Level 38"] -pub type LEV38_R = crate::BitReader; +pub type LEV38_R = crate::BitReader; #[doc = "Field `LEV39` reader - Level 39"] -pub type LEV39_R = crate::BitReader; +pub type LEV39_R = crate::BitReader; #[doc = "Field `LEV40` reader - Level 40"] -pub type LEV40_R = crate::BitReader; +pub type LEV40_R = crate::BitReader; #[doc = "Field `LEV41` reader - Level 41"] -pub type LEV41_R = crate::BitReader; +pub type LEV41_R = crate::BitReader; #[doc = "Field `LEV42` reader - Level 42"] -pub type LEV42_R = crate::BitReader; +pub type LEV42_R = crate::BitReader; #[doc = "Field `LEV43` reader - Level 43"] -pub type LEV43_R = crate::BitReader; +pub type LEV43_R = crate::BitReader; #[doc = "Field `LEV44` reader - Level 44"] -pub type LEV44_R = crate::BitReader; +pub type LEV44_R = crate::BitReader; #[doc = "Field `LEV45` reader - Level 45"] -pub type LEV45_R = crate::BitReader; +pub type LEV45_R = crate::BitReader; #[doc = "Field `LEV46` reader - Level 46"] -pub type LEV46_R = crate::BitReader; +pub type LEV46_R = crate::BitReader; #[doc = "Field `LEV47` reader - Level 47"] -pub type LEV47_R = crate::BitReader; +pub type LEV47_R = crate::BitReader; #[doc = "Field `LEV48` reader - Level 48"] -pub type LEV48_R = crate::BitReader; +pub type LEV48_R = crate::BitReader; #[doc = "Field `LEV49` reader - Level 49"] -pub type LEV49_R = crate::BitReader; +pub type LEV49_R = crate::BitReader; #[doc = "Field `LEV50` reader - Level 50"] -pub type LEV50_R = crate::BitReader; +pub type LEV50_R = crate::BitReader; #[doc = "Field `LEV51` reader - Level 51"] -pub type LEV51_R = crate::BitReader; +pub type LEV51_R = crate::BitReader; #[doc = "Field `LEV52` reader - Level 52"] -pub type LEV52_R = crate::BitReader; +pub type LEV52_R = crate::BitReader; #[doc = "Field `LEV53` reader - Level 53"] -pub type LEV53_R = crate::BitReader; +pub type LEV53_R = crate::BitReader; #[doc = "Field `LEV54` reader - Level 54"] -pub type LEV54_R = crate::BitReader; +pub type LEV54_R = crate::BitReader; #[doc = "Field `LEV55` reader - Level 55"] -pub type LEV55_R = crate::BitReader; +pub type LEV55_R = crate::BitReader; #[doc = "Field `LEV56` reader - Level 56"] -pub type LEV56_R = crate::BitReader; +pub type LEV56_R = crate::BitReader; #[doc = "Field `LEV57` reader - Level 57"] -pub type LEV57_R = crate::BitReader; +pub type LEV57_R = crate::BitReader; impl R { #[doc = "Bit 0 - Level 32"] #[inline(always)] @@ -197,12 +184,47 @@ impl R { LEV57_R::new(((self.bits >> 25) & 1) != 0) } } -#[doc = "GPIO Pin Level 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplev1](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPLEV1") + .field("lev32", &format_args!("{}", self.lev32().bit())) + .field("lev33", &format_args!("{}", self.lev33().bit())) + .field("lev34", &format_args!("{}", self.lev34().bit())) + .field("lev35", &format_args!("{}", self.lev35().bit())) + .field("lev36", &format_args!("{}", self.lev36().bit())) + .field("lev37", &format_args!("{}", self.lev37().bit())) + .field("lev38", &format_args!("{}", self.lev38().bit())) + .field("lev39", &format_args!("{}", self.lev39().bit())) + .field("lev40", &format_args!("{}", self.lev40().bit())) + .field("lev41", &format_args!("{}", self.lev41().bit())) + .field("lev42", &format_args!("{}", self.lev42().bit())) + .field("lev43", &format_args!("{}", self.lev43().bit())) + .field("lev44", &format_args!("{}", self.lev44().bit())) + .field("lev45", &format_args!("{}", self.lev45().bit())) + .field("lev46", &format_args!("{}", self.lev46().bit())) + .field("lev47", &format_args!("{}", self.lev47().bit())) + .field("lev48", &format_args!("{}", self.lev48().bit())) + .field("lev49", &format_args!("{}", self.lev49().bit())) + .field("lev50", &format_args!("{}", self.lev50().bit())) + .field("lev51", &format_args!("{}", self.lev51().bit())) + .field("lev52", &format_args!("{}", self.lev52().bit())) + .field("lev53", &format_args!("{}", self.lev53().bit())) + .field("lev54", &format_args!("{}", self.lev54().bit())) + .field("lev55", &format_args!("{}", self.lev55().bit())) + .field("lev56", &format_args!("{}", self.lev56().bit())) + .field("lev57", &format_args!("{}", self.lev57().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "GPIO Pin Level 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplev1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPLEV1_SPEC; impl crate::RegisterSpec for GPLEV1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gplev1::R](R) reader structure"] -impl crate::Readable for GPLEV1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gplev1::R`](R) reader structure"] +impl crate::Readable for GPLEV1_SPEC {} diff --git a/crates/bcm2711-lpa/src/gpio/gpren0.rs b/crates/bcm2711-lpa/src/gpio/gpren0.rs index af4f16c..f4dfc2e 100644 --- a/crates/bcm2711-lpa/src/gpio/gpren0.rs +++ b/crates/bcm2711-lpa/src/gpio/gpren0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPREN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPREN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `REN0` reader - Rising edge enabled 0"] -pub type REN0_R = crate::BitReader; +pub type REN0_R = crate::BitReader; #[doc = "Field `REN0` writer - Rising edge enabled 0"] -pub type REN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN1` reader - Rising edge enabled 1"] -pub type REN1_R = crate::BitReader; +pub type REN1_R = crate::BitReader; #[doc = "Field `REN1` writer - Rising edge enabled 1"] -pub type REN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN2` reader - Rising edge enabled 2"] -pub type REN2_R = crate::BitReader; +pub type REN2_R = crate::BitReader; #[doc = "Field `REN2` writer - Rising edge enabled 2"] -pub type REN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN3` reader - Rising edge enabled 3"] -pub type REN3_R = crate::BitReader; +pub type REN3_R = crate::BitReader; #[doc = "Field `REN3` writer - Rising edge enabled 3"] -pub type REN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN4` reader - Rising edge enabled 4"] -pub type REN4_R = crate::BitReader; +pub type REN4_R = crate::BitReader; #[doc = "Field `REN4` writer - Rising edge enabled 4"] -pub type REN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN5` reader - Rising edge enabled 5"] -pub type REN5_R = crate::BitReader; +pub type REN5_R = crate::BitReader; #[doc = "Field `REN5` writer - Rising edge enabled 5"] -pub type REN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN6` reader - Rising edge enabled 6"] -pub type REN6_R = crate::BitReader; +pub type REN6_R = crate::BitReader; #[doc = "Field `REN6` writer - Rising edge enabled 6"] -pub type REN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN7` reader - Rising edge enabled 7"] -pub type REN7_R = crate::BitReader; +pub type REN7_R = crate::BitReader; #[doc = "Field `REN7` writer - Rising edge enabled 7"] -pub type REN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN8` reader - Rising edge enabled 8"] -pub type REN8_R = crate::BitReader; +pub type REN8_R = crate::BitReader; #[doc = "Field `REN8` writer - Rising edge enabled 8"] -pub type REN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN9` reader - Rising edge enabled 9"] -pub type REN9_R = crate::BitReader; +pub type REN9_R = crate::BitReader; #[doc = "Field `REN9` writer - Rising edge enabled 9"] -pub type REN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN10` reader - Rising edge enabled 10"] -pub type REN10_R = crate::BitReader; +pub type REN10_R = crate::BitReader; #[doc = "Field `REN10` writer - Rising edge enabled 10"] -pub type REN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN11` reader - Rising edge enabled 11"] -pub type REN11_R = crate::BitReader; +pub type REN11_R = crate::BitReader; #[doc = "Field `REN11` writer - Rising edge enabled 11"] -pub type REN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN12` reader - Rising edge enabled 12"] -pub type REN12_R = crate::BitReader; +pub type REN12_R = crate::BitReader; #[doc = "Field `REN12` writer - Rising edge enabled 12"] -pub type REN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN13` reader - Rising edge enabled 13"] -pub type REN13_R = crate::BitReader; +pub type REN13_R = crate::BitReader; #[doc = "Field `REN13` writer - Rising edge enabled 13"] -pub type REN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN14` reader - Rising edge enabled 14"] -pub type REN14_R = crate::BitReader; +pub type REN14_R = crate::BitReader; #[doc = "Field `REN14` writer - Rising edge enabled 14"] -pub type REN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN15` reader - Rising edge enabled 15"] -pub type REN15_R = crate::BitReader; +pub type REN15_R = crate::BitReader; #[doc = "Field `REN15` writer - Rising edge enabled 15"] -pub type REN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN16` reader - Rising edge enabled 16"] -pub type REN16_R = crate::BitReader; +pub type REN16_R = crate::BitReader; #[doc = "Field `REN16` writer - Rising edge enabled 16"] -pub type REN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN17` reader - Rising edge enabled 17"] -pub type REN17_R = crate::BitReader; +pub type REN17_R = crate::BitReader; #[doc = "Field `REN17` writer - Rising edge enabled 17"] -pub type REN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN18` reader - Rising edge enabled 18"] -pub type REN18_R = crate::BitReader; +pub type REN18_R = crate::BitReader; #[doc = "Field `REN18` writer - Rising edge enabled 18"] -pub type REN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN19` reader - Rising edge enabled 19"] -pub type REN19_R = crate::BitReader; +pub type REN19_R = crate::BitReader; #[doc = "Field `REN19` writer - Rising edge enabled 19"] -pub type REN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN20` reader - Rising edge enabled 20"] -pub type REN20_R = crate::BitReader; +pub type REN20_R = crate::BitReader; #[doc = "Field `REN20` writer - Rising edge enabled 20"] -pub type REN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN21` reader - Rising edge enabled 21"] -pub type REN21_R = crate::BitReader; +pub type REN21_R = crate::BitReader; #[doc = "Field `REN21` writer - Rising edge enabled 21"] -pub type REN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN22` reader - Rising edge enabled 22"] -pub type REN22_R = crate::BitReader; +pub type REN22_R = crate::BitReader; #[doc = "Field `REN22` writer - Rising edge enabled 22"] -pub type REN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN23` reader - Rising edge enabled 23"] -pub type REN23_R = crate::BitReader; +pub type REN23_R = crate::BitReader; #[doc = "Field `REN23` writer - Rising edge enabled 23"] -pub type REN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN24` reader - Rising edge enabled 24"] -pub type REN24_R = crate::BitReader; +pub type REN24_R = crate::BitReader; #[doc = "Field `REN24` writer - Rising edge enabled 24"] -pub type REN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN25` reader - Rising edge enabled 25"] -pub type REN25_R = crate::BitReader; +pub type REN25_R = crate::BitReader; #[doc = "Field `REN25` writer - Rising edge enabled 25"] -pub type REN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN26` reader - Rising edge enabled 26"] -pub type REN26_R = crate::BitReader; +pub type REN26_R = crate::BitReader; #[doc = "Field `REN26` writer - Rising edge enabled 26"] -pub type REN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN27` reader - Rising edge enabled 27"] -pub type REN27_R = crate::BitReader; +pub type REN27_R = crate::BitReader; #[doc = "Field `REN27` writer - Rising edge enabled 27"] -pub type REN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN28` reader - Rising edge enabled 28"] -pub type REN28_R = crate::BitReader; +pub type REN28_R = crate::BitReader; #[doc = "Field `REN28` writer - Rising edge enabled 28"] -pub type REN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN29` reader - Rising edge enabled 29"] -pub type REN29_R = crate::BitReader; +pub type REN29_R = crate::BitReader; #[doc = "Field `REN29` writer - Rising edge enabled 29"] -pub type REN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN30` reader - Rising edge enabled 30"] -pub type REN30_R = crate::BitReader; +pub type REN30_R = crate::BitReader; #[doc = "Field `REN30` writer - Rising edge enabled 30"] -pub type REN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN31` reader - Rising edge enabled 31"] -pub type REN31_R = crate::BitReader; +pub type REN31_R = crate::BitReader; #[doc = "Field `REN31` writer - Rising edge enabled 31"] -pub type REN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Rising edge enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { REN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPREN0") + .field("ren0", &format_args!("{}", self.ren0().bit())) + .field("ren1", &format_args!("{}", self.ren1().bit())) + .field("ren2", &format_args!("{}", self.ren2().bit())) + .field("ren3", &format_args!("{}", self.ren3().bit())) + .field("ren4", &format_args!("{}", self.ren4().bit())) + .field("ren5", &format_args!("{}", self.ren5().bit())) + .field("ren6", &format_args!("{}", self.ren6().bit())) + .field("ren7", &format_args!("{}", self.ren7().bit())) + .field("ren8", &format_args!("{}", self.ren8().bit())) + .field("ren9", &format_args!("{}", self.ren9().bit())) + .field("ren10", &format_args!("{}", self.ren10().bit())) + .field("ren11", &format_args!("{}", self.ren11().bit())) + .field("ren12", &format_args!("{}", self.ren12().bit())) + .field("ren13", &format_args!("{}", self.ren13().bit())) + .field("ren14", &format_args!("{}", self.ren14().bit())) + .field("ren15", &format_args!("{}", self.ren15().bit())) + .field("ren16", &format_args!("{}", self.ren16().bit())) + .field("ren17", &format_args!("{}", self.ren17().bit())) + .field("ren18", &format_args!("{}", self.ren18().bit())) + .field("ren19", &format_args!("{}", self.ren19().bit())) + .field("ren20", &format_args!("{}", self.ren20().bit())) + .field("ren21", &format_args!("{}", self.ren21().bit())) + .field("ren22", &format_args!("{}", self.ren22().bit())) + .field("ren23", &format_args!("{}", self.ren23().bit())) + .field("ren24", &format_args!("{}", self.ren24().bit())) + .field("ren25", &format_args!("{}", self.ren25().bit())) + .field("ren26", &format_args!("{}", self.ren26().bit())) + .field("ren27", &format_args!("{}", self.ren27().bit())) + .field("ren28", &format_args!("{}", self.ren28().bit())) + .field("ren29", &format_args!("{}", self.ren29().bit())) + .field("ren30", &format_args!("{}", self.ren30().bit())) + .field("ren31", &format_args!("{}", self.ren31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Rising edge enabled 0"] #[inline(always)] #[must_use] - pub fn ren0(&mut self) -> REN0_W<0> { + pub fn ren0(&mut self) -> REN0_W { REN0_W::new(self) } #[doc = "Bit 1 - Rising edge enabled 1"] #[inline(always)] #[must_use] - pub fn ren1(&mut self) -> REN1_W<1> { + pub fn ren1(&mut self) -> REN1_W { REN1_W::new(self) } #[doc = "Bit 2 - Rising edge enabled 2"] #[inline(always)] #[must_use] - pub fn ren2(&mut self) -> REN2_W<2> { + pub fn ren2(&mut self) -> REN2_W { REN2_W::new(self) } #[doc = "Bit 3 - Rising edge enabled 3"] #[inline(always)] #[must_use] - pub fn ren3(&mut self) -> REN3_W<3> { + pub fn ren3(&mut self) -> REN3_W { REN3_W::new(self) } #[doc = "Bit 4 - Rising edge enabled 4"] #[inline(always)] #[must_use] - pub fn ren4(&mut self) -> REN4_W<4> { + pub fn ren4(&mut self) -> REN4_W { REN4_W::new(self) } #[doc = "Bit 5 - Rising edge enabled 5"] #[inline(always)] #[must_use] - pub fn ren5(&mut self) -> REN5_W<5> { + pub fn ren5(&mut self) -> REN5_W { REN5_W::new(self) } #[doc = "Bit 6 - Rising edge enabled 6"] #[inline(always)] #[must_use] - pub fn ren6(&mut self) -> REN6_W<6> { + pub fn ren6(&mut self) -> REN6_W { REN6_W::new(self) } #[doc = "Bit 7 - Rising edge enabled 7"] #[inline(always)] #[must_use] - pub fn ren7(&mut self) -> REN7_W<7> { + pub fn ren7(&mut self) -> REN7_W { REN7_W::new(self) } #[doc = "Bit 8 - Rising edge enabled 8"] #[inline(always)] #[must_use] - pub fn ren8(&mut self) -> REN8_W<8> { + pub fn ren8(&mut self) -> REN8_W { REN8_W::new(self) } #[doc = "Bit 9 - Rising edge enabled 9"] #[inline(always)] #[must_use] - pub fn ren9(&mut self) -> REN9_W<9> { + pub fn ren9(&mut self) -> REN9_W { REN9_W::new(self) } #[doc = "Bit 10 - Rising edge enabled 10"] #[inline(always)] #[must_use] - pub fn ren10(&mut self) -> REN10_W<10> { + pub fn ren10(&mut self) -> REN10_W { REN10_W::new(self) } #[doc = "Bit 11 - Rising edge enabled 11"] #[inline(always)] #[must_use] - pub fn ren11(&mut self) -> REN11_W<11> { + pub fn ren11(&mut self) -> REN11_W { REN11_W::new(self) } #[doc = "Bit 12 - Rising edge enabled 12"] #[inline(always)] #[must_use] - pub fn ren12(&mut self) -> REN12_W<12> { + pub fn ren12(&mut self) -> REN12_W { REN12_W::new(self) } #[doc = "Bit 13 - Rising edge enabled 13"] #[inline(always)] #[must_use] - pub fn ren13(&mut self) -> REN13_W<13> { + pub fn ren13(&mut self) -> REN13_W { REN13_W::new(self) } #[doc = "Bit 14 - Rising edge enabled 14"] #[inline(always)] #[must_use] - pub fn ren14(&mut self) -> REN14_W<14> { + pub fn ren14(&mut self) -> REN14_W { REN14_W::new(self) } #[doc = "Bit 15 - Rising edge enabled 15"] #[inline(always)] #[must_use] - pub fn ren15(&mut self) -> REN15_W<15> { + pub fn ren15(&mut self) -> REN15_W { REN15_W::new(self) } #[doc = "Bit 16 - Rising edge enabled 16"] #[inline(always)] #[must_use] - pub fn ren16(&mut self) -> REN16_W<16> { + pub fn ren16(&mut self) -> REN16_W { REN16_W::new(self) } #[doc = "Bit 17 - Rising edge enabled 17"] #[inline(always)] #[must_use] - pub fn ren17(&mut self) -> REN17_W<17> { + pub fn ren17(&mut self) -> REN17_W { REN17_W::new(self) } #[doc = "Bit 18 - Rising edge enabled 18"] #[inline(always)] #[must_use] - pub fn ren18(&mut self) -> REN18_W<18> { + pub fn ren18(&mut self) -> REN18_W { REN18_W::new(self) } #[doc = "Bit 19 - Rising edge enabled 19"] #[inline(always)] #[must_use] - pub fn ren19(&mut self) -> REN19_W<19> { + pub fn ren19(&mut self) -> REN19_W { REN19_W::new(self) } #[doc = "Bit 20 - Rising edge enabled 20"] #[inline(always)] #[must_use] - pub fn ren20(&mut self) -> REN20_W<20> { + pub fn ren20(&mut self) -> REN20_W { REN20_W::new(self) } #[doc = "Bit 21 - Rising edge enabled 21"] #[inline(always)] #[must_use] - pub fn ren21(&mut self) -> REN21_W<21> { + pub fn ren21(&mut self) -> REN21_W { REN21_W::new(self) } #[doc = "Bit 22 - Rising edge enabled 22"] #[inline(always)] #[must_use] - pub fn ren22(&mut self) -> REN22_W<22> { + pub fn ren22(&mut self) -> REN22_W { REN22_W::new(self) } #[doc = "Bit 23 - Rising edge enabled 23"] #[inline(always)] #[must_use] - pub fn ren23(&mut self) -> REN23_W<23> { + pub fn ren23(&mut self) -> REN23_W { REN23_W::new(self) } #[doc = "Bit 24 - Rising edge enabled 24"] #[inline(always)] #[must_use] - pub fn ren24(&mut self) -> REN24_W<24> { + pub fn ren24(&mut self) -> REN24_W { REN24_W::new(self) } #[doc = "Bit 25 - Rising edge enabled 25"] #[inline(always)] #[must_use] - pub fn ren25(&mut self) -> REN25_W<25> { + pub fn ren25(&mut self) -> REN25_W { REN25_W::new(self) } #[doc = "Bit 26 - Rising edge enabled 26"] #[inline(always)] #[must_use] - pub fn ren26(&mut self) -> REN26_W<26> { + pub fn ren26(&mut self) -> REN26_W { REN26_W::new(self) } #[doc = "Bit 27 - Rising edge enabled 27"] #[inline(always)] #[must_use] - pub fn ren27(&mut self) -> REN27_W<27> { + pub fn ren27(&mut self) -> REN27_W { REN27_W::new(self) } #[doc = "Bit 28 - Rising edge enabled 28"] #[inline(always)] #[must_use] - pub fn ren28(&mut self) -> REN28_W<28> { + pub fn ren28(&mut self) -> REN28_W { REN28_W::new(self) } #[doc = "Bit 29 - Rising edge enabled 29"] #[inline(always)] #[must_use] - pub fn ren29(&mut self) -> REN29_W<29> { + pub fn ren29(&mut self) -> REN29_W { REN29_W::new(self) } #[doc = "Bit 30 - Rising edge enabled 30"] #[inline(always)] #[must_use] - pub fn ren30(&mut self) -> REN30_W<30> { + pub fn ren30(&mut self) -> REN30_W { REN30_W::new(self) } #[doc = "Bit 31 - Rising edge enabled 31"] #[inline(always)] #[must_use] - pub fn ren31(&mut self) -> REN31_W<31> { + pub fn ren31(&mut self) -> REN31_W { REN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Rising Edge Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpren0](index.html) module"] +#[doc = "GPIO Pin Rising Edge Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpren0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpren0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPREN0_SPEC; impl crate::RegisterSpec for GPREN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpren0::R](R) reader structure"] -impl crate::Readable for GPREN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpren0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpren0::R`](R) reader structure"] +impl crate::Readable for GPREN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpren0::W`](W) writer structure"] impl crate::Writable for GPREN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpren1.rs b/crates/bcm2711-lpa/src/gpio/gpren1.rs index e5b0650..9710e89 100644 --- a/crates/bcm2711-lpa/src/gpio/gpren1.rs +++ b/crates/bcm2711-lpa/src/gpio/gpren1.rs @@ -1,143 +1,111 @@ #[doc = "Register `GPREN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPREN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `REN32` reader - Rising edge enabled 32"] -pub type REN32_R = crate::BitReader; +pub type REN32_R = crate::BitReader; #[doc = "Field `REN32` writer - Rising edge enabled 32"] -pub type REN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN33` reader - Rising edge enabled 33"] -pub type REN33_R = crate::BitReader; +pub type REN33_R = crate::BitReader; #[doc = "Field `REN33` writer - Rising edge enabled 33"] -pub type REN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN34` reader - Rising edge enabled 34"] -pub type REN34_R = crate::BitReader; +pub type REN34_R = crate::BitReader; #[doc = "Field `REN34` writer - Rising edge enabled 34"] -pub type REN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN35` reader - Rising edge enabled 35"] -pub type REN35_R = crate::BitReader; +pub type REN35_R = crate::BitReader; #[doc = "Field `REN35` writer - Rising edge enabled 35"] -pub type REN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN36` reader - Rising edge enabled 36"] -pub type REN36_R = crate::BitReader; +pub type REN36_R = crate::BitReader; #[doc = "Field `REN36` writer - Rising edge enabled 36"] -pub type REN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN37` reader - Rising edge enabled 37"] -pub type REN37_R = crate::BitReader; +pub type REN37_R = crate::BitReader; #[doc = "Field `REN37` writer - Rising edge enabled 37"] -pub type REN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN38` reader - Rising edge enabled 38"] -pub type REN38_R = crate::BitReader; +pub type REN38_R = crate::BitReader; #[doc = "Field `REN38` writer - Rising edge enabled 38"] -pub type REN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN39` reader - Rising edge enabled 39"] -pub type REN39_R = crate::BitReader; +pub type REN39_R = crate::BitReader; #[doc = "Field `REN39` writer - Rising edge enabled 39"] -pub type REN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN40` reader - Rising edge enabled 40"] -pub type REN40_R = crate::BitReader; +pub type REN40_R = crate::BitReader; #[doc = "Field `REN40` writer - Rising edge enabled 40"] -pub type REN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN41` reader - Rising edge enabled 41"] -pub type REN41_R = crate::BitReader; +pub type REN41_R = crate::BitReader; #[doc = "Field `REN41` writer - Rising edge enabled 41"] -pub type REN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN42` reader - Rising edge enabled 42"] -pub type REN42_R = crate::BitReader; +pub type REN42_R = crate::BitReader; #[doc = "Field `REN42` writer - Rising edge enabled 42"] -pub type REN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN43` reader - Rising edge enabled 43"] -pub type REN43_R = crate::BitReader; +pub type REN43_R = crate::BitReader; #[doc = "Field `REN43` writer - Rising edge enabled 43"] -pub type REN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN44` reader - Rising edge enabled 44"] -pub type REN44_R = crate::BitReader; +pub type REN44_R = crate::BitReader; #[doc = "Field `REN44` writer - Rising edge enabled 44"] -pub type REN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN45` reader - Rising edge enabled 45"] -pub type REN45_R = crate::BitReader; +pub type REN45_R = crate::BitReader; #[doc = "Field `REN45` writer - Rising edge enabled 45"] -pub type REN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN46` reader - Rising edge enabled 46"] -pub type REN46_R = crate::BitReader; +pub type REN46_R = crate::BitReader; #[doc = "Field `REN46` writer - Rising edge enabled 46"] -pub type REN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN47` reader - Rising edge enabled 47"] -pub type REN47_R = crate::BitReader; +pub type REN47_R = crate::BitReader; #[doc = "Field `REN47` writer - Rising edge enabled 47"] -pub type REN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN48` reader - Rising edge enabled 48"] -pub type REN48_R = crate::BitReader; +pub type REN48_R = crate::BitReader; #[doc = "Field `REN48` writer - Rising edge enabled 48"] -pub type REN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN49` reader - Rising edge enabled 49"] -pub type REN49_R = crate::BitReader; +pub type REN49_R = crate::BitReader; #[doc = "Field `REN49` writer - Rising edge enabled 49"] -pub type REN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN50` reader - Rising edge enabled 50"] -pub type REN50_R = crate::BitReader; +pub type REN50_R = crate::BitReader; #[doc = "Field `REN50` writer - Rising edge enabled 50"] -pub type REN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN51` reader - Rising edge enabled 51"] -pub type REN51_R = crate::BitReader; +pub type REN51_R = crate::BitReader; #[doc = "Field `REN51` writer - Rising edge enabled 51"] -pub type REN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN52` reader - Rising edge enabled 52"] -pub type REN52_R = crate::BitReader; +pub type REN52_R = crate::BitReader; #[doc = "Field `REN52` writer - Rising edge enabled 52"] -pub type REN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN53` reader - Rising edge enabled 53"] -pub type REN53_R = crate::BitReader; +pub type REN53_R = crate::BitReader; #[doc = "Field `REN53` writer - Rising edge enabled 53"] -pub type REN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN54` reader - Rising edge enabled 54"] -pub type REN54_R = crate::BitReader; +pub type REN54_R = crate::BitReader; #[doc = "Field `REN54` writer - Rising edge enabled 54"] -pub type REN54_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN54_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN55` reader - Rising edge enabled 55"] -pub type REN55_R = crate::BitReader; +pub type REN55_R = crate::BitReader; #[doc = "Field `REN55` writer - Rising edge enabled 55"] -pub type REN55_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN55_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN56` reader - Rising edge enabled 56"] -pub type REN56_R = crate::BitReader; +pub type REN56_R = crate::BitReader; #[doc = "Field `REN56` writer - Rising edge enabled 56"] -pub type REN56_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN57` reader - Rising edge enabled 57"] -pub type REN57_R = crate::BitReader; +pub type REN57_R = crate::BitReader; #[doc = "Field `REN57` writer - Rising edge enabled 57"] -pub type REN57_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Rising edge enabled 32"] #[inline(always)] @@ -270,182 +238,220 @@ impl R { REN57_R::new(((self.bits >> 25) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPREN1") + .field("ren32", &format_args!("{}", self.ren32().bit())) + .field("ren33", &format_args!("{}", self.ren33().bit())) + .field("ren34", &format_args!("{}", self.ren34().bit())) + .field("ren35", &format_args!("{}", self.ren35().bit())) + .field("ren36", &format_args!("{}", self.ren36().bit())) + .field("ren37", &format_args!("{}", self.ren37().bit())) + .field("ren38", &format_args!("{}", self.ren38().bit())) + .field("ren39", &format_args!("{}", self.ren39().bit())) + .field("ren40", &format_args!("{}", self.ren40().bit())) + .field("ren41", &format_args!("{}", self.ren41().bit())) + .field("ren42", &format_args!("{}", self.ren42().bit())) + .field("ren43", &format_args!("{}", self.ren43().bit())) + .field("ren44", &format_args!("{}", self.ren44().bit())) + .field("ren45", &format_args!("{}", self.ren45().bit())) + .field("ren46", &format_args!("{}", self.ren46().bit())) + .field("ren47", &format_args!("{}", self.ren47().bit())) + .field("ren48", &format_args!("{}", self.ren48().bit())) + .field("ren49", &format_args!("{}", self.ren49().bit())) + .field("ren50", &format_args!("{}", self.ren50().bit())) + .field("ren51", &format_args!("{}", self.ren51().bit())) + .field("ren52", &format_args!("{}", self.ren52().bit())) + .field("ren53", &format_args!("{}", self.ren53().bit())) + .field("ren54", &format_args!("{}", self.ren54().bit())) + .field("ren55", &format_args!("{}", self.ren55().bit())) + .field("ren56", &format_args!("{}", self.ren56().bit())) + .field("ren57", &format_args!("{}", self.ren57().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Rising edge enabled 32"] #[inline(always)] #[must_use] - pub fn ren32(&mut self) -> REN32_W<0> { + pub fn ren32(&mut self) -> REN32_W { REN32_W::new(self) } #[doc = "Bit 1 - Rising edge enabled 33"] #[inline(always)] #[must_use] - pub fn ren33(&mut self) -> REN33_W<1> { + pub fn ren33(&mut self) -> REN33_W { REN33_W::new(self) } #[doc = "Bit 2 - Rising edge enabled 34"] #[inline(always)] #[must_use] - pub fn ren34(&mut self) -> REN34_W<2> { + pub fn ren34(&mut self) -> REN34_W { REN34_W::new(self) } #[doc = "Bit 3 - Rising edge enabled 35"] #[inline(always)] #[must_use] - pub fn ren35(&mut self) -> REN35_W<3> { + pub fn ren35(&mut self) -> REN35_W { REN35_W::new(self) } #[doc = "Bit 4 - Rising edge enabled 36"] #[inline(always)] #[must_use] - pub fn ren36(&mut self) -> REN36_W<4> { + pub fn ren36(&mut self) -> REN36_W { REN36_W::new(self) } #[doc = "Bit 5 - Rising edge enabled 37"] #[inline(always)] #[must_use] - pub fn ren37(&mut self) -> REN37_W<5> { + pub fn ren37(&mut self) -> REN37_W { REN37_W::new(self) } #[doc = "Bit 6 - Rising edge enabled 38"] #[inline(always)] #[must_use] - pub fn ren38(&mut self) -> REN38_W<6> { + pub fn ren38(&mut self) -> REN38_W { REN38_W::new(self) } #[doc = "Bit 7 - Rising edge enabled 39"] #[inline(always)] #[must_use] - pub fn ren39(&mut self) -> REN39_W<7> { + pub fn ren39(&mut self) -> REN39_W { REN39_W::new(self) } #[doc = "Bit 8 - Rising edge enabled 40"] #[inline(always)] #[must_use] - pub fn ren40(&mut self) -> REN40_W<8> { + pub fn ren40(&mut self) -> REN40_W { REN40_W::new(self) } #[doc = "Bit 9 - Rising edge enabled 41"] #[inline(always)] #[must_use] - pub fn ren41(&mut self) -> REN41_W<9> { + pub fn ren41(&mut self) -> REN41_W { REN41_W::new(self) } #[doc = "Bit 10 - Rising edge enabled 42"] #[inline(always)] #[must_use] - pub fn ren42(&mut self) -> REN42_W<10> { + pub fn ren42(&mut self) -> REN42_W { REN42_W::new(self) } #[doc = "Bit 11 - Rising edge enabled 43"] #[inline(always)] #[must_use] - pub fn ren43(&mut self) -> REN43_W<11> { + pub fn ren43(&mut self) -> REN43_W { REN43_W::new(self) } #[doc = "Bit 12 - Rising edge enabled 44"] #[inline(always)] #[must_use] - pub fn ren44(&mut self) -> REN44_W<12> { + pub fn ren44(&mut self) -> REN44_W { REN44_W::new(self) } #[doc = "Bit 13 - Rising edge enabled 45"] #[inline(always)] #[must_use] - pub fn ren45(&mut self) -> REN45_W<13> { + pub fn ren45(&mut self) -> REN45_W { REN45_W::new(self) } #[doc = "Bit 14 - Rising edge enabled 46"] #[inline(always)] #[must_use] - pub fn ren46(&mut self) -> REN46_W<14> { + pub fn ren46(&mut self) -> REN46_W { REN46_W::new(self) } #[doc = "Bit 15 - Rising edge enabled 47"] #[inline(always)] #[must_use] - pub fn ren47(&mut self) -> REN47_W<15> { + pub fn ren47(&mut self) -> REN47_W { REN47_W::new(self) } #[doc = "Bit 16 - Rising edge enabled 48"] #[inline(always)] #[must_use] - pub fn ren48(&mut self) -> REN48_W<16> { + pub fn ren48(&mut self) -> REN48_W { REN48_W::new(self) } #[doc = "Bit 17 - Rising edge enabled 49"] #[inline(always)] #[must_use] - pub fn ren49(&mut self) -> REN49_W<17> { + pub fn ren49(&mut self) -> REN49_W { REN49_W::new(self) } #[doc = "Bit 18 - Rising edge enabled 50"] #[inline(always)] #[must_use] - pub fn ren50(&mut self) -> REN50_W<18> { + pub fn ren50(&mut self) -> REN50_W { REN50_W::new(self) } #[doc = "Bit 19 - Rising edge enabled 51"] #[inline(always)] #[must_use] - pub fn ren51(&mut self) -> REN51_W<19> { + pub fn ren51(&mut self) -> REN51_W { REN51_W::new(self) } #[doc = "Bit 20 - Rising edge enabled 52"] #[inline(always)] #[must_use] - pub fn ren52(&mut self) -> REN52_W<20> { + pub fn ren52(&mut self) -> REN52_W { REN52_W::new(self) } #[doc = "Bit 21 - Rising edge enabled 53"] #[inline(always)] #[must_use] - pub fn ren53(&mut self) -> REN53_W<21> { + pub fn ren53(&mut self) -> REN53_W { REN53_W::new(self) } #[doc = "Bit 22 - Rising edge enabled 54"] #[inline(always)] #[must_use] - pub fn ren54(&mut self) -> REN54_W<22> { + pub fn ren54(&mut self) -> REN54_W { REN54_W::new(self) } #[doc = "Bit 23 - Rising edge enabled 55"] #[inline(always)] #[must_use] - pub fn ren55(&mut self) -> REN55_W<23> { + pub fn ren55(&mut self) -> REN55_W { REN55_W::new(self) } #[doc = "Bit 24 - Rising edge enabled 56"] #[inline(always)] #[must_use] - pub fn ren56(&mut self) -> REN56_W<24> { + pub fn ren56(&mut self) -> REN56_W { REN56_W::new(self) } #[doc = "Bit 25 - Rising edge enabled 57"] #[inline(always)] #[must_use] - pub fn ren57(&mut self) -> REN57_W<25> { + pub fn ren57(&mut self) -> REN57_W { REN57_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Rising Edge Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpren1](index.html) module"] +#[doc = "GPIO Pin Rising Edge Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpren1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpren1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPREN1_SPEC; impl crate::RegisterSpec for GPREN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpren1::R](R) reader structure"] -impl crate::Readable for GPREN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpren1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpren1::R`](R) reader structure"] +impl crate::Readable for GPREN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpren1::W`](W) writer structure"] impl crate::Writable for GPREN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/gpio/gpset0.rs b/crates/bcm2711-lpa/src/gpio/gpset0.rs index 49e2659..513781b 100644 --- a/crates/bcm2711-lpa/src/gpio/gpset0.rs +++ b/crates/bcm2711-lpa/src/gpio/gpset0.rs @@ -1,296 +1,285 @@ #[doc = "Register `GPSET0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SET0` writer - Set 0"] -pub type SET0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET1` writer - Set 1"] -pub type SET1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET2` writer - Set 2"] -pub type SET2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET3` writer - Set 3"] -pub type SET3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET4` writer - Set 4"] -pub type SET4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET5` writer - Set 5"] -pub type SET5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET6` writer - Set 6"] -pub type SET6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET7` writer - Set 7"] -pub type SET7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET7_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET8` writer - Set 8"] -pub type SET8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET8_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET9` writer - Set 9"] -pub type SET9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET9_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET10` writer - Set 10"] -pub type SET10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET10_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET11` writer - Set 11"] -pub type SET11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET11_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET12` writer - Set 12"] -pub type SET12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET12_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET13` writer - Set 13"] -pub type SET13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET13_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET14` writer - Set 14"] -pub type SET14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET14_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET15` writer - Set 15"] -pub type SET15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET15_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET16` writer - Set 16"] -pub type SET16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET16_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET17` writer - Set 17"] -pub type SET17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET17_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET18` writer - Set 18"] -pub type SET18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET18_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET19` writer - Set 19"] -pub type SET19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET19_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET20` writer - Set 20"] -pub type SET20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET20_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET21` writer - Set 21"] -pub type SET21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET21_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET22` writer - Set 22"] -pub type SET22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET22_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET23` writer - Set 23"] -pub type SET23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET23_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET24` writer - Set 24"] -pub type SET24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET24_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET25` writer - Set 25"] -pub type SET25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET25_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET26` writer - Set 26"] -pub type SET26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET26_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET27` writer - Set 27"] -pub type SET27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET27_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET28` writer - Set 28"] -pub type SET28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET28_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET29` writer - Set 29"] -pub type SET29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET29_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET30` writer - Set 30"] -pub type SET30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET30_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET31` writer - Set 31"] -pub type SET31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET31_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - Set 0"] #[inline(always)] #[must_use] - pub fn set0(&mut self) -> SET0_W<0> { + pub fn set0(&mut self) -> SET0_W { SET0_W::new(self) } #[doc = "Bit 1 - Set 1"] #[inline(always)] #[must_use] - pub fn set1(&mut self) -> SET1_W<1> { + pub fn set1(&mut self) -> SET1_W { SET1_W::new(self) } #[doc = "Bit 2 - Set 2"] #[inline(always)] #[must_use] - pub fn set2(&mut self) -> SET2_W<2> { + pub fn set2(&mut self) -> SET2_W { SET2_W::new(self) } #[doc = "Bit 3 - Set 3"] #[inline(always)] #[must_use] - pub fn set3(&mut self) -> SET3_W<3> { + pub fn set3(&mut self) -> SET3_W { SET3_W::new(self) } #[doc = "Bit 4 - Set 4"] #[inline(always)] #[must_use] - pub fn set4(&mut self) -> SET4_W<4> { + pub fn set4(&mut self) -> SET4_W { SET4_W::new(self) } #[doc = "Bit 5 - Set 5"] #[inline(always)] #[must_use] - pub fn set5(&mut self) -> SET5_W<5> { + pub fn set5(&mut self) -> SET5_W { SET5_W::new(self) } #[doc = "Bit 6 - Set 6"] #[inline(always)] #[must_use] - pub fn set6(&mut self) -> SET6_W<6> { + pub fn set6(&mut self) -> SET6_W { SET6_W::new(self) } #[doc = "Bit 7 - Set 7"] #[inline(always)] #[must_use] - pub fn set7(&mut self) -> SET7_W<7> { + pub fn set7(&mut self) -> SET7_W { SET7_W::new(self) } #[doc = "Bit 8 - Set 8"] #[inline(always)] #[must_use] - pub fn set8(&mut self) -> SET8_W<8> { + pub fn set8(&mut self) -> SET8_W { SET8_W::new(self) } #[doc = "Bit 9 - Set 9"] #[inline(always)] #[must_use] - pub fn set9(&mut self) -> SET9_W<9> { + pub fn set9(&mut self) -> SET9_W { SET9_W::new(self) } #[doc = "Bit 10 - Set 10"] #[inline(always)] #[must_use] - pub fn set10(&mut self) -> SET10_W<10> { + pub fn set10(&mut self) -> SET10_W { SET10_W::new(self) } #[doc = "Bit 11 - Set 11"] #[inline(always)] #[must_use] - pub fn set11(&mut self) -> SET11_W<11> { + pub fn set11(&mut self) -> SET11_W { SET11_W::new(self) } #[doc = "Bit 12 - Set 12"] #[inline(always)] #[must_use] - pub fn set12(&mut self) -> SET12_W<12> { + pub fn set12(&mut self) -> SET12_W { SET12_W::new(self) } #[doc = "Bit 13 - Set 13"] #[inline(always)] #[must_use] - pub fn set13(&mut self) -> SET13_W<13> { + pub fn set13(&mut self) -> SET13_W { SET13_W::new(self) } #[doc = "Bit 14 - Set 14"] #[inline(always)] #[must_use] - pub fn set14(&mut self) -> SET14_W<14> { + pub fn set14(&mut self) -> SET14_W { SET14_W::new(self) } #[doc = "Bit 15 - Set 15"] #[inline(always)] #[must_use] - pub fn set15(&mut self) -> SET15_W<15> { + pub fn set15(&mut self) -> SET15_W { SET15_W::new(self) } #[doc = "Bit 16 - Set 16"] #[inline(always)] #[must_use] - pub fn set16(&mut self) -> SET16_W<16> { + pub fn set16(&mut self) -> SET16_W { SET16_W::new(self) } #[doc = "Bit 17 - Set 17"] #[inline(always)] #[must_use] - pub fn set17(&mut self) -> SET17_W<17> { + pub fn set17(&mut self) -> SET17_W { SET17_W::new(self) } #[doc = "Bit 18 - Set 18"] #[inline(always)] #[must_use] - pub fn set18(&mut self) -> SET18_W<18> { + pub fn set18(&mut self) -> SET18_W { SET18_W::new(self) } #[doc = "Bit 19 - Set 19"] #[inline(always)] #[must_use] - pub fn set19(&mut self) -> SET19_W<19> { + pub fn set19(&mut self) -> SET19_W { SET19_W::new(self) } #[doc = "Bit 20 - Set 20"] #[inline(always)] #[must_use] - pub fn set20(&mut self) -> SET20_W<20> { + pub fn set20(&mut self) -> SET20_W { SET20_W::new(self) } #[doc = "Bit 21 - Set 21"] #[inline(always)] #[must_use] - pub fn set21(&mut self) -> SET21_W<21> { + pub fn set21(&mut self) -> SET21_W { SET21_W::new(self) } #[doc = "Bit 22 - Set 22"] #[inline(always)] #[must_use] - pub fn set22(&mut self) -> SET22_W<22> { + pub fn set22(&mut self) -> SET22_W { SET22_W::new(self) } #[doc = "Bit 23 - Set 23"] #[inline(always)] #[must_use] - pub fn set23(&mut self) -> SET23_W<23> { + pub fn set23(&mut self) -> SET23_W { SET23_W::new(self) } #[doc = "Bit 24 - Set 24"] #[inline(always)] #[must_use] - pub fn set24(&mut self) -> SET24_W<24> { + pub fn set24(&mut self) -> SET24_W { SET24_W::new(self) } #[doc = "Bit 25 - Set 25"] #[inline(always)] #[must_use] - pub fn set25(&mut self) -> SET25_W<25> { + pub fn set25(&mut self) -> SET25_W { SET25_W::new(self) } #[doc = "Bit 26 - Set 26"] #[inline(always)] #[must_use] - pub fn set26(&mut self) -> SET26_W<26> { + pub fn set26(&mut self) -> SET26_W { SET26_W::new(self) } #[doc = "Bit 27 - Set 27"] #[inline(always)] #[must_use] - pub fn set27(&mut self) -> SET27_W<27> { + pub fn set27(&mut self) -> SET27_W { SET27_W::new(self) } #[doc = "Bit 28 - Set 28"] #[inline(always)] #[must_use] - pub fn set28(&mut self) -> SET28_W<28> { + pub fn set28(&mut self) -> SET28_W { SET28_W::new(self) } #[doc = "Bit 29 - Set 29"] #[inline(always)] #[must_use] - pub fn set29(&mut self) -> SET29_W<29> { + pub fn set29(&mut self) -> SET29_W { SET29_W::new(self) } #[doc = "Bit 30 - Set 30"] #[inline(always)] #[must_use] - pub fn set30(&mut self) -> SET30_W<30> { + pub fn set30(&mut self) -> SET30_W { SET30_W::new(self) } #[doc = "Bit 31 - Set 31"] #[inline(always)] #[must_use] - pub fn set31(&mut self) -> SET31_W<31> { + pub fn set31(&mut self) -> SET31_W { SET31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Output Set 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpset0](index.html) module"] +#[doc = "GPIO Pin Output Set 0\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpset0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPSET0_SPEC; impl crate::RegisterSpec for GPSET0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpset0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpset0::W`](W) writer structure"] impl crate::Writable for GPSET0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/gpio/gpset1.rs b/crates/bcm2711-lpa/src/gpio/gpset1.rs index 8e7b482..74ceb5b 100644 --- a/crates/bcm2711-lpa/src/gpio/gpset1.rs +++ b/crates/bcm2711-lpa/src/gpio/gpset1.rs @@ -1,248 +1,237 @@ #[doc = "Register `GPSET1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SET32` writer - Set 32"] -pub type SET32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET32_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET33` writer - Set 33"] -pub type SET33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET33_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET34` writer - Set 34"] -pub type SET34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET34_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET35` writer - Set 35"] -pub type SET35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET35_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET36` writer - Set 36"] -pub type SET36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET36_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET37` writer - Set 37"] -pub type SET37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET37_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET38` writer - Set 38"] -pub type SET38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET38_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET39` writer - Set 39"] -pub type SET39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET39_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET40` writer - Set 40"] -pub type SET40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET40_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET41` writer - Set 41"] -pub type SET41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET41_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET42` writer - Set 42"] -pub type SET42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET42_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET43` writer - Set 43"] -pub type SET43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET43_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET44` writer - Set 44"] -pub type SET44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET44_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET45` writer - Set 45"] -pub type SET45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET45_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET46` writer - Set 46"] -pub type SET46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET46_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET47` writer - Set 47"] -pub type SET47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET47_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET48` writer - Set 48"] -pub type SET48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET48_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET49` writer - Set 49"] -pub type SET49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET49_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET50` writer - Set 50"] -pub type SET50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET50_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET51` writer - Set 51"] -pub type SET51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET51_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET52` writer - Set 52"] -pub type SET52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET52_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET53` writer - Set 53"] -pub type SET53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET53_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET54` writer - Set 54"] -pub type SET54_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET54_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET55` writer - Set 55"] -pub type SET55_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET55_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET56` writer - Set 56"] -pub type SET56_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET56_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET57` writer - Set 57"] -pub type SET57_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET57_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - Set 32"] #[inline(always)] #[must_use] - pub fn set32(&mut self) -> SET32_W<0> { + pub fn set32(&mut self) -> SET32_W { SET32_W::new(self) } #[doc = "Bit 1 - Set 33"] #[inline(always)] #[must_use] - pub fn set33(&mut self) -> SET33_W<1> { + pub fn set33(&mut self) -> SET33_W { SET33_W::new(self) } #[doc = "Bit 2 - Set 34"] #[inline(always)] #[must_use] - pub fn set34(&mut self) -> SET34_W<2> { + pub fn set34(&mut self) -> SET34_W { SET34_W::new(self) } #[doc = "Bit 3 - Set 35"] #[inline(always)] #[must_use] - pub fn set35(&mut self) -> SET35_W<3> { + pub fn set35(&mut self) -> SET35_W { SET35_W::new(self) } #[doc = "Bit 4 - Set 36"] #[inline(always)] #[must_use] - pub fn set36(&mut self) -> SET36_W<4> { + pub fn set36(&mut self) -> SET36_W { SET36_W::new(self) } #[doc = "Bit 5 - Set 37"] #[inline(always)] #[must_use] - pub fn set37(&mut self) -> SET37_W<5> { + pub fn set37(&mut self) -> SET37_W { SET37_W::new(self) } #[doc = "Bit 6 - Set 38"] #[inline(always)] #[must_use] - pub fn set38(&mut self) -> SET38_W<6> { + pub fn set38(&mut self) -> SET38_W { SET38_W::new(self) } #[doc = "Bit 7 - Set 39"] #[inline(always)] #[must_use] - pub fn set39(&mut self) -> SET39_W<7> { + pub fn set39(&mut self) -> SET39_W { SET39_W::new(self) } #[doc = "Bit 8 - Set 40"] #[inline(always)] #[must_use] - pub fn set40(&mut self) -> SET40_W<8> { + pub fn set40(&mut self) -> SET40_W { SET40_W::new(self) } #[doc = "Bit 9 - Set 41"] #[inline(always)] #[must_use] - pub fn set41(&mut self) -> SET41_W<9> { + pub fn set41(&mut self) -> SET41_W { SET41_W::new(self) } #[doc = "Bit 10 - Set 42"] #[inline(always)] #[must_use] - pub fn set42(&mut self) -> SET42_W<10> { + pub fn set42(&mut self) -> SET42_W { SET42_W::new(self) } #[doc = "Bit 11 - Set 43"] #[inline(always)] #[must_use] - pub fn set43(&mut self) -> SET43_W<11> { + pub fn set43(&mut self) -> SET43_W { SET43_W::new(self) } #[doc = "Bit 12 - Set 44"] #[inline(always)] #[must_use] - pub fn set44(&mut self) -> SET44_W<12> { + pub fn set44(&mut self) -> SET44_W { SET44_W::new(self) } #[doc = "Bit 13 - Set 45"] #[inline(always)] #[must_use] - pub fn set45(&mut self) -> SET45_W<13> { + pub fn set45(&mut self) -> SET45_W { SET45_W::new(self) } #[doc = "Bit 14 - Set 46"] #[inline(always)] #[must_use] - pub fn set46(&mut self) -> SET46_W<14> { + pub fn set46(&mut self) -> SET46_W { SET46_W::new(self) } #[doc = "Bit 15 - Set 47"] #[inline(always)] #[must_use] - pub fn set47(&mut self) -> SET47_W<15> { + pub fn set47(&mut self) -> SET47_W { SET47_W::new(self) } #[doc = "Bit 16 - Set 48"] #[inline(always)] #[must_use] - pub fn set48(&mut self) -> SET48_W<16> { + pub fn set48(&mut self) -> SET48_W { SET48_W::new(self) } #[doc = "Bit 17 - Set 49"] #[inline(always)] #[must_use] - pub fn set49(&mut self) -> SET49_W<17> { + pub fn set49(&mut self) -> SET49_W { SET49_W::new(self) } #[doc = "Bit 18 - Set 50"] #[inline(always)] #[must_use] - pub fn set50(&mut self) -> SET50_W<18> { + pub fn set50(&mut self) -> SET50_W { SET50_W::new(self) } #[doc = "Bit 19 - Set 51"] #[inline(always)] #[must_use] - pub fn set51(&mut self) -> SET51_W<19> { + pub fn set51(&mut self) -> SET51_W { SET51_W::new(self) } #[doc = "Bit 20 - Set 52"] #[inline(always)] #[must_use] - pub fn set52(&mut self) -> SET52_W<20> { + pub fn set52(&mut self) -> SET52_W { SET52_W::new(self) } #[doc = "Bit 21 - Set 53"] #[inline(always)] #[must_use] - pub fn set53(&mut self) -> SET53_W<21> { + pub fn set53(&mut self) -> SET53_W { SET53_W::new(self) } #[doc = "Bit 22 - Set 54"] #[inline(always)] #[must_use] - pub fn set54(&mut self) -> SET54_W<22> { + pub fn set54(&mut self) -> SET54_W { SET54_W::new(self) } #[doc = "Bit 23 - Set 55"] #[inline(always)] #[must_use] - pub fn set55(&mut self) -> SET55_W<23> { + pub fn set55(&mut self) -> SET55_W { SET55_W::new(self) } #[doc = "Bit 24 - Set 56"] #[inline(always)] #[must_use] - pub fn set56(&mut self) -> SET56_W<24> { + pub fn set56(&mut self) -> SET56_W { SET56_W::new(self) } #[doc = "Bit 25 - Set 57"] #[inline(always)] #[must_use] - pub fn set57(&mut self) -> SET57_W<25> { + pub fn set57(&mut self) -> SET57_W { SET57_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Output Set 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpset1](index.html) module"] +#[doc = "GPIO Pin Output Set 1\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpset1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPSET1_SPEC; impl crate::RegisterSpec for GPSET1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpset1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpset1::W`](W) writer structure"] impl crate::Writable for GPSET1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x03ff_ffff; } diff --git a/crates/bcm2711-lpa/src/lib.rs b/crates/bcm2711-lpa/src/lib.rs index 8f40b81..a0b3c89 100644 --- a/crates/bcm2711-lpa/src/lib.rs +++ b/crates/bcm2711-lpa/src/lib.rs @@ -1,5 +1,5 @@ -#![doc = "Peripheral access API for BCM2711_LPA microcontrollers (generated using svd2rust v0.28.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] -svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.28.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![doc = "Peripheral access API for BCM2711_LPA microcontrollers (generated using svd2rust v0.30.2 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.30.2/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -8,7 +8,8 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] +#![deny(private_bounds)] +#![deny(private_interfaces)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] @@ -41,6 +42,24 @@ impl VCMAILBOX { pub const fn ptr() -> *const vcmailbox::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for VCMAILBOX { type Target = vcmailbox::RegisterBlock; @@ -69,6 +88,24 @@ impl CM_PCM { pub const fn ptr() -> *const cm_pcm::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for CM_PCM { type Target = cm_pcm::RegisterBlock; @@ -97,6 +134,24 @@ impl CM_PWM { pub const fn ptr() -> *const cm_pcm::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for CM_PWM { type Target = cm_pcm::RegisterBlock; @@ -125,6 +180,24 @@ impl GPIO { pub const fn ptr() -> *const gpio::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for GPIO { type Target = gpio::RegisterBlock; @@ -153,6 +226,24 @@ impl SYSTMR { pub const fn ptr() -> *const systmr::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SYSTMR { type Target = systmr::RegisterBlock; @@ -181,6 +272,24 @@ impl UART0 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART0 { type Target = uart0::RegisterBlock; @@ -209,6 +318,24 @@ impl UART2 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART2 { type Target = uart0::RegisterBlock; @@ -237,6 +364,24 @@ impl UART3 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART3 { type Target = uart0::RegisterBlock; @@ -265,6 +410,24 @@ impl UART4 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART4 { type Target = uart0::RegisterBlock; @@ -293,6 +456,24 @@ impl UART5 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART5 { type Target = uart0::RegisterBlock; @@ -321,6 +502,24 @@ impl SPI0 { pub const fn ptr() -> *const spi0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI0 { type Target = spi0::RegisterBlock; @@ -349,6 +548,24 @@ impl SPI3 { pub const fn ptr() -> *const spi0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI3 { type Target = spi0::RegisterBlock; @@ -377,6 +594,24 @@ impl SPI4 { pub const fn ptr() -> *const spi0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI4 { type Target = spi0::RegisterBlock; @@ -405,6 +640,24 @@ impl SPI5 { pub const fn ptr() -> *const spi0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI5 { type Target = spi0::RegisterBlock; @@ -433,6 +686,24 @@ impl SPI6 { pub const fn ptr() -> *const spi0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI6 { type Target = spi0::RegisterBlock; @@ -461,6 +732,24 @@ impl PACTL { pub const fn ptr() -> *const pactl::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PACTL { type Target = pactl::RegisterBlock; @@ -489,6 +778,24 @@ impl BSC0 { pub const fn ptr() -> *const bsc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for BSC0 { type Target = bsc0::RegisterBlock; @@ -517,6 +824,24 @@ impl BSC1 { pub const fn ptr() -> *const bsc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for BSC1 { type Target = bsc0::RegisterBlock; @@ -545,6 +870,24 @@ impl BSC3 { pub const fn ptr() -> *const bsc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for BSC3 { type Target = bsc0::RegisterBlock; @@ -573,6 +916,24 @@ impl BSC4 { pub const fn ptr() -> *const bsc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for BSC4 { type Target = bsc0::RegisterBlock; @@ -601,6 +962,24 @@ impl BSC5 { pub const fn ptr() -> *const bsc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for BSC5 { type Target = bsc0::RegisterBlock; @@ -629,6 +1008,24 @@ impl BSC6 { pub const fn ptr() -> *const bsc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for BSC6 { type Target = bsc0::RegisterBlock; @@ -657,6 +1054,24 @@ impl PWM0 { pub const fn ptr() -> *const pwm0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PWM0 { type Target = pwm0::RegisterBlock; @@ -685,6 +1100,24 @@ impl PWM1 { pub const fn ptr() -> *const pwm0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PWM1 { type Target = pwm0::RegisterBlock; @@ -713,6 +1146,24 @@ impl AUX { pub const fn ptr() -> *const aux::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for AUX { type Target = aux::RegisterBlock; @@ -741,6 +1192,24 @@ impl UART1 { pub const fn ptr() -> *const uart1::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART1 { type Target = uart1::RegisterBlock; @@ -769,6 +1238,24 @@ impl SPI1 { pub const fn ptr() -> *const spi1::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI1 { type Target = spi1::RegisterBlock; @@ -797,6 +1284,24 @@ impl SPI2 { pub const fn ptr() -> *const spi1::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI2 { type Target = spi1::RegisterBlock; @@ -825,6 +1330,24 @@ impl LIC { pub const fn ptr() -> *const lic::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for LIC { type Target = lic::RegisterBlock; @@ -853,6 +1376,24 @@ impl GIC_DIST { pub const fn ptr() -> *const gic_dist::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for GIC_DIST { type Target = gic_dist::RegisterBlock; @@ -881,6 +1422,24 @@ impl GIC_CPU { pub const fn ptr() -> *const gic_cpu::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for GIC_CPU { type Target = gic_cpu::RegisterBlock; @@ -909,6 +1468,24 @@ impl USB_OTG_GLOBAL { pub const fn ptr() -> *const usb_otg_global::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USB_OTG_GLOBAL { type Target = usb_otg_global::RegisterBlock; @@ -937,6 +1514,24 @@ impl USB_OTG_HOST { pub const fn ptr() -> *const usb_otg_host::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USB_OTG_HOST { type Target = usb_otg_host::RegisterBlock; @@ -965,6 +1560,24 @@ impl USB_OTG_DEVICE { pub const fn ptr() -> *const usb_otg_device::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USB_OTG_DEVICE { type Target = usb_otg_device::RegisterBlock; @@ -993,6 +1606,24 @@ impl USB_OTG_PWRCLK { pub const fn ptr() -> *const usb_otg_pwrclk::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USB_OTG_PWRCLK { type Target = usb_otg_pwrclk::RegisterBlock; @@ -1021,6 +1652,24 @@ impl EMMC { pub const fn ptr() -> *const emmc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for EMMC { type Target = emmc::RegisterBlock; diff --git a/crates/bcm2711-lpa/src/lic.rs b/crates/bcm2711-lpa/src/lic.rs index bc15cd4..36d6423 100644 --- a/crates/bcm2711-lpa/src/lic.rs +++ b/crates/bcm2711-lpa/src/lic.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { _reserved0: [u8; 0x0200], #[doc = "0x200 - Basic pending info"] @@ -23,43 +24,53 @@ pub struct RegisterBlock { #[doc = "0x224 - Disable basic interrupts"] pub disable_basic: DISABLE_BASIC, } -#[doc = "BASIC_PENDING (r) register accessor: an alias for `Reg`"] +#[doc = "BASIC_PENDING (r) register accessor: Basic pending info\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`basic_pending::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@basic_pending`] +module"] pub type BASIC_PENDING = crate::Reg; #[doc = "Basic pending info"] pub mod basic_pending; -#[doc = "PENDING_1 (r) register accessor: an alias for `Reg`"] +#[doc = "PENDING_1 (r) register accessor: Pending state for interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_1`] +module"] pub type PENDING_1 = crate::Reg; #[doc = "Pending state for interrupts 1 - 31"] pub mod pending_1; -#[doc = "PENDING_2 (r) register accessor: an alias for `Reg`"] +#[doc = "PENDING_2 (r) register accessor: Pending state for interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_2`] +module"] pub type PENDING_2 = crate::Reg; #[doc = "Pending state for interrupts 32 - 63"] pub mod pending_2; -#[doc = "FIQ_CONTROL (rw) register accessor: an alias for `Reg`"] +#[doc = "FIQ_CONTROL (rw) register accessor: FIQ control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fiq_control::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fiq_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fiq_control`] +module"] pub type FIQ_CONTROL = crate::Reg; #[doc = "FIQ control"] pub mod fiq_control; -#[doc = "ENABLE_1 (rw) register accessor: an alias for `Reg`"] +#[doc = "ENABLE_1 (rw) register accessor: Enable interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_1`] +module"] pub type ENABLE_1 = crate::Reg; #[doc = "Enable interrupts 1 - 31"] pub mod enable_1; -#[doc = "ENABLE_2 (rw) register accessor: an alias for `Reg`"] +#[doc = "ENABLE_2 (rw) register accessor: Enable interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_2`] +module"] pub type ENABLE_2 = crate::Reg; #[doc = "Enable interrupts 32 - 63"] pub mod enable_2; -#[doc = "ENABLE_BASIC (rw) register accessor: an alias for `Reg`"] +#[doc = "ENABLE_BASIC (rw) register accessor: Enable basic interrupts\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_basic::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_basic::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_basic`] +module"] pub type ENABLE_BASIC = crate::Reg; #[doc = "Enable basic interrupts"] pub mod enable_basic; -#[doc = "DISABLE_1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DISABLE_1 (rw) register accessor: Disable interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@disable_1`] +module"] pub type DISABLE_1 = crate::Reg; #[doc = "Disable interrupts 1 - 31"] pub mod disable_1; -#[doc = "DISABLE_2 (rw) register accessor: an alias for `Reg`"] +#[doc = "DISABLE_2 (rw) register accessor: Disable interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@disable_2`] +module"] pub type DISABLE_2 = crate::Reg; #[doc = "Disable interrupts 32 - 63"] pub mod disable_2; -#[doc = "DISABLE_BASIC (rw) register accessor: an alias for `Reg`"] +#[doc = "DISABLE_BASIC (rw) register accessor: Disable basic interrupts\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_basic::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_basic::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@disable_basic`] +module"] pub type DISABLE_BASIC = crate::Reg; #[doc = "Disable basic interrupts"] pub mod disable_basic; diff --git a/crates/bcm2711-lpa/src/lic/basic_pending.rs b/crates/bcm2711-lpa/src/lic/basic_pending.rs index 10dd271..52b9471 100644 --- a/crates/bcm2711-lpa/src/lic/basic_pending.rs +++ b/crates/bcm2711-lpa/src/lic/basic_pending.rs @@ -1,60 +1,47 @@ #[doc = "Register `BASIC_PENDING` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `PENDING_1` reader - One or more bits are set in PENDING_1 (ignores 7, 9, 10, 18, 19)"] -pub type PENDING_1_R = crate::BitReader; +pub type PENDING_1_R = crate::BitReader; #[doc = "Field `PENDING_2` reader - One or more bits are set in PENDING_2 (ignores 53 - 57, 62)"] -pub type PENDING_2_R = crate::BitReader; +pub type PENDING_2_R = crate::BitReader; #[doc = "Field `INT7` reader - Interrupt 7"] -pub type INT7_R = crate::BitReader; +pub type INT7_R = crate::BitReader; #[doc = "Field `INT9` reader - Interrupt 9"] -pub type INT9_R = crate::BitReader; +pub type INT9_R = crate::BitReader; #[doc = "Field `INT10` reader - Interrupt 10"] -pub type INT10_R = crate::BitReader; +pub type INT10_R = crate::BitReader; #[doc = "Field `INT18` reader - Interrupt 18"] -pub type INT18_R = crate::BitReader; +pub type INT18_R = crate::BitReader; #[doc = "Field `INT19` reader - Interrupt 19"] -pub type INT19_R = crate::BitReader; +pub type INT19_R = crate::BitReader; #[doc = "Field `INT53` reader - Interrupt 53"] -pub type INT53_R = crate::BitReader; +pub type INT53_R = crate::BitReader; #[doc = "Field `INT54` reader - Interrupt 54"] -pub type INT54_R = crate::BitReader; +pub type INT54_R = crate::BitReader; #[doc = "Field `INT55` reader - Interrupt 55"] -pub type INT55_R = crate::BitReader; +pub type INT55_R = crate::BitReader; #[doc = "Field `INT56` reader - Interrupt 56"] -pub type INT56_R = crate::BitReader; +pub type INT56_R = crate::BitReader; #[doc = "Field `INT57` reader - Interrupt 57"] -pub type INT57_R = crate::BitReader; +pub type INT57_R = crate::BitReader; #[doc = "Field `INT62` reader - Interrupt 62"] -pub type INT62_R = crate::BitReader; +pub type INT62_R = crate::BitReader; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -162,15 +149,51 @@ impl R { INT62_R::new(((self.bits >> 20) & 1) != 0) } } -#[doc = "Basic pending info\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [basic_pending](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BASIC_PENDING") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .field("pending_1", &format_args!("{}", self.pending_1().bit())) + .field("pending_2", &format_args!("{}", self.pending_2().bit())) + .field("int7", &format_args!("{}", self.int7().bit())) + .field("int9", &format_args!("{}", self.int9().bit())) + .field("int10", &format_args!("{}", self.int10().bit())) + .field("int18", &format_args!("{}", self.int18().bit())) + .field("int19", &format_args!("{}", self.int19().bit())) + .field("int53", &format_args!("{}", self.int53().bit())) + .field("int54", &format_args!("{}", self.int54().bit())) + .field("int55", &format_args!("{}", self.int55().bit())) + .field("int56", &format_args!("{}", self.int56().bit())) + .field("int57", &format_args!("{}", self.int57().bit())) + .field("int62", &format_args!("{}", self.int62().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Basic pending info\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`basic_pending::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BASIC_PENDING_SPEC; impl crate::RegisterSpec for BASIC_PENDING_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [basic_pending::R](R) reader structure"] -impl crate::Readable for BASIC_PENDING_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`basic_pending::R`](R) reader structure"] +impl crate::Readable for BASIC_PENDING_SPEC {} #[doc = "`reset()` method sets BASIC_PENDING to value 0"] impl crate::Resettable for BASIC_PENDING_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/lic/disable_1.rs b/crates/bcm2711-lpa/src/lic/disable_1.rs index e575ff9..65d348a 100644 --- a/crates/bcm2711-lpa/src/lic/disable_1.rs +++ b/crates/bcm2711-lpa/src/lic/disable_1.rs @@ -1,167 +1,135 @@ #[doc = "Register `DISABLE_1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DISABLE_1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT0` reader - Interrupt 0"] -pub type INT0_R = crate::BitReader; +pub type INT0_R = crate::BitReader; #[doc = "Field `INT0` writer - Interrupt 0"] -pub type INT0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT1` reader - Interrupt 1"] -pub type INT1_R = crate::BitReader; +pub type INT1_R = crate::BitReader; #[doc = "Field `INT1` writer - Interrupt 1"] -pub type INT1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT2` reader - Interrupt 2"] -pub type INT2_R = crate::BitReader; +pub type INT2_R = crate::BitReader; #[doc = "Field `INT2` writer - Interrupt 2"] -pub type INT2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT3` reader - Interrupt 3"] -pub type INT3_R = crate::BitReader; +pub type INT3_R = crate::BitReader; #[doc = "Field `INT3` writer - Interrupt 3"] -pub type INT3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT4` reader - Interrupt 4"] -pub type INT4_R = crate::BitReader; +pub type INT4_R = crate::BitReader; #[doc = "Field `INT4` writer - Interrupt 4"] -pub type INT4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT5` reader - Interrupt 5"] -pub type INT5_R = crate::BitReader; +pub type INT5_R = crate::BitReader; #[doc = "Field `INT5` writer - Interrupt 5"] -pub type INT5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT6` reader - Interrupt 6"] -pub type INT6_R = crate::BitReader; +pub type INT6_R = crate::BitReader; #[doc = "Field `INT6` writer - Interrupt 6"] -pub type INT6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT7` reader - Interrupt 7"] -pub type INT7_R = crate::BitReader; +pub type INT7_R = crate::BitReader; #[doc = "Field `INT7` writer - Interrupt 7"] -pub type INT7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT8` reader - Interrupt 8"] -pub type INT8_R = crate::BitReader; +pub type INT8_R = crate::BitReader; #[doc = "Field `INT8` writer - Interrupt 8"] -pub type INT8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT9` reader - Interrupt 9"] -pub type INT9_R = crate::BitReader; +pub type INT9_R = crate::BitReader; #[doc = "Field `INT9` writer - Interrupt 9"] -pub type INT9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT9_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT10` reader - Interrupt 10"] -pub type INT10_R = crate::BitReader; +pub type INT10_R = crate::BitReader; #[doc = "Field `INT10` writer - Interrupt 10"] -pub type INT10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT11` reader - Interrupt 11"] -pub type INT11_R = crate::BitReader; +pub type INT11_R = crate::BitReader; #[doc = "Field `INT11` writer - Interrupt 11"] -pub type INT11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT12` reader - Interrupt 12"] -pub type INT12_R = crate::BitReader; +pub type INT12_R = crate::BitReader; #[doc = "Field `INT12` writer - Interrupt 12"] -pub type INT12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT13` reader - Interrupt 13"] -pub type INT13_R = crate::BitReader; +pub type INT13_R = crate::BitReader; #[doc = "Field `INT13` writer - Interrupt 13"] -pub type INT13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT14` reader - Interrupt 14"] -pub type INT14_R = crate::BitReader; +pub type INT14_R = crate::BitReader; #[doc = "Field `INT14` writer - Interrupt 14"] -pub type INT14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT15` reader - Interrupt 15"] -pub type INT15_R = crate::BitReader; +pub type INT15_R = crate::BitReader; #[doc = "Field `INT15` writer - Interrupt 15"] -pub type INT15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT16` reader - Interrupt 16"] -pub type INT16_R = crate::BitReader; +pub type INT16_R = crate::BitReader; #[doc = "Field `INT16` writer - Interrupt 16"] -pub type INT16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT16_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT17` reader - Interrupt 17"] -pub type INT17_R = crate::BitReader; +pub type INT17_R = crate::BitReader; #[doc = "Field `INT17` writer - Interrupt 17"] -pub type INT17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT17_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT18` reader - Interrupt 18"] -pub type INT18_R = crate::BitReader; +pub type INT18_R = crate::BitReader; #[doc = "Field `INT18` writer - Interrupt 18"] -pub type INT18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT18_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT19` reader - Interrupt 19"] -pub type INT19_R = crate::BitReader; +pub type INT19_R = crate::BitReader; #[doc = "Field `INT19` writer - Interrupt 19"] -pub type INT19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT19_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT20` reader - Interrupt 20"] -pub type INT20_R = crate::BitReader; +pub type INT20_R = crate::BitReader; #[doc = "Field `INT20` writer - Interrupt 20"] -pub type INT20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT20_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT21` reader - Interrupt 21"] -pub type INT21_R = crate::BitReader; +pub type INT21_R = crate::BitReader; #[doc = "Field `INT21` writer - Interrupt 21"] -pub type INT21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT21_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT22` reader - Interrupt 22"] -pub type INT22_R = crate::BitReader; +pub type INT22_R = crate::BitReader; #[doc = "Field `INT22` writer - Interrupt 22"] -pub type INT22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT22_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT23` reader - Interrupt 23"] -pub type INT23_R = crate::BitReader; +pub type INT23_R = crate::BitReader; #[doc = "Field `INT23` writer - Interrupt 23"] -pub type INT23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT23_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT24` reader - Interrupt 24"] -pub type INT24_R = crate::BitReader; +pub type INT24_R = crate::BitReader; #[doc = "Field `INT24` writer - Interrupt 24"] -pub type INT24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT24_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT25` reader - Interrupt 25"] -pub type INT25_R = crate::BitReader; +pub type INT25_R = crate::BitReader; #[doc = "Field `INT25` writer - Interrupt 25"] -pub type INT25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT25_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT26` reader - Interrupt 26"] -pub type INT26_R = crate::BitReader; +pub type INT26_R = crate::BitReader; #[doc = "Field `INT26` writer - Interrupt 26"] -pub type INT26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT26_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT27` reader - Interrupt 27"] -pub type INT27_R = crate::BitReader; +pub type INT27_R = crate::BitReader; #[doc = "Field `INT27` writer - Interrupt 27"] -pub type INT27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT27_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT28` reader - Interrupt 28"] -pub type INT28_R = crate::BitReader; +pub type INT28_R = crate::BitReader; #[doc = "Field `INT28` writer - Interrupt 28"] -pub type INT28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT28_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT29` reader - Interrupt 29"] -pub type INT29_R = crate::BitReader; +pub type INT29_R = crate::BitReader; #[doc = "Field `INT29` writer - Interrupt 29"] -pub type INT29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT29_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT30` reader - Interrupt 30"] -pub type INT30_R = crate::BitReader; +pub type INT30_R = crate::BitReader; #[doc = "Field `INT30` writer - Interrupt 30"] -pub type INT30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT30_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT31` reader - Interrupt 31"] -pub type INT31_R = crate::BitReader; +pub type INT31_R = crate::BitReader; #[doc = "Field `INT31` writer - Interrupt 31"] -pub type INT31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type INT31_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DISABLE_1") + .field("int0", &format_args!("{}", self.int0().bit())) + .field("int1", &format_args!("{}", self.int1().bit())) + .field("int2", &format_args!("{}", self.int2().bit())) + .field("int3", &format_args!("{}", self.int3().bit())) + .field("int4", &format_args!("{}", self.int4().bit())) + .field("int5", &format_args!("{}", self.int5().bit())) + .field("int6", &format_args!("{}", self.int6().bit())) + .field("int7", &format_args!("{}", self.int7().bit())) + .field("int8", &format_args!("{}", self.int8().bit())) + .field("int9", &format_args!("{}", self.int9().bit())) + .field("int10", &format_args!("{}", self.int10().bit())) + .field("int11", &format_args!("{}", self.int11().bit())) + .field("int12", &format_args!("{}", self.int12().bit())) + .field("int13", &format_args!("{}", self.int13().bit())) + .field("int14", &format_args!("{}", self.int14().bit())) + .field("int15", &format_args!("{}", self.int15().bit())) + .field("int16", &format_args!("{}", self.int16().bit())) + .field("int17", &format_args!("{}", self.int17().bit())) + .field("int18", &format_args!("{}", self.int18().bit())) + .field("int19", &format_args!("{}", self.int19().bit())) + .field("int20", &format_args!("{}", self.int20().bit())) + .field("int21", &format_args!("{}", self.int21().bit())) + .field("int22", &format_args!("{}", self.int22().bit())) + .field("int23", &format_args!("{}", self.int23().bit())) + .field("int24", &format_args!("{}", self.int24().bit())) + .field("int25", &format_args!("{}", self.int25().bit())) + .field("int26", &format_args!("{}", self.int26().bit())) + .field("int27", &format_args!("{}", self.int27().bit())) + .field("int28", &format_args!("{}", self.int28().bit())) + .field("int29", &format_args!("{}", self.int29().bit())) + .field("int30", &format_args!("{}", self.int30().bit())) + .field("int31", &format_args!("{}", self.int31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] #[must_use] - pub fn int0(&mut self) -> INT0_W<0> { + pub fn int0(&mut self) -> INT0_W { INT0_W::new(self) } #[doc = "Bit 1 - Interrupt 1"] #[inline(always)] #[must_use] - pub fn int1(&mut self) -> INT1_W<1> { + pub fn int1(&mut self) -> INT1_W { INT1_W::new(self) } #[doc = "Bit 2 - Interrupt 2"] #[inline(always)] #[must_use] - pub fn int2(&mut self) -> INT2_W<2> { + pub fn int2(&mut self) -> INT2_W { INT2_W::new(self) } #[doc = "Bit 3 - Interrupt 3"] #[inline(always)] #[must_use] - pub fn int3(&mut self) -> INT3_W<3> { + pub fn int3(&mut self) -> INT3_W { INT3_W::new(self) } #[doc = "Bit 4 - Interrupt 4"] #[inline(always)] #[must_use] - pub fn int4(&mut self) -> INT4_W<4> { + pub fn int4(&mut self) -> INT4_W { INT4_W::new(self) } #[doc = "Bit 5 - Interrupt 5"] #[inline(always)] #[must_use] - pub fn int5(&mut self) -> INT5_W<5> { + pub fn int5(&mut self) -> INT5_W { INT5_W::new(self) } #[doc = "Bit 6 - Interrupt 6"] #[inline(always)] #[must_use] - pub fn int6(&mut self) -> INT6_W<6> { + pub fn int6(&mut self) -> INT6_W { INT6_W::new(self) } #[doc = "Bit 7 - Interrupt 7"] #[inline(always)] #[must_use] - pub fn int7(&mut self) -> INT7_W<7> { + pub fn int7(&mut self) -> INT7_W { INT7_W::new(self) } #[doc = "Bit 8 - Interrupt 8"] #[inline(always)] #[must_use] - pub fn int8(&mut self) -> INT8_W<8> { + pub fn int8(&mut self) -> INT8_W { INT8_W::new(self) } #[doc = "Bit 9 - Interrupt 9"] #[inline(always)] #[must_use] - pub fn int9(&mut self) -> INT9_W<9> { + pub fn int9(&mut self) -> INT9_W { INT9_W::new(self) } #[doc = "Bit 10 - Interrupt 10"] #[inline(always)] #[must_use] - pub fn int10(&mut self) -> INT10_W<10> { + pub fn int10(&mut self) -> INT10_W { INT10_W::new(self) } #[doc = "Bit 11 - Interrupt 11"] #[inline(always)] #[must_use] - pub fn int11(&mut self) -> INT11_W<11> { + pub fn int11(&mut self) -> INT11_W { INT11_W::new(self) } #[doc = "Bit 12 - Interrupt 12"] #[inline(always)] #[must_use] - pub fn int12(&mut self) -> INT12_W<12> { + pub fn int12(&mut self) -> INT12_W { INT12_W::new(self) } #[doc = "Bit 13 - Interrupt 13"] #[inline(always)] #[must_use] - pub fn int13(&mut self) -> INT13_W<13> { + pub fn int13(&mut self) -> INT13_W { INT13_W::new(self) } #[doc = "Bit 14 - Interrupt 14"] #[inline(always)] #[must_use] - pub fn int14(&mut self) -> INT14_W<14> { + pub fn int14(&mut self) -> INT14_W { INT14_W::new(self) } #[doc = "Bit 15 - Interrupt 15"] #[inline(always)] #[must_use] - pub fn int15(&mut self) -> INT15_W<15> { + pub fn int15(&mut self) -> INT15_W { INT15_W::new(self) } #[doc = "Bit 16 - Interrupt 16"] #[inline(always)] #[must_use] - pub fn int16(&mut self) -> INT16_W<16> { + pub fn int16(&mut self) -> INT16_W { INT16_W::new(self) } #[doc = "Bit 17 - Interrupt 17"] #[inline(always)] #[must_use] - pub fn int17(&mut self) -> INT17_W<17> { + pub fn int17(&mut self) -> INT17_W { INT17_W::new(self) } #[doc = "Bit 18 - Interrupt 18"] #[inline(always)] #[must_use] - pub fn int18(&mut self) -> INT18_W<18> { + pub fn int18(&mut self) -> INT18_W { INT18_W::new(self) } #[doc = "Bit 19 - Interrupt 19"] #[inline(always)] #[must_use] - pub fn int19(&mut self) -> INT19_W<19> { + pub fn int19(&mut self) -> INT19_W { INT19_W::new(self) } #[doc = "Bit 20 - Interrupt 20"] #[inline(always)] #[must_use] - pub fn int20(&mut self) -> INT20_W<20> { + pub fn int20(&mut self) -> INT20_W { INT20_W::new(self) } #[doc = "Bit 21 - Interrupt 21"] #[inline(always)] #[must_use] - pub fn int21(&mut self) -> INT21_W<21> { + pub fn int21(&mut self) -> INT21_W { INT21_W::new(self) } #[doc = "Bit 22 - Interrupt 22"] #[inline(always)] #[must_use] - pub fn int22(&mut self) -> INT22_W<22> { + pub fn int22(&mut self) -> INT22_W { INT22_W::new(self) } #[doc = "Bit 23 - Interrupt 23"] #[inline(always)] #[must_use] - pub fn int23(&mut self) -> INT23_W<23> { + pub fn int23(&mut self) -> INT23_W { INT23_W::new(self) } #[doc = "Bit 24 - Interrupt 24"] #[inline(always)] #[must_use] - pub fn int24(&mut self) -> INT24_W<24> { + pub fn int24(&mut self) -> INT24_W { INT24_W::new(self) } #[doc = "Bit 25 - Interrupt 25"] #[inline(always)] #[must_use] - pub fn int25(&mut self) -> INT25_W<25> { + pub fn int25(&mut self) -> INT25_W { INT25_W::new(self) } #[doc = "Bit 26 - Interrupt 26"] #[inline(always)] #[must_use] - pub fn int26(&mut self) -> INT26_W<26> { + pub fn int26(&mut self) -> INT26_W { INT26_W::new(self) } #[doc = "Bit 27 - Interrupt 27"] #[inline(always)] #[must_use] - pub fn int27(&mut self) -> INT27_W<27> { + pub fn int27(&mut self) -> INT27_W { INT27_W::new(self) } #[doc = "Bit 28 - Interrupt 28"] #[inline(always)] #[must_use] - pub fn int28(&mut self) -> INT28_W<28> { + pub fn int28(&mut self) -> INT28_W { INT28_W::new(self) } #[doc = "Bit 29 - Interrupt 29"] #[inline(always)] #[must_use] - pub fn int29(&mut self) -> INT29_W<29> { + pub fn int29(&mut self) -> INT29_W { INT29_W::new(self) } #[doc = "Bit 30 - Interrupt 30"] #[inline(always)] #[must_use] - pub fn int30(&mut self) -> INT30_W<30> { + pub fn int30(&mut self) -> INT30_W { INT30_W::new(self) } #[doc = "Bit 31 - Interrupt 31"] #[inline(always)] #[must_use] - pub fn int31(&mut self) -> INT31_W<31> { + pub fn int31(&mut self) -> INT31_W { INT31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Disable interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_1](index.html) module"] +#[doc = "Disable interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DISABLE_1_SPEC; impl crate::RegisterSpec for DISABLE_1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [disable_1::R](R) reader structure"] -impl crate::Readable for DISABLE_1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [disable_1::W](W) writer structure"] +#[doc = "`read()` method returns [`disable_1::R`](R) reader structure"] +impl crate::Readable for DISABLE_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`disable_1::W`](W) writer structure"] impl crate::Writable for DISABLE_1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/lic/disable_2.rs b/crates/bcm2711-lpa/src/lic/disable_2.rs index 72f4f7a..a60ad36 100644 --- a/crates/bcm2711-lpa/src/lic/disable_2.rs +++ b/crates/bcm2711-lpa/src/lic/disable_2.rs @@ -1,167 +1,135 @@ #[doc = "Register `DISABLE_2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DISABLE_2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT32` reader - Interrupt 32"] -pub type INT32_R = crate::BitReader; +pub type INT32_R = crate::BitReader; #[doc = "Field `INT32` writer - Interrupt 32"] -pub type INT32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT32_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT33` reader - Interrupt 33"] -pub type INT33_R = crate::BitReader; +pub type INT33_R = crate::BitReader; #[doc = "Field `INT33` writer - Interrupt 33"] -pub type INT33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT33_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT34` reader - Interrupt 34"] -pub type INT34_R = crate::BitReader; +pub type INT34_R = crate::BitReader; #[doc = "Field `INT34` writer - Interrupt 34"] -pub type INT34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT34_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT35` reader - Interrupt 35"] -pub type INT35_R = crate::BitReader; +pub type INT35_R = crate::BitReader; #[doc = "Field `INT35` writer - Interrupt 35"] -pub type INT35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT35_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT36` reader - Interrupt 36"] -pub type INT36_R = crate::BitReader; +pub type INT36_R = crate::BitReader; #[doc = "Field `INT36` writer - Interrupt 36"] -pub type INT36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT36_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT37` reader - Interrupt 37"] -pub type INT37_R = crate::BitReader; +pub type INT37_R = crate::BitReader; #[doc = "Field `INT37` writer - Interrupt 37"] -pub type INT37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT37_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT38` reader - Interrupt 38"] -pub type INT38_R = crate::BitReader; +pub type INT38_R = crate::BitReader; #[doc = "Field `INT38` writer - Interrupt 38"] -pub type INT38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT38_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT39` reader - Interrupt 39"] -pub type INT39_R = crate::BitReader; +pub type INT39_R = crate::BitReader; #[doc = "Field `INT39` writer - Interrupt 39"] -pub type INT39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT39_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT40` reader - Interrupt 40"] -pub type INT40_R = crate::BitReader; +pub type INT40_R = crate::BitReader; #[doc = "Field `INT40` writer - Interrupt 40"] -pub type INT40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT40_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT41` reader - Interrupt 41"] -pub type INT41_R = crate::BitReader; +pub type INT41_R = crate::BitReader; #[doc = "Field `INT41` writer - Interrupt 41"] -pub type INT41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT41_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT42` reader - Interrupt 42"] -pub type INT42_R = crate::BitReader; +pub type INT42_R = crate::BitReader; #[doc = "Field `INT42` writer - Interrupt 42"] -pub type INT42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT42_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT43` reader - Interrupt 43"] -pub type INT43_R = crate::BitReader; +pub type INT43_R = crate::BitReader; #[doc = "Field `INT43` writer - Interrupt 43"] -pub type INT43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT43_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT44` reader - Interrupt 44"] -pub type INT44_R = crate::BitReader; +pub type INT44_R = crate::BitReader; #[doc = "Field `INT44` writer - Interrupt 44"] -pub type INT44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT44_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT45` reader - Interrupt 45"] -pub type INT45_R = crate::BitReader; +pub type INT45_R = crate::BitReader; #[doc = "Field `INT45` writer - Interrupt 45"] -pub type INT45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT45_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT46` reader - Interrupt 46"] -pub type INT46_R = crate::BitReader; +pub type INT46_R = crate::BitReader; #[doc = "Field `INT46` writer - Interrupt 46"] -pub type INT46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT46_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT47` reader - Interrupt 47"] -pub type INT47_R = crate::BitReader; +pub type INT47_R = crate::BitReader; #[doc = "Field `INT47` writer - Interrupt 47"] -pub type INT47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT47_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT48` reader - Interrupt 48"] -pub type INT48_R = crate::BitReader; +pub type INT48_R = crate::BitReader; #[doc = "Field `INT48` writer - Interrupt 48"] -pub type INT48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT48_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT49` reader - Interrupt 49"] -pub type INT49_R = crate::BitReader; +pub type INT49_R = crate::BitReader; #[doc = "Field `INT49` writer - Interrupt 49"] -pub type INT49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT49_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT50` reader - Interrupt 50"] -pub type INT50_R = crate::BitReader; +pub type INT50_R = crate::BitReader; #[doc = "Field `INT50` writer - Interrupt 50"] -pub type INT50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT50_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT51` reader - Interrupt 51"] -pub type INT51_R = crate::BitReader; +pub type INT51_R = crate::BitReader; #[doc = "Field `INT51` writer - Interrupt 51"] -pub type INT51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT51_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT52` reader - Interrupt 52"] -pub type INT52_R = crate::BitReader; +pub type INT52_R = crate::BitReader; #[doc = "Field `INT52` writer - Interrupt 52"] -pub type INT52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT52_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT53` reader - Interrupt 53"] -pub type INT53_R = crate::BitReader; +pub type INT53_R = crate::BitReader; #[doc = "Field `INT53` writer - Interrupt 53"] -pub type INT53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT53_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT54` reader - Interrupt 54"] -pub type INT54_R = crate::BitReader; +pub type INT54_R = crate::BitReader; #[doc = "Field `INT54` writer - Interrupt 54"] -pub type INT54_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT54_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT55` reader - Interrupt 55"] -pub type INT55_R = crate::BitReader; +pub type INT55_R = crate::BitReader; #[doc = "Field `INT55` writer - Interrupt 55"] -pub type INT55_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT55_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT56` reader - Interrupt 56"] -pub type INT56_R = crate::BitReader; +pub type INT56_R = crate::BitReader; #[doc = "Field `INT56` writer - Interrupt 56"] -pub type INT56_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT56_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT57` reader - Interrupt 57"] -pub type INT57_R = crate::BitReader; +pub type INT57_R = crate::BitReader; #[doc = "Field `INT57` writer - Interrupt 57"] -pub type INT57_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT57_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT58` reader - Interrupt 58"] -pub type INT58_R = crate::BitReader; +pub type INT58_R = crate::BitReader; #[doc = "Field `INT58` writer - Interrupt 58"] -pub type INT58_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT58_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT59` reader - Interrupt 59"] -pub type INT59_R = crate::BitReader; +pub type INT59_R = crate::BitReader; #[doc = "Field `INT59` writer - Interrupt 59"] -pub type INT59_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT59_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT60` reader - Interrupt 60"] -pub type INT60_R = crate::BitReader; +pub type INT60_R = crate::BitReader; #[doc = "Field `INT60` writer - Interrupt 60"] -pub type INT60_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT60_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT61` reader - Interrupt 61"] -pub type INT61_R = crate::BitReader; +pub type INT61_R = crate::BitReader; #[doc = "Field `INT61` writer - Interrupt 61"] -pub type INT61_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT61_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT62` reader - Interrupt 62"] -pub type INT62_R = crate::BitReader; +pub type INT62_R = crate::BitReader; #[doc = "Field `INT62` writer - Interrupt 62"] -pub type INT62_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT62_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `INT63` reader - Interrupt 63"] -pub type INT63_R = crate::BitReader; +pub type INT63_R = crate::BitReader; #[doc = "Field `INT63` writer - Interrupt 63"] -pub type INT63_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type INT63_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT63_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DISABLE_2") + .field("int32", &format_args!("{}", self.int32().bit())) + .field("int33", &format_args!("{}", self.int33().bit())) + .field("int34", &format_args!("{}", self.int34().bit())) + .field("int35", &format_args!("{}", self.int35().bit())) + .field("int36", &format_args!("{}", self.int36().bit())) + .field("int37", &format_args!("{}", self.int37().bit())) + .field("int38", &format_args!("{}", self.int38().bit())) + .field("int39", &format_args!("{}", self.int39().bit())) + .field("int40", &format_args!("{}", self.int40().bit())) + .field("int41", &format_args!("{}", self.int41().bit())) + .field("int42", &format_args!("{}", self.int42().bit())) + .field("int43", &format_args!("{}", self.int43().bit())) + .field("int44", &format_args!("{}", self.int44().bit())) + .field("int45", &format_args!("{}", self.int45().bit())) + .field("int46", &format_args!("{}", self.int46().bit())) + .field("int47", &format_args!("{}", self.int47().bit())) + .field("int48", &format_args!("{}", self.int48().bit())) + .field("int49", &format_args!("{}", self.int49().bit())) + .field("int50", &format_args!("{}", self.int50().bit())) + .field("int51", &format_args!("{}", self.int51().bit())) + .field("int52", &format_args!("{}", self.int52().bit())) + .field("int53", &format_args!("{}", self.int53().bit())) + .field("int54", &format_args!("{}", self.int54().bit())) + .field("int55", &format_args!("{}", self.int55().bit())) + .field("int56", &format_args!("{}", self.int56().bit())) + .field("int57", &format_args!("{}", self.int57().bit())) + .field("int58", &format_args!("{}", self.int58().bit())) + .field("int59", &format_args!("{}", self.int59().bit())) + .field("int60", &format_args!("{}", self.int60().bit())) + .field("int61", &format_args!("{}", self.int61().bit())) + .field("int62", &format_args!("{}", self.int62().bit())) + .field("int63", &format_args!("{}", self.int63().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] #[must_use] - pub fn int32(&mut self) -> INT32_W<0> { + pub fn int32(&mut self) -> INT32_W { INT32_W::new(self) } #[doc = "Bit 1 - Interrupt 33"] #[inline(always)] #[must_use] - pub fn int33(&mut self) -> INT33_W<1> { + pub fn int33(&mut self) -> INT33_W { INT33_W::new(self) } #[doc = "Bit 2 - Interrupt 34"] #[inline(always)] #[must_use] - pub fn int34(&mut self) -> INT34_W<2> { + pub fn int34(&mut self) -> INT34_W { INT34_W::new(self) } #[doc = "Bit 3 - Interrupt 35"] #[inline(always)] #[must_use] - pub fn int35(&mut self) -> INT35_W<3> { + pub fn int35(&mut self) -> INT35_W { INT35_W::new(self) } #[doc = "Bit 4 - Interrupt 36"] #[inline(always)] #[must_use] - pub fn int36(&mut self) -> INT36_W<4> { + pub fn int36(&mut self) -> INT36_W { INT36_W::new(self) } #[doc = "Bit 5 - Interrupt 37"] #[inline(always)] #[must_use] - pub fn int37(&mut self) -> INT37_W<5> { + pub fn int37(&mut self) -> INT37_W { INT37_W::new(self) } #[doc = "Bit 6 - Interrupt 38"] #[inline(always)] #[must_use] - pub fn int38(&mut self) -> INT38_W<6> { + pub fn int38(&mut self) -> INT38_W { INT38_W::new(self) } #[doc = "Bit 7 - Interrupt 39"] #[inline(always)] #[must_use] - pub fn int39(&mut self) -> INT39_W<7> { + pub fn int39(&mut self) -> INT39_W { INT39_W::new(self) } #[doc = "Bit 8 - Interrupt 40"] #[inline(always)] #[must_use] - pub fn int40(&mut self) -> INT40_W<8> { + pub fn int40(&mut self) -> INT40_W { INT40_W::new(self) } #[doc = "Bit 9 - Interrupt 41"] #[inline(always)] #[must_use] - pub fn int41(&mut self) -> INT41_W<9> { + pub fn int41(&mut self) -> INT41_W { INT41_W::new(self) } #[doc = "Bit 10 - Interrupt 42"] #[inline(always)] #[must_use] - pub fn int42(&mut self) -> INT42_W<10> { + pub fn int42(&mut self) -> INT42_W { INT42_W::new(self) } #[doc = "Bit 11 - Interrupt 43"] #[inline(always)] #[must_use] - pub fn int43(&mut self) -> INT43_W<11> { + pub fn int43(&mut self) -> INT43_W { INT43_W::new(self) } #[doc = "Bit 12 - Interrupt 44"] #[inline(always)] #[must_use] - pub fn int44(&mut self) -> INT44_W<12> { + pub fn int44(&mut self) -> INT44_W { INT44_W::new(self) } #[doc = "Bit 13 - Interrupt 45"] #[inline(always)] #[must_use] - pub fn int45(&mut self) -> INT45_W<13> { + pub fn int45(&mut self) -> INT45_W { INT45_W::new(self) } #[doc = "Bit 14 - Interrupt 46"] #[inline(always)] #[must_use] - pub fn int46(&mut self) -> INT46_W<14> { + pub fn int46(&mut self) -> INT46_W { INT46_W::new(self) } #[doc = "Bit 15 - Interrupt 47"] #[inline(always)] #[must_use] - pub fn int47(&mut self) -> INT47_W<15> { + pub fn int47(&mut self) -> INT47_W { INT47_W::new(self) } #[doc = "Bit 16 - Interrupt 48"] #[inline(always)] #[must_use] - pub fn int48(&mut self) -> INT48_W<16> { + pub fn int48(&mut self) -> INT48_W { INT48_W::new(self) } #[doc = "Bit 17 - Interrupt 49"] #[inline(always)] #[must_use] - pub fn int49(&mut self) -> INT49_W<17> { + pub fn int49(&mut self) -> INT49_W { INT49_W::new(self) } #[doc = "Bit 18 - Interrupt 50"] #[inline(always)] #[must_use] - pub fn int50(&mut self) -> INT50_W<18> { + pub fn int50(&mut self) -> INT50_W { INT50_W::new(self) } #[doc = "Bit 19 - Interrupt 51"] #[inline(always)] #[must_use] - pub fn int51(&mut self) -> INT51_W<19> { + pub fn int51(&mut self) -> INT51_W { INT51_W::new(self) } #[doc = "Bit 20 - Interrupt 52"] #[inline(always)] #[must_use] - pub fn int52(&mut self) -> INT52_W<20> { + pub fn int52(&mut self) -> INT52_W { INT52_W::new(self) } #[doc = "Bit 21 - Interrupt 53"] #[inline(always)] #[must_use] - pub fn int53(&mut self) -> INT53_W<21> { + pub fn int53(&mut self) -> INT53_W { INT53_W::new(self) } #[doc = "Bit 22 - Interrupt 54"] #[inline(always)] #[must_use] - pub fn int54(&mut self) -> INT54_W<22> { + pub fn int54(&mut self) -> INT54_W { INT54_W::new(self) } #[doc = "Bit 23 - Interrupt 55"] #[inline(always)] #[must_use] - pub fn int55(&mut self) -> INT55_W<23> { + pub fn int55(&mut self) -> INT55_W { INT55_W::new(self) } #[doc = "Bit 24 - Interrupt 56"] #[inline(always)] #[must_use] - pub fn int56(&mut self) -> INT56_W<24> { + pub fn int56(&mut self) -> INT56_W { INT56_W::new(self) } #[doc = "Bit 25 - Interrupt 57"] #[inline(always)] #[must_use] - pub fn int57(&mut self) -> INT57_W<25> { + pub fn int57(&mut self) -> INT57_W { INT57_W::new(self) } #[doc = "Bit 26 - Interrupt 58"] #[inline(always)] #[must_use] - pub fn int58(&mut self) -> INT58_W<26> { + pub fn int58(&mut self) -> INT58_W { INT58_W::new(self) } #[doc = "Bit 27 - Interrupt 59"] #[inline(always)] #[must_use] - pub fn int59(&mut self) -> INT59_W<27> { + pub fn int59(&mut self) -> INT59_W { INT59_W::new(self) } #[doc = "Bit 28 - Interrupt 60"] #[inline(always)] #[must_use] - pub fn int60(&mut self) -> INT60_W<28> { + pub fn int60(&mut self) -> INT60_W { INT60_W::new(self) } #[doc = "Bit 29 - Interrupt 61"] #[inline(always)] #[must_use] - pub fn int61(&mut self) -> INT61_W<29> { + pub fn int61(&mut self) -> INT61_W { INT61_W::new(self) } #[doc = "Bit 30 - Interrupt 62"] #[inline(always)] #[must_use] - pub fn int62(&mut self) -> INT62_W<30> { + pub fn int62(&mut self) -> INT62_W { INT62_W::new(self) } #[doc = "Bit 31 - Interrupt 63"] #[inline(always)] #[must_use] - pub fn int63(&mut self) -> INT63_W<31> { + pub fn int63(&mut self) -> INT63_W { INT63_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Disable interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_2](index.html) module"] +#[doc = "Disable interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DISABLE_2_SPEC; impl crate::RegisterSpec for DISABLE_2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [disable_2::R](R) reader structure"] -impl crate::Readable for DISABLE_2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [disable_2::W](W) writer structure"] +#[doc = "`read()` method returns [`disable_2::R`](R) reader structure"] +impl crate::Readable for DISABLE_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`disable_2::W`](W) writer structure"] impl crate::Writable for DISABLE_2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/lic/disable_basic.rs b/crates/bcm2711-lpa/src/lic/disable_basic.rs index df73f14..da28ed6 100644 --- a/crates/bcm2711-lpa/src/lic/disable_basic.rs +++ b/crates/bcm2711-lpa/src/lic/disable_basic.rs @@ -1,73 +1,39 @@ #[doc = "Register `DISABLE_BASIC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DISABLE_BASIC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -110,74 +76,100 @@ impl R { ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DISABLE_BASIC") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Disable basic interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_basic](index.html) module"] +#[doc = "Disable basic interrupts\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_basic::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_basic::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DISABLE_BASIC_SPEC; impl crate::RegisterSpec for DISABLE_BASIC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [disable_basic::R](R) reader structure"] -impl crate::Readable for DISABLE_BASIC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [disable_basic::W](W) writer structure"] +#[doc = "`read()` method returns [`disable_basic::R`](R) reader structure"] +impl crate::Readable for DISABLE_BASIC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`disable_basic::W`](W) writer structure"] impl crate::Writable for DISABLE_BASIC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; } diff --git a/crates/bcm2711-lpa/src/lic/enable_1.rs b/crates/bcm2711-lpa/src/lic/enable_1.rs index bb6550a..061118e 100644 --- a/crates/bcm2711-lpa/src/lic/enable_1.rs +++ b/crates/bcm2711-lpa/src/lic/enable_1.rs @@ -1,167 +1,135 @@ #[doc = "Register `ENABLE_1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ENABLE_1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT0` reader - Interrupt 0"] -pub type INT0_R = crate::BitReader; +pub type INT0_R = crate::BitReader; #[doc = "Field `INT0` writer - Interrupt 0"] -pub type INT0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT1` reader - Interrupt 1"] -pub type INT1_R = crate::BitReader; +pub type INT1_R = crate::BitReader; #[doc = "Field `INT1` writer - Interrupt 1"] -pub type INT1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT2` reader - Interrupt 2"] -pub type INT2_R = crate::BitReader; +pub type INT2_R = crate::BitReader; #[doc = "Field `INT2` writer - Interrupt 2"] -pub type INT2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT3` reader - Interrupt 3"] -pub type INT3_R = crate::BitReader; +pub type INT3_R = crate::BitReader; #[doc = "Field `INT3` writer - Interrupt 3"] -pub type INT3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT4` reader - Interrupt 4"] -pub type INT4_R = crate::BitReader; +pub type INT4_R = crate::BitReader; #[doc = "Field `INT4` writer - Interrupt 4"] -pub type INT4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT5` reader - Interrupt 5"] -pub type INT5_R = crate::BitReader; +pub type INT5_R = crate::BitReader; #[doc = "Field `INT5` writer - Interrupt 5"] -pub type INT5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT6` reader - Interrupt 6"] -pub type INT6_R = crate::BitReader; +pub type INT6_R = crate::BitReader; #[doc = "Field `INT6` writer - Interrupt 6"] -pub type INT6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT7` reader - Interrupt 7"] -pub type INT7_R = crate::BitReader; +pub type INT7_R = crate::BitReader; #[doc = "Field `INT7` writer - Interrupt 7"] -pub type INT7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT7_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT8` reader - Interrupt 8"] -pub type INT8_R = crate::BitReader; +pub type INT8_R = crate::BitReader; #[doc = "Field `INT8` writer - Interrupt 8"] -pub type INT8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT8_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT9` reader - Interrupt 9"] -pub type INT9_R = crate::BitReader; +pub type INT9_R = crate::BitReader; #[doc = "Field `INT9` writer - Interrupt 9"] -pub type INT9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT9_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT10` reader - Interrupt 10"] -pub type INT10_R = crate::BitReader; +pub type INT10_R = crate::BitReader; #[doc = "Field `INT10` writer - Interrupt 10"] -pub type INT10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT10_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT11` reader - Interrupt 11"] -pub type INT11_R = crate::BitReader; +pub type INT11_R = crate::BitReader; #[doc = "Field `INT11` writer - Interrupt 11"] -pub type INT11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT11_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT12` reader - Interrupt 12"] -pub type INT12_R = crate::BitReader; +pub type INT12_R = crate::BitReader; #[doc = "Field `INT12` writer - Interrupt 12"] -pub type INT12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT12_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT13` reader - Interrupt 13"] -pub type INT13_R = crate::BitReader; +pub type INT13_R = crate::BitReader; #[doc = "Field `INT13` writer - Interrupt 13"] -pub type INT13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT13_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT14` reader - Interrupt 14"] -pub type INT14_R = crate::BitReader; +pub type INT14_R = crate::BitReader; #[doc = "Field `INT14` writer - Interrupt 14"] -pub type INT14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT14_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT15` reader - Interrupt 15"] -pub type INT15_R = crate::BitReader; +pub type INT15_R = crate::BitReader; #[doc = "Field `INT15` writer - Interrupt 15"] -pub type INT15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT15_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT16` reader - Interrupt 16"] -pub type INT16_R = crate::BitReader; +pub type INT16_R = crate::BitReader; #[doc = "Field `INT16` writer - Interrupt 16"] -pub type INT16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT16_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT17` reader - Interrupt 17"] -pub type INT17_R = crate::BitReader; +pub type INT17_R = crate::BitReader; #[doc = "Field `INT17` writer - Interrupt 17"] -pub type INT17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT17_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT18` reader - Interrupt 18"] -pub type INT18_R = crate::BitReader; +pub type INT18_R = crate::BitReader; #[doc = "Field `INT18` writer - Interrupt 18"] -pub type INT18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT18_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT19` reader - Interrupt 19"] -pub type INT19_R = crate::BitReader; +pub type INT19_R = crate::BitReader; #[doc = "Field `INT19` writer - Interrupt 19"] -pub type INT19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT19_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT20` reader - Interrupt 20"] -pub type INT20_R = crate::BitReader; +pub type INT20_R = crate::BitReader; #[doc = "Field `INT20` writer - Interrupt 20"] -pub type INT20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT20_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT21` reader - Interrupt 21"] -pub type INT21_R = crate::BitReader; +pub type INT21_R = crate::BitReader; #[doc = "Field `INT21` writer - Interrupt 21"] -pub type INT21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT21_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT22` reader - Interrupt 22"] -pub type INT22_R = crate::BitReader; +pub type INT22_R = crate::BitReader; #[doc = "Field `INT22` writer - Interrupt 22"] -pub type INT22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT22_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT23` reader - Interrupt 23"] -pub type INT23_R = crate::BitReader; +pub type INT23_R = crate::BitReader; #[doc = "Field `INT23` writer - Interrupt 23"] -pub type INT23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT23_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT24` reader - Interrupt 24"] -pub type INT24_R = crate::BitReader; +pub type INT24_R = crate::BitReader; #[doc = "Field `INT24` writer - Interrupt 24"] -pub type INT24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT24_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT25` reader - Interrupt 25"] -pub type INT25_R = crate::BitReader; +pub type INT25_R = crate::BitReader; #[doc = "Field `INT25` writer - Interrupt 25"] -pub type INT25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT25_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT26` reader - Interrupt 26"] -pub type INT26_R = crate::BitReader; +pub type INT26_R = crate::BitReader; #[doc = "Field `INT26` writer - Interrupt 26"] -pub type INT26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT26_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT27` reader - Interrupt 27"] -pub type INT27_R = crate::BitReader; +pub type INT27_R = crate::BitReader; #[doc = "Field `INT27` writer - Interrupt 27"] -pub type INT27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT27_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT28` reader - Interrupt 28"] -pub type INT28_R = crate::BitReader; +pub type INT28_R = crate::BitReader; #[doc = "Field `INT28` writer - Interrupt 28"] -pub type INT28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT28_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT29` reader - Interrupt 29"] -pub type INT29_R = crate::BitReader; +pub type INT29_R = crate::BitReader; #[doc = "Field `INT29` writer - Interrupt 29"] -pub type INT29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT29_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT30` reader - Interrupt 30"] -pub type INT30_R = crate::BitReader; +pub type INT30_R = crate::BitReader; #[doc = "Field `INT30` writer - Interrupt 30"] -pub type INT30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT30_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT31` reader - Interrupt 31"] -pub type INT31_R = crate::BitReader; +pub type INT31_R = crate::BitReader; #[doc = "Field `INT31` writer - Interrupt 31"] -pub type INT31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type INT31_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLE_1") + .field("int0", &format_args!("{}", self.int0().bit())) + .field("int1", &format_args!("{}", self.int1().bit())) + .field("int2", &format_args!("{}", self.int2().bit())) + .field("int3", &format_args!("{}", self.int3().bit())) + .field("int4", &format_args!("{}", self.int4().bit())) + .field("int5", &format_args!("{}", self.int5().bit())) + .field("int6", &format_args!("{}", self.int6().bit())) + .field("int7", &format_args!("{}", self.int7().bit())) + .field("int8", &format_args!("{}", self.int8().bit())) + .field("int9", &format_args!("{}", self.int9().bit())) + .field("int10", &format_args!("{}", self.int10().bit())) + .field("int11", &format_args!("{}", self.int11().bit())) + .field("int12", &format_args!("{}", self.int12().bit())) + .field("int13", &format_args!("{}", self.int13().bit())) + .field("int14", &format_args!("{}", self.int14().bit())) + .field("int15", &format_args!("{}", self.int15().bit())) + .field("int16", &format_args!("{}", self.int16().bit())) + .field("int17", &format_args!("{}", self.int17().bit())) + .field("int18", &format_args!("{}", self.int18().bit())) + .field("int19", &format_args!("{}", self.int19().bit())) + .field("int20", &format_args!("{}", self.int20().bit())) + .field("int21", &format_args!("{}", self.int21().bit())) + .field("int22", &format_args!("{}", self.int22().bit())) + .field("int23", &format_args!("{}", self.int23().bit())) + .field("int24", &format_args!("{}", self.int24().bit())) + .field("int25", &format_args!("{}", self.int25().bit())) + .field("int26", &format_args!("{}", self.int26().bit())) + .field("int27", &format_args!("{}", self.int27().bit())) + .field("int28", &format_args!("{}", self.int28().bit())) + .field("int29", &format_args!("{}", self.int29().bit())) + .field("int30", &format_args!("{}", self.int30().bit())) + .field("int31", &format_args!("{}", self.int31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] #[must_use] - pub fn int0(&mut self) -> INT0_W<0> { + pub fn int0(&mut self) -> INT0_W { INT0_W::new(self) } #[doc = "Bit 1 - Interrupt 1"] #[inline(always)] #[must_use] - pub fn int1(&mut self) -> INT1_W<1> { + pub fn int1(&mut self) -> INT1_W { INT1_W::new(self) } #[doc = "Bit 2 - Interrupt 2"] #[inline(always)] #[must_use] - pub fn int2(&mut self) -> INT2_W<2> { + pub fn int2(&mut self) -> INT2_W { INT2_W::new(self) } #[doc = "Bit 3 - Interrupt 3"] #[inline(always)] #[must_use] - pub fn int3(&mut self) -> INT3_W<3> { + pub fn int3(&mut self) -> INT3_W { INT3_W::new(self) } #[doc = "Bit 4 - Interrupt 4"] #[inline(always)] #[must_use] - pub fn int4(&mut self) -> INT4_W<4> { + pub fn int4(&mut self) -> INT4_W { INT4_W::new(self) } #[doc = "Bit 5 - Interrupt 5"] #[inline(always)] #[must_use] - pub fn int5(&mut self) -> INT5_W<5> { + pub fn int5(&mut self) -> INT5_W { INT5_W::new(self) } #[doc = "Bit 6 - Interrupt 6"] #[inline(always)] #[must_use] - pub fn int6(&mut self) -> INT6_W<6> { + pub fn int6(&mut self) -> INT6_W { INT6_W::new(self) } #[doc = "Bit 7 - Interrupt 7"] #[inline(always)] #[must_use] - pub fn int7(&mut self) -> INT7_W<7> { + pub fn int7(&mut self) -> INT7_W { INT7_W::new(self) } #[doc = "Bit 8 - Interrupt 8"] #[inline(always)] #[must_use] - pub fn int8(&mut self) -> INT8_W<8> { + pub fn int8(&mut self) -> INT8_W { INT8_W::new(self) } #[doc = "Bit 9 - Interrupt 9"] #[inline(always)] #[must_use] - pub fn int9(&mut self) -> INT9_W<9> { + pub fn int9(&mut self) -> INT9_W { INT9_W::new(self) } #[doc = "Bit 10 - Interrupt 10"] #[inline(always)] #[must_use] - pub fn int10(&mut self) -> INT10_W<10> { + pub fn int10(&mut self) -> INT10_W { INT10_W::new(self) } #[doc = "Bit 11 - Interrupt 11"] #[inline(always)] #[must_use] - pub fn int11(&mut self) -> INT11_W<11> { + pub fn int11(&mut self) -> INT11_W { INT11_W::new(self) } #[doc = "Bit 12 - Interrupt 12"] #[inline(always)] #[must_use] - pub fn int12(&mut self) -> INT12_W<12> { + pub fn int12(&mut self) -> INT12_W { INT12_W::new(self) } #[doc = "Bit 13 - Interrupt 13"] #[inline(always)] #[must_use] - pub fn int13(&mut self) -> INT13_W<13> { + pub fn int13(&mut self) -> INT13_W { INT13_W::new(self) } #[doc = "Bit 14 - Interrupt 14"] #[inline(always)] #[must_use] - pub fn int14(&mut self) -> INT14_W<14> { + pub fn int14(&mut self) -> INT14_W { INT14_W::new(self) } #[doc = "Bit 15 - Interrupt 15"] #[inline(always)] #[must_use] - pub fn int15(&mut self) -> INT15_W<15> { + pub fn int15(&mut self) -> INT15_W { INT15_W::new(self) } #[doc = "Bit 16 - Interrupt 16"] #[inline(always)] #[must_use] - pub fn int16(&mut self) -> INT16_W<16> { + pub fn int16(&mut self) -> INT16_W { INT16_W::new(self) } #[doc = "Bit 17 - Interrupt 17"] #[inline(always)] #[must_use] - pub fn int17(&mut self) -> INT17_W<17> { + pub fn int17(&mut self) -> INT17_W { INT17_W::new(self) } #[doc = "Bit 18 - Interrupt 18"] #[inline(always)] #[must_use] - pub fn int18(&mut self) -> INT18_W<18> { + pub fn int18(&mut self) -> INT18_W { INT18_W::new(self) } #[doc = "Bit 19 - Interrupt 19"] #[inline(always)] #[must_use] - pub fn int19(&mut self) -> INT19_W<19> { + pub fn int19(&mut self) -> INT19_W { INT19_W::new(self) } #[doc = "Bit 20 - Interrupt 20"] #[inline(always)] #[must_use] - pub fn int20(&mut self) -> INT20_W<20> { + pub fn int20(&mut self) -> INT20_W { INT20_W::new(self) } #[doc = "Bit 21 - Interrupt 21"] #[inline(always)] #[must_use] - pub fn int21(&mut self) -> INT21_W<21> { + pub fn int21(&mut self) -> INT21_W { INT21_W::new(self) } #[doc = "Bit 22 - Interrupt 22"] #[inline(always)] #[must_use] - pub fn int22(&mut self) -> INT22_W<22> { + pub fn int22(&mut self) -> INT22_W { INT22_W::new(self) } #[doc = "Bit 23 - Interrupt 23"] #[inline(always)] #[must_use] - pub fn int23(&mut self) -> INT23_W<23> { + pub fn int23(&mut self) -> INT23_W { INT23_W::new(self) } #[doc = "Bit 24 - Interrupt 24"] #[inline(always)] #[must_use] - pub fn int24(&mut self) -> INT24_W<24> { + pub fn int24(&mut self) -> INT24_W { INT24_W::new(self) } #[doc = "Bit 25 - Interrupt 25"] #[inline(always)] #[must_use] - pub fn int25(&mut self) -> INT25_W<25> { + pub fn int25(&mut self) -> INT25_W { INT25_W::new(self) } #[doc = "Bit 26 - Interrupt 26"] #[inline(always)] #[must_use] - pub fn int26(&mut self) -> INT26_W<26> { + pub fn int26(&mut self) -> INT26_W { INT26_W::new(self) } #[doc = "Bit 27 - Interrupt 27"] #[inline(always)] #[must_use] - pub fn int27(&mut self) -> INT27_W<27> { + pub fn int27(&mut self) -> INT27_W { INT27_W::new(self) } #[doc = "Bit 28 - Interrupt 28"] #[inline(always)] #[must_use] - pub fn int28(&mut self) -> INT28_W<28> { + pub fn int28(&mut self) -> INT28_W { INT28_W::new(self) } #[doc = "Bit 29 - Interrupt 29"] #[inline(always)] #[must_use] - pub fn int29(&mut self) -> INT29_W<29> { + pub fn int29(&mut self) -> INT29_W { INT29_W::new(self) } #[doc = "Bit 30 - Interrupt 30"] #[inline(always)] #[must_use] - pub fn int30(&mut self) -> INT30_W<30> { + pub fn int30(&mut self) -> INT30_W { INT30_W::new(self) } #[doc = "Bit 31 - Interrupt 31"] #[inline(always)] #[must_use] - pub fn int31(&mut self) -> INT31_W<31> { + pub fn int31(&mut self) -> INT31_W { INT31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_1](index.html) module"] +#[doc = "Enable interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLE_1_SPEC; impl crate::RegisterSpec for ENABLE_1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enable_1::R](R) reader structure"] -impl crate::Readable for ENABLE_1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [enable_1::W](W) writer structure"] +#[doc = "`read()` method returns [`enable_1::R`](R) reader structure"] +impl crate::Readable for ENABLE_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enable_1::W`](W) writer structure"] impl crate::Writable for ENABLE_1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/lic/enable_2.rs b/crates/bcm2711-lpa/src/lic/enable_2.rs index 1f0dd90..f3f9e50 100644 --- a/crates/bcm2711-lpa/src/lic/enable_2.rs +++ b/crates/bcm2711-lpa/src/lic/enable_2.rs @@ -1,167 +1,135 @@ #[doc = "Register `ENABLE_2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ENABLE_2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INT32` reader - Interrupt 32"] -pub type INT32_R = crate::BitReader; +pub type INT32_R = crate::BitReader; #[doc = "Field `INT32` writer - Interrupt 32"] -pub type INT32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT32_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT33` reader - Interrupt 33"] -pub type INT33_R = crate::BitReader; +pub type INT33_R = crate::BitReader; #[doc = "Field `INT33` writer - Interrupt 33"] -pub type INT33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT33_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT34` reader - Interrupt 34"] -pub type INT34_R = crate::BitReader; +pub type INT34_R = crate::BitReader; #[doc = "Field `INT34` writer - Interrupt 34"] -pub type INT34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT34_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT35` reader - Interrupt 35"] -pub type INT35_R = crate::BitReader; +pub type INT35_R = crate::BitReader; #[doc = "Field `INT35` writer - Interrupt 35"] -pub type INT35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT35_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT36` reader - Interrupt 36"] -pub type INT36_R = crate::BitReader; +pub type INT36_R = crate::BitReader; #[doc = "Field `INT36` writer - Interrupt 36"] -pub type INT36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT36_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT37` reader - Interrupt 37"] -pub type INT37_R = crate::BitReader; +pub type INT37_R = crate::BitReader; #[doc = "Field `INT37` writer - Interrupt 37"] -pub type INT37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT37_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT38` reader - Interrupt 38"] -pub type INT38_R = crate::BitReader; +pub type INT38_R = crate::BitReader; #[doc = "Field `INT38` writer - Interrupt 38"] -pub type INT38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT38_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT39` reader - Interrupt 39"] -pub type INT39_R = crate::BitReader; +pub type INT39_R = crate::BitReader; #[doc = "Field `INT39` writer - Interrupt 39"] -pub type INT39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT39_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT40` reader - Interrupt 40"] -pub type INT40_R = crate::BitReader; +pub type INT40_R = crate::BitReader; #[doc = "Field `INT40` writer - Interrupt 40"] -pub type INT40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT40_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT41` reader - Interrupt 41"] -pub type INT41_R = crate::BitReader; +pub type INT41_R = crate::BitReader; #[doc = "Field `INT41` writer - Interrupt 41"] -pub type INT41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT41_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT42` reader - Interrupt 42"] -pub type INT42_R = crate::BitReader; +pub type INT42_R = crate::BitReader; #[doc = "Field `INT42` writer - Interrupt 42"] -pub type INT42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT42_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT43` reader - Interrupt 43"] -pub type INT43_R = crate::BitReader; +pub type INT43_R = crate::BitReader; #[doc = "Field `INT43` writer - Interrupt 43"] -pub type INT43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT43_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT44` reader - Interrupt 44"] -pub type INT44_R = crate::BitReader; +pub type INT44_R = crate::BitReader; #[doc = "Field `INT44` writer - Interrupt 44"] -pub type INT44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT44_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT45` reader - Interrupt 45"] -pub type INT45_R = crate::BitReader; +pub type INT45_R = crate::BitReader; #[doc = "Field `INT45` writer - Interrupt 45"] -pub type INT45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT45_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT46` reader - Interrupt 46"] -pub type INT46_R = crate::BitReader; +pub type INT46_R = crate::BitReader; #[doc = "Field `INT46` writer - Interrupt 46"] -pub type INT46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT46_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT47` reader - Interrupt 47"] -pub type INT47_R = crate::BitReader; +pub type INT47_R = crate::BitReader; #[doc = "Field `INT47` writer - Interrupt 47"] -pub type INT47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT47_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT48` reader - Interrupt 48"] -pub type INT48_R = crate::BitReader; +pub type INT48_R = crate::BitReader; #[doc = "Field `INT48` writer - Interrupt 48"] -pub type INT48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT48_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT49` reader - Interrupt 49"] -pub type INT49_R = crate::BitReader; +pub type INT49_R = crate::BitReader; #[doc = "Field `INT49` writer - Interrupt 49"] -pub type INT49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT49_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT50` reader - Interrupt 50"] -pub type INT50_R = crate::BitReader; +pub type INT50_R = crate::BitReader; #[doc = "Field `INT50` writer - Interrupt 50"] -pub type INT50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT50_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT51` reader - Interrupt 51"] -pub type INT51_R = crate::BitReader; +pub type INT51_R = crate::BitReader; #[doc = "Field `INT51` writer - Interrupt 51"] -pub type INT51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT51_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT52` reader - Interrupt 52"] -pub type INT52_R = crate::BitReader; +pub type INT52_R = crate::BitReader; #[doc = "Field `INT52` writer - Interrupt 52"] -pub type INT52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT52_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT53` reader - Interrupt 53"] -pub type INT53_R = crate::BitReader; +pub type INT53_R = crate::BitReader; #[doc = "Field `INT53` writer - Interrupt 53"] -pub type INT53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT53_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT54` reader - Interrupt 54"] -pub type INT54_R = crate::BitReader; +pub type INT54_R = crate::BitReader; #[doc = "Field `INT54` writer - Interrupt 54"] -pub type INT54_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT54_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT55` reader - Interrupt 55"] -pub type INT55_R = crate::BitReader; +pub type INT55_R = crate::BitReader; #[doc = "Field `INT55` writer - Interrupt 55"] -pub type INT55_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT55_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT56` reader - Interrupt 56"] -pub type INT56_R = crate::BitReader; +pub type INT56_R = crate::BitReader; #[doc = "Field `INT56` writer - Interrupt 56"] -pub type INT56_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT56_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT57` reader - Interrupt 57"] -pub type INT57_R = crate::BitReader; +pub type INT57_R = crate::BitReader; #[doc = "Field `INT57` writer - Interrupt 57"] -pub type INT57_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT57_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT58` reader - Interrupt 58"] -pub type INT58_R = crate::BitReader; +pub type INT58_R = crate::BitReader; #[doc = "Field `INT58` writer - Interrupt 58"] -pub type INT58_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT58_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT59` reader - Interrupt 59"] -pub type INT59_R = crate::BitReader; +pub type INT59_R = crate::BitReader; #[doc = "Field `INT59` writer - Interrupt 59"] -pub type INT59_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT59_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT60` reader - Interrupt 60"] -pub type INT60_R = crate::BitReader; +pub type INT60_R = crate::BitReader; #[doc = "Field `INT60` writer - Interrupt 60"] -pub type INT60_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT60_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT61` reader - Interrupt 61"] -pub type INT61_R = crate::BitReader; +pub type INT61_R = crate::BitReader; #[doc = "Field `INT61` writer - Interrupt 61"] -pub type INT61_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT61_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT62` reader - Interrupt 62"] -pub type INT62_R = crate::BitReader; +pub type INT62_R = crate::BitReader; #[doc = "Field `INT62` writer - Interrupt 62"] -pub type INT62_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT62_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `INT63` reader - Interrupt 63"] -pub type INT63_R = crate::BitReader; +pub type INT63_R = crate::BitReader; #[doc = "Field `INT63` writer - Interrupt 63"] -pub type INT63_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type INT63_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { INT63_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLE_2") + .field("int32", &format_args!("{}", self.int32().bit())) + .field("int33", &format_args!("{}", self.int33().bit())) + .field("int34", &format_args!("{}", self.int34().bit())) + .field("int35", &format_args!("{}", self.int35().bit())) + .field("int36", &format_args!("{}", self.int36().bit())) + .field("int37", &format_args!("{}", self.int37().bit())) + .field("int38", &format_args!("{}", self.int38().bit())) + .field("int39", &format_args!("{}", self.int39().bit())) + .field("int40", &format_args!("{}", self.int40().bit())) + .field("int41", &format_args!("{}", self.int41().bit())) + .field("int42", &format_args!("{}", self.int42().bit())) + .field("int43", &format_args!("{}", self.int43().bit())) + .field("int44", &format_args!("{}", self.int44().bit())) + .field("int45", &format_args!("{}", self.int45().bit())) + .field("int46", &format_args!("{}", self.int46().bit())) + .field("int47", &format_args!("{}", self.int47().bit())) + .field("int48", &format_args!("{}", self.int48().bit())) + .field("int49", &format_args!("{}", self.int49().bit())) + .field("int50", &format_args!("{}", self.int50().bit())) + .field("int51", &format_args!("{}", self.int51().bit())) + .field("int52", &format_args!("{}", self.int52().bit())) + .field("int53", &format_args!("{}", self.int53().bit())) + .field("int54", &format_args!("{}", self.int54().bit())) + .field("int55", &format_args!("{}", self.int55().bit())) + .field("int56", &format_args!("{}", self.int56().bit())) + .field("int57", &format_args!("{}", self.int57().bit())) + .field("int58", &format_args!("{}", self.int58().bit())) + .field("int59", &format_args!("{}", self.int59().bit())) + .field("int60", &format_args!("{}", self.int60().bit())) + .field("int61", &format_args!("{}", self.int61().bit())) + .field("int62", &format_args!("{}", self.int62().bit())) + .field("int63", &format_args!("{}", self.int63().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] #[must_use] - pub fn int32(&mut self) -> INT32_W<0> { + pub fn int32(&mut self) -> INT32_W { INT32_W::new(self) } #[doc = "Bit 1 - Interrupt 33"] #[inline(always)] #[must_use] - pub fn int33(&mut self) -> INT33_W<1> { + pub fn int33(&mut self) -> INT33_W { INT33_W::new(self) } #[doc = "Bit 2 - Interrupt 34"] #[inline(always)] #[must_use] - pub fn int34(&mut self) -> INT34_W<2> { + pub fn int34(&mut self) -> INT34_W { INT34_W::new(self) } #[doc = "Bit 3 - Interrupt 35"] #[inline(always)] #[must_use] - pub fn int35(&mut self) -> INT35_W<3> { + pub fn int35(&mut self) -> INT35_W { INT35_W::new(self) } #[doc = "Bit 4 - Interrupt 36"] #[inline(always)] #[must_use] - pub fn int36(&mut self) -> INT36_W<4> { + pub fn int36(&mut self) -> INT36_W { INT36_W::new(self) } #[doc = "Bit 5 - Interrupt 37"] #[inline(always)] #[must_use] - pub fn int37(&mut self) -> INT37_W<5> { + pub fn int37(&mut self) -> INT37_W { INT37_W::new(self) } #[doc = "Bit 6 - Interrupt 38"] #[inline(always)] #[must_use] - pub fn int38(&mut self) -> INT38_W<6> { + pub fn int38(&mut self) -> INT38_W { INT38_W::new(self) } #[doc = "Bit 7 - Interrupt 39"] #[inline(always)] #[must_use] - pub fn int39(&mut self) -> INT39_W<7> { + pub fn int39(&mut self) -> INT39_W { INT39_W::new(self) } #[doc = "Bit 8 - Interrupt 40"] #[inline(always)] #[must_use] - pub fn int40(&mut self) -> INT40_W<8> { + pub fn int40(&mut self) -> INT40_W { INT40_W::new(self) } #[doc = "Bit 9 - Interrupt 41"] #[inline(always)] #[must_use] - pub fn int41(&mut self) -> INT41_W<9> { + pub fn int41(&mut self) -> INT41_W { INT41_W::new(self) } #[doc = "Bit 10 - Interrupt 42"] #[inline(always)] #[must_use] - pub fn int42(&mut self) -> INT42_W<10> { + pub fn int42(&mut self) -> INT42_W { INT42_W::new(self) } #[doc = "Bit 11 - Interrupt 43"] #[inline(always)] #[must_use] - pub fn int43(&mut self) -> INT43_W<11> { + pub fn int43(&mut self) -> INT43_W { INT43_W::new(self) } #[doc = "Bit 12 - Interrupt 44"] #[inline(always)] #[must_use] - pub fn int44(&mut self) -> INT44_W<12> { + pub fn int44(&mut self) -> INT44_W { INT44_W::new(self) } #[doc = "Bit 13 - Interrupt 45"] #[inline(always)] #[must_use] - pub fn int45(&mut self) -> INT45_W<13> { + pub fn int45(&mut self) -> INT45_W { INT45_W::new(self) } #[doc = "Bit 14 - Interrupt 46"] #[inline(always)] #[must_use] - pub fn int46(&mut self) -> INT46_W<14> { + pub fn int46(&mut self) -> INT46_W { INT46_W::new(self) } #[doc = "Bit 15 - Interrupt 47"] #[inline(always)] #[must_use] - pub fn int47(&mut self) -> INT47_W<15> { + pub fn int47(&mut self) -> INT47_W { INT47_W::new(self) } #[doc = "Bit 16 - Interrupt 48"] #[inline(always)] #[must_use] - pub fn int48(&mut self) -> INT48_W<16> { + pub fn int48(&mut self) -> INT48_W { INT48_W::new(self) } #[doc = "Bit 17 - Interrupt 49"] #[inline(always)] #[must_use] - pub fn int49(&mut self) -> INT49_W<17> { + pub fn int49(&mut self) -> INT49_W { INT49_W::new(self) } #[doc = "Bit 18 - Interrupt 50"] #[inline(always)] #[must_use] - pub fn int50(&mut self) -> INT50_W<18> { + pub fn int50(&mut self) -> INT50_W { INT50_W::new(self) } #[doc = "Bit 19 - Interrupt 51"] #[inline(always)] #[must_use] - pub fn int51(&mut self) -> INT51_W<19> { + pub fn int51(&mut self) -> INT51_W { INT51_W::new(self) } #[doc = "Bit 20 - Interrupt 52"] #[inline(always)] #[must_use] - pub fn int52(&mut self) -> INT52_W<20> { + pub fn int52(&mut self) -> INT52_W { INT52_W::new(self) } #[doc = "Bit 21 - Interrupt 53"] #[inline(always)] #[must_use] - pub fn int53(&mut self) -> INT53_W<21> { + pub fn int53(&mut self) -> INT53_W { INT53_W::new(self) } #[doc = "Bit 22 - Interrupt 54"] #[inline(always)] #[must_use] - pub fn int54(&mut self) -> INT54_W<22> { + pub fn int54(&mut self) -> INT54_W { INT54_W::new(self) } #[doc = "Bit 23 - Interrupt 55"] #[inline(always)] #[must_use] - pub fn int55(&mut self) -> INT55_W<23> { + pub fn int55(&mut self) -> INT55_W { INT55_W::new(self) } #[doc = "Bit 24 - Interrupt 56"] #[inline(always)] #[must_use] - pub fn int56(&mut self) -> INT56_W<24> { + pub fn int56(&mut self) -> INT56_W { INT56_W::new(self) } #[doc = "Bit 25 - Interrupt 57"] #[inline(always)] #[must_use] - pub fn int57(&mut self) -> INT57_W<25> { + pub fn int57(&mut self) -> INT57_W { INT57_W::new(self) } #[doc = "Bit 26 - Interrupt 58"] #[inline(always)] #[must_use] - pub fn int58(&mut self) -> INT58_W<26> { + pub fn int58(&mut self) -> INT58_W { INT58_W::new(self) } #[doc = "Bit 27 - Interrupt 59"] #[inline(always)] #[must_use] - pub fn int59(&mut self) -> INT59_W<27> { + pub fn int59(&mut self) -> INT59_W { INT59_W::new(self) } #[doc = "Bit 28 - Interrupt 60"] #[inline(always)] #[must_use] - pub fn int60(&mut self) -> INT60_W<28> { + pub fn int60(&mut self) -> INT60_W { INT60_W::new(self) } #[doc = "Bit 29 - Interrupt 61"] #[inline(always)] #[must_use] - pub fn int61(&mut self) -> INT61_W<29> { + pub fn int61(&mut self) -> INT61_W { INT61_W::new(self) } #[doc = "Bit 30 - Interrupt 62"] #[inline(always)] #[must_use] - pub fn int62(&mut self) -> INT62_W<30> { + pub fn int62(&mut self) -> INT62_W { INT62_W::new(self) } #[doc = "Bit 31 - Interrupt 63"] #[inline(always)] #[must_use] - pub fn int63(&mut self) -> INT63_W<31> { + pub fn int63(&mut self) -> INT63_W { INT63_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_2](index.html) module"] +#[doc = "Enable interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLE_2_SPEC; impl crate::RegisterSpec for ENABLE_2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enable_2::R](R) reader structure"] -impl crate::Readable for ENABLE_2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [enable_2::W](W) writer structure"] +#[doc = "`read()` method returns [`enable_2::R`](R) reader structure"] +impl crate::Readable for ENABLE_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enable_2::W`](W) writer structure"] impl crate::Writable for ENABLE_2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2711-lpa/src/lic/enable_basic.rs b/crates/bcm2711-lpa/src/lic/enable_basic.rs index b401deb..3533529 100644 --- a/crates/bcm2711-lpa/src/lic/enable_basic.rs +++ b/crates/bcm2711-lpa/src/lic/enable_basic.rs @@ -1,72 +1,39 @@ #[doc = "Register `ENABLE_BASIC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ENABLE_BASIC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -109,74 +76,100 @@ impl R { ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLE_BASIC") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable basic interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_basic](index.html) module"] +#[doc = "Enable basic interrupts\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_basic::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_basic::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLE_BASIC_SPEC; impl crate::RegisterSpec for ENABLE_BASIC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enable_basic::R](R) reader structure"] -impl crate::Readable for ENABLE_BASIC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [enable_basic::W](W) writer structure"] +#[doc = "`read()` method returns [`enable_basic::R`](R) reader structure"] +impl crate::Readable for ENABLE_BASIC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enable_basic::W`](W) writer structure"] impl crate::Writable for ENABLE_BASIC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; } diff --git a/crates/bcm2711-lpa/src/lic/fiq_control.rs b/crates/bcm2711-lpa/src/lic/fiq_control.rs index a54e91f..d27183a 100644 --- a/crates/bcm2711-lpa/src/lic/fiq_control.rs +++ b/crates/bcm2711-lpa/src/lic/fiq_control.rs @@ -1,41 +1,9 @@ #[doc = "Register `FIQ_CONTROL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FIQ_CONTROL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SOURCE` reader - FIQ Source"] -pub type SOURCE_R = crate::FieldReader; +pub type SOURCE_R = crate::FieldReader; #[doc = "FIQ Source\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -191,10 +159,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for SOURCE_A { + type Ux = u8; +} impl SOURCE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(SOURCE_A::INT0), 1 => Some(SOURCE_A::INT1), @@ -271,736 +242,739 @@ impl SOURCE_R { _ => None, } } - #[doc = "Checks if the value of the field is `INT0`"] + #[doc = "Interrupt 0"] #[inline(always)] pub fn is_int0(&self) -> bool { *self == SOURCE_A::INT0 } - #[doc = "Checks if the value of the field is `INT1`"] + #[doc = "Interrupt 1"] #[inline(always)] pub fn is_int1(&self) -> bool { *self == SOURCE_A::INT1 } - #[doc = "Checks if the value of the field is `INT2`"] + #[doc = "Interrupt 2"] #[inline(always)] pub fn is_int2(&self) -> bool { *self == SOURCE_A::INT2 } - #[doc = "Checks if the value of the field is `INT3`"] + #[doc = "Interrupt 3"] #[inline(always)] pub fn is_int3(&self) -> bool { *self == SOURCE_A::INT3 } - #[doc = "Checks if the value of the field is `INT4`"] + #[doc = "Interrupt 4"] #[inline(always)] pub fn is_int4(&self) -> bool { *self == SOURCE_A::INT4 } - #[doc = "Checks if the value of the field is `INT5`"] + #[doc = "Interrupt 5"] #[inline(always)] pub fn is_int5(&self) -> bool { *self == SOURCE_A::INT5 } - #[doc = "Checks if the value of the field is `INT6`"] + #[doc = "Interrupt 6"] #[inline(always)] pub fn is_int6(&self) -> bool { *self == SOURCE_A::INT6 } - #[doc = "Checks if the value of the field is `INT7`"] + #[doc = "Interrupt 7"] #[inline(always)] pub fn is_int7(&self) -> bool { *self == SOURCE_A::INT7 } - #[doc = "Checks if the value of the field is `INT8`"] + #[doc = "Interrupt 8"] #[inline(always)] pub fn is_int8(&self) -> bool { *self == SOURCE_A::INT8 } - #[doc = "Checks if the value of the field is `INT9`"] + #[doc = "Interrupt 9"] #[inline(always)] pub fn is_int9(&self) -> bool { *self == SOURCE_A::INT9 } - #[doc = "Checks if the value of the field is `INT10`"] + #[doc = "Interrupt 10"] #[inline(always)] pub fn is_int10(&self) -> bool { *self == SOURCE_A::INT10 } - #[doc = "Checks if the value of the field is `INT11`"] + #[doc = "Interrupt 11"] #[inline(always)] pub fn is_int11(&self) -> bool { *self == SOURCE_A::INT11 } - #[doc = "Checks if the value of the field is `INT12`"] + #[doc = "Interrupt 12"] #[inline(always)] pub fn is_int12(&self) -> bool { *self == SOURCE_A::INT12 } - #[doc = "Checks if the value of the field is `INT13`"] + #[doc = "Interrupt 13"] #[inline(always)] pub fn is_int13(&self) -> bool { *self == SOURCE_A::INT13 } - #[doc = "Checks if the value of the field is `INT14`"] + #[doc = "Interrupt 14"] #[inline(always)] pub fn is_int14(&self) -> bool { *self == SOURCE_A::INT14 } - #[doc = "Checks if the value of the field is `INT15`"] + #[doc = "Interrupt 15"] #[inline(always)] pub fn is_int15(&self) -> bool { *self == SOURCE_A::INT15 } - #[doc = "Checks if the value of the field is `INT16`"] + #[doc = "Interrupt 16"] #[inline(always)] pub fn is_int16(&self) -> bool { *self == SOURCE_A::INT16 } - #[doc = "Checks if the value of the field is `INT17`"] + #[doc = "Interrupt 17"] #[inline(always)] pub fn is_int17(&self) -> bool { *self == SOURCE_A::INT17 } - #[doc = "Checks if the value of the field is `INT18`"] + #[doc = "Interrupt 18"] #[inline(always)] pub fn is_int18(&self) -> bool { *self == SOURCE_A::INT18 } - #[doc = "Checks if the value of the field is `INT19`"] + #[doc = "Interrupt 19"] #[inline(always)] pub fn is_int19(&self) -> bool { *self == SOURCE_A::INT19 } - #[doc = "Checks if the value of the field is `INT20`"] + #[doc = "Interrupt 20"] #[inline(always)] pub fn is_int20(&self) -> bool { *self == SOURCE_A::INT20 } - #[doc = "Checks if the value of the field is `INT21`"] + #[doc = "Interrupt 21"] #[inline(always)] pub fn is_int21(&self) -> bool { *self == SOURCE_A::INT21 } - #[doc = "Checks if the value of the field is `INT22`"] + #[doc = "Interrupt 22"] #[inline(always)] pub fn is_int22(&self) -> bool { *self == SOURCE_A::INT22 } - #[doc = "Checks if the value of the field is `INT23`"] + #[doc = "Interrupt 23"] #[inline(always)] pub fn is_int23(&self) -> bool { *self == SOURCE_A::INT23 } - #[doc = "Checks if the value of the field is `INT24`"] + #[doc = "Interrupt 24"] #[inline(always)] pub fn is_int24(&self) -> bool { *self == SOURCE_A::INT24 } - #[doc = "Checks if the value of the field is `INT25`"] + #[doc = "Interrupt 25"] #[inline(always)] pub fn is_int25(&self) -> bool { *self == SOURCE_A::INT25 } - #[doc = "Checks if the value of the field is `INT26`"] + #[doc = "Interrupt 26"] #[inline(always)] pub fn is_int26(&self) -> bool { *self == SOURCE_A::INT26 } - #[doc = "Checks if the value of the field is `INT27`"] + #[doc = "Interrupt 27"] #[inline(always)] pub fn is_int27(&self) -> bool { *self == SOURCE_A::INT27 } - #[doc = "Checks if the value of the field is `INT28`"] + #[doc = "Interrupt 28"] #[inline(always)] pub fn is_int28(&self) -> bool { *self == SOURCE_A::INT28 } - #[doc = "Checks if the value of the field is `INT29`"] + #[doc = "Interrupt 29"] #[inline(always)] pub fn is_int29(&self) -> bool { *self == SOURCE_A::INT29 } - #[doc = "Checks if the value of the field is `INT30`"] + #[doc = "Interrupt 30"] #[inline(always)] pub fn is_int30(&self) -> bool { *self == SOURCE_A::INT30 } - #[doc = "Checks if the value of the field is `INT31`"] + #[doc = "Interrupt 31"] #[inline(always)] pub fn is_int31(&self) -> bool { *self == SOURCE_A::INT31 } - #[doc = "Checks if the value of the field is `INT32`"] + #[doc = "Interrupt 32"] #[inline(always)] pub fn is_int32(&self) -> bool { *self == SOURCE_A::INT32 } - #[doc = "Checks if the value of the field is `INT33`"] + #[doc = "Interrupt 33"] #[inline(always)] pub fn is_int33(&self) -> bool { *self == SOURCE_A::INT33 } - #[doc = "Checks if the value of the field is `INT34`"] + #[doc = "Interrupt 34"] #[inline(always)] pub fn is_int34(&self) -> bool { *self == SOURCE_A::INT34 } - #[doc = "Checks if the value of the field is `INT35`"] + #[doc = "Interrupt 35"] #[inline(always)] pub fn is_int35(&self) -> bool { *self == SOURCE_A::INT35 } - #[doc = "Checks if the value of the field is `INT36`"] + #[doc = "Interrupt 36"] #[inline(always)] pub fn is_int36(&self) -> bool { *self == SOURCE_A::INT36 } - #[doc = "Checks if the value of the field is `INT37`"] + #[doc = "Interrupt 37"] #[inline(always)] pub fn is_int37(&self) -> bool { *self == SOURCE_A::INT37 } - #[doc = "Checks if the value of the field is `INT38`"] + #[doc = "Interrupt 38"] #[inline(always)] pub fn is_int38(&self) -> bool { *self == SOURCE_A::INT38 } - #[doc = "Checks if the value of the field is `INT39`"] + #[doc = "Interrupt 39"] #[inline(always)] pub fn is_int39(&self) -> bool { *self == SOURCE_A::INT39 } - #[doc = "Checks if the value of the field is `INT40`"] + #[doc = "Interrupt 40"] #[inline(always)] pub fn is_int40(&self) -> bool { *self == SOURCE_A::INT40 } - #[doc = "Checks if the value of the field is `INT41`"] + #[doc = "Interrupt 41"] #[inline(always)] pub fn is_int41(&self) -> bool { *self == SOURCE_A::INT41 } - #[doc = "Checks if the value of the field is `INT42`"] + #[doc = "Interrupt 42"] #[inline(always)] pub fn is_int42(&self) -> bool { *self == SOURCE_A::INT42 } - #[doc = "Checks if the value of the field is `INT43`"] + #[doc = "Interrupt 43"] #[inline(always)] pub fn is_int43(&self) -> bool { *self == SOURCE_A::INT43 } - #[doc = "Checks if the value of the field is `INT44`"] + #[doc = "Interrupt 44"] #[inline(always)] pub fn is_int44(&self) -> bool { *self == SOURCE_A::INT44 } - #[doc = "Checks if the value of the field is `INT45`"] + #[doc = "Interrupt 45"] #[inline(always)] pub fn is_int45(&self) -> bool { *self == SOURCE_A::INT45 } - #[doc = "Checks if the value of the field is `INT46`"] + #[doc = "Interrupt 46"] #[inline(always)] pub fn is_int46(&self) -> bool { *self == SOURCE_A::INT46 } - #[doc = "Checks if the value of the field is `INT47`"] + #[doc = "Interrupt 47"] #[inline(always)] pub fn is_int47(&self) -> bool { *self == SOURCE_A::INT47 } - #[doc = "Checks if the value of the field is `INT48`"] + #[doc = "Interrupt 48"] #[inline(always)] pub fn is_int48(&self) -> bool { *self == SOURCE_A::INT48 } - #[doc = "Checks if the value of the field is `INT49`"] + #[doc = "Interrupt 49"] #[inline(always)] pub fn is_int49(&self) -> bool { *self == SOURCE_A::INT49 } - #[doc = "Checks if the value of the field is `INT50`"] + #[doc = "Interrupt 50"] #[inline(always)] pub fn is_int50(&self) -> bool { *self == SOURCE_A::INT50 } - #[doc = "Checks if the value of the field is `INT51`"] + #[doc = "Interrupt 51"] #[inline(always)] pub fn is_int51(&self) -> bool { *self == SOURCE_A::INT51 } - #[doc = "Checks if the value of the field is `INT52`"] + #[doc = "Interrupt 52"] #[inline(always)] pub fn is_int52(&self) -> bool { *self == SOURCE_A::INT52 } - #[doc = "Checks if the value of the field is `INT53`"] + #[doc = "Interrupt 53"] #[inline(always)] pub fn is_int53(&self) -> bool { *self == SOURCE_A::INT53 } - #[doc = "Checks if the value of the field is `INT54`"] + #[doc = "Interrupt 54"] #[inline(always)] pub fn is_int54(&self) -> bool { *self == SOURCE_A::INT54 } - #[doc = "Checks if the value of the field is `INT55`"] + #[doc = "Interrupt 55"] #[inline(always)] pub fn is_int55(&self) -> bool { *self == SOURCE_A::INT55 } - #[doc = "Checks if the value of the field is `INT56`"] + #[doc = "Interrupt 56"] #[inline(always)] pub fn is_int56(&self) -> bool { *self == SOURCE_A::INT56 } - #[doc = "Checks if the value of the field is `INT57`"] + #[doc = "Interrupt 57"] #[inline(always)] pub fn is_int57(&self) -> bool { *self == SOURCE_A::INT57 } - #[doc = "Checks if the value of the field is `INT58`"] + #[doc = "Interrupt 58"] #[inline(always)] pub fn is_int58(&self) -> bool { *self == SOURCE_A::INT58 } - #[doc = "Checks if the value of the field is `INT59`"] + #[doc = "Interrupt 59"] #[inline(always)] pub fn is_int59(&self) -> bool { *self == SOURCE_A::INT59 } - #[doc = "Checks if the value of the field is `INT60`"] + #[doc = "Interrupt 60"] #[inline(always)] pub fn is_int60(&self) -> bool { *self == SOURCE_A::INT60 } - #[doc = "Checks if the value of the field is `INT61`"] + #[doc = "Interrupt 61"] #[inline(always)] pub fn is_int61(&self) -> bool { *self == SOURCE_A::INT61 } - #[doc = "Checks if the value of the field is `INT62`"] + #[doc = "Interrupt 62"] #[inline(always)] pub fn is_int62(&self) -> bool { *self == SOURCE_A::INT62 } - #[doc = "Checks if the value of the field is `INT63`"] + #[doc = "Interrupt 63"] #[inline(always)] pub fn is_int63(&self) -> bool { *self == SOURCE_A::INT63 } - #[doc = "Checks if the value of the field is `TIMER`"] + #[doc = "ARMC Timer"] #[inline(always)] pub fn is_timer(&self) -> bool { *self == SOURCE_A::TIMER } - #[doc = "Checks if the value of the field is `MAILBOX`"] + #[doc = "Mailbox"] #[inline(always)] pub fn is_mailbox(&self) -> bool { *self == SOURCE_A::MAILBOX } - #[doc = "Checks if the value of the field is `DOORBELL0`"] + #[doc = "Doorbell 0"] #[inline(always)] pub fn is_doorbell0(&self) -> bool { *self == SOURCE_A::DOORBELL0 } - #[doc = "Checks if the value of the field is `DOORBELL1`"] + #[doc = "Doorbell 1"] #[inline(always)] pub fn is_doorbell1(&self) -> bool { *self == SOURCE_A::DOORBELL1 } - #[doc = "Checks if the value of the field is `VPU0_HALTED`"] + #[doc = "VPU0 halted"] #[inline(always)] pub fn is_vpu0_halted(&self) -> bool { *self == SOURCE_A::VPU0_HALTED } - #[doc = "Checks if the value of the field is `VPU1_HALTED`"] + #[doc = "VPU1 halted"] #[inline(always)] pub fn is_vpu1_halted(&self) -> bool { *self == SOURCE_A::VPU1_HALTED } - #[doc = "Checks if the value of the field is `ARM_ADDRESS_ERROR`"] + #[doc = "ARM address error"] #[inline(always)] pub fn is_arm_address_error(&self) -> bool { *self == SOURCE_A::ARM_ADDRESS_ERROR } - #[doc = "Checks if the value of the field is `ARM_AXI_ERROR`"] + #[doc = "ARM AXI error"] #[inline(always)] pub fn is_arm_axi_error(&self) -> bool { *self == SOURCE_A::ARM_AXI_ERROR } } #[doc = "Field `SOURCE` writer - FIQ Source"] -pub type SOURCE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, FIQ_CONTROL_SPEC, u8, SOURCE_A, 7, O>; -impl<'a, const O: u8> SOURCE_W<'a, O> { +pub type SOURCE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O, SOURCE_A>; +impl<'a, REG, const O: u8> SOURCE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Interrupt 0"] #[inline(always)] - pub fn int0(self) -> &'a mut W { + pub fn int0(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT0) } #[doc = "Interrupt 1"] #[inline(always)] - pub fn int1(self) -> &'a mut W { + pub fn int1(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT1) } #[doc = "Interrupt 2"] #[inline(always)] - pub fn int2(self) -> &'a mut W { + pub fn int2(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT2) } #[doc = "Interrupt 3"] #[inline(always)] - pub fn int3(self) -> &'a mut W { + pub fn int3(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT3) } #[doc = "Interrupt 4"] #[inline(always)] - pub fn int4(self) -> &'a mut W { + pub fn int4(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT4) } #[doc = "Interrupt 5"] #[inline(always)] - pub fn int5(self) -> &'a mut W { + pub fn int5(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT5) } #[doc = "Interrupt 6"] #[inline(always)] - pub fn int6(self) -> &'a mut W { + pub fn int6(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT6) } #[doc = "Interrupt 7"] #[inline(always)] - pub fn int7(self) -> &'a mut W { + pub fn int7(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT7) } #[doc = "Interrupt 8"] #[inline(always)] - pub fn int8(self) -> &'a mut W { + pub fn int8(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT8) } #[doc = "Interrupt 9"] #[inline(always)] - pub fn int9(self) -> &'a mut W { + pub fn int9(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT9) } #[doc = "Interrupt 10"] #[inline(always)] - pub fn int10(self) -> &'a mut W { + pub fn int10(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT10) } #[doc = "Interrupt 11"] #[inline(always)] - pub fn int11(self) -> &'a mut W { + pub fn int11(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT11) } #[doc = "Interrupt 12"] #[inline(always)] - pub fn int12(self) -> &'a mut W { + pub fn int12(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT12) } #[doc = "Interrupt 13"] #[inline(always)] - pub fn int13(self) -> &'a mut W { + pub fn int13(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT13) } #[doc = "Interrupt 14"] #[inline(always)] - pub fn int14(self) -> &'a mut W { + pub fn int14(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT14) } #[doc = "Interrupt 15"] #[inline(always)] - pub fn int15(self) -> &'a mut W { + pub fn int15(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT15) } #[doc = "Interrupt 16"] #[inline(always)] - pub fn int16(self) -> &'a mut W { + pub fn int16(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT16) } #[doc = "Interrupt 17"] #[inline(always)] - pub fn int17(self) -> &'a mut W { + pub fn int17(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT17) } #[doc = "Interrupt 18"] #[inline(always)] - pub fn int18(self) -> &'a mut W { + pub fn int18(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT18) } #[doc = "Interrupt 19"] #[inline(always)] - pub fn int19(self) -> &'a mut W { + pub fn int19(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT19) } #[doc = "Interrupt 20"] #[inline(always)] - pub fn int20(self) -> &'a mut W { + pub fn int20(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT20) } #[doc = "Interrupt 21"] #[inline(always)] - pub fn int21(self) -> &'a mut W { + pub fn int21(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT21) } #[doc = "Interrupt 22"] #[inline(always)] - pub fn int22(self) -> &'a mut W { + pub fn int22(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT22) } #[doc = "Interrupt 23"] #[inline(always)] - pub fn int23(self) -> &'a mut W { + pub fn int23(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT23) } #[doc = "Interrupt 24"] #[inline(always)] - pub fn int24(self) -> &'a mut W { + pub fn int24(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT24) } #[doc = "Interrupt 25"] #[inline(always)] - pub fn int25(self) -> &'a mut W { + pub fn int25(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT25) } #[doc = "Interrupt 26"] #[inline(always)] - pub fn int26(self) -> &'a mut W { + pub fn int26(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT26) } #[doc = "Interrupt 27"] #[inline(always)] - pub fn int27(self) -> &'a mut W { + pub fn int27(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT27) } #[doc = "Interrupt 28"] #[inline(always)] - pub fn int28(self) -> &'a mut W { + pub fn int28(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT28) } #[doc = "Interrupt 29"] #[inline(always)] - pub fn int29(self) -> &'a mut W { + pub fn int29(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT29) } #[doc = "Interrupt 30"] #[inline(always)] - pub fn int30(self) -> &'a mut W { + pub fn int30(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT30) } #[doc = "Interrupt 31"] #[inline(always)] - pub fn int31(self) -> &'a mut W { + pub fn int31(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT31) } #[doc = "Interrupt 32"] #[inline(always)] - pub fn int32(self) -> &'a mut W { + pub fn int32(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT32) } #[doc = "Interrupt 33"] #[inline(always)] - pub fn int33(self) -> &'a mut W { + pub fn int33(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT33) } #[doc = "Interrupt 34"] #[inline(always)] - pub fn int34(self) -> &'a mut W { + pub fn int34(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT34) } #[doc = "Interrupt 35"] #[inline(always)] - pub fn int35(self) -> &'a mut W { + pub fn int35(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT35) } #[doc = "Interrupt 36"] #[inline(always)] - pub fn int36(self) -> &'a mut W { + pub fn int36(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT36) } #[doc = "Interrupt 37"] #[inline(always)] - pub fn int37(self) -> &'a mut W { + pub fn int37(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT37) } #[doc = "Interrupt 38"] #[inline(always)] - pub fn int38(self) -> &'a mut W { + pub fn int38(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT38) } #[doc = "Interrupt 39"] #[inline(always)] - pub fn int39(self) -> &'a mut W { + pub fn int39(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT39) } #[doc = "Interrupt 40"] #[inline(always)] - pub fn int40(self) -> &'a mut W { + pub fn int40(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT40) } #[doc = "Interrupt 41"] #[inline(always)] - pub fn int41(self) -> &'a mut W { + pub fn int41(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT41) } #[doc = "Interrupt 42"] #[inline(always)] - pub fn int42(self) -> &'a mut W { + pub fn int42(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT42) } #[doc = "Interrupt 43"] #[inline(always)] - pub fn int43(self) -> &'a mut W { + pub fn int43(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT43) } #[doc = "Interrupt 44"] #[inline(always)] - pub fn int44(self) -> &'a mut W { + pub fn int44(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT44) } #[doc = "Interrupt 45"] #[inline(always)] - pub fn int45(self) -> &'a mut W { + pub fn int45(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT45) } #[doc = "Interrupt 46"] #[inline(always)] - pub fn int46(self) -> &'a mut W { + pub fn int46(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT46) } #[doc = "Interrupt 47"] #[inline(always)] - pub fn int47(self) -> &'a mut W { + pub fn int47(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT47) } #[doc = "Interrupt 48"] #[inline(always)] - pub fn int48(self) -> &'a mut W { + pub fn int48(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT48) } #[doc = "Interrupt 49"] #[inline(always)] - pub fn int49(self) -> &'a mut W { + pub fn int49(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT49) } #[doc = "Interrupt 50"] #[inline(always)] - pub fn int50(self) -> &'a mut W { + pub fn int50(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT50) } #[doc = "Interrupt 51"] #[inline(always)] - pub fn int51(self) -> &'a mut W { + pub fn int51(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT51) } #[doc = "Interrupt 52"] #[inline(always)] - pub fn int52(self) -> &'a mut W { + pub fn int52(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT52) } #[doc = "Interrupt 53"] #[inline(always)] - pub fn int53(self) -> &'a mut W { + pub fn int53(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT53) } #[doc = "Interrupt 54"] #[inline(always)] - pub fn int54(self) -> &'a mut W { + pub fn int54(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT54) } #[doc = "Interrupt 55"] #[inline(always)] - pub fn int55(self) -> &'a mut W { + pub fn int55(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT55) } #[doc = "Interrupt 56"] #[inline(always)] - pub fn int56(self) -> &'a mut W { + pub fn int56(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT56) } #[doc = "Interrupt 57"] #[inline(always)] - pub fn int57(self) -> &'a mut W { + pub fn int57(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT57) } #[doc = "Interrupt 58"] #[inline(always)] - pub fn int58(self) -> &'a mut W { + pub fn int58(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT58) } #[doc = "Interrupt 59"] #[inline(always)] - pub fn int59(self) -> &'a mut W { + pub fn int59(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT59) } #[doc = "Interrupt 60"] #[inline(always)] - pub fn int60(self) -> &'a mut W { + pub fn int60(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT60) } #[doc = "Interrupt 61"] #[inline(always)] - pub fn int61(self) -> &'a mut W { + pub fn int61(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT61) } #[doc = "Interrupt 62"] #[inline(always)] - pub fn int62(self) -> &'a mut W { + pub fn int62(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT62) } #[doc = "Interrupt 63"] #[inline(always)] - pub fn int63(self) -> &'a mut W { + pub fn int63(self) -> &'a mut crate::W { self.variant(SOURCE_A::INT63) } #[doc = "ARMC Timer"] #[inline(always)] - pub fn timer(self) -> &'a mut W { + pub fn timer(self) -> &'a mut crate::W { self.variant(SOURCE_A::TIMER) } #[doc = "Mailbox"] #[inline(always)] - pub fn mailbox(self) -> &'a mut W { + pub fn mailbox(self) -> &'a mut crate::W { self.variant(SOURCE_A::MAILBOX) } #[doc = "Doorbell 0"] #[inline(always)] - pub fn doorbell0(self) -> &'a mut W { + pub fn doorbell0(self) -> &'a mut crate::W { self.variant(SOURCE_A::DOORBELL0) } #[doc = "Doorbell 1"] #[inline(always)] - pub fn doorbell1(self) -> &'a mut W { + pub fn doorbell1(self) -> &'a mut crate::W { self.variant(SOURCE_A::DOORBELL1) } #[doc = "VPU0 halted"] #[inline(always)] - pub fn vpu0_halted(self) -> &'a mut W { + pub fn vpu0_halted(self) -> &'a mut crate::W { self.variant(SOURCE_A::VPU0_HALTED) } #[doc = "VPU1 halted"] #[inline(always)] - pub fn vpu1_halted(self) -> &'a mut W { + pub fn vpu1_halted(self) -> &'a mut crate::W { self.variant(SOURCE_A::VPU1_HALTED) } #[doc = "ARM address error"] #[inline(always)] - pub fn arm_address_error(self) -> &'a mut W { + pub fn arm_address_error(self) -> &'a mut crate::W { self.variant(SOURCE_A::ARM_ADDRESS_ERROR) } #[doc = "ARM AXI error"] #[inline(always)] - pub fn arm_axi_error(self) -> &'a mut W { + pub fn arm_axi_error(self) -> &'a mut crate::W { self.variant(SOURCE_A::ARM_AXI_ERROR) } } #[doc = "Field `ENABLE` reader - FIQ Enable"] -pub type ENABLE_R = crate::BitReader; +pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - FIQ Enable"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIQ_CONTROL_SPEC, bool, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - FIQ Source"] #[inline(always)] @@ -1013,38 +987,52 @@ impl R { ENABLE_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIQ_CONTROL") + .field("enable", &format_args!("{}", self.enable().bit())) + .field("source", &format_args!("{}", self.source().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - FIQ Source"] #[inline(always)] #[must_use] - pub fn source(&mut self) -> SOURCE_W<0> { + pub fn source(&mut self) -> SOURCE_W { SOURCE_W::new(self) } #[doc = "Bit 7 - FIQ Enable"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<7> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "FIQ control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fiq_control](index.html) module"] +#[doc = "FIQ control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fiq_control::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fiq_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIQ_CONTROL_SPEC; impl crate::RegisterSpec for FIQ_CONTROL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fiq_control::R](R) reader structure"] -impl crate::Readable for FIQ_CONTROL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fiq_control::W](W) writer structure"] +#[doc = "`read()` method returns [`fiq_control::R`](R) reader structure"] +impl crate::Readable for FIQ_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fiq_control::W`](W) writer structure"] impl crate::Writable for FIQ_CONTROL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/lic/pending_1.rs b/crates/bcm2711-lpa/src/lic/pending_1.rs index 0dbe7c6..efe3f18 100644 --- a/crates/bcm2711-lpa/src/lic/pending_1.rs +++ b/crates/bcm2711-lpa/src/lic/pending_1.rs @@ -1,82 +1,69 @@ #[doc = "Register `PENDING_1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `INT0` reader - Interrupt 0"] -pub type INT0_R = crate::BitReader; +pub type INT0_R = crate::BitReader; #[doc = "Field `INT1` reader - Interrupt 1"] -pub type INT1_R = crate::BitReader; +pub type INT1_R = crate::BitReader; #[doc = "Field `INT2` reader - Interrupt 2"] -pub type INT2_R = crate::BitReader; +pub type INT2_R = crate::BitReader; #[doc = "Field `INT3` reader - Interrupt 3"] -pub type INT3_R = crate::BitReader; +pub type INT3_R = crate::BitReader; #[doc = "Field `INT4` reader - Interrupt 4"] -pub type INT4_R = crate::BitReader; +pub type INT4_R = crate::BitReader; #[doc = "Field `INT5` reader - Interrupt 5"] -pub type INT5_R = crate::BitReader; +pub type INT5_R = crate::BitReader; #[doc = "Field `INT6` reader - Interrupt 6"] -pub type INT6_R = crate::BitReader; +pub type INT6_R = crate::BitReader; #[doc = "Field `INT7` reader - Interrupt 7"] -pub type INT7_R = crate::BitReader; +pub type INT7_R = crate::BitReader; #[doc = "Field `INT8` reader - Interrupt 8"] -pub type INT8_R = crate::BitReader; +pub type INT8_R = crate::BitReader; #[doc = "Field `INT9` reader - Interrupt 9"] -pub type INT9_R = crate::BitReader; +pub type INT9_R = crate::BitReader; #[doc = "Field `INT10` reader - Interrupt 10"] -pub type INT10_R = crate::BitReader; +pub type INT10_R = crate::BitReader; #[doc = "Field `INT11` reader - Interrupt 11"] -pub type INT11_R = crate::BitReader; +pub type INT11_R = crate::BitReader; #[doc = "Field `INT12` reader - Interrupt 12"] -pub type INT12_R = crate::BitReader; +pub type INT12_R = crate::BitReader; #[doc = "Field `INT13` reader - Interrupt 13"] -pub type INT13_R = crate::BitReader; +pub type INT13_R = crate::BitReader; #[doc = "Field `INT14` reader - Interrupt 14"] -pub type INT14_R = crate::BitReader; +pub type INT14_R = crate::BitReader; #[doc = "Field `INT15` reader - Interrupt 15"] -pub type INT15_R = crate::BitReader; +pub type INT15_R = crate::BitReader; #[doc = "Field `INT16` reader - Interrupt 16"] -pub type INT16_R = crate::BitReader; +pub type INT16_R = crate::BitReader; #[doc = "Field `INT17` reader - Interrupt 17"] -pub type INT17_R = crate::BitReader; +pub type INT17_R = crate::BitReader; #[doc = "Field `INT18` reader - Interrupt 18"] -pub type INT18_R = crate::BitReader; +pub type INT18_R = crate::BitReader; #[doc = "Field `INT19` reader - Interrupt 19"] -pub type INT19_R = crate::BitReader; +pub type INT19_R = crate::BitReader; #[doc = "Field `INT20` reader - Interrupt 20"] -pub type INT20_R = crate::BitReader; +pub type INT20_R = crate::BitReader; #[doc = "Field `INT21` reader - Interrupt 21"] -pub type INT21_R = crate::BitReader; +pub type INT21_R = crate::BitReader; #[doc = "Field `INT22` reader - Interrupt 22"] -pub type INT22_R = crate::BitReader; +pub type INT22_R = crate::BitReader; #[doc = "Field `INT23` reader - Interrupt 23"] -pub type INT23_R = crate::BitReader; +pub type INT23_R = crate::BitReader; #[doc = "Field `INT24` reader - Interrupt 24"] -pub type INT24_R = crate::BitReader; +pub type INT24_R = crate::BitReader; #[doc = "Field `INT25` reader - Interrupt 25"] -pub type INT25_R = crate::BitReader; +pub type INT25_R = crate::BitReader; #[doc = "Field `INT26` reader - Interrupt 26"] -pub type INT26_R = crate::BitReader; +pub type INT26_R = crate::BitReader; #[doc = "Field `INT27` reader - Interrupt 27"] -pub type INT27_R = crate::BitReader; +pub type INT27_R = crate::BitReader; #[doc = "Field `INT28` reader - Interrupt 28"] -pub type INT28_R = crate::BitReader; +pub type INT28_R = crate::BitReader; #[doc = "Field `INT29` reader - Interrupt 29"] -pub type INT29_R = crate::BitReader; +pub type INT29_R = crate::BitReader; #[doc = "Field `INT30` reader - Interrupt 30"] -pub type INT30_R = crate::BitReader; +pub type INT30_R = crate::BitReader; #[doc = "Field `INT31` reader - Interrupt 31"] -pub type INT31_R = crate::BitReader; +pub type INT31_R = crate::BitReader; impl R { #[doc = "Bit 0 - Interrupt 0"] #[inline(always)] @@ -239,15 +226,56 @@ impl R { INT31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Pending state for interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending_1](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PENDING_1") + .field("int0", &format_args!("{}", self.int0().bit())) + .field("int1", &format_args!("{}", self.int1().bit())) + .field("int2", &format_args!("{}", self.int2().bit())) + .field("int3", &format_args!("{}", self.int3().bit())) + .field("int4", &format_args!("{}", self.int4().bit())) + .field("int5", &format_args!("{}", self.int5().bit())) + .field("int6", &format_args!("{}", self.int6().bit())) + .field("int7", &format_args!("{}", self.int7().bit())) + .field("int8", &format_args!("{}", self.int8().bit())) + .field("int9", &format_args!("{}", self.int9().bit())) + .field("int10", &format_args!("{}", self.int10().bit())) + .field("int11", &format_args!("{}", self.int11().bit())) + .field("int12", &format_args!("{}", self.int12().bit())) + .field("int13", &format_args!("{}", self.int13().bit())) + .field("int14", &format_args!("{}", self.int14().bit())) + .field("int15", &format_args!("{}", self.int15().bit())) + .field("int16", &format_args!("{}", self.int16().bit())) + .field("int17", &format_args!("{}", self.int17().bit())) + .field("int18", &format_args!("{}", self.int18().bit())) + .field("int19", &format_args!("{}", self.int19().bit())) + .field("int20", &format_args!("{}", self.int20().bit())) + .field("int21", &format_args!("{}", self.int21().bit())) + .field("int22", &format_args!("{}", self.int22().bit())) + .field("int23", &format_args!("{}", self.int23().bit())) + .field("int24", &format_args!("{}", self.int24().bit())) + .field("int25", &format_args!("{}", self.int25().bit())) + .field("int26", &format_args!("{}", self.int26().bit())) + .field("int27", &format_args!("{}", self.int27().bit())) + .field("int28", &format_args!("{}", self.int28().bit())) + .field("int29", &format_args!("{}", self.int29().bit())) + .field("int30", &format_args!("{}", self.int30().bit())) + .field("int31", &format_args!("{}", self.int31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Pending state for interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PENDING_1_SPEC; impl crate::RegisterSpec for PENDING_1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pending_1::R](R) reader structure"] -impl crate::Readable for PENDING_1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pending_1::R`](R) reader structure"] +impl crate::Readable for PENDING_1_SPEC {} #[doc = "`reset()` method sets PENDING_1 to value 0"] impl crate::Resettable for PENDING_1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/lic/pending_2.rs b/crates/bcm2711-lpa/src/lic/pending_2.rs index 6d8066c..44e3573 100644 --- a/crates/bcm2711-lpa/src/lic/pending_2.rs +++ b/crates/bcm2711-lpa/src/lic/pending_2.rs @@ -1,82 +1,69 @@ #[doc = "Register `PENDING_2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `INT32` reader - Interrupt 32"] -pub type INT32_R = crate::BitReader; +pub type INT32_R = crate::BitReader; #[doc = "Field `INT33` reader - Interrupt 33"] -pub type INT33_R = crate::BitReader; +pub type INT33_R = crate::BitReader; #[doc = "Field `INT34` reader - Interrupt 34"] -pub type INT34_R = crate::BitReader; +pub type INT34_R = crate::BitReader; #[doc = "Field `INT35` reader - Interrupt 35"] -pub type INT35_R = crate::BitReader; +pub type INT35_R = crate::BitReader; #[doc = "Field `INT36` reader - Interrupt 36"] -pub type INT36_R = crate::BitReader; +pub type INT36_R = crate::BitReader; #[doc = "Field `INT37` reader - Interrupt 37"] -pub type INT37_R = crate::BitReader; +pub type INT37_R = crate::BitReader; #[doc = "Field `INT38` reader - Interrupt 38"] -pub type INT38_R = crate::BitReader; +pub type INT38_R = crate::BitReader; #[doc = "Field `INT39` reader - Interrupt 39"] -pub type INT39_R = crate::BitReader; +pub type INT39_R = crate::BitReader; #[doc = "Field `INT40` reader - Interrupt 40"] -pub type INT40_R = crate::BitReader; +pub type INT40_R = crate::BitReader; #[doc = "Field `INT41` reader - Interrupt 41"] -pub type INT41_R = crate::BitReader; +pub type INT41_R = crate::BitReader; #[doc = "Field `INT42` reader - Interrupt 42"] -pub type INT42_R = crate::BitReader; +pub type INT42_R = crate::BitReader; #[doc = "Field `INT43` reader - Interrupt 43"] -pub type INT43_R = crate::BitReader; +pub type INT43_R = crate::BitReader; #[doc = "Field `INT44` reader - Interrupt 44"] -pub type INT44_R = crate::BitReader; +pub type INT44_R = crate::BitReader; #[doc = "Field `INT45` reader - Interrupt 45"] -pub type INT45_R = crate::BitReader; +pub type INT45_R = crate::BitReader; #[doc = "Field `INT46` reader - Interrupt 46"] -pub type INT46_R = crate::BitReader; +pub type INT46_R = crate::BitReader; #[doc = "Field `INT47` reader - Interrupt 47"] -pub type INT47_R = crate::BitReader; +pub type INT47_R = crate::BitReader; #[doc = "Field `INT48` reader - Interrupt 48"] -pub type INT48_R = crate::BitReader; +pub type INT48_R = crate::BitReader; #[doc = "Field `INT49` reader - Interrupt 49"] -pub type INT49_R = crate::BitReader; +pub type INT49_R = crate::BitReader; #[doc = "Field `INT50` reader - Interrupt 50"] -pub type INT50_R = crate::BitReader; +pub type INT50_R = crate::BitReader; #[doc = "Field `INT51` reader - Interrupt 51"] -pub type INT51_R = crate::BitReader; +pub type INT51_R = crate::BitReader; #[doc = "Field `INT52` reader - Interrupt 52"] -pub type INT52_R = crate::BitReader; +pub type INT52_R = crate::BitReader; #[doc = "Field `INT53` reader - Interrupt 53"] -pub type INT53_R = crate::BitReader; +pub type INT53_R = crate::BitReader; #[doc = "Field `INT54` reader - Interrupt 54"] -pub type INT54_R = crate::BitReader; +pub type INT54_R = crate::BitReader; #[doc = "Field `INT55` reader - Interrupt 55"] -pub type INT55_R = crate::BitReader; +pub type INT55_R = crate::BitReader; #[doc = "Field `INT56` reader - Interrupt 56"] -pub type INT56_R = crate::BitReader; +pub type INT56_R = crate::BitReader; #[doc = "Field `INT57` reader - Interrupt 57"] -pub type INT57_R = crate::BitReader; +pub type INT57_R = crate::BitReader; #[doc = "Field `INT58` reader - Interrupt 58"] -pub type INT58_R = crate::BitReader; +pub type INT58_R = crate::BitReader; #[doc = "Field `INT59` reader - Interrupt 59"] -pub type INT59_R = crate::BitReader; +pub type INT59_R = crate::BitReader; #[doc = "Field `INT60` reader - Interrupt 60"] -pub type INT60_R = crate::BitReader; +pub type INT60_R = crate::BitReader; #[doc = "Field `INT61` reader - Interrupt 61"] -pub type INT61_R = crate::BitReader; +pub type INT61_R = crate::BitReader; #[doc = "Field `INT62` reader - Interrupt 62"] -pub type INT62_R = crate::BitReader; +pub type INT62_R = crate::BitReader; #[doc = "Field `INT63` reader - Interrupt 63"] -pub type INT63_R = crate::BitReader; +pub type INT63_R = crate::BitReader; impl R { #[doc = "Bit 0 - Interrupt 32"] #[inline(always)] @@ -239,15 +226,56 @@ impl R { INT63_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Pending state for interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending_2](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PENDING_2") + .field("int32", &format_args!("{}", self.int32().bit())) + .field("int33", &format_args!("{}", self.int33().bit())) + .field("int34", &format_args!("{}", self.int34().bit())) + .field("int35", &format_args!("{}", self.int35().bit())) + .field("int36", &format_args!("{}", self.int36().bit())) + .field("int37", &format_args!("{}", self.int37().bit())) + .field("int38", &format_args!("{}", self.int38().bit())) + .field("int39", &format_args!("{}", self.int39().bit())) + .field("int40", &format_args!("{}", self.int40().bit())) + .field("int41", &format_args!("{}", self.int41().bit())) + .field("int42", &format_args!("{}", self.int42().bit())) + .field("int43", &format_args!("{}", self.int43().bit())) + .field("int44", &format_args!("{}", self.int44().bit())) + .field("int45", &format_args!("{}", self.int45().bit())) + .field("int46", &format_args!("{}", self.int46().bit())) + .field("int47", &format_args!("{}", self.int47().bit())) + .field("int48", &format_args!("{}", self.int48().bit())) + .field("int49", &format_args!("{}", self.int49().bit())) + .field("int50", &format_args!("{}", self.int50().bit())) + .field("int51", &format_args!("{}", self.int51().bit())) + .field("int52", &format_args!("{}", self.int52().bit())) + .field("int53", &format_args!("{}", self.int53().bit())) + .field("int54", &format_args!("{}", self.int54().bit())) + .field("int55", &format_args!("{}", self.int55().bit())) + .field("int56", &format_args!("{}", self.int56().bit())) + .field("int57", &format_args!("{}", self.int57().bit())) + .field("int58", &format_args!("{}", self.int58().bit())) + .field("int59", &format_args!("{}", self.int59().bit())) + .field("int60", &format_args!("{}", self.int60().bit())) + .field("int61", &format_args!("{}", self.int61().bit())) + .field("int62", &format_args!("{}", self.int62().bit())) + .field("int63", &format_args!("{}", self.int63().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Pending state for interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PENDING_2_SPEC; impl crate::RegisterSpec for PENDING_2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pending_2::R](R) reader structure"] -impl crate::Readable for PENDING_2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pending_2::R`](R) reader structure"] +impl crate::Readable for PENDING_2_SPEC {} #[doc = "`reset()` method sets PENDING_2 to value 0"] impl crate::Resettable for PENDING_2_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/pactl.rs b/crates/bcm2711-lpa/src/pactl.rs index 0c6b249..197aa4a 100644 --- a/crates/bcm2711-lpa/src/pactl.rs +++ b/crates/bcm2711-lpa/src/pactl.rs @@ -1,10 +1,12 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Interrupt status"] pub cs: CS, } -#[doc = "CS (rw) register accessor: an alias for `Reg`"] +#[doc = "CS (rw) register accessor: Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cs`] +module"] pub type CS = crate::Reg; #[doc = "Interrupt status"] pub mod cs; diff --git a/crates/bcm2711-lpa/src/pactl/cs.rs b/crates/bcm2711-lpa/src/pactl/cs.rs index f574fd9..859135b 100644 --- a/crates/bcm2711-lpa/src/pactl/cs.rs +++ b/crates/bcm2711-lpa/src/pactl/cs.rs @@ -1,119 +1,87 @@ #[doc = "Register `CS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SPI_0` reader - SPI0 interrupt active"] -pub type SPI_0_R = crate::BitReader; +pub type SPI_0_R = crate::BitReader; #[doc = "Field `SPI_0` writer - SPI0 interrupt active"] -pub type SPI_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type SPI_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_1` reader - SPI1 interrupt active"] -pub type SPI_1_R = crate::BitReader; +pub type SPI_1_R = crate::BitReader; #[doc = "Field `SPI_1` writer - SPI1 interrupt active"] -pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type SPI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_2` reader - SPI2 interrupt active"] -pub type SPI_2_R = crate::BitReader; +pub type SPI_2_R = crate::BitReader; #[doc = "Field `SPI_2` writer - SPI2 interrupt active"] -pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type SPI_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_3` reader - SPI3 interrupt active"] -pub type SPI_3_R = crate::BitReader; +pub type SPI_3_R = crate::BitReader; #[doc = "Field `SPI_3` writer - SPI3 interrupt active"] -pub type SPI_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type SPI_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_4` reader - SPI4 interrupt active"] -pub type SPI_4_R = crate::BitReader; +pub type SPI_4_R = crate::BitReader; #[doc = "Field `SPI_4` writer - SPI4 interrupt active"] -pub type SPI_4_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type SPI_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_5` reader - SPI5 interrupt active"] -pub type SPI_5_R = crate::BitReader; +pub type SPI_5_R = crate::BitReader; #[doc = "Field `SPI_5` writer - SPI5 interrupt active"] -pub type SPI_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type SPI_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_6` reader - SPI6 interrupt active"] -pub type SPI_6_R = crate::BitReader; +pub type SPI_6_R = crate::BitReader; #[doc = "Field `SPI_6` writer - SPI6 interrupt active"] -pub type SPI_6_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type SPI_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2C_0` reader - I2C0 interrupt active"] -pub type I2C_0_R = crate::BitReader; +pub type I2C_0_R = crate::BitReader; #[doc = "Field `I2C_0` writer - I2C0 interrupt active"] -pub type I2C_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type I2C_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2C_1` reader - I2C1 interrupt active"] -pub type I2C_1_R = crate::BitReader; +pub type I2C_1_R = crate::BitReader; #[doc = "Field `I2C_1` writer - I2C1 interrupt active"] -pub type I2C_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type I2C_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2C_2` reader - I2C2 interrupt active"] -pub type I2C_2_R = crate::BitReader; +pub type I2C_2_R = crate::BitReader; #[doc = "Field `I2C_2` writer - I2C2 interrupt active"] -pub type I2C_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type I2C_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2C_3` reader - I2C3 interrupt active"] -pub type I2C_3_R = crate::BitReader; +pub type I2C_3_R = crate::BitReader; #[doc = "Field `I2C_3` writer - I2C3 interrupt active"] -pub type I2C_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type I2C_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2C_4` reader - I2C4 interrupt active"] -pub type I2C_4_R = crate::BitReader; +pub type I2C_4_R = crate::BitReader; #[doc = "Field `I2C_4` writer - I2C4 interrupt active"] -pub type I2C_4_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type I2C_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2C_5` reader - I2C5 interrupt active"] -pub type I2C_5_R = crate::BitReader; +pub type I2C_5_R = crate::BitReader; #[doc = "Field `I2C_5` writer - I2C5 interrupt active"] -pub type I2C_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type I2C_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2C_6` reader - I2C6 interrupt active"] -pub type I2C_6_R = crate::BitReader; +pub type I2C_6_R = crate::BitReader; #[doc = "Field `I2C_6` writer - I2C6 interrupt active"] -pub type I2C_6_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type I2C_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2C_7` reader - I2C7 interrupt active"] -pub type I2C_7_R = crate::BitReader; +pub type I2C_7_R = crate::BitReader; #[doc = "Field `I2C_7` writer - I2C7 interrupt active"] -pub type I2C_7_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type I2C_7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UART_5` reader - UART5 interrupt active"] -pub type UART_5_R = crate::BitReader; +pub type UART_5_R = crate::BitReader; #[doc = "Field `UART_5` writer - UART5 interrupt active"] -pub type UART_5_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type UART_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UART_4` reader - UART4 interrupt active"] -pub type UART_4_R = crate::BitReader; +pub type UART_4_R = crate::BitReader; #[doc = "Field `UART_4` writer - UART4 interrupt active"] -pub type UART_4_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type UART_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UART_3` reader - UART3 interrupt active"] -pub type UART_3_R = crate::BitReader; +pub type UART_3_R = crate::BitReader; #[doc = "Field `UART_3` writer - UART3 interrupt active"] -pub type UART_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type UART_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UART_2` reader - UART2 interrupt active"] -pub type UART_2_R = crate::BitReader; +pub type UART_2_R = crate::BitReader; #[doc = "Field `UART_2` writer - UART2 interrupt active"] -pub type UART_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type UART_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UART_0` reader - UART0 interrupt active"] -pub type UART_0_R = crate::BitReader; +pub type UART_0_R = crate::BitReader; #[doc = "Field `UART_0` writer - UART0 interrupt active"] -pub type UART_0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type UART_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - SPI0 interrupt active"] #[inline(always)] @@ -216,146 +184,178 @@ impl R { UART_0_R::new(((self.bits >> 20) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CS") + .field("spi_0", &format_args!("{}", self.spi_0().bit())) + .field("spi_1", &format_args!("{}", self.spi_1().bit())) + .field("spi_2", &format_args!("{}", self.spi_2().bit())) + .field("spi_3", &format_args!("{}", self.spi_3().bit())) + .field("spi_4", &format_args!("{}", self.spi_4().bit())) + .field("spi_5", &format_args!("{}", self.spi_5().bit())) + .field("spi_6", &format_args!("{}", self.spi_6().bit())) + .field("i2c_0", &format_args!("{}", self.i2c_0().bit())) + .field("i2c_1", &format_args!("{}", self.i2c_1().bit())) + .field("i2c_2", &format_args!("{}", self.i2c_2().bit())) + .field("i2c_3", &format_args!("{}", self.i2c_3().bit())) + .field("i2c_4", &format_args!("{}", self.i2c_4().bit())) + .field("i2c_5", &format_args!("{}", self.i2c_5().bit())) + .field("i2c_6", &format_args!("{}", self.i2c_6().bit())) + .field("i2c_7", &format_args!("{}", self.i2c_7().bit())) + .field("uart_5", &format_args!("{}", self.uart_5().bit())) + .field("uart_4", &format_args!("{}", self.uart_4().bit())) + .field("uart_3", &format_args!("{}", self.uart_3().bit())) + .field("uart_2", &format_args!("{}", self.uart_2().bit())) + .field("uart_0", &format_args!("{}", self.uart_0().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - SPI0 interrupt active"] #[inline(always)] #[must_use] - pub fn spi_0(&mut self) -> SPI_0_W<0> { + pub fn spi_0(&mut self) -> SPI_0_W { SPI_0_W::new(self) } #[doc = "Bit 1 - SPI1 interrupt active"] #[inline(always)] #[must_use] - pub fn spi_1(&mut self) -> SPI_1_W<1> { + pub fn spi_1(&mut self) -> SPI_1_W { SPI_1_W::new(self) } #[doc = "Bit 2 - SPI2 interrupt active"] #[inline(always)] #[must_use] - pub fn spi_2(&mut self) -> SPI_2_W<2> { + pub fn spi_2(&mut self) -> SPI_2_W { SPI_2_W::new(self) } #[doc = "Bit 3 - SPI3 interrupt active"] #[inline(always)] #[must_use] - pub fn spi_3(&mut self) -> SPI_3_W<3> { + pub fn spi_3(&mut self) -> SPI_3_W { SPI_3_W::new(self) } #[doc = "Bit 4 - SPI4 interrupt active"] #[inline(always)] #[must_use] - pub fn spi_4(&mut self) -> SPI_4_W<4> { + pub fn spi_4(&mut self) -> SPI_4_W { SPI_4_W::new(self) } #[doc = "Bit 5 - SPI5 interrupt active"] #[inline(always)] #[must_use] - pub fn spi_5(&mut self) -> SPI_5_W<5> { + pub fn spi_5(&mut self) -> SPI_5_W { SPI_5_W::new(self) } #[doc = "Bit 6 - SPI6 interrupt active"] #[inline(always)] #[must_use] - pub fn spi_6(&mut self) -> SPI_6_W<6> { + pub fn spi_6(&mut self) -> SPI_6_W { SPI_6_W::new(self) } #[doc = "Bit 8 - I2C0 interrupt active"] #[inline(always)] #[must_use] - pub fn i2c_0(&mut self) -> I2C_0_W<8> { + pub fn i2c_0(&mut self) -> I2C_0_W { I2C_0_W::new(self) } #[doc = "Bit 9 - I2C1 interrupt active"] #[inline(always)] #[must_use] - pub fn i2c_1(&mut self) -> I2C_1_W<9> { + pub fn i2c_1(&mut self) -> I2C_1_W { I2C_1_W::new(self) } #[doc = "Bit 10 - I2C2 interrupt active"] #[inline(always)] #[must_use] - pub fn i2c_2(&mut self) -> I2C_2_W<10> { + pub fn i2c_2(&mut self) -> I2C_2_W { I2C_2_W::new(self) } #[doc = "Bit 11 - I2C3 interrupt active"] #[inline(always)] #[must_use] - pub fn i2c_3(&mut self) -> I2C_3_W<11> { + pub fn i2c_3(&mut self) -> I2C_3_W { I2C_3_W::new(self) } #[doc = "Bit 12 - I2C4 interrupt active"] #[inline(always)] #[must_use] - pub fn i2c_4(&mut self) -> I2C_4_W<12> { + pub fn i2c_4(&mut self) -> I2C_4_W { I2C_4_W::new(self) } #[doc = "Bit 13 - I2C5 interrupt active"] #[inline(always)] #[must_use] - pub fn i2c_5(&mut self) -> I2C_5_W<13> { + pub fn i2c_5(&mut self) -> I2C_5_W { I2C_5_W::new(self) } #[doc = "Bit 14 - I2C6 interrupt active"] #[inline(always)] #[must_use] - pub fn i2c_6(&mut self) -> I2C_6_W<14> { + pub fn i2c_6(&mut self) -> I2C_6_W { I2C_6_W::new(self) } #[doc = "Bit 15 - I2C7 interrupt active"] #[inline(always)] #[must_use] - pub fn i2c_7(&mut self) -> I2C_7_W<15> { + pub fn i2c_7(&mut self) -> I2C_7_W { I2C_7_W::new(self) } #[doc = "Bit 16 - UART5 interrupt active"] #[inline(always)] #[must_use] - pub fn uart_5(&mut self) -> UART_5_W<16> { + pub fn uart_5(&mut self) -> UART_5_W { UART_5_W::new(self) } #[doc = "Bit 17 - UART4 interrupt active"] #[inline(always)] #[must_use] - pub fn uart_4(&mut self) -> UART_4_W<17> { + pub fn uart_4(&mut self) -> UART_4_W { UART_4_W::new(self) } #[doc = "Bit 18 - UART3 interrupt active"] #[inline(always)] #[must_use] - pub fn uart_3(&mut self) -> UART_3_W<18> { + pub fn uart_3(&mut self) -> UART_3_W { UART_3_W::new(self) } #[doc = "Bit 19 - UART2 interrupt active"] #[inline(always)] #[must_use] - pub fn uart_2(&mut self) -> UART_2_W<19> { + pub fn uart_2(&mut self) -> UART_2_W { UART_2_W::new(self) } #[doc = "Bit 20 - UART0 interrupt active"] #[inline(always)] #[must_use] - pub fn uart_0(&mut self) -> UART_0_W<20> { + pub fn uart_0(&mut self) -> UART_0_W { UART_0_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +#[doc = "Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CS_SPEC; impl crate::RegisterSpec for CS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cs::R](R) reader structure"] -impl crate::Readable for CS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/pwm0.rs b/crates/bcm2711-lpa/src/pwm0.rs index 4270433..4306916 100644 --- a/crates/bcm2711-lpa/src/pwm0.rs +++ b/crates/bcm2711-lpa/src/pwm0.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control"] pub ctl: CTL, @@ -20,35 +21,43 @@ pub struct RegisterBlock { #[doc = "0x24 - Channel 2 data"] pub dat2: DAT2, } -#[doc = "CTL (rw) register accessor: an alias for `Reg`"] +#[doc = "CTL (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl`] +module"] pub type CTL = crate::Reg; #[doc = "Control"] pub mod ctl; -#[doc = "STA (rw) register accessor: an alias for `Reg`"] +#[doc = "STA (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sta`] +module"] pub type STA = crate::Reg; #[doc = "Status"] pub mod sta; -#[doc = "DMAC (rw) register accessor: an alias for `Reg`"] +#[doc = "DMAC (rw) register accessor: DMA control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmac::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmac::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac`] +module"] pub type DMAC = crate::Reg; #[doc = "DMA control"] pub mod dmac; -#[doc = "RNG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "RNG1 (rw) register accessor: Range for channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rng1`] +module"] pub type RNG1 = crate::Reg; #[doc = "Range for channel 1"] pub mod rng1; -#[doc = "DAT1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DAT1 (rw) register accessor: Channel 1 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dat1`] +module"] pub type DAT1 = crate::Reg; #[doc = "Channel 1 data"] pub mod dat1; -#[doc = "FIF1 (w) register accessor: an alias for `Reg`"] +#[doc = "FIF1 (w) register accessor: FIFO input\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fif1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fif1`] +module"] pub type FIF1 = crate::Reg; #[doc = "FIFO input"] pub mod fif1; -#[doc = "RNG2 (rw) register accessor: an alias for `Reg`"] +#[doc = "RNG2 (rw) register accessor: Range for channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rng2`] +module"] pub type RNG2 = crate::Reg; #[doc = "Range for channel 2"] pub mod rng2; -#[doc = "DAT2 (rw) register accessor: an alias for `Reg`"] +#[doc = "DAT2 (rw) register accessor: Channel 2 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dat2`] +module"] pub type DAT2 = crate::Reg; #[doc = "Channel 2 data"] pub mod dat2; diff --git a/crates/bcm2711-lpa/src/pwm0/ctl.rs b/crates/bcm2711-lpa/src/pwm0/ctl.rs index b41b326..d1b9d57 100644 --- a/crates/bcm2711-lpa/src/pwm0/ctl.rs +++ b/crates/bcm2711-lpa/src/pwm0/ctl.rs @@ -1,43 +1,11 @@ #[doc = "Register `CTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PWEN1` reader - Enable channel 1"] -pub type PWEN1_R = crate::BitReader; +pub type PWEN1_R = crate::BitReader; #[doc = "Field `PWEN1` writer - Enable channel 1"] -pub type PWEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type PWEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MODE1` reader - Channel 1 mode"] pub type MODE1_R = crate::BitReader; #[doc = "Channel 1 mode\n\nValue on reset: 0"] @@ -57,65 +25,68 @@ impl From for bool { impl MODE1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> MODE1_A { + pub const fn variant(&self) -> MODE1_A { match self.bits { false => MODE1_A::PWM, true => MODE1_A::SERIAL, } } - #[doc = "Checks if the value of the field is `PWM`"] + #[doc = "`0`"] #[inline(always)] pub fn is_pwm(&self) -> bool { *self == MODE1_A::PWM } - #[doc = "Checks if the value of the field is `SERIAL`"] + #[doc = "`1`"] #[inline(always)] pub fn is_serial(&self) -> bool { *self == MODE1_A::SERIAL } } #[doc = "Field `MODE1` writer - Channel 1 mode"] -pub type MODE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, MODE1_A, O>; -impl<'a, const O: u8> MODE1_W<'a, O> { +pub type MODE1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MODE1_A>; +impl<'a, REG, const O: u8> MODE1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn pwm(self) -> &'a mut W { + pub fn pwm(self) -> &'a mut crate::W { self.variant(MODE1_A::PWM) } #[doc = "`1`"] #[inline(always)] - pub fn serial(self) -> &'a mut W { + pub fn serial(self) -> &'a mut crate::W { self.variant(MODE1_A::SERIAL) } } #[doc = "Field `RPTL1` reader - Repeat last value from FIFO for channel 1"] -pub type RPTL1_R = crate::BitReader; +pub type RPTL1_R = crate::BitReader; #[doc = "Field `RPTL1` writer - Repeat last value from FIFO for channel 1"] -pub type RPTL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type RPTL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SBIT1` reader - State when not transmitting on channel 1"] -pub type SBIT1_R = crate::BitReader; +pub type SBIT1_R = crate::BitReader; #[doc = "Field `SBIT1` writer - State when not transmitting on channel 1"] -pub type SBIT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type SBIT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POLA1` reader - Channel 1 polarity inverted"] -pub type POLA1_R = crate::BitReader; +pub type POLA1_R = crate::BitReader; #[doc = "Field `POLA1` writer - Channel 1 polarity inverted"] -pub type POLA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type POLA1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USEF1` reader - Use FIFO for channel 1"] -pub type USEF1_R = crate::BitReader; +pub type USEF1_R = crate::BitReader; #[doc = "Field `USEF1` writer - Use FIFO for channel 1"] -pub type USEF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type USEF1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLRF1` reader - Clear FIFO"] -pub type CLRF1_R = crate::BitReader; +pub type CLRF1_R = crate::BitReader; #[doc = "Field `CLRF1` writer - Clear FIFO"] -pub type CLRF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type CLRF1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSEN1` reader - M/S mode for channel 1"] -pub type MSEN1_R = crate::BitReader; +pub type MSEN1_R = crate::BitReader; #[doc = "Field `MSEN1` writer - M/S mode for channel 1"] -pub type MSEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type MSEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWEN2` reader - Enable channel 2"] -pub type PWEN2_R = crate::BitReader; +pub type PWEN2_R = crate::BitReader; #[doc = "Field `PWEN2` writer - Enable channel 2"] -pub type PWEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type PWEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MODE2` reader - Channel 2 mode"] pub type MODE2_R = crate::BitReader; #[doc = "Channel 2 mode\n\nValue on reset: 0"] @@ -135,57 +106,60 @@ impl From for bool { impl MODE2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> MODE2_A { + pub const fn variant(&self) -> MODE2_A { match self.bits { false => MODE2_A::PWM, true => MODE2_A::SERIAL, } } - #[doc = "Checks if the value of the field is `PWM`"] + #[doc = "`0`"] #[inline(always)] pub fn is_pwm(&self) -> bool { *self == MODE2_A::PWM } - #[doc = "Checks if the value of the field is `SERIAL`"] + #[doc = "`1`"] #[inline(always)] pub fn is_serial(&self) -> bool { *self == MODE2_A::SERIAL } } #[doc = "Field `MODE2` writer - Channel 2 mode"] -pub type MODE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, MODE2_A, O>; -impl<'a, const O: u8> MODE2_W<'a, O> { +pub type MODE2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MODE2_A>; +impl<'a, REG, const O: u8> MODE2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn pwm(self) -> &'a mut W { + pub fn pwm(self) -> &'a mut crate::W { self.variant(MODE2_A::PWM) } #[doc = "`1`"] #[inline(always)] - pub fn serial(self) -> &'a mut W { + pub fn serial(self) -> &'a mut crate::W { self.variant(MODE2_A::SERIAL) } } #[doc = "Field `RPTL2` reader - Repeat last value from FIFO for channel 2"] -pub type RPTL2_R = crate::BitReader; +pub type RPTL2_R = crate::BitReader; #[doc = "Field `RPTL2` writer - Repeat last value from FIFO for channel 2"] -pub type RPTL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type RPTL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SBIT2` reader - State when not transmitting on channel 2"] -pub type SBIT2_R = crate::BitReader; +pub type SBIT2_R = crate::BitReader; #[doc = "Field `SBIT2` writer - State when not transmitting on channel 2"] -pub type SBIT2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type SBIT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POLA2` reader - Channel 2 polarity inverted"] -pub type POLA2_R = crate::BitReader; +pub type POLA2_R = crate::BitReader; #[doc = "Field `POLA2` writer - Channel 2 polarity inverted"] -pub type POLA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type POLA2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USEF2` reader - Use FIFO for channel 2"] -pub type USEF2_R = crate::BitReader; +pub type USEF2_R = crate::BitReader; #[doc = "Field `USEF2` writer - Use FIFO for channel 2"] -pub type USEF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type USEF2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSEN2` reader - M/S mode for channel 2"] -pub type MSEN2_R = crate::BitReader; +pub type MSEN2_R = crate::BitReader; #[doc = "Field `MSEN2` writer - M/S mode for channel 2"] -pub type MSEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type MSEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable channel 1"] #[inline(always)] @@ -263,116 +237,143 @@ impl R { MSEN2_R::new(((self.bits >> 15) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTL") + .field("msen2", &format_args!("{}", self.msen2().bit())) + .field("usef2", &format_args!("{}", self.usef2().bit())) + .field("pola2", &format_args!("{}", self.pola2().bit())) + .field("sbit2", &format_args!("{}", self.sbit2().bit())) + .field("rptl2", &format_args!("{}", self.rptl2().bit())) + .field("mode2", &format_args!("{}", self.mode2().bit())) + .field("pwen2", &format_args!("{}", self.pwen2().bit())) + .field("msen1", &format_args!("{}", self.msen1().bit())) + .field("clrf1", &format_args!("{}", self.clrf1().bit())) + .field("usef1", &format_args!("{}", self.usef1().bit())) + .field("pola1", &format_args!("{}", self.pola1().bit())) + .field("sbit1", &format_args!("{}", self.sbit1().bit())) + .field("rptl1", &format_args!("{}", self.rptl1().bit())) + .field("mode1", &format_args!("{}", self.mode1().bit())) + .field("pwen1", &format_args!("{}", self.pwen1().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable channel 1"] #[inline(always)] #[must_use] - pub fn pwen1(&mut self) -> PWEN1_W<0> { + pub fn pwen1(&mut self) -> PWEN1_W { PWEN1_W::new(self) } #[doc = "Bit 1 - Channel 1 mode"] #[inline(always)] #[must_use] - pub fn mode1(&mut self) -> MODE1_W<1> { + pub fn mode1(&mut self) -> MODE1_W { MODE1_W::new(self) } #[doc = "Bit 2 - Repeat last value from FIFO for channel 1"] #[inline(always)] #[must_use] - pub fn rptl1(&mut self) -> RPTL1_W<2> { + pub fn rptl1(&mut self) -> RPTL1_W { RPTL1_W::new(self) } #[doc = "Bit 3 - State when not transmitting on channel 1"] #[inline(always)] #[must_use] - pub fn sbit1(&mut self) -> SBIT1_W<3> { + pub fn sbit1(&mut self) -> SBIT1_W { SBIT1_W::new(self) } #[doc = "Bit 4 - Channel 1 polarity inverted"] #[inline(always)] #[must_use] - pub fn pola1(&mut self) -> POLA1_W<4> { + pub fn pola1(&mut self) -> POLA1_W { POLA1_W::new(self) } #[doc = "Bit 5 - Use FIFO for channel 1"] #[inline(always)] #[must_use] - pub fn usef1(&mut self) -> USEF1_W<5> { + pub fn usef1(&mut self) -> USEF1_W { USEF1_W::new(self) } #[doc = "Bit 6 - Clear FIFO"] #[inline(always)] #[must_use] - pub fn clrf1(&mut self) -> CLRF1_W<6> { + pub fn clrf1(&mut self) -> CLRF1_W { CLRF1_W::new(self) } #[doc = "Bit 7 - M/S mode for channel 1"] #[inline(always)] #[must_use] - pub fn msen1(&mut self) -> MSEN1_W<7> { + pub fn msen1(&mut self) -> MSEN1_W { MSEN1_W::new(self) } #[doc = "Bit 8 - Enable channel 2"] #[inline(always)] #[must_use] - pub fn pwen2(&mut self) -> PWEN2_W<8> { + pub fn pwen2(&mut self) -> PWEN2_W { PWEN2_W::new(self) } #[doc = "Bit 9 - Channel 2 mode"] #[inline(always)] #[must_use] - pub fn mode2(&mut self) -> MODE2_W<9> { + pub fn mode2(&mut self) -> MODE2_W { MODE2_W::new(self) } #[doc = "Bit 10 - Repeat last value from FIFO for channel 2"] #[inline(always)] #[must_use] - pub fn rptl2(&mut self) -> RPTL2_W<10> { + pub fn rptl2(&mut self) -> RPTL2_W { RPTL2_W::new(self) } #[doc = "Bit 11 - State when not transmitting on channel 2"] #[inline(always)] #[must_use] - pub fn sbit2(&mut self) -> SBIT2_W<11> { + pub fn sbit2(&mut self) -> SBIT2_W { SBIT2_W::new(self) } #[doc = "Bit 12 - Channel 2 polarity inverted"] #[inline(always)] #[must_use] - pub fn pola2(&mut self) -> POLA2_W<12> { + pub fn pola2(&mut self) -> POLA2_W { POLA2_W::new(self) } #[doc = "Bit 13 - Use FIFO for channel 2"] #[inline(always)] #[must_use] - pub fn usef2(&mut self) -> USEF2_W<13> { + pub fn usef2(&mut self) -> USEF2_W { USEF2_W::new(self) } #[doc = "Bit 15 - M/S mode for channel 2"] #[inline(always)] #[must_use] - pub fn msen2(&mut self) -> MSEN2_W<15> { + pub fn msen2(&mut self) -> MSEN2_W { MSEN2_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL_SPEC; impl crate::RegisterSpec for CTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctl::R](R) reader structure"] -impl crate::Readable for CTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctl::W](W) writer structure"] +#[doc = "`read()` method returns [`ctl::R`](R) reader structure"] +impl crate::Readable for CTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] impl crate::Writable for CTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/pwm0/dat1.rs b/crates/bcm2711-lpa/src/pwm0/dat1.rs index c197492..b70672a 100644 --- a/crates/bcm2711-lpa/src/pwm0/dat1.rs +++ b/crates/bcm2711-lpa/src/pwm0/dat1.rs @@ -1,59 +1,38 @@ #[doc = "Register `DAT1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DAT1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel 1 data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dat1](index.html) module"] +#[doc = "Channel 1 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DAT1_SPEC; impl crate::RegisterSpec for DAT1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dat1::R](R) reader structure"] -impl crate::Readable for DAT1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dat1::W](W) writer structure"] +#[doc = "`read()` method returns [`dat1::R`](R) reader structure"] +impl crate::Readable for DAT1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dat1::W`](W) writer structure"] impl crate::Writable for DAT1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/pwm0/dat2.rs b/crates/bcm2711-lpa/src/pwm0/dat2.rs index b9e07a3..00bb85f 100644 --- a/crates/bcm2711-lpa/src/pwm0/dat2.rs +++ b/crates/bcm2711-lpa/src/pwm0/dat2.rs @@ -1,59 +1,38 @@ #[doc = "Register `DAT2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DAT2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel 2 data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dat2](index.html) module"] +#[doc = "Channel 2 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DAT2_SPEC; impl crate::RegisterSpec for DAT2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dat2::R](R) reader structure"] -impl crate::Readable for DAT2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dat2::W](W) writer structure"] +#[doc = "`read()` method returns [`dat2::R`](R) reader structure"] +impl crate::Readable for DAT2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dat2::W`](W) writer structure"] impl crate::Writable for DAT2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/pwm0/dmac.rs b/crates/bcm2711-lpa/src/pwm0/dmac.rs index b201822..d73ccfd 100644 --- a/crates/bcm2711-lpa/src/pwm0/dmac.rs +++ b/crates/bcm2711-lpa/src/pwm0/dmac.rs @@ -1,51 +1,19 @@ #[doc = "Register `DMAC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMAC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DREQ` reader - DMA threshold for DREQ signal"] -pub type DREQ_R = crate::FieldReader; +pub type DREQ_R = crate::FieldReader; #[doc = "Field `DREQ` writer - DMA threshold for DREQ signal"] -pub type DREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAC_SPEC, u8, u8, 8, O>; +pub type DREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PANIC` reader - DMA threshold for panic signal"] -pub type PANIC_R = crate::FieldReader; +pub type PANIC_R = crate::FieldReader; #[doc = "Field `PANIC` writer - DMA threshold for panic signal"] -pub type PANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAC_SPEC, u8, u8, 8, O>; +pub type PANIC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ENAB` reader - DMA enabled"] -pub type ENAB_R = crate::BitReader; +pub type ENAB_R = crate::BitReader; #[doc = "Field `ENAB` writer - DMA enabled"] -pub type ENAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAC_SPEC, bool, O>; +pub type ENAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:7 - DMA threshold for DREQ signal"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { ENAB_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC") + .field("enab", &format_args!("{}", self.enab().bit())) + .field("panic", &format_args!("{}", self.panic().bits())) + .field("dreq", &format_args!("{}", self.dreq().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DMA threshold for DREQ signal"] #[inline(always)] #[must_use] - pub fn dreq(&mut self) -> DREQ_W<0> { + pub fn dreq(&mut self) -> DREQ_W { DREQ_W::new(self) } #[doc = "Bits 8:15 - DMA threshold for panic signal"] #[inline(always)] #[must_use] - pub fn panic(&mut self) -> PANIC_W<8> { + pub fn panic(&mut self) -> PANIC_W { PANIC_W::new(self) } #[doc = "Bit 31 - DMA enabled"] #[inline(always)] #[must_use] - pub fn enab(&mut self) -> ENAB_W<31> { + pub fn enab(&mut self) -> ENAB_W { ENAB_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmac](index.html) module"] +#[doc = "DMA control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmac::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmac::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMAC_SPEC; impl crate::RegisterSpec for DMAC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dmac::R](R) reader structure"] -impl crate::Readable for DMAC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dmac::W](W) writer structure"] +#[doc = "`read()` method returns [`dmac::R`](R) reader structure"] +impl crate::Readable for DMAC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dmac::W`](W) writer structure"] impl crate::Writable for DMAC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/pwm0/fif1.rs b/crates/bcm2711-lpa/src/pwm0/fif1.rs index e786328..9cf85c2 100644 --- a/crates/bcm2711-lpa/src/pwm0/fif1.rs +++ b/crates/bcm2711-lpa/src/pwm0/fif1.rs @@ -1,40 +1,29 @@ #[doc = "Register `FIF1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +pub type W = crate::W; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "FIFO input\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fif1](index.html) module"] +#[doc = "FIFO input\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fif1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIF1_SPEC; impl crate::RegisterSpec for FIF1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [fif1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`fif1::W`](W) writer structure"] impl crate::Writable for FIF1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/pwm0/rng1.rs b/crates/bcm2711-lpa/src/pwm0/rng1.rs index b6f5446..2a01d68 100644 --- a/crates/bcm2711-lpa/src/pwm0/rng1.rs +++ b/crates/bcm2711-lpa/src/pwm0/rng1.rs @@ -1,59 +1,38 @@ #[doc = "Register `RNG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RNG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Range for channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rng1](index.html) module"] +#[doc = "Range for channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RNG1_SPEC; impl crate::RegisterSpec for RNG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rng1::R](R) reader structure"] -impl crate::Readable for RNG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rng1::W](W) writer structure"] +#[doc = "`read()` method returns [`rng1::R`](R) reader structure"] +impl crate::Readable for RNG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng1::W`](W) writer structure"] impl crate::Writable for RNG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/pwm0/rng2.rs b/crates/bcm2711-lpa/src/pwm0/rng2.rs index 0cc95d5..c7a9f74 100644 --- a/crates/bcm2711-lpa/src/pwm0/rng2.rs +++ b/crates/bcm2711-lpa/src/pwm0/rng2.rs @@ -1,59 +1,38 @@ #[doc = "Register `RNG2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RNG2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Range for channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rng2](index.html) module"] +#[doc = "Range for channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RNG2_SPEC; impl crate::RegisterSpec for RNG2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rng2::R](R) reader structure"] -impl crate::Readable for RNG2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rng2::W](W) writer structure"] +#[doc = "`read()` method returns [`rng2::R`](R) reader structure"] +impl crate::Readable for RNG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng2::W`](W) writer structure"] impl crate::Writable for RNG2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/pwm0/sta.rs b/crates/bcm2711-lpa/src/pwm0/sta.rs index f0b99b7..a0076a9 100644 --- a/crates/bcm2711-lpa/src/pwm0/sta.rs +++ b/crates/bcm2711-lpa/src/pwm0/sta.rs @@ -1,91 +1,59 @@ #[doc = "Register `STA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FULL1` reader - FIFO full"] -pub type FULL1_R = crate::BitReader; +pub type FULL1_R = crate::BitReader; #[doc = "Field `FULL1` writer - FIFO full"] -pub type FULL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type FULL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EMPT1` reader - FIFO empty"] -pub type EMPT1_R = crate::BitReader; +pub type EMPT1_R = crate::BitReader; #[doc = "Field `EMPT1` writer - FIFO empty"] -pub type EMPT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type EMPT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WERR1` reader - FIFO write error"] -pub type WERR1_R = crate::BitReader; +pub type WERR1_R = crate::BitReader; #[doc = "Field `WERR1` writer - FIFO write error"] -pub type WERR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type WERR1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RERR1` reader - FIFO read error"] -pub type RERR1_R = crate::BitReader; +pub type RERR1_R = crate::BitReader; #[doc = "Field `RERR1` writer - FIFO read error"] -pub type RERR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type RERR1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAPO1` reader - Channel 1 gap occurred"] -pub type GAPO1_R = crate::BitReader; +pub type GAPO1_R = crate::BitReader; #[doc = "Field `GAPO1` writer - Channel 1 gap occurred"] -pub type GAPO1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type GAPO1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAPO2` reader - Channel 2 gap occurred"] -pub type GAPO2_R = crate::BitReader; +pub type GAPO2_R = crate::BitReader; #[doc = "Field `GAPO2` writer - Channel 2 gap occurred"] -pub type GAPO2_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type GAPO2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAPO3` reader - Channel 3 gap occurred"] -pub type GAPO3_R = crate::BitReader; +pub type GAPO3_R = crate::BitReader; #[doc = "Field `GAPO3` writer - Channel 3 gap occurred"] -pub type GAPO3_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type GAPO3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAPO4` reader - Channel 4 gap occurred"] -pub type GAPO4_R = crate::BitReader; +pub type GAPO4_R = crate::BitReader; #[doc = "Field `GAPO4` writer - Channel 4 gap occurred"] -pub type GAPO4_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type GAPO4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BERR` reader - Bus error"] -pub type BERR_R = crate::BitReader; +pub type BERR_R = crate::BitReader; #[doc = "Field `BERR` writer - Bus error"] -pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type BERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STA1` reader - Channel 1 state"] -pub type STA1_R = crate::BitReader; +pub type STA1_R = crate::BitReader; #[doc = "Field `STA1` writer - Channel 1 state"] -pub type STA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type STA1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STA2` reader - Channel 2 state"] -pub type STA2_R = crate::BitReader; +pub type STA2_R = crate::BitReader; #[doc = "Field `STA2` writer - Channel 2 state"] -pub type STA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type STA2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STA3` reader - Channel 3 state"] -pub type STA3_R = crate::BitReader; +pub type STA3_R = crate::BitReader; #[doc = "Field `STA3` writer - Channel 3 state"] -pub type STA3_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type STA3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STA4` reader - Channel 4 state"] -pub type STA4_R = crate::BitReader; +pub type STA4_R = crate::BitReader; #[doc = "Field `STA4` writer - Channel 4 state"] -pub type STA4_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type STA4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - FIFO full"] #[inline(always)] @@ -153,104 +121,129 @@ impl R { STA4_R::new(((self.bits >> 12) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STA") + .field("sta4", &format_args!("{}", self.sta4().bit())) + .field("sta3", &format_args!("{}", self.sta3().bit())) + .field("sta2", &format_args!("{}", self.sta2().bit())) + .field("sta1", &format_args!("{}", self.sta1().bit())) + .field("berr", &format_args!("{}", self.berr().bit())) + .field("gapo4", &format_args!("{}", self.gapo4().bit())) + .field("gapo3", &format_args!("{}", self.gapo3().bit())) + .field("gapo2", &format_args!("{}", self.gapo2().bit())) + .field("gapo1", &format_args!("{}", self.gapo1().bit())) + .field("rerr1", &format_args!("{}", self.rerr1().bit())) + .field("werr1", &format_args!("{}", self.werr1().bit())) + .field("empt1", &format_args!("{}", self.empt1().bit())) + .field("full1", &format_args!("{}", self.full1().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - FIFO full"] #[inline(always)] #[must_use] - pub fn full1(&mut self) -> FULL1_W<0> { + pub fn full1(&mut self) -> FULL1_W { FULL1_W::new(self) } #[doc = "Bit 1 - FIFO empty"] #[inline(always)] #[must_use] - pub fn empt1(&mut self) -> EMPT1_W<1> { + pub fn empt1(&mut self) -> EMPT1_W { EMPT1_W::new(self) } #[doc = "Bit 2 - FIFO write error"] #[inline(always)] #[must_use] - pub fn werr1(&mut self) -> WERR1_W<2> { + pub fn werr1(&mut self) -> WERR1_W { WERR1_W::new(self) } #[doc = "Bit 3 - FIFO read error"] #[inline(always)] #[must_use] - pub fn rerr1(&mut self) -> RERR1_W<3> { + pub fn rerr1(&mut self) -> RERR1_W { RERR1_W::new(self) } #[doc = "Bit 4 - Channel 1 gap occurred"] #[inline(always)] #[must_use] - pub fn gapo1(&mut self) -> GAPO1_W<4> { + pub fn gapo1(&mut self) -> GAPO1_W { GAPO1_W::new(self) } #[doc = "Bit 5 - Channel 2 gap occurred"] #[inline(always)] #[must_use] - pub fn gapo2(&mut self) -> GAPO2_W<5> { + pub fn gapo2(&mut self) -> GAPO2_W { GAPO2_W::new(self) } #[doc = "Bit 6 - Channel 3 gap occurred"] #[inline(always)] #[must_use] - pub fn gapo3(&mut self) -> GAPO3_W<6> { + pub fn gapo3(&mut self) -> GAPO3_W { GAPO3_W::new(self) } #[doc = "Bit 7 - Channel 4 gap occurred"] #[inline(always)] #[must_use] - pub fn gapo4(&mut self) -> GAPO4_W<7> { + pub fn gapo4(&mut self) -> GAPO4_W { GAPO4_W::new(self) } #[doc = "Bit 8 - Bus error"] #[inline(always)] #[must_use] - pub fn berr(&mut self) -> BERR_W<8> { + pub fn berr(&mut self) -> BERR_W { BERR_W::new(self) } #[doc = "Bit 9 - Channel 1 state"] #[inline(always)] #[must_use] - pub fn sta1(&mut self) -> STA1_W<9> { + pub fn sta1(&mut self) -> STA1_W { STA1_W::new(self) } #[doc = "Bit 10 - Channel 2 state"] #[inline(always)] #[must_use] - pub fn sta2(&mut self) -> STA2_W<10> { + pub fn sta2(&mut self) -> STA2_W { STA2_W::new(self) } #[doc = "Bit 11 - Channel 3 state"] #[inline(always)] #[must_use] - pub fn sta3(&mut self) -> STA3_W<11> { + pub fn sta3(&mut self) -> STA3_W { STA3_W::new(self) } #[doc = "Bit 12 - Channel 4 state"] #[inline(always)] #[must_use] - pub fn sta4(&mut self) -> STA4_W<12> { + pub fn sta4(&mut self) -> STA4_W { STA4_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sta](index.html) module"] +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STA_SPEC; impl crate::RegisterSpec for STA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sta::R](R) reader structure"] -impl crate::Readable for STA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sta::W](W) writer structure"] +#[doc = "`read()` method returns [`sta::R`](R) reader structure"] +impl crate::Readable for STA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sta::W`](W) writer structure"] impl crate::Writable for STA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/spi0.rs b/crates/bcm2711-lpa/src/spi0.rs index 88737df..66be9b6 100644 --- a/crates/bcm2711-lpa/src/spi0.rs +++ b/crates/bcm2711-lpa/src/spi0.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control and Status"] pub cs: CS, @@ -14,27 +15,33 @@ pub struct RegisterBlock { #[doc = "0x14 - "] pub dc: DC, } -#[doc = "CS (rw) register accessor: an alias for `Reg`"] +#[doc = "CS (rw) register accessor: Control and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cs`] +module"] pub type CS = crate::Reg; #[doc = "Control and Status"] pub mod cs; -#[doc = "FIFO (rw) register accessor: an alias for `Reg`"] +#[doc = "FIFO (rw) register accessor: FIFO access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`] +module"] pub type FIFO = crate::Reg; #[doc = "FIFO access"] pub mod fifo; -#[doc = "CLK (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK (rw) register accessor: Clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk`] +module"] pub type CLK = crate::Reg; #[doc = "Clock divider"] pub mod clk; -#[doc = "DLEN (rw) register accessor: an alias for `Reg`"] +#[doc = "DLEN (rw) register accessor: Data length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlen`] +module"] pub type DLEN = crate::Reg; #[doc = "Data length"] pub mod dlen; -#[doc = "LTOH (rw) register accessor: an alias for `Reg`"] +#[doc = "LTOH (rw) register accessor: LoSSI output hold delay\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ltoh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ltoh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ltoh`] +module"] pub type LTOH = crate::Reg; #[doc = "LoSSI output hold delay"] pub mod ltoh; -#[doc = "DC (rw) register accessor: an alias for `Reg`"] +#[doc = "DC (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc`] +module"] pub type DC = crate::Reg; #[doc = ""] pub mod dc; diff --git a/crates/bcm2711-lpa/src/spi0/clk.rs b/crates/bcm2711-lpa/src/spi0/clk.rs index ef3272e..54ce877 100644 --- a/crates/bcm2711-lpa/src/spi0/clk.rs +++ b/crates/bcm2711-lpa/src/spi0/clk.rs @@ -1,43 +1,11 @@ #[doc = "Register `CLK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CDIV` reader - Clock divider"] -pub type CDIV_R = crate::FieldReader; +pub type CDIV_R = crate::FieldReader; #[doc = "Field `CDIV` writer - Clock divider"] -pub type CDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_SPEC, u16, u16, 16, O>; +pub type CDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Clock divider"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { CDIV_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK") + .field("cdiv", &format_args!("{}", self.cdiv().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Clock divider"] #[inline(always)] #[must_use] - pub fn cdiv(&mut self) -> CDIV_W<0> { + pub fn cdiv(&mut self) -> CDIV_W { CDIV_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk](index.html) module"] +#[doc = "Clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_SPEC; impl crate::RegisterSpec for CLK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk::R](R) reader structure"] -impl crate::Readable for CLK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk::W](W) writer structure"] +#[doc = "`read()` method returns [`clk::R`](R) reader structure"] +impl crate::Readable for CLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk::W`](W) writer structure"] impl crate::Writable for CLK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/spi0/cs.rs b/crates/bcm2711-lpa/src/spi0/cs.rs index 50227aa..06511e6 100644 --- a/crates/bcm2711-lpa/src/spi0/cs.rs +++ b/crates/bcm2711-lpa/src/spi0/cs.rs @@ -1,53 +1,21 @@ #[doc = "Register `CS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CS` reader - Chip select"] -pub type CS_R = crate::FieldReader; +pub type CS_R = crate::FieldReader; #[doc = "Field `CS` writer - Chip select"] -pub type CS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, u8, 2, O>; +pub type CS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `CPHA` reader - Clock phase"] -pub type CPHA_R = crate::BitReader; +pub type CPHA_R = crate::BitReader; #[doc = "Field `CPHA` writer - Clock phase"] -pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CPHA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPOL` reader - Clock polarity"] -pub type CPOL_R = crate::BitReader; +pub type CPOL_R = crate::BitReader; #[doc = "Field `CPOL` writer - Clock polarity"] -pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLEAR` reader - Clear the FIFO(s)"] -pub type CLEAR_R = crate::FieldReader; +pub type CLEAR_R = crate::FieldReader; #[doc = "Clear the FIFO(s)\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -65,10 +33,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for CLEAR_A { + type Ux = u8; +} impl CLEAR_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 1 => Some(CLEAR_A::TX), 2 => Some(CLEAR_A::RX), @@ -76,111 +47,115 @@ impl CLEAR_R { _ => None, } } - #[doc = "Checks if the value of the field is `TX`"] + #[doc = "`1`"] #[inline(always)] pub fn is_tx(&self) -> bool { *self == CLEAR_A::TX } - #[doc = "Checks if the value of the field is `RX`"] + #[doc = "`10`"] #[inline(always)] pub fn is_rx(&self) -> bool { *self == CLEAR_A::RX } - #[doc = "Checks if the value of the field is `BOTH`"] + #[doc = "`11`"] #[inline(always)] pub fn is_both(&self) -> bool { *self == CLEAR_A::BOTH } } #[doc = "Field `CLEAR` writer - Clear the FIFO(s)"] -pub type CLEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, CLEAR_A, 2, O>; -impl<'a, const O: u8> CLEAR_W<'a, O> { +pub type CLEAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, CLEAR_A>; +impl<'a, REG, const O: u8> CLEAR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1`"] #[inline(always)] - pub fn tx(self) -> &'a mut W { + pub fn tx(self) -> &'a mut crate::W { self.variant(CLEAR_A::TX) } #[doc = "`10`"] #[inline(always)] - pub fn rx(self) -> &'a mut W { + pub fn rx(self) -> &'a mut crate::W { self.variant(CLEAR_A::RX) } #[doc = "`11`"] #[inline(always)] - pub fn both(self) -> &'a mut W { + pub fn both(self) -> &'a mut crate::W { self.variant(CLEAR_A::BOTH) } } #[doc = "Field `CSPOL` reader - Chip select polarity"] -pub type CSPOL_R = crate::BitReader; +pub type CSPOL_R = crate::BitReader; #[doc = "Field `CSPOL` writer - Chip select polarity"] -pub type CSPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CSPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TA` reader - Transfer active"] -pub type TA_R = crate::BitReader; +pub type TA_R = crate::BitReader; #[doc = "Field `TA` writer - Transfer active"] -pub type TA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type TA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMAEN` reader - Enable DMA"] -pub type DMAEN_R = crate::BitReader; +pub type DMAEN_R = crate::BitReader; #[doc = "Field `DMAEN` writer - Enable DMA"] -pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type DMAEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTD` reader - Interrupt on done"] -pub type INTD_R = crate::BitReader; +pub type INTD_R = crate::BitReader; #[doc = "Field `INTD` writer - Interrupt on done"] -pub type INTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type INTD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTR` reader - Interrupt on RX"] -pub type INTR_R = crate::BitReader; +pub type INTR_R = crate::BitReader; #[doc = "Field `INTR` writer - Interrupt on RX"] -pub type INTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type INTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ADCS` reader - Automatically deassert chip select"] -pub type ADCS_R = crate::BitReader; +pub type ADCS_R = crate::BitReader; #[doc = "Field `ADCS` writer - Automatically deassert chip select"] -pub type ADCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type ADCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN` reader - Read enable"] -pub type REN_R = crate::BitReader; +pub type REN_R = crate::BitReader; #[doc = "Field `REN` writer - Read enable"] -pub type REN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type REN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN` reader - LoSSI enable"] -pub type LEN_R = crate::BitReader; +pub type LEN_R = crate::BitReader; #[doc = "Field `LEN` writer - LoSSI enable"] -pub type LEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type LEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LMONO` reader - "] -pub type LMONO_R = crate::BitReader; +pub type LMONO_R = crate::BitReader; #[doc = "Field `LMONO` writer - "] -pub type LMONO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type LMONO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TE_EN` reader - "] -pub type TE_EN_R = crate::BitReader; +pub type TE_EN_R = crate::BitReader; #[doc = "Field `TE_EN` writer - "] -pub type TE_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type TE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DONE` reader - Transfer is done"] -pub type DONE_R = crate::BitReader; +pub type DONE_R = crate::BitReader; #[doc = "Field `RXD` reader - RX FIFO contains data"] -pub type RXD_R = crate::BitReader; +pub type RXD_R = crate::BitReader; #[doc = "Field `TXD` reader - TX FIFO can accept data"] -pub type TXD_R = crate::BitReader; +pub type TXD_R = crate::BitReader; #[doc = "Field `RXR` reader - RX FIFO has data to be read"] -pub type RXR_R = crate::BitReader; +pub type RXR_R = crate::BitReader; #[doc = "Field `RXF` reader - RX FIFO full"] -pub type RXF_R = crate::BitReader; +pub type RXF_R = crate::BitReader; #[doc = "Field `CSPOL0` reader - Chip select 0 polarity"] -pub type CSPOL0_R = crate::BitReader; +pub type CSPOL0_R = crate::BitReader; #[doc = "Field `CSPOL0` writer - Chip select 0 polarity"] -pub type CSPOL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CSPOL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSPOL1` reader - Chip select 1 polarity"] -pub type CSPOL1_R = crate::BitReader; +pub type CSPOL1_R = crate::BitReader; #[doc = "Field `CSPOL1` writer - Chip select 1 polarity"] -pub type CSPOL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CSPOL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSPOL2` reader - Chip select 2 polarity"] -pub type CSPOL2_R = crate::BitReader; +pub type CSPOL2_R = crate::BitReader; #[doc = "Field `CSPOL2` writer - Chip select 2 polarity"] -pub type CSPOL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CSPOL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_LEN` reader - Enable DMA in LoSSI mode"] -pub type DMA_LEN_R = crate::BitReader; +pub type DMA_LEN_R = crate::BitReader; #[doc = "Field `DMA_LEN` writer - Enable DMA in LoSSI mode"] -pub type DMA_LEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type DMA_LEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN_LONG` reader - Enable long data word in LoSSI mode"] -pub type LEN_LONG_R = crate::BitReader; +pub type LEN_LONG_R = crate::BitReader; #[doc = "Field `LEN_LONG` writer - Enable long data word in LoSSI mode"] -pub type LEN_LONG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type LEN_LONG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:1 - Chip select"] #[inline(always)] @@ -303,140 +278,176 @@ impl R { LEN_LONG_R::new(((self.bits >> 25) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CS") + .field("len_long", &format_args!("{}", self.len_long().bit())) + .field("dma_len", &format_args!("{}", self.dma_len().bit())) + .field("cspol2", &format_args!("{}", self.cspol2().bit())) + .field("cspol1", &format_args!("{}", self.cspol1().bit())) + .field("cspol0", &format_args!("{}", self.cspol0().bit())) + .field("rxf", &format_args!("{}", self.rxf().bit())) + .field("rxr", &format_args!("{}", self.rxr().bit())) + .field("txd", &format_args!("{}", self.txd().bit())) + .field("rxd", &format_args!("{}", self.rxd().bit())) + .field("done", &format_args!("{}", self.done().bit())) + .field("te_en", &format_args!("{}", self.te_en().bit())) + .field("lmono", &format_args!("{}", self.lmono().bit())) + .field("len", &format_args!("{}", self.len().bit())) + .field("ren", &format_args!("{}", self.ren().bit())) + .field("adcs", &format_args!("{}", self.adcs().bit())) + .field("intr", &format_args!("{}", self.intr().bit())) + .field("intd", &format_args!("{}", self.intd().bit())) + .field("dmaen", &format_args!("{}", self.dmaen().bit())) + .field("ta", &format_args!("{}", self.ta().bit())) + .field("cspol", &format_args!("{}", self.cspol().bit())) + .field("clear", &format_args!("{}", self.clear().bits())) + .field("cpol", &format_args!("{}", self.cpol().bit())) + .field("cpha", &format_args!("{}", self.cpha().bit())) + .field("cs", &format_args!("{}", self.cs().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Chip select"] #[inline(always)] #[must_use] - pub fn cs(&mut self) -> CS_W<0> { + pub fn cs(&mut self) -> CS_W { CS_W::new(self) } #[doc = "Bit 2 - Clock phase"] #[inline(always)] #[must_use] - pub fn cpha(&mut self) -> CPHA_W<2> { + pub fn cpha(&mut self) -> CPHA_W { CPHA_W::new(self) } #[doc = "Bit 3 - Clock polarity"] #[inline(always)] #[must_use] - pub fn cpol(&mut self) -> CPOL_W<3> { + pub fn cpol(&mut self) -> CPOL_W { CPOL_W::new(self) } #[doc = "Bits 4:5 - Clear the FIFO(s)"] #[inline(always)] #[must_use] - pub fn clear(&mut self) -> CLEAR_W<4> { + pub fn clear(&mut self) -> CLEAR_W { CLEAR_W::new(self) } #[doc = "Bit 6 - Chip select polarity"] #[inline(always)] #[must_use] - pub fn cspol(&mut self) -> CSPOL_W<6> { + pub fn cspol(&mut self) -> CSPOL_W { CSPOL_W::new(self) } #[doc = "Bit 7 - Transfer active"] #[inline(always)] #[must_use] - pub fn ta(&mut self) -> TA_W<7> { + pub fn ta(&mut self) -> TA_W { TA_W::new(self) } #[doc = "Bit 8 - Enable DMA"] #[inline(always)] #[must_use] - pub fn dmaen(&mut self) -> DMAEN_W<8> { + pub fn dmaen(&mut self) -> DMAEN_W { DMAEN_W::new(self) } #[doc = "Bit 9 - Interrupt on done"] #[inline(always)] #[must_use] - pub fn intd(&mut self) -> INTD_W<9> { + pub fn intd(&mut self) -> INTD_W { INTD_W::new(self) } #[doc = "Bit 10 - Interrupt on RX"] #[inline(always)] #[must_use] - pub fn intr(&mut self) -> INTR_W<10> { + pub fn intr(&mut self) -> INTR_W { INTR_W::new(self) } #[doc = "Bit 11 - Automatically deassert chip select"] #[inline(always)] #[must_use] - pub fn adcs(&mut self) -> ADCS_W<11> { + pub fn adcs(&mut self) -> ADCS_W { ADCS_W::new(self) } #[doc = "Bit 12 - Read enable"] #[inline(always)] #[must_use] - pub fn ren(&mut self) -> REN_W<12> { + pub fn ren(&mut self) -> REN_W { REN_W::new(self) } #[doc = "Bit 13 - LoSSI enable"] #[inline(always)] #[must_use] - pub fn len(&mut self) -> LEN_W<13> { + pub fn len(&mut self) -> LEN_W { LEN_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn lmono(&mut self) -> LMONO_W<14> { + pub fn lmono(&mut self) -> LMONO_W { LMONO_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn te_en(&mut self) -> TE_EN_W<15> { + pub fn te_en(&mut self) -> TE_EN_W { TE_EN_W::new(self) } #[doc = "Bit 21 - Chip select 0 polarity"] #[inline(always)] #[must_use] - pub fn cspol0(&mut self) -> CSPOL0_W<21> { + pub fn cspol0(&mut self) -> CSPOL0_W { CSPOL0_W::new(self) } #[doc = "Bit 22 - Chip select 1 polarity"] #[inline(always)] #[must_use] - pub fn cspol1(&mut self) -> CSPOL1_W<22> { + pub fn cspol1(&mut self) -> CSPOL1_W { CSPOL1_W::new(self) } #[doc = "Bit 23 - Chip select 2 polarity"] #[inline(always)] #[must_use] - pub fn cspol2(&mut self) -> CSPOL2_W<23> { + pub fn cspol2(&mut self) -> CSPOL2_W { CSPOL2_W::new(self) } #[doc = "Bit 24 - Enable DMA in LoSSI mode"] #[inline(always)] #[must_use] - pub fn dma_len(&mut self) -> DMA_LEN_W<24> { + pub fn dma_len(&mut self) -> DMA_LEN_W { DMA_LEN_W::new(self) } #[doc = "Bit 25 - Enable long data word in LoSSI mode"] #[inline(always)] #[must_use] - pub fn len_long(&mut self) -> LEN_LONG_W<25> { + pub fn len_long(&mut self) -> LEN_LONG_W { LEN_LONG_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control and Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +#[doc = "Control and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CS_SPEC; impl crate::RegisterSpec for CS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cs::R](R) reader structure"] -impl crate::Readable for CS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/spi0/dc.rs b/crates/bcm2711-lpa/src/spi0/dc.rs index 281dd71..23813da 100644 --- a/crates/bcm2711-lpa/src/spi0/dc.rs +++ b/crates/bcm2711-lpa/src/spi0/dc.rs @@ -1,55 +1,23 @@ #[doc = "Register `DC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TDREQ` reader - DMA Write request threshold"] -pub type TDREQ_R = crate::FieldReader; +pub type TDREQ_R = crate::FieldReader; #[doc = "Field `TDREQ` writer - DMA Write request threshold"] -pub type TDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +pub type TDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `TPANIC` reader - DMA write panic threshold"] -pub type TPANIC_R = crate::FieldReader; +pub type TPANIC_R = crate::FieldReader; #[doc = "Field `TPANIC` writer - DMA write panic threshold"] -pub type TPANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +pub type TPANIC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `RDREQ` reader - DMA read request threshold"] -pub type RDREQ_R = crate::FieldReader; +pub type RDREQ_R = crate::FieldReader; #[doc = "Field `RDREQ` writer - DMA read request threshold"] -pub type RDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +pub type RDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `RPANIC` reader - DMA read panic threshold"] -pub type RPANIC_R = crate::FieldReader; +pub type RPANIC_R = crate::FieldReader; #[doc = "Field `RPANIC` writer - DMA read panic threshold"] -pub type RPANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +pub type RPANIC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - DMA Write request threshold"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { RPANIC_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DC") + .field("rpanic", &format_args!("{}", self.rpanic().bits())) + .field("rdreq", &format_args!("{}", self.rdreq().bits())) + .field("tpanic", &format_args!("{}", self.tpanic().bits())) + .field("tdreq", &format_args!("{}", self.tdreq().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DMA Write request threshold"] #[inline(always)] #[must_use] - pub fn tdreq(&mut self) -> TDREQ_W<0> { + pub fn tdreq(&mut self) -> TDREQ_W { TDREQ_W::new(self) } #[doc = "Bits 8:15 - DMA write panic threshold"] #[inline(always)] #[must_use] - pub fn tpanic(&mut self) -> TPANIC_W<8> { + pub fn tpanic(&mut self) -> TPANIC_W { TPANIC_W::new(self) } #[doc = "Bits 16:23 - DMA read request threshold"] #[inline(always)] #[must_use] - pub fn rdreq(&mut self) -> RDREQ_W<16> { + pub fn rdreq(&mut self) -> RDREQ_W { RDREQ_W::new(self) } #[doc = "Bits 24:31 - DMA read panic threshold"] #[inline(always)] #[must_use] - pub fn rpanic(&mut self) -> RPANIC_W<24> { + pub fn rpanic(&mut self) -> RPANIC_W { RPANIC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dc](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DC_SPEC; impl crate::RegisterSpec for DC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dc::R](R) reader structure"] -impl crate::Readable for DC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dc::W](W) writer structure"] +#[doc = "`read()` method returns [`dc::R`](R) reader structure"] +impl crate::Readable for DC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dc::W`](W) writer structure"] impl crate::Writable for DC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/spi0/dlen.rs b/crates/bcm2711-lpa/src/spi0/dlen.rs index 25e2771..5c7bb83 100644 --- a/crates/bcm2711-lpa/src/spi0/dlen.rs +++ b/crates/bcm2711-lpa/src/spi0/dlen.rs @@ -1,43 +1,11 @@ #[doc = "Register `DLEN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DLEN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DLEN` reader - Data length"] -pub type DLEN_R = crate::FieldReader; +pub type DLEN_R = crate::FieldReader; #[doc = "Field `DLEN` writer - Data length"] -pub type DLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLEN_SPEC, u16, u16, 16, O>; +pub type DLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Data length"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DLEN_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DLEN") + .field("dlen", &format_args!("{}", self.dlen().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Data length"] #[inline(always)] #[must_use] - pub fn dlen(&mut self) -> DLEN_W<0> { + pub fn dlen(&mut self) -> DLEN_W { DLEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlen](index.html) module"] +#[doc = "Data length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DLEN_SPEC; impl crate::RegisterSpec for DLEN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dlen::R](R) reader structure"] -impl crate::Readable for DLEN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dlen::W](W) writer structure"] +#[doc = "`read()` method returns [`dlen::R`](R) reader structure"] +impl crate::Readable for DLEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dlen::W`](W) writer structure"] impl crate::Writable for DLEN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/spi0/fifo.rs b/crates/bcm2711-lpa/src/spi0/fifo.rs index 46d2ece..937c27b 100644 --- a/crates/bcm2711-lpa/src/spi0/fifo.rs +++ b/crates/bcm2711-lpa/src/spi0/fifo.rs @@ -1,43 +1,11 @@ #[doc = "Register `FIFO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FIFO` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - Data"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - Data"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u32, u32, 32, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Data"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - Data"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "FIFO access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"] +#[doc = "FIFO access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_SPEC; impl crate::RegisterSpec for FIFO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fifo::R](R) reader structure"] -impl crate::Readable for FIFO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"] +#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] +impl crate::Readable for FIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"] impl crate::Writable for FIFO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/spi0/ltoh.rs b/crates/bcm2711-lpa/src/spi0/ltoh.rs index 5d0ab3f..15d66d8 100644 --- a/crates/bcm2711-lpa/src/spi0/ltoh.rs +++ b/crates/bcm2711-lpa/src/spi0/ltoh.rs @@ -1,43 +1,11 @@ #[doc = "Register `LTOH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LTOH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TOH` reader - Output hold delay"] -pub type TOH_R = crate::FieldReader; +pub type TOH_R = crate::FieldReader; #[doc = "Field `TOH` writer - Output hold delay"] -pub type TOH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LTOH_SPEC, u8, u8, 4, O>; +pub type TOH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - Output hold delay"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { TOH_R::new((self.bits & 0x0f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LTOH") + .field("toh", &format_args!("{}", self.toh().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:3 - Output hold delay"] #[inline(always)] #[must_use] - pub fn toh(&mut self) -> TOH_W<0> { + pub fn toh(&mut self) -> TOH_W { TOH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LoSSI output hold delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ltoh](index.html) module"] +#[doc = "LoSSI output hold delay\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ltoh::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ltoh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LTOH_SPEC; impl crate::RegisterSpec for LTOH_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ltoh::R](R) reader structure"] -impl crate::Readable for LTOH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ltoh::W](W) writer structure"] +#[doc = "`read()` method returns [`ltoh::R`](R) reader structure"] +impl crate::Readable for LTOH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ltoh::W`](W) writer structure"] impl crate::Writable for LTOH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/spi1.rs b/crates/bcm2711-lpa/src/spi1.rs index 1547fcc..0031aa9 100644 --- a/crates/bcm2711-lpa/src/spi1.rs +++ b/crates/bcm2711-lpa/src/spi1.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control 0"] pub cntl0: CNTL0, @@ -14,27 +15,33 @@ pub struct RegisterBlock { #[doc = "0x20..0x30 - Writing to the FIFO will maintain CS at the end of the access"] pub txhold: [TXHOLD; 4], } -#[doc = "CNTL0 (rw) register accessor: an alias for `Reg`"] +#[doc = "CNTL0 (rw) register accessor: Control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntl0`] +module"] pub type CNTL0 = crate::Reg; #[doc = "Control 0"] pub mod cntl0; -#[doc = "CNTL1 (rw) register accessor: an alias for `Reg`"] +#[doc = "CNTL1 (rw) register accessor: Control 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntl1`] +module"] pub type CNTL1 = crate::Reg; #[doc = "Control 1"] pub mod cntl1; -#[doc = "STAT (rw) register accessor: an alias for `Reg`"] +#[doc = "STAT (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] +module"] pub type STAT = crate::Reg; #[doc = "Status"] pub mod stat; -#[doc = "PEEK (r) register accessor: an alias for `Reg`"] +#[doc = "PEEK (r) register accessor: Read the RXFIFO without removing an entry\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peek`] +module"] pub type PEEK = crate::Reg; #[doc = "Read the RXFIFO without removing an entry"] pub mod peek; -#[doc = "IO (rw) register accessor: an alias for `Reg`"] +#[doc = "IO (rw) register accessor: Writing to the FIFO will deassert CS at the end of the access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io`] +module"] pub type IO = crate::Reg; #[doc = "Writing to the FIFO will deassert CS at the end of the access"] pub mod io; -#[doc = "TXHOLD (rw) register accessor: an alias for `Reg`"] +#[doc = "TXHOLD (rw) register accessor: Writing to the FIFO will maintain CS at the end of the access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txhold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txhold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txhold`] +module"] pub type TXHOLD = crate::Reg; #[doc = "Writing to the FIFO will maintain CS at the end of the access"] pub mod txhold; diff --git a/crates/bcm2711-lpa/src/spi1/cntl0.rs b/crates/bcm2711-lpa/src/spi1/cntl0.rs index b9354b5..df7d957 100644 --- a/crates/bcm2711-lpa/src/spi1/cntl0.rs +++ b/crates/bcm2711-lpa/src/spi1/cntl0.rs @@ -1,69 +1,37 @@ #[doc = "Register `CNTL0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CNTL0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SHIFT_LENGTH` reader - Number of bits to shift"] -pub type SHIFT_LENGTH_R = crate::FieldReader; +pub type SHIFT_LENGTH_R = crate::FieldReader; #[doc = "Field `SHIFT_LENGTH` writer - Number of bits to shift"] -pub type SHIFT_LENGTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u8, u8, 6, O>; +pub type SHIFT_LENGTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `MSB_FIRST` reader - Shift out the most significant bit (MSB) first"] -pub type MSB_FIRST_R = crate::BitReader; +pub type MSB_FIRST_R = crate::BitReader; #[doc = "Field `MSB_FIRST` writer - Shift out the most significant bit (MSB) first"] -pub type MSB_FIRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type MSB_FIRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INVERT_CLK` reader - Idle clock high"] -pub type INVERT_CLK_R = crate::BitReader; +pub type INVERT_CLK_R = crate::BitReader; #[doc = "Field `INVERT_CLK` writer - Idle clock high"] -pub type INVERT_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type INVERT_CLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OUT_RISING` reader - Data is clocked out on rising edge of CLK"] -pub type OUT_RISING_R = crate::BitReader; +pub type OUT_RISING_R = crate::BitReader; #[doc = "Field `OUT_RISING` writer - Data is clocked out on rising edge of CLK"] -pub type OUT_RISING_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type OUT_RISING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLEAR_FIFOS` reader - Clear FIFOs"] -pub type CLEAR_FIFOS_R = crate::BitReader; +pub type CLEAR_FIFOS_R = crate::BitReader; #[doc = "Field `CLEAR_FIFOS` writer - Clear FIFOs"] -pub type CLEAR_FIFOS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type CLEAR_FIFOS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IN_RISING` reader - Data is clocked in on rising edge of CLK"] -pub type IN_RISING_R = crate::BitReader; +pub type IN_RISING_R = crate::BitReader; #[doc = "Field `IN_RISING` writer - Data is clocked in on rising edge of CLK"] -pub type IN_RISING_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type IN_RISING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - Enable the interface"] -pub type ENABLE_R = crate::BitReader; +pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Enable the interface"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOUT_HOLD_TIME` reader - Controls extra DOUT hold time in system clock cycles"] -pub type DOUT_HOLD_TIME_R = crate::FieldReader; +pub type DOUT_HOLD_TIME_R = crate::FieldReader; #[doc = "Controls extra DOUT hold time in system clock cycles\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -83,10 +51,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for DOUT_HOLD_TIME_A { + type Ux = u8; +} impl DOUT_HOLD_TIME_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DOUT_HOLD_TIME_A { + pub const fn variant(&self) -> DOUT_HOLD_TIME_A { match self.bits { 0 => DOUT_HOLD_TIME_A::_0, 1 => DOUT_HOLD_TIME_A::_1, @@ -95,72 +66,76 @@ impl DOUT_HOLD_TIME_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_0`"] + #[doc = "`0`"] #[inline(always)] pub fn is_0(&self) -> bool { *self == DOUT_HOLD_TIME_A::_0 } - #[doc = "Checks if the value of the field is `_1`"] + #[doc = "`1`"] #[inline(always)] pub fn is_1(&self) -> bool { *self == DOUT_HOLD_TIME_A::_1 } - #[doc = "Checks if the value of the field is `_4`"] + #[doc = "`10`"] #[inline(always)] pub fn is_4(&self) -> bool { *self == DOUT_HOLD_TIME_A::_4 } - #[doc = "Checks if the value of the field is `_7`"] + #[doc = "`11`"] #[inline(always)] pub fn is_7(&self) -> bool { *self == DOUT_HOLD_TIME_A::_7 } } #[doc = "Field `DOUT_HOLD_TIME` writer - Controls extra DOUT hold time in system clock cycles"] -pub type DOUT_HOLD_TIME_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, CNTL0_SPEC, u8, DOUT_HOLD_TIME_A, 2, O>; -impl<'a, const O: u8> DOUT_HOLD_TIME_W<'a, O> { +pub type DOUT_HOLD_TIME_W<'a, REG, const O: u8> = + crate::FieldWriterSafe<'a, REG, 2, O, DOUT_HOLD_TIME_A>; +impl<'a, REG, const O: u8> DOUT_HOLD_TIME_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _0(self) -> &'a mut W { + pub fn _0(self) -> &'a mut crate::W { self.variant(DOUT_HOLD_TIME_A::_0) } #[doc = "`1`"] #[inline(always)] - pub fn _1(self) -> &'a mut W { + pub fn _1(self) -> &'a mut crate::W { self.variant(DOUT_HOLD_TIME_A::_1) } #[doc = "`10`"] #[inline(always)] - pub fn _4(self) -> &'a mut W { + pub fn _4(self) -> &'a mut crate::W { self.variant(DOUT_HOLD_TIME_A::_4) } #[doc = "`11`"] #[inline(always)] - pub fn _7(self) -> &'a mut W { + pub fn _7(self) -> &'a mut crate::W { self.variant(DOUT_HOLD_TIME_A::_7) } } #[doc = "Field `VARIABLE_WIDTH` reader - Take shift length and data from FIFO"] -pub type VARIABLE_WIDTH_R = crate::BitReader; +pub type VARIABLE_WIDTH_R = crate::BitReader; #[doc = "Field `VARIABLE_WIDTH` writer - Take shift length and data from FIFO"] -pub type VARIABLE_WIDTH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type VARIABLE_WIDTH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VARIABLE_CS` reader - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] -pub type VARIABLE_CS_R = crate::BitReader; +pub type VARIABLE_CS_R = crate::BitReader; #[doc = "Field `VARIABLE_CS` writer - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] -pub type VARIABLE_CS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type VARIABLE_CS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POST_INPUT` reader - Post input mode"] -pub type POST_INPUT_R = crate::BitReader; +pub type POST_INPUT_R = crate::BitReader; #[doc = "Field `POST_INPUT` writer - Post input mode"] -pub type POST_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type POST_INPUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHIP_SELECTS` reader - The CS pattern when active"] -pub type CHIP_SELECTS_R = crate::FieldReader; +pub type CHIP_SELECTS_R = crate::FieldReader; #[doc = "Field `CHIP_SELECTS` writer - The CS pattern when active"] -pub type CHIP_SELECTS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u8, u8, 3, O>; +pub type CHIP_SELECTS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `SPEED` reader - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] -pub type SPEED_R = crate::FieldReader; +pub type SPEED_R = crate::FieldReader; #[doc = "Field `SPEED` writer - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] -pub type SPEED_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u16, u16, 12, O>; +pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; impl R { #[doc = "Bits 0:5 - Number of bits to shift"] #[inline(always)] @@ -228,104 +203,141 @@ impl R { SPEED_R::new(((self.bits >> 20) & 0x0fff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CNTL0") + .field("speed", &format_args!("{}", self.speed().bits())) + .field( + "chip_selects", + &format_args!("{}", self.chip_selects().bits()), + ) + .field("post_input", &format_args!("{}", self.post_input().bit())) + .field("variable_cs", &format_args!("{}", self.variable_cs().bit())) + .field( + "variable_width", + &format_args!("{}", self.variable_width().bit()), + ) + .field( + "dout_hold_time", + &format_args!("{}", self.dout_hold_time().bits()), + ) + .field("enable", &format_args!("{}", self.enable().bit())) + .field("in_rising", &format_args!("{}", self.in_rising().bit())) + .field("clear_fifos", &format_args!("{}", self.clear_fifos().bit())) + .field("out_rising", &format_args!("{}", self.out_rising().bit())) + .field("invert_clk", &format_args!("{}", self.invert_clk().bit())) + .field("msb_first", &format_args!("{}", self.msb_first().bit())) + .field( + "shift_length", + &format_args!("{}", self.shift_length().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5 - Number of bits to shift"] #[inline(always)] #[must_use] - pub fn shift_length(&mut self) -> SHIFT_LENGTH_W<0> { + pub fn shift_length(&mut self) -> SHIFT_LENGTH_W { SHIFT_LENGTH_W::new(self) } #[doc = "Bit 6 - Shift out the most significant bit (MSB) first"] #[inline(always)] #[must_use] - pub fn msb_first(&mut self) -> MSB_FIRST_W<6> { + pub fn msb_first(&mut self) -> MSB_FIRST_W { MSB_FIRST_W::new(self) } #[doc = "Bit 7 - Idle clock high"] #[inline(always)] #[must_use] - pub fn invert_clk(&mut self) -> INVERT_CLK_W<7> { + pub fn invert_clk(&mut self) -> INVERT_CLK_W { INVERT_CLK_W::new(self) } #[doc = "Bit 8 - Data is clocked out on rising edge of CLK"] #[inline(always)] #[must_use] - pub fn out_rising(&mut self) -> OUT_RISING_W<8> { + pub fn out_rising(&mut self) -> OUT_RISING_W { OUT_RISING_W::new(self) } #[doc = "Bit 9 - Clear FIFOs"] #[inline(always)] #[must_use] - pub fn clear_fifos(&mut self) -> CLEAR_FIFOS_W<9> { + pub fn clear_fifos(&mut self) -> CLEAR_FIFOS_W { CLEAR_FIFOS_W::new(self) } #[doc = "Bit 10 - Data is clocked in on rising edge of CLK"] #[inline(always)] #[must_use] - pub fn in_rising(&mut self) -> IN_RISING_W<10> { + pub fn in_rising(&mut self) -> IN_RISING_W { IN_RISING_W::new(self) } #[doc = "Bit 11 - Enable the interface"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<11> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bits 12:13 - Controls extra DOUT hold time in system clock cycles"] #[inline(always)] #[must_use] - pub fn dout_hold_time(&mut self) -> DOUT_HOLD_TIME_W<12> { + pub fn dout_hold_time(&mut self) -> DOUT_HOLD_TIME_W { DOUT_HOLD_TIME_W::new(self) } #[doc = "Bit 14 - Take shift length and data from FIFO"] #[inline(always)] #[must_use] - pub fn variable_width(&mut self) -> VARIABLE_WIDTH_W<14> { + pub fn variable_width(&mut self) -> VARIABLE_WIDTH_W { VARIABLE_WIDTH_W::new(self) } #[doc = "Bit 15 - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] #[inline(always)] #[must_use] - pub fn variable_cs(&mut self) -> VARIABLE_CS_W<15> { + pub fn variable_cs(&mut self) -> VARIABLE_CS_W { VARIABLE_CS_W::new(self) } #[doc = "Bit 16 - Post input mode"] #[inline(always)] #[must_use] - pub fn post_input(&mut self) -> POST_INPUT_W<16> { + pub fn post_input(&mut self) -> POST_INPUT_W { POST_INPUT_W::new(self) } #[doc = "Bits 17:19 - The CS pattern when active"] #[inline(always)] #[must_use] - pub fn chip_selects(&mut self) -> CHIP_SELECTS_W<17> { + pub fn chip_selects(&mut self) -> CHIP_SELECTS_W { CHIP_SELECTS_W::new(self) } #[doc = "Bits 20:31 - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W<20> { + pub fn speed(&mut self) -> SPEED_W { SPEED_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl0](index.html) module"] +#[doc = "Control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CNTL0_SPEC; impl crate::RegisterSpec for CNTL0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cntl0::R](R) reader structure"] -impl crate::Readable for CNTL0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cntl0::W](W) writer structure"] +#[doc = "`read()` method returns [`cntl0::R`](R) reader structure"] +impl crate::Readable for CNTL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cntl0::W`](W) writer structure"] impl crate::Writable for CNTL0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/spi1/cntl1.rs b/crates/bcm2711-lpa/src/spi1/cntl1.rs index c7d627b..c1f0228 100644 --- a/crates/bcm2711-lpa/src/spi1/cntl1.rs +++ b/crates/bcm2711-lpa/src/spi1/cntl1.rs @@ -1,59 +1,27 @@ #[doc = "Register `CNTL1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CNTL1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `KEEP_INPUT` reader - Don't clear the RX shift register before a new transaction"] -pub type KEEP_INPUT_R = crate::BitReader; +pub type KEEP_INPUT_R = crate::BitReader; #[doc = "Field `KEEP_INPUT` writer - Don't clear the RX shift register before a new transaction"] -pub type KEEP_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +pub type KEEP_INPUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSB_FIRST` reader - Shift the most significant bit first (MSB)"] -pub type MSB_FIRST_R = crate::BitReader; +pub type MSB_FIRST_R = crate::BitReader; #[doc = "Field `MSB_FIRST` writer - Shift the most significant bit first (MSB)"] -pub type MSB_FIRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +pub type MSB_FIRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DONE_ENABLE` reader - Enable DONE interrupt"] -pub type DONE_ENABLE_R = crate::BitReader; +pub type DONE_ENABLE_R = crate::BitReader; #[doc = "Field `DONE_ENABLE` writer - Enable DONE interrupt"] -pub type DONE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +pub type DONE_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXE_ENABLE` reader - Enable TX empty interrupt"] -pub type TXE_ENABLE_R = crate::BitReader; +pub type TXE_ENABLE_R = crate::BitReader; #[doc = "Field `TXE_ENABLE` writer - Enable TX empty interrupt"] -pub type TXE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +pub type TXE_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CS_HIGH_TIME` reader - Additional SPI clock cycles where CS is high"] -pub type CS_HIGH_TIME_R = crate::FieldReader; +pub type CS_HIGH_TIME_R = crate::FieldReader; #[doc = "Field `CS_HIGH_TIME` writer - Additional SPI clock cycles where CS is high"] -pub type CS_HIGH_TIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL1_SPEC, u8, u8, 3, O>; +pub type CS_HIGH_TIME_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bit 0 - Don't clear the RX shift register before a new transaction"] #[inline(always)] @@ -81,56 +49,76 @@ impl R { CS_HIGH_TIME_R::new(((self.bits >> 8) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CNTL1") + .field( + "cs_high_time", + &format_args!("{}", self.cs_high_time().bits()), + ) + .field("txe_enable", &format_args!("{}", self.txe_enable().bit())) + .field("done_enable", &format_args!("{}", self.done_enable().bit())) + .field("msb_first", &format_args!("{}", self.msb_first().bit())) + .field("keep_input", &format_args!("{}", self.keep_input().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Don't clear the RX shift register before a new transaction"] #[inline(always)] #[must_use] - pub fn keep_input(&mut self) -> KEEP_INPUT_W<0> { + pub fn keep_input(&mut self) -> KEEP_INPUT_W { KEEP_INPUT_W::new(self) } #[doc = "Bit 1 - Shift the most significant bit first (MSB)"] #[inline(always)] #[must_use] - pub fn msb_first(&mut self) -> MSB_FIRST_W<1> { + pub fn msb_first(&mut self) -> MSB_FIRST_W { MSB_FIRST_W::new(self) } #[doc = "Bit 6 - Enable DONE interrupt"] #[inline(always)] #[must_use] - pub fn done_enable(&mut self) -> DONE_ENABLE_W<6> { + pub fn done_enable(&mut self) -> DONE_ENABLE_W { DONE_ENABLE_W::new(self) } #[doc = "Bit 7 - Enable TX empty interrupt"] #[inline(always)] #[must_use] - pub fn txe_enable(&mut self) -> TXE_ENABLE_W<7> { + pub fn txe_enable(&mut self) -> TXE_ENABLE_W { TXE_ENABLE_W::new(self) } #[doc = "Bits 8:10 - Additional SPI clock cycles where CS is high"] #[inline(always)] #[must_use] - pub fn cs_high_time(&mut self) -> CS_HIGH_TIME_W<8> { + pub fn cs_high_time(&mut self) -> CS_HIGH_TIME_W { CS_HIGH_TIME_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl1](index.html) module"] +#[doc = "Control 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CNTL1_SPEC; impl crate::RegisterSpec for CNTL1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cntl1::R](R) reader structure"] -impl crate::Readable for CNTL1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cntl1::W](W) writer structure"] +#[doc = "`read()` method returns [`cntl1::R`](R) reader structure"] +impl crate::Readable for CNTL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cntl1::W`](W) writer structure"] impl crate::Writable for CNTL1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/spi1/io.rs b/crates/bcm2711-lpa/src/spi1/io.rs index 365004d..6564875 100644 --- a/crates/bcm2711-lpa/src/spi1/io.rs +++ b/crates/bcm2711-lpa/src/spi1/io.rs @@ -1,43 +1,11 @@ #[doc = "Register `IO%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IO%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - FIFO data access"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - FIFO data access"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO_SPEC, u16, u16, 16, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IO") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Writing to the FIFO will deassert CS at the end of the access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](index.html) module"] +#[doc = "Writing to the FIFO will deassert CS at the end of the access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IO_SPEC; impl crate::RegisterSpec for IO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [io::R](R) reader structure"] -impl crate::Readable for IO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [io::W](W) writer structure"] +#[doc = "`read()` method returns [`io::R`](R) reader structure"] +impl crate::Readable for IO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`io::W`](W) writer structure"] impl crate::Writable for IO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/spi1/peek.rs b/crates/bcm2711-lpa/src/spi1/peek.rs index b4a7333..7ceeb4a 100644 --- a/crates/bcm2711-lpa/src/spi1/peek.rs +++ b/crates/bcm2711-lpa/src/spi1/peek.rs @@ -1,20 +1,7 @@ #[doc = "Register `PEEK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DATA` reader - FIFO data access"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] @@ -22,15 +9,25 @@ impl R { DATA_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Read the RXFIFO without removing an entry\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PEEK") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Read the RXFIFO without removing an entry\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEEK_SPEC; impl crate::RegisterSpec for PEEK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [peek::R](R) reader structure"] -impl crate::Readable for PEEK_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`peek::R`](R) reader structure"] +impl crate::Readable for PEEK_SPEC {} #[doc = "`reset()` method sets PEEK to value 0"] impl crate::Resettable for PEEK_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/spi1/stat.rs b/crates/bcm2711-lpa/src/spi1/stat.rs index 0dd56f6..9fe3977 100644 --- a/crates/bcm2711-lpa/src/spi1/stat.rs +++ b/crates/bcm2711-lpa/src/spi1/stat.rs @@ -1,71 +1,39 @@ #[doc = "Register `STAT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STAT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BIT_COUNT` reader - Number of bits left to be processed."] -pub type BIT_COUNT_R = crate::FieldReader; +pub type BIT_COUNT_R = crate::FieldReader; #[doc = "Field `BIT_COUNT` writer - Number of bits left to be processed."] -pub type BIT_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 6, O>; +pub type BIT_COUNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `BUSY` reader - Indicates a transfer is ongoing"] -pub type BUSY_R = crate::BitReader; +pub type BUSY_R = crate::BitReader; #[doc = "Field `BUSY` writer - Indicates a transfer is ongoing"] -pub type BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type BUSY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_EMPTY` reader - RX FIFO is empty"] -pub type RX_EMPTY_R = crate::BitReader; +pub type RX_EMPTY_R = crate::BitReader; #[doc = "Field `RX_EMPTY` writer - RX FIFO is empty"] -pub type RX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_FULL` reader - RX FIFO is full"] -pub type RX_FULL_R = crate::BitReader; +pub type RX_FULL_R = crate::BitReader; #[doc = "Field `RX_FULL` writer - RX FIFO is full"] -pub type RX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_EMPTY` reader - TX FIFO is empty"] -pub type TX_EMPTY_R = crate::BitReader; +pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `TX_EMPTY` writer - TX FIFO is empty"] -pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_FULL` reader - TX FIFO is full"] -pub type TX_FULL_R = crate::BitReader; +pub type TX_FULL_R = crate::BitReader; #[doc = "Field `TX_FULL` writer - TX FIFO is full"] -pub type TX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_LEVEL` reader - Number of entries in RX FIFO"] -pub type RX_LEVEL_R = crate::FieldReader; +pub type RX_LEVEL_R = crate::FieldReader; #[doc = "Field `RX_LEVEL` writer - Number of entries in RX FIFO"] -pub type RX_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +pub type RX_LEVEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TX_LEVEL` reader - Number of entries in TX FIFO"] -pub type TX_LEVEL_R = crate::FieldReader; +pub type TX_LEVEL_R = crate::FieldReader; #[doc = "Field `TX_LEVEL` writer - Number of entries in TX FIFO"] -pub type TX_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +pub type TX_LEVEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:5 - Number of bits left to be processed."] #[inline(always)] @@ -108,74 +76,94 @@ impl R { TX_LEVEL_R::new(((self.bits >> 24) & 0x0f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STAT") + .field("tx_level", &format_args!("{}", self.tx_level().bits())) + .field("rx_level", &format_args!("{}", self.rx_level().bits())) + .field("tx_full", &format_args!("{}", self.tx_full().bit())) + .field("tx_empty", &format_args!("{}", self.tx_empty().bit())) + .field("rx_full", &format_args!("{}", self.rx_full().bit())) + .field("rx_empty", &format_args!("{}", self.rx_empty().bit())) + .field("busy", &format_args!("{}", self.busy().bit())) + .field("bit_count", &format_args!("{}", self.bit_count().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5 - Number of bits left to be processed."] #[inline(always)] #[must_use] - pub fn bit_count(&mut self) -> BIT_COUNT_W<0> { + pub fn bit_count(&mut self) -> BIT_COUNT_W { BIT_COUNT_W::new(self) } #[doc = "Bit 6 - Indicates a transfer is ongoing"] #[inline(always)] #[must_use] - pub fn busy(&mut self) -> BUSY_W<6> { + pub fn busy(&mut self) -> BUSY_W { BUSY_W::new(self) } #[doc = "Bit 7 - RX FIFO is empty"] #[inline(always)] #[must_use] - pub fn rx_empty(&mut self) -> RX_EMPTY_W<7> { + pub fn rx_empty(&mut self) -> RX_EMPTY_W { RX_EMPTY_W::new(self) } #[doc = "Bit 8 - RX FIFO is full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W<8> { + pub fn rx_full(&mut self) -> RX_FULL_W { RX_FULL_W::new(self) } #[doc = "Bit 9 - TX FIFO is empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W<9> { + pub fn tx_empty(&mut self) -> TX_EMPTY_W { TX_EMPTY_W::new(self) } #[doc = "Bit 10 - TX FIFO is full"] #[inline(always)] #[must_use] - pub fn tx_full(&mut self) -> TX_FULL_W<10> { + pub fn tx_full(&mut self) -> TX_FULL_W { TX_FULL_W::new(self) } #[doc = "Bits 16:19 - Number of entries in RX FIFO"] #[inline(always)] #[must_use] - pub fn rx_level(&mut self) -> RX_LEVEL_W<16> { + pub fn rx_level(&mut self) -> RX_LEVEL_W { RX_LEVEL_W::new(self) } #[doc = "Bits 24:27 - Number of entries in TX FIFO"] #[inline(always)] #[must_use] - pub fn tx_level(&mut self) -> TX_LEVEL_W<24> { + pub fn tx_level(&mut self) -> TX_LEVEL_W { TX_LEVEL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"] +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STAT_SPEC; impl crate::RegisterSpec for STAT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [stat::R](R) reader structure"] -impl crate::Readable for STAT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"] +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] impl crate::Writable for STAT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/spi1/txhold.rs b/crates/bcm2711-lpa/src/spi1/txhold.rs index a2ca31b..8c29938 100644 --- a/crates/bcm2711-lpa/src/spi1/txhold.rs +++ b/crates/bcm2711-lpa/src/spi1/txhold.rs @@ -1,43 +1,11 @@ #[doc = "Register `TXHOLD%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TXHOLD%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - FIFO data access"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - FIFO data access"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXHOLD_SPEC, u16, u16, 16, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TXHOLD") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Writing to the FIFO will maintain CS at the end of the access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txhold](index.html) module"] +#[doc = "Writing to the FIFO will maintain CS at the end of the access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txhold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txhold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXHOLD_SPEC; impl crate::RegisterSpec for TXHOLD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txhold::R](R) reader structure"] -impl crate::Readable for TXHOLD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [txhold::W](W) writer structure"] +#[doc = "`read()` method returns [`txhold::R`](R) reader structure"] +impl crate::Readable for TXHOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txhold::W`](W) writer structure"] impl crate::Writable for TXHOLD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/systmr.rs b/crates/bcm2711-lpa/src/systmr.rs index 859ea09..31647d3 100644 --- a/crates/bcm2711-lpa/src/systmr.rs +++ b/crates/bcm2711-lpa/src/systmr.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control / Status"] pub cs: CS, @@ -16,31 +17,38 @@ pub struct RegisterBlock { #[doc = "0x18 - Compare channel 3"] pub c3: C3, } -#[doc = "CS (rw) register accessor: an alias for `Reg`"] +#[doc = "CS (rw) register accessor: Control / Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cs`] +module"] pub type CS = crate::Reg; #[doc = "Control / Status"] pub mod cs; -#[doc = "CLO (r) register accessor: an alias for `Reg`"] +#[doc = "CLO (r) register accessor: Lower 32 bits for the free running counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clo`] +module"] pub type CLO = crate::Reg; #[doc = "Lower 32 bits for the free running counter"] pub mod clo; -#[doc = "CHI (r) register accessor: an alias for `Reg`"] +#[doc = "CHI (r) register accessor: Higher 32 bits for the free running counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chi`] +module"] pub type CHI = crate::Reg; #[doc = "Higher 32 bits for the free running counter"] pub mod chi; -#[doc = "C0 (rw) register accessor: an alias for `Reg`"] +#[doc = "C0 (rw) register accessor: Compare channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c0`] +module"] pub type C0 = crate::Reg; #[doc = "Compare channel 0"] pub mod c0; -#[doc = "C1 (rw) register accessor: an alias for `Reg`"] +#[doc = "C1 (rw) register accessor: Compare channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c1`] +module"] pub type C1 = crate::Reg; #[doc = "Compare channel 1"] pub mod c1; -#[doc = "C2 (rw) register accessor: an alias for `Reg`"] +#[doc = "C2 (rw) register accessor: Compare channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c2`] +module"] pub type C2 = crate::Reg; #[doc = "Compare channel 2"] pub mod c2; -#[doc = "C3 (rw) register accessor: an alias for `Reg`"] +#[doc = "C3 (rw) register accessor: Compare channel 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c3`] +module"] pub type C3 = crate::Reg; #[doc = "Compare channel 3"] pub mod c3; diff --git a/crates/bcm2711-lpa/src/systmr/c0.rs b/crates/bcm2711-lpa/src/systmr/c0.rs index 20b09d2..18be8a7 100644 --- a/crates/bcm2711-lpa/src/systmr/c0.rs +++ b/crates/bcm2711-lpa/src/systmr/c0.rs @@ -1,59 +1,38 @@ #[doc = "Register `C0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Compare channel 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c0](index.html) module"] +#[doc = "Compare channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C0_SPEC; impl crate::RegisterSpec for C0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c0::R](R) reader structure"] -impl crate::Readable for C0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c0::W](W) writer structure"] +#[doc = "`read()` method returns [`c0::R`](R) reader structure"] +impl crate::Readable for C0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c0::W`](W) writer structure"] impl crate::Writable for C0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/systmr/c1.rs b/crates/bcm2711-lpa/src/systmr/c1.rs index 87cf5ed..bcf565c 100644 --- a/crates/bcm2711-lpa/src/systmr/c1.rs +++ b/crates/bcm2711-lpa/src/systmr/c1.rs @@ -1,59 +1,38 @@ #[doc = "Register `C1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Compare channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c1](index.html) module"] +#[doc = "Compare channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C1_SPEC; impl crate::RegisterSpec for C1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c1::R](R) reader structure"] -impl crate::Readable for C1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c1::W](W) writer structure"] +#[doc = "`read()` method returns [`c1::R`](R) reader structure"] +impl crate::Readable for C1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c1::W`](W) writer structure"] impl crate::Writable for C1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/systmr/c2.rs b/crates/bcm2711-lpa/src/systmr/c2.rs index 8c9c84b..e91e152 100644 --- a/crates/bcm2711-lpa/src/systmr/c2.rs +++ b/crates/bcm2711-lpa/src/systmr/c2.rs @@ -1,59 +1,38 @@ #[doc = "Register `C2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Compare channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c2](index.html) module"] +#[doc = "Compare channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C2_SPEC; impl crate::RegisterSpec for C2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c2::R](R) reader structure"] -impl crate::Readable for C2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c2::W](W) writer structure"] +#[doc = "`read()` method returns [`c2::R`](R) reader structure"] +impl crate::Readable for C2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c2::W`](W) writer structure"] impl crate::Writable for C2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/systmr/c3.rs b/crates/bcm2711-lpa/src/systmr/c3.rs index 0ac0aa2..a33918f 100644 --- a/crates/bcm2711-lpa/src/systmr/c3.rs +++ b/crates/bcm2711-lpa/src/systmr/c3.rs @@ -1,59 +1,38 @@ #[doc = "Register `C3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Compare channel 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c3](index.html) module"] +#[doc = "Compare channel 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C3_SPEC; impl crate::RegisterSpec for C3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c3::R](R) reader structure"] -impl crate::Readable for C3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c3::W](W) writer structure"] +#[doc = "`read()` method returns [`c3::R`](R) reader structure"] +impl crate::Readable for C3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c3::W`](W) writer structure"] impl crate::Writable for C3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/systmr/chi.rs b/crates/bcm2711-lpa/src/systmr/chi.rs index 9f162ef..7313db2 100644 --- a/crates/bcm2711-lpa/src/systmr/chi.rs +++ b/crates/bcm2711-lpa/src/systmr/chi.rs @@ -1,27 +1,22 @@ #[doc = "Register `CHI` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } -#[doc = "Higher 32 bits for the free running counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chi](index.html) module"] +#[doc = "Higher 32 bits for the free running counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CHI_SPEC; impl crate::RegisterSpec for CHI_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [chi::R](R) reader structure"] -impl crate::Readable for CHI_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`chi::R`](R) reader structure"] +impl crate::Readable for CHI_SPEC {} #[doc = "`reset()` method sets CHI to value 0"] impl crate::Resettable for CHI_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/systmr/clo.rs b/crates/bcm2711-lpa/src/systmr/clo.rs index 0a4b01f..43986b1 100644 --- a/crates/bcm2711-lpa/src/systmr/clo.rs +++ b/crates/bcm2711-lpa/src/systmr/clo.rs @@ -1,27 +1,22 @@ #[doc = "Register `CLO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } -#[doc = "Lower 32 bits for the free running counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clo](index.html) module"] +#[doc = "Lower 32 bits for the free running counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLO_SPEC; impl crate::RegisterSpec for CLO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clo::R](R) reader structure"] -impl crate::Readable for CLO_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clo::R`](R) reader structure"] +impl crate::Readable for CLO_SPEC {} #[doc = "`reset()` method sets CLO to value 0"] impl crate::Resettable for CLO_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/systmr/cs.rs b/crates/bcm2711-lpa/src/systmr/cs.rs index dcb8ec2..3e1660d 100644 --- a/crates/bcm2711-lpa/src/systmr/cs.rs +++ b/crates/bcm2711-lpa/src/systmr/cs.rs @@ -1,55 +1,23 @@ #[doc = "Register `CS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `M0` reader - System timer match 0"] -pub type M0_R = crate::BitReader; +pub type M0_R = crate::BitReader; #[doc = "Field `M0` writer - System timer match 0"] -pub type M0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +pub type M0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `M1` reader - System timer match 1"] -pub type M1_R = crate::BitReader; +pub type M1_R = crate::BitReader; #[doc = "Field `M1` writer - System timer match 1"] -pub type M1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +pub type M1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `M2` reader - System timer match 2"] -pub type M2_R = crate::BitReader; +pub type M2_R = crate::BitReader; #[doc = "Field `M2` writer - System timer match 2"] -pub type M2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +pub type M2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `M3` reader - System timer match 3"] -pub type M3_R = crate::BitReader; +pub type M3_R = crate::BitReader; #[doc = "Field `M3` writer - System timer match 3"] -pub type M3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +pub type M3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - System timer match 0"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { M3_R::new(((self.bits >> 3) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CS") + .field("m3", &format_args!("{}", self.m3().bit())) + .field("m2", &format_args!("{}", self.m2().bit())) + .field("m1", &format_args!("{}", self.m1().bit())) + .field("m0", &format_args!("{}", self.m0().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - System timer match 0"] #[inline(always)] #[must_use] - pub fn m0(&mut self) -> M0_W<0> { + pub fn m0(&mut self) -> M0_W { M0_W::new(self) } #[doc = "Bit 1 - System timer match 1"] #[inline(always)] #[must_use] - pub fn m1(&mut self) -> M1_W<1> { + pub fn m1(&mut self) -> M1_W { M1_W::new(self) } #[doc = "Bit 2 - System timer match 2"] #[inline(always)] #[must_use] - pub fn m2(&mut self) -> M2_W<2> { + pub fn m2(&mut self) -> M2_W { M2_W::new(self) } #[doc = "Bit 3 - System timer match 3"] #[inline(always)] #[must_use] - pub fn m3(&mut self) -> M3_W<3> { + pub fn m3(&mut self) -> M3_W { M3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control / Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +#[doc = "Control / Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CS_SPEC; impl crate::RegisterSpec for CS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cs::R](R) reader structure"] -impl crate::Readable for CS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0f; } diff --git a/crates/bcm2711-lpa/src/uart0.rs b/crates/bcm2711-lpa/src/uart0.rs index aade8a9..a12a501 100644 --- a/crates/bcm2711-lpa/src/uart0.rs +++ b/crates/bcm2711-lpa/src/uart0.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Data Register"] pub dr: DR, @@ -41,59 +42,73 @@ impl RegisterBlock { unsafe { &*(self as *const Self).cast::().add(4usize).cast() } } } -#[doc = "DR (rw) register accessor: an alias for `Reg`"] +#[doc = "DR (rw) register accessor: Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`] +module"] pub type DR = crate::Reg; #[doc = "Data Register"] pub mod dr; -#[doc = "RSR (r) register accessor: an alias for `Reg`"] +#[doc = "RSR (r) register accessor: Receive Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsr`] +module"] pub type RSR = crate::Reg; #[doc = "Receive Status Register"] pub mod rsr; -#[doc = "ECR (w) register accessor: an alias for `Reg`"] +#[doc = "ECR (w) register accessor: Error Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr`] +module"] pub type ECR = crate::Reg; #[doc = "Error Clear Register"] pub mod ecr; -#[doc = "FR (rw) register accessor: an alias for `Reg`"] +#[doc = "FR (rw) register accessor: Flag Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fr`] +module"] pub type FR = crate::Reg; #[doc = "Flag Register"] pub mod fr; -#[doc = "IBRD (rw) register accessor: an alias for `Reg`"] +#[doc = "IBRD (rw) register accessor: Integer Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibrd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibrd`] +module"] pub type IBRD = crate::Reg; #[doc = "Integer Baud Rate Register"] pub mod ibrd; -#[doc = "FBRD (rw) register accessor: an alias for `Reg`"] +#[doc = "FBRD (rw) register accessor: Fractional Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fbrd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fbrd`] +module"] pub type FBRD = crate::Reg; #[doc = "Fractional Baud Rate Register"] pub mod fbrd; -#[doc = "LCR_H (rw) register accessor: an alias for `Reg`"] +#[doc = "LCR_H (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr_h::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr_h::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr_h`] +module"] pub type LCR_H = crate::Reg; #[doc = "Line Control Register"] pub mod lcr_h; -#[doc = "CR (rw) register accessor: an alias for `Reg`"] +#[doc = "CR (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "IFLS (rw) register accessor: an alias for `Reg`"] +#[doc = "IFLS (rw) register accessor: Interrupt FIFO Level Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifls::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifls::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ifls`] +module"] pub type IFLS = crate::Reg; #[doc = "Interrupt FIFO Level Select Register"] pub mod ifls; -#[doc = "IMSC (rw) register accessor: an alias for `Reg`"] +#[doc = "IMSC (rw) register accessor: Interrupt Mask set_Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imsc`] +module"] pub type IMSC = crate::Reg; #[doc = "Interrupt Mask set_Clear Register"] pub mod imsc; -#[doc = "RIS (r) register accessor: an alias for `Reg`"] +#[doc = "RIS (r) register accessor: Raw Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`] +module"] pub type RIS = crate::Reg; #[doc = "Raw Interrupt Status Register"] pub mod ris; -#[doc = "MIS (r) register accessor: an alias for `Reg`"] +#[doc = "MIS (r) register accessor: Masked Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`] +module"] pub type MIS = crate::Reg; #[doc = "Masked Interrupt Status Register"] pub mod mis; -#[doc = "ICR (w) register accessor: an alias for `Reg`"] +#[doc = "ICR (w) register accessor: Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`] +module"] pub type ICR = crate::Reg; #[doc = "Interrupt Clear Register"] pub mod icr; -#[doc = "DMACR (rw) register accessor: an alias for `Reg`"] +#[doc = "DMACR (rw) register accessor: DMA Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmacr`] +module"] pub type DMACR = crate::Reg; #[doc = "DMA Control Register"] pub mod dmacr; diff --git a/crates/bcm2711-lpa/src/uart0/cr.rs b/crates/bcm2711-lpa/src/uart0/cr.rs index 6c47a00..bfbc283 100644 --- a/crates/bcm2711-lpa/src/uart0/cr.rs +++ b/crates/bcm2711-lpa/src/uart0/cr.rs @@ -1,75 +1,43 @@ #[doc = "Register `CR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UARTEN` reader - UARTEN"] -pub type UARTEN_R = crate::BitReader; +pub type UARTEN_R = crate::BitReader; #[doc = "Field `UARTEN` writer - UARTEN"] -pub type UARTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type UARTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SIREN` reader - SIREN"] -pub type SIREN_R = crate::BitReader; +pub type SIREN_R = crate::BitReader; #[doc = "Field `SIREN` writer - SIREN"] -pub type SIREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type SIREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SIRLP` reader - SIRLP"] -pub type SIRLP_R = crate::BitReader; +pub type SIRLP_R = crate::BitReader; #[doc = "Field `SIRLP` writer - SIRLP"] -pub type SIRLP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type SIRLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXE` reader - TXE"] -pub type TXE_R = crate::BitReader; +pub type TXE_R = crate::BitReader; #[doc = "Field `TXE` writer - TXE"] -pub type TXE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type TXE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXE` reader - RXE"] -pub type RXE_R = crate::BitReader; +pub type RXE_R = crate::BitReader; #[doc = "Field `RXE` writer - RXE"] -pub type RXE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type RXE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTR` reader - DTR"] -pub type DTR_R = crate::BitReader; +pub type DTR_R = crate::BitReader; #[doc = "Field `DTR` writer - DTR"] -pub type DTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTS` reader - RTS"] -pub type RTS_R = crate::BitReader; +pub type RTS_R = crate::BitReader; #[doc = "Field `RTS` writer - RTS"] -pub type RTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTSEN` reader - RTSEN"] -pub type RTSEN_R = crate::BitReader; +pub type RTSEN_R = crate::BitReader; #[doc = "Field `RTSEN` writer - RTSEN"] -pub type RTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type RTSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTSEN` reader - CTSEN"] -pub type CTSEN_R = crate::BitReader; +pub type CTSEN_R = crate::BitReader; #[doc = "Field `CTSEN` writer - CTSEN"] -pub type CTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type CTSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - UARTEN"] #[inline(always)] @@ -117,80 +85,101 @@ impl R { CTSEN_R::new(((self.bits >> 15) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CR") + .field("uarten", &format_args!("{}", self.uarten().bit())) + .field("siren", &format_args!("{}", self.siren().bit())) + .field("sirlp", &format_args!("{}", self.sirlp().bit())) + .field("txe", &format_args!("{}", self.txe().bit())) + .field("rxe", &format_args!("{}", self.rxe().bit())) + .field("dtr", &format_args!("{}", self.dtr().bit())) + .field("rts", &format_args!("{}", self.rts().bit())) + .field("rtsen", &format_args!("{}", self.rtsen().bit())) + .field("ctsen", &format_args!("{}", self.ctsen().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - UARTEN"] #[inline(always)] #[must_use] - pub fn uarten(&mut self) -> UARTEN_W<0> { + pub fn uarten(&mut self) -> UARTEN_W { UARTEN_W::new(self) } #[doc = "Bit 1 - SIREN"] #[inline(always)] #[must_use] - pub fn siren(&mut self) -> SIREN_W<1> { + pub fn siren(&mut self) -> SIREN_W { SIREN_W::new(self) } #[doc = "Bit 2 - SIRLP"] #[inline(always)] #[must_use] - pub fn sirlp(&mut self) -> SIRLP_W<2> { + pub fn sirlp(&mut self) -> SIRLP_W { SIRLP_W::new(self) } #[doc = "Bit 8 - TXE"] #[inline(always)] #[must_use] - pub fn txe(&mut self) -> TXE_W<8> { + pub fn txe(&mut self) -> TXE_W { TXE_W::new(self) } #[doc = "Bit 9 - RXE"] #[inline(always)] #[must_use] - pub fn rxe(&mut self) -> RXE_W<9> { + pub fn rxe(&mut self) -> RXE_W { RXE_W::new(self) } #[doc = "Bit 10 - DTR"] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W<10> { + pub fn dtr(&mut self) -> DTR_W { DTR_W::new(self) } #[doc = "Bit 11 - RTS"] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W<11> { + pub fn rts(&mut self) -> RTS_W { RTS_W::new(self) } #[doc = "Bit 14 - RTSEN"] #[inline(always)] #[must_use] - pub fn rtsen(&mut self) -> RTSEN_W<14> { + pub fn rtsen(&mut self) -> RTSEN_W { RTSEN_W::new(self) } #[doc = "Bit 15 - CTSEN"] #[inline(always)] #[must_use] - pub fn ctsen(&mut self) -> CTSEN_W<15> { + pub fn ctsen(&mut self) -> CTSEN_W { CTSEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cr::R](R) reader structure"] -impl crate::Readable for CR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`read()` method returns [`cr::R`](R) reader structure"] +impl crate::Readable for CR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart0/dmacr.rs b/crates/bcm2711-lpa/src/uart0/dmacr.rs index 8bd3632..40efa50 100644 --- a/crates/bcm2711-lpa/src/uart0/dmacr.rs +++ b/crates/bcm2711-lpa/src/uart0/dmacr.rs @@ -1,51 +1,19 @@ #[doc = "Register `DMACR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMACR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXDMAE` reader - RXDMAE"] -pub type RXDMAE_R = crate::BitReader; +pub type RXDMAE_R = crate::BitReader; #[doc = "Field `RXDMAE` writer - RXDMAE"] -pub type RXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXDMAE` reader - TXDMAE"] -pub type TXDMAE_R = crate::BitReader; +pub type TXDMAE_R = crate::BitReader; #[doc = "Field `TXDMAE` writer - TXDMAE"] -pub type TXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMAONERR` reader - DMAONERR"] -pub type DMAONERR_R = crate::BitReader; +pub type DMAONERR_R = crate::BitReader; #[doc = "Field `DMAONERR` writer - DMAONERR"] -pub type DMAONERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +pub type DMAONERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - RXDMAE"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { DMAONERR_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMACR") + .field("rxdmae", &format_args!("{}", self.rxdmae().bit())) + .field("txdmae", &format_args!("{}", self.txdmae().bit())) + .field("dmaonerr", &format_args!("{}", self.dmaonerr().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - RXDMAE"] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W<0> { + pub fn rxdmae(&mut self) -> RXDMAE_W { RXDMAE_W::new(self) } #[doc = "Bit 1 - TXDMAE"] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W<1> { + pub fn txdmae(&mut self) -> TXDMAE_W { TXDMAE_W::new(self) } #[doc = "Bit 2 - DMAONERR"] #[inline(always)] #[must_use] - pub fn dmaonerr(&mut self) -> DMAONERR_W<2> { + pub fn dmaonerr(&mut self) -> DMAONERR_W { DMAONERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacr](index.html) module"] +#[doc = "DMA Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMACR_SPEC; impl crate::RegisterSpec for DMACR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dmacr::R](R) reader structure"] -impl crate::Readable for DMACR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dmacr::W](W) writer structure"] +#[doc = "`read()` method returns [`dmacr::R`](R) reader structure"] +impl crate::Readable for DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dmacr::W`](W) writer structure"] impl crate::Writable for DMACR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart0/dr.rs b/crates/bcm2711-lpa/src/uart0/dr.rs index 236d30b..3c7f81e 100644 --- a/crates/bcm2711-lpa/src/uart0/dr.rs +++ b/crates/bcm2711-lpa/src/uart0/dr.rs @@ -1,59 +1,27 @@ #[doc = "Register `DR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - DATA"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - DATA"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DR_SPEC, u8, u8, 8, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `FE` reader - FE"] -pub type FE_R = crate::BitReader; +pub type FE_R = crate::BitReader; #[doc = "Field `FE` writer - FE"] -pub type FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +pub type FE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PE` reader - PE"] -pub type PE_R = crate::BitReader; +pub type PE_R = crate::BitReader; #[doc = "Field `PE` writer - PE"] -pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +pub type PE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BE` reader - BE"] -pub type BE_R = crate::BitReader; +pub type BE_R = crate::BitReader; #[doc = "Field `BE` writer - BE"] -pub type BE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +pub type BE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OE` reader - OE"] -pub type OE_R = crate::BitReader; +pub type OE_R = crate::BitReader; #[doc = "Field `OE` writer - OE"] -pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +pub type OE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:7 - DATA"] #[inline(always)] @@ -81,56 +49,73 @@ impl R { OE_R::new(((self.bits >> 11) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DR") + .field("data", &format_args!("{}", self.data().bits())) + .field("fe", &format_args!("{}", self.fe().bit())) + .field("pe", &format_args!("{}", self.pe().bit())) + .field("be", &format_args!("{}", self.be().bit())) + .field("oe", &format_args!("{}", self.oe().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DATA"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } #[doc = "Bit 8 - FE"] #[inline(always)] #[must_use] - pub fn fe(&mut self) -> FE_W<8> { + pub fn fe(&mut self) -> FE_W { FE_W::new(self) } #[doc = "Bit 9 - PE"] #[inline(always)] #[must_use] - pub fn pe(&mut self) -> PE_W<9> { + pub fn pe(&mut self) -> PE_W { PE_W::new(self) } #[doc = "Bit 10 - BE"] #[inline(always)] #[must_use] - pub fn be(&mut self) -> BE_W<10> { + pub fn be(&mut self) -> BE_W { BE_W::new(self) } #[doc = "Bit 11 - OE"] #[inline(always)] #[must_use] - pub fn oe(&mut self) -> OE_W<11> { + pub fn oe(&mut self) -> OE_W { OE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"] +#[doc = "Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DR_SPEC; impl crate::RegisterSpec for DR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dr::R](R) reader structure"] -impl crate::Readable for DR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"] +#[doc = "`read()` method returns [`dr::R`](R) reader structure"] +impl crate::Readable for DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"] impl crate::Writable for DR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart0/ecr.rs b/crates/bcm2711-lpa/src/uart0/ecr.rs index f469e97..97efb0b 100644 --- a/crates/bcm2711-lpa/src/uart0/ecr.rs +++ b/crates/bcm2711-lpa/src/uart0/ecr.rs @@ -1,72 +1,61 @@ #[doc = "Register `ECR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FE` writer - FE"] -pub type FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +pub type FE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PE` writer - PE"] -pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +pub type PE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BE` writer - BE"] -pub type BE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +pub type BE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OE` writer - OE"] -pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +pub type OE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - FE"] #[inline(always)] #[must_use] - pub fn fe(&mut self) -> FE_W<0> { + pub fn fe(&mut self) -> FE_W { FE_W::new(self) } #[doc = "Bit 1 - PE"] #[inline(always)] #[must_use] - pub fn pe(&mut self) -> PE_W<1> { + pub fn pe(&mut self) -> PE_W { PE_W::new(self) } #[doc = "Bit 2 - BE"] #[inline(always)] #[must_use] - pub fn be(&mut self) -> BE_W<2> { + pub fn be(&mut self) -> BE_W { BE_W::new(self) } #[doc = "Bit 3 - OE"] #[inline(always)] #[must_use] - pub fn oe(&mut self) -> OE_W<3> { + pub fn oe(&mut self) -> OE_W { OE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Error Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecr](index.html) module"] +#[doc = "Error Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ECR_SPEC; impl crate::RegisterSpec for ECR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ecr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ecr::W`](W) writer structure"] impl crate::Writable for ECR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart0/fbrd.rs b/crates/bcm2711-lpa/src/uart0/fbrd.rs index 14ae9a3..e0fe228 100644 --- a/crates/bcm2711-lpa/src/uart0/fbrd.rs +++ b/crates/bcm2711-lpa/src/uart0/fbrd.rs @@ -1,43 +1,11 @@ #[doc = "Register `FBRD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FBRD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BAUDDIVFRAC` reader - BAUDDIVFRAC"] -pub type BAUDDIVFRAC_R = crate::FieldReader; +pub type BAUDDIVFRAC_R = crate::FieldReader; #[doc = "Field `BAUDDIVFRAC` writer - BAUDDIVFRAC"] -pub type BAUDDIVFRAC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FBRD_SPEC, u8, u8, 6, O>; +pub type BAUDDIVFRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5 - BAUDDIVFRAC"] #[inline(always)] @@ -45,32 +13,48 @@ impl R { BAUDDIVFRAC_R::new((self.bits & 0x3f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FBRD") + .field( + "bauddivfrac", + &format_args!("{}", self.bauddivfrac().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5 - BAUDDIVFRAC"] #[inline(always)] #[must_use] - pub fn bauddivfrac(&mut self) -> BAUDDIVFRAC_W<0> { + pub fn bauddivfrac(&mut self) -> BAUDDIVFRAC_W { BAUDDIVFRAC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Fractional Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fbrd](index.html) module"] +#[doc = "Fractional Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fbrd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FBRD_SPEC; impl crate::RegisterSpec for FBRD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fbrd::R](R) reader structure"] -impl crate::Readable for FBRD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fbrd::W](W) writer structure"] +#[doc = "`read()` method returns [`fbrd::R`](R) reader structure"] +impl crate::Readable for FBRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fbrd::W`](W) writer structure"] impl crate::Writable for FBRD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart0/fr.rs b/crates/bcm2711-lpa/src/uart0/fr.rs index 641becc..d70703c 100644 --- a/crates/bcm2711-lpa/src/uart0/fr.rs +++ b/crates/bcm2711-lpa/src/uart0/fr.rs @@ -1,75 +1,43 @@ #[doc = "Register `FR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CTS` reader - CTS"] -pub type CTS_R = crate::BitReader; +pub type CTS_R = crate::BitReader; #[doc = "Field `CTS` writer - CTS"] -pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type CTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSR` reader - DSR"] -pub type DSR_R = crate::BitReader; +pub type DSR_R = crate::BitReader; #[doc = "Field `DSR` writer - DSR"] -pub type DSR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type DSR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCD` reader - DCD"] -pub type DCD_R = crate::BitReader; +pub type DCD_R = crate::BitReader; #[doc = "Field `DCD` writer - DCD"] -pub type DCD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type DCD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUSY` reader - BUSY"] -pub type BUSY_R = crate::BitReader; +pub type BUSY_R = crate::BitReader; #[doc = "Field `BUSY` writer - BUSY"] -pub type BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type BUSY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFE` reader - RXFE"] -pub type RXFE_R = crate::BitReader; +pub type RXFE_R = crate::BitReader; #[doc = "Field `RXFE` writer - RXFE"] -pub type RXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type RXFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFF` reader - TXFF"] -pub type TXFF_R = crate::BitReader; +pub type TXFF_R = crate::BitReader; #[doc = "Field `TXFF` writer - TXFF"] -pub type TXFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type TXFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFF` reader - RXFF"] -pub type RXFF_R = crate::BitReader; +pub type RXFF_R = crate::BitReader; #[doc = "Field `RXFF` writer - RXFF"] -pub type RXFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type RXFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFE` reader - TXFE"] -pub type TXFE_R = crate::BitReader; +pub type TXFE_R = crate::BitReader; #[doc = "Field `TXFE` writer - TXFE"] -pub type TXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type TXFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RI` reader - RI"] -pub type RI_R = crate::BitReader; +pub type RI_R = crate::BitReader; #[doc = "Field `RI` writer - RI"] -pub type RI_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type RI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - CTS"] #[inline(always)] @@ -117,80 +85,101 @@ impl R { RI_R::new(((self.bits >> 8) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FR") + .field("cts", &format_args!("{}", self.cts().bit())) + .field("dsr", &format_args!("{}", self.dsr().bit())) + .field("dcd", &format_args!("{}", self.dcd().bit())) + .field("busy", &format_args!("{}", self.busy().bit())) + .field("rxfe", &format_args!("{}", self.rxfe().bit())) + .field("txff", &format_args!("{}", self.txff().bit())) + .field("rxff", &format_args!("{}", self.rxff().bit())) + .field("txfe", &format_args!("{}", self.txfe().bit())) + .field("ri", &format_args!("{}", self.ri().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - CTS"] #[inline(always)] #[must_use] - pub fn cts(&mut self) -> CTS_W<0> { + pub fn cts(&mut self) -> CTS_W { CTS_W::new(self) } #[doc = "Bit 1 - DSR"] #[inline(always)] #[must_use] - pub fn dsr(&mut self) -> DSR_W<1> { + pub fn dsr(&mut self) -> DSR_W { DSR_W::new(self) } #[doc = "Bit 2 - DCD"] #[inline(always)] #[must_use] - pub fn dcd(&mut self) -> DCD_W<2> { + pub fn dcd(&mut self) -> DCD_W { DCD_W::new(self) } #[doc = "Bit 3 - BUSY"] #[inline(always)] #[must_use] - pub fn busy(&mut self) -> BUSY_W<3> { + pub fn busy(&mut self) -> BUSY_W { BUSY_W::new(self) } #[doc = "Bit 4 - RXFE"] #[inline(always)] #[must_use] - pub fn rxfe(&mut self) -> RXFE_W<4> { + pub fn rxfe(&mut self) -> RXFE_W { RXFE_W::new(self) } #[doc = "Bit 5 - TXFF"] #[inline(always)] #[must_use] - pub fn txff(&mut self) -> TXFF_W<5> { + pub fn txff(&mut self) -> TXFF_W { TXFF_W::new(self) } #[doc = "Bit 6 - RXFF"] #[inline(always)] #[must_use] - pub fn rxff(&mut self) -> RXFF_W<6> { + pub fn rxff(&mut self) -> RXFF_W { RXFF_W::new(self) } #[doc = "Bit 7 - TXFE"] #[inline(always)] #[must_use] - pub fn txfe(&mut self) -> TXFE_W<7> { + pub fn txfe(&mut self) -> TXFE_W { TXFE_W::new(self) } #[doc = "Bit 8 - RI"] #[inline(always)] #[must_use] - pub fn ri(&mut self) -> RI_W<8> { + pub fn ri(&mut self) -> RI_W { RI_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fr](index.html) module"] +#[doc = "Flag Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FR_SPEC; impl crate::RegisterSpec for FR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fr::R](R) reader structure"] -impl crate::Readable for FR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fr::W](W) writer structure"] +#[doc = "`read()` method returns [`fr::R`](R) reader structure"] +impl crate::Readable for FR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fr::W`](W) writer structure"] impl crate::Writable for FR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart0/ibrd.rs b/crates/bcm2711-lpa/src/uart0/ibrd.rs index 65af80e..07441c8 100644 --- a/crates/bcm2711-lpa/src/uart0/ibrd.rs +++ b/crates/bcm2711-lpa/src/uart0/ibrd.rs @@ -1,43 +1,11 @@ #[doc = "Register `IBRD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IBRD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BAUDDIVINT` reader - BAUDDIVINT"] -pub type BAUDDIVINT_R = crate::FieldReader; +pub type BAUDDIVINT_R = crate::FieldReader; #[doc = "Field `BAUDDIVINT` writer - BAUDDIVINT"] -pub type BAUDDIVINT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IBRD_SPEC, u16, u16, 16, O>; +pub type BAUDDIVINT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - BAUDDIVINT"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { BAUDDIVINT_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IBRD") + .field("bauddivint", &format_args!("{}", self.bauddivint().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - BAUDDIVINT"] #[inline(always)] #[must_use] - pub fn bauddivint(&mut self) -> BAUDDIVINT_W<0> { + pub fn bauddivint(&mut self) -> BAUDDIVINT_W { BAUDDIVINT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Integer Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ibrd](index.html) module"] +#[doc = "Integer Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibrd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IBRD_SPEC; impl crate::RegisterSpec for IBRD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ibrd::R](R) reader structure"] -impl crate::Readable for IBRD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ibrd::W](W) writer structure"] +#[doc = "`read()` method returns [`ibrd::R`](R) reader structure"] +impl crate::Readable for IBRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ibrd::W`](W) writer structure"] impl crate::Writable for IBRD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart0/icr.rs b/crates/bcm2711-lpa/src/uart0/icr.rs index 509869e..e69a3e9 100644 --- a/crates/bcm2711-lpa/src/uart0/icr.rs +++ b/crates/bcm2711-lpa/src/uart0/icr.rs @@ -1,128 +1,117 @@ #[doc = "Register `ICR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RIMIC` writer - RIMIC"] -pub type RIMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type RIMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTSMIC` writer - CTSMIC"] -pub type CTSMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type CTSMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCDMIC` writer - DCDMIC"] -pub type DCDMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type DCDMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSRMIC` writer - DSRMIC"] -pub type DSRMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type DSRMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXIC` writer - RXIC"] -pub type RXIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type RXIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXIC` writer - TXIC"] -pub type TXIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type TXIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTIC` writer - RTIC"] -pub type RTIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEIC` writer - FEIC"] -pub type FEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type FEIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEIC` writer - PEIC"] -pub type PEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type PEIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BEIC` writer - BEIC"] -pub type BEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type BEIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEIC` writer - OEIC"] -pub type OEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type OEIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - RIMIC"] #[inline(always)] #[must_use] - pub fn rimic(&mut self) -> RIMIC_W<0> { + pub fn rimic(&mut self) -> RIMIC_W { RIMIC_W::new(self) } #[doc = "Bit 1 - CTSMIC"] #[inline(always)] #[must_use] - pub fn ctsmic(&mut self) -> CTSMIC_W<1> { + pub fn ctsmic(&mut self) -> CTSMIC_W { CTSMIC_W::new(self) } #[doc = "Bit 2 - DCDMIC"] #[inline(always)] #[must_use] - pub fn dcdmic(&mut self) -> DCDMIC_W<2> { + pub fn dcdmic(&mut self) -> DCDMIC_W { DCDMIC_W::new(self) } #[doc = "Bit 3 - DSRMIC"] #[inline(always)] #[must_use] - pub fn dsrmic(&mut self) -> DSRMIC_W<3> { + pub fn dsrmic(&mut self) -> DSRMIC_W { DSRMIC_W::new(self) } #[doc = "Bit 4 - RXIC"] #[inline(always)] #[must_use] - pub fn rxic(&mut self) -> RXIC_W<4> { + pub fn rxic(&mut self) -> RXIC_W { RXIC_W::new(self) } #[doc = "Bit 5 - TXIC"] #[inline(always)] #[must_use] - pub fn txic(&mut self) -> TXIC_W<5> { + pub fn txic(&mut self) -> TXIC_W { TXIC_W::new(self) } #[doc = "Bit 6 - RTIC"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W<6> { + pub fn rtic(&mut self) -> RTIC_W { RTIC_W::new(self) } #[doc = "Bit 7 - FEIC"] #[inline(always)] #[must_use] - pub fn feic(&mut self) -> FEIC_W<7> { + pub fn feic(&mut self) -> FEIC_W { FEIC_W::new(self) } #[doc = "Bit 8 - PEIC"] #[inline(always)] #[must_use] - pub fn peic(&mut self) -> PEIC_W<8> { + pub fn peic(&mut self) -> PEIC_W { PEIC_W::new(self) } #[doc = "Bit 9 - BEIC"] #[inline(always)] #[must_use] - pub fn beic(&mut self) -> BEIC_W<9> { + pub fn beic(&mut self) -> BEIC_W { BEIC_W::new(self) } #[doc = "Bit 10 - OEIC"] #[inline(always)] #[must_use] - pub fn oeic(&mut self) -> OEIC_W<10> { + pub fn oeic(&mut self) -> OEIC_W { OEIC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"] +#[doc = "Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ICR_SPEC; impl crate::RegisterSpec for ICR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [icr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] impl crate::Writable for ICR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart0/ifls.rs b/crates/bcm2711-lpa/src/uart0/ifls.rs index 0cfe8d5..5119af0 100644 --- a/crates/bcm2711-lpa/src/uart0/ifls.rs +++ b/crates/bcm2711-lpa/src/uart0/ifls.rs @@ -1,47 +1,15 @@ #[doc = "Register `IFLS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IFLS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXIFLSEL` reader - TXIFLSEL"] -pub type TXIFLSEL_R = crate::FieldReader; +pub type TXIFLSEL_R = crate::FieldReader; #[doc = "Field `TXIFLSEL` writer - TXIFLSEL"] -pub type TXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFLS_SPEC, u8, u8, 3, O>; +pub type TXIFLSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `RXIFLSEL` reader - RXIFLSEL"] -pub type RXIFLSEL_R = crate::FieldReader; +pub type RXIFLSEL_R = crate::FieldReader; #[doc = "Field `RXIFLSEL` writer - RXIFLSEL"] -pub type RXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFLS_SPEC, u8, u8, 3, O>; +pub type RXIFLSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:2 - TXIFLSEL"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { RXIFLSEL_R::new(((self.bits >> 3) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IFLS") + .field("txiflsel", &format_args!("{}", self.txiflsel().bits())) + .field("rxiflsel", &format_args!("{}", self.rxiflsel().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - TXIFLSEL"] #[inline(always)] #[must_use] - pub fn txiflsel(&mut self) -> TXIFLSEL_W<0> { + pub fn txiflsel(&mut self) -> TXIFLSEL_W { TXIFLSEL_W::new(self) } #[doc = "Bits 3:5 - RXIFLSEL"] #[inline(always)] #[must_use] - pub fn rxiflsel(&mut self) -> RXIFLSEL_W<3> { + pub fn rxiflsel(&mut self) -> RXIFLSEL_W { RXIFLSEL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt FIFO Level Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifls](index.html) module"] +#[doc = "Interrupt FIFO Level Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifls::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifls::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IFLS_SPEC; impl crate::RegisterSpec for IFLS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ifls::R](R) reader structure"] -impl crate::Readable for IFLS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ifls::W](W) writer structure"] +#[doc = "`read()` method returns [`ifls::R`](R) reader structure"] +impl crate::Readable for IFLS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ifls::W`](W) writer structure"] impl crate::Writable for IFLS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart0/imsc.rs b/crates/bcm2711-lpa/src/uart0/imsc.rs index 1b0fb46..80b23a4 100644 --- a/crates/bcm2711-lpa/src/uart0/imsc.rs +++ b/crates/bcm2711-lpa/src/uart0/imsc.rs @@ -1,83 +1,51 @@ #[doc = "Register `IMSC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IMSC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RIMIM` reader - RIMIM"] -pub type RIMIM_R = crate::BitReader; +pub type RIMIM_R = crate::BitReader; #[doc = "Field `RIMIM` writer - RIMIM"] -pub type RIMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type RIMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTSMIM` reader - CTSMIM"] -pub type CTSMIM_R = crate::BitReader; +pub type CTSMIM_R = crate::BitReader; #[doc = "Field `CTSMIM` writer - CTSMIM"] -pub type CTSMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type CTSMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCDMIM` reader - DCDMIM"] -pub type DCDMIM_R = crate::BitReader; +pub type DCDMIM_R = crate::BitReader; #[doc = "Field `DCDMIM` writer - DCDMIM"] -pub type DCDMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type DCDMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSRMIM` reader - DSRMIM"] -pub type DSRMIM_R = crate::BitReader; +pub type DSRMIM_R = crate::BitReader; #[doc = "Field `DSRMIM` writer - DSRMIM"] -pub type DSRMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type DSRMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXIM` reader - RXIM"] -pub type RXIM_R = crate::BitReader; +pub type RXIM_R = crate::BitReader; #[doc = "Field `RXIM` writer - RXIM"] -pub type RXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXIM` reader - TXIM"] -pub type TXIM_R = crate::BitReader; +pub type TXIM_R = crate::BitReader; #[doc = "Field `TXIM` writer - TXIM"] -pub type TXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTIM` reader - RTIM"] -pub type RTIM_R = crate::BitReader; +pub type RTIM_R = crate::BitReader; #[doc = "Field `RTIM` writer - RTIM"] -pub type RTIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEIM` reader - FEIM"] -pub type FEIM_R = crate::BitReader; +pub type FEIM_R = crate::BitReader; #[doc = "Field `FEIM` writer - FEIM"] -pub type FEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type FEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEIM` reader - PEIM"] -pub type PEIM_R = crate::BitReader; +pub type PEIM_R = crate::BitReader; #[doc = "Field `PEIM` writer - PEIM"] -pub type PEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type PEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BEIM` reader - BEIM"] -pub type BEIM_R = crate::BitReader; +pub type BEIM_R = crate::BitReader; #[doc = "Field `BEIM` writer - BEIM"] -pub type BEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type BEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEIM` reader - OEIM"] -pub type OEIM_R = crate::BitReader; +pub type OEIM_R = crate::BitReader; #[doc = "Field `OEIM` writer - OEIM"] -pub type OEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type OEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - RIMIM"] #[inline(always)] @@ -135,92 +103,115 @@ impl R { OEIM_R::new(((self.bits >> 10) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IMSC") + .field("rimim", &format_args!("{}", self.rimim().bit())) + .field("ctsmim", &format_args!("{}", self.ctsmim().bit())) + .field("dcdmim", &format_args!("{}", self.dcdmim().bit())) + .field("dsrmim", &format_args!("{}", self.dsrmim().bit())) + .field("rxim", &format_args!("{}", self.rxim().bit())) + .field("txim", &format_args!("{}", self.txim().bit())) + .field("rtim", &format_args!("{}", self.rtim().bit())) + .field("feim", &format_args!("{}", self.feim().bit())) + .field("peim", &format_args!("{}", self.peim().bit())) + .field("beim", &format_args!("{}", self.beim().bit())) + .field("oeim", &format_args!("{}", self.oeim().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - RIMIM"] #[inline(always)] #[must_use] - pub fn rimim(&mut self) -> RIMIM_W<0> { + pub fn rimim(&mut self) -> RIMIM_W { RIMIM_W::new(self) } #[doc = "Bit 1 - CTSMIM"] #[inline(always)] #[must_use] - pub fn ctsmim(&mut self) -> CTSMIM_W<1> { + pub fn ctsmim(&mut self) -> CTSMIM_W { CTSMIM_W::new(self) } #[doc = "Bit 2 - DCDMIM"] #[inline(always)] #[must_use] - pub fn dcdmim(&mut self) -> DCDMIM_W<2> { + pub fn dcdmim(&mut self) -> DCDMIM_W { DCDMIM_W::new(self) } #[doc = "Bit 3 - DSRMIM"] #[inline(always)] #[must_use] - pub fn dsrmim(&mut self) -> DSRMIM_W<3> { + pub fn dsrmim(&mut self) -> DSRMIM_W { DSRMIM_W::new(self) } #[doc = "Bit 4 - RXIM"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W<4> { + pub fn rxim(&mut self) -> RXIM_W { RXIM_W::new(self) } #[doc = "Bit 5 - TXIM"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W<5> { + pub fn txim(&mut self) -> TXIM_W { TXIM_W::new(self) } #[doc = "Bit 6 - RTIM"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W<6> { + pub fn rtim(&mut self) -> RTIM_W { RTIM_W::new(self) } #[doc = "Bit 7 - FEIM"] #[inline(always)] #[must_use] - pub fn feim(&mut self) -> FEIM_W<7> { + pub fn feim(&mut self) -> FEIM_W { FEIM_W::new(self) } #[doc = "Bit 8 - PEIM"] #[inline(always)] #[must_use] - pub fn peim(&mut self) -> PEIM_W<8> { + pub fn peim(&mut self) -> PEIM_W { PEIM_W::new(self) } #[doc = "Bit 9 - BEIM"] #[inline(always)] #[must_use] - pub fn beim(&mut self) -> BEIM_W<9> { + pub fn beim(&mut self) -> BEIM_W { BEIM_W::new(self) } #[doc = "Bit 10 - OEIM"] #[inline(always)] #[must_use] - pub fn oeim(&mut self) -> OEIM_W<10> { + pub fn oeim(&mut self) -> OEIM_W { OEIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Mask set_Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imsc](index.html) module"] +#[doc = "Interrupt Mask set_Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imsc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMSC_SPEC; impl crate::RegisterSpec for IMSC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imsc::R](R) reader structure"] -impl crate::Readable for IMSC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [imsc::W](W) writer structure"] +#[doc = "`read()` method returns [`imsc::R`](R) reader structure"] +impl crate::Readable for IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`imsc::W`](W) writer structure"] impl crate::Writable for IMSC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart0/lcr_h.rs b/crates/bcm2711-lpa/src/uart0/lcr_h.rs index 6e02317..b6c85cc 100644 --- a/crates/bcm2711-lpa/src/uart0/lcr_h.rs +++ b/crates/bcm2711-lpa/src/uart0/lcr_h.rs @@ -1,67 +1,35 @@ #[doc = "Register `LCR_H` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LCR_H` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BRK` reader - BRK"] -pub type BRK_R = crate::BitReader; +pub type BRK_R = crate::BitReader; #[doc = "Field `BRK` writer - BRK"] -pub type BRK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type BRK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEN` reader - PEN"] -pub type PEN_R = crate::BitReader; +pub type PEN_R = crate::BitReader; #[doc = "Field `PEN` writer - PEN"] -pub type PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPS` reader - EPS"] -pub type EPS_R = crate::BitReader; +pub type EPS_R = crate::BitReader; #[doc = "Field `EPS` writer - EPS"] -pub type EPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STP2` reader - STP2"] -pub type STP2_R = crate::BitReader; +pub type STP2_R = crate::BitReader; #[doc = "Field `STP2` writer - STP2"] -pub type STP2_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type STP2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN` reader - FEN"] -pub type FEN_R = crate::BitReader; +pub type FEN_R = crate::BitReader; #[doc = "Field `FEN` writer - FEN"] -pub type FEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type FEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WLEN` reader - WLEN"] -pub type WLEN_R = crate::FieldReader; +pub type WLEN_R = crate::FieldReader; #[doc = "Field `WLEN` writer - WLEN"] -pub type WLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LCR_H_SPEC, u8, u8, 2, O>; +pub type WLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `SPS` reader - SPS"] -pub type SPS_R = crate::BitReader; +pub type SPS_R = crate::BitReader; #[doc = "Field `SPS` writer - SPS"] -pub type SPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type SPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - BRK"] #[inline(always)] @@ -99,68 +67,87 @@ impl R { SPS_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCR_H") + .field("brk", &format_args!("{}", self.brk().bit())) + .field("pen", &format_args!("{}", self.pen().bit())) + .field("eps", &format_args!("{}", self.eps().bit())) + .field("stp2", &format_args!("{}", self.stp2().bit())) + .field("fen", &format_args!("{}", self.fen().bit())) + .field("wlen", &format_args!("{}", self.wlen().bits())) + .field("sps", &format_args!("{}", self.sps().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - BRK"] #[inline(always)] #[must_use] - pub fn brk(&mut self) -> BRK_W<0> { + pub fn brk(&mut self) -> BRK_W { BRK_W::new(self) } #[doc = "Bit 1 - PEN"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W<1> { + pub fn pen(&mut self) -> PEN_W { PEN_W::new(self) } #[doc = "Bit 2 - EPS"] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W<2> { + pub fn eps(&mut self) -> EPS_W { EPS_W::new(self) } #[doc = "Bit 3 - STP2"] #[inline(always)] #[must_use] - pub fn stp2(&mut self) -> STP2_W<3> { + pub fn stp2(&mut self) -> STP2_W { STP2_W::new(self) } #[doc = "Bit 4 - FEN"] #[inline(always)] #[must_use] - pub fn fen(&mut self) -> FEN_W<4> { + pub fn fen(&mut self) -> FEN_W { FEN_W::new(self) } #[doc = "Bits 5:6 - WLEN"] #[inline(always)] #[must_use] - pub fn wlen(&mut self) -> WLEN_W<5> { + pub fn wlen(&mut self) -> WLEN_W { WLEN_W::new(self) } #[doc = "Bit 7 - SPS"] #[inline(always)] #[must_use] - pub fn sps(&mut self) -> SPS_W<7> { + pub fn sps(&mut self) -> SPS_W { SPS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Line Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr_h](index.html) module"] +#[doc = "Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr_h::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr_h::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LCR_H_SPEC; impl crate::RegisterSpec for LCR_H_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lcr_h::R](R) reader structure"] -impl crate::Readable for LCR_H_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [lcr_h::W](W) writer structure"] +#[doc = "`read()` method returns [`lcr_h::R`](R) reader structure"] +impl crate::Readable for LCR_H_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcr_h::W`](W) writer structure"] impl crate::Writable for LCR_H_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart0/mis.rs b/crates/bcm2711-lpa/src/uart0/mis.rs index ce802e5..8ecfc00 100644 --- a/crates/bcm2711-lpa/src/uart0/mis.rs +++ b/crates/bcm2711-lpa/src/uart0/mis.rs @@ -1,40 +1,27 @@ #[doc = "Register `MIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RIMMIS` reader - RIMMIS"] -pub type RIMMIS_R = crate::BitReader; +pub type RIMMIS_R = crate::BitReader; #[doc = "Field `CTSMMIS` reader - CTSMMIS"] -pub type CTSMMIS_R = crate::BitReader; +pub type CTSMMIS_R = crate::BitReader; #[doc = "Field `DCDMMIS` reader - DCDMMIS"] -pub type DCDMMIS_R = crate::BitReader; +pub type DCDMMIS_R = crate::BitReader; #[doc = "Field `DSRMMIS` reader - DSRMMIS"] -pub type DSRMMIS_R = crate::BitReader; +pub type DSRMMIS_R = crate::BitReader; #[doc = "Field `RXMIS` reader - RXMIS"] -pub type RXMIS_R = crate::BitReader; +pub type RXMIS_R = crate::BitReader; #[doc = "Field `TXMIS` reader - TXMIS"] -pub type TXMIS_R = crate::BitReader; +pub type TXMIS_R = crate::BitReader; #[doc = "Field `RTMIS` reader - RTMIS"] -pub type RTMIS_R = crate::BitReader; +pub type RTMIS_R = crate::BitReader; #[doc = "Field `FEMIS` reader - FEMIS"] -pub type FEMIS_R = crate::BitReader; +pub type FEMIS_R = crate::BitReader; #[doc = "Field `PEMIS` reader - PEMIS"] -pub type PEMIS_R = crate::BitReader; +pub type PEMIS_R = crate::BitReader; #[doc = "Field `BEMIS` reader - BEMIS"] -pub type BEMIS_R = crate::BitReader; +pub type BEMIS_R = crate::BitReader; #[doc = "Field `OEMIS` reader - OEMIS"] -pub type OEMIS_R = crate::BitReader; +pub type OEMIS_R = crate::BitReader; impl R { #[doc = "Bit 0 - RIMMIS"] #[inline(always)] @@ -92,15 +79,35 @@ impl R { OEMIS_R::new(((self.bits >> 10) & 1) != 0) } } -#[doc = "Masked Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mis](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MIS") + .field("rimmis", &format_args!("{}", self.rimmis().bit())) + .field("ctsmmis", &format_args!("{}", self.ctsmmis().bit())) + .field("dcdmmis", &format_args!("{}", self.dcdmmis().bit())) + .field("dsrmmis", &format_args!("{}", self.dsrmmis().bit())) + .field("rxmis", &format_args!("{}", self.rxmis().bit())) + .field("txmis", &format_args!("{}", self.txmis().bit())) + .field("rtmis", &format_args!("{}", self.rtmis().bit())) + .field("femis", &format_args!("{}", self.femis().bit())) + .field("pemis", &format_args!("{}", self.pemis().bit())) + .field("bemis", &format_args!("{}", self.bemis().bit())) + .field("oemis", &format_args!("{}", self.oemis().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Masked Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MIS_SPEC; impl crate::RegisterSpec for MIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mis::R](R) reader structure"] -impl crate::Readable for MIS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`mis::R`](R) reader structure"] +impl crate::Readable for MIS_SPEC {} #[doc = "`reset()` method sets MIS to value 0"] impl crate::Resettable for MIS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/uart0/ris.rs b/crates/bcm2711-lpa/src/uart0/ris.rs index 0ab6b9d..9da59ba 100644 --- a/crates/bcm2711-lpa/src/uart0/ris.rs +++ b/crates/bcm2711-lpa/src/uart0/ris.rs @@ -1,40 +1,27 @@ #[doc = "Register `RIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RIRMIS` reader - RIRMIS"] -pub type RIRMIS_R = crate::BitReader; +pub type RIRMIS_R = crate::BitReader; #[doc = "Field `CTSRMIS` reader - CTSRMIS"] -pub type CTSRMIS_R = crate::BitReader; +pub type CTSRMIS_R = crate::BitReader; #[doc = "Field `DCDRMIS` reader - DCDRMIS"] -pub type DCDRMIS_R = crate::BitReader; +pub type DCDRMIS_R = crate::BitReader; #[doc = "Field `DSRRMIS` reader - DSRRMIS"] -pub type DSRRMIS_R = crate::BitReader; +pub type DSRRMIS_R = crate::BitReader; #[doc = "Field `RXRIS` reader - RXRIS"] -pub type RXRIS_R = crate::BitReader; +pub type RXRIS_R = crate::BitReader; #[doc = "Field `TXRIS` reader - TXRIS"] -pub type TXRIS_R = crate::BitReader; +pub type TXRIS_R = crate::BitReader; #[doc = "Field `RTRIS` reader - RTRIS"] -pub type RTRIS_R = crate::BitReader; +pub type RTRIS_R = crate::BitReader; #[doc = "Field `FERIS` reader - FERIS"] -pub type FERIS_R = crate::BitReader; +pub type FERIS_R = crate::BitReader; #[doc = "Field `PERIS` reader - PERIS"] -pub type PERIS_R = crate::BitReader; +pub type PERIS_R = crate::BitReader; #[doc = "Field `BERIS` reader - BERIS"] -pub type BERIS_R = crate::BitReader; +pub type BERIS_R = crate::BitReader; #[doc = "Field `OERIS` reader - OERIS"] -pub type OERIS_R = crate::BitReader; +pub type OERIS_R = crate::BitReader; impl R { #[doc = "Bit 0 - RIRMIS"] #[inline(always)] @@ -92,15 +79,35 @@ impl R { OERIS_R::new(((self.bits >> 10) & 1) != 0) } } -#[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ris](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RIS") + .field("rirmis", &format_args!("{}", self.rirmis().bit())) + .field("ctsrmis", &format_args!("{}", self.ctsrmis().bit())) + .field("dcdrmis", &format_args!("{}", self.dcdrmis().bit())) + .field("dsrrmis", &format_args!("{}", self.dsrrmis().bit())) + .field("rxris", &format_args!("{}", self.rxris().bit())) + .field("txris", &format_args!("{}", self.txris().bit())) + .field("rtris", &format_args!("{}", self.rtris().bit())) + .field("feris", &format_args!("{}", self.feris().bit())) + .field("peris", &format_args!("{}", self.peris().bit())) + .field("beris", &format_args!("{}", self.beris().bit())) + .field("oeris", &format_args!("{}", self.oeris().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Raw Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RIS_SPEC; impl crate::RegisterSpec for RIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ris::R](R) reader structure"] -impl crate::Readable for RIS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ris::R`](R) reader structure"] +impl crate::Readable for RIS_SPEC {} #[doc = "`reset()` method sets RIS to value 0"] impl crate::Resettable for RIS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/uart0/rsr.rs b/crates/bcm2711-lpa/src/uart0/rsr.rs index 90a9e0d..524d503 100644 --- a/crates/bcm2711-lpa/src/uart0/rsr.rs +++ b/crates/bcm2711-lpa/src/uart0/rsr.rs @@ -1,26 +1,13 @@ #[doc = "Register `RSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FE` reader - FE"] -pub type FE_R = crate::BitReader; +pub type FE_R = crate::BitReader; #[doc = "Field `PE` reader - PE"] -pub type PE_R = crate::BitReader; +pub type PE_R = crate::BitReader; #[doc = "Field `BE` reader - BE"] -pub type BE_R = crate::BitReader; +pub type BE_R = crate::BitReader; #[doc = "Field `OE` reader - OE"] -pub type OE_R = crate::BitReader; +pub type OE_R = crate::BitReader; impl R { #[doc = "Bit 0 - FE"] #[inline(always)] @@ -43,15 +30,28 @@ impl R { OE_R::new(((self.bits >> 3) & 1) != 0) } } -#[doc = "Receive Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rsr](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSR") + .field("fe", &format_args!("{}", self.fe().bit())) + .field("pe", &format_args!("{}", self.pe().bit())) + .field("be", &format_args!("{}", self.be().bit())) + .field("oe", &format_args!("{}", self.oe().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Receive Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSR_SPEC; impl crate::RegisterSpec for RSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rsr::R](R) reader structure"] -impl crate::Readable for RSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rsr::R`](R) reader structure"] +impl crate::Readable for RSR_SPEC {} #[doc = "`reset()` method sets RSR to value 0"] impl crate::Resettable for RSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/uart1.rs b/crates/bcm2711-lpa/src/uart1.rs index a87a1e5..7cc03cc 100644 --- a/crates/bcm2711-lpa/src/uart1.rs +++ b/crates/bcm2711-lpa/src/uart1.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { _reserved_0_io: [u8; 0x04], _reserved_1_ier: [u8; 0x04], @@ -45,55 +46,68 @@ impl RegisterBlock { unsafe { &*(self as *const Self).cast::().add(4usize).cast() } } } -#[doc = "IO (rw) register accessor: an alias for `Reg`"] +#[doc = "IO (rw) register accessor: I/O Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io`] +module"] pub type IO = crate::Reg; #[doc = "I/O Data"] pub mod io; -#[doc = "BAUDL (rw) register accessor: an alias for `Reg`"] +#[doc = "BAUDL (rw) register accessor: Lower bits of baudrate when DLAB is set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baudl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baudl`] +module"] pub type BAUDL = crate::Reg; #[doc = "Lower bits of baudrate when DLAB is set"] pub mod baudl; -#[doc = "IER (rw) register accessor: an alias for `Reg`"] +#[doc = "IER (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable"] pub mod ier; -#[doc = "BAUDH (rw) register accessor: an alias for `Reg`"] +#[doc = "BAUDH (rw) register accessor: High bits of baudrate when DLAB is set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baudh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baudh`] +module"] pub type BAUDH = crate::Reg; #[doc = "High bits of baudrate when DLAB is set"] pub mod baudh; -#[doc = "IIR (rw) register accessor: an alias for `Reg`"] +#[doc = "IIR (rw) register accessor: Interrupt Identify\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] +module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identify"] pub mod iir; -#[doc = "LCR (rw) register accessor: an alias for `Reg`"] +#[doc = "LCR (rw) register accessor: Line control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] +module"] pub type LCR = crate::Reg; #[doc = "Line control"] pub mod lcr; -#[doc = "MCR (rw) register accessor: an alias for `Reg`"] +#[doc = "MCR (rw) register accessor: Modem Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] +module"] pub type MCR = crate::Reg; #[doc = "Modem Control"] pub mod mcr; -#[doc = "LSR (rw) register accessor: an alias for `Reg`"] +#[doc = "LSR (rw) register accessor: Line Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] +module"] pub type LSR = crate::Reg; #[doc = "Line Status"] pub mod lsr; -#[doc = "MSR (rw) register accessor: an alias for `Reg`"] +#[doc = "MSR (rw) register accessor: Modem Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] +module"] pub type MSR = crate::Reg; #[doc = "Modem Status"] pub mod msr; -#[doc = "SCRATCH (rw) register accessor: an alias for `Reg`"] +#[doc = "SCRATCH (rw) register accessor: Scratch\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scratch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scratch`] +module"] pub type SCRATCH = crate::Reg; #[doc = "Scratch"] pub mod scratch; -#[doc = "CNTL (rw) register accessor: an alias for `Reg`"] +#[doc = "CNTL (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntl`] +module"] pub type CNTL = crate::Reg; #[doc = "Control"] pub mod cntl; -#[doc = "STAT (rw) register accessor: an alias for `Reg`"] +#[doc = "STAT (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] +module"] pub type STAT = crate::Reg; #[doc = "Status"] pub mod stat; -#[doc = "BAUD (rw) register accessor: an alias for `Reg`"] +#[doc = "BAUD (rw) register accessor: Baudrate\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baud::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baud::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baud`] +module"] pub type BAUD = crate::Reg; #[doc = "Baudrate"] pub mod baud; diff --git a/crates/bcm2711-lpa/src/uart1/baud.rs b/crates/bcm2711-lpa/src/uart1/baud.rs index 088c774..4cc37c7 100644 --- a/crates/bcm2711-lpa/src/uart1/baud.rs +++ b/crates/bcm2711-lpa/src/uart1/baud.rs @@ -1,59 +1,38 @@ #[doc = "Register `BAUD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BAUD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Baudrate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +#[doc = "Baudrate\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baud::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baud::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BAUD_SPEC; impl crate::RegisterSpec for BAUD_SPEC { type Ux = u16; } -#[doc = "`read()` method returns [baud::R](R) reader structure"] -impl crate::Readable for BAUD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +#[doc = "`read()` method returns [`baud::R`](R) reader structure"] +impl crate::Readable for BAUD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`baud::W`](W) writer structure"] impl crate::Writable for BAUD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart1/baudh.rs b/crates/bcm2711-lpa/src/uart1/baudh.rs index 8c30695..aa2fa88 100644 --- a/crates/bcm2711-lpa/src/uart1/baudh.rs +++ b/crates/bcm2711-lpa/src/uart1/baudh.rs @@ -1,59 +1,38 @@ #[doc = "Register `BAUDH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BAUDH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "High bits of baudrate when DLAB is set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudh](index.html) module"] +#[doc = "High bits of baudrate when DLAB is set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baudh::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BAUDH_SPEC; impl crate::RegisterSpec for BAUDH_SPEC { type Ux = u8; } -#[doc = "`read()` method returns [baudh::R](R) reader structure"] -impl crate::Readable for BAUDH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [baudh::W](W) writer structure"] +#[doc = "`read()` method returns [`baudh::R`](R) reader structure"] +impl crate::Readable for BAUDH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`baudh::W`](W) writer structure"] impl crate::Writable for BAUDH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart1/baudl.rs b/crates/bcm2711-lpa/src/uart1/baudl.rs index ca7c9f0..a9c9850 100644 --- a/crates/bcm2711-lpa/src/uart1/baudl.rs +++ b/crates/bcm2711-lpa/src/uart1/baudl.rs @@ -1,59 +1,38 @@ #[doc = "Register `BAUDL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BAUDL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Lower bits of baudrate when DLAB is set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudl](index.html) module"] +#[doc = "Lower bits of baudrate when DLAB is set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baudl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BAUDL_SPEC; impl crate::RegisterSpec for BAUDL_SPEC { type Ux = u8; } -#[doc = "`read()` method returns [baudl::R](R) reader structure"] -impl crate::Readable for BAUDL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [baudl::W](W) writer structure"] +#[doc = "`read()` method returns [`baudl::R`](R) reader structure"] +impl crate::Readable for BAUDL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`baudl::W`](W) writer structure"] impl crate::Writable for BAUDL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart1/cntl.rs b/crates/bcm2711-lpa/src/uart1/cntl.rs index 4125093..ca942f3 100644 --- a/crates/bcm2711-lpa/src/uart1/cntl.rs +++ b/crates/bcm2711-lpa/src/uart1/cntl.rs @@ -1,57 +1,25 @@ #[doc = "Register `CNTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CNTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RX_ENABLE` reader - Enable receive"] -pub type RX_ENABLE_R = crate::BitReader; +pub type RX_ENABLE_R = crate::BitReader; #[doc = "Field `RX_ENABLE` writer - Enable receive"] -pub type RX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +pub type RX_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_ENABLE` reader - Enable transmit"] -pub type TX_ENABLE_R = crate::BitReader; +pub type TX_ENABLE_R = crate::BitReader; #[doc = "Field `TX_ENABLE` writer - Enable transmit"] -pub type TX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +pub type TX_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTS_ENABLE` reader - Enable auto receive flow control with RTS"] -pub type RTS_ENABLE_R = crate::BitReader; +pub type RTS_ENABLE_R = crate::BitReader; #[doc = "Field `RTS_ENABLE` writer - Enable auto receive flow control with RTS"] -pub type RTS_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +pub type RTS_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTS_ENABLE` reader - Enable auto transmit flow control with CTS"] -pub type CTS_ENABLE_R = crate::BitReader; +pub type CTS_ENABLE_R = crate::BitReader; #[doc = "Field `CTS_ENABLE` writer - Enable auto transmit flow control with CTS"] -pub type CTS_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +pub type CTS_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTS_FIFO_LEVEL` reader - FIFO level to de-assert RTS"] -pub type RTS_FIFO_LEVEL_R = crate::FieldReader; +pub type RTS_FIFO_LEVEL_R = crate::FieldReader; #[doc = "FIFO level to de-assert RTS\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -71,10 +39,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FIFO_LEVEL_A { + type Ux = u8; +} impl RTS_FIFO_LEVEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FIFO_LEVEL_A { + pub const fn variant(&self) -> FIFO_LEVEL_A { match self.bits { 0 => FIFO_LEVEL_A::_3EMPTY, 1 => FIFO_LEVEL_A::_2EMPTY, @@ -83,49 +54,53 @@ impl RTS_FIFO_LEVEL_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_3EMPTY`"] + #[doc = "3 empty spaces"] #[inline(always)] pub fn is_3empty(&self) -> bool { *self == FIFO_LEVEL_A::_3EMPTY } - #[doc = "Checks if the value of the field is `_2EMPTY`"] + #[doc = "2 empty spaces"] #[inline(always)] pub fn is_2empty(&self) -> bool { *self == FIFO_LEVEL_A::_2EMPTY } - #[doc = "Checks if the value of the field is `_1EMPTY`"] + #[doc = "1 empty spaces"] #[inline(always)] pub fn is_1empty(&self) -> bool { *self == FIFO_LEVEL_A::_1EMPTY } - #[doc = "Checks if the value of the field is `_4EMPTY`"] + #[doc = "4 empty spaces"] #[inline(always)] pub fn is_4empty(&self) -> bool { *self == FIFO_LEVEL_A::_4EMPTY } } #[doc = "Field `RTS_FIFO_LEVEL` writer - FIFO level to de-assert RTS"] -pub type RTS_FIFO_LEVEL_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, CNTL_SPEC, u8, FIFO_LEVEL_A, 2, O>; -impl<'a, const O: u8> RTS_FIFO_LEVEL_W<'a, O> { +pub type RTS_FIFO_LEVEL_W<'a, REG, const O: u8> = + crate::FieldWriterSafe<'a, REG, 2, O, FIFO_LEVEL_A>; +impl<'a, REG, const O: u8> RTS_FIFO_LEVEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "3 empty spaces"] #[inline(always)] - pub fn _3empty(self) -> &'a mut W { + pub fn _3empty(self) -> &'a mut crate::W { self.variant(FIFO_LEVEL_A::_3EMPTY) } #[doc = "2 empty spaces"] #[inline(always)] - pub fn _2empty(self) -> &'a mut W { + pub fn _2empty(self) -> &'a mut crate::W { self.variant(FIFO_LEVEL_A::_2EMPTY) } #[doc = "1 empty spaces"] #[inline(always)] - pub fn _1empty(self) -> &'a mut W { + pub fn _1empty(self) -> &'a mut crate::W { self.variant(FIFO_LEVEL_A::_1EMPTY) } #[doc = "4 empty spaces"] #[inline(always)] - pub fn _4empty(self) -> &'a mut W { + pub fn _4empty(self) -> &'a mut crate::W { self.variant(FIFO_LEVEL_A::_4EMPTY) } } @@ -152,34 +127,37 @@ impl From for bool { impl CTS_ASSERT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ASSERT_LEVEL_A { + pub const fn variant(&self) -> ASSERT_LEVEL_A { match self.bits { false => ASSERT_LEVEL_A::HIGH, true => ASSERT_LEVEL_A::LOW, } } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "Assert high"] #[inline(always)] pub fn is_high(&self) -> bool { *self == ASSERT_LEVEL_A::HIGH } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "Assert low"] #[inline(always)] pub fn is_low(&self) -> bool { *self == ASSERT_LEVEL_A::LOW } } #[doc = "Field `CTS_ASSERT` writer - CTS assert level"] -pub type CTS_ASSERT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, ASSERT_LEVEL_A, O>; -impl<'a, const O: u8> CTS_ASSERT_W<'a, O> { +pub type CTS_ASSERT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ASSERT_LEVEL_A>; +impl<'a, REG, const O: u8> CTS_ASSERT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Assert high"] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(ASSERT_LEVEL_A::HIGH) } #[doc = "Assert low"] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(ASSERT_LEVEL_A::LOW) } } @@ -220,68 +198,90 @@ impl R { CTS_ASSERT_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CNTL") + .field("cts_assert", &format_args!("{}", self.cts_assert().bit())) + .field("rts_assert", &format_args!("{}", self.rts_assert().bit())) + .field( + "rts_fifo_level", + &format_args!("{}", self.rts_fifo_level().bits()), + ) + .field("cts_enable", &format_args!("{}", self.cts_enable().bit())) + .field("rts_enable", &format_args!("{}", self.rts_enable().bit())) + .field("tx_enable", &format_args!("{}", self.tx_enable().bit())) + .field("rx_enable", &format_args!("{}", self.rx_enable().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable receive"] #[inline(always)] #[must_use] - pub fn rx_enable(&mut self) -> RX_ENABLE_W<0> { + pub fn rx_enable(&mut self) -> RX_ENABLE_W { RX_ENABLE_W::new(self) } #[doc = "Bit 1 - Enable transmit"] #[inline(always)] #[must_use] - pub fn tx_enable(&mut self) -> TX_ENABLE_W<1> { + pub fn tx_enable(&mut self) -> TX_ENABLE_W { TX_ENABLE_W::new(self) } #[doc = "Bit 2 - Enable auto receive flow control with RTS"] #[inline(always)] #[must_use] - pub fn rts_enable(&mut self) -> RTS_ENABLE_W<2> { + pub fn rts_enable(&mut self) -> RTS_ENABLE_W { RTS_ENABLE_W::new(self) } #[doc = "Bit 3 - Enable auto transmit flow control with CTS"] #[inline(always)] #[must_use] - pub fn cts_enable(&mut self) -> CTS_ENABLE_W<3> { + pub fn cts_enable(&mut self) -> CTS_ENABLE_W { CTS_ENABLE_W::new(self) } #[doc = "Bits 4:5 - FIFO level to de-assert RTS"] #[inline(always)] #[must_use] - pub fn rts_fifo_level(&mut self) -> RTS_FIFO_LEVEL_W<4> { + pub fn rts_fifo_level(&mut self) -> RTS_FIFO_LEVEL_W { RTS_FIFO_LEVEL_W::new(self) } #[doc = "Bit 6 - RTS assert level"] #[inline(always)] #[must_use] - pub fn rts_assert(&mut self) -> RTS_ASSERT_W<6> { + pub fn rts_assert(&mut self) -> RTS_ASSERT_W { RTS_ASSERT_W::new(self) } #[doc = "Bit 7 - CTS assert level"] #[inline(always)] #[must_use] - pub fn cts_assert(&mut self) -> CTS_ASSERT_W<7> { + pub fn cts_assert(&mut self) -> CTS_ASSERT_W { CTS_ASSERT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CNTL_SPEC; impl crate::RegisterSpec for CNTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cntl::R](R) reader structure"] -impl crate::Readable for CNTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cntl::W](W) writer structure"] +#[doc = "`read()` method returns [`cntl::R`](R) reader structure"] +impl crate::Readable for CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cntl::W`](W) writer structure"] impl crate::Writable for CNTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart1/ier.rs b/crates/bcm2711-lpa/src/uart1/ier.rs index 450afd5..f3188e7 100644 --- a/crates/bcm2711-lpa/src/uart1/ier.rs +++ b/crates/bcm2711-lpa/src/uart1/ier.rs @@ -1,47 +1,15 @@ #[doc = "Register `IER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA_READY` reader - Receive FIFO has at least 1 byte"] -pub type DATA_READY_R = crate::BitReader; +pub type DATA_READY_R = crate::BitReader; #[doc = "Field `DATA_READY` writer - Receive FIFO has at least 1 byte"] -pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>; +pub type DATA_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_READY` reader - Transmit FIFO is empty"] -pub type TX_READY_R = crate::BitReader; +pub type TX_READY_R = crate::BitReader; #[doc = "Field `TX_READY` writer - Transmit FIFO is empty"] -pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>; +pub type TX_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Receive FIFO has at least 1 byte"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { TX_READY_R::new(((self.bits >> 1) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IER") + .field("tx_ready", &format_args!("{}", self.tx_ready().bit())) + .field("data_ready", &format_args!("{}", self.data_ready().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Receive FIFO has at least 1 byte"] #[inline(always)] #[must_use] - pub fn data_ready(&mut self) -> DATA_READY_W<0> { + pub fn data_ready(&mut self) -> DATA_READY_W { DATA_READY_W::new(self) } #[doc = "Bit 1 - Transmit FIFO is empty"] #[inline(always)] #[must_use] - pub fn tx_ready(&mut self) -> TX_READY_W<1> { + pub fn tx_ready(&mut self) -> TX_READY_W { TX_READY_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ier::R](R) reader structure"] -impl crate::Readable for IER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`read()` method returns [`ier::R`](R) reader structure"] +impl crate::Readable for IER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart1/iir.rs b/crates/bcm2711-lpa/src/uart1/iir.rs index 6f66eac..b7a876b 100644 --- a/crates/bcm2711-lpa/src/uart1/iir.rs +++ b/crates/bcm2711-lpa/src/uart1/iir.rs @@ -1,51 +1,19 @@ #[doc = "Register `IIR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IIR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `nPENDING` reader - No pending interrupt"] -pub type N_PENDING_R = crate::BitReader; +pub type N_PENDING_R = crate::BitReader; #[doc = "Field `nPENDING` writer - No pending interrupt"] -pub type N_PENDING_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +pub type N_PENDING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_READY` reader - Receive FIFO has at least 1 byte"] -pub type DATA_READY_R = crate::BitReader; +pub type DATA_READY_R = crate::BitReader; #[doc = "Field `DATA_READY` writer - Receive FIFO has at least 1 byte"] -pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +pub type DATA_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_READY` reader - Transmit FIFO is empty"] -pub type TX_READY_R = crate::BitReader; +pub type TX_READY_R = crate::BitReader; #[doc = "Field `TX_READY` writer - Transmit FIFO is empty"] -pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +pub type TX_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - No pending interrupt"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { TX_READY_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IIR") + .field("tx_ready", &format_args!("{}", self.tx_ready().bit())) + .field("data_ready", &format_args!("{}", self.data_ready().bit())) + .field("n_pending", &format_args!("{}", self.n_pending().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - No pending interrupt"] #[inline(always)] #[must_use] - pub fn n_pending(&mut self) -> N_PENDING_W<0> { + pub fn n_pending(&mut self) -> N_PENDING_W { N_PENDING_W::new(self) } #[doc = "Bit 1 - Receive FIFO has at least 1 byte"] #[inline(always)] #[must_use] - pub fn data_ready(&mut self) -> DATA_READY_W<1> { + pub fn data_ready(&mut self) -> DATA_READY_W { DATA_READY_W::new(self) } #[doc = "Bit 2 - Transmit FIFO is empty"] #[inline(always)] #[must_use] - pub fn tx_ready(&mut self) -> TX_READY_W<2> { + pub fn tx_ready(&mut self) -> TX_READY_W { TX_READY_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Identify\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iir](index.html) module"] +#[doc = "Interrupt Identify\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IIR_SPEC; impl crate::RegisterSpec for IIR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [iir::R](R) reader structure"] -impl crate::Readable for IIR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [iir::W](W) writer structure"] +#[doc = "`read()` method returns [`iir::R`](R) reader structure"] +impl crate::Readable for IIR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`iir::W`](W) writer structure"] impl crate::Writable for IIR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart1/io.rs b/crates/bcm2711-lpa/src/uart1/io.rs index 84cd075..1873e08 100644 --- a/crates/bcm2711-lpa/src/uart1/io.rs +++ b/crates/bcm2711-lpa/src/uart1/io.rs @@ -1,43 +1,11 @@ #[doc = "Register `IO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IO` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - FIFO access"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - FIFO access"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO_SPEC, u8, u8, 8, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - FIFO access"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new((self.bits & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IO") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - FIFO access"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "I/O Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](index.html) module"] +#[doc = "I/O Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IO_SPEC; impl crate::RegisterSpec for IO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [io::R](R) reader structure"] -impl crate::Readable for IO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [io::W](W) writer structure"] +#[doc = "`read()` method returns [`io::R`](R) reader structure"] +impl crate::Readable for IO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`io::W`](W) writer structure"] impl crate::Writable for IO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart1/lcr.rs b/crates/bcm2711-lpa/src/uart1/lcr.rs index 16b3c2b..38e7d1e 100644 --- a/crates/bcm2711-lpa/src/uart1/lcr.rs +++ b/crates/bcm2711-lpa/src/uart1/lcr.rs @@ -1,41 +1,9 @@ #[doc = "Register `LCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA_SIZE` reader - UART word size"] -pub type DATA_SIZE_R = crate::FieldReader; +pub type DATA_SIZE_R = crate::FieldReader; #[doc = "UART word size\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -51,49 +19,56 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for MODE_A { + type Ux = u8; +} impl DATA_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(MODE_A::_7BIT), 3 => Some(MODE_A::_8BIT), _ => None, } } - #[doc = "Checks if the value of the field is `_7BIT`"] + #[doc = "7 bit"] #[inline(always)] pub fn is_7bit(&self) -> bool { *self == MODE_A::_7BIT } - #[doc = "Checks if the value of the field is `_8BIT`"] + #[doc = "8 bit"] #[inline(always)] pub fn is_8bit(&self) -> bool { *self == MODE_A::_8BIT } } #[doc = "Field `DATA_SIZE` writer - UART word size"] -pub type DATA_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LCR_SPEC, u8, MODE_A, 2, O>; -impl<'a, const O: u8> DATA_SIZE_W<'a, O> { +pub type DATA_SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, MODE_A>; +impl<'a, REG, const O: u8> DATA_SIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "7 bit"] #[inline(always)] - pub fn _7bit(self) -> &'a mut W { + pub fn _7bit(self) -> &'a mut crate::W { self.variant(MODE_A::_7BIT) } #[doc = "8 bit"] #[inline(always)] - pub fn _8bit(self) -> &'a mut W { + pub fn _8bit(self) -> &'a mut crate::W { self.variant(MODE_A::_8BIT) } } #[doc = "Field `BREAK` reader - Pull TX low continuously to send break"] -pub type BREAK_R = crate::BitReader; +pub type BREAK_R = crate::BitReader; #[doc = "Field `BREAK` writer - Pull TX low continuously to send break"] -pub type BREAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_SPEC, bool, O>; +pub type BREAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DLAB` reader - First two registers are baudrate"] -pub type DLAB_R = crate::BitReader; +pub type DLAB_R = crate::BitReader; #[doc = "Field `DLAB` writer - First two registers are baudrate"] -pub type DLAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_SPEC, bool, O>; +pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:1 - UART word size"] #[inline(always)] @@ -111,44 +86,59 @@ impl R { DLAB_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCR") + .field("dlab", &format_args!("{}", self.dlab().bit())) + .field("break_", &format_args!("{}", self.break_().bit())) + .field("data_size", &format_args!("{}", self.data_size().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - UART word size"] #[inline(always)] #[must_use] - pub fn data_size(&mut self) -> DATA_SIZE_W<0> { + pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W::new(self) } #[doc = "Bit 6 - Pull TX low continuously to send break"] #[inline(always)] #[must_use] - pub fn break_(&mut self) -> BREAK_W<6> { + pub fn break_(&mut self) -> BREAK_W { BREAK_W::new(self) } #[doc = "Bit 7 - First two registers are baudrate"] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W<7> { + pub fn dlab(&mut self) -> DLAB_W { DLAB_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Line control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr](index.html) module"] +#[doc = "Line control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LCR_SPEC; impl crate::RegisterSpec for LCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lcr::R](R) reader structure"] -impl crate::Readable for LCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [lcr::W](W) writer structure"] +#[doc = "`read()` method returns [`lcr::R`](R) reader structure"] +impl crate::Readable for LCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcr::W`](W) writer structure"] impl crate::Writable for LCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart1/lsr.rs b/crates/bcm2711-lpa/src/uart1/lsr.rs index ba34ba7..83455e7 100644 --- a/crates/bcm2711-lpa/src/uart1/lsr.rs +++ b/crates/bcm2711-lpa/src/uart1/lsr.rs @@ -1,55 +1,23 @@ #[doc = "Register `LSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA_READY` reader - Receive FIFO has at least one byte"] -pub type DATA_READY_R = crate::BitReader; +pub type DATA_READY_R = crate::BitReader; #[doc = "Field `DATA_READY` writer - Receive FIFO has at least one byte"] -pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +pub type DATA_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_OVERRUN` reader - Receive FIFO overrun"] -pub type RX_OVERRUN_R = crate::BitReader; +pub type RX_OVERRUN_R = crate::BitReader; #[doc = "Field `RX_OVERRUN` writer - Receive FIFO overrun"] -pub type RX_OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +pub type RX_OVERRUN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_EMPTY` reader - Transmit FIFO has room for at least one byte"] -pub type TX_EMPTY_R = crate::BitReader; +pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `TX_EMPTY` writer - Transmit FIFO has room for at least one byte"] -pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_IDLE` reader - Transmit FIFO empty and all bits shifted out"] -pub type TX_IDLE_R = crate::BitReader; +pub type TX_IDLE_R = crate::BitReader; #[doc = "Field `TX_IDLE` writer - Transmit FIFO empty and all bits shifted out"] -pub type TX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +pub type TX_IDLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Receive FIFO has at least one byte"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { TX_IDLE_R::new(((self.bits >> 6) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LSR") + .field("tx_idle", &format_args!("{}", self.tx_idle().bit())) + .field("tx_empty", &format_args!("{}", self.tx_empty().bit())) + .field("rx_overrun", &format_args!("{}", self.rx_overrun().bit())) + .field("data_ready", &format_args!("{}", self.data_ready().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Receive FIFO has at least one byte"] #[inline(always)] #[must_use] - pub fn data_ready(&mut self) -> DATA_READY_W<0> { + pub fn data_ready(&mut self) -> DATA_READY_W { DATA_READY_W::new(self) } #[doc = "Bit 1 - Receive FIFO overrun"] #[inline(always)] #[must_use] - pub fn rx_overrun(&mut self) -> RX_OVERRUN_W<1> { + pub fn rx_overrun(&mut self) -> RX_OVERRUN_W { RX_OVERRUN_W::new(self) } #[doc = "Bit 5 - Transmit FIFO has room for at least one byte"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W<5> { + pub fn tx_empty(&mut self) -> TX_EMPTY_W { TX_EMPTY_W::new(self) } #[doc = "Bit 6 - Transmit FIFO empty and all bits shifted out"] #[inline(always)] #[must_use] - pub fn tx_idle(&mut self) -> TX_IDLE_W<6> { + pub fn tx_idle(&mut self) -> TX_IDLE_W { TX_IDLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Line Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lsr](index.html) module"] +#[doc = "Line Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LSR_SPEC; impl crate::RegisterSpec for LSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lsr::R](R) reader structure"] -impl crate::Readable for LSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [lsr::W](W) writer structure"] +#[doc = "`read()` method returns [`lsr::R`](R) reader structure"] +impl crate::Readable for LSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lsr::W`](W) writer structure"] impl crate::Writable for LSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart1/mcr.rs b/crates/bcm2711-lpa/src/uart1/mcr.rs index 89de0a8..26a7cb4 100644 --- a/crates/bcm2711-lpa/src/uart1/mcr.rs +++ b/crates/bcm2711-lpa/src/uart1/mcr.rs @@ -1,43 +1,11 @@ #[doc = "Register `MCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RTS` reader - RTS is low"] -pub type RTS_R = crate::BitReader; +pub type RTS_R = crate::BitReader; #[doc = "Field `RTS` writer - RTS is low"] -pub type RTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>; +pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - RTS is low"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { RTS_R::new(((self.bits >> 1) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCR") + .field("rts", &format_args!("{}", self.rts().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - RTS is low"] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W<1> { + pub fn rts(&mut self) -> RTS_W { RTS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Modem Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr](index.html) module"] +#[doc = "Modem Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCR_SPEC; impl crate::RegisterSpec for MCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mcr::R](R) reader structure"] -impl crate::Readable for MCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mcr::W](W) writer structure"] +#[doc = "`read()` method returns [`mcr::R`](R) reader structure"] +impl crate::Readable for MCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] impl crate::Writable for MCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart1/msr.rs b/crates/bcm2711-lpa/src/uart1/msr.rs index 3960539..c6e81af 100644 --- a/crates/bcm2711-lpa/src/uart1/msr.rs +++ b/crates/bcm2711-lpa/src/uart1/msr.rs @@ -1,43 +1,11 @@ #[doc = "Register `MSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CTS` reader - CTS is low"] -pub type CTS_R = crate::BitReader; +pub type CTS_R = crate::BitReader; #[doc = "Field `CTS` writer - CTS is low"] -pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSR_SPEC, bool, O>; +pub type CTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 4 - CTS is low"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { CTS_R::new(((self.bits >> 4) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MSR") + .field("cts", &format_args!("{}", self.cts().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 4 - CTS is low"] #[inline(always)] #[must_use] - pub fn cts(&mut self) -> CTS_W<4> { + pub fn cts(&mut self) -> CTS_W { CTS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Modem Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msr](index.html) module"] +#[doc = "Modem Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MSR_SPEC; impl crate::RegisterSpec for MSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [msr::R](R) reader structure"] -impl crate::Readable for MSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [msr::W](W) writer structure"] +#[doc = "`read()` method returns [`msr::R`](R) reader structure"] +impl crate::Readable for MSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`msr::W`](W) writer structure"] impl crate::Writable for MSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart1/scratch.rs b/crates/bcm2711-lpa/src/uart1/scratch.rs index c85f068..bd73381 100644 --- a/crates/bcm2711-lpa/src/uart1/scratch.rs +++ b/crates/bcm2711-lpa/src/uart1/scratch.rs @@ -1,59 +1,38 @@ #[doc = "Register `SCRATCH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCRATCH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Scratch\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scratch](index.html) module"] +#[doc = "Scratch\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scratch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCRATCH_SPEC; impl crate::RegisterSpec for SCRATCH_SPEC { type Ux = u8; } -#[doc = "`read()` method returns [scratch::R](R) reader structure"] -impl crate::Readable for SCRATCH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scratch::W](W) writer structure"] +#[doc = "`read()` method returns [`scratch::R`](R) reader structure"] +impl crate::Readable for SCRATCH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch::W`](W) writer structure"] impl crate::Writable for SCRATCH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/uart1/stat.rs b/crates/bcm2711-lpa/src/uart1/stat.rs index 114015e..b876fef 100644 --- a/crates/bcm2711-lpa/src/uart1/stat.rs +++ b/crates/bcm2711-lpa/src/uart1/stat.rs @@ -1,87 +1,55 @@ #[doc = "Register `STAT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STAT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA_READY` reader - Receive FIFO has at least one symbol"] -pub type DATA_READY_R = crate::BitReader; +pub type DATA_READY_R = crate::BitReader; #[doc = "Field `DATA_READY` writer - Receive FIFO has at least one symbol"] -pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type DATA_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_READY` reader - Transmit FIFO has space for at least one symbol"] -pub type TX_READY_R = crate::BitReader; +pub type TX_READY_R = crate::BitReader; #[doc = "Field `TX_READY` writer - Transmit FIFO has space for at least one symbol"] -pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_IDLE` reader - Receiver is idle"] -pub type RX_IDLE_R = crate::BitReader; +pub type RX_IDLE_R = crate::BitReader; #[doc = "Field `RX_IDLE` writer - Receiver is idle"] -pub type RX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RX_IDLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_IDLE` reader - Transmitter is idle"] -pub type TX_IDLE_R = crate::BitReader; +pub type TX_IDLE_R = crate::BitReader; #[doc = "Field `TX_IDLE` writer - Transmitter is idle"] -pub type TX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_IDLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_OVERRUN` reader - Receive FIFO overrun"] -pub type RX_OVERRUN_R = crate::BitReader; +pub type RX_OVERRUN_R = crate::BitReader; #[doc = "Field `RX_OVERRUN` writer - Receive FIFO overrun"] -pub type RX_OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RX_OVERRUN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_FULL` reader - Transmit FIFO is full"] -pub type TX_FULL_R = crate::BitReader; +pub type TX_FULL_R = crate::BitReader; #[doc = "Field `TX_FULL` writer - Transmit FIFO is full"] -pub type TX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTS_STATUS` reader - RTS state"] -pub type RTS_STATUS_R = crate::BitReader; +pub type RTS_STATUS_R = crate::BitReader; #[doc = "Field `RTS_STATUS` writer - RTS state"] -pub type RTS_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RTS_STATUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTS_STATUS` reader - CTS state"] -pub type CTS_STATUS_R = crate::BitReader; +pub type CTS_STATUS_R = crate::BitReader; #[doc = "Field `CTS_STATUS` writer - CTS state"] -pub type CTS_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type CTS_STATUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_EMPTY` reader - Transmit FIFO is completely empty"] -pub type TX_EMPTY_R = crate::BitReader; +pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `TX_EMPTY` writer - Transmit FIFO is completely empty"] -pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_DONE` reader - Transmit FIFO is empty and transmitter is idle"] -pub type TX_DONE_R = crate::BitReader; +pub type TX_DONE_R = crate::BitReader; #[doc = "Field `TX_DONE` writer - Transmit FIFO is empty and transmitter is idle"] -pub type TX_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_FIFO_LEVEL` reader - How many entries are filled in the RX FIFO"] -pub type RX_FIFO_LEVEL_R = crate::FieldReader; +pub type RX_FIFO_LEVEL_R = crate::FieldReader; #[doc = "Field `RX_FIFO_LEVEL` writer - How many entries are filled in the RX FIFO"] -pub type RX_FIFO_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +pub type RX_FIFO_LEVEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TX_FIFO_LEVEL` reader - How many entries are filled in the TX FIFO"] -pub type TX_FIFO_LEVEL_R = crate::FieldReader; +pub type TX_FIFO_LEVEL_R = crate::FieldReader; #[doc = "Field `TX_FIFO_LEVEL` writer - How many entries are filled in the TX FIFO"] -pub type TX_FIFO_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +pub type TX_FIFO_LEVEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bit 0 - Receive FIFO has at least one symbol"] #[inline(always)] @@ -144,98 +112,128 @@ impl R { TX_FIFO_LEVEL_R::new(((self.bits >> 24) & 0x0f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STAT") + .field( + "tx_fifo_level", + &format_args!("{}", self.tx_fifo_level().bits()), + ) + .field( + "rx_fifo_level", + &format_args!("{}", self.rx_fifo_level().bits()), + ) + .field("tx_done", &format_args!("{}", self.tx_done().bit())) + .field("tx_empty", &format_args!("{}", self.tx_empty().bit())) + .field("cts_status", &format_args!("{}", self.cts_status().bit())) + .field("rts_status", &format_args!("{}", self.rts_status().bit())) + .field("tx_full", &format_args!("{}", self.tx_full().bit())) + .field("rx_overrun", &format_args!("{}", self.rx_overrun().bit())) + .field("tx_idle", &format_args!("{}", self.tx_idle().bit())) + .field("rx_idle", &format_args!("{}", self.rx_idle().bit())) + .field("tx_ready", &format_args!("{}", self.tx_ready().bit())) + .field("data_ready", &format_args!("{}", self.data_ready().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Receive FIFO has at least one symbol"] #[inline(always)] #[must_use] - pub fn data_ready(&mut self) -> DATA_READY_W<0> { + pub fn data_ready(&mut self) -> DATA_READY_W { DATA_READY_W::new(self) } #[doc = "Bit 1 - Transmit FIFO has space for at least one symbol"] #[inline(always)] #[must_use] - pub fn tx_ready(&mut self) -> TX_READY_W<1> { + pub fn tx_ready(&mut self) -> TX_READY_W { TX_READY_W::new(self) } #[doc = "Bit 2 - Receiver is idle"] #[inline(always)] #[must_use] - pub fn rx_idle(&mut self) -> RX_IDLE_W<2> { + pub fn rx_idle(&mut self) -> RX_IDLE_W { RX_IDLE_W::new(self) } #[doc = "Bit 3 - Transmitter is idle"] #[inline(always)] #[must_use] - pub fn tx_idle(&mut self) -> TX_IDLE_W<3> { + pub fn tx_idle(&mut self) -> TX_IDLE_W { TX_IDLE_W::new(self) } #[doc = "Bit 4 - Receive FIFO overrun"] #[inline(always)] #[must_use] - pub fn rx_overrun(&mut self) -> RX_OVERRUN_W<4> { + pub fn rx_overrun(&mut self) -> RX_OVERRUN_W { RX_OVERRUN_W::new(self) } #[doc = "Bit 5 - Transmit FIFO is full"] #[inline(always)] #[must_use] - pub fn tx_full(&mut self) -> TX_FULL_W<5> { + pub fn tx_full(&mut self) -> TX_FULL_W { TX_FULL_W::new(self) } #[doc = "Bit 6 - RTS state"] #[inline(always)] #[must_use] - pub fn rts_status(&mut self) -> RTS_STATUS_W<6> { + pub fn rts_status(&mut self) -> RTS_STATUS_W { RTS_STATUS_W::new(self) } #[doc = "Bit 7 - CTS state"] #[inline(always)] #[must_use] - pub fn cts_status(&mut self) -> CTS_STATUS_W<7> { + pub fn cts_status(&mut self) -> CTS_STATUS_W { CTS_STATUS_W::new(self) } #[doc = "Bit 8 - Transmit FIFO is completely empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W<8> { + pub fn tx_empty(&mut self) -> TX_EMPTY_W { TX_EMPTY_W::new(self) } #[doc = "Bit 9 - Transmit FIFO is empty and transmitter is idle"] #[inline(always)] #[must_use] - pub fn tx_done(&mut self) -> TX_DONE_W<9> { + pub fn tx_done(&mut self) -> TX_DONE_W { TX_DONE_W::new(self) } #[doc = "Bits 16:19 - How many entries are filled in the RX FIFO"] #[inline(always)] #[must_use] - pub fn rx_fifo_level(&mut self) -> RX_FIFO_LEVEL_W<16> { + pub fn rx_fifo_level(&mut self) -> RX_FIFO_LEVEL_W { RX_FIFO_LEVEL_W::new(self) } #[doc = "Bits 24:27 - How many entries are filled in the TX FIFO"] #[inline(always)] #[must_use] - pub fn tx_fifo_level(&mut self) -> TX_FIFO_LEVEL_W<24> { + pub fn tx_fifo_level(&mut self) -> TX_FIFO_LEVEL_W { TX_FIFO_LEVEL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"] +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STAT_SPEC; impl crate::RegisterSpec for STAT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [stat::R](R) reader structure"] -impl crate::Readable for STAT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"] +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] impl crate::Writable for STAT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device.rs b/crates/bcm2711-lpa/src/usb_otg_device.rs index 8050e54..d432f5d 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - OTG_HS device configuration register"] pub dcfg: DCFG, @@ -107,63 +108,78 @@ pub struct RegisterBlock { #[doc = "0x460..0x478 - OUT Endpoint %s"] pub out_endpoint11: OUT_ENDPOINT, } -#[doc = "DCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "DCFG (rw) register accessor: OTG_HS device configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcfg`] +module"] pub type DCFG = crate::Reg; #[doc = "OTG_HS device configuration register"] pub mod dcfg; -#[doc = "DCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "DCTL (rw) register accessor: OTG_HS device control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dctl`] +module"] pub type DCTL = crate::Reg; #[doc = "OTG_HS device control register"] pub mod dctl; -#[doc = "DSTS (r) register accessor: an alias for `Reg`"] +#[doc = "DSTS (r) register accessor: OTG_HS device status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsts::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsts`] +module"] pub type DSTS = crate::Reg; #[doc = "OTG_HS device status register"] pub mod dsts; -#[doc = "DIEPMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPMSK (rw) register accessor: OTG_HS device IN endpoint common interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepmsk`] +module"] pub type DIEPMSK = crate::Reg; #[doc = "OTG_HS device IN endpoint common interrupt mask register"] pub mod diepmsk; -#[doc = "DOEPMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPMSK (rw) register accessor: OTG_HS device OUT endpoint common interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepmsk`] +module"] pub type DOEPMSK = crate::Reg; #[doc = "OTG_HS device OUT endpoint common interrupt mask register"] pub mod doepmsk; -#[doc = "DAINT (r) register accessor: an alias for `Reg`"] +#[doc = "DAINT (r) register accessor: OTG_HS device all endpoints interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daint::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daint`] +module"] pub type DAINT = crate::Reg; #[doc = "OTG_HS device all endpoints interrupt register"] pub mod daint; -#[doc = "DAINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DAINTMSK (rw) register accessor: OTG_HS all endpoints interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`daintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daintmsk`] +module"] pub type DAINTMSK = crate::Reg; #[doc = "OTG_HS all endpoints interrupt mask register"] pub mod daintmsk; -#[doc = "DVBUSDIS (rw) register accessor: an alias for `Reg`"] +#[doc = "DVBUSDIS (rw) register accessor: OTG_HS device VBUS discharge time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dvbusdis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dvbusdis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dvbusdis`] +module"] pub type DVBUSDIS = crate::Reg; #[doc = "OTG_HS device VBUS discharge time register"] pub mod dvbusdis; -#[doc = "DVBUSPULSE (rw) register accessor: an alias for `Reg`"] +#[doc = "DVBUSPULSE (rw) register accessor: OTG_HS device VBUS pulsing time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dvbuspulse::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dvbuspulse::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dvbuspulse`] +module"] pub type DVBUSPULSE = crate::Reg; #[doc = "OTG_HS device VBUS pulsing time register"] pub mod dvbuspulse; -#[doc = "DTHRCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "DTHRCTL (rw) register accessor: OTG_HS Device threshold control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dthrctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dthrctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dthrctl`] +module"] pub type DTHRCTL = crate::Reg; #[doc = "OTG_HS Device threshold control register"] pub mod dthrctl; -#[doc = "DIEPEMPMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPEMPMSK (rw) register accessor: OTG_HS device IN endpoint FIFO empty interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepempmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepempmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepempmsk`] +module"] pub type DIEPEMPMSK = crate::Reg; #[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register"] pub mod diepempmsk; -#[doc = "DEACHINT (rw) register accessor: an alias for `Reg`"] +#[doc = "DEACHINT (rw) register accessor: OTG_HS device each endpoint interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deachint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deachint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@deachint`] +module"] pub type DEACHINT = crate::Reg; #[doc = "OTG_HS device each endpoint interrupt register"] pub mod deachint; -#[doc = "DEACHINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DEACHINTMSK (rw) register accessor: OTG_HS device each endpoint interrupt register mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deachintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deachintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@deachintmsk`] +module"] pub type DEACHINTMSK = crate::Reg; #[doc = "OTG_HS device each endpoint interrupt register mask"] pub mod deachintmsk; -#[doc = "DIEPEACHMSK1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPEACHMSK1 (rw) register accessor: OTG_HS device each in endpoint-1 interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepeachmsk1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepeachmsk1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepeachmsk1`] +module"] pub type DIEPEACHMSK1 = crate::Reg; #[doc = "OTG_HS device each in endpoint-1 interrupt register"] pub mod diepeachmsk1; -#[doc = "DOEPEACHMSK1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPEACHMSK1 (rw) register accessor: OTG_HS device each OUT endpoint-1 interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepeachmsk1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepeachmsk1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepeachmsk1`] +module"] pub type DOEPEACHMSK1 = crate::Reg; #[doc = "OTG_HS device each OUT endpoint-1 interrupt register"] pub mod doepeachmsk1; diff --git a/crates/bcm2711-lpa/src/usb_otg_device/daint.rs b/crates/bcm2711-lpa/src/usb_otg_device/daint.rs index 14c25b3..3210b36 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/daint.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/daint.rs @@ -1,22 +1,9 @@ #[doc = "Register `DAINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `IEPINT` reader - IN endpoint interrupt bits"] -pub type IEPINT_R = crate::FieldReader; +pub type IEPINT_R = crate::FieldReader; #[doc = "Field `OEPINT` reader - OUT endpoint interrupt bits"] -pub type OEPINT_R = crate::FieldReader; +pub type OEPINT_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - IN endpoint interrupt bits"] #[inline(always)] @@ -29,15 +16,26 @@ impl R { OEPINT_R::new(((self.bits >> 16) & 0xffff) as u16) } } -#[doc = "OTG_HS device all endpoints interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daint](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAINT") + .field("iepint", &format_args!("{}", self.iepint().bits())) + .field("oepint", &format_args!("{}", self.oepint().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS device all endpoints interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daint::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DAINT_SPEC; impl crate::RegisterSpec for DAINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [daint::R](R) reader structure"] -impl crate::Readable for DAINT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`daint::R`](R) reader structure"] +impl crate::Readable for DAINT_SPEC {} #[doc = "`reset()` method sets DAINT to value 0"] impl crate::Resettable for DAINT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/usb_otg_device/daintmsk.rs b/crates/bcm2711-lpa/src/usb_otg_device/daintmsk.rs index bf7c858..44196aa 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/daintmsk.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/daintmsk.rs @@ -1,47 +1,15 @@ #[doc = "Register `DAINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DAINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IEPM` reader - IN EP interrupt mask bits"] -pub type IEPM_R = crate::FieldReader; +pub type IEPM_R = crate::FieldReader; #[doc = "Field `IEPM` writer - IN EP interrupt mask bits"] -pub type IEPM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DAINTMSK_SPEC, u16, u16, 16, O>; +pub type IEPM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `OEPM` reader - OUT EP interrupt mask bits"] -pub type OEPM_R = crate::FieldReader; +pub type OEPM_R = crate::FieldReader; #[doc = "Field `OEPM` writer - OUT EP interrupt mask bits"] -pub type OEPM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DAINTMSK_SPEC, u16, u16, 16, O>; +pub type OEPM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN EP interrupt mask bits"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { OEPM_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAINTMSK") + .field("iepm", &format_args!("{}", self.iepm().bits())) + .field("oepm", &format_args!("{}", self.oepm().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN EP interrupt mask bits"] #[inline(always)] #[must_use] - pub fn iepm(&mut self) -> IEPM_W<0> { + pub fn iepm(&mut self) -> IEPM_W { IEPM_W::new(self) } #[doc = "Bits 16:31 - OUT EP interrupt mask bits"] #[inline(always)] #[must_use] - pub fn oepm(&mut self) -> OEPM_W<16> { + pub fn oepm(&mut self) -> OEPM_W { OEPM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS all endpoints interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daintmsk](index.html) module"] +#[doc = "OTG_HS all endpoints interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`daintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DAINTMSK_SPEC; impl crate::RegisterSpec for DAINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [daintmsk::R](R) reader structure"] -impl crate::Readable for DAINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [daintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`daintmsk::R`](R) reader structure"] +impl crate::Readable for DAINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`daintmsk::W`](W) writer structure"] impl crate::Writable for DAINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/dcfg.rs b/crates/bcm2711-lpa/src/usb_otg_device/dcfg.rs index ad6ef16..fc2bbc8 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/dcfg.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/dcfg.rs @@ -1,59 +1,27 @@ #[doc = "Register `DCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DSPD` reader - Device speed"] -pub type DSPD_R = crate::FieldReader; +pub type DSPD_R = crate::FieldReader; #[doc = "Field `DSPD` writer - Device speed"] -pub type DSPD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +pub type DSPD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `NZLSOHSK` reader - Nonzero-length status OUT handshake"] -pub type NZLSOHSK_R = crate::BitReader; +pub type NZLSOHSK_R = crate::BitReader; #[doc = "Field `NZLSOHSK` writer - Nonzero-length status OUT handshake"] -pub type NZLSOHSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCFG_SPEC, bool, O>; +pub type NZLSOHSK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAD` reader - Device address"] -pub type DAD_R = crate::FieldReader; +pub type DAD_R = crate::FieldReader; #[doc = "Field `DAD` writer - Device address"] -pub type DAD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 7, O>; +pub type DAD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `PFIVL` reader - Periodic (micro)frame interval"] -pub type PFIVL_R = crate::FieldReader; +pub type PFIVL_R = crate::FieldReader; #[doc = "Field `PFIVL` writer - Periodic (micro)frame interval"] -pub type PFIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +pub type PFIVL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `PERSCHIVL` reader - Periodic scheduling interval"] -pub type PERSCHIVL_R = crate::FieldReader; +pub type PERSCHIVL_R = crate::FieldReader; #[doc = "Field `PERSCHIVL` writer - Periodic scheduling interval"] -pub type PERSCHIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +pub type PERSCHIVL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:1 - Device speed"] #[inline(always)] @@ -81,56 +49,73 @@ impl R { PERSCHIVL_R::new(((self.bits >> 24) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DCFG") + .field("dspd", &format_args!("{}", self.dspd().bits())) + .field("nzlsohsk", &format_args!("{}", self.nzlsohsk().bit())) + .field("dad", &format_args!("{}", self.dad().bits())) + .field("pfivl", &format_args!("{}", self.pfivl().bits())) + .field("perschivl", &format_args!("{}", self.perschivl().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Device speed"] #[inline(always)] #[must_use] - pub fn dspd(&mut self) -> DSPD_W<0> { + pub fn dspd(&mut self) -> DSPD_W { DSPD_W::new(self) } #[doc = "Bit 2 - Nonzero-length status OUT handshake"] #[inline(always)] #[must_use] - pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<2> { + pub fn nzlsohsk(&mut self) -> NZLSOHSK_W { NZLSOHSK_W::new(self) } #[doc = "Bits 4:10 - Device address"] #[inline(always)] #[must_use] - pub fn dad(&mut self) -> DAD_W<4> { + pub fn dad(&mut self) -> DAD_W { DAD_W::new(self) } #[doc = "Bits 11:12 - Periodic (micro)frame interval"] #[inline(always)] #[must_use] - pub fn pfivl(&mut self) -> PFIVL_W<11> { + pub fn pfivl(&mut self) -> PFIVL_W { PFIVL_W::new(self) } #[doc = "Bits 24:25 - Periodic scheduling interval"] #[inline(always)] #[must_use] - pub fn perschivl(&mut self) -> PERSCHIVL_W<24> { + pub fn perschivl(&mut self) -> PERSCHIVL_W { PERSCHIVL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +#[doc = "OTG_HS device configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DCFG_SPEC; impl crate::RegisterSpec for DCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dcfg::R](R) reader structure"] -impl crate::Readable for DCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`dcfg::R`](R) reader structure"] +impl crate::Readable for DCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dcfg::W`](W) writer structure"] impl crate::Writable for DCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/dctl.rs b/crates/bcm2711-lpa/src/usb_otg_device/dctl.rs index ed73ebd..42ffebd 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/dctl.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/dctl.rs @@ -1,67 +1,35 @@ #[doc = "Register `DCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RWUSIG` reader - Remote wakeup signaling"] -pub type RWUSIG_R = crate::BitReader; +pub type RWUSIG_R = crate::BitReader; #[doc = "Field `RWUSIG` writer - Remote wakeup signaling"] -pub type RWUSIG_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type RWUSIG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SDIS` reader - Soft disconnect"] -pub type SDIS_R = crate::BitReader; +pub type SDIS_R = crate::BitReader; #[doc = "Field `SDIS` writer - Soft disconnect"] -pub type SDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type SDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GINSTS` reader - Global IN NAK status"] -pub type GINSTS_R = crate::BitReader; +pub type GINSTS_R = crate::BitReader; #[doc = "Field `GONSTS` reader - Global OUT NAK status"] -pub type GONSTS_R = crate::BitReader; +pub type GONSTS_R = crate::BitReader; #[doc = "Field `TCTL` reader - Test control"] -pub type TCTL_R = crate::FieldReader; +pub type TCTL_R = crate::FieldReader; #[doc = "Field `TCTL` writer - Test control"] -pub type TCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCTL_SPEC, u8, u8, 3, O>; +pub type TCTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `SGINAK` writer - Set global IN NAK"] -pub type SGINAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type SGINAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CGINAK` writer - Clear global IN NAK"] -pub type CGINAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type CGINAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SGONAK` writer - Set global OUT NAK"] -pub type SGONAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type SGONAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CGONAK` writer - Clear global OUT NAK"] -pub type CGONAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type CGONAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POPRGDNE` reader - Power-on programming done"] -pub type POPRGDNE_R = crate::BitReader; +pub type POPRGDNE_R = crate::BitReader; #[doc = "Field `POPRGDNE` writer - Power-on programming done"] -pub type POPRGDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type POPRGDNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Remote wakeup signaling"] #[inline(always)] @@ -94,74 +62,92 @@ impl R { POPRGDNE_R::new(((self.bits >> 11) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DCTL") + .field("rwusig", &format_args!("{}", self.rwusig().bit())) + .field("sdis", &format_args!("{}", self.sdis().bit())) + .field("ginsts", &format_args!("{}", self.ginsts().bit())) + .field("gonsts", &format_args!("{}", self.gonsts().bit())) + .field("tctl", &format_args!("{}", self.tctl().bits())) + .field("poprgdne", &format_args!("{}", self.poprgdne().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Remote wakeup signaling"] #[inline(always)] #[must_use] - pub fn rwusig(&mut self) -> RWUSIG_W<0> { + pub fn rwusig(&mut self) -> RWUSIG_W { RWUSIG_W::new(self) } #[doc = "Bit 1 - Soft disconnect"] #[inline(always)] #[must_use] - pub fn sdis(&mut self) -> SDIS_W<1> { + pub fn sdis(&mut self) -> SDIS_W { SDIS_W::new(self) } #[doc = "Bits 4:6 - Test control"] #[inline(always)] #[must_use] - pub fn tctl(&mut self) -> TCTL_W<4> { + pub fn tctl(&mut self) -> TCTL_W { TCTL_W::new(self) } #[doc = "Bit 7 - Set global IN NAK"] #[inline(always)] #[must_use] - pub fn sginak(&mut self) -> SGINAK_W<7> { + pub fn sginak(&mut self) -> SGINAK_W { SGINAK_W::new(self) } #[doc = "Bit 8 - Clear global IN NAK"] #[inline(always)] #[must_use] - pub fn cginak(&mut self) -> CGINAK_W<8> { + pub fn cginak(&mut self) -> CGINAK_W { CGINAK_W::new(self) } #[doc = "Bit 9 - Set global OUT NAK"] #[inline(always)] #[must_use] - pub fn sgonak(&mut self) -> SGONAK_W<9> { + pub fn sgonak(&mut self) -> SGONAK_W { SGONAK_W::new(self) } #[doc = "Bit 10 - Clear global OUT NAK"] #[inline(always)] #[must_use] - pub fn cgonak(&mut self) -> CGONAK_W<10> { + pub fn cgonak(&mut self) -> CGONAK_W { CGONAK_W::new(self) } #[doc = "Bit 11 - Power-on programming done"] #[inline(always)] #[must_use] - pub fn poprgdne(&mut self) -> POPRGDNE_W<11> { + pub fn poprgdne(&mut self) -> POPRGDNE_W { POPRGDNE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dctl](index.html) module"] +#[doc = "OTG_HS device control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DCTL_SPEC; impl crate::RegisterSpec for DCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dctl::R](R) reader structure"] -impl crate::Readable for DCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dctl::W](W) writer structure"] +#[doc = "`read()` method returns [`dctl::R`](R) reader structure"] +impl crate::Readable for DCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dctl::W`](W) writer structure"] impl crate::Writable for DCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/deachint.rs b/crates/bcm2711-lpa/src/usb_otg_device/deachint.rs index b2e2a0b..f8f0c35 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/deachint.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/deachint.rs @@ -1,47 +1,15 @@ #[doc = "Register `DEACHINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEACHINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IEP1INT` reader - IN endpoint 1interrupt bit"] -pub type IEP1INT_R = crate::BitReader; +pub type IEP1INT_R = crate::BitReader; #[doc = "Field `IEP1INT` writer - IN endpoint 1interrupt bit"] -pub type IEP1INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINT_SPEC, bool, O>; +pub type IEP1INT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEP1INT` reader - OUT endpoint 1 interrupt bit"] -pub type OEP1INT_R = crate::BitReader; +pub type OEP1INT_R = crate::BitReader; #[doc = "Field `OEP1INT` writer - OUT endpoint 1 interrupt bit"] -pub type OEP1INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINT_SPEC, bool, O>; +pub type OEP1INT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - IN endpoint 1interrupt bit"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { OEP1INT_R::new(((self.bits >> 17) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEACHINT") + .field("iep1int", &format_args!("{}", self.iep1int().bit())) + .field("oep1int", &format_args!("{}", self.oep1int().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - IN endpoint 1interrupt bit"] #[inline(always)] #[must_use] - pub fn iep1int(&mut self) -> IEP1INT_W<1> { + pub fn iep1int(&mut self) -> IEP1INT_W { IEP1INT_W::new(self) } #[doc = "Bit 17 - OUT endpoint 1 interrupt bit"] #[inline(always)] #[must_use] - pub fn oep1int(&mut self) -> OEP1INT_W<17> { + pub fn oep1int(&mut self) -> OEP1INT_W { OEP1INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device each endpoint interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deachint](index.html) module"] +#[doc = "OTG_HS device each endpoint interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deachint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deachint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEACHINT_SPEC; impl crate::RegisterSpec for DEACHINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deachint::R](R) reader structure"] -impl crate::Readable for DEACHINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [deachint::W](W) writer structure"] +#[doc = "`read()` method returns [`deachint::R`](R) reader structure"] +impl crate::Readable for DEACHINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`deachint::W`](W) writer structure"] impl crate::Writable for DEACHINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/deachintmsk.rs b/crates/bcm2711-lpa/src/usb_otg_device/deachintmsk.rs index 635cecf..8979089 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/deachintmsk.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/deachintmsk.rs @@ -1,47 +1,15 @@ #[doc = "Register `DEACHINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEACHINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IEP1INTM` reader - IN Endpoint 1 interrupt mask bit"] -pub type IEP1INTM_R = crate::BitReader; +pub type IEP1INTM_R = crate::BitReader; #[doc = "Field `IEP1INTM` writer - IN Endpoint 1 interrupt mask bit"] -pub type IEP1INTM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINTMSK_SPEC, bool, O>; +pub type IEP1INTM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEP1INTM` reader - OUT Endpoint 1 interrupt mask bit"] -pub type OEP1INTM_R = crate::BitReader; +pub type OEP1INTM_R = crate::BitReader; #[doc = "Field `OEP1INTM` writer - OUT Endpoint 1 interrupt mask bit"] -pub type OEP1INTM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINTMSK_SPEC, bool, O>; +pub type OEP1INTM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - IN Endpoint 1 interrupt mask bit"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { OEP1INTM_R::new(((self.bits >> 17) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEACHINTMSK") + .field("iep1intm", &format_args!("{}", self.iep1intm().bit())) + .field("oep1intm", &format_args!("{}", self.oep1intm().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - IN Endpoint 1 interrupt mask bit"] #[inline(always)] #[must_use] - pub fn iep1intm(&mut self) -> IEP1INTM_W<1> { + pub fn iep1intm(&mut self) -> IEP1INTM_W { IEP1INTM_W::new(self) } #[doc = "Bit 17 - OUT Endpoint 1 interrupt mask bit"] #[inline(always)] #[must_use] - pub fn oep1intm(&mut self) -> OEP1INTM_W<17> { + pub fn oep1intm(&mut self) -> OEP1INTM_W { OEP1INTM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device each endpoint interrupt register mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deachintmsk](index.html) module"] +#[doc = "OTG_HS device each endpoint interrupt register mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deachintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deachintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEACHINTMSK_SPEC; impl crate::RegisterSpec for DEACHINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deachintmsk::R](R) reader structure"] -impl crate::Readable for DEACHINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [deachintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`deachintmsk::R`](R) reader structure"] +impl crate::Readable for DEACHINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`deachintmsk::W`](W) writer structure"] impl crate::Writable for DEACHINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/diepeachmsk1.rs b/crates/bcm2711-lpa/src/usb_otg_device/diepeachmsk1.rs index 6e00947..b6d85a8 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/diepeachmsk1.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/diepeachmsk1.rs @@ -1,75 +1,43 @@ #[doc = "Register `DIEPEACHMSK1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPEACHMSK1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] -pub type EPDM_R = crate::BitReader; +pub type EPDM_R = crate::BitReader; #[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] -pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type EPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOM` reader - Timeout condition mask (nonisochronous endpoints)"] -pub type TOM_R = crate::BitReader; +pub type TOM_R = crate::BitReader; #[doc = "Field `TOM` writer - Timeout condition mask (nonisochronous endpoints)"] -pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type TOM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_R = crate::BitReader; +pub type ITTXFEMSK_R = crate::BitReader; #[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type ITTXFEMSK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] -pub type INEPNMM_R = crate::BitReader; +pub type INEPNMM_R = crate::BitReader; #[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] -pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type INEPNMM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] -pub type INEPNEM_R = crate::BitReader; +pub type INEPNEM_R = crate::BitReader; #[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] -pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type INEPNEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFURM` reader - FIFO underrun mask"] -pub type TXFURM_R = crate::BitReader; +pub type TXFURM_R = crate::BitReader; #[doc = "Field `TXFURM` writer - FIFO underrun mask"] -pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type TXFURM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BIM` reader - BNA interrupt mask"] -pub type BIM_R = crate::BitReader; +pub type BIM_R = crate::BitReader; #[doc = "Field `BIM` writer - BNA interrupt mask"] -pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type BIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKM` reader - NAK interrupt mask"] -pub type NAKM_R = crate::BitReader; +pub type NAKM_R = crate::BitReader; #[doc = "Field `NAKM` writer - NAK interrupt mask"] -pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type NAKM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] @@ -117,80 +85,101 @@ impl R { NAKM_R::new(((self.bits >> 13) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPEACHMSK1") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("epdm", &format_args!("{}", self.epdm().bit())) + .field("tom", &format_args!("{}", self.tom().bit())) + .field("ittxfemsk", &format_args!("{}", self.ittxfemsk().bit())) + .field("inepnmm", &format_args!("{}", self.inepnmm().bit())) + .field("inepnem", &format_args!("{}", self.inepnem().bit())) + .field("txfurm", &format_args!("{}", self.txfurm().bit())) + .field("bim", &format_args!("{}", self.bim().bit())) + .field("nakm", &format_args!("{}", self.nakm().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt mask"] #[inline(always)] #[must_use] - pub fn epdm(&mut self) -> EPDM_W<1> { + pub fn epdm(&mut self) -> EPDM_W { EPDM_W::new(self) } #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] #[inline(always)] #[must_use] - pub fn tom(&mut self) -> TOM_W<3> { + pub fn tom(&mut self) -> TOM_W { TOM_W::new(self) } #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W { ITTXFEMSK_W::new(self) } #[doc = "Bit 5 - IN token received with EP mismatch mask"] #[inline(always)] #[must_use] - pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + pub fn inepnmm(&mut self) -> INEPNMM_W { INEPNMM_W::new(self) } #[doc = "Bit 6 - IN endpoint NAK effective mask"] #[inline(always)] #[must_use] - pub fn inepnem(&mut self) -> INEPNEM_W<6> { + pub fn inepnem(&mut self) -> INEPNEM_W { INEPNEM_W::new(self) } #[doc = "Bit 8 - FIFO underrun mask"] #[inline(always)] #[must_use] - pub fn txfurm(&mut self) -> TXFURM_W<8> { + pub fn txfurm(&mut self) -> TXFURM_W { TXFURM_W::new(self) } #[doc = "Bit 9 - BNA interrupt mask"] #[inline(always)] #[must_use] - pub fn bim(&mut self) -> BIM_W<9> { + pub fn bim(&mut self) -> BIM_W { BIM_W::new(self) } #[doc = "Bit 13 - NAK interrupt mask"] #[inline(always)] #[must_use] - pub fn nakm(&mut self) -> NAKM_W<13> { + pub fn nakm(&mut self) -> NAKM_W { NAKM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device each in endpoint-1 interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepeachmsk1](index.html) module"] +#[doc = "OTG_HS device each in endpoint-1 interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepeachmsk1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepeachmsk1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPEACHMSK1_SPEC; impl crate::RegisterSpec for DIEPEACHMSK1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepeachmsk1::R](R) reader structure"] -impl crate::Readable for DIEPEACHMSK1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepeachmsk1::W](W) writer structure"] +#[doc = "`read()` method returns [`diepeachmsk1::R`](R) reader structure"] +impl crate::Readable for DIEPEACHMSK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepeachmsk1::W`](W) writer structure"] impl crate::Writable for DIEPEACHMSK1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/diepempmsk.rs b/crates/bcm2711-lpa/src/usb_otg_device/diepempmsk.rs index 8e5b978..89831f3 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/diepempmsk.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/diepempmsk.rs @@ -1,44 +1,11 @@ #[doc = "Register `DIEPEMPMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPEMPMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXFEM` reader - IN EP Tx FIFO empty interrupt mask bits"] -pub type INEPTXFEM_R = crate::FieldReader; +pub type INEPTXFEM_R = crate::FieldReader; #[doc = "Field `INEPTXFEM` writer - IN EP Tx FIFO empty interrupt mask bits"] -pub type INEPTXFEM_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, DIEPEMPMSK_SPEC, u16, u16, 16, O>; +pub type INEPTXFEM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits"] #[inline(always)] @@ -46,32 +13,45 @@ impl R { INEPTXFEM_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPEMPMSK") + .field("ineptxfem", &format_args!("{}", self.ineptxfem().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits"] #[inline(always)] #[must_use] - pub fn ineptxfem(&mut self) -> INEPTXFEM_W<0> { + pub fn ineptxfem(&mut self) -> INEPTXFEM_W { INEPTXFEM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepempmsk](index.html) module"] +#[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepempmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepempmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPEMPMSK_SPEC; impl crate::RegisterSpec for DIEPEMPMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepempmsk::R](R) reader structure"] -impl crate::Readable for DIEPEMPMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepempmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`diepempmsk::R`](R) reader structure"] +impl crate::Readable for DIEPEMPMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepempmsk::W`](W) writer structure"] impl crate::Writable for DIEPEMPMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/diepmsk.rs b/crates/bcm2711-lpa/src/usb_otg_device/diepmsk.rs index 6411ce9..8bd397c 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/diepmsk.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/diepmsk.rs @@ -1,71 +1,39 @@ #[doc = "Register `DIEPMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] -pub type EPDM_R = crate::BitReader; +pub type EPDM_R = crate::BitReader; #[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] -pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type EPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOM` reader - Timeout condition mask (nonisochronous endpoints)"] -pub type TOM_R = crate::BitReader; +pub type TOM_R = crate::BitReader; #[doc = "Field `TOM` writer - Timeout condition mask (nonisochronous endpoints)"] -pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type TOM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_R = crate::BitReader; +pub type ITTXFEMSK_R = crate::BitReader; #[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type ITTXFEMSK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] -pub type INEPNMM_R = crate::BitReader; +pub type INEPNMM_R = crate::BitReader; #[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] -pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type INEPNMM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] -pub type INEPNEM_R = crate::BitReader; +pub type INEPNEM_R = crate::BitReader; #[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] -pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type INEPNEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFURM` reader - FIFO underrun mask"] -pub type TXFURM_R = crate::BitReader; +pub type TXFURM_R = crate::BitReader; #[doc = "Field `TXFURM` writer - FIFO underrun mask"] -pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type TXFURM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BIM` reader - BNA interrupt mask"] -pub type BIM_R = crate::BitReader; +pub type BIM_R = crate::BitReader; #[doc = "Field `BIM` writer - BNA interrupt mask"] -pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type BIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] @@ -108,74 +76,94 @@ impl R { BIM_R::new(((self.bits >> 9) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPMSK") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("epdm", &format_args!("{}", self.epdm().bit())) + .field("tom", &format_args!("{}", self.tom().bit())) + .field("ittxfemsk", &format_args!("{}", self.ittxfemsk().bit())) + .field("inepnmm", &format_args!("{}", self.inepnmm().bit())) + .field("inepnem", &format_args!("{}", self.inepnem().bit())) + .field("txfurm", &format_args!("{}", self.txfurm().bit())) + .field("bim", &format_args!("{}", self.bim().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt mask"] #[inline(always)] #[must_use] - pub fn epdm(&mut self) -> EPDM_W<1> { + pub fn epdm(&mut self) -> EPDM_W { EPDM_W::new(self) } #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] #[inline(always)] #[must_use] - pub fn tom(&mut self) -> TOM_W<3> { + pub fn tom(&mut self) -> TOM_W { TOM_W::new(self) } #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W { ITTXFEMSK_W::new(self) } #[doc = "Bit 5 - IN token received with EP mismatch mask"] #[inline(always)] #[must_use] - pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + pub fn inepnmm(&mut self) -> INEPNMM_W { INEPNMM_W::new(self) } #[doc = "Bit 6 - IN endpoint NAK effective mask"] #[inline(always)] #[must_use] - pub fn inepnem(&mut self) -> INEPNEM_W<6> { + pub fn inepnem(&mut self) -> INEPNEM_W { INEPNEM_W::new(self) } #[doc = "Bit 8 - FIFO underrun mask"] #[inline(always)] #[must_use] - pub fn txfurm(&mut self) -> TXFURM_W<8> { + pub fn txfurm(&mut self) -> TXFURM_W { TXFURM_W::new(self) } #[doc = "Bit 9 - BNA interrupt mask"] #[inline(always)] #[must_use] - pub fn bim(&mut self) -> BIM_W<9> { + pub fn bim(&mut self) -> BIM_W { BIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint common interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepmsk](index.html) module"] +#[doc = "OTG_HS device IN endpoint common interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPMSK_SPEC; impl crate::RegisterSpec for DIEPMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepmsk::R](R) reader structure"] -impl crate::Readable for DIEPMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`diepmsk::R`](R) reader structure"] +impl crate::Readable for DIEPMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepmsk::W`](W) writer structure"] impl crate::Writable for DIEPMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/doepeachmsk1.rs b/crates/bcm2711-lpa/src/usb_otg_device/doepeachmsk1.rs index 31a5ab1..7c60dcc 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/doepeachmsk1.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/doepeachmsk1.rs @@ -1,83 +1,51 @@ #[doc = "Register `DOEPEACHMSK1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPEACHMSK1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] -pub type EPDM_R = crate::BitReader; +pub type EPDM_R = crate::BitReader; #[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] -pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type EPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOM` reader - Timeout condition mask"] -pub type TOM_R = crate::BitReader; +pub type TOM_R = crate::BitReader; #[doc = "Field `TOM` writer - Timeout condition mask"] -pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type TOM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_R = crate::BitReader; +pub type ITTXFEMSK_R = crate::BitReader; #[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type ITTXFEMSK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] -pub type INEPNMM_R = crate::BitReader; +pub type INEPNMM_R = crate::BitReader; #[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] -pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type INEPNMM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] -pub type INEPNEM_R = crate::BitReader; +pub type INEPNEM_R = crate::BitReader; #[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] -pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type INEPNEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFURM` reader - OUT packet error mask"] -pub type TXFURM_R = crate::BitReader; +pub type TXFURM_R = crate::BitReader; #[doc = "Field `TXFURM` writer - OUT packet error mask"] -pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type TXFURM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BIM` reader - BNA interrupt mask"] -pub type BIM_R = crate::BitReader; +pub type BIM_R = crate::BitReader; #[doc = "Field `BIM` writer - BNA interrupt mask"] -pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type BIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BERRM` reader - Bubble error interrupt mask"] -pub type BERRM_R = crate::BitReader; +pub type BERRM_R = crate::BitReader; #[doc = "Field `BERRM` writer - Bubble error interrupt mask"] -pub type BERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type BERRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKM` reader - NAK interrupt mask"] -pub type NAKM_R = crate::BitReader; +pub type NAKM_R = crate::BitReader; #[doc = "Field `NAKM` writer - NAK interrupt mask"] -pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type NAKM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYETM` reader - NYET interrupt mask"] -pub type NYETM_R = crate::BitReader; +pub type NYETM_R = crate::BitReader; #[doc = "Field `NYETM` writer - NYET interrupt mask"] -pub type NYETM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type NYETM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] @@ -135,92 +103,115 @@ impl R { NYETM_R::new(((self.bits >> 14) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPEACHMSK1") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("epdm", &format_args!("{}", self.epdm().bit())) + .field("tom", &format_args!("{}", self.tom().bit())) + .field("ittxfemsk", &format_args!("{}", self.ittxfemsk().bit())) + .field("inepnmm", &format_args!("{}", self.inepnmm().bit())) + .field("inepnem", &format_args!("{}", self.inepnem().bit())) + .field("txfurm", &format_args!("{}", self.txfurm().bit())) + .field("bim", &format_args!("{}", self.bim().bit())) + .field("berrm", &format_args!("{}", self.berrm().bit())) + .field("nakm", &format_args!("{}", self.nakm().bit())) + .field("nyetm", &format_args!("{}", self.nyetm().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt mask"] #[inline(always)] #[must_use] - pub fn epdm(&mut self) -> EPDM_W<1> { + pub fn epdm(&mut self) -> EPDM_W { EPDM_W::new(self) } #[doc = "Bit 3 - Timeout condition mask"] #[inline(always)] #[must_use] - pub fn tom(&mut self) -> TOM_W<3> { + pub fn tom(&mut self) -> TOM_W { TOM_W::new(self) } #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W { ITTXFEMSK_W::new(self) } #[doc = "Bit 5 - IN token received with EP mismatch mask"] #[inline(always)] #[must_use] - pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + pub fn inepnmm(&mut self) -> INEPNMM_W { INEPNMM_W::new(self) } #[doc = "Bit 6 - IN endpoint NAK effective mask"] #[inline(always)] #[must_use] - pub fn inepnem(&mut self) -> INEPNEM_W<6> { + pub fn inepnem(&mut self) -> INEPNEM_W { INEPNEM_W::new(self) } #[doc = "Bit 8 - OUT packet error mask"] #[inline(always)] #[must_use] - pub fn txfurm(&mut self) -> TXFURM_W<8> { + pub fn txfurm(&mut self) -> TXFURM_W { TXFURM_W::new(self) } #[doc = "Bit 9 - BNA interrupt mask"] #[inline(always)] #[must_use] - pub fn bim(&mut self) -> BIM_W<9> { + pub fn bim(&mut self) -> BIM_W { BIM_W::new(self) } #[doc = "Bit 12 - Bubble error interrupt mask"] #[inline(always)] #[must_use] - pub fn berrm(&mut self) -> BERRM_W<12> { + pub fn berrm(&mut self) -> BERRM_W { BERRM_W::new(self) } #[doc = "Bit 13 - NAK interrupt mask"] #[inline(always)] #[must_use] - pub fn nakm(&mut self) -> NAKM_W<13> { + pub fn nakm(&mut self) -> NAKM_W { NAKM_W::new(self) } #[doc = "Bit 14 - NYET interrupt mask"] #[inline(always)] #[must_use] - pub fn nyetm(&mut self) -> NYETM_W<14> { + pub fn nyetm(&mut self) -> NYETM_W { NYETM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device each OUT endpoint-1 interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepeachmsk1](index.html) module"] +#[doc = "OTG_HS device each OUT endpoint-1 interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepeachmsk1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepeachmsk1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPEACHMSK1_SPEC; impl crate::RegisterSpec for DOEPEACHMSK1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepeachmsk1::R](R) reader structure"] -impl crate::Readable for DOEPEACHMSK1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepeachmsk1::W](W) writer structure"] +#[doc = "`read()` method returns [`doepeachmsk1::R`](R) reader structure"] +impl crate::Readable for DOEPEACHMSK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepeachmsk1::W`](W) writer structure"] impl crate::Writable for DOEPEACHMSK1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/doepmsk.rs b/crates/bcm2711-lpa/src/usb_otg_device/doepmsk.rs index 46e5ca8..dbed437 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/doepmsk.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/doepmsk.rs @@ -1,67 +1,35 @@ #[doc = "Register `DOEPMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] -pub type EPDM_R = crate::BitReader; +pub type EPDM_R = crate::BitReader; #[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] -pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type EPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STUPM` reader - SETUP phase done mask"] -pub type STUPM_R = crate::BitReader; +pub type STUPM_R = crate::BitReader; #[doc = "Field `STUPM` writer - SETUP phase done mask"] -pub type STUPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type STUPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OTEPDM` reader - OUT token received when endpoint disabled mask"] -pub type OTEPDM_R = crate::BitReader; +pub type OTEPDM_R = crate::BitReader; #[doc = "Field `OTEPDM` writer - OUT token received when endpoint disabled mask"] -pub type OTEPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type OTEPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `B2BSTUP` reader - Back-to-back SETUP packets received mask"] -pub type B2BSTUP_R = crate::BitReader; +pub type B2BSTUP_R = crate::BitReader; #[doc = "Field `B2BSTUP` writer - Back-to-back SETUP packets received mask"] -pub type B2BSTUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type B2BSTUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OPEM` reader - OUT packet error mask"] -pub type OPEM_R = crate::BitReader; +pub type OPEM_R = crate::BitReader; #[doc = "Field `OPEM` writer - OUT packet error mask"] -pub type OPEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type OPEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOIM` reader - BNA interrupt mask"] -pub type BOIM_R = crate::BitReader; +pub type BOIM_R = crate::BitReader; #[doc = "Field `BOIM` writer - BNA interrupt mask"] -pub type BOIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type BOIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] @@ -99,68 +67,87 @@ impl R { BOIM_R::new(((self.bits >> 9) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPMSK") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("epdm", &format_args!("{}", self.epdm().bit())) + .field("stupm", &format_args!("{}", self.stupm().bit())) + .field("otepdm", &format_args!("{}", self.otepdm().bit())) + .field("b2bstup", &format_args!("{}", self.b2bstup().bit())) + .field("opem", &format_args!("{}", self.opem().bit())) + .field("boim", &format_args!("{}", self.boim().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt mask"] #[inline(always)] #[must_use] - pub fn epdm(&mut self) -> EPDM_W<1> { + pub fn epdm(&mut self) -> EPDM_W { EPDM_W::new(self) } #[doc = "Bit 3 - SETUP phase done mask"] #[inline(always)] #[must_use] - pub fn stupm(&mut self) -> STUPM_W<3> { + pub fn stupm(&mut self) -> STUPM_W { STUPM_W::new(self) } #[doc = "Bit 4 - OUT token received when endpoint disabled mask"] #[inline(always)] #[must_use] - pub fn otepdm(&mut self) -> OTEPDM_W<4> { + pub fn otepdm(&mut self) -> OTEPDM_W { OTEPDM_W::new(self) } #[doc = "Bit 6 - Back-to-back SETUP packets received mask"] #[inline(always)] #[must_use] - pub fn b2bstup(&mut self) -> B2BSTUP_W<6> { + pub fn b2bstup(&mut self) -> B2BSTUP_W { B2BSTUP_W::new(self) } #[doc = "Bit 8 - OUT packet error mask"] #[inline(always)] #[must_use] - pub fn opem(&mut self) -> OPEM_W<8> { + pub fn opem(&mut self) -> OPEM_W { OPEM_W::new(self) } #[doc = "Bit 9 - BNA interrupt mask"] #[inline(always)] #[must_use] - pub fn boim(&mut self) -> BOIM_W<9> { + pub fn boim(&mut self) -> BOIM_W { BOIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device OUT endpoint common interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepmsk](index.html) module"] +#[doc = "OTG_HS device OUT endpoint common interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPMSK_SPEC; impl crate::RegisterSpec for DOEPMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepmsk::R](R) reader structure"] -impl crate::Readable for DOEPMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`doepmsk::R`](R) reader structure"] +impl crate::Readable for DOEPMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepmsk::W`](W) writer structure"] impl crate::Writable for DOEPMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/dsts.rs b/crates/bcm2711-lpa/src/usb_otg_device/dsts.rs index ddf0900..3d4bf4f 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/dsts.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/dsts.rs @@ -1,26 +1,13 @@ #[doc = "Register `DSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SUSPSTS` reader - Suspend status"] -pub type SUSPSTS_R = crate::BitReader; +pub type SUSPSTS_R = crate::BitReader; #[doc = "Field `ENUMSPD` reader - Enumerated speed"] -pub type ENUMSPD_R = crate::FieldReader; +pub type ENUMSPD_R = crate::FieldReader; #[doc = "Field `EERR` reader - Erratic error"] -pub type EERR_R = crate::BitReader; +pub type EERR_R = crate::BitReader; #[doc = "Field `FNSOF` reader - Frame number of the received SOF"] -pub type FNSOF_R = crate::FieldReader; +pub type FNSOF_R = crate::FieldReader; impl R { #[doc = "Bit 0 - Suspend status"] #[inline(always)] @@ -43,15 +30,28 @@ impl R { FNSOF_R::new(((self.bits >> 8) & 0x3fff) as u16) } } -#[doc = "OTG_HS device status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dsts](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSTS") + .field("suspsts", &format_args!("{}", self.suspsts().bit())) + .field("enumspd", &format_args!("{}", self.enumspd().bits())) + .field("eerr", &format_args!("{}", self.eerr().bit())) + .field("fnsof", &format_args!("{}", self.fnsof().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS device status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsts::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DSTS_SPEC; impl crate::RegisterSpec for DSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dsts::R](R) reader structure"] -impl crate::Readable for DSTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`dsts::R`](R) reader structure"] +impl crate::Readable for DSTS_SPEC {} #[doc = "`reset()` method sets DSTS to value 0x10"] impl crate::Resettable for DSTS_SPEC { const RESET_VALUE: Self::Ux = 0x10; diff --git a/crates/bcm2711-lpa/src/usb_otg_device/dthrctl.rs b/crates/bcm2711-lpa/src/usb_otg_device/dthrctl.rs index ea85092..5044505 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/dthrctl.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/dthrctl.rs @@ -1,63 +1,31 @@ #[doc = "Register `DTHRCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DTHRCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NONISOTHREN` reader - Nonisochronous IN endpoints threshold enable"] -pub type NONISOTHREN_R = crate::BitReader; +pub type NONISOTHREN_R = crate::BitReader; #[doc = "Field `NONISOTHREN` writer - Nonisochronous IN endpoints threshold enable"] -pub type NONISOTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +pub type NONISOTHREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISOTHREN` reader - ISO IN endpoint threshold enable"] -pub type ISOTHREN_R = crate::BitReader; +pub type ISOTHREN_R = crate::BitReader; #[doc = "Field `ISOTHREN` writer - ISO IN endpoint threshold enable"] -pub type ISOTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +pub type ISOTHREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXTHRLEN` reader - Transmit threshold length"] -pub type TXTHRLEN_R = crate::FieldReader; +pub type TXTHRLEN_R = crate::FieldReader; #[doc = "Field `TXTHRLEN` writer - Transmit threshold length"] -pub type TXTHRLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DTHRCTL_SPEC, u16, u16, 9, O>; +pub type TXTHRLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 9, O, u16>; #[doc = "Field `RXTHREN` reader - Receive threshold enable"] -pub type RXTHREN_R = crate::BitReader; +pub type RXTHREN_R = crate::BitReader; #[doc = "Field `RXTHREN` writer - Receive threshold enable"] -pub type RXTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +pub type RXTHREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXTHRLEN` reader - Receive threshold length"] -pub type RXTHRLEN_R = crate::FieldReader; +pub type RXTHRLEN_R = crate::FieldReader; #[doc = "Field `RXTHRLEN` writer - Receive threshold length"] -pub type RXTHRLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DTHRCTL_SPEC, u16, u16, 9, O>; +pub type RXTHRLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 9, O, u16>; #[doc = "Field `ARPEN` reader - Arbiter parking enable"] -pub type ARPEN_R = crate::BitReader; +pub type ARPEN_R = crate::BitReader; #[doc = "Field `ARPEN` writer - Arbiter parking enable"] -pub type ARPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +pub type ARPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Nonisochronous IN endpoints threshold enable"] #[inline(always)] @@ -90,62 +58,80 @@ impl R { ARPEN_R::new(((self.bits >> 27) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DTHRCTL") + .field("nonisothren", &format_args!("{}", self.nonisothren().bit())) + .field("isothren", &format_args!("{}", self.isothren().bit())) + .field("txthrlen", &format_args!("{}", self.txthrlen().bits())) + .field("rxthren", &format_args!("{}", self.rxthren().bit())) + .field("rxthrlen", &format_args!("{}", self.rxthrlen().bits())) + .field("arpen", &format_args!("{}", self.arpen().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Nonisochronous IN endpoints threshold enable"] #[inline(always)] #[must_use] - pub fn nonisothren(&mut self) -> NONISOTHREN_W<0> { + pub fn nonisothren(&mut self) -> NONISOTHREN_W { NONISOTHREN_W::new(self) } #[doc = "Bit 1 - ISO IN endpoint threshold enable"] #[inline(always)] #[must_use] - pub fn isothren(&mut self) -> ISOTHREN_W<1> { + pub fn isothren(&mut self) -> ISOTHREN_W { ISOTHREN_W::new(self) } #[doc = "Bits 2:10 - Transmit threshold length"] #[inline(always)] #[must_use] - pub fn txthrlen(&mut self) -> TXTHRLEN_W<2> { + pub fn txthrlen(&mut self) -> TXTHRLEN_W { TXTHRLEN_W::new(self) } #[doc = "Bit 16 - Receive threshold enable"] #[inline(always)] #[must_use] - pub fn rxthren(&mut self) -> RXTHREN_W<16> { + pub fn rxthren(&mut self) -> RXTHREN_W { RXTHREN_W::new(self) } #[doc = "Bits 17:25 - Receive threshold length"] #[inline(always)] #[must_use] - pub fn rxthrlen(&mut self) -> RXTHRLEN_W<17> { + pub fn rxthrlen(&mut self) -> RXTHRLEN_W { RXTHRLEN_W::new(self) } #[doc = "Bit 27 - Arbiter parking enable"] #[inline(always)] #[must_use] - pub fn arpen(&mut self) -> ARPEN_W<27> { + pub fn arpen(&mut self) -> ARPEN_W { ARPEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS Device threshold control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dthrctl](index.html) module"] +#[doc = "OTG_HS Device threshold control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dthrctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dthrctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DTHRCTL_SPEC; impl crate::RegisterSpec for DTHRCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dthrctl::R](R) reader structure"] -impl crate::Readable for DTHRCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dthrctl::W](W) writer structure"] +#[doc = "`read()` method returns [`dthrctl::R`](R) reader structure"] +impl crate::Readable for DTHRCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dthrctl::W`](W) writer structure"] impl crate::Writable for DTHRCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/dvbusdis.rs b/crates/bcm2711-lpa/src/usb_otg_device/dvbusdis.rs index 403e00a..06b297e 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/dvbusdis.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/dvbusdis.rs @@ -1,43 +1,11 @@ #[doc = "Register `DVBUSDIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DVBUSDIS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VBUSDT` reader - Device VBUS discharge time"] -pub type VBUSDT_R = crate::FieldReader; +pub type VBUSDT_R = crate::FieldReader; #[doc = "Field `VBUSDT` writer - Device VBUS discharge time"] -pub type VBUSDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DVBUSDIS_SPEC, u16, u16, 16, O>; +pub type VBUSDT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Device VBUS discharge time"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { VBUSDT_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DVBUSDIS") + .field("vbusdt", &format_args!("{}", self.vbusdt().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Device VBUS discharge time"] #[inline(always)] #[must_use] - pub fn vbusdt(&mut self) -> VBUSDT_W<0> { + pub fn vbusdt(&mut self) -> VBUSDT_W { VBUSDT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device VBUS discharge time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbusdis](index.html) module"] +#[doc = "OTG_HS device VBUS discharge time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dvbusdis::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dvbusdis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DVBUSDIS_SPEC; impl crate::RegisterSpec for DVBUSDIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dvbusdis::R](R) reader structure"] -impl crate::Readable for DVBUSDIS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dvbusdis::W](W) writer structure"] +#[doc = "`read()` method returns [`dvbusdis::R`](R) reader structure"] +impl crate::Readable for DVBUSDIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dvbusdis::W`](W) writer structure"] impl crate::Writable for DVBUSDIS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/dvbuspulse.rs b/crates/bcm2711-lpa/src/usb_otg_device/dvbuspulse.rs index 4871f7b..52acecf 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/dvbuspulse.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/dvbuspulse.rs @@ -1,43 +1,11 @@ #[doc = "Register `DVBUSPULSE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DVBUSPULSE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DVBUSP` reader - Device VBUS pulsing time"] -pub type DVBUSP_R = crate::FieldReader; +pub type DVBUSP_R = crate::FieldReader; #[doc = "Field `DVBUSP` writer - Device VBUS pulsing time"] -pub type DVBUSP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DVBUSPULSE_SPEC, u16, u16, 12, O>; +pub type DVBUSP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; impl R { #[doc = "Bits 0:11 - Device VBUS pulsing time"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DVBUSP_R::new((self.bits & 0x0fff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DVBUSPULSE") + .field("dvbusp", &format_args!("{}", self.dvbusp().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:11 - Device VBUS pulsing time"] #[inline(always)] #[must_use] - pub fn dvbusp(&mut self) -> DVBUSP_W<0> { + pub fn dvbusp(&mut self) -> DVBUSP_W { DVBUSP_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device VBUS pulsing time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbuspulse](index.html) module"] +#[doc = "OTG_HS device VBUS pulsing time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dvbuspulse::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dvbuspulse::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DVBUSPULSE_SPEC; impl crate::RegisterSpec for DVBUSPULSE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dvbuspulse::R](R) reader structure"] -impl crate::Readable for DVBUSPULSE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dvbuspulse::W](W) writer structure"] +#[doc = "`read()` method returns [`dvbuspulse::R`](R) reader structure"] +impl crate::Readable for DVBUSPULSE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dvbuspulse::W`](W) writer structure"] impl crate::Writable for DVBUSPULSE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint.rs b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint.rs index 5fd5349..0e94feb 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct IN_ENDPOINT { #[doc = "0x00 - Control"] pub diepctl0: DIEPCTL0, @@ -14,23 +15,28 @@ pub struct IN_ENDPOINT { #[doc = "0x18 - Transmit FIFO status"] pub dtxfsts: DTXFSTS, } -#[doc = "DIEPCTL0 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPCTL0 (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepctl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepctl0`] +module"] pub type DIEPCTL0 = crate::Reg; #[doc = "Control"] pub mod diepctl0; -#[doc = "DIEPINT (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPINT (rw) register accessor: Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepint`] +module"] pub type DIEPINT = crate::Reg; #[doc = "Interrupt"] pub mod diepint; -#[doc = "DIEPTSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTSIZ (rw) register accessor: Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptsiz`] +module"] pub type DIEPTSIZ = crate::Reg; #[doc = "Transfer size"] pub mod dieptsiz; -#[doc = "DIEPDMA (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPDMA (rw) register accessor: DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepdma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepdma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepdma`] +module"] pub type DIEPDMA = crate::Reg; #[doc = "DMA address"] pub mod diepdma; -#[doc = "DTXFSTS (r) register accessor: an alias for `Reg`"] +#[doc = "DTXFSTS (r) register accessor: Transmit FIFO status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtxfsts::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtxfsts`] +module"] pub type DTXFSTS = crate::Reg; #[doc = "Transmit FIFO status"] pub mod dtxfsts; diff --git a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs index b8fa051..899b0d7 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs @@ -1,79 +1,47 @@ #[doc = "Register `DIEPCTL0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPCTL0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MPSIZ` reader - Maximum packet size"] -pub type MPSIZ_R = crate::FieldReader; +pub type MPSIZ_R = crate::FieldReader; #[doc = "Field `MPSIZ` writer - Maximum packet size"] -pub type MPSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u16, u16, 11, O>; +pub type MPSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 11, O, u16>; #[doc = "Field `USBAEP` reader - USB active endpoint"] -pub type USBAEP_R = crate::BitReader; +pub type USBAEP_R = crate::BitReader; #[doc = "Field `USBAEP` writer - USB active endpoint"] -pub type USBAEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type USBAEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EONUM_DPID` reader - Even/odd frame"] -pub type EONUM_DPID_R = crate::BitReader; +pub type EONUM_DPID_R = crate::BitReader; #[doc = "Field `NAKSTS` reader - NAK status"] -pub type NAKSTS_R = crate::BitReader; +pub type NAKSTS_R = crate::BitReader; #[doc = "Field `EPTYP` reader - Endpoint type"] -pub type EPTYP_R = crate::FieldReader; +pub type EPTYP_R = crate::FieldReader; #[doc = "Field `EPTYP` writer - Endpoint type"] -pub type EPTYP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u8, u8, 2, O>; +pub type EPTYP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `Stall` reader - STALL handshake"] -pub type STALL_R = crate::BitReader; +pub type STALL_R = crate::BitReader; #[doc = "Field `Stall` writer - STALL handshake"] -pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFNUM` reader - TxFIFO number"] -pub type TXFNUM_R = crate::FieldReader; +pub type TXFNUM_R = crate::FieldReader; #[doc = "Field `TXFNUM` writer - TxFIFO number"] -pub type TXFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u8, u8, 4, O>; +pub type TXFNUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CNAK` writer - Clear NAK"] -pub type CNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type CNAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SNAK` writer - Set NAK"] -pub type SNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type SNAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SD0PID_SEVNFRM` writer - Set DATA0 PID"] -pub type SD0PID_SEVNFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type SD0PID_SEVNFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SODDFRM` writer - Set odd frame"] -pub type SODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type SODDFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDIS` reader - Endpoint disable"] -pub type EPDIS_R = crate::BitReader; +pub type EPDIS_R = crate::BitReader; #[doc = "Field `EPDIS` writer - Endpoint disable"] -pub type EPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type EPDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPENA` reader - Endpoint enable"] -pub type EPENA_R = crate::BitReader; +pub type EPENA_R = crate::BitReader; #[doc = "Field `EPENA` writer - Endpoint enable"] -pub type EPENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type EPENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] @@ -121,92 +89,113 @@ impl R { EPENA_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPCTL0") + .field("mpsiz", &format_args!("{}", self.mpsiz().bits())) + .field("usbaep", &format_args!("{}", self.usbaep().bit())) + .field("eonum_dpid", &format_args!("{}", self.eonum_dpid().bit())) + .field("naksts", &format_args!("{}", self.naksts().bit())) + .field("eptyp", &format_args!("{}", self.eptyp().bits())) + .field("stall", &format_args!("{}", self.stall().bit())) + .field("txfnum", &format_args!("{}", self.txfnum().bits())) + .field("epdis", &format_args!("{}", self.epdis().bit())) + .field("epena", &format_args!("{}", self.epena().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] #[must_use] - pub fn mpsiz(&mut self) -> MPSIZ_W<0> { + pub fn mpsiz(&mut self) -> MPSIZ_W { MPSIZ_W::new(self) } #[doc = "Bit 15 - USB active endpoint"] #[inline(always)] #[must_use] - pub fn usbaep(&mut self) -> USBAEP_W<15> { + pub fn usbaep(&mut self) -> USBAEP_W { USBAEP_W::new(self) } #[doc = "Bits 18:19 - Endpoint type"] #[inline(always)] #[must_use] - pub fn eptyp(&mut self) -> EPTYP_W<18> { + pub fn eptyp(&mut self) -> EPTYP_W { EPTYP_W::new(self) } #[doc = "Bit 21 - STALL handshake"] #[inline(always)] #[must_use] - pub fn stall(&mut self) -> STALL_W<21> { + pub fn stall(&mut self) -> STALL_W { STALL_W::new(self) } #[doc = "Bits 22:25 - TxFIFO number"] #[inline(always)] #[must_use] - pub fn txfnum(&mut self) -> TXFNUM_W<22> { + pub fn txfnum(&mut self) -> TXFNUM_W { TXFNUM_W::new(self) } #[doc = "Bit 26 - Clear NAK"] #[inline(always)] #[must_use] - pub fn cnak(&mut self) -> CNAK_W<26> { + pub fn cnak(&mut self) -> CNAK_W { CNAK_W::new(self) } #[doc = "Bit 27 - Set NAK"] #[inline(always)] #[must_use] - pub fn snak(&mut self) -> SNAK_W<27> { + pub fn snak(&mut self) -> SNAK_W { SNAK_W::new(self) } #[doc = "Bit 28 - Set DATA0 PID"] #[inline(always)] #[must_use] - pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<28> { + pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W { SD0PID_SEVNFRM_W::new(self) } #[doc = "Bit 29 - Set odd frame"] #[inline(always)] #[must_use] - pub fn soddfrm(&mut self) -> SODDFRM_W<29> { + pub fn soddfrm(&mut self) -> SODDFRM_W { SODDFRM_W::new(self) } #[doc = "Bit 30 - Endpoint disable"] #[inline(always)] #[must_use] - pub fn epdis(&mut self) -> EPDIS_W<30> { + pub fn epdis(&mut self) -> EPDIS_W { EPDIS_W::new(self) } #[doc = "Bit 31 - Endpoint enable"] #[inline(always)] #[must_use] - pub fn epena(&mut self) -> EPENA_W<31> { + pub fn epena(&mut self) -> EPENA_W { EPENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepctl0](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPCTL0_SPEC; impl crate::RegisterSpec for DIEPCTL0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepctl0::R](R) reader structure"] -impl crate::Readable for DIEPCTL0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepctl0::W](W) writer structure"] +#[doc = "`read()` method returns [`diepctl0::R`](R) reader structure"] +impl crate::Readable for DIEPCTL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepctl0::W`](W) writer structure"] impl crate::Writable for DIEPCTL0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepdma.rs b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepdma.rs index 321905e..18f13ad 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepdma.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepdma.rs @@ -1,43 +1,11 @@ #[doc = "Register `DIEPDMA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPDMA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMAADDR` reader - DMA address"] -pub type DMAADDR_R = crate::FieldReader; +pub type DMAADDR_R = crate::FieldReader; #[doc = "Field `DMAADDR` writer - DMA address"] -pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPDMA_SPEC, u32, u32, 32, O>; +pub type DMAADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DMAADDR_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPDMA") + .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] #[must_use] - pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + pub fn dmaaddr(&mut self) -> DMAADDR_W { DMAADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepdma](index.html) module"] +#[doc = "DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepdma::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepdma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPDMA_SPEC; impl crate::RegisterSpec for DIEPDMA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepdma::R](R) reader structure"] -impl crate::Readable for DIEPDMA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepdma::W](W) writer structure"] +#[doc = "`read()` method returns [`diepdma::R`](R) reader structure"] +impl crate::Readable for DIEPDMA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepdma::W`](W) writer structure"] impl crate::Writable for DIEPDMA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepint.rs b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepint.rs index f85ca85..bd21aa2 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepint.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/diepint.rs @@ -1,81 +1,49 @@ #[doc = "Register `DIEPINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRC` reader - Transfer completed interrupt"] -pub type XFRC_R = crate::BitReader; +pub type XFRC_R = crate::BitReader; #[doc = "Field `XFRC` writer - Transfer completed interrupt"] -pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type XFRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISD` reader - Endpoint disabled interrupt"] -pub type EPDISD_R = crate::BitReader; +pub type EPDISD_R = crate::BitReader; #[doc = "Field `EPDISD` writer - Endpoint disabled interrupt"] -pub type EPDISD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type EPDISD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOC` reader - Timeout condition"] -pub type TOC_R = crate::BitReader; +pub type TOC_R = crate::BitReader; #[doc = "Field `TOC` writer - Timeout condition"] -pub type TOC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type TOC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITTXFE` reader - IN token received when TxFIFO is empty"] -pub type ITTXFE_R = crate::BitReader; +pub type ITTXFE_R = crate::BitReader; #[doc = "Field `ITTXFE` writer - IN token received when TxFIFO is empty"] -pub type ITTXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type ITTXFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNE` reader - IN endpoint NAK effective"] -pub type INEPNE_R = crate::BitReader; +pub type INEPNE_R = crate::BitReader; #[doc = "Field `INEPNE` writer - IN endpoint NAK effective"] -pub type INEPNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type INEPNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFE` reader - Transmit FIFO empty"] -pub type TXFE_R = crate::BitReader; +pub type TXFE_R = crate::BitReader; #[doc = "Field `TXFIFOUDRN` reader - Transmit Fifo Underrun"] -pub type TXFIFOUDRN_R = crate::BitReader; +pub type TXFIFOUDRN_R = crate::BitReader; #[doc = "Field `TXFIFOUDRN` writer - Transmit Fifo Underrun"] -pub type TXFIFOUDRN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type TXFIFOUDRN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BNA` reader - Buffer not available interrupt"] -pub type BNA_R = crate::BitReader; +pub type BNA_R = crate::BitReader; #[doc = "Field `BNA` writer - Buffer not available interrupt"] -pub type BNA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type BNA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PKTDRPSTS` reader - Packet dropped status"] -pub type PKTDRPSTS_R = crate::BitReader; +pub type PKTDRPSTS_R = crate::BitReader; #[doc = "Field `PKTDRPSTS` writer - Packet dropped status"] -pub type PKTDRPSTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type PKTDRPSTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BERR` reader - Babble error interrupt"] -pub type BERR_R = crate::BitReader; +pub type BERR_R = crate::BitReader; #[doc = "Field `BERR` writer - Babble error interrupt"] -pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type BERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAK` reader - NAK interrupt"] -pub type NAK_R = crate::BitReader; +pub type NAK_R = crate::BitReader; #[doc = "Field `NAK` writer - NAK interrupt"] -pub type NAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type NAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt"] #[inline(always)] @@ -133,86 +101,109 @@ impl R { NAK_R::new(((self.bits >> 13) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPINT") + .field("xfrc", &format_args!("{}", self.xfrc().bit())) + .field("epdisd", &format_args!("{}", self.epdisd().bit())) + .field("toc", &format_args!("{}", self.toc().bit())) + .field("ittxfe", &format_args!("{}", self.ittxfe().bit())) + .field("inepne", &format_args!("{}", self.inepne().bit())) + .field("txfe", &format_args!("{}", self.txfe().bit())) + .field("txfifoudrn", &format_args!("{}", self.txfifoudrn().bit())) + .field("bna", &format_args!("{}", self.bna().bit())) + .field("pktdrpsts", &format_args!("{}", self.pktdrpsts().bit())) + .field("berr", &format_args!("{}", self.berr().bit())) + .field("nak", &format_args!("{}", self.nak().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt"] #[inline(always)] #[must_use] - pub fn xfrc(&mut self) -> XFRC_W<0> { + pub fn xfrc(&mut self) -> XFRC_W { XFRC_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt"] #[inline(always)] #[must_use] - pub fn epdisd(&mut self) -> EPDISD_W<1> { + pub fn epdisd(&mut self) -> EPDISD_W { EPDISD_W::new(self) } #[doc = "Bit 3 - Timeout condition"] #[inline(always)] #[must_use] - pub fn toc(&mut self) -> TOC_W<3> { + pub fn toc(&mut self) -> TOC_W { TOC_W::new(self) } #[doc = "Bit 4 - IN token received when TxFIFO is empty"] #[inline(always)] #[must_use] - pub fn ittxfe(&mut self) -> ITTXFE_W<4> { + pub fn ittxfe(&mut self) -> ITTXFE_W { ITTXFE_W::new(self) } #[doc = "Bit 6 - IN endpoint NAK effective"] #[inline(always)] #[must_use] - pub fn inepne(&mut self) -> INEPNE_W<6> { + pub fn inepne(&mut self) -> INEPNE_W { INEPNE_W::new(self) } #[doc = "Bit 8 - Transmit Fifo Underrun"] #[inline(always)] #[must_use] - pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<8> { + pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W { TXFIFOUDRN_W::new(self) } #[doc = "Bit 9 - Buffer not available interrupt"] #[inline(always)] #[must_use] - pub fn bna(&mut self) -> BNA_W<9> { + pub fn bna(&mut self) -> BNA_W { BNA_W::new(self) } #[doc = "Bit 11 - Packet dropped status"] #[inline(always)] #[must_use] - pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<11> { + pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W { PKTDRPSTS_W::new(self) } #[doc = "Bit 12 - Babble error interrupt"] #[inline(always)] #[must_use] - pub fn berr(&mut self) -> BERR_W<12> { + pub fn berr(&mut self) -> BERR_W { BERR_W::new(self) } #[doc = "Bit 13 - NAK interrupt"] #[inline(always)] #[must_use] - pub fn nak(&mut self) -> NAK_W<13> { + pub fn nak(&mut self) -> NAK_W { NAK_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepint](index.html) module"] +#[doc = "Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPINT_SPEC; impl crate::RegisterSpec for DIEPINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepint::R](R) reader structure"] -impl crate::Readable for DIEPINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepint::W](W) writer structure"] +#[doc = "`read()` method returns [`diepint::R`](R) reader structure"] +impl crate::Readable for DIEPINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepint::W`](W) writer structure"] impl crate::Writable for DIEPINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs index 7f94dcb..72226f2 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRSIZ` reader - Transfer size"] -pub type XFRSIZ_R = crate::FieldReader; +pub type XFRSIZ_R = crate::FieldReader; #[doc = "Field `XFRSIZ` writer - Transfer size"] -pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTSIZ_SPEC, u8, u8, 7, O>; +pub type XFRSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `PKTCNT` reader - Packet count"] -pub type PKTCNT_R = crate::FieldReader; +pub type PKTCNT_R = crate::FieldReader; #[doc = "Field `PKTCNT` writer - Packet count"] -pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTSIZ_SPEC, u8, u8, 2, O>; +pub type PKTCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:6 - Transfer size"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { PKTCNT_R::new(((self.bits >> 19) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTSIZ") + .field("xfrsiz", &format_args!("{}", self.xfrsiz().bits())) + .field("pktcnt", &format_args!("{}", self.pktcnt().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - Transfer size"] #[inline(always)] #[must_use] - pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + pub fn xfrsiz(&mut self) -> XFRSIZ_W { XFRSIZ_W::new(self) } #[doc = "Bits 19:20 - Packet count"] #[inline(always)] #[must_use] - pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + pub fn pktcnt(&mut self) -> PKTCNT_W { PKTCNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptsiz](index.html) module"] +#[doc = "Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTSIZ_SPEC; impl crate::RegisterSpec for DIEPTSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptsiz::R](R) reader structure"] -impl crate::Readable for DIEPTSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptsiz::R`](R) reader structure"] +impl crate::Readable for DIEPTSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptsiz::W`](W) writer structure"] impl crate::Writable for DIEPTSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs index c962826..abe4eef 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs @@ -1,20 +1,7 @@ #[doc = "Register `DTXFSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `INEPTFSAV` reader - IN endpoint TxFIFO space avail"] -pub type INEPTFSAV_R = crate::FieldReader; +pub type INEPTFSAV_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - IN endpoint TxFIFO space avail"] #[inline(always)] @@ -22,15 +9,25 @@ impl R { INEPTFSAV_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Transmit FIFO status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dtxfsts](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DTXFSTS") + .field("ineptfsav", &format_args!("{}", self.ineptfsav().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Transmit FIFO status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtxfsts::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DTXFSTS_SPEC; impl crate::RegisterSpec for DTXFSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dtxfsts::R](R) reader structure"] -impl crate::Readable for DTXFSTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`dtxfsts::R`](R) reader structure"] +impl crate::Readable for DTXFSTS_SPEC {} #[doc = "`reset()` method sets DTXFSTS to value 0"] impl crate::Resettable for DTXFSTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint.rs b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint.rs index a3a9e56..360b7f9 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct OUT_ENDPOINT { #[doc = "0x00 - Control"] pub doepctl: DOEPCTL, @@ -12,19 +13,23 @@ pub struct OUT_ENDPOINT { #[doc = "0x14 - DMA address"] pub doepdma: DOEPDMA, } -#[doc = "DOEPCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPCTL (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepctl`] +module"] pub type DOEPCTL = crate::Reg; #[doc = "Control"] pub mod doepctl; -#[doc = "DOEPINT (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPINT (rw) register accessor: Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepint`] +module"] pub type DOEPINT = crate::Reg; #[doc = "Interrupt"] pub mod doepint; -#[doc = "DOEPTSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPTSIZ (rw) register accessor: Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doeptsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doeptsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doeptsiz`] +module"] pub type DOEPTSIZ = crate::Reg; #[doc = "Transfer size"] pub mod doeptsiz; -#[doc = "DOEPDMA (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPDMA (rw) register accessor: DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepdma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepdma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepdma`] +module"] pub type DOEPDMA = crate::Reg; #[doc = "DMA address"] pub mod doepdma; diff --git a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepctl.rs b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepctl.rs index 2f6baf5..47f7dd2 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepctl.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepctl.rs @@ -1,63 +1,31 @@ #[doc = "Register `DOEPCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MPSIZ` reader - Maximum packet size"] -pub type MPSIZ_R = crate::FieldReader; +pub type MPSIZ_R = crate::FieldReader; #[doc = "Field `USBAEP` reader - USB active endpoint"] -pub type USBAEP_R = crate::BitReader; +pub type USBAEP_R = crate::BitReader; #[doc = "Field `NAKSTS` reader - NAK status"] -pub type NAKSTS_R = crate::BitReader; +pub type NAKSTS_R = crate::BitReader; #[doc = "Field `EPTYP` reader - Endpoint type"] -pub type EPTYP_R = crate::FieldReader; +pub type EPTYP_R = crate::FieldReader; #[doc = "Field `SNPM` reader - Snoop mode"] -pub type SNPM_R = crate::BitReader; +pub type SNPM_R = crate::BitReader; #[doc = "Field `SNPM` writer - Snoop mode"] -pub type SNPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type SNPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `Stall` reader - STALL handshake"] -pub type STALL_R = crate::BitReader; +pub type STALL_R = crate::BitReader; #[doc = "Field `Stall` writer - STALL handshake"] -pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CNAK` writer - Clear NAK"] -pub type CNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type CNAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SNAK` writer - Set NAK"] -pub type SNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type SNAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDIS` reader - Endpoint disable"] -pub type EPDIS_R = crate::BitReader; +pub type EPDIS_R = crate::BitReader; #[doc = "Field `EPENA` writer - Endpoint enable"] -pub type EPENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type EPENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:1 - Maximum packet size"] #[inline(always)] @@ -95,56 +63,75 @@ impl R { EPDIS_R::new(((self.bits >> 30) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPCTL") + .field("mpsiz", &format_args!("{}", self.mpsiz().bits())) + .field("usbaep", &format_args!("{}", self.usbaep().bit())) + .field("naksts", &format_args!("{}", self.naksts().bit())) + .field("eptyp", &format_args!("{}", self.eptyp().bits())) + .field("snpm", &format_args!("{}", self.snpm().bit())) + .field("stall", &format_args!("{}", self.stall().bit())) + .field("epdis", &format_args!("{}", self.epdis().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 20 - Snoop mode"] #[inline(always)] #[must_use] - pub fn snpm(&mut self) -> SNPM_W<20> { + pub fn snpm(&mut self) -> SNPM_W { SNPM_W::new(self) } #[doc = "Bit 21 - STALL handshake"] #[inline(always)] #[must_use] - pub fn stall(&mut self) -> STALL_W<21> { + pub fn stall(&mut self) -> STALL_W { STALL_W::new(self) } #[doc = "Bit 26 - Clear NAK"] #[inline(always)] #[must_use] - pub fn cnak(&mut self) -> CNAK_W<26> { + pub fn cnak(&mut self) -> CNAK_W { CNAK_W::new(self) } #[doc = "Bit 27 - Set NAK"] #[inline(always)] #[must_use] - pub fn snak(&mut self) -> SNAK_W<27> { + pub fn snak(&mut self) -> SNAK_W { SNAK_W::new(self) } #[doc = "Bit 31 - Endpoint enable"] #[inline(always)] #[must_use] - pub fn epena(&mut self) -> EPENA_W<31> { + pub fn epena(&mut self) -> EPENA_W { EPENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepctl](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPCTL_SPEC; impl crate::RegisterSpec for DOEPCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepctl::R](R) reader structure"] -impl crate::Readable for DOEPCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepctl::W](W) writer structure"] +#[doc = "`read()` method returns [`doepctl::R`](R) reader structure"] +impl crate::Readable for DOEPCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepctl::W`](W) writer structure"] impl crate::Writable for DOEPCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepdma.rs b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepdma.rs index 92089f0..ab7d95d 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepdma.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepdma.rs @@ -1,43 +1,11 @@ #[doc = "Register `DOEPDMA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPDMA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMAADDR` reader - DMA address"] -pub type DMAADDR_R = crate::FieldReader; +pub type DMAADDR_R = crate::FieldReader; #[doc = "Field `DMAADDR` writer - DMA address"] -pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPDMA_SPEC, u32, u32, 32, O>; +pub type DMAADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DMAADDR_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPDMA") + .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] #[must_use] - pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + pub fn dmaaddr(&mut self) -> DMAADDR_W { DMAADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepdma](index.html) module"] +#[doc = "DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepdma::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepdma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPDMA_SPEC; impl crate::RegisterSpec for DOEPDMA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepdma::R](R) reader structure"] -impl crate::Readable for DOEPDMA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepdma::W](W) writer structure"] +#[doc = "`read()` method returns [`doepdma::R`](R) reader structure"] +impl crate::Readable for DOEPDMA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepdma::W`](W) writer structure"] impl crate::Writable for DOEPDMA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepint.rs b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepint.rs index 365d667..0552c9b 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepint.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doepint.rs @@ -1,63 +1,31 @@ #[doc = "Register `DOEPINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRC` reader - Transfer completed interrupt"] -pub type XFRC_R = crate::BitReader; +pub type XFRC_R = crate::BitReader; #[doc = "Field `XFRC` writer - Transfer completed interrupt"] -pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type XFRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISD` reader - Endpoint disabled interrupt"] -pub type EPDISD_R = crate::BitReader; +pub type EPDISD_R = crate::BitReader; #[doc = "Field `EPDISD` writer - Endpoint disabled interrupt"] -pub type EPDISD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type EPDISD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STUP` reader - SETUP phase done"] -pub type STUP_R = crate::BitReader; +pub type STUP_R = crate::BitReader; #[doc = "Field `STUP` writer - SETUP phase done"] -pub type STUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type STUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OTEPDIS` reader - OUT token received when endpoint disabled"] -pub type OTEPDIS_R = crate::BitReader; +pub type OTEPDIS_R = crate::BitReader; #[doc = "Field `OTEPDIS` writer - OUT token received when endpoint disabled"] -pub type OTEPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type OTEPDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `B2BSTUP` reader - Back-to-back SETUP packets received"] -pub type B2BSTUP_R = crate::BitReader; +pub type B2BSTUP_R = crate::BitReader; #[doc = "Field `B2BSTUP` writer - Back-to-back SETUP packets received"] -pub type B2BSTUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type B2BSTUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYET` reader - NYET interrupt"] -pub type NYET_R = crate::BitReader; +pub type NYET_R = crate::BitReader; #[doc = "Field `NYET` writer - NYET interrupt"] -pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type NYET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt"] #[inline(always)] @@ -90,62 +58,80 @@ impl R { NYET_R::new(((self.bits >> 14) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPINT") + .field("xfrc", &format_args!("{}", self.xfrc().bit())) + .field("epdisd", &format_args!("{}", self.epdisd().bit())) + .field("stup", &format_args!("{}", self.stup().bit())) + .field("otepdis", &format_args!("{}", self.otepdis().bit())) + .field("b2bstup", &format_args!("{}", self.b2bstup().bit())) + .field("nyet", &format_args!("{}", self.nyet().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt"] #[inline(always)] #[must_use] - pub fn xfrc(&mut self) -> XFRC_W<0> { + pub fn xfrc(&mut self) -> XFRC_W { XFRC_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt"] #[inline(always)] #[must_use] - pub fn epdisd(&mut self) -> EPDISD_W<1> { + pub fn epdisd(&mut self) -> EPDISD_W { EPDISD_W::new(self) } #[doc = "Bit 3 - SETUP phase done"] #[inline(always)] #[must_use] - pub fn stup(&mut self) -> STUP_W<3> { + pub fn stup(&mut self) -> STUP_W { STUP_W::new(self) } #[doc = "Bit 4 - OUT token received when endpoint disabled"] #[inline(always)] #[must_use] - pub fn otepdis(&mut self) -> OTEPDIS_W<4> { + pub fn otepdis(&mut self) -> OTEPDIS_W { OTEPDIS_W::new(self) } #[doc = "Bit 6 - Back-to-back SETUP packets received"] #[inline(always)] #[must_use] - pub fn b2bstup(&mut self) -> B2BSTUP_W<6> { + pub fn b2bstup(&mut self) -> B2BSTUP_W { B2BSTUP_W::new(self) } #[doc = "Bit 14 - NYET interrupt"] #[inline(always)] #[must_use] - pub fn nyet(&mut self) -> NYET_W<14> { + pub fn nyet(&mut self) -> NYET_W { NYET_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepint](index.html) module"] +#[doc = "Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPINT_SPEC; impl crate::RegisterSpec for DOEPINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepint::R](R) reader structure"] -impl crate::Readable for DOEPINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepint::W](W) writer structure"] +#[doc = "`read()` method returns [`doepint::R`](R) reader structure"] +impl crate::Readable for DOEPINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepint::W`](W) writer structure"] impl crate::Writable for DOEPINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs index 0f78e4d..4606c37 100644 --- a/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs +++ b/crates/bcm2711-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs @@ -1,51 +1,19 @@ #[doc = "Register `DOEPTSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPTSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRSIZ` reader - Transfer size"] -pub type XFRSIZ_R = crate::FieldReader; +pub type XFRSIZ_R = crate::FieldReader; #[doc = "Field `XFRSIZ` writer - Transfer size"] -pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPTSIZ_SPEC, u8, u8, 7, O>; +pub type XFRSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `PKTCNT` reader - Packet count"] -pub type PKTCNT_R = crate::BitReader; +pub type PKTCNT_R = crate::BitReader; #[doc = "Field `PKTCNT` writer - Packet count"] -pub type PKTCNT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPTSIZ_SPEC, bool, O>; +pub type PKTCNT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STUPCNT` reader - SETUP packet count"] -pub type STUPCNT_R = crate::FieldReader; +pub type STUPCNT_R = crate::FieldReader; #[doc = "Field `STUPCNT` writer - SETUP packet count"] -pub type STUPCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPTSIZ_SPEC, u8, u8, 2, O>; +pub type STUPCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:6 - Transfer size"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { STUPCNT_R::new(((self.bits >> 29) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPTSIZ") + .field("xfrsiz", &format_args!("{}", self.xfrsiz().bits())) + .field("pktcnt", &format_args!("{}", self.pktcnt().bit())) + .field("stupcnt", &format_args!("{}", self.stupcnt().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - Transfer size"] #[inline(always)] #[must_use] - pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + pub fn xfrsiz(&mut self) -> XFRSIZ_W { XFRSIZ_W::new(self) } #[doc = "Bit 19 - Packet count"] #[inline(always)] #[must_use] - pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + pub fn pktcnt(&mut self) -> PKTCNT_W { PKTCNT_W::new(self) } #[doc = "Bits 29:30 - SETUP packet count"] #[inline(always)] #[must_use] - pub fn stupcnt(&mut self) -> STUPCNT_W<29> { + pub fn stupcnt(&mut self) -> STUPCNT_W { STUPCNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doeptsiz](index.html) module"] +#[doc = "Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doeptsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doeptsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPTSIZ_SPEC; impl crate::RegisterSpec for DOEPTSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doeptsiz::R](R) reader structure"] -impl crate::Readable for DOEPTSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doeptsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`doeptsiz::R`](R) reader structure"] +impl crate::Readable for DOEPTSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doeptsiz::W`](W) writer structure"] impl crate::Writable for DOEPTSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global.rs b/crates/bcm2711-lpa/src/usb_otg_global.rs index a6b35cb..d8a5a57 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - OTG_HS control and status register"] pub gotgctl: GOTGCTL, @@ -84,115 +85,143 @@ impl RegisterBlock { unsafe { &*(self as *const Self).cast::().add(40usize).cast() } } } -#[doc = "GOTGCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "GOTGCTL (rw) register accessor: OTG_HS control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gotgctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gotgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gotgctl`] +module"] pub type GOTGCTL = crate::Reg; #[doc = "OTG_HS control and status register"] pub mod gotgctl; -#[doc = "GOTGINT (rw) register accessor: an alias for `Reg`"] +#[doc = "GOTGINT (rw) register accessor: OTG_HS interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gotgint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gotgint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gotgint`] +module"] pub type GOTGINT = crate::Reg; #[doc = "OTG_HS interrupt register"] pub mod gotgint; -#[doc = "GAHBCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "GAHBCFG (rw) register accessor: OTG_HS AHB configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gahbcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gahbcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gahbcfg`] +module"] pub type GAHBCFG = crate::Reg; #[doc = "OTG_HS AHB configuration register"] pub mod gahbcfg; -#[doc = "GUSBCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "GUSBCFG (rw) register accessor: OTG_HS USB configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gusbcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gusbcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gusbcfg`] +module"] pub type GUSBCFG = crate::Reg; #[doc = "OTG_HS USB configuration register"] pub mod gusbcfg; -#[doc = "GRSTCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "GRSTCTL (rw) register accessor: OTG_HS reset register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grstctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grstctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grstctl`] +module"] pub type GRSTCTL = crate::Reg; #[doc = "OTG_HS reset register"] pub mod grstctl; -#[doc = "GINTSTS (rw) register accessor: an alias for `Reg`"] +#[doc = "GINTSTS (rw) register accessor: OTG_HS core interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gintsts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gintsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gintsts`] +module"] pub type GINTSTS = crate::Reg; #[doc = "OTG_HS core interrupt register"] pub mod gintsts; -#[doc = "GINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "GINTMSK (rw) register accessor: OTG_HS interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gintmsk`] +module"] pub type GINTMSK = crate::Reg; #[doc = "OTG_HS interrupt mask register"] pub mod gintmsk; -#[doc = "GRXSTSR_Host (r) register accessor: an alias for `Reg`"] +#[doc = "GRXSTSR_Host (r) register accessor: OTG_HS Receive status debug read register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr_host::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsr_host`] +module"] pub type GRXSTSR_HOST = crate::Reg; #[doc = "OTG_HS Receive status debug read register (host mode)"] pub mod grxstsr_host; -#[doc = "GRXSTSP_Host (r) register accessor: an alias for `Reg`"] +#[doc = "GRXSTSP_Host (r) register accessor: OTG_HS status read and pop register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp_host::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsp_host`] +module"] pub type GRXSTSP_HOST = crate::Reg; #[doc = "OTG_HS status read and pop register (host mode)"] pub mod grxstsp_host; -#[doc = "GRXFSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "GRXFSIZ (rw) register accessor: OTG_HS Receive FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxfsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grxfsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxfsiz`] +module"] pub type GRXFSIZ = crate::Reg; #[doc = "OTG_HS Receive FIFO size register"] pub mod grxfsiz; -#[doc = "GNPTXFSIZ_Host (rw) register accessor: an alias for `Reg`"] +#[doc = "GNPTXFSIZ_Host (rw) register accessor: OTG_HS nonperiodic transmit FIFO size register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxfsiz_host::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gnptxfsiz_host::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gnptxfsiz_host`] +module"] pub type GNPTXFSIZ_HOST = crate::Reg; #[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)"] pub mod gnptxfsiz_host; -#[doc = "TX0FSIZ_Peripheral (rw) register accessor: an alias for `Reg`"] +#[doc = "TX0FSIZ_Peripheral (rw) register accessor: Endpoint 0 transmit FIFO size (peripheral mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx0fsiz_peripheral::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx0fsiz_peripheral::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx0fsiz_peripheral`] +module"] pub type TX0FSIZ_PERIPHERAL = crate::Reg; #[doc = "Endpoint 0 transmit FIFO size (peripheral mode)"] pub mod tx0fsiz_peripheral; -#[doc = "GNPTXSTS (r) register accessor: an alias for `Reg`"] +#[doc = "GNPTXSTS (r) register accessor: OTG_HS nonperiodic transmit FIFO/queue status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxsts::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gnptxsts`] +module"] pub type GNPTXSTS = crate::Reg; #[doc = "OTG_HS nonperiodic transmit FIFO/queue status register"] pub mod gnptxsts; -#[doc = "GCCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "GCCFG (rw) register accessor: OTG_HS general core configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gccfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gccfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gccfg`] +module"] pub type GCCFG = crate::Reg; #[doc = "OTG_HS general core configuration register"] pub mod gccfg; -#[doc = "CID (rw) register accessor: an alias for `Reg`"] +#[doc = "CID (rw) register accessor: OTG_HS core ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cid::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cid::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cid`] +module"] pub type CID = crate::Reg; #[doc = "OTG_HS core ID register"] pub mod cid; -#[doc = "VID (r) register accessor: an alias for `Reg`"] +#[doc = "VID (r) register accessor: OTG_HS vendor ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid`] +module"] pub type VID = crate::Reg; #[doc = "OTG_HS vendor ID register"] pub mod vid; -#[doc = "HW_DIRECTION (r) register accessor: an alias for `Reg`"] +#[doc = "HW_DIRECTION (r) register accessor: Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_direction::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_direction`] +module"] pub type HW_DIRECTION = crate::Reg; #[doc = "Direction"] pub mod hw_direction; -#[doc = "HW_CONFIG0 (r) register accessor: an alias for `Reg`"] +#[doc = "HW_CONFIG0 (r) register accessor: Hardware Config 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_config0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_config0`] +module"] pub type HW_CONFIG0 = crate::Reg; #[doc = "Hardware Config 0"] pub mod hw_config0; -#[doc = "HPTXFSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "HPTXFSIZ (rw) register accessor: OTG_HS Host periodic transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxfsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hptxfsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hptxfsiz`] +module"] pub type HPTXFSIZ = crate::Reg; #[doc = "OTG_HS Host periodic transmit FIFO size register"] pub mod hptxfsiz; -#[doc = "DIEPTXF1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF1 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf1`] +module"] pub type DIEPTXF1 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf1; -#[doc = "DIEPTXF2 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF2 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf2`] +module"] pub type DIEPTXF2 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf2; -#[doc = "DIEPTXF3 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF3 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf3`] +module"] pub type DIEPTXF3 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf3; -#[doc = "DIEPTXF4 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF4 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf4`] +module"] pub type DIEPTXF4 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf4; -#[doc = "DIEPTXF5 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF5 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf5`] +module"] pub type DIEPTXF5 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf5; -#[doc = "DIEPTXF6 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF6 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf6`] +module"] pub type DIEPTXF6 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf6; -#[doc = "DIEPTXF7 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF7 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf7`] +module"] pub type DIEPTXF7 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf7; -#[doc = "GRXSTSR_Peripheral (r) register accessor: an alias for `Reg`"] +#[doc = "GRXSTSR_Peripheral (r) register accessor: OTG_HS Receive status debug read register (peripheral mode mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr_peripheral::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsr_peripheral`] +module"] pub type GRXSTSR_PERIPHERAL = crate::Reg; #[doc = "OTG_HS Receive status debug read register (peripheral mode mode)"] pub mod grxstsr_peripheral; -#[doc = "GRXSTSP_Peripheral (r) register accessor: an alias for `Reg`"] +#[doc = "GRXSTSP_Peripheral (r) register accessor: OTG_HS status read and pop register (peripheral mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp_peripheral::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsp_peripheral`] +module"] pub type GRXSTSP_PERIPHERAL = crate::Reg; #[doc = "OTG_HS status read and pop register (peripheral mode)"] pub mod grxstsp_peripheral; diff --git a/crates/bcm2711-lpa/src/usb_otg_global/cid.rs b/crates/bcm2711-lpa/src/usb_otg_global/cid.rs index 5a8ef55..c840ab9 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/cid.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/cid.rs @@ -1,43 +1,11 @@ #[doc = "Register `CID` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CID` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PRODUCT_ID` reader - Product ID field"] -pub type PRODUCT_ID_R = crate::FieldReader; +pub type PRODUCT_ID_R = crate::FieldReader; #[doc = "Field `PRODUCT_ID` writer - Product ID field"] -pub type PRODUCT_ID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CID_SPEC, u32, u32, 32, O>; +pub type PRODUCT_ID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Product ID field"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { PRODUCT_ID_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CID") + .field("product_id", &format_args!("{}", self.product_id().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - Product ID field"] #[inline(always)] #[must_use] - pub fn product_id(&mut self) -> PRODUCT_ID_W<0> { + pub fn product_id(&mut self) -> PRODUCT_ID_W { PRODUCT_ID_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS core ID register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid](index.html) module"] +#[doc = "OTG_HS core ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cid::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cid::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CID_SPEC; impl crate::RegisterSpec for CID_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cid::R](R) reader structure"] -impl crate::Readable for CID_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cid::W](W) writer structure"] +#[doc = "`read()` method returns [`cid::R`](R) reader structure"] +impl crate::Readable for CID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cid::W`](W) writer structure"] impl crate::Writable for CID_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf1.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf1.rs index b79803c..52be8d1 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf1.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf1.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF1_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF1_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF1") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf1](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF1_SPEC; impl crate::RegisterSpec for DIEPTXF1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf1::R](R) reader structure"] -impl crate::Readable for DIEPTXF1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf1::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf1::R`](R) reader structure"] +impl crate::Readable for DIEPTXF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf1::W`](W) writer structure"] impl crate::Writable for DIEPTXF1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf2.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf2.rs index cdf9d1b..ce63253 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf2.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf2.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF2_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF2_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF2") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf2](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF2_SPEC; impl crate::RegisterSpec for DIEPTXF2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf2::R](R) reader structure"] -impl crate::Readable for DIEPTXF2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf2::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf2::R`](R) reader structure"] +impl crate::Readable for DIEPTXF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf2::W`](W) writer structure"] impl crate::Writable for DIEPTXF2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf3.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf3.rs index 8eaba75..18a518c 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf3.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf3.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF3_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF3_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF3") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf3](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF3_SPEC; impl crate::RegisterSpec for DIEPTXF3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf3::R](R) reader structure"] -impl crate::Readable for DIEPTXF3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf3::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf3::R`](R) reader structure"] +impl crate::Readable for DIEPTXF3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf3::W`](W) writer structure"] impl crate::Writable for DIEPTXF3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf4.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf4.rs index 6b30646..9b23f1d 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf4.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf4.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF4_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF4_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF4") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf4](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF4_SPEC; impl crate::RegisterSpec for DIEPTXF4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf4::R](R) reader structure"] -impl crate::Readable for DIEPTXF4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf4::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf4::R`](R) reader structure"] +impl crate::Readable for DIEPTXF4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf4::W`](W) writer structure"] impl crate::Writable for DIEPTXF4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf5.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf5.rs index e2b7d98..03b144c 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf5.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf5.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF5_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF5_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF5") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf5](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF5_SPEC; impl crate::RegisterSpec for DIEPTXF5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf5::R](R) reader structure"] -impl crate::Readable for DIEPTXF5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf5::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf5::R`](R) reader structure"] +impl crate::Readable for DIEPTXF5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf5::W`](W) writer structure"] impl crate::Writable for DIEPTXF5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf6.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf6.rs index da38751..57dcb25 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf6.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf6.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF6_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF6_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF6") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf6](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF6_SPEC; impl crate::RegisterSpec for DIEPTXF6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf6::R](R) reader structure"] -impl crate::Readable for DIEPTXF6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf6::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf6::R`](R) reader structure"] +impl crate::Readable for DIEPTXF6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf6::W`](W) writer structure"] impl crate::Writable for DIEPTXF6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf7.rs b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf7.rs index 811d528..7a99ea4 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/dieptxf7.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/dieptxf7.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF7` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF7` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF7_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF7_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF7") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf7](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF7_SPEC; impl crate::RegisterSpec for DIEPTXF7_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf7::R](R) reader structure"] -impl crate::Readable for DIEPTXF7_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf7::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf7::R`](R) reader structure"] +impl crate::Readable for DIEPTXF7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf7::W`](W) writer structure"] impl crate::Writable for DIEPTXF7_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gahbcfg.rs b/crates/bcm2711-lpa/src/usb_otg_global/gahbcfg.rs index 987d389..a135db6 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/gahbcfg.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/gahbcfg.rs @@ -1,45 +1,13 @@ #[doc = "Register `GAHBCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GAHBCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GINT` reader - Global interrupt mask"] -pub type GINT_R = crate::BitReader; +pub type GINT_R = crate::BitReader; #[doc = "Field `GINT` writer - Global interrupt mask"] -pub type GINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type GINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AXI_BURST` reader - Maximum AXI burst length"] -pub type AXI_BURST_R = crate::FieldReader; +pub type AXI_BURST_R = crate::FieldReader; #[doc = "Maximum AXI burst length\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -59,10 +27,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for BURST_A { + type Ux = u8; +} impl AXI_BURST_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> BURST_A { + pub const fn variant(&self) -> BURST_A { match self.bits { 0 => BURST_A::_4, 1 => BURST_A::_3, @@ -71,68 +42,71 @@ impl AXI_BURST_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_4`"] + #[doc = "`0`"] #[inline(always)] pub fn is_4(&self) -> bool { *self == BURST_A::_4 } - #[doc = "Checks if the value of the field is `_3`"] + #[doc = "`1`"] #[inline(always)] pub fn is_3(&self) -> bool { *self == BURST_A::_3 } - #[doc = "Checks if the value of the field is `_2`"] + #[doc = "`10`"] #[inline(always)] pub fn is_2(&self) -> bool { *self == BURST_A::_2 } - #[doc = "Checks if the value of the field is `_1`"] + #[doc = "`11`"] #[inline(always)] pub fn is_1(&self) -> bool { *self == BURST_A::_1 } } #[doc = "Field `AXI_BURST` writer - Maximum AXI burst length"] -pub type AXI_BURST_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GAHBCFG_SPEC, u8, BURST_A, 2, O>; -impl<'a, const O: u8> AXI_BURST_W<'a, O> { +pub type AXI_BURST_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, BURST_A>; +impl<'a, REG, const O: u8> AXI_BURST_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _4(self) -> &'a mut W { + pub fn _4(self) -> &'a mut crate::W { self.variant(BURST_A::_4) } #[doc = "`1`"] #[inline(always)] - pub fn _3(self) -> &'a mut W { + pub fn _3(self) -> &'a mut crate::W { self.variant(BURST_A::_3) } #[doc = "`10`"] #[inline(always)] - pub fn _2(self) -> &'a mut W { + pub fn _2(self) -> &'a mut crate::W { self.variant(BURST_A::_2) } #[doc = "`11`"] #[inline(always)] - pub fn _1(self) -> &'a mut W { + pub fn _1(self) -> &'a mut crate::W { self.variant(BURST_A::_1) } } #[doc = "Field `AXI_WAIT` reader - Wait for all AXI writes before signaling DMA"] -pub type AXI_WAIT_R = crate::BitReader; +pub type AXI_WAIT_R = crate::BitReader; #[doc = "Field `AXI_WAIT` writer - Wait for all AXI writes before signaling DMA"] -pub type AXI_WAIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type AXI_WAIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMAEN` reader - DMA enable"] -pub type DMAEN_R = crate::BitReader; +pub type DMAEN_R = crate::BitReader; #[doc = "Field `DMAEN` writer - DMA enable"] -pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type DMAEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFELVL` reader - TxFIFO empty level"] -pub type TXFELVL_R = crate::BitReader; +pub type TXFELVL_R = crate::BitReader; #[doc = "Field `TXFELVL` writer - TxFIFO empty level"] -pub type TXFELVL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type TXFELVL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTXFELVL` reader - Periodic TxFIFO empty level"] -pub type PTXFELVL_R = crate::BitReader; +pub type PTXFELVL_R = crate::BitReader; #[doc = "Field `PTXFELVL` writer - Periodic TxFIFO empty level"] -pub type PTXFELVL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type PTXFELVL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Global interrupt mask"] #[inline(always)] @@ -165,62 +139,80 @@ impl R { PTXFELVL_R::new(((self.bits >> 8) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAHBCFG") + .field("gint", &format_args!("{}", self.gint().bit())) + .field("axi_wait", &format_args!("{}", self.axi_wait().bit())) + .field("axi_burst", &format_args!("{}", self.axi_burst().bits())) + .field("dmaen", &format_args!("{}", self.dmaen().bit())) + .field("txfelvl", &format_args!("{}", self.txfelvl().bit())) + .field("ptxfelvl", &format_args!("{}", self.ptxfelvl().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Global interrupt mask"] #[inline(always)] #[must_use] - pub fn gint(&mut self) -> GINT_W<0> { + pub fn gint(&mut self) -> GINT_W { GINT_W::new(self) } #[doc = "Bits 1:2 - Maximum AXI burst length"] #[inline(always)] #[must_use] - pub fn axi_burst(&mut self) -> AXI_BURST_W<1> { + pub fn axi_burst(&mut self) -> AXI_BURST_W { AXI_BURST_W::new(self) } #[doc = "Bit 4 - Wait for all AXI writes before signaling DMA"] #[inline(always)] #[must_use] - pub fn axi_wait(&mut self) -> AXI_WAIT_W<4> { + pub fn axi_wait(&mut self) -> AXI_WAIT_W { AXI_WAIT_W::new(self) } #[doc = "Bit 5 - DMA enable"] #[inline(always)] #[must_use] - pub fn dmaen(&mut self) -> DMAEN_W<5> { + pub fn dmaen(&mut self) -> DMAEN_W { DMAEN_W::new(self) } #[doc = "Bit 7 - TxFIFO empty level"] #[inline(always)] #[must_use] - pub fn txfelvl(&mut self) -> TXFELVL_W<7> { + pub fn txfelvl(&mut self) -> TXFELVL_W { TXFELVL_W::new(self) } #[doc = "Bit 8 - Periodic TxFIFO empty level"] #[inline(always)] #[must_use] - pub fn ptxfelvl(&mut self) -> PTXFELVL_W<8> { + pub fn ptxfelvl(&mut self) -> PTXFELVL_W { PTXFELVL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS AHB configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gahbcfg](index.html) module"] +#[doc = "OTG_HS AHB configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gahbcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gahbcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GAHBCFG_SPEC; impl crate::RegisterSpec for GAHBCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gahbcfg::R](R) reader structure"] -impl crate::Readable for GAHBCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gahbcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`gahbcfg::R`](R) reader structure"] +impl crate::Readable for GAHBCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gahbcfg::W`](W) writer structure"] impl crate::Writable for GAHBCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gccfg.rs b/crates/bcm2711-lpa/src/usb_otg_global/gccfg.rs index 4dbbf5c..6612077 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/gccfg.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/gccfg.rs @@ -1,63 +1,31 @@ #[doc = "Register `GCCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GCCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PWRDWN` reader - Power down"] -pub type PWRDWN_R = crate::BitReader; +pub type PWRDWN_R = crate::BitReader; #[doc = "Field `PWRDWN` writer - Power down"] -pub type PWRDWN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type PWRDWN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2CPADEN` reader - Enable I2C bus connection for the external I2C PHY interface"] -pub type I2CPADEN_R = crate::BitReader; +pub type I2CPADEN_R = crate::BitReader; #[doc = "Field `I2CPADEN` writer - Enable I2C bus connection for the external I2C PHY interface"] -pub type I2CPADEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type I2CPADEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUSASEN` reader - Enable the VBUS sensing device"] -pub type VBUSASEN_R = crate::BitReader; +pub type VBUSASEN_R = crate::BitReader; #[doc = "Field `VBUSASEN` writer - Enable the VBUS sensing device"] -pub type VBUSASEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type VBUSASEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUSBSEN` reader - Enable the VBUS sensing device"] -pub type VBUSBSEN_R = crate::BitReader; +pub type VBUSBSEN_R = crate::BitReader; #[doc = "Field `VBUSBSEN` writer - Enable the VBUS sensing device"] -pub type VBUSBSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type VBUSBSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOFOUTEN` reader - SOF output enable"] -pub type SOFOUTEN_R = crate::BitReader; +pub type SOFOUTEN_R = crate::BitReader; #[doc = "Field `SOFOUTEN` writer - SOF output enable"] -pub type SOFOUTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type SOFOUTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NOVBUSSENS` reader - VBUS sensing disable option"] -pub type NOVBUSSENS_R = crate::BitReader; +pub type NOVBUSSENS_R = crate::BitReader; #[doc = "Field `NOVBUSSENS` writer - VBUS sensing disable option"] -pub type NOVBUSSENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type NOVBUSSENS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 16 - Power down"] #[inline(always)] @@ -90,62 +58,80 @@ impl R { NOVBUSSENS_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCCFG") + .field("pwrdwn", &format_args!("{}", self.pwrdwn().bit())) + .field("i2cpaden", &format_args!("{}", self.i2cpaden().bit())) + .field("vbusasen", &format_args!("{}", self.vbusasen().bit())) + .field("vbusbsen", &format_args!("{}", self.vbusbsen().bit())) + .field("sofouten", &format_args!("{}", self.sofouten().bit())) + .field("novbussens", &format_args!("{}", self.novbussens().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 16 - Power down"] #[inline(always)] #[must_use] - pub fn pwrdwn(&mut self) -> PWRDWN_W<16> { + pub fn pwrdwn(&mut self) -> PWRDWN_W { PWRDWN_W::new(self) } #[doc = "Bit 17 - Enable I2C bus connection for the external I2C PHY interface"] #[inline(always)] #[must_use] - pub fn i2cpaden(&mut self) -> I2CPADEN_W<17> { + pub fn i2cpaden(&mut self) -> I2CPADEN_W { I2CPADEN_W::new(self) } #[doc = "Bit 18 - Enable the VBUS sensing device"] #[inline(always)] #[must_use] - pub fn vbusasen(&mut self) -> VBUSASEN_W<18> { + pub fn vbusasen(&mut self) -> VBUSASEN_W { VBUSASEN_W::new(self) } #[doc = "Bit 19 - Enable the VBUS sensing device"] #[inline(always)] #[must_use] - pub fn vbusbsen(&mut self) -> VBUSBSEN_W<19> { + pub fn vbusbsen(&mut self) -> VBUSBSEN_W { VBUSBSEN_W::new(self) } #[doc = "Bit 20 - SOF output enable"] #[inline(always)] #[must_use] - pub fn sofouten(&mut self) -> SOFOUTEN_W<20> { + pub fn sofouten(&mut self) -> SOFOUTEN_W { SOFOUTEN_W::new(self) } #[doc = "Bit 21 - VBUS sensing disable option"] #[inline(always)] #[must_use] - pub fn novbussens(&mut self) -> NOVBUSSENS_W<21> { + pub fn novbussens(&mut self) -> NOVBUSSENS_W { NOVBUSSENS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS general core configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gccfg](index.html) module"] +#[doc = "OTG_HS general core configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gccfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gccfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GCCFG_SPEC; impl crate::RegisterSpec for GCCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gccfg::R](R) reader structure"] -impl crate::Readable for GCCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gccfg::W](W) writer structure"] +#[doc = "`read()` method returns [`gccfg::R`](R) reader structure"] +impl crate::Readable for GCCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gccfg::W`](W) writer structure"] impl crate::Writable for GCCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gintmsk.rs b/crates/bcm2711-lpa/src/usb_otg_global/gintmsk.rs index d3fdb2d..1a856d7 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/gintmsk.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/gintmsk.rs @@ -1,141 +1,109 @@ #[doc = "Register `GINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MMISM` reader - Mode mismatch interrupt mask"] -pub type MMISM_R = crate::BitReader; +pub type MMISM_R = crate::BitReader; #[doc = "Field `MMISM` writer - Mode mismatch interrupt mask"] -pub type MMISM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type MMISM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OTGINT` reader - OTG interrupt mask"] -pub type OTGINT_R = crate::BitReader; +pub type OTGINT_R = crate::BitReader; #[doc = "Field `OTGINT` writer - OTG interrupt mask"] -pub type OTGINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type OTGINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOFM` reader - Start of frame mask"] -pub type SOFM_R = crate::BitReader; +pub type SOFM_R = crate::BitReader; #[doc = "Field `SOFM` writer - Start of frame mask"] -pub type SOFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type SOFM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFLVLM` reader - Receive FIFO nonempty mask"] -pub type RXFLVLM_R = crate::BitReader; +pub type RXFLVLM_R = crate::BitReader; #[doc = "Field `RXFLVLM` writer - Receive FIFO nonempty mask"] -pub type RXFLVLM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type RXFLVLM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NPTXFEM` reader - Nonperiodic TxFIFO empty mask"] -pub type NPTXFEM_R = crate::BitReader; +pub type NPTXFEM_R = crate::BitReader; #[doc = "Field `NPTXFEM` writer - Nonperiodic TxFIFO empty mask"] -pub type NPTXFEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type NPTXFEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GINAKEFFM` reader - Global nonperiodic IN NAK effective mask"] -pub type GINAKEFFM_R = crate::BitReader; +pub type GINAKEFFM_R = crate::BitReader; #[doc = "Field `GINAKEFFM` writer - Global nonperiodic IN NAK effective mask"] -pub type GINAKEFFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type GINAKEFFM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GONAKEFFM` reader - Global OUT NAK effective mask"] -pub type GONAKEFFM_R = crate::BitReader; +pub type GONAKEFFM_R = crate::BitReader; #[doc = "Field `GONAKEFFM` writer - Global OUT NAK effective mask"] -pub type GONAKEFFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type GONAKEFFM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ESUSPM` reader - Early suspend mask"] -pub type ESUSPM_R = crate::BitReader; +pub type ESUSPM_R = crate::BitReader; #[doc = "Field `ESUSPM` writer - Early suspend mask"] -pub type ESUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type ESUSPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBSUSPM` reader - USB suspend mask"] -pub type USBSUSPM_R = crate::BitReader; +pub type USBSUSPM_R = crate::BitReader; #[doc = "Field `USBSUSPM` writer - USB suspend mask"] -pub type USBSUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type USBSUSPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBRST` reader - USB reset mask"] -pub type USBRST_R = crate::BitReader; +pub type USBRST_R = crate::BitReader; #[doc = "Field `USBRST` writer - USB reset mask"] -pub type USBRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type USBRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENUMDNEM` reader - Enumeration done mask"] -pub type ENUMDNEM_R = crate::BitReader; +pub type ENUMDNEM_R = crate::BitReader; #[doc = "Field `ENUMDNEM` writer - Enumeration done mask"] -pub type ENUMDNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type ENUMDNEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISOODRPM` reader - Isochronous OUT packet dropped interrupt mask"] -pub type ISOODRPM_R = crate::BitReader; +pub type ISOODRPM_R = crate::BitReader; #[doc = "Field `ISOODRPM` writer - Isochronous OUT packet dropped interrupt mask"] -pub type ISOODRPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type ISOODRPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOPFM` reader - End of periodic frame interrupt mask"] -pub type EOPFM_R = crate::BitReader; +pub type EOPFM_R = crate::BitReader; #[doc = "Field `EOPFM` writer - End of periodic frame interrupt mask"] -pub type EOPFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type EOPFM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPMISM` reader - Endpoint mismatch interrupt mask"] -pub type EPMISM_R = crate::BitReader; +pub type EPMISM_R = crate::BitReader; #[doc = "Field `EPMISM` writer - Endpoint mismatch interrupt mask"] -pub type EPMISM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type EPMISM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IEPINT` reader - IN endpoints interrupt mask"] -pub type IEPINT_R = crate::BitReader; +pub type IEPINT_R = crate::BitReader; #[doc = "Field `IEPINT` writer - IN endpoints interrupt mask"] -pub type IEPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type IEPINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEPINT` reader - OUT endpoints interrupt mask"] -pub type OEPINT_R = crate::BitReader; +pub type OEPINT_R = crate::BitReader; #[doc = "Field `OEPINT` writer - OUT endpoints interrupt mask"] -pub type OEPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type OEPINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IISOIXFRM` reader - Incomplete isochronous IN transfer mask"] -pub type IISOIXFRM_R = crate::BitReader; +pub type IISOIXFRM_R = crate::BitReader; #[doc = "Field `IISOIXFRM` writer - Incomplete isochronous IN transfer mask"] -pub type IISOIXFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type IISOIXFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PXFRM_IISOOXFRM` reader - Incomplete periodic transfer mask"] -pub type PXFRM_IISOOXFRM_R = crate::BitReader; +pub type PXFRM_IISOOXFRM_R = crate::BitReader; #[doc = "Field `PXFRM_IISOOXFRM` writer - Incomplete periodic transfer mask"] -pub type PXFRM_IISOOXFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type PXFRM_IISOOXFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSUSPM` reader - Data fetch suspended mask"] -pub type FSUSPM_R = crate::BitReader; +pub type FSUSPM_R = crate::BitReader; #[doc = "Field `FSUSPM` writer - Data fetch suspended mask"] -pub type FSUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type FSUSPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRTIM` reader - Host port interrupt mask"] -pub type PRTIM_R = crate::BitReader; +pub type PRTIM_R = crate::BitReader; #[doc = "Field `HCIM` reader - Host channels interrupt mask"] -pub type HCIM_R = crate::BitReader; +pub type HCIM_R = crate::BitReader; #[doc = "Field `HCIM` writer - Host channels interrupt mask"] -pub type HCIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type HCIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTXFEM` reader - Periodic TxFIFO empty mask"] -pub type PTXFEM_R = crate::BitReader; +pub type PTXFEM_R = crate::BitReader; #[doc = "Field `PTXFEM` writer - Periodic TxFIFO empty mask"] -pub type PTXFEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type PTXFEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CIDSCHGM` reader - Connector ID status change mask"] -pub type CIDSCHGM_R = crate::BitReader; +pub type CIDSCHGM_R = crate::BitReader; #[doc = "Field `CIDSCHGM` writer - Connector ID status change mask"] -pub type CIDSCHGM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type CIDSCHGM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISCINT` reader - Disconnect detected interrupt mask"] -pub type DISCINT_R = crate::BitReader; +pub type DISCINT_R = crate::BitReader; #[doc = "Field `DISCINT` writer - Disconnect detected interrupt mask"] -pub type DISCINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type DISCINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRQIM` reader - Session request/new session detected interrupt mask"] -pub type SRQIM_R = crate::BitReader; +pub type SRQIM_R = crate::BitReader; #[doc = "Field `SRQIM` writer - Session request/new session detected interrupt mask"] -pub type SRQIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type SRQIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WUIM` reader - Resume/remote wakeup detected interrupt mask"] -pub type WUIM_R = crate::BitReader; +pub type WUIM_R = crate::BitReader; #[doc = "Field `WUIM` writer - Resume/remote wakeup detected interrupt mask"] -pub type WUIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type WUIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - Mode mismatch interrupt mask"] #[inline(always)] @@ -268,176 +236,217 @@ impl R { WUIM_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GINTMSK") + .field("mmism", &format_args!("{}", self.mmism().bit())) + .field("otgint", &format_args!("{}", self.otgint().bit())) + .field("sofm", &format_args!("{}", self.sofm().bit())) + .field("rxflvlm", &format_args!("{}", self.rxflvlm().bit())) + .field("nptxfem", &format_args!("{}", self.nptxfem().bit())) + .field("ginakeffm", &format_args!("{}", self.ginakeffm().bit())) + .field("gonakeffm", &format_args!("{}", self.gonakeffm().bit())) + .field("esuspm", &format_args!("{}", self.esuspm().bit())) + .field("usbsuspm", &format_args!("{}", self.usbsuspm().bit())) + .field("usbrst", &format_args!("{}", self.usbrst().bit())) + .field("enumdnem", &format_args!("{}", self.enumdnem().bit())) + .field("isoodrpm", &format_args!("{}", self.isoodrpm().bit())) + .field("eopfm", &format_args!("{}", self.eopfm().bit())) + .field("epmism", &format_args!("{}", self.epmism().bit())) + .field("iepint", &format_args!("{}", self.iepint().bit())) + .field("oepint", &format_args!("{}", self.oepint().bit())) + .field("iisoixfrm", &format_args!("{}", self.iisoixfrm().bit())) + .field( + "pxfrm_iisooxfrm", + &format_args!("{}", self.pxfrm_iisooxfrm().bit()), + ) + .field("fsuspm", &format_args!("{}", self.fsuspm().bit())) + .field("prtim", &format_args!("{}", self.prtim().bit())) + .field("hcim", &format_args!("{}", self.hcim().bit())) + .field("ptxfem", &format_args!("{}", self.ptxfem().bit())) + .field("cidschgm", &format_args!("{}", self.cidschgm().bit())) + .field("discint", &format_args!("{}", self.discint().bit())) + .field("srqim", &format_args!("{}", self.srqim().bit())) + .field("wuim", &format_args!("{}", self.wuim().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Mode mismatch interrupt mask"] #[inline(always)] #[must_use] - pub fn mmism(&mut self) -> MMISM_W<1> { + pub fn mmism(&mut self) -> MMISM_W { MMISM_W::new(self) } #[doc = "Bit 2 - OTG interrupt mask"] #[inline(always)] #[must_use] - pub fn otgint(&mut self) -> OTGINT_W<2> { + pub fn otgint(&mut self) -> OTGINT_W { OTGINT_W::new(self) } #[doc = "Bit 3 - Start of frame mask"] #[inline(always)] #[must_use] - pub fn sofm(&mut self) -> SOFM_W<3> { + pub fn sofm(&mut self) -> SOFM_W { SOFM_W::new(self) } #[doc = "Bit 4 - Receive FIFO nonempty mask"] #[inline(always)] #[must_use] - pub fn rxflvlm(&mut self) -> RXFLVLM_W<4> { + pub fn rxflvlm(&mut self) -> RXFLVLM_W { RXFLVLM_W::new(self) } #[doc = "Bit 5 - Nonperiodic TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn nptxfem(&mut self) -> NPTXFEM_W<5> { + pub fn nptxfem(&mut self) -> NPTXFEM_W { NPTXFEM_W::new(self) } #[doc = "Bit 6 - Global nonperiodic IN NAK effective mask"] #[inline(always)] #[must_use] - pub fn ginakeffm(&mut self) -> GINAKEFFM_W<6> { + pub fn ginakeffm(&mut self) -> GINAKEFFM_W { GINAKEFFM_W::new(self) } #[doc = "Bit 7 - Global OUT NAK effective mask"] #[inline(always)] #[must_use] - pub fn gonakeffm(&mut self) -> GONAKEFFM_W<7> { + pub fn gonakeffm(&mut self) -> GONAKEFFM_W { GONAKEFFM_W::new(self) } #[doc = "Bit 10 - Early suspend mask"] #[inline(always)] #[must_use] - pub fn esuspm(&mut self) -> ESUSPM_W<10> { + pub fn esuspm(&mut self) -> ESUSPM_W { ESUSPM_W::new(self) } #[doc = "Bit 11 - USB suspend mask"] #[inline(always)] #[must_use] - pub fn usbsuspm(&mut self) -> USBSUSPM_W<11> { + pub fn usbsuspm(&mut self) -> USBSUSPM_W { USBSUSPM_W::new(self) } #[doc = "Bit 12 - USB reset mask"] #[inline(always)] #[must_use] - pub fn usbrst(&mut self) -> USBRST_W<12> { + pub fn usbrst(&mut self) -> USBRST_W { USBRST_W::new(self) } #[doc = "Bit 13 - Enumeration done mask"] #[inline(always)] #[must_use] - pub fn enumdnem(&mut self) -> ENUMDNEM_W<13> { + pub fn enumdnem(&mut self) -> ENUMDNEM_W { ENUMDNEM_W::new(self) } #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt mask"] #[inline(always)] #[must_use] - pub fn isoodrpm(&mut self) -> ISOODRPM_W<14> { + pub fn isoodrpm(&mut self) -> ISOODRPM_W { ISOODRPM_W::new(self) } #[doc = "Bit 15 - End of periodic frame interrupt mask"] #[inline(always)] #[must_use] - pub fn eopfm(&mut self) -> EOPFM_W<15> { + pub fn eopfm(&mut self) -> EOPFM_W { EOPFM_W::new(self) } #[doc = "Bit 17 - Endpoint mismatch interrupt mask"] #[inline(always)] #[must_use] - pub fn epmism(&mut self) -> EPMISM_W<17> { + pub fn epmism(&mut self) -> EPMISM_W { EPMISM_W::new(self) } #[doc = "Bit 18 - IN endpoints interrupt mask"] #[inline(always)] #[must_use] - pub fn iepint(&mut self) -> IEPINT_W<18> { + pub fn iepint(&mut self) -> IEPINT_W { IEPINT_W::new(self) } #[doc = "Bit 19 - OUT endpoints interrupt mask"] #[inline(always)] #[must_use] - pub fn oepint(&mut self) -> OEPINT_W<19> { + pub fn oepint(&mut self) -> OEPINT_W { OEPINT_W::new(self) } #[doc = "Bit 20 - Incomplete isochronous IN transfer mask"] #[inline(always)] #[must_use] - pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<20> { + pub fn iisoixfrm(&mut self) -> IISOIXFRM_W { IISOIXFRM_W::new(self) } #[doc = "Bit 21 - Incomplete periodic transfer mask"] #[inline(always)] #[must_use] - pub fn pxfrm_iisooxfrm(&mut self) -> PXFRM_IISOOXFRM_W<21> { + pub fn pxfrm_iisooxfrm(&mut self) -> PXFRM_IISOOXFRM_W { PXFRM_IISOOXFRM_W::new(self) } #[doc = "Bit 22 - Data fetch suspended mask"] #[inline(always)] #[must_use] - pub fn fsuspm(&mut self) -> FSUSPM_W<22> { + pub fn fsuspm(&mut self) -> FSUSPM_W { FSUSPM_W::new(self) } #[doc = "Bit 25 - Host channels interrupt mask"] #[inline(always)] #[must_use] - pub fn hcim(&mut self) -> HCIM_W<25> { + pub fn hcim(&mut self) -> HCIM_W { HCIM_W::new(self) } #[doc = "Bit 26 - Periodic TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn ptxfem(&mut self) -> PTXFEM_W<26> { + pub fn ptxfem(&mut self) -> PTXFEM_W { PTXFEM_W::new(self) } #[doc = "Bit 28 - Connector ID status change mask"] #[inline(always)] #[must_use] - pub fn cidschgm(&mut self) -> CIDSCHGM_W<28> { + pub fn cidschgm(&mut self) -> CIDSCHGM_W { CIDSCHGM_W::new(self) } #[doc = "Bit 29 - Disconnect detected interrupt mask"] #[inline(always)] #[must_use] - pub fn discint(&mut self) -> DISCINT_W<29> { + pub fn discint(&mut self) -> DISCINT_W { DISCINT_W::new(self) } #[doc = "Bit 30 - Session request/new session detected interrupt mask"] #[inline(always)] #[must_use] - pub fn srqim(&mut self) -> SRQIM_W<30> { + pub fn srqim(&mut self) -> SRQIM_W { SRQIM_W::new(self) } #[doc = "Bit 31 - Resume/remote wakeup detected interrupt mask"] #[inline(always)] #[must_use] - pub fn wuim(&mut self) -> WUIM_W<31> { + pub fn wuim(&mut self) -> WUIM_W { WUIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintmsk](index.html) module"] +#[doc = "OTG_HS interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GINTMSK_SPEC; impl crate::RegisterSpec for GINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gintmsk::R](R) reader structure"] -impl crate::Readable for GINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`gintmsk::R`](R) reader structure"] +impl crate::Readable for GINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gintmsk::W`](W) writer structure"] impl crate::Writable for GINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gintsts.rs b/crates/bcm2711-lpa/src/usb_otg_global/gintsts.rs index 4dd3aa9..513d718 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/gintsts.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/gintsts.rs @@ -1,121 +1,89 @@ #[doc = "Register `GINTSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GINTSTS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMOD` reader - Current mode of operation"] -pub type CMOD_R = crate::BitReader; +pub type CMOD_R = crate::BitReader; #[doc = "Field `MMIS` reader - Mode mismatch interrupt"] -pub type MMIS_R = crate::BitReader; +pub type MMIS_R = crate::BitReader; #[doc = "Field `MMIS` writer - Mode mismatch interrupt"] -pub type MMIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type MMIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OTGINT` reader - OTG interrupt"] -pub type OTGINT_R = crate::BitReader; +pub type OTGINT_R = crate::BitReader; #[doc = "Field `SOF` reader - Start of frame"] -pub type SOF_R = crate::BitReader; +pub type SOF_R = crate::BitReader; #[doc = "Field `SOF` writer - Start of frame"] -pub type SOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type SOF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFLVL` reader - RxFIFO nonempty"] -pub type RXFLVL_R = crate::BitReader; +pub type RXFLVL_R = crate::BitReader; #[doc = "Field `NPTXFE` reader - Nonperiodic TxFIFO empty"] -pub type NPTXFE_R = crate::BitReader; +pub type NPTXFE_R = crate::BitReader; #[doc = "Field `GINAKEFF` reader - Global IN nonperiodic NAK effective"] -pub type GINAKEFF_R = crate::BitReader; +pub type GINAKEFF_R = crate::BitReader; #[doc = "Field `BOUTNAKEFF` reader - Global OUT NAK effective"] -pub type BOUTNAKEFF_R = crate::BitReader; +pub type BOUTNAKEFF_R = crate::BitReader; #[doc = "Field `ESUSP` reader - Early suspend"] -pub type ESUSP_R = crate::BitReader; +pub type ESUSP_R = crate::BitReader; #[doc = "Field `ESUSP` writer - Early suspend"] -pub type ESUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type ESUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBSUSP` reader - USB suspend"] -pub type USBSUSP_R = crate::BitReader; +pub type USBSUSP_R = crate::BitReader; #[doc = "Field `USBSUSP` writer - USB suspend"] -pub type USBSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type USBSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBRST` reader - USB reset"] -pub type USBRST_R = crate::BitReader; +pub type USBRST_R = crate::BitReader; #[doc = "Field `USBRST` writer - USB reset"] -pub type USBRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type USBRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENUMDNE` reader - Enumeration done"] -pub type ENUMDNE_R = crate::BitReader; +pub type ENUMDNE_R = crate::BitReader; #[doc = "Field `ENUMDNE` writer - Enumeration done"] -pub type ENUMDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type ENUMDNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISOODRP` reader - Isochronous OUT packet dropped interrupt"] -pub type ISOODRP_R = crate::BitReader; +pub type ISOODRP_R = crate::BitReader; #[doc = "Field `ISOODRP` writer - Isochronous OUT packet dropped interrupt"] -pub type ISOODRP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type ISOODRP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOPF` reader - End of periodic frame interrupt"] -pub type EOPF_R = crate::BitReader; +pub type EOPF_R = crate::BitReader; #[doc = "Field `EOPF` writer - End of periodic frame interrupt"] -pub type EOPF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type EOPF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IEPINT` reader - IN endpoint interrupt"] -pub type IEPINT_R = crate::BitReader; +pub type IEPINT_R = crate::BitReader; #[doc = "Field `OEPINT` reader - OUT endpoint interrupt"] -pub type OEPINT_R = crate::BitReader; +pub type OEPINT_R = crate::BitReader; #[doc = "Field `IISOIXFR` reader - Incomplete isochronous IN transfer"] -pub type IISOIXFR_R = crate::BitReader; +pub type IISOIXFR_R = crate::BitReader; #[doc = "Field `IISOIXFR` writer - Incomplete isochronous IN transfer"] -pub type IISOIXFR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type IISOIXFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PXFR_INCOMPISOOUT` reader - Incomplete periodic transfer"] -pub type PXFR_INCOMPISOOUT_R = crate::BitReader; +pub type PXFR_INCOMPISOOUT_R = crate::BitReader; #[doc = "Field `PXFR_INCOMPISOOUT` writer - Incomplete periodic transfer"] -pub type PXFR_INCOMPISOOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type PXFR_INCOMPISOOUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATAFSUSP` reader - Data fetch suspended"] -pub type DATAFSUSP_R = crate::BitReader; +pub type DATAFSUSP_R = crate::BitReader; #[doc = "Field `DATAFSUSP` writer - Data fetch suspended"] -pub type DATAFSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type DATAFSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HPRTINT` reader - Host port interrupt"] -pub type HPRTINT_R = crate::BitReader; +pub type HPRTINT_R = crate::BitReader; #[doc = "Field `HCINT` reader - Host channels interrupt"] -pub type HCINT_R = crate::BitReader; +pub type HCINT_R = crate::BitReader; #[doc = "Field `PTXFE` reader - Periodic TxFIFO empty"] -pub type PTXFE_R = crate::BitReader; +pub type PTXFE_R = crate::BitReader; #[doc = "Field `CIDSCHG` reader - Connector ID status change"] -pub type CIDSCHG_R = crate::BitReader; +pub type CIDSCHG_R = crate::BitReader; #[doc = "Field `CIDSCHG` writer - Connector ID status change"] -pub type CIDSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type CIDSCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISCINT` reader - Disconnect detected interrupt"] -pub type DISCINT_R = crate::BitReader; +pub type DISCINT_R = crate::BitReader; #[doc = "Field `DISCINT` writer - Disconnect detected interrupt"] -pub type DISCINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type DISCINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRQINT` reader - Session request/new session detected interrupt"] -pub type SRQINT_R = crate::BitReader; +pub type SRQINT_R = crate::BitReader; #[doc = "Field `SRQINT` writer - Session request/new session detected interrupt"] -pub type SRQINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type SRQINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WKUINT` reader - Resume/remote wakeup detected interrupt"] -pub type WKUINT_R = crate::BitReader; +pub type WKUINT_R = crate::BitReader; #[doc = "Field `WKUINT` writer - Resume/remote wakeup detected interrupt"] -pub type WKUINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type WKUINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Current mode of operation"] #[inline(always)] @@ -248,116 +216,157 @@ impl R { WKUINT_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GINTSTS") + .field("cmod", &format_args!("{}", self.cmod().bit())) + .field("mmis", &format_args!("{}", self.mmis().bit())) + .field("otgint", &format_args!("{}", self.otgint().bit())) + .field("sof", &format_args!("{}", self.sof().bit())) + .field("rxflvl", &format_args!("{}", self.rxflvl().bit())) + .field("nptxfe", &format_args!("{}", self.nptxfe().bit())) + .field("ginakeff", &format_args!("{}", self.ginakeff().bit())) + .field("boutnakeff", &format_args!("{}", self.boutnakeff().bit())) + .field("esusp", &format_args!("{}", self.esusp().bit())) + .field("usbsusp", &format_args!("{}", self.usbsusp().bit())) + .field("usbrst", &format_args!("{}", self.usbrst().bit())) + .field("enumdne", &format_args!("{}", self.enumdne().bit())) + .field("isoodrp", &format_args!("{}", self.isoodrp().bit())) + .field("eopf", &format_args!("{}", self.eopf().bit())) + .field("iepint", &format_args!("{}", self.iepint().bit())) + .field("oepint", &format_args!("{}", self.oepint().bit())) + .field("iisoixfr", &format_args!("{}", self.iisoixfr().bit())) + .field( + "pxfr_incompisoout", + &format_args!("{}", self.pxfr_incompisoout().bit()), + ) + .field("datafsusp", &format_args!("{}", self.datafsusp().bit())) + .field("hprtint", &format_args!("{}", self.hprtint().bit())) + .field("hcint", &format_args!("{}", self.hcint().bit())) + .field("ptxfe", &format_args!("{}", self.ptxfe().bit())) + .field("cidschg", &format_args!("{}", self.cidschg().bit())) + .field("discint", &format_args!("{}", self.discint().bit())) + .field("srqint", &format_args!("{}", self.srqint().bit())) + .field("wkuint", &format_args!("{}", self.wkuint().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Mode mismatch interrupt"] #[inline(always)] #[must_use] - pub fn mmis(&mut self) -> MMIS_W<1> { + pub fn mmis(&mut self) -> MMIS_W { MMIS_W::new(self) } #[doc = "Bit 3 - Start of frame"] #[inline(always)] #[must_use] - pub fn sof(&mut self) -> SOF_W<3> { + pub fn sof(&mut self) -> SOF_W { SOF_W::new(self) } #[doc = "Bit 10 - Early suspend"] #[inline(always)] #[must_use] - pub fn esusp(&mut self) -> ESUSP_W<10> { + pub fn esusp(&mut self) -> ESUSP_W { ESUSP_W::new(self) } #[doc = "Bit 11 - USB suspend"] #[inline(always)] #[must_use] - pub fn usbsusp(&mut self) -> USBSUSP_W<11> { + pub fn usbsusp(&mut self) -> USBSUSP_W { USBSUSP_W::new(self) } #[doc = "Bit 12 - USB reset"] #[inline(always)] #[must_use] - pub fn usbrst(&mut self) -> USBRST_W<12> { + pub fn usbrst(&mut self) -> USBRST_W { USBRST_W::new(self) } #[doc = "Bit 13 - Enumeration done"] #[inline(always)] #[must_use] - pub fn enumdne(&mut self) -> ENUMDNE_W<13> { + pub fn enumdne(&mut self) -> ENUMDNE_W { ENUMDNE_W::new(self) } #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt"] #[inline(always)] #[must_use] - pub fn isoodrp(&mut self) -> ISOODRP_W<14> { + pub fn isoodrp(&mut self) -> ISOODRP_W { ISOODRP_W::new(self) } #[doc = "Bit 15 - End of periodic frame interrupt"] #[inline(always)] #[must_use] - pub fn eopf(&mut self) -> EOPF_W<15> { + pub fn eopf(&mut self) -> EOPF_W { EOPF_W::new(self) } #[doc = "Bit 20 - Incomplete isochronous IN transfer"] #[inline(always)] #[must_use] - pub fn iisoixfr(&mut self) -> IISOIXFR_W<20> { + pub fn iisoixfr(&mut self) -> IISOIXFR_W { IISOIXFR_W::new(self) } #[doc = "Bit 21 - Incomplete periodic transfer"] #[inline(always)] #[must_use] - pub fn pxfr_incompisoout(&mut self) -> PXFR_INCOMPISOOUT_W<21> { + pub fn pxfr_incompisoout(&mut self) -> PXFR_INCOMPISOOUT_W { PXFR_INCOMPISOOUT_W::new(self) } #[doc = "Bit 22 - Data fetch suspended"] #[inline(always)] #[must_use] - pub fn datafsusp(&mut self) -> DATAFSUSP_W<22> { + pub fn datafsusp(&mut self) -> DATAFSUSP_W { DATAFSUSP_W::new(self) } #[doc = "Bit 28 - Connector ID status change"] #[inline(always)] #[must_use] - pub fn cidschg(&mut self) -> CIDSCHG_W<28> { + pub fn cidschg(&mut self) -> CIDSCHG_W { CIDSCHG_W::new(self) } #[doc = "Bit 29 - Disconnect detected interrupt"] #[inline(always)] #[must_use] - pub fn discint(&mut self) -> DISCINT_W<29> { + pub fn discint(&mut self) -> DISCINT_W { DISCINT_W::new(self) } #[doc = "Bit 30 - Session request/new session detected interrupt"] #[inline(always)] #[must_use] - pub fn srqint(&mut self) -> SRQINT_W<30> { + pub fn srqint(&mut self) -> SRQINT_W { SRQINT_W::new(self) } #[doc = "Bit 31 - Resume/remote wakeup detected interrupt"] #[inline(always)] #[must_use] - pub fn wkuint(&mut self) -> WKUINT_W<31> { + pub fn wkuint(&mut self) -> WKUINT_W { WKUINT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS core interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintsts](index.html) module"] +#[doc = "OTG_HS core interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gintsts::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gintsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GINTSTS_SPEC; impl crate::RegisterSpec for GINTSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gintsts::R](R) reader structure"] -impl crate::Readable for GINTSTS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gintsts::W](W) writer structure"] +#[doc = "`read()` method returns [`gintsts::R`](R) reader structure"] +impl crate::Readable for GINTSTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gintsts::W`](W) writer structure"] impl crate::Writable for GINTSTS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gnptxfsiz_host.rs b/crates/bcm2711-lpa/src/usb_otg_global/gnptxfsiz_host.rs index 89a5540..b2b7b4e 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/gnptxfsiz_host.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/gnptxfsiz_host.rs @@ -1,49 +1,15 @@ #[doc = "Register `GNPTXFSIZ_Host` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GNPTXFSIZ_Host` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NPTXFSA` reader - Nonperiodic transmit RAM start address"] -pub type NPTXFSA_R = crate::FieldReader; +pub type NPTXFSA_R = crate::FieldReader; #[doc = "Field `NPTXFSA` writer - Nonperiodic transmit RAM start address"] -pub type NPTXFSA_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GNPTXFSIZ_HOST_SPEC, u16, u16, 16, O>; +pub type NPTXFSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `NPTXFD` reader - Nonperiodic TxFIFO depth"] -pub type NPTXFD_R = crate::FieldReader; +pub type NPTXFD_R = crate::FieldReader; #[doc = "Field `NPTXFD` writer - Nonperiodic TxFIFO depth"] -pub type NPTXFD_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GNPTXFSIZ_HOST_SPEC, u16, u16, 16, O>; +pub type NPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Nonperiodic transmit RAM start address"] #[inline(always)] @@ -56,38 +22,52 @@ impl R { NPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GNPTXFSIZ_Host") + .field("nptxfsa", &format_args!("{}", self.nptxfsa().bits())) + .field("nptxfd", &format_args!("{}", self.nptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Nonperiodic transmit RAM start address"] #[inline(always)] #[must_use] - pub fn nptxfsa(&mut self) -> NPTXFSA_W<0> { + pub fn nptxfsa(&mut self) -> NPTXFSA_W { NPTXFSA_W::new(self) } #[doc = "Bits 16:31 - Nonperiodic TxFIFO depth"] #[inline(always)] #[must_use] - pub fn nptxfd(&mut self) -> NPTXFD_W<16> { + pub fn nptxfd(&mut self) -> NPTXFD_W { NPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxfsiz_host](index.html) module"] +#[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxfsiz_host::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gnptxfsiz_host::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GNPTXFSIZ_HOST_SPEC; impl crate::RegisterSpec for GNPTXFSIZ_HOST_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gnptxfsiz_host::R](R) reader structure"] -impl crate::Readable for GNPTXFSIZ_HOST_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gnptxfsiz_host::W](W) writer structure"] +#[doc = "`read()` method returns [`gnptxfsiz_host::R`](R) reader structure"] +impl crate::Readable for GNPTXFSIZ_HOST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gnptxfsiz_host::W`](W) writer structure"] impl crate::Writable for GNPTXFSIZ_HOST_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gnptxsts.rs b/crates/bcm2711-lpa/src/usb_otg_global/gnptxsts.rs index 65ffd12..2b32a6f 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/gnptxsts.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/gnptxsts.rs @@ -1,24 +1,11 @@ #[doc = "Register `GNPTXSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NPTXFSAV` reader - Nonperiodic TxFIFO space available"] -pub type NPTXFSAV_R = crate::FieldReader; +pub type NPTXFSAV_R = crate::FieldReader; #[doc = "Field `NPTQXSAV` reader - Nonperiodic transmit request queue space available"] -pub type NPTQXSAV_R = crate::FieldReader; +pub type NPTQXSAV_R = crate::FieldReader; #[doc = "Field `NPTXQTOP` reader - Top of the nonperiodic transmit request queue"] -pub type NPTXQTOP_R = crate::FieldReader; +pub type NPTXQTOP_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - Nonperiodic TxFIFO space available"] #[inline(always)] @@ -36,15 +23,27 @@ impl R { NPTXQTOP_R::new(((self.bits >> 24) & 0x7f) as u8) } } -#[doc = "OTG_HS nonperiodic transmit FIFO/queue status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxsts](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GNPTXSTS") + .field("nptxfsav", &format_args!("{}", self.nptxfsav().bits())) + .field("nptqxsav", &format_args!("{}", self.nptqxsav().bits())) + .field("nptxqtop", &format_args!("{}", self.nptxqtop().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS nonperiodic transmit FIFO/queue status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxsts::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GNPTXSTS_SPEC; impl crate::RegisterSpec for GNPTXSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gnptxsts::R](R) reader structure"] -impl crate::Readable for GNPTXSTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gnptxsts::R`](R) reader structure"] +impl crate::Readable for GNPTXSTS_SPEC {} #[doc = "`reset()` method sets GNPTXSTS to value 0x0008_0200"] impl crate::Resettable for GNPTXSTS_SPEC { const RESET_VALUE: Self::Ux = 0x0008_0200; diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gotgctl.rs b/crates/bcm2711-lpa/src/usb_otg_global/gotgctl.rs index 6576636..36b3f21 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/gotgctl.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/gotgctl.rs @@ -1,67 +1,35 @@ #[doc = "Register `GOTGCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GOTGCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SRQSCS` reader - Session request success"] -pub type SRQSCS_R = crate::BitReader; +pub type SRQSCS_R = crate::BitReader; #[doc = "Field `SRQ` reader - Session request"] -pub type SRQ_R = crate::BitReader; +pub type SRQ_R = crate::BitReader; #[doc = "Field `SRQ` writer - Session request"] -pub type SRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +pub type SRQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HNGSCS` reader - Host negotiation success"] -pub type HNGSCS_R = crate::BitReader; +pub type HNGSCS_R = crate::BitReader; #[doc = "Field `HNPRQ` reader - HNP request"] -pub type HNPRQ_R = crate::BitReader; +pub type HNPRQ_R = crate::BitReader; #[doc = "Field `HNPRQ` writer - HNP request"] -pub type HNPRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +pub type HNPRQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HSHNPEN` reader - Host set HNP enable"] -pub type HSHNPEN_R = crate::BitReader; +pub type HSHNPEN_R = crate::BitReader; #[doc = "Field `HSHNPEN` writer - Host set HNP enable"] -pub type HSHNPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +pub type HSHNPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DHNPEN` reader - Device HNP enabled"] -pub type DHNPEN_R = crate::BitReader; +pub type DHNPEN_R = crate::BitReader; #[doc = "Field `DHNPEN` writer - Device HNP enabled"] -pub type DHNPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +pub type DHNPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CIDSTS` reader - Connector ID status"] -pub type CIDSTS_R = crate::BitReader; +pub type CIDSTS_R = crate::BitReader; #[doc = "Field `DBCT` reader - Long/short debounce time"] -pub type DBCT_R = crate::BitReader; +pub type DBCT_R = crate::BitReader; #[doc = "Field `ASVLD` reader - A-session valid"] -pub type ASVLD_R = crate::BitReader; +pub type ASVLD_R = crate::BitReader; #[doc = "Field `BSVLD` reader - B-session valid"] -pub type BSVLD_R = crate::BitReader; +pub type BSVLD_R = crate::BitReader; impl R { #[doc = "Bit 0 - Session request success"] #[inline(always)] @@ -114,50 +82,72 @@ impl R { BSVLD_R::new(((self.bits >> 19) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GOTGCTL") + .field("srqscs", &format_args!("{}", self.srqscs().bit())) + .field("srq", &format_args!("{}", self.srq().bit())) + .field("hngscs", &format_args!("{}", self.hngscs().bit())) + .field("hnprq", &format_args!("{}", self.hnprq().bit())) + .field("hshnpen", &format_args!("{}", self.hshnpen().bit())) + .field("dhnpen", &format_args!("{}", self.dhnpen().bit())) + .field("cidsts", &format_args!("{}", self.cidsts().bit())) + .field("dbct", &format_args!("{}", self.dbct().bit())) + .field("asvld", &format_args!("{}", self.asvld().bit())) + .field("bsvld", &format_args!("{}", self.bsvld().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Session request"] #[inline(always)] #[must_use] - pub fn srq(&mut self) -> SRQ_W<1> { + pub fn srq(&mut self) -> SRQ_W { SRQ_W::new(self) } #[doc = "Bit 9 - HNP request"] #[inline(always)] #[must_use] - pub fn hnprq(&mut self) -> HNPRQ_W<9> { + pub fn hnprq(&mut self) -> HNPRQ_W { HNPRQ_W::new(self) } #[doc = "Bit 10 - Host set HNP enable"] #[inline(always)] #[must_use] - pub fn hshnpen(&mut self) -> HSHNPEN_W<10> { + pub fn hshnpen(&mut self) -> HSHNPEN_W { HSHNPEN_W::new(self) } #[doc = "Bit 11 - Device HNP enabled"] #[inline(always)] #[must_use] - pub fn dhnpen(&mut self) -> DHNPEN_W<11> { + pub fn dhnpen(&mut self) -> DHNPEN_W { DHNPEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgctl](index.html) module"] +#[doc = "OTG_HS control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gotgctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gotgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GOTGCTL_SPEC; impl crate::RegisterSpec for GOTGCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gotgctl::R](R) reader structure"] -impl crate::Readable for GOTGCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gotgctl::W](W) writer structure"] +#[doc = "`read()` method returns [`gotgctl::R`](R) reader structure"] +impl crate::Readable for GOTGCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gotgctl::W`](W) writer structure"] impl crate::Writable for GOTGCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gotgint.rs b/crates/bcm2711-lpa/src/usb_otg_global/gotgint.rs index b2c3ab9..a44613f 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/gotgint.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/gotgint.rs @@ -1,63 +1,31 @@ #[doc = "Register `GOTGINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GOTGINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SEDET` reader - Session end detected"] -pub type SEDET_R = crate::BitReader; +pub type SEDET_R = crate::BitReader; #[doc = "Field `SEDET` writer - Session end detected"] -pub type SEDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type SEDET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRSSCHG` reader - Session request success status change"] -pub type SRSSCHG_R = crate::BitReader; +pub type SRSSCHG_R = crate::BitReader; #[doc = "Field `SRSSCHG` writer - Session request success status change"] -pub type SRSSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type SRSSCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HNSSCHG` reader - Host negotiation success status change"] -pub type HNSSCHG_R = crate::BitReader; +pub type HNSSCHG_R = crate::BitReader; #[doc = "Field `HNSSCHG` writer - Host negotiation success status change"] -pub type HNSSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type HNSSCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HNGDET` reader - Host negotiation detected"] -pub type HNGDET_R = crate::BitReader; +pub type HNGDET_R = crate::BitReader; #[doc = "Field `HNGDET` writer - Host negotiation detected"] -pub type HNGDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type HNGDET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ADTOCHG` reader - A-device timeout change"] -pub type ADTOCHG_R = crate::BitReader; +pub type ADTOCHG_R = crate::BitReader; #[doc = "Field `ADTOCHG` writer - A-device timeout change"] -pub type ADTOCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type ADTOCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DBCDNE` reader - Debounce done"] -pub type DBCDNE_R = crate::BitReader; +pub type DBCDNE_R = crate::BitReader; #[doc = "Field `DBCDNE` writer - Debounce done"] -pub type DBCDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type DBCDNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 2 - Session end detected"] #[inline(always)] @@ -90,62 +58,80 @@ impl R { DBCDNE_R::new(((self.bits >> 19) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GOTGINT") + .field("sedet", &format_args!("{}", self.sedet().bit())) + .field("srsschg", &format_args!("{}", self.srsschg().bit())) + .field("hnsschg", &format_args!("{}", self.hnsschg().bit())) + .field("hngdet", &format_args!("{}", self.hngdet().bit())) + .field("adtochg", &format_args!("{}", self.adtochg().bit())) + .field("dbcdne", &format_args!("{}", self.dbcdne().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 2 - Session end detected"] #[inline(always)] #[must_use] - pub fn sedet(&mut self) -> SEDET_W<2> { + pub fn sedet(&mut self) -> SEDET_W { SEDET_W::new(self) } #[doc = "Bit 8 - Session request success status change"] #[inline(always)] #[must_use] - pub fn srsschg(&mut self) -> SRSSCHG_W<8> { + pub fn srsschg(&mut self) -> SRSSCHG_W { SRSSCHG_W::new(self) } #[doc = "Bit 9 - Host negotiation success status change"] #[inline(always)] #[must_use] - pub fn hnsschg(&mut self) -> HNSSCHG_W<9> { + pub fn hnsschg(&mut self) -> HNSSCHG_W { HNSSCHG_W::new(self) } #[doc = "Bit 17 - Host negotiation detected"] #[inline(always)] #[must_use] - pub fn hngdet(&mut self) -> HNGDET_W<17> { + pub fn hngdet(&mut self) -> HNGDET_W { HNGDET_W::new(self) } #[doc = "Bit 18 - A-device timeout change"] #[inline(always)] #[must_use] - pub fn adtochg(&mut self) -> ADTOCHG_W<18> { + pub fn adtochg(&mut self) -> ADTOCHG_W { ADTOCHG_W::new(self) } #[doc = "Bit 19 - Debounce done"] #[inline(always)] #[must_use] - pub fn dbcdne(&mut self) -> DBCDNE_W<19> { + pub fn dbcdne(&mut self) -> DBCDNE_W { DBCDNE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgint](index.html) module"] +#[doc = "OTG_HS interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gotgint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gotgint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GOTGINT_SPEC; impl crate::RegisterSpec for GOTGINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gotgint::R](R) reader structure"] -impl crate::Readable for GOTGINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gotgint::W](W) writer structure"] +#[doc = "`read()` method returns [`gotgint::R`](R) reader structure"] +impl crate::Readable for GOTGINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gotgint::W`](W) writer structure"] impl crate::Writable for GOTGINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/grstctl.rs b/crates/bcm2711-lpa/src/usb_otg_global/grstctl.rs index c3f83dc..799d4ca 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/grstctl.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/grstctl.rs @@ -1,67 +1,35 @@ #[doc = "Register `GRSTCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GRSTCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CSRST` reader - Core soft reset"] -pub type CSRST_R = crate::BitReader; +pub type CSRST_R = crate::BitReader; #[doc = "Field `CSRST` writer - Core soft reset"] -pub type CSRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type CSRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HSRST` reader - HCLK soft reset"] -pub type HSRST_R = crate::BitReader; +pub type HSRST_R = crate::BitReader; #[doc = "Field `HSRST` writer - HCLK soft reset"] -pub type HSRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type HSRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FCRST` reader - Host frame counter reset"] -pub type FCRST_R = crate::BitReader; +pub type FCRST_R = crate::BitReader; #[doc = "Field `FCRST` writer - Host frame counter reset"] -pub type FCRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type FCRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFFLSH` reader - RxFIFO flush"] -pub type RXFFLSH_R = crate::BitReader; +pub type RXFFLSH_R = crate::BitReader; #[doc = "Field `RXFFLSH` writer - RxFIFO flush"] -pub type RXFFLSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type RXFFLSH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFFLSH` reader - TxFIFO flush"] -pub type TXFFLSH_R = crate::BitReader; +pub type TXFFLSH_R = crate::BitReader; #[doc = "Field `TXFFLSH` writer - TxFIFO flush"] -pub type TXFFLSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type TXFFLSH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFNUM` reader - TxFIFO number"] -pub type TXFNUM_R = crate::FieldReader; +pub type TXFNUM_R = crate::FieldReader; #[doc = "Field `TXFNUM` writer - TxFIFO number"] -pub type TXFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GRSTCTL_SPEC, u8, u8, 5, O>; +pub type TXFNUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `DMAREQ` reader - DMA request signal"] -pub type DMAREQ_R = crate::BitReader; +pub type DMAREQ_R = crate::BitReader; #[doc = "Field `AHBIDL` reader - AHB master idle"] -pub type AHBIDL_R = crate::BitReader; +pub type AHBIDL_R = crate::BitReader; impl R { #[doc = "Bit 0 - Core soft reset"] #[inline(always)] @@ -104,62 +72,82 @@ impl R { AHBIDL_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRSTCTL") + .field("csrst", &format_args!("{}", self.csrst().bit())) + .field("hsrst", &format_args!("{}", self.hsrst().bit())) + .field("fcrst", &format_args!("{}", self.fcrst().bit())) + .field("rxfflsh", &format_args!("{}", self.rxfflsh().bit())) + .field("txfflsh", &format_args!("{}", self.txfflsh().bit())) + .field("txfnum", &format_args!("{}", self.txfnum().bits())) + .field("dmareq", &format_args!("{}", self.dmareq().bit())) + .field("ahbidl", &format_args!("{}", self.ahbidl().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Core soft reset"] #[inline(always)] #[must_use] - pub fn csrst(&mut self) -> CSRST_W<0> { + pub fn csrst(&mut self) -> CSRST_W { CSRST_W::new(self) } #[doc = "Bit 1 - HCLK soft reset"] #[inline(always)] #[must_use] - pub fn hsrst(&mut self) -> HSRST_W<1> { + pub fn hsrst(&mut self) -> HSRST_W { HSRST_W::new(self) } #[doc = "Bit 2 - Host frame counter reset"] #[inline(always)] #[must_use] - pub fn fcrst(&mut self) -> FCRST_W<2> { + pub fn fcrst(&mut self) -> FCRST_W { FCRST_W::new(self) } #[doc = "Bit 4 - RxFIFO flush"] #[inline(always)] #[must_use] - pub fn rxfflsh(&mut self) -> RXFFLSH_W<4> { + pub fn rxfflsh(&mut self) -> RXFFLSH_W { RXFFLSH_W::new(self) } #[doc = "Bit 5 - TxFIFO flush"] #[inline(always)] #[must_use] - pub fn txfflsh(&mut self) -> TXFFLSH_W<5> { + pub fn txfflsh(&mut self) -> TXFFLSH_W { TXFFLSH_W::new(self) } #[doc = "Bits 6:10 - TxFIFO number"] #[inline(always)] #[must_use] - pub fn txfnum(&mut self) -> TXFNUM_W<6> { + pub fn txfnum(&mut self) -> TXFNUM_W { TXFNUM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS reset register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grstctl](index.html) module"] +#[doc = "OTG_HS reset register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grstctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grstctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRSTCTL_SPEC; impl crate::RegisterSpec for GRSTCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grstctl::R](R) reader structure"] -impl crate::Readable for GRSTCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [grstctl::W](W) writer structure"] +#[doc = "`read()` method returns [`grstctl::R`](R) reader structure"] +impl crate::Readable for GRSTCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`grstctl::W`](W) writer structure"] impl crate::Writable for GRSTCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/grxfsiz.rs b/crates/bcm2711-lpa/src/usb_otg_global/grxfsiz.rs index ec6ba8c..b243ab8 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/grxfsiz.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/grxfsiz.rs @@ -1,43 +1,11 @@ #[doc = "Register `GRXFSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GRXFSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXFD` reader - RxFIFO depth"] -pub type RXFD_R = crate::FieldReader; +pub type RXFD_R = crate::FieldReader; #[doc = "Field `RXFD` writer - RxFIFO depth"] -pub type RXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GRXFSIZ_SPEC, u16, u16, 16, O>; +pub type RXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - RxFIFO depth"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { RXFD_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXFSIZ") + .field("rxfd", &format_args!("{}", self.rxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - RxFIFO depth"] #[inline(always)] #[must_use] - pub fn rxfd(&mut self) -> RXFD_W<0> { + pub fn rxfd(&mut self) -> RXFD_W { RXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS Receive FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxfsiz](index.html) module"] +#[doc = "OTG_HS Receive FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxfsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grxfsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXFSIZ_SPEC; impl crate::RegisterSpec for GRXFSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxfsiz::R](R) reader structure"] -impl crate::Readable for GRXFSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [grxfsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`grxfsiz::R`](R) reader structure"] +impl crate::Readable for GRXFSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`grxfsiz::W`](W) writer structure"] impl crate::Writable for GRXFSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_host.rs b/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_host.rs index a0231ff..5e8d3bb 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_host.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_host.rs @@ -1,26 +1,13 @@ #[doc = "Register `GRXSTSP_Host` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CHNUM` reader - Channel number"] -pub type CHNUM_R = crate::FieldReader; +pub type CHNUM_R = crate::FieldReader; #[doc = "Field `BCNT` reader - Byte count"] -pub type BCNT_R = crate::FieldReader; +pub type BCNT_R = crate::FieldReader; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `PKTSTS` reader - Packet status"] -pub type PKTSTS_R = crate::FieldReader; +pub type PKTSTS_R = crate::FieldReader; impl R { #[doc = "Bits 0:3 - Channel number"] #[inline(always)] @@ -43,15 +30,28 @@ impl R { PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) } } -#[doc = "OTG_HS status read and pop register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsp_host](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXSTSP_Host") + .field("chnum", &format_args!("{}", self.chnum().bits())) + .field("bcnt", &format_args!("{}", self.bcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .field("pktsts", &format_args!("{}", self.pktsts().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS status read and pop register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp_host::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXSTSP_HOST_SPEC; impl crate::RegisterSpec for GRXSTSP_HOST_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxstsp_host::R](R) reader structure"] -impl crate::Readable for GRXSTSP_HOST_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`grxstsp_host::R`](R) reader structure"] +impl crate::Readable for GRXSTSP_HOST_SPEC {} #[doc = "`reset()` method sets GRXSTSP_Host to value 0"] impl crate::Resettable for GRXSTSP_HOST_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_peripheral.rs b/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_peripheral.rs index 5de1533..e28018e 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_peripheral.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/grxstsp_peripheral.rs @@ -1,28 +1,15 @@ #[doc = "Register `GRXSTSP_Peripheral` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EPNUM` reader - Endpoint number"] -pub type EPNUM_R = crate::FieldReader; +pub type EPNUM_R = crate::FieldReader; #[doc = "Field `BCNT` reader - Byte count"] -pub type BCNT_R = crate::FieldReader; +pub type BCNT_R = crate::FieldReader; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `PKTSTS` reader - Packet status"] -pub type PKTSTS_R = crate::FieldReader; +pub type PKTSTS_R = crate::FieldReader; #[doc = "Field `FRMNUM` reader - Frame number"] -pub type FRMNUM_R = crate::FieldReader; +pub type FRMNUM_R = crate::FieldReader; impl R { #[doc = "Bits 0:3 - Endpoint number"] #[inline(always)] @@ -50,15 +37,29 @@ impl R { FRMNUM_R::new(((self.bits >> 21) & 0x0f) as u8) } } -#[doc = "OTG_HS status read and pop register (peripheral mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsp_peripheral](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXSTSP_Peripheral") + .field("epnum", &format_args!("{}", self.epnum().bits())) + .field("bcnt", &format_args!("{}", self.bcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .field("pktsts", &format_args!("{}", self.pktsts().bits())) + .field("frmnum", &format_args!("{}", self.frmnum().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS status read and pop register (peripheral mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp_peripheral::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXSTSP_PERIPHERAL_SPEC; impl crate::RegisterSpec for GRXSTSP_PERIPHERAL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxstsp_peripheral::R](R) reader structure"] -impl crate::Readable for GRXSTSP_PERIPHERAL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`grxstsp_peripheral::R`](R) reader structure"] +impl crate::Readable for GRXSTSP_PERIPHERAL_SPEC {} #[doc = "`reset()` method sets GRXSTSP_Peripheral to value 0"] impl crate::Resettable for GRXSTSP_PERIPHERAL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_host.rs b/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_host.rs index 399a9f8..e9e1ba6 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_host.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_host.rs @@ -1,26 +1,13 @@ #[doc = "Register `GRXSTSR_Host` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CHNUM` reader - Channel number"] -pub type CHNUM_R = crate::FieldReader; +pub type CHNUM_R = crate::FieldReader; #[doc = "Field `BCNT` reader - Byte count"] -pub type BCNT_R = crate::FieldReader; +pub type BCNT_R = crate::FieldReader; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `PKTSTS` reader - Packet status"] -pub type PKTSTS_R = crate::FieldReader; +pub type PKTSTS_R = crate::FieldReader; impl R { #[doc = "Bits 0:3 - Channel number"] #[inline(always)] @@ -43,15 +30,28 @@ impl R { PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) } } -#[doc = "OTG_HS Receive status debug read register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsr_host](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXSTSR_Host") + .field("chnum", &format_args!("{}", self.chnum().bits())) + .field("bcnt", &format_args!("{}", self.bcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .field("pktsts", &format_args!("{}", self.pktsts().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS Receive status debug read register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr_host::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXSTSR_HOST_SPEC; impl crate::RegisterSpec for GRXSTSR_HOST_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxstsr_host::R](R) reader structure"] -impl crate::Readable for GRXSTSR_HOST_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`grxstsr_host::R`](R) reader structure"] +impl crate::Readable for GRXSTSR_HOST_SPEC {} #[doc = "`reset()` method sets GRXSTSR_Host to value 0"] impl crate::Resettable for GRXSTSR_HOST_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_peripheral.rs b/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_peripheral.rs index 89558d9..d6f8ca3 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_peripheral.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/grxstsr_peripheral.rs @@ -1,28 +1,15 @@ #[doc = "Register `GRXSTSR_Peripheral` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EPNUM` reader - Endpoint number"] -pub type EPNUM_R = crate::FieldReader; +pub type EPNUM_R = crate::FieldReader; #[doc = "Field `BCNT` reader - Byte count"] -pub type BCNT_R = crate::FieldReader; +pub type BCNT_R = crate::FieldReader; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `PKTSTS` reader - Packet status"] -pub type PKTSTS_R = crate::FieldReader; +pub type PKTSTS_R = crate::FieldReader; #[doc = "Field `FRMNUM` reader - Frame number"] -pub type FRMNUM_R = crate::FieldReader; +pub type FRMNUM_R = crate::FieldReader; impl R { #[doc = "Bits 0:3 - Endpoint number"] #[inline(always)] @@ -50,15 +37,29 @@ impl R { FRMNUM_R::new(((self.bits >> 21) & 0x0f) as u8) } } -#[doc = "OTG_HS Receive status debug read register (peripheral mode mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsr_peripheral](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXSTSR_Peripheral") + .field("epnum", &format_args!("{}", self.epnum().bits())) + .field("bcnt", &format_args!("{}", self.bcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .field("pktsts", &format_args!("{}", self.pktsts().bits())) + .field("frmnum", &format_args!("{}", self.frmnum().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS Receive status debug read register (peripheral mode mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr_peripheral::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXSTSR_PERIPHERAL_SPEC; impl crate::RegisterSpec for GRXSTSR_PERIPHERAL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxstsr_peripheral::R](R) reader structure"] -impl crate::Readable for GRXSTSR_PERIPHERAL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`grxstsr_peripheral::R`](R) reader structure"] +impl crate::Readable for GRXSTSR_PERIPHERAL_SPEC {} #[doc = "`reset()` method sets GRXSTSR_Peripheral to value 0"] impl crate::Resettable for GRXSTSR_PERIPHERAL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/usb_otg_global/gusbcfg.rs b/crates/bcm2711-lpa/src/usb_otg_global/gusbcfg.rs index a958441..b5f882e 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/gusbcfg.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/gusbcfg.rs @@ -1,43 +1,11 @@ #[doc = "Register `GUSBCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GUSBCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TOCAL` reader - FS timeout calibration"] -pub type TOCAL_R = crate::FieldReader; +pub type TOCAL_R = crate::FieldReader; #[doc = "Field `TOCAL` writer - FS timeout calibration"] -pub type TOCAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GUSBCFG_SPEC, u8, u8, 3, O>; +pub type TOCAL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `PHYIF` reader - PHY Interface width"] pub type PHYIF_R = crate::BitReader; #[doc = "PHY Interface width\n\nValue on reset: 0"] @@ -57,34 +25,37 @@ impl From for bool { impl PHYIF_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PHYIF_A { + pub const fn variant(&self) -> PHYIF_A { match self.bits { false => PHYIF_A::_8BIT, true => PHYIF_A::_16BIT, } } - #[doc = "Checks if the value of the field is `_8BIT`"] + #[doc = "`0`"] #[inline(always)] pub fn is_8bit(&self) -> bool { *self == PHYIF_A::_8BIT } - #[doc = "Checks if the value of the field is `_16BIT`"] + #[doc = "`1`"] #[inline(always)] pub fn is_16bit(&self) -> bool { *self == PHYIF_A::_16BIT } } #[doc = "Field `PHYIF` writer - PHY Interface width"] -pub type PHYIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYIF_A, O>; -impl<'a, const O: u8> PHYIF_W<'a, O> { +pub type PHYIF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PHYIF_A>; +impl<'a, REG, const O: u8> PHYIF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn _8bit(self) -> &'a mut W { + pub fn _8bit(self) -> &'a mut crate::W { self.variant(PHYIF_A::_8BIT) } #[doc = "`1`"] #[inline(always)] - pub fn _16bit(self) -> &'a mut W { + pub fn _16bit(self) -> &'a mut crate::W { self.variant(PHYIF_A::_16BIT) } } @@ -107,34 +78,37 @@ impl From for bool { impl PHYTYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PHYTYPE_A { + pub const fn variant(&self) -> PHYTYPE_A { match self.bits { false => PHYTYPE_A::UTMI, true => PHYTYPE_A::ULPI, } } - #[doc = "Checks if the value of the field is `UTMI`"] + #[doc = "`0`"] #[inline(always)] pub fn is_utmi(&self) -> bool { *self == PHYTYPE_A::UTMI } - #[doc = "Checks if the value of the field is `ULPI`"] + #[doc = "`1`"] #[inline(always)] pub fn is_ulpi(&self) -> bool { *self == PHYTYPE_A::ULPI } } #[doc = "Field `PHYTYPE` writer - PHY Type"] -pub type PHYTYPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYTYPE_A, O>; -impl<'a, const O: u8> PHYTYPE_W<'a, O> { +pub type PHYTYPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PHYTYPE_A>; +impl<'a, REG, const O: u8> PHYTYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn utmi(self) -> &'a mut W { + pub fn utmi(self) -> &'a mut crate::W { self.variant(PHYTYPE_A::UTMI) } #[doc = "`1`"] #[inline(always)] - pub fn ulpi(self) -> &'a mut W { + pub fn ulpi(self) -> &'a mut crate::W { self.variant(PHYTYPE_A::ULPI) } } @@ -157,34 +131,37 @@ impl From for bool { impl FSIF_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSIF_A { + pub const fn variant(&self) -> FSIF_A { match self.bits { false => FSIF_A::_6PIN, true => FSIF_A::_3PIN, } } - #[doc = "Checks if the value of the field is `_6PIN`"] + #[doc = "`0`"] #[inline(always)] pub fn is_6pin(&self) -> bool { *self == FSIF_A::_6PIN } - #[doc = "Checks if the value of the field is `_3PIN`"] + #[doc = "`1`"] #[inline(always)] pub fn is_3pin(&self) -> bool { *self == FSIF_A::_3PIN } } #[doc = "Field `FSIF` writer - Full speed interface"] -pub type FSIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, FSIF_A, O>; -impl<'a, const O: u8> FSIF_W<'a, O> { +pub type FSIF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, FSIF_A>; +impl<'a, REG, const O: u8> FSIF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn _6pin(self) -> &'a mut W { + pub fn _6pin(self) -> &'a mut crate::W { self.variant(FSIF_A::_6PIN) } #[doc = "`1`"] #[inline(always)] - pub fn _3pin(self) -> &'a mut W { + pub fn _3pin(self) -> &'a mut crate::W { self.variant(FSIF_A::_3PIN) } } @@ -207,34 +184,37 @@ impl From for bool { impl PHYSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PHYSEL_A { + pub const fn variant(&self) -> PHYSEL_A { match self.bits { false => PHYSEL_A::USB20, true => PHYSEL_A::USB11, } } - #[doc = "Checks if the value of the field is `USB20`"] + #[doc = "`0`"] #[inline(always)] pub fn is_usb20(&self) -> bool { *self == PHYSEL_A::USB20 } - #[doc = "Checks if the value of the field is `USB11`"] + #[doc = "`1`"] #[inline(always)] pub fn is_usb11(&self) -> bool { *self == PHYSEL_A::USB11 } } #[doc = "Field `PHYSEL` writer - Transceiver select"] -pub type PHYSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYSEL_A, O>; -impl<'a, const O: u8> PHYSEL_W<'a, O> { +pub type PHYSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PHYSEL_A>; +impl<'a, REG, const O: u8> PHYSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn usb20(self) -> &'a mut W { + pub fn usb20(self) -> &'a mut crate::W { self.variant(PHYSEL_A::USB20) } #[doc = "`1`"] #[inline(always)] - pub fn usb11(self) -> &'a mut W { + pub fn usb11(self) -> &'a mut crate::W { self.variant(PHYSEL_A::USB11) } } @@ -257,101 +237,104 @@ impl From for bool { impl DDRSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DDRSEL_A { + pub const fn variant(&self) -> DDRSEL_A { match self.bits { false => DDRSEL_A::SINGLE, true => DDRSEL_A::DOUBLE, } } - #[doc = "Checks if the value of the field is `SINGLE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_single(&self) -> bool { *self == DDRSEL_A::SINGLE } - #[doc = "Checks if the value of the field is `DOUBLE`"] + #[doc = "`1`"] #[inline(always)] pub fn is_double(&self) -> bool { *self == DDRSEL_A::DOUBLE } } #[doc = "Field `DDRSEL` writer - ULPI data rate"] -pub type DDRSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, DDRSEL_A, O>; -impl<'a, const O: u8> DDRSEL_W<'a, O> { +pub type DDRSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DDRSEL_A>; +impl<'a, REG, const O: u8> DDRSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn single(self) -> &'a mut W { + pub fn single(self) -> &'a mut crate::W { self.variant(DDRSEL_A::SINGLE) } #[doc = "`1`"] #[inline(always)] - pub fn double(self) -> &'a mut W { + pub fn double(self) -> &'a mut crate::W { self.variant(DDRSEL_A::DOUBLE) } } #[doc = "Field `SRPCAP` reader - SRP-capable"] -pub type SRPCAP_R = crate::BitReader; +pub type SRPCAP_R = crate::BitReader; #[doc = "Field `SRPCAP` writer - SRP-capable"] -pub type SRPCAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type SRPCAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HNPCAP` reader - HNP-capable"] -pub type HNPCAP_R = crate::BitReader; +pub type HNPCAP_R = crate::BitReader; #[doc = "Field `HNPCAP` writer - HNP-capable"] -pub type HNPCAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type HNPCAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TRDT` reader - USB turnaround time"] -pub type TRDT_R = crate::FieldReader; +pub type TRDT_R = crate::FieldReader; #[doc = "Field `TRDT` writer - USB turnaround time"] -pub type TRDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GUSBCFG_SPEC, u8, u8, 4, O>; +pub type TRDT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `PHYLPCS` reader - PHY Low-power clock select"] -pub type PHYLPCS_R = crate::BitReader; +pub type PHYLPCS_R = crate::BitReader; #[doc = "Field `PHYLPCS` writer - PHY Low-power clock select"] -pub type PHYLPCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type PHYLPCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIFSLS` reader - ULPI FS/LS select"] -pub type ULPIFSLS_R = crate::BitReader; +pub type ULPIFSLS_R = crate::BitReader; #[doc = "Field `ULPIFSLS` writer - ULPI FS/LS select"] -pub type ULPIFSLS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIFSLS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIAR` reader - ULPI Auto-resume"] -pub type ULPIAR_R = crate::BitReader; +pub type ULPIAR_R = crate::BitReader; #[doc = "Field `ULPIAR` writer - ULPI Auto-resume"] -pub type ULPIAR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPICSM` reader - ULPI Clock SuspendM"] -pub type ULPICSM_R = crate::BitReader; +pub type ULPICSM_R = crate::BitReader; #[doc = "Field `ULPICSM` writer - ULPI Clock SuspendM"] -pub type ULPICSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPICSM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIEVBUSD` reader - ULPI External VBUS Drive"] -pub type ULPIEVBUSD_R = crate::BitReader; +pub type ULPIEVBUSD_R = crate::BitReader; #[doc = "Field `ULPIEVBUSD` writer - ULPI External VBUS Drive"] -pub type ULPIEVBUSD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIEVBUSD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIEVBUSI` reader - ULPI external VBUS indicator"] -pub type ULPIEVBUSI_R = crate::BitReader; +pub type ULPIEVBUSI_R = crate::BitReader; #[doc = "Field `ULPIEVBUSI` writer - ULPI external VBUS indicator"] -pub type ULPIEVBUSI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIEVBUSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSDPS` reader - TermSel DLine pulsing selection"] -pub type TSDPS_R = crate::BitReader; +pub type TSDPS_R = crate::BitReader; #[doc = "Field `TSDPS` writer - TermSel DLine pulsing selection"] -pub type TSDPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type TSDPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCCI` reader - Indicator complement"] -pub type PCCI_R = crate::BitReader; +pub type PCCI_R = crate::BitReader; #[doc = "Field `PCCI` writer - Indicator complement"] -pub type PCCI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type PCCI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTCI` reader - Indicator pass through"] -pub type PTCI_R = crate::BitReader; +pub type PTCI_R = crate::BitReader; #[doc = "Field `PTCI` writer - Indicator pass through"] -pub type PTCI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type PTCI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIIPD` reader - ULPI interface protect disable"] -pub type ULPIIPD_R = crate::BitReader; +pub type ULPIIPD_R = crate::BitReader; #[doc = "Field `ULPIIPD` writer - ULPI interface protect disable"] -pub type ULPIIPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIIPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FHMOD` reader - Forced host mode"] -pub type FHMOD_R = crate::BitReader; +pub type FHMOD_R = crate::BitReader; #[doc = "Field `FHMOD` writer - Forced host mode"] -pub type FHMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type FHMOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FDMOD` reader - Forced peripheral mode"] -pub type FDMOD_R = crate::BitReader; +pub type FDMOD_R = crate::BitReader; #[doc = "Field `FDMOD` writer - Forced peripheral mode"] -pub type FDMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type FDMOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTXPKT` reader - Corrupt Tx packet"] -pub type CTXPKT_R = crate::BitReader; +pub type CTXPKT_R = crate::BitReader; #[doc = "Field `CTXPKT` writer - Corrupt Tx packet"] -pub type CTXPKT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type CTXPKT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:2 - FS timeout calibration"] #[inline(always)] @@ -464,158 +447,192 @@ impl R { CTXPKT_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GUSBCFG") + .field("tocal", &format_args!("{}", self.tocal().bits())) + .field("phyif", &format_args!("{}", self.phyif().bit())) + .field("phytype", &format_args!("{}", self.phytype().bit())) + .field("fsif", &format_args!("{}", self.fsif().bit())) + .field("physel", &format_args!("{}", self.physel().bit())) + .field("ddrsel", &format_args!("{}", self.ddrsel().bit())) + .field("srpcap", &format_args!("{}", self.srpcap().bit())) + .field("hnpcap", &format_args!("{}", self.hnpcap().bit())) + .field("trdt", &format_args!("{}", self.trdt().bits())) + .field("phylpcs", &format_args!("{}", self.phylpcs().bit())) + .field("ulpifsls", &format_args!("{}", self.ulpifsls().bit())) + .field("ulpiar", &format_args!("{}", self.ulpiar().bit())) + .field("ulpicsm", &format_args!("{}", self.ulpicsm().bit())) + .field("ulpievbusd", &format_args!("{}", self.ulpievbusd().bit())) + .field("ulpievbusi", &format_args!("{}", self.ulpievbusi().bit())) + .field("tsdps", &format_args!("{}", self.tsdps().bit())) + .field("pcci", &format_args!("{}", self.pcci().bit())) + .field("ptci", &format_args!("{}", self.ptci().bit())) + .field("ulpiipd", &format_args!("{}", self.ulpiipd().bit())) + .field("fhmod", &format_args!("{}", self.fhmod().bit())) + .field("fdmod", &format_args!("{}", self.fdmod().bit())) + .field("ctxpkt", &format_args!("{}", self.ctxpkt().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - FS timeout calibration"] #[inline(always)] #[must_use] - pub fn tocal(&mut self) -> TOCAL_W<0> { + pub fn tocal(&mut self) -> TOCAL_W { TOCAL_W::new(self) } #[doc = "Bit 3 - PHY Interface width"] #[inline(always)] #[must_use] - pub fn phyif(&mut self) -> PHYIF_W<3> { + pub fn phyif(&mut self) -> PHYIF_W { PHYIF_W::new(self) } #[doc = "Bit 4 - PHY Type"] #[inline(always)] #[must_use] - pub fn phytype(&mut self) -> PHYTYPE_W<4> { + pub fn phytype(&mut self) -> PHYTYPE_W { PHYTYPE_W::new(self) } #[doc = "Bit 5 - Full speed interface"] #[inline(always)] #[must_use] - pub fn fsif(&mut self) -> FSIF_W<5> { + pub fn fsif(&mut self) -> FSIF_W { FSIF_W::new(self) } #[doc = "Bit 6 - Transceiver select"] #[inline(always)] #[must_use] - pub fn physel(&mut self) -> PHYSEL_W<6> { + pub fn physel(&mut self) -> PHYSEL_W { PHYSEL_W::new(self) } #[doc = "Bit 7 - ULPI data rate"] #[inline(always)] #[must_use] - pub fn ddrsel(&mut self) -> DDRSEL_W<7> { + pub fn ddrsel(&mut self) -> DDRSEL_W { DDRSEL_W::new(self) } #[doc = "Bit 8 - SRP-capable"] #[inline(always)] #[must_use] - pub fn srpcap(&mut self) -> SRPCAP_W<8> { + pub fn srpcap(&mut self) -> SRPCAP_W { SRPCAP_W::new(self) } #[doc = "Bit 9 - HNP-capable"] #[inline(always)] #[must_use] - pub fn hnpcap(&mut self) -> HNPCAP_W<9> { + pub fn hnpcap(&mut self) -> HNPCAP_W { HNPCAP_W::new(self) } #[doc = "Bits 10:13 - USB turnaround time"] #[inline(always)] #[must_use] - pub fn trdt(&mut self) -> TRDT_W<10> { + pub fn trdt(&mut self) -> TRDT_W { TRDT_W::new(self) } #[doc = "Bit 15 - PHY Low-power clock select"] #[inline(always)] #[must_use] - pub fn phylpcs(&mut self) -> PHYLPCS_W<15> { + pub fn phylpcs(&mut self) -> PHYLPCS_W { PHYLPCS_W::new(self) } #[doc = "Bit 17 - ULPI FS/LS select"] #[inline(always)] #[must_use] - pub fn ulpifsls(&mut self) -> ULPIFSLS_W<17> { + pub fn ulpifsls(&mut self) -> ULPIFSLS_W { ULPIFSLS_W::new(self) } #[doc = "Bit 18 - ULPI Auto-resume"] #[inline(always)] #[must_use] - pub fn ulpiar(&mut self) -> ULPIAR_W<18> { + pub fn ulpiar(&mut self) -> ULPIAR_W { ULPIAR_W::new(self) } #[doc = "Bit 19 - ULPI Clock SuspendM"] #[inline(always)] #[must_use] - pub fn ulpicsm(&mut self) -> ULPICSM_W<19> { + pub fn ulpicsm(&mut self) -> ULPICSM_W { ULPICSM_W::new(self) } #[doc = "Bit 20 - ULPI External VBUS Drive"] #[inline(always)] #[must_use] - pub fn ulpievbusd(&mut self) -> ULPIEVBUSD_W<20> { + pub fn ulpievbusd(&mut self) -> ULPIEVBUSD_W { ULPIEVBUSD_W::new(self) } #[doc = "Bit 21 - ULPI external VBUS indicator"] #[inline(always)] #[must_use] - pub fn ulpievbusi(&mut self) -> ULPIEVBUSI_W<21> { + pub fn ulpievbusi(&mut self) -> ULPIEVBUSI_W { ULPIEVBUSI_W::new(self) } #[doc = "Bit 22 - TermSel DLine pulsing selection"] #[inline(always)] #[must_use] - pub fn tsdps(&mut self) -> TSDPS_W<22> { + pub fn tsdps(&mut self) -> TSDPS_W { TSDPS_W::new(self) } #[doc = "Bit 23 - Indicator complement"] #[inline(always)] #[must_use] - pub fn pcci(&mut self) -> PCCI_W<23> { + pub fn pcci(&mut self) -> PCCI_W { PCCI_W::new(self) } #[doc = "Bit 24 - Indicator pass through"] #[inline(always)] #[must_use] - pub fn ptci(&mut self) -> PTCI_W<24> { + pub fn ptci(&mut self) -> PTCI_W { PTCI_W::new(self) } #[doc = "Bit 25 - ULPI interface protect disable"] #[inline(always)] #[must_use] - pub fn ulpiipd(&mut self) -> ULPIIPD_W<25> { + pub fn ulpiipd(&mut self) -> ULPIIPD_W { ULPIIPD_W::new(self) } #[doc = "Bit 29 - Forced host mode"] #[inline(always)] #[must_use] - pub fn fhmod(&mut self) -> FHMOD_W<29> { + pub fn fhmod(&mut self) -> FHMOD_W { FHMOD_W::new(self) } #[doc = "Bit 30 - Forced peripheral mode"] #[inline(always)] #[must_use] - pub fn fdmod(&mut self) -> FDMOD_W<30> { + pub fn fdmod(&mut self) -> FDMOD_W { FDMOD_W::new(self) } #[doc = "Bit 31 - Corrupt Tx packet"] #[inline(always)] #[must_use] - pub fn ctxpkt(&mut self) -> CTXPKT_W<31> { + pub fn ctxpkt(&mut self) -> CTXPKT_W { CTXPKT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS USB configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gusbcfg](index.html) module"] +#[doc = "OTG_HS USB configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gusbcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gusbcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GUSBCFG_SPEC; impl crate::RegisterSpec for GUSBCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gusbcfg::R](R) reader structure"] -impl crate::Readable for GUSBCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gusbcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`gusbcfg::R`](R) reader structure"] +impl crate::Readable for GUSBCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gusbcfg::W`](W) writer structure"] impl crate::Writable for GUSBCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/hptxfsiz.rs b/crates/bcm2711-lpa/src/usb_otg_global/hptxfsiz.rs index c50a180..cd99421 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/hptxfsiz.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/hptxfsiz.rs @@ -1,47 +1,15 @@ #[doc = "Register `HPTXFSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HPTXFSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PTXSA` reader - Host periodic TxFIFO start address"] -pub type PTXSA_R = crate::FieldReader; +pub type PTXSA_R = crate::FieldReader; #[doc = "Field `PTXSA` writer - Host periodic TxFIFO start address"] -pub type PTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXFSIZ_SPEC, u16, u16, 16, O>; +pub type PTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `PTXFD` reader - Host periodic TxFIFO depth"] -pub type PTXFD_R = crate::FieldReader; +pub type PTXFD_R = crate::FieldReader; #[doc = "Field `PTXFD` writer - Host periodic TxFIFO depth"] -pub type PTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXFSIZ_SPEC, u16, u16, 16, O>; +pub type PTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Host periodic TxFIFO start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { PTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HPTXFSIZ") + .field("ptxsa", &format_args!("{}", self.ptxsa().bits())) + .field("ptxfd", &format_args!("{}", self.ptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Host periodic TxFIFO start address"] #[inline(always)] #[must_use] - pub fn ptxsa(&mut self) -> PTXSA_W<0> { + pub fn ptxsa(&mut self) -> PTXSA_W { PTXSA_W::new(self) } #[doc = "Bits 16:31 - Host periodic TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ptxfd(&mut self) -> PTXFD_W<16> { + pub fn ptxfd(&mut self) -> PTXFD_W { PTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS Host periodic transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxfsiz](index.html) module"] +#[doc = "OTG_HS Host periodic transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxfsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hptxfsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HPTXFSIZ_SPEC; impl crate::RegisterSpec for HPTXFSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hptxfsiz::R](R) reader structure"] -impl crate::Readable for HPTXFSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hptxfsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`hptxfsiz::R`](R) reader structure"] +impl crate::Readable for HPTXFSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hptxfsiz::W`](W) writer structure"] impl crate::Writable for HPTXFSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/hw_config0.rs b/crates/bcm2711-lpa/src/usb_otg_global/hw_config0.rs index 13715b7..93348b4 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/hw_config0.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/hw_config0.rs @@ -1,20 +1,7 @@ #[doc = "Register `HW_CONFIG0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `OPERATING_MODE` reader - Operating Mode"] -pub type OPERATING_MODE_R = crate::FieldReader; +pub type OPERATING_MODE_R = crate::FieldReader; #[doc = "Operating Mode"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -40,10 +27,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for OPERATING_MODE_A { + type Ux = u8; +} impl OPERATING_MODE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(OPERATING_MODE_A::HNP_SRP_CAPABLE), 1 => Some(OPERATING_MODE_A::SRP_ONLY_CAPABLE), @@ -55,44 +45,44 @@ impl OPERATING_MODE_R { _ => None, } } - #[doc = "Checks if the value of the field is `HNP_SRP_CAPABLE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_hnp_srp_capable(&self) -> bool { *self == OPERATING_MODE_A::HNP_SRP_CAPABLE } - #[doc = "Checks if the value of the field is `SRP_ONLY_CAPABLE`"] + #[doc = "`1`"] #[inline(always)] pub fn is_srp_only_capable(&self) -> bool { *self == OPERATING_MODE_A::SRP_ONLY_CAPABLE } - #[doc = "Checks if the value of the field is `NO_HNP_SRP_CAPABLE`"] + #[doc = "`10`"] #[inline(always)] pub fn is_no_hnp_srp_capable(&self) -> bool { *self == OPERATING_MODE_A::NO_HNP_SRP_CAPABLE } - #[doc = "Checks if the value of the field is `SRP_CAPABLE_DEVICE`"] + #[doc = "`11`"] #[inline(always)] pub fn is_srp_capable_device(&self) -> bool { *self == OPERATING_MODE_A::SRP_CAPABLE_DEVICE } - #[doc = "Checks if the value of the field is `NO_SRP_CAPABLE_DEVICE`"] + #[doc = "`100`"] #[inline(always)] pub fn is_no_srp_capable_device(&self) -> bool { *self == OPERATING_MODE_A::NO_SRP_CAPABLE_DEVICE } - #[doc = "Checks if the value of the field is `SRP_CAPABLE_HOST`"] + #[doc = "`101`"] #[inline(always)] pub fn is_srp_capable_host(&self) -> bool { *self == OPERATING_MODE_A::SRP_CAPABLE_HOST } - #[doc = "Checks if the value of the field is `NO_SRP_CAPABLE_HOST`"] + #[doc = "`110`"] #[inline(always)] pub fn is_no_srp_capable_host(&self) -> bool { *self == OPERATING_MODE_A::NO_SRP_CAPABLE_HOST } } #[doc = "Field `ARCHITECTURE` reader - Architecture"] -pub type ARCHITECTURE_R = crate::FieldReader; +pub type ARCHITECTURE_R = crate::FieldReader; #[doc = "Architecture"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -110,10 +100,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for ARCHITECTURE_A { + type Ux = u8; +} impl ARCHITECTURE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(ARCHITECTURE_A::SLAVE_ONLY), 1 => Some(ARCHITECTURE_A::EXTERNAL_DMA), @@ -121,26 +114,26 @@ impl ARCHITECTURE_R { _ => None, } } - #[doc = "Checks if the value of the field is `SLAVE_ONLY`"] + #[doc = "`0`"] #[inline(always)] pub fn is_slave_only(&self) -> bool { *self == ARCHITECTURE_A::SLAVE_ONLY } - #[doc = "Checks if the value of the field is `EXTERNAL_DMA`"] + #[doc = "`1`"] #[inline(always)] pub fn is_external_dma(&self) -> bool { *self == ARCHITECTURE_A::EXTERNAL_DMA } - #[doc = "Checks if the value of the field is `INTERNAL_DMA`"] + #[doc = "`10`"] #[inline(always)] pub fn is_internal_dma(&self) -> bool { *self == ARCHITECTURE_A::INTERNAL_DMA } } #[doc = "Field `POINT_TO_POINT` reader - Point to Point"] -pub type POINT_TO_POINT_R = crate::BitReader; +pub type POINT_TO_POINT_R = crate::BitReader; #[doc = "Field `HIGH_SPEED_PHY` reader - High Speed Physical"] -pub type HIGH_SPEED_PHY_R = crate::FieldReader; +pub type HIGH_SPEED_PHY_R = crate::FieldReader; #[doc = "High Speed Physical"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -160,10 +153,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for HIGH_SPEED_PHY_A { + type Ux = u8; +} impl HIGH_SPEED_PHY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> HIGH_SPEED_PHY_A { + pub const fn variant(&self) -> HIGH_SPEED_PHY_A { match self.bits { 0 => HIGH_SPEED_PHY_A::NOT_SUPPORTED, 1 => HIGH_SPEED_PHY_A::UTMI, @@ -172,29 +168,29 @@ impl HIGH_SPEED_PHY_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NOT_SUPPORTED`"] + #[doc = "`0`"] #[inline(always)] pub fn is_not_supported(&self) -> bool { *self == HIGH_SPEED_PHY_A::NOT_SUPPORTED } - #[doc = "Checks if the value of the field is `UTMI`"] + #[doc = "`1`"] #[inline(always)] pub fn is_utmi(&self) -> bool { *self == HIGH_SPEED_PHY_A::UTMI } - #[doc = "Checks if the value of the field is `ULPI`"] + #[doc = "`10`"] #[inline(always)] pub fn is_ulpi(&self) -> bool { *self == HIGH_SPEED_PHY_A::ULPI } - #[doc = "Checks if the value of the field is `UTMI_ULPI`"] + #[doc = "`11`"] #[inline(always)] pub fn is_utmi_ulpi(&self) -> bool { *self == HIGH_SPEED_PHY_A::UTMI_ULPI } } #[doc = "Field `FULL_SPEED_PHY` reader - Full Speed Physical"] -pub type FULL_SPEED_PHY_R = crate::FieldReader; +pub type FULL_SPEED_PHY_R = crate::FieldReader; #[doc = "Full Speed Physical"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -214,10 +210,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FULL_SPEED_PHY_A { + type Ux = u8; +} impl FULL_SPEED_PHY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FULL_SPEED_PHY_A { + pub const fn variant(&self) -> FULL_SPEED_PHY_A { match self.bits { 0 => FULL_SPEED_PHY_A::PHY0, 1 => FULL_SPEED_PHY_A::DEDICATED, @@ -226,45 +225,45 @@ impl FULL_SPEED_PHY_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `PHY0`"] + #[doc = "`0`"] #[inline(always)] pub fn is_phy0(&self) -> bool { *self == FULL_SPEED_PHY_A::PHY0 } - #[doc = "Checks if the value of the field is `DEDICATED`"] + #[doc = "`1`"] #[inline(always)] pub fn is_dedicated(&self) -> bool { *self == FULL_SPEED_PHY_A::DEDICATED } - #[doc = "Checks if the value of the field is `PHY2`"] + #[doc = "`10`"] #[inline(always)] pub fn is_phy2(&self) -> bool { *self == FULL_SPEED_PHY_A::PHY2 } - #[doc = "Checks if the value of the field is `PHY3`"] + #[doc = "`11`"] #[inline(always)] pub fn is_phy3(&self) -> bool { *self == FULL_SPEED_PHY_A::PHY3 } } #[doc = "Field `DEVICE_END_POINT_COUNT` reader - Device end point count"] -pub type DEVICE_END_POINT_COUNT_R = crate::FieldReader; +pub type DEVICE_END_POINT_COUNT_R = crate::FieldReader; #[doc = "Field `HOST_CHANNEL_COUNT` reader - Host channel count"] -pub type HOST_CHANNEL_COUNT_R = crate::FieldReader; +pub type HOST_CHANNEL_COUNT_R = crate::FieldReader; #[doc = "Field `SUPPORTS_PERIODIC_ENDPOINTS` reader - Supports periodic endpoints"] -pub type SUPPORTS_PERIODIC_ENDPOINTS_R = crate::BitReader; +pub type SUPPORTS_PERIODIC_ENDPOINTS_R = crate::BitReader; #[doc = "Field `DYNAMIC_FIFO` reader - Dynamic FIFO"] -pub type DYNAMIC_FIFO_R = crate::BitReader; +pub type DYNAMIC_FIFO_R = crate::BitReader; #[doc = "Field `MULTI_PROC_INT` reader - Multi proc int"] -pub type MULTI_PROC_INT_R = crate::BitReader; +pub type MULTI_PROC_INT_R = crate::BitReader; #[doc = "Field `NON_PERIODIC_QUEUE_DEPTH` reader - Non periodic queue depth"] -pub type NON_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; +pub type NON_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; #[doc = "Field `HOST_PERIODIC_QUEUE_DEPTH` reader - Host periodic queue depth"] -pub type HOST_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; +pub type HOST_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; #[doc = "Field `DEVICE_TOKEN_QUEUE_DEPTH` reader - Device token queue depth"] -pub type DEVICE_TOKEN_QUEUE_DEPTH_R = crate::FieldReader; +pub type DEVICE_TOKEN_QUEUE_DEPTH_R = crate::FieldReader; #[doc = "Field `ENABLE_IC_USB` reader - Enable IC USB"] -pub type ENABLE_IC_USB_R = crate::BitReader; +pub type ENABLE_IC_USB_R = crate::BitReader; impl R { #[doc = "Bits 0:2 - Operating Mode"] #[inline(always)] @@ -337,12 +336,77 @@ impl R { ENABLE_IC_USB_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Hardware Config 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hw_config0](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HW_CONFIG0") + .field( + "operating_mode", + &format_args!("{}", self.operating_mode().bits()), + ) + .field( + "architecture", + &format_args!("{}", self.architecture().bits()), + ) + .field( + "point_to_point", + &format_args!("{}", self.point_to_point().bit()), + ) + .field( + "high_speed_phy", + &format_args!("{}", self.high_speed_phy().bits()), + ) + .field( + "full_speed_phy", + &format_args!("{}", self.full_speed_phy().bits()), + ) + .field( + "device_end_point_count", + &format_args!("{}", self.device_end_point_count().bits()), + ) + .field( + "host_channel_count", + &format_args!("{}", self.host_channel_count().bits()), + ) + .field( + "supports_periodic_endpoints", + &format_args!("{}", self.supports_periodic_endpoints().bit()), + ) + .field( + "dynamic_fifo", + &format_args!("{}", self.dynamic_fifo().bit()), + ) + .field( + "multi_proc_int", + &format_args!("{}", self.multi_proc_int().bit()), + ) + .field( + "non_periodic_queue_depth", + &format_args!("{}", self.non_periodic_queue_depth().bits()), + ) + .field( + "host_periodic_queue_depth", + &format_args!("{}", self.host_periodic_queue_depth().bits()), + ) + .field( + "device_token_queue_depth", + &format_args!("{}", self.device_token_queue_depth().bits()), + ) + .field( + "enable_ic_usb", + &format_args!("{}", self.enable_ic_usb().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Hardware Config 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_config0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HW_CONFIG0_SPEC; impl crate::RegisterSpec for HW_CONFIG0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hw_config0::R](R) reader structure"] -impl crate::Readable for HW_CONFIG0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hw_config0::R`](R) reader structure"] +impl crate::Readable for HW_CONFIG0_SPEC {} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/hw_direction.rs b/crates/bcm2711-lpa/src/usb_otg_global/hw_direction.rs index 1ca29d0..3545475 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/hw_direction.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/hw_direction.rs @@ -1,20 +1,7 @@ #[doc = "Register `HW_DIRECTION` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DIRECTION[0-15]` reader - Direction %s"] -pub type DIRECTION_R = crate::FieldReader; +pub type DIRECTION_R = crate::FieldReader; #[doc = "Direction %s"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -32,10 +19,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for DIRECTION_A { + type Ux = u8; +} impl DIRECTION_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(DIRECTION_A::BIDIR), 1 => Some(DIRECTION_A::IN), @@ -43,17 +33,17 @@ impl DIRECTION_R { _ => None, } } - #[doc = "Checks if the value of the field is `BIDIR`"] + #[doc = "`0`"] #[inline(always)] pub fn is_bidir(&self) -> bool { *self == DIRECTION_A::BIDIR } - #[doc = "Checks if the value of the field is `IN`"] + #[doc = "`1`"] #[inline(always)] pub fn is_in(&self) -> bool { *self == DIRECTION_A::IN } - #[doc = "Checks if the value of the field is `OUT`"] + #[doc = "`10`"] #[inline(always)] pub fn is_out(&self) -> bool { *self == DIRECTION_A::OUT @@ -146,12 +136,55 @@ impl R { DIRECTION_R::new(((self.bits >> 30) & 3) as u8) } } -#[doc = "Direction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hw_direction](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HW_DIRECTION") + .field("direction0", &format_args!("{}", self.direction0().bits())) + .field("direction1", &format_args!("{}", self.direction1().bits())) + .field("direction2", &format_args!("{}", self.direction2().bits())) + .field("direction3", &format_args!("{}", self.direction3().bits())) + .field("direction4", &format_args!("{}", self.direction4().bits())) + .field("direction5", &format_args!("{}", self.direction5().bits())) + .field("direction6", &format_args!("{}", self.direction6().bits())) + .field("direction7", &format_args!("{}", self.direction7().bits())) + .field("direction8", &format_args!("{}", self.direction8().bits())) + .field("direction9", &format_args!("{}", self.direction9().bits())) + .field( + "direction10", + &format_args!("{}", self.direction10().bits()), + ) + .field( + "direction11", + &format_args!("{}", self.direction11().bits()), + ) + .field( + "direction12", + &format_args!("{}", self.direction12().bits()), + ) + .field( + "direction13", + &format_args!("{}", self.direction13().bits()), + ) + .field( + "direction14", + &format_args!("{}", self.direction14().bits()), + ) + .field( + "direction15", + &format_args!("{}", self.direction15().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_direction::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HW_DIRECTION_SPEC; impl crate::RegisterSpec for HW_DIRECTION_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hw_direction::R](R) reader structure"] -impl crate::Readable for HW_DIRECTION_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hw_direction::R`](R) reader structure"] +impl crate::Readable for HW_DIRECTION_SPEC {} diff --git a/crates/bcm2711-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs b/crates/bcm2711-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs index 8734146..73658ab 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs @@ -1,49 +1,15 @@ #[doc = "Register `TX0FSIZ_Peripheral` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TX0FSIZ_Peripheral` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TX0FSA` reader - Endpoint 0 transmit RAM start address"] -pub type TX0FSA_R = crate::FieldReader; +pub type TX0FSA_R = crate::FieldReader; #[doc = "Field `TX0FSA` writer - Endpoint 0 transmit RAM start address"] -pub type TX0FSA_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, TX0FSIZ_PERIPHERAL_SPEC, u16, u16, 16, O>; +pub type TX0FSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `TX0FD` reader - Endpoint 0 TxFIFO depth"] -pub type TX0FD_R = crate::FieldReader; +pub type TX0FD_R = crate::FieldReader; #[doc = "Field `TX0FD` writer - Endpoint 0 TxFIFO depth"] -pub type TX0FD_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, TX0FSIZ_PERIPHERAL_SPEC, u16, u16, 16, O>; +pub type TX0FD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Endpoint 0 transmit RAM start address"] #[inline(always)] @@ -56,38 +22,52 @@ impl R { TX0FD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX0FSIZ_Peripheral") + .field("tx0fsa", &format_args!("{}", self.tx0fsa().bits())) + .field("tx0fd", &format_args!("{}", self.tx0fd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Endpoint 0 transmit RAM start address"] #[inline(always)] #[must_use] - pub fn tx0fsa(&mut self) -> TX0FSA_W<0> { + pub fn tx0fsa(&mut self) -> TX0FSA_W { TX0FSA_W::new(self) } #[doc = "Bits 16:31 - Endpoint 0 TxFIFO depth"] #[inline(always)] #[must_use] - pub fn tx0fd(&mut self) -> TX0FD_W<16> { + pub fn tx0fd(&mut self) -> TX0FD_W { TX0FD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Endpoint 0 transmit FIFO size (peripheral mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx0fsiz_peripheral](index.html) module"] +#[doc = "Endpoint 0 transmit FIFO size (peripheral mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx0fsiz_peripheral::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx0fsiz_peripheral::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TX0FSIZ_PERIPHERAL_SPEC; impl crate::RegisterSpec for TX0FSIZ_PERIPHERAL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tx0fsiz_peripheral::R](R) reader structure"] -impl crate::Readable for TX0FSIZ_PERIPHERAL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tx0fsiz_peripheral::W](W) writer structure"] +#[doc = "`read()` method returns [`tx0fsiz_peripheral::R`](R) reader structure"] +impl crate::Readable for TX0FSIZ_PERIPHERAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx0fsiz_peripheral::W`](W) writer structure"] impl crate::Writable for TX0FSIZ_PERIPHERAL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_global/vid.rs b/crates/bcm2711-lpa/src/usb_otg_global/vid.rs index ae468f7..732dd16 100644 --- a/crates/bcm2711-lpa/src/usb_otg_global/vid.rs +++ b/crates/bcm2711-lpa/src/usb_otg_global/vid.rs @@ -1,24 +1,19 @@ #[doc = "Register `VID` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } -#[doc = "OTG_HS vendor ID register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vid](index.html) module"] +#[doc = "OTG_HS vendor ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct VID_SPEC; impl crate::RegisterSpec for VID_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [vid::R](R) reader structure"] -impl crate::Readable for VID_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`vid::R`](R) reader structure"] +impl crate::Readable for VID_SPEC {} diff --git a/crates/bcm2711-lpa/src/usb_otg_host.rs b/crates/bcm2711-lpa/src/usb_otg_host.rs index c2b6fb8..f40a06f 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - OTG_HS host configuration register"] pub hcfg: HCFG, @@ -54,31 +55,38 @@ pub struct RegisterBlock { #[doc = "0x260..0x278 - Host channel %s"] pub host_channel11: HOST_CHANNEL, } -#[doc = "HCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "HCFG (rw) register accessor: OTG_HS host configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcfg`] +module"] pub type HCFG = crate::Reg; #[doc = "OTG_HS host configuration register"] pub mod hcfg; -#[doc = "HFIR (rw) register accessor: an alias for `Reg`"] +#[doc = "HFIR (rw) register accessor: OTG_HS Host frame interval register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hfir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hfir`] +module"] pub type HFIR = crate::Reg; #[doc = "OTG_HS Host frame interval register"] pub mod hfir; -#[doc = "HFNUM (r) register accessor: an alias for `Reg`"] +#[doc = "HFNUM (r) register accessor: OTG_HS host frame number/frame time remaining register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfnum::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hfnum`] +module"] pub type HFNUM = crate::Reg; #[doc = "OTG_HS host frame number/frame time remaining register"] pub mod hfnum; -#[doc = "HPTXSTS (rw) register accessor: an alias for `Reg`"] +#[doc = "HPTXSTS (rw) register accessor: Host periodic transmit FIFO/queue status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxsts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hptxsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hptxsts`] +module"] pub type HPTXSTS = crate::Reg; #[doc = "Host periodic transmit FIFO/queue status register"] pub mod hptxsts; -#[doc = "HAINT (r) register accessor: an alias for `Reg`"] +#[doc = "HAINT (r) register accessor: OTG_HS Host all channels interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haint::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@haint`] +module"] pub type HAINT = crate::Reg; #[doc = "OTG_HS Host all channels interrupt register"] pub mod haint; -#[doc = "HAINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "HAINTMSK (rw) register accessor: OTG_HS host all channels interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`haintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@haintmsk`] +module"] pub type HAINTMSK = crate::Reg; #[doc = "OTG_HS host all channels interrupt mask register"] pub mod haintmsk; -#[doc = "HPRT (rw) register accessor: an alias for `Reg`"] +#[doc = "HPRT (rw) register accessor: OTG_HS host port control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hprt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hprt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hprt`] +module"] pub type HPRT = crate::Reg; #[doc = "OTG_HS host port control and status register"] pub mod hprt; diff --git a/crates/bcm2711-lpa/src/usb_otg_host/haint.rs b/crates/bcm2711-lpa/src/usb_otg_host/haint.rs index 16455f3..fd11584 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/haint.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/haint.rs @@ -1,20 +1,7 @@ #[doc = "Register `HAINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `HAINT` reader - Channel interrupts"] -pub type HAINT_R = crate::FieldReader; +pub type HAINT_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - Channel interrupts"] #[inline(always)] @@ -22,15 +9,25 @@ impl R { HAINT_R::new((self.bits & 0xffff) as u16) } } -#[doc = "OTG_HS Host all channels interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haint](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HAINT") + .field("haint", &format_args!("{}", self.haint().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS Host all channels interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haint::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HAINT_SPEC; impl crate::RegisterSpec for HAINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [haint::R](R) reader structure"] -impl crate::Readable for HAINT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`haint::R`](R) reader structure"] +impl crate::Readable for HAINT_SPEC {} #[doc = "`reset()` method sets HAINT to value 0"] impl crate::Resettable for HAINT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2711-lpa/src/usb_otg_host/haintmsk.rs b/crates/bcm2711-lpa/src/usb_otg_host/haintmsk.rs index 69df5e9..f820459 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/haintmsk.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/haintmsk.rs @@ -1,43 +1,11 @@ #[doc = "Register `HAINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HAINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HAINTM` reader - Channel interrupt mask"] -pub type HAINTM_R = crate::FieldReader; +pub type HAINTM_R = crate::FieldReader; #[doc = "Field `HAINTM` writer - Channel interrupt mask"] -pub type HAINTM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HAINTMSK_SPEC, u16, u16, 16, O>; +pub type HAINTM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Channel interrupt mask"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { HAINTM_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HAINTMSK") + .field("haintm", &format_args!("{}", self.haintm().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Channel interrupt mask"] #[inline(always)] #[must_use] - pub fn haintm(&mut self) -> HAINTM_W<0> { + pub fn haintm(&mut self) -> HAINTM_W { HAINTM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS host all channels interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haintmsk](index.html) module"] +#[doc = "OTG_HS host all channels interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`haintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HAINTMSK_SPEC; impl crate::RegisterSpec for HAINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [haintmsk::R](R) reader structure"] -impl crate::Readable for HAINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [haintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`haintmsk::R`](R) reader structure"] +impl crate::Readable for HAINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`haintmsk::W`](W) writer structure"] impl crate::Writable for HAINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_host/hcfg.rs b/crates/bcm2711-lpa/src/usb_otg_host/hcfg.rs index 17f4b01..af6795d 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/hcfg.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/hcfg.rs @@ -1,45 +1,13 @@ #[doc = "Register `HCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSLSPCS` reader - FS/LS PHY clock select"] -pub type FSLSPCS_R = crate::FieldReader; +pub type FSLSPCS_R = crate::FieldReader; #[doc = "Field `FSLSPCS` writer - FS/LS PHY clock select"] -pub type FSLSPCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCFG_SPEC, u8, u8, 2, O>; +pub type FSLSPCS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `FSLSS` reader - FS- and LS-only support"] -pub type FSLSS_R = crate::BitReader; +pub type FSLSS_R = crate::BitReader; impl R { #[doc = "Bits 0:1 - FS/LS PHY clock select"] #[inline(always)] @@ -52,32 +20,46 @@ impl R { FSLSS_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCFG") + .field("fslspcs", &format_args!("{}", self.fslspcs().bits())) + .field("fslss", &format_args!("{}", self.fslss().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - FS/LS PHY clock select"] #[inline(always)] #[must_use] - pub fn fslspcs(&mut self) -> FSLSPCS_W<0> { + pub fn fslspcs(&mut self) -> FSLSPCS_W { FSLSPCS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS host configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcfg](index.html) module"] +#[doc = "OTG_HS host configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCFG_SPEC; impl crate::RegisterSpec for HCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcfg::R](R) reader structure"] -impl crate::Readable for HCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`hcfg::R`](R) reader structure"] +impl crate::Readable for HCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcfg::W`](W) writer structure"] impl crate::Writable for HCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_host/hfir.rs b/crates/bcm2711-lpa/src/usb_otg_host/hfir.rs index 9182ff2..d373916 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/hfir.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/hfir.rs @@ -1,43 +1,11 @@ #[doc = "Register `HFIR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HFIR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FRIVL` reader - Frame interval"] -pub type FRIVL_R = crate::FieldReader; +pub type FRIVL_R = crate::FieldReader; #[doc = "Field `FRIVL` writer - Frame interval"] -pub type FRIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HFIR_SPEC, u16, u16, 16, O>; +pub type FRIVL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Frame interval"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { FRIVL_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HFIR") + .field("frivl", &format_args!("{}", self.frivl().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Frame interval"] #[inline(always)] #[must_use] - pub fn frivl(&mut self) -> FRIVL_W<0> { + pub fn frivl(&mut self) -> FRIVL_W { FRIVL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS Host frame interval register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfir](index.html) module"] +#[doc = "OTG_HS Host frame interval register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hfir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HFIR_SPEC; impl crate::RegisterSpec for HFIR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hfir::R](R) reader structure"] -impl crate::Readable for HFIR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hfir::W](W) writer structure"] +#[doc = "`read()` method returns [`hfir::R`](R) reader structure"] +impl crate::Readable for HFIR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hfir::W`](W) writer structure"] impl crate::Writable for HFIR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_host/hfnum.rs b/crates/bcm2711-lpa/src/usb_otg_host/hfnum.rs index 0df982a..5bb48e9 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/hfnum.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/hfnum.rs @@ -1,22 +1,9 @@ #[doc = "Register `HFNUM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FRNUM` reader - Frame number"] -pub type FRNUM_R = crate::FieldReader; +pub type FRNUM_R = crate::FieldReader; #[doc = "Field `FTREM` reader - Frame time remaining"] -pub type FTREM_R = crate::FieldReader; +pub type FTREM_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - Frame number"] #[inline(always)] @@ -29,15 +16,26 @@ impl R { FTREM_R::new(((self.bits >> 16) & 0xffff) as u16) } } -#[doc = "OTG_HS host frame number/frame time remaining register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfnum](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HFNUM") + .field("frnum", &format_args!("{}", self.frnum().bits())) + .field("ftrem", &format_args!("{}", self.ftrem().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS host frame number/frame time remaining register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfnum::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HFNUM_SPEC; impl crate::RegisterSpec for HFNUM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hfnum::R](R) reader structure"] -impl crate::Readable for HFNUM_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hfnum::R`](R) reader structure"] +impl crate::Readable for HFNUM_SPEC {} #[doc = "`reset()` method sets HFNUM to value 0x3fff"] impl crate::Resettable for HFNUM_SPEC { const RESET_VALUE: Self::Ux = 0x3fff; diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel.rs index ee4a815..54d36d3 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/host_channel.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct HOST_CHANNEL { #[doc = "0x00 - Characteristics register"] pub hcchar: HCCHAR, @@ -14,27 +15,33 @@ pub struct HOST_CHANNEL { #[doc = "0x14 - DMA address"] pub hcdma: HCDMA, } -#[doc = "HCCHAR (rw) register accessor: an alias for `Reg`"] +#[doc = "HCCHAR (rw) register accessor: Characteristics register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcchar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcchar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcchar`] +module"] pub type HCCHAR = crate::Reg; #[doc = "Characteristics register"] pub mod hcchar; -#[doc = "HCSPLT (rw) register accessor: an alias for `Reg`"] +#[doc = "HCSPLT (rw) register accessor: Split control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcsplt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcsplt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcsplt`] +module"] pub type HCSPLT = crate::Reg; #[doc = "Split control register"] pub mod hcsplt; -#[doc = "HCINT (rw) register accessor: an alias for `Reg`"] +#[doc = "HCINT (rw) register accessor: Interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcint`] +module"] pub type HCINT = crate::Reg; #[doc = "Interrupt register"] pub mod hcint; -#[doc = "HCINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "HCINTMSK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcintmsk`] +module"] pub type HCINTMSK = crate::Reg; #[doc = "Interrupt mask"] pub mod hcintmsk; -#[doc = "HCTSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "HCTSIZ (rw) register accessor: Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hctsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hctsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hctsiz`] +module"] pub type HCTSIZ = crate::Reg; #[doc = "Transfer size"] pub mod hctsiz; -#[doc = "HCDMA (rw) register accessor: an alias for `Reg`"] +#[doc = "HCDMA (rw) register accessor: DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcdma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcdma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcdma`] +module"] pub type HCDMA = crate::Reg; #[doc = "DMA address"] pub mod hcdma; diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcchar.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcchar.rs index d73f560..4bc5c53 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcchar.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcchar.rs @@ -1,79 +1,47 @@ #[doc = "Register `HCCHAR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCCHAR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MPSIZ` reader - Maximum packet size"] -pub type MPSIZ_R = crate::FieldReader; +pub type MPSIZ_R = crate::FieldReader; #[doc = "Field `MPSIZ` writer - Maximum packet size"] -pub type MPSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u16, u16, 11, O>; +pub type MPSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 11, O, u16>; #[doc = "Field `EPNUM` reader - Endpoint number"] -pub type EPNUM_R = crate::FieldReader; +pub type EPNUM_R = crate::FieldReader; #[doc = "Field `EPNUM` writer - Endpoint number"] -pub type EPNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 4, O>; +pub type EPNUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `EPDIR` reader - Endpoint direction"] -pub type EPDIR_R = crate::BitReader; +pub type EPDIR_R = crate::BitReader; #[doc = "Field `EPDIR` writer - Endpoint direction"] -pub type EPDIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type EPDIR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LSDEV` reader - Low-speed device"] -pub type LSDEV_R = crate::BitReader; +pub type LSDEV_R = crate::BitReader; #[doc = "Field `LSDEV` writer - Low-speed device"] -pub type LSDEV_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type LSDEV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPTYP` reader - Endpoint type"] -pub type EPTYP_R = crate::FieldReader; +pub type EPTYP_R = crate::FieldReader; #[doc = "Field `EPTYP` writer - Endpoint type"] -pub type EPTYP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 2, O>; +pub type EPTYP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `MC` reader - Multi Count (MC) / Error Count (EC)"] -pub type MC_R = crate::FieldReader; +pub type MC_R = crate::FieldReader; #[doc = "Field `MC` writer - Multi Count (MC) / Error Count (EC)"] -pub type MC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 2, O>; +pub type MC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `DAD` reader - Device address"] -pub type DAD_R = crate::FieldReader; +pub type DAD_R = crate::FieldReader; #[doc = "Field `DAD` writer - Device address"] -pub type DAD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 7, O>; +pub type DAD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `ODDFRM` reader - Odd frame"] -pub type ODDFRM_R = crate::BitReader; +pub type ODDFRM_R = crate::BitReader; #[doc = "Field `ODDFRM` writer - Odd frame"] -pub type ODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type ODDFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHDIS` reader - Channel disable"] -pub type CHDIS_R = crate::BitReader; +pub type CHDIS_R = crate::BitReader; #[doc = "Field `CHDIS` writer - Channel disable"] -pub type CHDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type CHDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHENA` reader - Channel enable"] -pub type CHENA_R = crate::BitReader; +pub type CHENA_R = crate::BitReader; #[doc = "Field `CHENA` writer - Channel enable"] -pub type CHENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type CHENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] @@ -126,86 +94,108 @@ impl R { CHENA_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCCHAR") + .field("mpsiz", &format_args!("{}", self.mpsiz().bits())) + .field("epnum", &format_args!("{}", self.epnum().bits())) + .field("epdir", &format_args!("{}", self.epdir().bit())) + .field("lsdev", &format_args!("{}", self.lsdev().bit())) + .field("eptyp", &format_args!("{}", self.eptyp().bits())) + .field("mc", &format_args!("{}", self.mc().bits())) + .field("dad", &format_args!("{}", self.dad().bits())) + .field("oddfrm", &format_args!("{}", self.oddfrm().bit())) + .field("chdis", &format_args!("{}", self.chdis().bit())) + .field("chena", &format_args!("{}", self.chena().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] #[must_use] - pub fn mpsiz(&mut self) -> MPSIZ_W<0> { + pub fn mpsiz(&mut self) -> MPSIZ_W { MPSIZ_W::new(self) } #[doc = "Bits 11:14 - Endpoint number"] #[inline(always)] #[must_use] - pub fn epnum(&mut self) -> EPNUM_W<11> { + pub fn epnum(&mut self) -> EPNUM_W { EPNUM_W::new(self) } #[doc = "Bit 15 - Endpoint direction"] #[inline(always)] #[must_use] - pub fn epdir(&mut self) -> EPDIR_W<15> { + pub fn epdir(&mut self) -> EPDIR_W { EPDIR_W::new(self) } #[doc = "Bit 17 - Low-speed device"] #[inline(always)] #[must_use] - pub fn lsdev(&mut self) -> LSDEV_W<17> { + pub fn lsdev(&mut self) -> LSDEV_W { LSDEV_W::new(self) } #[doc = "Bits 18:19 - Endpoint type"] #[inline(always)] #[must_use] - pub fn eptyp(&mut self) -> EPTYP_W<18> { + pub fn eptyp(&mut self) -> EPTYP_W { EPTYP_W::new(self) } #[doc = "Bits 20:21 - Multi Count (MC) / Error Count (EC)"] #[inline(always)] #[must_use] - pub fn mc(&mut self) -> MC_W<20> { + pub fn mc(&mut self) -> MC_W { MC_W::new(self) } #[doc = "Bits 22:28 - Device address"] #[inline(always)] #[must_use] - pub fn dad(&mut self) -> DAD_W<22> { + pub fn dad(&mut self) -> DAD_W { DAD_W::new(self) } #[doc = "Bit 29 - Odd frame"] #[inline(always)] #[must_use] - pub fn oddfrm(&mut self) -> ODDFRM_W<29> { + pub fn oddfrm(&mut self) -> ODDFRM_W { ODDFRM_W::new(self) } #[doc = "Bit 30 - Channel disable"] #[inline(always)] #[must_use] - pub fn chdis(&mut self) -> CHDIS_W<30> { + pub fn chdis(&mut self) -> CHDIS_W { CHDIS_W::new(self) } #[doc = "Bit 31 - Channel enable"] #[inline(always)] #[must_use] - pub fn chena(&mut self) -> CHENA_W<31> { + pub fn chena(&mut self) -> CHENA_W { CHENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Characteristics register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcchar](index.html) module"] +#[doc = "Characteristics register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcchar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcchar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCCHAR_SPEC; impl crate::RegisterSpec for HCCHAR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcchar::R](R) reader structure"] -impl crate::Readable for HCCHAR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcchar::W](W) writer structure"] +#[doc = "`read()` method returns [`hcchar::R`](R) reader structure"] +impl crate::Readable for HCCHAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcchar::W`](W) writer structure"] impl crate::Writable for HCCHAR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcdma.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcdma.rs index bfcef2a..49ce1a2 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcdma.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcdma.rs @@ -1,43 +1,11 @@ #[doc = "Register `HCDMA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCDMA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMAADDR` reader - DMA address"] -pub type DMAADDR_R = crate::FieldReader; +pub type DMAADDR_R = crate::FieldReader; #[doc = "Field `DMAADDR` writer - DMA address"] -pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCDMA_SPEC, u32, u32, 32, O>; +pub type DMAADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DMAADDR_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCDMA") + .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] #[must_use] - pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + pub fn dmaaddr(&mut self) -> DMAADDR_W { DMAADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcdma](index.html) module"] +#[doc = "DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcdma::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcdma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCDMA_SPEC; impl crate::RegisterSpec for HCDMA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcdma::R](R) reader structure"] -impl crate::Readable for HCDMA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcdma::W](W) writer structure"] +#[doc = "`read()` method returns [`hcdma::R`](R) reader structure"] +impl crate::Readable for HCDMA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcdma::W`](W) writer structure"] impl crate::Writable for HCDMA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcint.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcint.rs index a8ef9ea..0fd949e 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcint.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcint.rs @@ -1,83 +1,51 @@ #[doc = "Register `HCINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRC` reader - Transfer completed"] -pub type XFRC_R = crate::BitReader; +pub type XFRC_R = crate::BitReader; #[doc = "Field `XFRC` writer - Transfer completed"] -pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type XFRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHH` reader - Channel halted"] -pub type CHH_R = crate::BitReader; +pub type CHH_R = crate::BitReader; #[doc = "Field `CHH` writer - Channel halted"] -pub type CHH_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type CHH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AHBERR` reader - AHB error"] -pub type AHBERR_R = crate::BitReader; +pub type AHBERR_R = crate::BitReader; #[doc = "Field `AHBERR` writer - AHB error"] -pub type AHBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type AHBERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALL` reader - STALL response received interrupt"] -pub type STALL_R = crate::BitReader; +pub type STALL_R = crate::BitReader; #[doc = "Field `STALL` writer - STALL response received interrupt"] -pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAK` reader - NAK response received interrupt"] -pub type NAK_R = crate::BitReader; +pub type NAK_R = crate::BitReader; #[doc = "Field `NAK` writer - NAK response received interrupt"] -pub type NAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type NAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACK` reader - ACK response received/transmitted interrupt"] -pub type ACK_R = crate::BitReader; +pub type ACK_R = crate::BitReader; #[doc = "Field `ACK` writer - ACK response received/transmitted interrupt"] -pub type ACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type ACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYET` reader - Response received interrupt"] -pub type NYET_R = crate::BitReader; +pub type NYET_R = crate::BitReader; #[doc = "Field `NYET` writer - Response received interrupt"] -pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type NYET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXERR` reader - Transaction error"] -pub type TXERR_R = crate::BitReader; +pub type TXERR_R = crate::BitReader; #[doc = "Field `TXERR` writer - Transaction error"] -pub type TXERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type TXERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BBERR` reader - Babble error"] -pub type BBERR_R = crate::BitReader; +pub type BBERR_R = crate::BitReader; #[doc = "Field `BBERR` writer - Babble error"] -pub type BBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type BBERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRMOR` reader - Frame overrun"] -pub type FRMOR_R = crate::BitReader; +pub type FRMOR_R = crate::BitReader; #[doc = "Field `FRMOR` writer - Frame overrun"] -pub type FRMOR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type FRMOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTERR` reader - Data toggle error"] -pub type DTERR_R = crate::BitReader; +pub type DTERR_R = crate::BitReader; #[doc = "Field `DTERR` writer - Data toggle error"] -pub type DTERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type DTERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed"] #[inline(always)] @@ -135,92 +103,115 @@ impl R { DTERR_R::new(((self.bits >> 10) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCINT") + .field("xfrc", &format_args!("{}", self.xfrc().bit())) + .field("chh", &format_args!("{}", self.chh().bit())) + .field("ahberr", &format_args!("{}", self.ahberr().bit())) + .field("stall", &format_args!("{}", self.stall().bit())) + .field("nak", &format_args!("{}", self.nak().bit())) + .field("ack", &format_args!("{}", self.ack().bit())) + .field("nyet", &format_args!("{}", self.nyet().bit())) + .field("txerr", &format_args!("{}", self.txerr().bit())) + .field("bberr", &format_args!("{}", self.bberr().bit())) + .field("frmor", &format_args!("{}", self.frmor().bit())) + .field("dterr", &format_args!("{}", self.dterr().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed"] #[inline(always)] #[must_use] - pub fn xfrc(&mut self) -> XFRC_W<0> { + pub fn xfrc(&mut self) -> XFRC_W { XFRC_W::new(self) } #[doc = "Bit 1 - Channel halted"] #[inline(always)] #[must_use] - pub fn chh(&mut self) -> CHH_W<1> { + pub fn chh(&mut self) -> CHH_W { CHH_W::new(self) } #[doc = "Bit 2 - AHB error"] #[inline(always)] #[must_use] - pub fn ahberr(&mut self) -> AHBERR_W<2> { + pub fn ahberr(&mut self) -> AHBERR_W { AHBERR_W::new(self) } #[doc = "Bit 3 - STALL response received interrupt"] #[inline(always)] #[must_use] - pub fn stall(&mut self) -> STALL_W<3> { + pub fn stall(&mut self) -> STALL_W { STALL_W::new(self) } #[doc = "Bit 4 - NAK response received interrupt"] #[inline(always)] #[must_use] - pub fn nak(&mut self) -> NAK_W<4> { + pub fn nak(&mut self) -> NAK_W { NAK_W::new(self) } #[doc = "Bit 5 - ACK response received/transmitted interrupt"] #[inline(always)] #[must_use] - pub fn ack(&mut self) -> ACK_W<5> { + pub fn ack(&mut self) -> ACK_W { ACK_W::new(self) } #[doc = "Bit 6 - Response received interrupt"] #[inline(always)] #[must_use] - pub fn nyet(&mut self) -> NYET_W<6> { + pub fn nyet(&mut self) -> NYET_W { NYET_W::new(self) } #[doc = "Bit 7 - Transaction error"] #[inline(always)] #[must_use] - pub fn txerr(&mut self) -> TXERR_W<7> { + pub fn txerr(&mut self) -> TXERR_W { TXERR_W::new(self) } #[doc = "Bit 8 - Babble error"] #[inline(always)] #[must_use] - pub fn bberr(&mut self) -> BBERR_W<8> { + pub fn bberr(&mut self) -> BBERR_W { BBERR_W::new(self) } #[doc = "Bit 9 - Frame overrun"] #[inline(always)] #[must_use] - pub fn frmor(&mut self) -> FRMOR_W<9> { + pub fn frmor(&mut self) -> FRMOR_W { FRMOR_W::new(self) } #[doc = "Bit 10 - Data toggle error"] #[inline(always)] #[must_use] - pub fn dterr(&mut self) -> DTERR_W<10> { + pub fn dterr(&mut self) -> DTERR_W { DTERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcint](index.html) module"] +#[doc = "Interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCINT_SPEC; impl crate::RegisterSpec for HCINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcint::R](R) reader structure"] -impl crate::Readable for HCINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcint::W](W) writer structure"] +#[doc = "`read()` method returns [`hcint::R`](R) reader structure"] +impl crate::Readable for HCINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcint::W`](W) writer structure"] impl crate::Writable for HCINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcintmsk.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcintmsk.rs index e158cb4..03aa41c 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcintmsk.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcintmsk.rs @@ -1,83 +1,51 @@ #[doc = "Register `HCINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHHM` reader - Channel halted mask"] -pub type CHHM_R = crate::BitReader; +pub type CHHM_R = crate::BitReader; #[doc = "Field `CHHM` writer - Channel halted mask"] -pub type CHHM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type CHHM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AHBERR` reader - AHB error"] -pub type AHBERR_R = crate::BitReader; +pub type AHBERR_R = crate::BitReader; #[doc = "Field `AHBERR` writer - AHB error"] -pub type AHBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type AHBERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLM` reader - STALL response received interrupt mask"] -pub type STALLM_R = crate::BitReader; +pub type STALLM_R = crate::BitReader; #[doc = "Field `STALLM` writer - STALL response received interrupt mask"] -pub type STALLM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type STALLM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKM` reader - NAK response received interrupt mask"] -pub type NAKM_R = crate::BitReader; +pub type NAKM_R = crate::BitReader; #[doc = "Field `NAKM` writer - NAK response received interrupt mask"] -pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type NAKM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACKM` reader - ACK response received/transmitted interrupt mask"] -pub type ACKM_R = crate::BitReader; +pub type ACKM_R = crate::BitReader; #[doc = "Field `ACKM` writer - ACK response received/transmitted interrupt mask"] -pub type ACKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type ACKM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYET` reader - response received interrupt mask"] -pub type NYET_R = crate::BitReader; +pub type NYET_R = crate::BitReader; #[doc = "Field `NYET` writer - response received interrupt mask"] -pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type NYET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXERRM` reader - Transaction error mask"] -pub type TXERRM_R = crate::BitReader; +pub type TXERRM_R = crate::BitReader; #[doc = "Field `TXERRM` writer - Transaction error mask"] -pub type TXERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type TXERRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BBERRM` reader - Babble error mask"] -pub type BBERRM_R = crate::BitReader; +pub type BBERRM_R = crate::BitReader; #[doc = "Field `BBERRM` writer - Babble error mask"] -pub type BBERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type BBERRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRMORM` reader - Frame overrun mask"] -pub type FRMORM_R = crate::BitReader; +pub type FRMORM_R = crate::BitReader; #[doc = "Field `FRMORM` writer - Frame overrun mask"] -pub type FRMORM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type FRMORM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTERRM` reader - Data toggle error mask"] -pub type DTERRM_R = crate::BitReader; +pub type DTERRM_R = crate::BitReader; #[doc = "Field `DTERRM` writer - Data toggle error mask"] -pub type DTERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type DTERRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed mask"] #[inline(always)] @@ -135,92 +103,115 @@ impl R { DTERRM_R::new(((self.bits >> 10) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCINTMSK") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("chhm", &format_args!("{}", self.chhm().bit())) + .field("ahberr", &format_args!("{}", self.ahberr().bit())) + .field("stallm", &format_args!("{}", self.stallm().bit())) + .field("nakm", &format_args!("{}", self.nakm().bit())) + .field("ackm", &format_args!("{}", self.ackm().bit())) + .field("nyet", &format_args!("{}", self.nyet().bit())) + .field("txerrm", &format_args!("{}", self.txerrm().bit())) + .field("bberrm", &format_args!("{}", self.bberrm().bit())) + .field("frmorm", &format_args!("{}", self.frmorm().bit())) + .field("dterrm", &format_args!("{}", self.dterrm().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Channel halted mask"] #[inline(always)] #[must_use] - pub fn chhm(&mut self) -> CHHM_W<1> { + pub fn chhm(&mut self) -> CHHM_W { CHHM_W::new(self) } #[doc = "Bit 2 - AHB error"] #[inline(always)] #[must_use] - pub fn ahberr(&mut self) -> AHBERR_W<2> { + pub fn ahberr(&mut self) -> AHBERR_W { AHBERR_W::new(self) } #[doc = "Bit 3 - STALL response received interrupt mask"] #[inline(always)] #[must_use] - pub fn stallm(&mut self) -> STALLM_W<3> { + pub fn stallm(&mut self) -> STALLM_W { STALLM_W::new(self) } #[doc = "Bit 4 - NAK response received interrupt mask"] #[inline(always)] #[must_use] - pub fn nakm(&mut self) -> NAKM_W<4> { + pub fn nakm(&mut self) -> NAKM_W { NAKM_W::new(self) } #[doc = "Bit 5 - ACK response received/transmitted interrupt mask"] #[inline(always)] #[must_use] - pub fn ackm(&mut self) -> ACKM_W<5> { + pub fn ackm(&mut self) -> ACKM_W { ACKM_W::new(self) } #[doc = "Bit 6 - response received interrupt mask"] #[inline(always)] #[must_use] - pub fn nyet(&mut self) -> NYET_W<6> { + pub fn nyet(&mut self) -> NYET_W { NYET_W::new(self) } #[doc = "Bit 7 - Transaction error mask"] #[inline(always)] #[must_use] - pub fn txerrm(&mut self) -> TXERRM_W<7> { + pub fn txerrm(&mut self) -> TXERRM_W { TXERRM_W::new(self) } #[doc = "Bit 8 - Babble error mask"] #[inline(always)] #[must_use] - pub fn bberrm(&mut self) -> BBERRM_W<8> { + pub fn bberrm(&mut self) -> BBERRM_W { BBERRM_W::new(self) } #[doc = "Bit 9 - Frame overrun mask"] #[inline(always)] #[must_use] - pub fn frmorm(&mut self) -> FRMORM_W<9> { + pub fn frmorm(&mut self) -> FRMORM_W { FRMORM_W::new(self) } #[doc = "Bit 10 - Data toggle error mask"] #[inline(always)] #[must_use] - pub fn dterrm(&mut self) -> DTERRM_W<10> { + pub fn dterrm(&mut self) -> DTERRM_W { DTERRM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcintmsk](index.html) module"] +#[doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCINTMSK_SPEC; impl crate::RegisterSpec for HCINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcintmsk::R](R) reader structure"] -impl crate::Readable for HCINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`hcintmsk::R`](R) reader structure"] +impl crate::Readable for HCINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcintmsk::W`](W) writer structure"] impl crate::Writable for HCINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcsplt.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcsplt.rs index b20ca79..dfc4fa0 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcsplt.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hcsplt.rs @@ -1,59 +1,27 @@ #[doc = "Register `HCSPLT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCSPLT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PRTADDR` reader - Port address"] -pub type PRTADDR_R = crate::FieldReader; +pub type PRTADDR_R = crate::FieldReader; #[doc = "Field `PRTADDR` writer - Port address"] -pub type PRTADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 7, O>; +pub type PRTADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `HUBADDR` reader - Hub address"] -pub type HUBADDR_R = crate::FieldReader; +pub type HUBADDR_R = crate::FieldReader; #[doc = "Field `HUBADDR` writer - Hub address"] -pub type HUBADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 7, O>; +pub type HUBADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `XACTPOS` reader - XACTPOS"] -pub type XACTPOS_R = crate::FieldReader; +pub type XACTPOS_R = crate::FieldReader; #[doc = "Field `XACTPOS` writer - XACTPOS"] -pub type XACTPOS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 2, O>; +pub type XACTPOS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `COMPLSPLT` reader - Do complete split"] -pub type COMPLSPLT_R = crate::BitReader; +pub type COMPLSPLT_R = crate::BitReader; #[doc = "Field `COMPLSPLT` writer - Do complete split"] -pub type COMPLSPLT_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCSPLT_SPEC, bool, O>; +pub type COMPLSPLT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPLITEN` reader - Split enable"] -pub type SPLITEN_R = crate::BitReader; +pub type SPLITEN_R = crate::BitReader; #[doc = "Field `SPLITEN` writer - Split enable"] -pub type SPLITEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCSPLT_SPEC, bool, O>; +pub type SPLITEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - Port address"] #[inline(always)] @@ -81,56 +49,73 @@ impl R { SPLITEN_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCSPLT") + .field("prtaddr", &format_args!("{}", self.prtaddr().bits())) + .field("hubaddr", &format_args!("{}", self.hubaddr().bits())) + .field("xactpos", &format_args!("{}", self.xactpos().bits())) + .field("complsplt", &format_args!("{}", self.complsplt().bit())) + .field("spliten", &format_args!("{}", self.spliten().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - Port address"] #[inline(always)] #[must_use] - pub fn prtaddr(&mut self) -> PRTADDR_W<0> { + pub fn prtaddr(&mut self) -> PRTADDR_W { PRTADDR_W::new(self) } #[doc = "Bits 7:13 - Hub address"] #[inline(always)] #[must_use] - pub fn hubaddr(&mut self) -> HUBADDR_W<7> { + pub fn hubaddr(&mut self) -> HUBADDR_W { HUBADDR_W::new(self) } #[doc = "Bits 14:15 - XACTPOS"] #[inline(always)] #[must_use] - pub fn xactpos(&mut self) -> XACTPOS_W<14> { + pub fn xactpos(&mut self) -> XACTPOS_W { XACTPOS_W::new(self) } #[doc = "Bit 16 - Do complete split"] #[inline(always)] #[must_use] - pub fn complsplt(&mut self) -> COMPLSPLT_W<16> { + pub fn complsplt(&mut self) -> COMPLSPLT_W { COMPLSPLT_W::new(self) } #[doc = "Bit 31 - Split enable"] #[inline(always)] #[must_use] - pub fn spliten(&mut self) -> SPLITEN_W<31> { + pub fn spliten(&mut self) -> SPLITEN_W { SPLITEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Split control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcsplt](index.html) module"] +#[doc = "Split control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcsplt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcsplt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCSPLT_SPEC; impl crate::RegisterSpec for HCSPLT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcsplt::R](R) reader structure"] -impl crate::Readable for HCSPLT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcsplt::W](W) writer structure"] +#[doc = "`read()` method returns [`hcsplt::R`](R) reader structure"] +impl crate::Readable for HCSPLT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcsplt::W`](W) writer structure"] impl crate::Writable for HCSPLT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hctsiz.rs b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hctsiz.rs index a7361fd..ebfe51b 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hctsiz.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/host_channel/hctsiz.rs @@ -1,51 +1,19 @@ #[doc = "Register `HCTSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCTSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRSIZ` reader - Transfer size"] -pub type XFRSIZ_R = crate::FieldReader; +pub type XFRSIZ_R = crate::FieldReader; #[doc = "Field `XFRSIZ` writer - Transfer size"] -pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u32, u32, 19, O>; +pub type XFRSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 19, O, u32>; #[doc = "Field `PKTCNT` reader - Packet count"] -pub type PKTCNT_R = crate::FieldReader; +pub type PKTCNT_R = crate::FieldReader; #[doc = "Field `PKTCNT` writer - Packet count"] -pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u16, u16, 10, O>; +pub type PKTCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `DPID` writer - Data PID"] -pub type DPID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u8, u8, 2, O>; +pub type DPID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:18 - Transfer size"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { DPID_R::new(((self.bits >> 29) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCTSIZ") + .field("xfrsiz", &format_args!("{}", self.xfrsiz().bits())) + .field("pktcnt", &format_args!("{}", self.pktcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:18 - Transfer size"] #[inline(always)] #[must_use] - pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + pub fn xfrsiz(&mut self) -> XFRSIZ_W { XFRSIZ_W::new(self) } #[doc = "Bits 19:28 - Packet count"] #[inline(always)] #[must_use] - pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + pub fn pktcnt(&mut self) -> PKTCNT_W { PKTCNT_W::new(self) } #[doc = "Bits 29:30 - Data PID"] #[inline(always)] #[must_use] - pub fn dpid(&mut self) -> DPID_W<29> { + pub fn dpid(&mut self) -> DPID_W { DPID_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hctsiz](index.html) module"] +#[doc = "Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hctsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hctsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCTSIZ_SPEC; impl crate::RegisterSpec for HCTSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hctsiz::R](R) reader structure"] -impl crate::Readable for HCTSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hctsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`hctsiz::R`](R) reader structure"] +impl crate::Readable for HCTSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hctsiz::W`](W) writer structure"] impl crate::Writable for HCTSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_host/hprt.rs b/crates/bcm2711-lpa/src/usb_otg_host/hprt.rs index cb893f3..ca27b6f 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/hprt.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/hprt.rs @@ -1,83 +1,51 @@ #[doc = "Register `HPRT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HPRT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PCSTS` reader - Port connect status"] -pub type PCSTS_R = crate::BitReader; +pub type PCSTS_R = crate::BitReader; #[doc = "Field `PCDET` reader - Port connect detected"] -pub type PCDET_R = crate::BitReader; +pub type PCDET_R = crate::BitReader; #[doc = "Field `PCDET` writer - Port connect detected"] -pub type PCDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PCDET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PENA` reader - Port enable"] -pub type PENA_R = crate::BitReader; +pub type PENA_R = crate::BitReader; #[doc = "Field `PENA` writer - Port enable"] -pub type PENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PENCHNG` reader - Port enable/disable change"] -pub type PENCHNG_R = crate::BitReader; +pub type PENCHNG_R = crate::BitReader; #[doc = "Field `PENCHNG` writer - Port enable/disable change"] -pub type PENCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PENCHNG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POCA` reader - Port overcurrent active"] -pub type POCA_R = crate::BitReader; +pub type POCA_R = crate::BitReader; #[doc = "Field `POCCHNG` reader - Port overcurrent change"] -pub type POCCHNG_R = crate::BitReader; +pub type POCCHNG_R = crate::BitReader; #[doc = "Field `POCCHNG` writer - Port overcurrent change"] -pub type POCCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type POCCHNG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRES` reader - Port resume"] -pub type PRES_R = crate::BitReader; +pub type PRES_R = crate::BitReader; #[doc = "Field `PRES` writer - Port resume"] -pub type PRES_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PSUSP` reader - Port suspend"] -pub type PSUSP_R = crate::BitReader; +pub type PSUSP_R = crate::BitReader; #[doc = "Field `PSUSP` writer - Port suspend"] -pub type PSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRST` reader - Port reset"] -pub type PRST_R = crate::BitReader; +pub type PRST_R = crate::BitReader; #[doc = "Field `PRST` writer - Port reset"] -pub type PRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PLSTS` reader - Port line status"] -pub type PLSTS_R = crate::FieldReader; +pub type PLSTS_R = crate::FieldReader; #[doc = "Field `PPWR` reader - Port power"] -pub type PPWR_R = crate::BitReader; +pub type PPWR_R = crate::BitReader; #[doc = "Field `PPWR` writer - Port power"] -pub type PPWR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PPWR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTCTL` reader - Port test control"] -pub type PTCTL_R = crate::FieldReader; +pub type PTCTL_R = crate::FieldReader; #[doc = "Field `PTCTL` writer - Port test control"] -pub type PTCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPRT_SPEC, u8, u8, 4, O>; +pub type PTCTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `PSPD` reader - Port speed"] -pub type PSPD_R = crate::FieldReader; +pub type PSPD_R = crate::FieldReader; impl R { #[doc = "Bit 0 - Port connect status"] #[inline(always)] @@ -145,80 +113,105 @@ impl R { PSPD_R::new(((self.bits >> 17) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HPRT") + .field("pcsts", &format_args!("{}", self.pcsts().bit())) + .field("pcdet", &format_args!("{}", self.pcdet().bit())) + .field("pena", &format_args!("{}", self.pena().bit())) + .field("penchng", &format_args!("{}", self.penchng().bit())) + .field("poca", &format_args!("{}", self.poca().bit())) + .field("pocchng", &format_args!("{}", self.pocchng().bit())) + .field("pres", &format_args!("{}", self.pres().bit())) + .field("psusp", &format_args!("{}", self.psusp().bit())) + .field("prst", &format_args!("{}", self.prst().bit())) + .field("plsts", &format_args!("{}", self.plsts().bits())) + .field("ppwr", &format_args!("{}", self.ppwr().bit())) + .field("ptctl", &format_args!("{}", self.ptctl().bits())) + .field("pspd", &format_args!("{}", self.pspd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Port connect detected"] #[inline(always)] #[must_use] - pub fn pcdet(&mut self) -> PCDET_W<1> { + pub fn pcdet(&mut self) -> PCDET_W { PCDET_W::new(self) } #[doc = "Bit 2 - Port enable"] #[inline(always)] #[must_use] - pub fn pena(&mut self) -> PENA_W<2> { + pub fn pena(&mut self) -> PENA_W { PENA_W::new(self) } #[doc = "Bit 3 - Port enable/disable change"] #[inline(always)] #[must_use] - pub fn penchng(&mut self) -> PENCHNG_W<3> { + pub fn penchng(&mut self) -> PENCHNG_W { PENCHNG_W::new(self) } #[doc = "Bit 5 - Port overcurrent change"] #[inline(always)] #[must_use] - pub fn pocchng(&mut self) -> POCCHNG_W<5> { + pub fn pocchng(&mut self) -> POCCHNG_W { POCCHNG_W::new(self) } #[doc = "Bit 6 - Port resume"] #[inline(always)] #[must_use] - pub fn pres(&mut self) -> PRES_W<6> { + pub fn pres(&mut self) -> PRES_W { PRES_W::new(self) } #[doc = "Bit 7 - Port suspend"] #[inline(always)] #[must_use] - pub fn psusp(&mut self) -> PSUSP_W<7> { + pub fn psusp(&mut self) -> PSUSP_W { PSUSP_W::new(self) } #[doc = "Bit 8 - Port reset"] #[inline(always)] #[must_use] - pub fn prst(&mut self) -> PRST_W<8> { + pub fn prst(&mut self) -> PRST_W { PRST_W::new(self) } #[doc = "Bit 12 - Port power"] #[inline(always)] #[must_use] - pub fn ppwr(&mut self) -> PPWR_W<12> { + pub fn ppwr(&mut self) -> PPWR_W { PPWR_W::new(self) } #[doc = "Bits 13:16 - Port test control"] #[inline(always)] #[must_use] - pub fn ptctl(&mut self) -> PTCTL_W<13> { + pub fn ptctl(&mut self) -> PTCTL_W { PTCTL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS host port control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hprt](index.html) module"] +#[doc = "OTG_HS host port control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hprt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hprt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HPRT_SPEC; impl crate::RegisterSpec for HPRT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hprt::R](R) reader structure"] -impl crate::Readable for HPRT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hprt::W](W) writer structure"] +#[doc = "`read()` method returns [`hprt::R`](R) reader structure"] +impl crate::Readable for HPRT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hprt::W`](W) writer structure"] impl crate::Writable for HPRT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_host/hptxsts.rs b/crates/bcm2711-lpa/src/usb_otg_host/hptxsts.rs index 3cb5895..ffb1b12 100644 --- a/crates/bcm2711-lpa/src/usb_otg_host/hptxsts.rs +++ b/crates/bcm2711-lpa/src/usb_otg_host/hptxsts.rs @@ -1,47 +1,15 @@ #[doc = "Register `HPTXSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HPTXSTS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PTXFSAVL` reader - Periodic transmit data FIFO space available"] -pub type PTXFSAVL_R = crate::FieldReader; +pub type PTXFSAVL_R = crate::FieldReader; #[doc = "Field `PTXFSAVL` writer - Periodic transmit data FIFO space available"] -pub type PTXFSAVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXSTS_SPEC, u16, u16, 16, O>; +pub type PTXFSAVL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `PTXQSAV` reader - Periodic transmit request queue space available"] -pub type PTXQSAV_R = crate::FieldReader; +pub type PTXQSAV_R = crate::FieldReader; #[doc = "Field `PTXQTOP` reader - Top of the periodic transmit request queue"] -pub type PTXQTOP_R = crate::FieldReader; +pub type PTXQTOP_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - Periodic transmit data FIFO space available"] #[inline(always)] @@ -59,32 +27,47 @@ impl R { PTXQTOP_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HPTXSTS") + .field("ptxfsavl", &format_args!("{}", self.ptxfsavl().bits())) + .field("ptxqsav", &format_args!("{}", self.ptxqsav().bits())) + .field("ptxqtop", &format_args!("{}", self.ptxqtop().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Periodic transmit data FIFO space available"] #[inline(always)] #[must_use] - pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<0> { + pub fn ptxfsavl(&mut self) -> PTXFSAVL_W { PTXFSAVL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host periodic transmit FIFO/queue status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxsts](index.html) module"] +#[doc = "Host periodic transmit FIFO/queue status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxsts::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hptxsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HPTXSTS_SPEC; impl crate::RegisterSpec for HPTXSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hptxsts::R](R) reader structure"] -impl crate::Readable for HPTXSTS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hptxsts::W](W) writer structure"] +#[doc = "`read()` method returns [`hptxsts::R`](R) reader structure"] +impl crate::Readable for HPTXSTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hptxsts::W`](W) writer structure"] impl crate::Writable for HPTXSTS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/usb_otg_pwrclk.rs b/crates/bcm2711-lpa/src/usb_otg_pwrclk.rs index 67a9eb5..242f3b2 100644 --- a/crates/bcm2711-lpa/src/usb_otg_pwrclk.rs +++ b/crates/bcm2711-lpa/src/usb_otg_pwrclk.rs @@ -1,10 +1,12 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - power and clock gating control"] pub pcgcctl: PCGCCTL, } -#[doc = "PCGCCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "PCGCCTL (rw) register accessor: power and clock gating control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcgcctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcgcctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcgcctl`] +module"] pub type PCGCCTL = crate::Reg; #[doc = "power and clock gating control"] pub mod pcgcctl; diff --git a/crates/bcm2711-lpa/src/usb_otg_pwrclk/pcgcctl.rs b/crates/bcm2711-lpa/src/usb_otg_pwrclk/pcgcctl.rs index 061312d..97a2598 100644 --- a/crates/bcm2711-lpa/src/usb_otg_pwrclk/pcgcctl.rs +++ b/crates/bcm2711-lpa/src/usb_otg_pwrclk/pcgcctl.rs @@ -1,102 +1,67 @@ #[doc = "Register `PCGCCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PCGCCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `STPPCLK` reader - Stop PHY clock"] -pub type STPPCLK_R = crate::BitReader; +pub type STPPCLK_R = crate::BitReader; #[doc = "Field `STPPCLK` writer - Stop PHY clock"] -pub type STPPCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type STPPCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GATEHCLK` reader - Gate HCLK"] -pub type GATEHCLK_R = crate::BitReader; +pub type GATEHCLK_R = crate::BitReader; #[doc = "Field `GATEHCLK` writer - Gate HCLK"] -pub type GATEHCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type GATEHCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWRCLMP` reader - Power clamp"] -pub type PWRCLMP_R = crate::BitReader; +pub type PWRCLMP_R = crate::BitReader; #[doc = "Field `PWRCLMP` writer - Power clamp"] -pub type PWRCLMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type PWRCLMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTPDWNMODULE` reader - Power down modules"] -pub type RSTPDWNMODULE_R = crate::BitReader; +pub type RSTPDWNMODULE_R = crate::BitReader; #[doc = "Field `RSTPDWNMODULE` writer - Power down modules"] -pub type RSTPDWNMODULE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type RSTPDWNMODULE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PHYSUSP` reader - PHY Suspended"] -pub type PHYSUSP_R = crate::BitReader; +pub type PHYSUSP_R = crate::BitReader; #[doc = "Field `PHYSUSP` writer - PHY Suspended"] -pub type PHYSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type PHYSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE_L1GATING` reader - Enable sleep clock gating"] -pub type ENABLE_L1GATING_R = crate::BitReader; +pub type ENABLE_L1GATING_R = crate::BitReader; #[doc = "Field `ENABLE_L1GATING` writer - Enable sleep clock gating"] -pub type ENABLE_L1GATING_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type ENABLE_L1GATING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PHYSLEEP` reader - PHY is in sleep mode"] -pub type PHYSLEEP_R = crate::BitReader; +pub type PHYSLEEP_R = crate::BitReader; #[doc = "Field `PHYSLEEP` writer - PHY is in sleep mode"] -pub type PHYSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type PHYSLEEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEEPSLEEP` reader - PHY is in deep sleep"] -pub type DEEPSLEEP_R = crate::BitReader; +pub type DEEPSLEEP_R = crate::BitReader; #[doc = "Field `DEEPSLEEP` writer - PHY is in deep sleep"] -pub type DEEPSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type DEEPSLEEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESETAFTERSUSP` reader - Reset after suspend"] -pub type RESETAFTERSUSP_R = crate::BitReader; +pub type RESETAFTERSUSP_R = crate::BitReader; #[doc = "Field `RESETAFTERSUSP` writer - Reset after suspend"] -pub type RESETAFTERSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type RESETAFTERSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESTOREMODE` reader - Restore mode"] -pub type RESTOREMODE_R = crate::BitReader; +pub type RESTOREMODE_R = crate::BitReader; #[doc = "Field `RESTOREMODE` writer - Restore mode"] -pub type RESTOREMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type RESTOREMODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENEXTNDEDHIBER` reader - Enable extended hibernation"] -pub type ENEXTNDEDHIBER_R = crate::BitReader; +pub type ENEXTNDEDHIBER_R = crate::BitReader; #[doc = "Field `ENEXTNDEDHIBER` writer - Enable extended hibernation"] -pub type ENEXTNDEDHIBER_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type ENEXTNDEDHIBER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EXTNDEDHIBERNATIONCLAMP` reader - Extended hibernation clamp"] -pub type EXTNDEDHIBERNATIONCLAMP_R = crate::BitReader; +pub type EXTNDEDHIBERNATIONCLAMP_R = crate::BitReader; #[doc = "Field `EXTNDEDHIBERNATIONCLAMP` writer - Extended hibernation clamp"] -pub type EXTNDEDHIBERNATIONCLAMP_W<'a, const O: u8> = - crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type EXTNDEDHIBERNATIONCLAMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EXTNDEDHIBERNATIONSWITCH` reader - Extended hibernation switch"] -pub type EXTNDEDHIBERNATIONSWITCH_R = crate::BitReader; +pub type EXTNDEDHIBERNATIONSWITCH_R = crate::BitReader; #[doc = "Field `EXTNDEDHIBERNATIONSWITCH` writer - Extended hibernation switch"] -pub type EXTNDEDHIBERNATIONSWITCH_W<'a, const O: u8> = - crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type EXTNDEDHIBERNATIONSWITCH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ESSREGRESTORED` reader - Essential register values restored"] -pub type ESSREGRESTORED_R = crate::BitReader; +pub type ESSREGRESTORED_R = crate::BitReader; #[doc = "Field `ESSREGRESTORED` writer - Essential register values restored"] -pub type ESSREGRESTORED_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type ESSREGRESTORED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESTORE_VALUE` reader - Restore value"] -pub type RESTORE_VALUE_R = crate::FieldReader; +pub type RESTORE_VALUE_R = crate::FieldReader; #[doc = "Field `RESTORE_VALUE` writer - Restore value"] -pub type RESTORE_VALUE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, PCGCCTL_SPEC, u32, u32, 18, O>; +pub type RESTORE_VALUE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 18, O, u32>; impl R { #[doc = "Bit 0 - Stop PHY clock"] #[inline(always)] @@ -174,116 +139,167 @@ impl R { RESTORE_VALUE_R::new((self.bits >> 14) & 0x0003_ffff) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PCGCCTL") + .field("stppclk", &format_args!("{}", self.stppclk().bit())) + .field("gatehclk", &format_args!("{}", self.gatehclk().bit())) + .field("pwrclmp", &format_args!("{}", self.pwrclmp().bit())) + .field( + "rstpdwnmodule", + &format_args!("{}", self.rstpdwnmodule().bit()), + ) + .field("physusp", &format_args!("{}", self.physusp().bit())) + .field( + "enable_l1gating", + &format_args!("{}", self.enable_l1gating().bit()), + ) + .field("physleep", &format_args!("{}", self.physleep().bit())) + .field("deepsleep", &format_args!("{}", self.deepsleep().bit())) + .field( + "resetaftersusp", + &format_args!("{}", self.resetaftersusp().bit()), + ) + .field("restoremode", &format_args!("{}", self.restoremode().bit())) + .field( + "enextndedhiber", + &format_args!("{}", self.enextndedhiber().bit()), + ) + .field( + "extndedhibernationclamp", + &format_args!("{}", self.extndedhibernationclamp().bit()), + ) + .field( + "extndedhibernationswitch", + &format_args!("{}", self.extndedhibernationswitch().bit()), + ) + .field( + "essregrestored", + &format_args!("{}", self.essregrestored().bit()), + ) + .field( + "restore_value", + &format_args!("{}", self.restore_value().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Stop PHY clock"] #[inline(always)] #[must_use] - pub fn stppclk(&mut self) -> STPPCLK_W<0> { + pub fn stppclk(&mut self) -> STPPCLK_W { STPPCLK_W::new(self) } #[doc = "Bit 1 - Gate HCLK"] #[inline(always)] #[must_use] - pub fn gatehclk(&mut self) -> GATEHCLK_W<1> { + pub fn gatehclk(&mut self) -> GATEHCLK_W { GATEHCLK_W::new(self) } #[doc = "Bit 2 - Power clamp"] #[inline(always)] #[must_use] - pub fn pwrclmp(&mut self) -> PWRCLMP_W<2> { + pub fn pwrclmp(&mut self) -> PWRCLMP_W { PWRCLMP_W::new(self) } #[doc = "Bit 3 - Power down modules"] #[inline(always)] #[must_use] - pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W<3> { + pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W { RSTPDWNMODULE_W::new(self) } #[doc = "Bit 4 - PHY Suspended"] #[inline(always)] #[must_use] - pub fn physusp(&mut self) -> PHYSUSP_W<4> { + pub fn physusp(&mut self) -> PHYSUSP_W { PHYSUSP_W::new(self) } #[doc = "Bit 5 - Enable sleep clock gating"] #[inline(always)] #[must_use] - pub fn enable_l1gating(&mut self) -> ENABLE_L1GATING_W<5> { + pub fn enable_l1gating(&mut self) -> ENABLE_L1GATING_W { ENABLE_L1GATING_W::new(self) } #[doc = "Bit 6 - PHY is in sleep mode"] #[inline(always)] #[must_use] - pub fn physleep(&mut self) -> PHYSLEEP_W<6> { + pub fn physleep(&mut self) -> PHYSLEEP_W { PHYSLEEP_W::new(self) } #[doc = "Bit 7 - PHY is in deep sleep"] #[inline(always)] #[must_use] - pub fn deepsleep(&mut self) -> DEEPSLEEP_W<7> { + pub fn deepsleep(&mut self) -> DEEPSLEEP_W { DEEPSLEEP_W::new(self) } #[doc = "Bit 8 - Reset after suspend"] #[inline(always)] #[must_use] - pub fn resetaftersusp(&mut self) -> RESETAFTERSUSP_W<8> { + pub fn resetaftersusp(&mut self) -> RESETAFTERSUSP_W { RESETAFTERSUSP_W::new(self) } #[doc = "Bit 9 - Restore mode"] #[inline(always)] #[must_use] - pub fn restoremode(&mut self) -> RESTOREMODE_W<9> { + pub fn restoremode(&mut self) -> RESTOREMODE_W { RESTOREMODE_W::new(self) } #[doc = "Bit 10 - Enable extended hibernation"] #[inline(always)] #[must_use] - pub fn enextndedhiber(&mut self) -> ENEXTNDEDHIBER_W<10> { + pub fn enextndedhiber(&mut self) -> ENEXTNDEDHIBER_W { ENEXTNDEDHIBER_W::new(self) } #[doc = "Bit 11 - Extended hibernation clamp"] #[inline(always)] #[must_use] - pub fn extndedhibernationclamp(&mut self) -> EXTNDEDHIBERNATIONCLAMP_W<11> { + pub fn extndedhibernationclamp(&mut self) -> EXTNDEDHIBERNATIONCLAMP_W { EXTNDEDHIBERNATIONCLAMP_W::new(self) } #[doc = "Bit 12 - Extended hibernation switch"] #[inline(always)] #[must_use] - pub fn extndedhibernationswitch(&mut self) -> EXTNDEDHIBERNATIONSWITCH_W<12> { + pub fn extndedhibernationswitch(&mut self) -> EXTNDEDHIBERNATIONSWITCH_W { EXTNDEDHIBERNATIONSWITCH_W::new(self) } #[doc = "Bit 13 - Essential register values restored"] #[inline(always)] #[must_use] - pub fn essregrestored(&mut self) -> ESSREGRESTORED_W<13> { + pub fn essregrestored(&mut self) -> ESSREGRESTORED_W { ESSREGRESTORED_W::new(self) } #[doc = "Bits 14:31 - Restore value"] #[inline(always)] #[must_use] - pub fn restore_value(&mut self) -> RESTORE_VALUE_W<14> { + pub fn restore_value(&mut self) -> RESTORE_VALUE_W { RESTORE_VALUE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "power and clock gating control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcgcctl](index.html) module"] +#[doc = "power and clock gating control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcgcctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcgcctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCGCCTL_SPEC; impl crate::RegisterSpec for PCGCCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pcgcctl::R](R) reader structure"] -impl crate::Readable for PCGCCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [pcgcctl::W](W) writer structure"] +#[doc = "`read()` method returns [`pcgcctl::R`](R) reader structure"] +impl crate::Readable for PCGCCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pcgcctl::W`](W) writer structure"] impl crate::Writable for PCGCCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/vcmailbox.rs b/crates/bcm2711-lpa/src/vcmailbox.rs index 7490467..f3d9184 100644 --- a/crates/bcm2711-lpa/src/vcmailbox.rs +++ b/crates/bcm2711-lpa/src/vcmailbox.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Read messages from the VideoCore"] pub read: READ, @@ -24,43 +25,53 @@ pub struct RegisterBlock { #[doc = "0x3c - "] pub config1: CONFIG1, } -#[doc = "READ (r) register accessor: an alias for `Reg`"] +#[doc = "READ (r) register accessor: Read messages from the VideoCore\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`read::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@read`] +module"] pub type READ = crate::Reg; #[doc = "Read messages from the VideoCore"] pub mod read; -#[doc = "PEEK0 (rw) register accessor: an alias for `Reg`"] +#[doc = "PEEK0 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peek0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peek0`] +module"] pub type PEEK0 = crate::Reg; #[doc = ""] pub mod peek0; -#[doc = "SENDER0 (rw) register accessor: an alias for `Reg`"] +#[doc = "SENDER0 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sender0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sender0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sender0`] +module"] pub type SENDER0 = crate::Reg; #[doc = ""] pub mod sender0; -#[doc = "STATUS0 (r) register accessor: an alias for `Reg`"] +#[doc = "STATUS0 (r) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status0`] +module"] pub type STATUS0 = crate::Reg; #[doc = ""] pub mod status0; -#[doc = "CONFIG0 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONFIG0 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config0`] +module"] pub type CONFIG0 = crate::Reg; #[doc = ""] pub mod config0; -#[doc = "WRITE (w) register accessor: an alias for `Reg`"] +#[doc = "WRITE (w) register accessor: Write messages to the VideoCore\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`write::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@write`] +module"] pub type WRITE = crate::Reg; #[doc = "Write messages to the VideoCore"] pub mod write; -#[doc = "PEEK1 (rw) register accessor: an alias for `Reg`"] +#[doc = "PEEK1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peek1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peek1`] +module"] pub type PEEK1 = crate::Reg; #[doc = ""] pub mod peek1; -#[doc = "SENDER1 (rw) register accessor: an alias for `Reg`"] +#[doc = "SENDER1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sender1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sender1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sender1`] +module"] pub type SENDER1 = crate::Reg; #[doc = ""] pub mod sender1; -#[doc = "STATUS1 (rw) register accessor: an alias for `Reg`"] +#[doc = "STATUS1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status1`] +module"] pub type STATUS1 = crate::Reg; #[doc = ""] pub mod status1; -#[doc = "CONFIG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONFIG1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config1`] +module"] pub type CONFIG1 = crate::Reg; #[doc = ""] pub mod config1; diff --git a/crates/bcm2711-lpa/src/vcmailbox/config0.rs b/crates/bcm2711-lpa/src/vcmailbox/config0.rs index dce060f..b90c56d 100644 --- a/crates/bcm2711-lpa/src/vcmailbox/config0.rs +++ b/crates/bcm2711-lpa/src/vcmailbox/config0.rs @@ -1,43 +1,11 @@ #[doc = "Register `CONFIG0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONFIG0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IRQEN` reader - Enable the interrupt when data is available"] -pub type IRQEN_R = crate::BitReader; +pub type IRQEN_R = crate::BitReader; #[doc = "Field `IRQEN` writer - Enable the interrupt when data is available"] -pub type IRQEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG0_SPEC, bool, O>; +pub type IRQEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable the interrupt when data is available"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { IRQEN_R::new((self.bits & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONFIG0") + .field("irqen", &format_args!("{}", self.irqen().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable the interrupt when data is available"] #[inline(always)] #[must_use] - pub fn irqen(&mut self) -> IRQEN_W<0> { + pub fn irqen(&mut self) -> IRQEN_W { IRQEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config0](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONFIG0_SPEC; impl crate::RegisterSpec for CONFIG0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [config0::R](R) reader structure"] -impl crate::Readable for CONFIG0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [config0::W](W) writer structure"] +#[doc = "`read()` method returns [`config0::R`](R) reader structure"] +impl crate::Readable for CONFIG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config0::W`](W) writer structure"] impl crate::Writable for CONFIG0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/vcmailbox/config1.rs b/crates/bcm2711-lpa/src/vcmailbox/config1.rs index 3c238a6..8a50eee 100644 --- a/crates/bcm2711-lpa/src/vcmailbox/config1.rs +++ b/crates/bcm2711-lpa/src/vcmailbox/config1.rs @@ -1,59 +1,38 @@ #[doc = "Register `CONFIG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONFIG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config1](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONFIG1_SPEC; impl crate::RegisterSpec for CONFIG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [config1::R](R) reader structure"] -impl crate::Readable for CONFIG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [config1::W](W) writer structure"] +#[doc = "`read()` method returns [`config1::R`](R) reader structure"] +impl crate::Readable for CONFIG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config1::W`](W) writer structure"] impl crate::Writable for CONFIG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/vcmailbox/peek0.rs b/crates/bcm2711-lpa/src/vcmailbox/peek0.rs index 3b63843..9119a22 100644 --- a/crates/bcm2711-lpa/src/vcmailbox/peek0.rs +++ b/crates/bcm2711-lpa/src/vcmailbox/peek0.rs @@ -1,59 +1,38 @@ #[doc = "Register `PEEK0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PEEK0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek0](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peek0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEEK0_SPEC; impl crate::RegisterSpec for PEEK0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [peek0::R](R) reader structure"] -impl crate::Readable for PEEK0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [peek0::W](W) writer structure"] +#[doc = "`read()` method returns [`peek0::R`](R) reader structure"] +impl crate::Readable for PEEK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peek0::W`](W) writer structure"] impl crate::Writable for PEEK0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/vcmailbox/peek1.rs b/crates/bcm2711-lpa/src/vcmailbox/peek1.rs index 2431cc4..221331c 100644 --- a/crates/bcm2711-lpa/src/vcmailbox/peek1.rs +++ b/crates/bcm2711-lpa/src/vcmailbox/peek1.rs @@ -1,59 +1,38 @@ #[doc = "Register `PEEK1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PEEK1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek1](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peek1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEEK1_SPEC; impl crate::RegisterSpec for PEEK1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [peek1::R](R) reader structure"] -impl crate::Readable for PEEK1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [peek1::W](W) writer structure"] +#[doc = "`read()` method returns [`peek1::R`](R) reader structure"] +impl crate::Readable for PEEK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peek1::W`](W) writer structure"] impl crate::Writable for PEEK1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/vcmailbox/read.rs b/crates/bcm2711-lpa/src/vcmailbox/read.rs index 60b2d04..7328372 100644 --- a/crates/bcm2711-lpa/src/vcmailbox/read.rs +++ b/crates/bcm2711-lpa/src/vcmailbox/read.rs @@ -1,24 +1,19 @@ #[doc = "Register `READ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } -#[doc = "Read messages from the VideoCore\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [read](index.html) module"] +#[doc = "Read messages from the VideoCore\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`read::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct READ_SPEC; impl crate::RegisterSpec for READ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [read::R](R) reader structure"] -impl crate::Readable for READ_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`read::R`](R) reader structure"] +impl crate::Readable for READ_SPEC {} diff --git a/crates/bcm2711-lpa/src/vcmailbox/sender0.rs b/crates/bcm2711-lpa/src/vcmailbox/sender0.rs index cbeb2f1..4b8ec27 100644 --- a/crates/bcm2711-lpa/src/vcmailbox/sender0.rs +++ b/crates/bcm2711-lpa/src/vcmailbox/sender0.rs @@ -1,59 +1,38 @@ #[doc = "Register `SENDER0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SENDER0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sender0](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sender0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sender0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SENDER0_SPEC; impl crate::RegisterSpec for SENDER0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sender0::R](R) reader structure"] -impl crate::Readable for SENDER0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sender0::W](W) writer structure"] +#[doc = "`read()` method returns [`sender0::R`](R) reader structure"] +impl crate::Readable for SENDER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sender0::W`](W) writer structure"] impl crate::Writable for SENDER0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/vcmailbox/sender1.rs b/crates/bcm2711-lpa/src/vcmailbox/sender1.rs index 1537c2d..f787ecb 100644 --- a/crates/bcm2711-lpa/src/vcmailbox/sender1.rs +++ b/crates/bcm2711-lpa/src/vcmailbox/sender1.rs @@ -1,59 +1,38 @@ #[doc = "Register `SENDER1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SENDER1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sender1](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sender1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sender1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SENDER1_SPEC; impl crate::RegisterSpec for SENDER1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sender1::R](R) reader structure"] -impl crate::Readable for SENDER1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sender1::W](W) writer structure"] +#[doc = "`read()` method returns [`sender1::R`](R) reader structure"] +impl crate::Readable for SENDER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sender1::W`](W) writer structure"] impl crate::Writable for SENDER1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/vcmailbox/status0.rs b/crates/bcm2711-lpa/src/vcmailbox/status0.rs index 035e2a4..92a12f6 100644 --- a/crates/bcm2711-lpa/src/vcmailbox/status0.rs +++ b/crates/bcm2711-lpa/src/vcmailbox/status0.rs @@ -1,22 +1,9 @@ #[doc = "Register `STATUS0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EMPTY` reader - "] -pub type EMPTY_R = crate::BitReader; +pub type EMPTY_R = crate::BitReader; #[doc = "Field `FULL` reader - "] -pub type FULL_R = crate::BitReader; +pub type FULL_R = crate::BitReader; impl R { #[doc = "Bit 30"] #[inline(always)] @@ -29,12 +16,23 @@ impl R { FULL_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status0](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS0") + .field("full", &format_args!("{}", self.full().bit())) + .field("empty", &format_args!("{}", self.empty().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STATUS0_SPEC; impl crate::RegisterSpec for STATUS0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [status0::R](R) reader structure"] -impl crate::Readable for STATUS0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`status0::R`](R) reader structure"] +impl crate::Readable for STATUS0_SPEC {} diff --git a/crates/bcm2711-lpa/src/vcmailbox/status1.rs b/crates/bcm2711-lpa/src/vcmailbox/status1.rs index 1a7b501..64ad85f 100644 --- a/crates/bcm2711-lpa/src/vcmailbox/status1.rs +++ b/crates/bcm2711-lpa/src/vcmailbox/status1.rs @@ -1,59 +1,38 @@ #[doc = "Register `STATUS1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STATUS1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status1](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STATUS1_SPEC; impl crate::RegisterSpec for STATUS1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [status1::R](R) reader structure"] -impl crate::Readable for STATUS1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [status1::W](W) writer structure"] +#[doc = "`read()` method returns [`status1::R`](R) reader structure"] +impl crate::Readable for STATUS1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status1::W`](W) writer structure"] impl crate::Writable for STATUS1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2711-lpa/src/vcmailbox/write.rs b/crates/bcm2711-lpa/src/vcmailbox/write.rs index 4e09735..f34b6af 100644 --- a/crates/bcm2711-lpa/src/vcmailbox/write.rs +++ b/crates/bcm2711-lpa/src/vcmailbox/write.rs @@ -1,40 +1,29 @@ #[doc = "Register `WRITE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +pub type W = crate::W; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write messages to the VideoCore\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [write](index.html) module"] +#[doc = "Write messages to the VideoCore\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`write::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WRITE_SPEC; impl crate::RegisterSpec for WRITE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [write::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`write::W`](W) writer structure"] impl crate::Writable for WRITE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/Cargo.toml b/crates/bcm2835-lpa/Cargo.toml index df22dc7..ae8a1c8 100644 --- a/crates/bcm2835-lpa/Cargo.toml +++ b/crates/bcm2835-lpa/Cargo.toml @@ -1,9 +1,9 @@ [package] name = "bcm2835-lpa" -version = "0.1.0" +version = "0.2.0" authors = ["Po-Yi Tsai "] edition = "2021" -rust-version = "1.61.0" +rust-version = "1.65.0" description = "Peripheral access crate for BCM2835 found in the Raspberry Pi 1 and Zero." repository = "https://github.com/abt8601/raspi-pacs" license = "Unlicense" diff --git a/crates/bcm2835-lpa/src/aux.rs b/crates/bcm2835-lpa/src/aux.rs index 5380cb2..e9cf956 100644 --- a/crates/bcm2835-lpa/src/aux.rs +++ b/crates/bcm2835-lpa/src/aux.rs @@ -1,16 +1,19 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Interrupt status"] pub irq: IRQ, #[doc = "0x04 - Enable sub-peripherals"] pub enables: ENABLES, } -#[doc = "IRQ (rw) register accessor: an alias for `Reg`"] +#[doc = "IRQ (rw) register accessor: Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq`] +module"] pub type IRQ = crate::Reg; #[doc = "Interrupt status"] pub mod irq; -#[doc = "ENABLES (rw) register accessor: an alias for `Reg`"] +#[doc = "ENABLES (rw) register accessor: Enable sub-peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enables::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enables::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enables`] +module"] pub type ENABLES = crate::Reg; #[doc = "Enable sub-peripherals"] pub mod enables; diff --git a/crates/bcm2835-lpa/src/aux/enables.rs b/crates/bcm2835-lpa/src/aux/enables.rs index eb9fc6d..c84adb4 100644 --- a/crates/bcm2835-lpa/src/aux/enables.rs +++ b/crates/bcm2835-lpa/src/aux/enables.rs @@ -1,51 +1,19 @@ #[doc = "Register `ENABLES` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ENABLES` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UART_1` reader - UART1 enabled"] -pub type UART_1_R = crate::BitReader; +pub type UART_1_R = crate::BitReader; #[doc = "Field `UART_1` writer - UART1 enabled"] -pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +pub type UART_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_1` reader - SPI1 enabled"] -pub type SPI_1_R = crate::BitReader; +pub type SPI_1_R = crate::BitReader; #[doc = "Field `SPI_1` writer - SPI1 enabled"] -pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +pub type SPI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_2` reader - SPI2 enabled"] -pub type SPI_2_R = crate::BitReader; +pub type SPI_2_R = crate::BitReader; #[doc = "Field `SPI_2` writer - SPI2 enabled"] -pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +pub type SPI_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - UART1 enabled"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { SPI_2_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLES") + .field("spi_2", &format_args!("{}", self.spi_2().bit())) + .field("spi_1", &format_args!("{}", self.spi_1().bit())) + .field("uart_1", &format_args!("{}", self.uart_1().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - UART1 enabled"] #[inline(always)] #[must_use] - pub fn uart_1(&mut self) -> UART_1_W<0> { + pub fn uart_1(&mut self) -> UART_1_W { UART_1_W::new(self) } #[doc = "Bit 1 - SPI1 enabled"] #[inline(always)] #[must_use] - pub fn spi_1(&mut self) -> SPI_1_W<1> { + pub fn spi_1(&mut self) -> SPI_1_W { SPI_1_W::new(self) } #[doc = "Bit 2 - SPI2 enabled"] #[inline(always)] #[must_use] - pub fn spi_2(&mut self) -> SPI_2_W<2> { + pub fn spi_2(&mut self) -> SPI_2_W { SPI_2_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable sub-peripherals\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enables](index.html) module"] +#[doc = "Enable sub-peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enables::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enables::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLES_SPEC; impl crate::RegisterSpec for ENABLES_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enables::R](R) reader structure"] -impl crate::Readable for ENABLES_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [enables::W](W) writer structure"] +#[doc = "`read()` method returns [`enables::R`](R) reader structure"] +impl crate::Readable for ENABLES_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enables::W`](W) writer structure"] impl crate::Writable for ENABLES_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/aux/irq.rs b/crates/bcm2835-lpa/src/aux/irq.rs index a59c319..785d02a 100644 --- a/crates/bcm2835-lpa/src/aux/irq.rs +++ b/crates/bcm2835-lpa/src/aux/irq.rs @@ -1,51 +1,19 @@ #[doc = "Register `IRQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UART_1` reader - UART1 interrupt active"] -pub type UART_1_R = crate::BitReader; +pub type UART_1_R = crate::BitReader; #[doc = "Field `UART_1` writer - UART1 interrupt active"] -pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +pub type UART_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_1` reader - SPI1 interrupt active"] -pub type SPI_1_R = crate::BitReader; +pub type SPI_1_R = crate::BitReader; #[doc = "Field `SPI_1` writer - SPI1 interrupt active"] -pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +pub type SPI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_2` reader - SPI2 interrupt active"] -pub type SPI_2_R = crate::BitReader; +pub type SPI_2_R = crate::BitReader; #[doc = "Field `SPI_2` writer - SPI2 interrupt active"] -pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +pub type SPI_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - UART1 interrupt active"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { SPI_2_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IRQ") + .field("spi_2", &format_args!("{}", self.spi_2().bit())) + .field("spi_1", &format_args!("{}", self.spi_1().bit())) + .field("uart_1", &format_args!("{}", self.uart_1().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - UART1 interrupt active"] #[inline(always)] #[must_use] - pub fn uart_1(&mut self) -> UART_1_W<0> { + pub fn uart_1(&mut self) -> UART_1_W { UART_1_W::new(self) } #[doc = "Bit 1 - SPI1 interrupt active"] #[inline(always)] #[must_use] - pub fn spi_1(&mut self) -> SPI_1_W<1> { + pub fn spi_1(&mut self) -> SPI_1_W { SPI_1_W::new(self) } #[doc = "Bit 2 - SPI2 interrupt active"] #[inline(always)] #[must_use] - pub fn spi_2(&mut self) -> SPI_2_W<2> { + pub fn spi_2(&mut self) -> SPI_2_W { SPI_2_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq](index.html) module"] +#[doc = "Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRQ_SPEC; impl crate::RegisterSpec for IRQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irq::R](R) reader structure"] -impl crate::Readable for IRQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irq::W](W) writer structure"] +#[doc = "`read()` method returns [`irq::R`](R) reader structure"] +impl crate::Readable for IRQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq::W`](W) writer structure"] impl crate::Writable for IRQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/bsc0.rs b/crates/bcm2835-lpa/src/bsc0.rs index 8ccfb52..0d1c120 100644 --- a/crates/bcm2835-lpa/src/bsc0.rs +++ b/crates/bcm2835-lpa/src/bsc0.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control"] pub c: C, @@ -18,35 +19,43 @@ pub struct RegisterBlock { #[doc = "0x1c - Clock stretch timeout (broken on 283x)"] pub clkt: CLKT, } -#[doc = "C (rw) register accessor: an alias for `Reg`"] +#[doc = "C (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c`] +module"] pub type C = crate::Reg; #[doc = "Control"] pub mod c; -#[doc = "S (rw) register accessor: an alias for `Reg`"] +#[doc = "S (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s`] +module"] pub type S = crate::Reg; #[doc = "Status"] pub mod s; -#[doc = "DLEN (rw) register accessor: an alias for `Reg`"] +#[doc = "DLEN (rw) register accessor: Data length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlen`] +module"] pub type DLEN = crate::Reg; #[doc = "Data length"] pub mod dlen; -#[doc = "A (rw) register accessor: an alias for `Reg`"] +#[doc = "A (rw) register accessor: Slave address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a`] +module"] pub type A = crate::Reg; #[doc = "Slave address"] pub mod a; -#[doc = "FIFO (rw) register accessor: an alias for `Reg`"] +#[doc = "FIFO (rw) register accessor: Data FIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`] +module"] pub type FIFO = crate::Reg; #[doc = "Data FIFO"] pub mod fifo; -#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV (rw) register accessor: Clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div`] +module"] pub type DIV = crate::Reg; #[doc = "Clock divider"] pub mod div; -#[doc = "DEL (rw) register accessor: an alias for `Reg`"] +#[doc = "DEL (rw) register accessor: Data delay (Values must be under CDIV / 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`del::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`del::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@del`] +module"] pub type DEL = crate::Reg; #[doc = "Data delay (Values must be under CDIV / 2)"] pub mod del; -#[doc = "CLKT (rw) register accessor: an alias for `Reg`"] +#[doc = "CLKT (rw) register accessor: Clock stretch timeout (broken on 283x)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkt`] +module"] pub type CLKT = crate::Reg; #[doc = "Clock stretch timeout (broken on 283x)"] pub mod clkt; diff --git a/crates/bcm2835-lpa/src/bsc0/a.rs b/crates/bcm2835-lpa/src/bsc0/a.rs index d98d147..e9669f3 100644 --- a/crates/bcm2835-lpa/src/bsc0/a.rs +++ b/crates/bcm2835-lpa/src/bsc0/a.rs @@ -1,43 +1,11 @@ #[doc = "Register `A` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `A` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDR` reader - Slave address"] -pub type ADDR_R = crate::FieldReader; +pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - Slave address"] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, A_SPEC, u8, u8, 7, O>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; impl R { #[doc = "Bits 0:6 - Slave address"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { ADDR_R::new((self.bits & 0x7f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A") + .field("addr", &format_args!("{}", self.addr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - Slave address"] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<0> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Slave address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [a](index.html) module"] +#[doc = "Slave address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct A_SPEC; impl crate::RegisterSpec for A_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [a::R](R) reader structure"] -impl crate::Readable for A_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [a::W](W) writer structure"] +#[doc = "`read()` method returns [`a::R`](R) reader structure"] +impl crate::Readable for A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a::W`](W) writer structure"] impl crate::Writable for A_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/bsc0/c.rs b/crates/bcm2835-lpa/src/bsc0/c.rs index f62d48d..85f86f7 100644 --- a/crates/bcm2835-lpa/src/bsc0/c.rs +++ b/crates/bcm2835-lpa/src/bsc0/c.rs @@ -1,67 +1,35 @@ #[doc = "Register `C` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `READ` reader - Transfer is read"] -pub type READ_R = crate::BitReader; +pub type READ_R = crate::BitReader; #[doc = "Field `READ` writer - Transfer is read"] -pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLEAR` reader - Clear the FIFO"] -pub type CLEAR_R = crate::FieldReader; +pub type CLEAR_R = crate::FieldReader; #[doc = "Field `CLEAR` writer - Clear the FIFO"] -pub type CLEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, C_SPEC, u8, u8, 2, O>; +pub type CLEAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `ST` reader - Start transfer"] -pub type ST_R = crate::BitReader; +pub type ST_R = crate::BitReader; #[doc = "Field `ST` writer - Start transfer"] -pub type ST_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTD` reader - Interrupt on done"] -pub type INTD_R = crate::BitReader; +pub type INTD_R = crate::BitReader; #[doc = "Field `INTD` writer - Interrupt on done"] -pub type INTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type INTD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTT` reader - Interrupt on TX"] -pub type INTT_R = crate::BitReader; +pub type INTT_R = crate::BitReader; #[doc = "Field `INTT` writer - Interrupt on TX"] -pub type INTT_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type INTT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTR` reader - Interrupt on RX"] -pub type INTR_R = crate::BitReader; +pub type INTR_R = crate::BitReader; #[doc = "Field `INTR` writer - Interrupt on RX"] -pub type INTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type INTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2CEN` reader - I2C Enable"] -pub type I2CEN_R = crate::BitReader; +pub type I2CEN_R = crate::BitReader; #[doc = "Field `I2CEN` writer - I2C Enable"] -pub type I2CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type I2CEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer is read"] #[inline(always)] @@ -99,68 +67,87 @@ impl R { I2CEN_R::new(((self.bits >> 15) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("C") + .field("i2cen", &format_args!("{}", self.i2cen().bit())) + .field("intr", &format_args!("{}", self.intr().bit())) + .field("intt", &format_args!("{}", self.intt().bit())) + .field("intd", &format_args!("{}", self.intd().bit())) + .field("st", &format_args!("{}", self.st().bit())) + .field("clear", &format_args!("{}", self.clear().bits())) + .field("read", &format_args!("{}", self.read().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer is read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W<0> { + pub fn read(&mut self) -> READ_W { READ_W::new(self) } #[doc = "Bits 4:5 - Clear the FIFO"] #[inline(always)] #[must_use] - pub fn clear(&mut self) -> CLEAR_W<4> { + pub fn clear(&mut self) -> CLEAR_W { CLEAR_W::new(self) } #[doc = "Bit 7 - Start transfer"] #[inline(always)] #[must_use] - pub fn st(&mut self) -> ST_W<7> { + pub fn st(&mut self) -> ST_W { ST_W::new(self) } #[doc = "Bit 8 - Interrupt on done"] #[inline(always)] #[must_use] - pub fn intd(&mut self) -> INTD_W<8> { + pub fn intd(&mut self) -> INTD_W { INTD_W::new(self) } #[doc = "Bit 9 - Interrupt on TX"] #[inline(always)] #[must_use] - pub fn intt(&mut self) -> INTT_W<9> { + pub fn intt(&mut self) -> INTT_W { INTT_W::new(self) } #[doc = "Bit 10 - Interrupt on RX"] #[inline(always)] #[must_use] - pub fn intr(&mut self) -> INTR_W<10> { + pub fn intr(&mut self) -> INTR_W { INTR_W::new(self) } #[doc = "Bit 15 - I2C Enable"] #[inline(always)] #[must_use] - pub fn i2cen(&mut self) -> I2CEN_W<15> { + pub fn i2cen(&mut self) -> I2CEN_W { I2CEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C_SPEC; impl crate::RegisterSpec for C_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c::R](R) reader structure"] -impl crate::Readable for C_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c::W](W) writer structure"] +#[doc = "`read()` method returns [`c::R`](R) reader structure"] +impl crate::Readable for C_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c::W`](W) writer structure"] impl crate::Writable for C_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/bsc0/clkt.rs b/crates/bcm2835-lpa/src/bsc0/clkt.rs index 15bc5c4..103f923 100644 --- a/crates/bcm2835-lpa/src/bsc0/clkt.rs +++ b/crates/bcm2835-lpa/src/bsc0/clkt.rs @@ -1,43 +1,11 @@ #[doc = "Register `CLKT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLKT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TOUT` reader - Number of SCL clock cycles to wait"] -pub type TOUT_R = crate::FieldReader; +pub type TOUT_R = crate::FieldReader; #[doc = "Field `TOUT` writer - Number of SCL clock cycles to wait"] -pub type TOUT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKT_SPEC, u16, u16, 16, O>; +pub type TOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { TOUT_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLKT") + .field("tout", &format_args!("{}", self.tout().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"] #[inline(always)] #[must_use] - pub fn tout(&mut self) -> TOUT_W<0> { + pub fn tout(&mut self) -> TOUT_W { TOUT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock stretch timeout (broken on 283x)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkt](index.html) module"] +#[doc = "Clock stretch timeout (broken on 283x)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKT_SPEC; impl crate::RegisterSpec for CLKT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clkt::R](R) reader structure"] -impl crate::Readable for CLKT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clkt::W](W) writer structure"] +#[doc = "`read()` method returns [`clkt::R`](R) reader structure"] +impl crate::Readable for CLKT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clkt::W`](W) writer structure"] impl crate::Writable for CLKT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/bsc0/del.rs b/crates/bcm2835-lpa/src/bsc0/del.rs index c39336b..4c0e876 100644 --- a/crates/bcm2835-lpa/src/bsc0/del.rs +++ b/crates/bcm2835-lpa/src/bsc0/del.rs @@ -1,47 +1,15 @@ #[doc = "Register `DEL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `REDL` reader - Delay before reading after a rising edge"] -pub type REDL_R = crate::FieldReader; +pub type REDL_R = crate::FieldReader; #[doc = "Field `REDL` writer - Delay before reading after a rising edge"] -pub type REDL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEL_SPEC, u16, u16, 16, O>; +pub type REDL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `FEDL` reader - Delay before reading after a falling edge"] -pub type FEDL_R = crate::FieldReader; +pub type FEDL_R = crate::FieldReader; #[doc = "Field `FEDL` writer - Delay before reading after a falling edge"] -pub type FEDL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEL_SPEC, u16, u16, 16, O>; +pub type FEDL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Delay before reading after a rising edge"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { FEDL_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEL") + .field("fedl", &format_args!("{}", self.fedl().bits())) + .field("redl", &format_args!("{}", self.redl().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Delay before reading after a rising edge"] #[inline(always)] #[must_use] - pub fn redl(&mut self) -> REDL_W<0> { + pub fn redl(&mut self) -> REDL_W { REDL_W::new(self) } #[doc = "Bits 16:31 - Delay before reading after a falling edge"] #[inline(always)] #[must_use] - pub fn fedl(&mut self) -> FEDL_W<16> { + pub fn fedl(&mut self) -> FEDL_W { FEDL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data delay (Values must be under CDIV / 2)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [del](index.html) module"] +#[doc = "Data delay (Values must be under CDIV / 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`del::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`del::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEL_SPEC; impl crate::RegisterSpec for DEL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [del::R](R) reader structure"] -impl crate::Readable for DEL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [del::W](W) writer structure"] +#[doc = "`read()` method returns [`del::R`](R) reader structure"] +impl crate::Readable for DEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`del::W`](W) writer structure"] impl crate::Writable for DEL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/bsc0/div.rs b/crates/bcm2835-lpa/src/bsc0/div.rs index ce0aa5a..9ffd801 100644 --- a/crates/bcm2835-lpa/src/bsc0/div.rs +++ b/crates/bcm2835-lpa/src/bsc0/div.rs @@ -1,43 +1,11 @@ #[doc = "Register `DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CDIV` reader - Divide the source clock"] -pub type CDIV_R = crate::FieldReader; +pub type CDIV_R = crate::FieldReader; #[doc = "Field `CDIV` writer - Divide the source clock"] -pub type CDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 16, O>; +pub type CDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Divide the source clock"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { CDIV_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIV") + .field("cdiv", &format_args!("{}", self.cdiv().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Divide the source clock"] #[inline(always)] #[must_use] - pub fn cdiv(&mut self) -> CDIV_W<0> { + pub fn cdiv(&mut self) -> CDIV_W { CDIV_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](index.html) module"] +#[doc = "Clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SPEC; impl crate::RegisterSpec for DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div::R](R) reader structure"] -impl crate::Readable for DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +#[doc = "`read()` method returns [`div::R`](R) reader structure"] +impl crate::Readable for DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] impl crate::Writable for DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/bsc0/dlen.rs b/crates/bcm2835-lpa/src/bsc0/dlen.rs index 25e2771..5c7bb83 100644 --- a/crates/bcm2835-lpa/src/bsc0/dlen.rs +++ b/crates/bcm2835-lpa/src/bsc0/dlen.rs @@ -1,43 +1,11 @@ #[doc = "Register `DLEN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DLEN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DLEN` reader - Data length"] -pub type DLEN_R = crate::FieldReader; +pub type DLEN_R = crate::FieldReader; #[doc = "Field `DLEN` writer - Data length"] -pub type DLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLEN_SPEC, u16, u16, 16, O>; +pub type DLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Data length"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DLEN_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DLEN") + .field("dlen", &format_args!("{}", self.dlen().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Data length"] #[inline(always)] #[must_use] - pub fn dlen(&mut self) -> DLEN_W<0> { + pub fn dlen(&mut self) -> DLEN_W { DLEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlen](index.html) module"] +#[doc = "Data length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DLEN_SPEC; impl crate::RegisterSpec for DLEN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dlen::R](R) reader structure"] -impl crate::Readable for DLEN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dlen::W](W) writer structure"] +#[doc = "`read()` method returns [`dlen::R`](R) reader structure"] +impl crate::Readable for DLEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dlen::W`](W) writer structure"] impl crate::Writable for DLEN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/bsc0/fifo.rs b/crates/bcm2835-lpa/src/bsc0/fifo.rs index f85912b..0536908 100644 --- a/crates/bcm2835-lpa/src/bsc0/fifo.rs +++ b/crates/bcm2835-lpa/src/bsc0/fifo.rs @@ -1,43 +1,11 @@ #[doc = "Register `FIFO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FIFO` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - Access the FIFO"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - Access the FIFO"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u8, u8, 8, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Access the FIFO"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new((self.bits & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Access the FIFO"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data FIFO\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"] +#[doc = "Data FIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_SPEC; impl crate::RegisterSpec for FIFO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fifo::R](R) reader structure"] -impl crate::Readable for FIFO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"] +#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] +impl crate::Readable for FIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"] impl crate::Writable for FIFO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/bsc0/s.rs b/crates/bcm2835-lpa/src/bsc0/s.rs index 45f365b..56cb006 100644 --- a/crates/bcm2835-lpa/src/bsc0/s.rs +++ b/crates/bcm2835-lpa/src/bsc0/s.rs @@ -1,65 +1,33 @@ #[doc = "Register `S` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `S` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TA` reader - Transfer active"] -pub type TA_R = crate::BitReader; +pub type TA_R = crate::BitReader; #[doc = "Field `DONE` reader - Transfer done"] -pub type DONE_R = crate::BitReader; +pub type DONE_R = crate::BitReader; #[doc = "Field `DONE` writer - Transfer done"] -pub type DONE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +pub type DONE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TXW` reader - FIFO needs to be written"] -pub type TXW_R = crate::BitReader; +pub type TXW_R = crate::BitReader; #[doc = "Field `RXR` reader - FIFO needs to be read"] -pub type RXR_R = crate::BitReader; +pub type RXR_R = crate::BitReader; #[doc = "Field `TXD` reader - FIFO has space for at least one byte"] -pub type TXD_R = crate::BitReader; +pub type TXD_R = crate::BitReader; #[doc = "Field `RXD` reader - FIFO contains at least one byte"] -pub type RXD_R = crate::BitReader; +pub type RXD_R = crate::BitReader; #[doc = "Field `TXE` reader - FIFO is empty. Nothing to transmit"] -pub type TXE_R = crate::BitReader; +pub type TXE_R = crate::BitReader; #[doc = "Field `RXF` reader - FIFO is full. Can't receive anything else"] -pub type RXF_R = crate::BitReader; +pub type RXF_R = crate::BitReader; #[doc = "Field `ERR` reader - Error: No ack"] -pub type ERR_R = crate::BitReader; +pub type ERR_R = crate::BitReader; #[doc = "Field `ERR` writer - Error: No ack"] -pub type ERR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +pub type ERR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLKT` reader - Clock stretch timeout"] -pub type CLKT_R = crate::BitReader; +pub type CLKT_R = crate::BitReader; #[doc = "Field `CLKT` writer - Clock stretch timeout"] -pub type CLKT_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +pub type CLKT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer active"] #[inline(always)] @@ -112,44 +80,66 @@ impl R { CLKT_R::new(((self.bits >> 9) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("S") + .field("clkt", &format_args!("{}", self.clkt().bit())) + .field("err", &format_args!("{}", self.err().bit())) + .field("rxf", &format_args!("{}", self.rxf().bit())) + .field("txe", &format_args!("{}", self.txe().bit())) + .field("rxd", &format_args!("{}", self.rxd().bit())) + .field("txd", &format_args!("{}", self.txd().bit())) + .field("rxr", &format_args!("{}", self.rxr().bit())) + .field("txw", &format_args!("{}", self.txw().bit())) + .field("done", &format_args!("{}", self.done().bit())) + .field("ta", &format_args!("{}", self.ta().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Transfer done"] #[inline(always)] #[must_use] - pub fn done(&mut self) -> DONE_W<1> { + pub fn done(&mut self) -> DONE_W { DONE_W::new(self) } #[doc = "Bit 8 - Error: No ack"] #[inline(always)] #[must_use] - pub fn err(&mut self) -> ERR_W<8> { + pub fn err(&mut self) -> ERR_W { ERR_W::new(self) } #[doc = "Bit 9 - Clock stretch timeout"] #[inline(always)] #[must_use] - pub fn clkt(&mut self) -> CLKT_W<9> { + pub fn clkt(&mut self) -> CLKT_W { CLKT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s](index.html) module"] +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct S_SPEC; impl crate::RegisterSpec for S_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [s::R](R) reader structure"] -impl crate::Readable for S_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [s::W](W) writer structure"] +#[doc = "`read()` method returns [`s::R`](R) reader structure"] +impl crate::Readable for S_SPEC {} +#[doc = "`write(|w| ..)` method takes [`s::W`](W) writer structure"] impl crate::Writable for S_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0302; } diff --git a/crates/bcm2835-lpa/src/cm_pcm.rs b/crates/bcm2835-lpa/src/cm_pcm.rs index 0c60fcd..855e1b0 100644 --- a/crates/bcm2835-lpa/src/cm_pcm.rs +++ b/crates/bcm2835-lpa/src/cm_pcm.rs @@ -1,16 +1,19 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control / Status"] pub cs: CS, #[doc = "0x04 - Clock divisor"] pub div: DIV, } -#[doc = "CS (rw) register accessor: an alias for `Reg`"] +#[doc = "CS (rw) register accessor: Control / Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cs`] +module"] pub type CS = crate::Reg; #[doc = "Control / Status"] pub mod cs; -#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV (rw) register accessor: Clock divisor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div`] +module"] pub type DIV = crate::Reg; #[doc = "Clock divisor"] pub mod div; diff --git a/crates/bcm2835-lpa/src/cm_pcm/cs.rs b/crates/bcm2835-lpa/src/cm_pcm/cs.rs index 67ddd60..036729f 100644 --- a/crates/bcm2835-lpa/src/cm_pcm/cs.rs +++ b/crates/bcm2835-lpa/src/cm_pcm/cs.rs @@ -1,41 +1,9 @@ #[doc = "Register `CS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SRC` reader - Clock source"] -pub type SRC_R = crate::FieldReader; +pub type SRC_R = crate::FieldReader; #[doc = "Clock source\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -61,10 +29,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for SRC_A { + type Ux = u8; +} impl SRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 1 => Some(SRC_A::XOSC), 2 => Some(SRC_A::TEST0), @@ -76,99 +47,103 @@ impl SRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `XOSC`"] + #[doc = "`1`"] #[inline(always)] pub fn is_xosc(&self) -> bool { *self == SRC_A::XOSC } - #[doc = "Checks if the value of the field is `TEST0`"] + #[doc = "`10`"] #[inline(always)] pub fn is_test0(&self) -> bool { *self == SRC_A::TEST0 } - #[doc = "Checks if the value of the field is `TEST1`"] + #[doc = "`11`"] #[inline(always)] pub fn is_test1(&self) -> bool { *self == SRC_A::TEST1 } - #[doc = "Checks if the value of the field is `PLLA`"] + #[doc = "`100`"] #[inline(always)] pub fn is_plla(&self) -> bool { *self == SRC_A::PLLA } - #[doc = "Checks if the value of the field is `PLLB`"] + #[doc = "`101`"] #[inline(always)] pub fn is_pllb(&self) -> bool { *self == SRC_A::PLLB } - #[doc = "Checks if the value of the field is `PLLC`"] + #[doc = "`110`"] #[inline(always)] pub fn is_pllc(&self) -> bool { *self == SRC_A::PLLC } - #[doc = "Checks if the value of the field is `HDMI`"] + #[doc = "`111`"] #[inline(always)] pub fn is_hdmi(&self) -> bool { *self == SRC_A::HDMI } } #[doc = "Field `SRC` writer - Clock source"] -pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, SRC_A, 4, O>; -impl<'a, const O: u8> SRC_W<'a, O> { +pub type SRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, SRC_A>; +impl<'a, REG, const O: u8> SRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1`"] #[inline(always)] - pub fn xosc(self) -> &'a mut W { + pub fn xosc(self) -> &'a mut crate::W { self.variant(SRC_A::XOSC) } #[doc = "`10`"] #[inline(always)] - pub fn test0(self) -> &'a mut W { + pub fn test0(self) -> &'a mut crate::W { self.variant(SRC_A::TEST0) } #[doc = "`11`"] #[inline(always)] - pub fn test1(self) -> &'a mut W { + pub fn test1(self) -> &'a mut crate::W { self.variant(SRC_A::TEST1) } #[doc = "`100`"] #[inline(always)] - pub fn plla(self) -> &'a mut W { + pub fn plla(self) -> &'a mut crate::W { self.variant(SRC_A::PLLA) } #[doc = "`101`"] #[inline(always)] - pub fn pllb(self) -> &'a mut W { + pub fn pllb(self) -> &'a mut crate::W { self.variant(SRC_A::PLLB) } #[doc = "`110`"] #[inline(always)] - pub fn pllc(self) -> &'a mut W { + pub fn pllc(self) -> &'a mut crate::W { self.variant(SRC_A::PLLC) } #[doc = "`111`"] #[inline(always)] - pub fn hdmi(self) -> &'a mut W { + pub fn hdmi(self) -> &'a mut crate::W { self.variant(SRC_A::HDMI) } } #[doc = "Field `ENAB` reader - Enable the clock generator. (Switch SRC first.)"] -pub type ENAB_R = crate::BitReader; +pub type ENAB_R = crate::BitReader; #[doc = "Field `ENAB` writer - Enable the clock generator. (Switch SRC first.)"] -pub type ENAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type ENAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `KILL` reader - Stop and reset the generator"] -pub type KILL_R = crate::BitReader; +pub type KILL_R = crate::BitReader; #[doc = "Field `KILL` writer - Stop and reset the generator"] -pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type KILL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUSY` reader - Indicates the clock generator is running"] -pub type BUSY_R = crate::BitReader; +pub type BUSY_R = crate::BitReader; #[doc = "Field `FLIP` reader - Generate an edge on output. (For testing)"] -pub type FLIP_R = crate::BitReader; +pub type FLIP_R = crate::BitReader; #[doc = "Field `FLIP` writer - Generate an edge on output. (For testing)"] -pub type FLIP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type FLIP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MASH` reader - MASH control, stage count"] -pub type MASH_R = crate::FieldReader; +pub type MASH_R = crate::FieldReader; #[doc = "Field `MASH` writer - MASH control, stage count"] -pub type MASH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, u8, 2, O>; +pub type MASH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Password. Always 0x5a\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -182,12 +157,19 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for PASSWD_AW { + type Ux = u8; +} #[doc = "Field `PASSWD` writer - Password. Always 0x5a"] -pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, PASSWD_AW, 8, O>; -impl<'a, const O: u8> PASSWD_W<'a, O> { +pub type PASSWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, PASSWD_AW>; +impl<'a, REG, const O: u8> PASSWD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1011010`"] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(PASSWD_AW::PASSWD) } } @@ -223,62 +205,80 @@ impl R { MASH_R::new(((self.bits >> 9) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CS") + .field("mash", &format_args!("{}", self.mash().bits())) + .field("flip", &format_args!("{}", self.flip().bit())) + .field("busy", &format_args!("{}", self.busy().bit())) + .field("kill", &format_args!("{}", self.kill().bit())) + .field("enab", &format_args!("{}", self.enab().bit())) + .field("src", &format_args!("{}", self.src().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:3 - Clock source"] #[inline(always)] #[must_use] - pub fn src(&mut self) -> SRC_W<0> { + pub fn src(&mut self) -> SRC_W { SRC_W::new(self) } #[doc = "Bit 4 - Enable the clock generator. (Switch SRC first.)"] #[inline(always)] #[must_use] - pub fn enab(&mut self) -> ENAB_W<4> { + pub fn enab(&mut self) -> ENAB_W { ENAB_W::new(self) } #[doc = "Bit 5 - Stop and reset the generator"] #[inline(always)] #[must_use] - pub fn kill(&mut self) -> KILL_W<5> { + pub fn kill(&mut self) -> KILL_W { KILL_W::new(self) } #[doc = "Bit 8 - Generate an edge on output. (For testing)"] #[inline(always)] #[must_use] - pub fn flip(&mut self) -> FLIP_W<8> { + pub fn flip(&mut self) -> FLIP_W { FLIP_W::new(self) } #[doc = "Bits 9:10 - MASH control, stage count"] #[inline(always)] #[must_use] - pub fn mash(&mut self) -> MASH_W<9> { + pub fn mash(&mut self) -> MASH_W { MASH_W::new(self) } #[doc = "Bits 24:31 - Password. Always 0x5a"] #[inline(always)] #[must_use] - pub fn passwd(&mut self) -> PASSWD_W<24> { + pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control / Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +#[doc = "Control / Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CS_SPEC; impl crate::RegisterSpec for CS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cs::R](R) reader structure"] -impl crate::Readable for CS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/cm_pcm/div.rs b/crates/bcm2835-lpa/src/cm_pcm/div.rs index a0c99f8..825974e 100644 --- a/crates/bcm2835-lpa/src/cm_pcm/div.rs +++ b/crates/bcm2835-lpa/src/cm_pcm/div.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DIVF` reader - Fractional part of divisor"] -pub type DIVF_R = crate::FieldReader; +pub type DIVF_R = crate::FieldReader; #[doc = "Field `DIVF` writer - Fractional part of divisor"] -pub type DIVF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 12, O>; +pub type DIVF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; #[doc = "Field `DIVI` reader - Integer part of divisor"] -pub type DIVI_R = crate::FieldReader; +pub type DIVI_R = crate::FieldReader; #[doc = "Field `DIVI` writer - Integer part of divisor"] -pub type DIVI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 12, O>; +pub type DIVI_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; #[doc = "Password. Always 0x5a\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -55,12 +23,19 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for PASSWD_AW { + type Ux = u8; +} #[doc = "Field `PASSWD` writer - Password. Always 0x5a"] -pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u8, PASSWD_AW, 8, O>; -impl<'a, const O: u8> PASSWD_W<'a, O> { +pub type PASSWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, PASSWD_AW>; +impl<'a, REG, const O: u8> PASSWD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1011010`"] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(PASSWD_AW::PASSWD) } } @@ -76,44 +51,58 @@ impl R { DIVI_R::new(((self.bits >> 12) & 0x0fff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIV") + .field("divi", &format_args!("{}", self.divi().bits())) + .field("divf", &format_args!("{}", self.divf().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:11 - Fractional part of divisor"] #[inline(always)] #[must_use] - pub fn divf(&mut self) -> DIVF_W<0> { + pub fn divf(&mut self) -> DIVF_W { DIVF_W::new(self) } #[doc = "Bits 12:23 - Integer part of divisor"] #[inline(always)] #[must_use] - pub fn divi(&mut self) -> DIVI_W<12> { + pub fn divi(&mut self) -> DIVI_W { DIVI_W::new(self) } #[doc = "Bits 24:31 - Password. Always 0x5a"] #[inline(always)] #[must_use] - pub fn passwd(&mut self) -> PASSWD_W<24> { + pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](index.html) module"] +#[doc = "Clock divisor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SPEC; impl crate::RegisterSpec for DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div::R](R) reader structure"] -impl crate::Readable for DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +#[doc = "`read()` method returns [`div::R`](R) reader structure"] +impl crate::Readable for DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] impl crate::Writable for DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc.rs b/crates/bcm2835-lpa/src/emmc.rs index e4be2cf..597a27a 100644 --- a/crates/bcm2835-lpa/src/emmc.rs +++ b/crates/bcm2835-lpa/src/emmc.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Argument for ACMD23 command"] pub arg2: ARG2, @@ -59,107 +60,133 @@ pub struct RegisterBlock { #[doc = "0xfc - Version information and slot interrupt status"] pub slotisr_ver: SLOTISR_VER, } -#[doc = "ARG2 (rw) register accessor: an alias for `Reg`"] +#[doc = "ARG2 (rw) register accessor: Argument for ACMD23 command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arg2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arg2`] +module"] pub type ARG2 = crate::Reg; #[doc = "Argument for ACMD23 command"] pub mod arg2; -#[doc = "BLKSIZECNT (rw) register accessor: an alias for `Reg`"] +#[doc = "BLKSIZECNT (rw) register accessor: Numer and size in bytes for data block to be transferred\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blksizecnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blksizecnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blksizecnt`] +module"] pub type BLKSIZECNT = crate::Reg; #[doc = "Numer and size in bytes for data block to be transferred"] pub mod blksizecnt; -#[doc = "ARG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "ARG1 (rw) register accessor: Argument for everything but ACMD23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arg1`] +module"] pub type ARG1 = crate::Reg; #[doc = "Argument for everything but ACMD23"] pub mod arg1; -#[doc = "CMDTM (rw) register accessor: an alias for `Reg`"] +#[doc = "CMDTM (rw) register accessor: Issue commands to the card\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdtm::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdtm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdtm`] +module"] pub type CMDTM = crate::Reg; #[doc = "Issue commands to the card"] pub mod cmdtm; -#[doc = "RESP0 (rw) register accessor: an alias for `Reg`"] +#[doc = "RESP0 (rw) register accessor: Status bits of the response\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp0`] +module"] pub type RESP0 = crate::Reg; #[doc = "Status bits of the response"] pub mod resp0; -#[doc = "RESP1 (rw) register accessor: an alias for `Reg`"] +#[doc = "RESP1 (rw) register accessor: Bits 63:32 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp1`] +module"] pub type RESP1 = crate::Reg; #[doc = "Bits 63:32 of CMD2 and CMD10 responses"] pub mod resp1; -#[doc = "RESP2 (rw) register accessor: an alias for `Reg`"] +#[doc = "RESP2 (rw) register accessor: Bits 95:64 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp2`] +module"] pub type RESP2 = crate::Reg; #[doc = "Bits 95:64 of CMD2 and CMD10 responses"] pub mod resp2; -#[doc = "RESP3 (rw) register accessor: an alias for `Reg`"] +#[doc = "RESP3 (rw) register accessor: Bits 127:96 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp3`] +module"] pub type RESP3 = crate::Reg; #[doc = "Bits 127:96 of CMD2 and CMD10 responses"] pub mod resp3; -#[doc = "DATA (rw) register accessor: an alias for `Reg`"] +#[doc = "DATA (rw) register accessor: Data to/from the card\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] +module"] pub type DATA = crate::Reg; #[doc = "Data to/from the card"] pub mod data; -#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +#[doc = "STATUS (rw) register accessor: Status info for debugging\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] +module"] pub type STATUS = crate::Reg; #[doc = "Status info for debugging"] pub mod status; -#[doc = "CONTROL0 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONTROL0 (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control0`] +module"] pub type CONTROL0 = crate::Reg; #[doc = "Control"] pub mod control0; -#[doc = "CONTROL1 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONTROL1 (rw) register accessor: Configure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control1`] +module"] pub type CONTROL1 = crate::Reg; #[doc = "Configure"] pub mod control1; -#[doc = "INTERRUPT (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERRUPT (rw) register accessor: Interrupt flags\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrupt`] +module"] pub type INTERRUPT = crate::Reg; #[doc = "Interrupt flags"] pub mod interrupt; -#[doc = "IRPT_MASK (rw) register accessor: an alias for `Reg`"] +#[doc = "IRPT_MASK (rw) register accessor: Mask interrupts that change in INTERRUPT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irpt_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irpt_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irpt_mask`] +module"] pub type IRPT_MASK = crate::Reg; #[doc = "Mask interrupts that change in INTERRUPT"] pub mod irpt_mask; -#[doc = "IRPT_EN (rw) register accessor: an alias for `Reg`"] +#[doc = "IRPT_EN (rw) register accessor: Enable interrupt to core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irpt_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irpt_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irpt_en`] +module"] pub type IRPT_EN = crate::Reg; #[doc = "Enable interrupt to core"] pub mod irpt_en; -#[doc = "CONTROL2 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONTROL2 (rw) register accessor: Control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control2`] +module"] pub type CONTROL2 = crate::Reg; #[doc = "Control 2"] pub mod control2; -#[doc = "FORCE_IRPT (rw) register accessor: an alias for `Reg`"] +#[doc = "FORCE_IRPT (rw) register accessor: Force an interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`force_irpt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`force_irpt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@force_irpt`] +module"] pub type FORCE_IRPT = crate::Reg; #[doc = "Force an interrupt"] pub mod force_irpt; -#[doc = "BOOT_TIMEOUT (rw) register accessor: an alias for `Reg`"] +#[doc = "BOOT_TIMEOUT (rw) register accessor: Number of SD clock cycles to wait for boot\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`boot_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`boot_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@boot_timeout`] +module"] pub type BOOT_TIMEOUT = crate::Reg; #[doc = "Number of SD clock cycles to wait for boot"] pub mod boot_timeout; -#[doc = "DBG_SEL (rw) register accessor: an alias for `Reg`"] +#[doc = "DBG_SEL (rw) register accessor: What submodules are accessed by the debug bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbg_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbg_sel`] +module"] pub type DBG_SEL = crate::Reg; #[doc = "What submodules are accessed by the debug bus"] pub mod dbg_sel; -#[doc = "EXRDFIFO_CFG (rw) register accessor: an alias for `Reg`"] +#[doc = "EXRDFIFO_CFG (rw) register accessor: Fine tune DMA request generation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exrdfifo_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrdfifo_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exrdfifo_cfg`] +module"] pub type EXRDFIFO_CFG = crate::Reg; #[doc = "Fine tune DMA request generation"] pub mod exrdfifo_cfg; -#[doc = "EXRDFIFO_EN (rw) register accessor: an alias for `Reg`"] +#[doc = "EXRDFIFO_EN (rw) register accessor: Enable the extension data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exrdfifo_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrdfifo_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exrdfifo_en`] +module"] pub type EXRDFIFO_EN = crate::Reg; #[doc = "Enable the extension data register"] pub mod exrdfifo_en; -#[doc = "TUNE_STEP (rw) register accessor: an alias for `Reg`"] +#[doc = "TUNE_STEP (rw) register accessor: Sample clock delay step duration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_step::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_step::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tune_step`] +module"] pub type TUNE_STEP = crate::Reg; #[doc = "Sample clock delay step duration"] pub mod tune_step; -#[doc = "TUNE_STEPS_STD (rw) register accessor: an alias for `Reg`"] +#[doc = "TUNE_STEPS_STD (rw) register accessor: Sample clock delay step count for SDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_steps_std::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_steps_std::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tune_steps_std`] +module"] pub type TUNE_STEPS_STD = crate::Reg; #[doc = "Sample clock delay step count for SDR"] pub mod tune_steps_std; -#[doc = "TUNE_STEPS_DDR (rw) register accessor: an alias for `Reg`"] +#[doc = "TUNE_STEPS_DDR (rw) register accessor: Sample clock delay step count for DDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_steps_ddr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_steps_ddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tune_steps_ddr`] +module"] pub type TUNE_STEPS_DDR = crate::Reg; #[doc = "Sample clock delay step count for DDR"] pub mod tune_steps_ddr; -#[doc = "SPI_INT_SPT (rw) register accessor: an alias for `Reg`"] +#[doc = "SPI_INT_SPT (rw) register accessor: Interrupts in SPI mode depend on CS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_int_spt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_int_spt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_int_spt`] +module"] pub type SPI_INT_SPT = crate::Reg; #[doc = "Interrupts in SPI mode depend on CS"] pub mod spi_int_spt; -#[doc = "SLOTISR_VER (rw) register accessor: an alias for `Reg`"] +#[doc = "SLOTISR_VER (rw) register accessor: Version information and slot interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slotisr_ver::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slotisr_ver::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slotisr_ver`] +module"] pub type SLOTISR_VER = crate::Reg; #[doc = "Version information and slot interrupt status"] pub mod slotisr_ver; diff --git a/crates/bcm2835-lpa/src/emmc/arg1.rs b/crates/bcm2835-lpa/src/emmc/arg1.rs index 4a25300..491f890 100644 --- a/crates/bcm2835-lpa/src/emmc/arg1.rs +++ b/crates/bcm2835-lpa/src/emmc/arg1.rs @@ -1,59 +1,38 @@ #[doc = "Register `ARG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ARG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Argument for everything but ACMD23\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arg1](index.html) module"] +#[doc = "Argument for everything but ACMD23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ARG1_SPEC; impl crate::RegisterSpec for ARG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [arg1::R](R) reader structure"] -impl crate::Readable for ARG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [arg1::W](W) writer structure"] +#[doc = "`read()` method returns [`arg1::R`](R) reader structure"] +impl crate::Readable for ARG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`arg1::W`](W) writer structure"] impl crate::Writable for ARG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/arg2.rs b/crates/bcm2835-lpa/src/emmc/arg2.rs index b295b35..90678c2 100644 --- a/crates/bcm2835-lpa/src/emmc/arg2.rs +++ b/crates/bcm2835-lpa/src/emmc/arg2.rs @@ -1,59 +1,38 @@ #[doc = "Register `ARG2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ARG2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Argument for ACMD23 command\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arg2](index.html) module"] +#[doc = "Argument for ACMD23 command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arg2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ARG2_SPEC; impl crate::RegisterSpec for ARG2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [arg2::R](R) reader structure"] -impl crate::Readable for ARG2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [arg2::W](W) writer structure"] +#[doc = "`read()` method returns [`arg2::R`](R) reader structure"] +impl crate::Readable for ARG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`arg2::W`](W) writer structure"] impl crate::Writable for ARG2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/blksizecnt.rs b/crates/bcm2835-lpa/src/emmc/blksizecnt.rs index f3dabd8..c6eec15 100644 --- a/crates/bcm2835-lpa/src/emmc/blksizecnt.rs +++ b/crates/bcm2835-lpa/src/emmc/blksizecnt.rs @@ -1,47 +1,15 @@ #[doc = "Register `BLKSIZECNT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BLKSIZECNT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BLKSIZE` reader - Block size in bytes"] -pub type BLKSIZE_R = crate::FieldReader; +pub type BLKSIZE_R = crate::FieldReader; #[doc = "Field `BLKSIZE` writer - Block size in bytes"] -pub type BLKSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BLKSIZECNT_SPEC, u16, u16, 10, O>; +pub type BLKSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `BLKCNT` reader - Number of blocks to be transferred"] -pub type BLKCNT_R = crate::FieldReader; +pub type BLKCNT_R = crate::FieldReader; #[doc = "Field `BLKCNT` writer - Number of blocks to be transferred"] -pub type BLKCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BLKSIZECNT_SPEC, u16, u16, 16, O>; +pub type BLKCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:9 - Block size in bytes"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { BLKCNT_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLKSIZECNT") + .field("blkcnt", &format_args!("{}", self.blkcnt().bits())) + .field("blksize", &format_args!("{}", self.blksize().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:9 - Block size in bytes"] #[inline(always)] #[must_use] - pub fn blksize(&mut self) -> BLKSIZE_W<0> { + pub fn blksize(&mut self) -> BLKSIZE_W { BLKSIZE_W::new(self) } #[doc = "Bits 16:31 - Number of blocks to be transferred"] #[inline(always)] #[must_use] - pub fn blkcnt(&mut self) -> BLKCNT_W<16> { + pub fn blkcnt(&mut self) -> BLKCNT_W { BLKCNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Numer and size in bytes for data block to be transferred\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [blksizecnt](index.html) module"] +#[doc = "Numer and size in bytes for data block to be transferred\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blksizecnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blksizecnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BLKSIZECNT_SPEC; impl crate::RegisterSpec for BLKSIZECNT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [blksizecnt::R](R) reader structure"] -impl crate::Readable for BLKSIZECNT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [blksizecnt::W](W) writer structure"] +#[doc = "`read()` method returns [`blksizecnt::R`](R) reader structure"] +impl crate::Readable for BLKSIZECNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blksizecnt::W`](W) writer structure"] impl crate::Writable for BLKSIZECNT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/boot_timeout.rs b/crates/bcm2835-lpa/src/emmc/boot_timeout.rs index 5a9943a..41d8ff1 100644 --- a/crates/bcm2835-lpa/src/emmc/boot_timeout.rs +++ b/crates/bcm2835-lpa/src/emmc/boot_timeout.rs @@ -1,59 +1,38 @@ #[doc = "Register `BOOT_TIMEOUT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BOOT_TIMEOUT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Number of SD clock cycles to wait for boot\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [boot_timeout](index.html) module"] +#[doc = "Number of SD clock cycles to wait for boot\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`boot_timeout::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`boot_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BOOT_TIMEOUT_SPEC; impl crate::RegisterSpec for BOOT_TIMEOUT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [boot_timeout::R](R) reader structure"] -impl crate::Readable for BOOT_TIMEOUT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [boot_timeout::W](W) writer structure"] +#[doc = "`read()` method returns [`boot_timeout::R`](R) reader structure"] +impl crate::Readable for BOOT_TIMEOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot_timeout::W`](W) writer structure"] impl crate::Writable for BOOT_TIMEOUT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/cmdtm.rs b/crates/bcm2835-lpa/src/emmc/cmdtm.rs index e30a873..6ff28c8 100644 --- a/crates/bcm2835-lpa/src/emmc/cmdtm.rs +++ b/crates/bcm2835-lpa/src/emmc/cmdtm.rs @@ -1,45 +1,13 @@ #[doc = "Register `CMDTM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CMDTM` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TM_BLKCNT_EN` reader - Enable block counter"] -pub type TM_BLKCNT_EN_R = crate::BitReader; +pub type TM_BLKCNT_EN_R = crate::BitReader; #[doc = "Field `TM_BLKCNT_EN` writer - Enable block counter"] -pub type TM_BLKCNT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +pub type TM_BLKCNT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TM_AUTO_CMD_EN` reader - Command after completion"] -pub type TM_AUTO_CMD_EN_R = crate::FieldReader; +pub type TM_AUTO_CMD_EN_R = crate::FieldReader; #[doc = "Command after completion\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -57,10 +25,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for TM_AUTO_CMD_EN_A { + type Ux = u8; +} impl TM_AUTO_CMD_EN_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(TM_AUTO_CMD_EN_A::NONE), 1 => Some(TM_AUTO_CMD_EN_A::CMD12), @@ -68,39 +39,43 @@ impl TM_AUTO_CMD_EN_R { _ => None, } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_none(&self) -> bool { *self == TM_AUTO_CMD_EN_A::NONE } - #[doc = "Checks if the value of the field is `CMD12`"] + #[doc = "`1`"] #[inline(always)] pub fn is_cmd12(&self) -> bool { *self == TM_AUTO_CMD_EN_A::CMD12 } - #[doc = "Checks if the value of the field is `CMD23`"] + #[doc = "`10`"] #[inline(always)] pub fn is_cmd23(&self) -> bool { *self == TM_AUTO_CMD_EN_A::CMD23 } } #[doc = "Field `TM_AUTO_CMD_EN` writer - Command after completion"] -pub type TM_AUTO_CMD_EN_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, CMDTM_SPEC, u8, TM_AUTO_CMD_EN_A, 2, O>; -impl<'a, const O: u8> TM_AUTO_CMD_EN_W<'a, O> { +pub type TM_AUTO_CMD_EN_W<'a, REG, const O: u8> = + crate::FieldWriter<'a, REG, 2, O, TM_AUTO_CMD_EN_A>; +impl<'a, REG, const O: u8> TM_AUTO_CMD_EN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(TM_AUTO_CMD_EN_A::NONE) } #[doc = "`1`"] #[inline(always)] - pub fn cmd12(self) -> &'a mut W { + pub fn cmd12(self) -> &'a mut crate::W { self.variant(TM_AUTO_CMD_EN_A::CMD12) } #[doc = "`10`"] #[inline(always)] - pub fn cmd23(self) -> &'a mut W { + pub fn cmd23(self) -> &'a mut crate::W { self.variant(TM_AUTO_CMD_EN_A::CMD23) } } @@ -123,34 +98,37 @@ impl From for bool { impl TM_DAT_DIR_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TM_DAT_DIR_A { + pub const fn variant(&self) -> TM_DAT_DIR_A { match self.bits { false => TM_DAT_DIR_A::HOST_TO_CARD, true => TM_DAT_DIR_A::CARD_TO_HOST, } } - #[doc = "Checks if the value of the field is `HOST_TO_CARD`"] + #[doc = "`0`"] #[inline(always)] pub fn is_host_to_card(&self) -> bool { *self == TM_DAT_DIR_A::HOST_TO_CARD } - #[doc = "Checks if the value of the field is `CARD_TO_HOST`"] + #[doc = "`1`"] #[inline(always)] pub fn is_card_to_host(&self) -> bool { *self == TM_DAT_DIR_A::CARD_TO_HOST } } #[doc = "Field `TM_DAT_DIR` writer - Direction of data transfer"] -pub type TM_DAT_DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, TM_DAT_DIR_A, O>; -impl<'a, const O: u8> TM_DAT_DIR_W<'a, O> { +pub type TM_DAT_DIR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TM_DAT_DIR_A>; +impl<'a, REG, const O: u8> TM_DAT_DIR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn host_to_card(self) -> &'a mut W { + pub fn host_to_card(self) -> &'a mut crate::W { self.variant(TM_DAT_DIR_A::HOST_TO_CARD) } #[doc = "`1`"] #[inline(always)] - pub fn card_to_host(self) -> &'a mut W { + pub fn card_to_host(self) -> &'a mut crate::W { self.variant(TM_DAT_DIR_A::CARD_TO_HOST) } } @@ -173,40 +151,42 @@ impl From for bool { impl TM_MULTI_BLOCK_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TM_MULTI_BLOCK_A { + pub const fn variant(&self) -> TM_MULTI_BLOCK_A { match self.bits { false => TM_MULTI_BLOCK_A::SINGLE, true => TM_MULTI_BLOCK_A::MULTIPLE, } } - #[doc = "Checks if the value of the field is `SINGLE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_single(&self) -> bool { *self == TM_MULTI_BLOCK_A::SINGLE } - #[doc = "Checks if the value of the field is `MULTIPLE`"] + #[doc = "`1`"] #[inline(always)] pub fn is_multiple(&self) -> bool { *self == TM_MULTI_BLOCK_A::MULTIPLE } } #[doc = "Field `TM_MULTI_BLOCK` writer - Type of data transfer"] -pub type TM_MULTI_BLOCK_W<'a, const O: u8> = - crate::BitWriter<'a, u32, CMDTM_SPEC, TM_MULTI_BLOCK_A, O>; -impl<'a, const O: u8> TM_MULTI_BLOCK_W<'a, O> { +pub type TM_MULTI_BLOCK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TM_MULTI_BLOCK_A>; +impl<'a, REG, const O: u8> TM_MULTI_BLOCK_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn single(self) -> &'a mut W { + pub fn single(self) -> &'a mut crate::W { self.variant(TM_MULTI_BLOCK_A::SINGLE) } #[doc = "`1`"] #[inline(always)] - pub fn multiple(self) -> &'a mut W { + pub fn multiple(self) -> &'a mut crate::W { self.variant(TM_MULTI_BLOCK_A::MULTIPLE) } } #[doc = "Field `CMD_RSPNS_TYPE` reader - Type of expected response"] -pub type CMD_RSPNS_TYPE_R = crate::FieldReader; +pub type CMD_RSPNS_TYPE_R = crate::FieldReader; #[doc = "Type of expected response\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -226,10 +206,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for RESPONSE_A { + type Ux = u8; +} impl CMD_RSPNS_TYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RESPONSE_A { + pub const fn variant(&self) -> RESPONSE_A { match self.bits { 0 => RESPONSE_A::NONE, 1 => RESPONSE_A::_136BITS, @@ -238,66 +221,69 @@ impl CMD_RSPNS_TYPE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_none(&self) -> bool { *self == RESPONSE_A::NONE } - #[doc = "Checks if the value of the field is `_136BITS`"] + #[doc = "`1`"] #[inline(always)] pub fn is_136bits(&self) -> bool { *self == RESPONSE_A::_136BITS } - #[doc = "Checks if the value of the field is `_48BITS`"] + #[doc = "`10`"] #[inline(always)] pub fn is_48bits(&self) -> bool { *self == RESPONSE_A::_48BITS } - #[doc = "Checks if the value of the field is `_48BITS_USING_BUSY`"] + #[doc = "`11`"] #[inline(always)] pub fn is_48bits_using_busy(&self) -> bool { *self == RESPONSE_A::_48BITS_USING_BUSY } } #[doc = "Field `CMD_RSPNS_TYPE` writer - Type of expected response"] -pub type CMD_RSPNS_TYPE_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, CMDTM_SPEC, u8, RESPONSE_A, 2, O>; -impl<'a, const O: u8> CMD_RSPNS_TYPE_W<'a, O> { +pub type CMD_RSPNS_TYPE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, RESPONSE_A>; +impl<'a, REG, const O: u8> CMD_RSPNS_TYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(RESPONSE_A::NONE) } #[doc = "`1`"] #[inline(always)] - pub fn _136bits(self) -> &'a mut W { + pub fn _136bits(self) -> &'a mut crate::W { self.variant(RESPONSE_A::_136BITS) } #[doc = "`10`"] #[inline(always)] - pub fn _48bits(self) -> &'a mut W { + pub fn _48bits(self) -> &'a mut crate::W { self.variant(RESPONSE_A::_48BITS) } #[doc = "`11`"] #[inline(always)] - pub fn _48bits_using_busy(self) -> &'a mut W { + pub fn _48bits_using_busy(self) -> &'a mut crate::W { self.variant(RESPONSE_A::_48BITS_USING_BUSY) } } #[doc = "Field `CMD_CRCCHK_EN` reader - Check the responses CRC"] -pub type CMD_CRCCHK_EN_R = crate::BitReader; +pub type CMD_CRCCHK_EN_R = crate::BitReader; #[doc = "Field `CMD_CRCCHK_EN` writer - Check the responses CRC"] -pub type CMD_CRCCHK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +pub type CMD_CRCCHK_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMD_IXCHK_EN` reader - Check that the response has the same command index"] -pub type CMD_IXCHK_EN_R = crate::BitReader; +pub type CMD_IXCHK_EN_R = crate::BitReader; #[doc = "Field `CMD_IXCHK_EN` writer - Check that the response has the same command index"] -pub type CMD_IXCHK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +pub type CMD_IXCHK_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMD_ISDATA` reader - Command involves data"] -pub type CMD_ISDATA_R = crate::BitReader; +pub type CMD_ISDATA_R = crate::BitReader; #[doc = "Field `CMD_ISDATA` writer - Command involves data"] -pub type CMD_ISDATA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +pub type CMD_ISDATA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMD_TYPE` reader - Type of command to be issued"] -pub type CMD_TYPE_R = crate::FieldReader; +pub type CMD_TYPE_R = crate::FieldReader; #[doc = "Type of command to be issued\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -317,10 +303,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for CMD_TYPE_A { + type Ux = u8; +} impl CMD_TYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> CMD_TYPE_A { + pub const fn variant(&self) -> CMD_TYPE_A { match self.bits { 0 => CMD_TYPE_A::NORMAL, 1 => CMD_TYPE_A::SUSPEND, @@ -329,56 +318,59 @@ impl CMD_TYPE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "`0`"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == CMD_TYPE_A::NORMAL } - #[doc = "Checks if the value of the field is `SUSPEND`"] + #[doc = "`1`"] #[inline(always)] pub fn is_suspend(&self) -> bool { *self == CMD_TYPE_A::SUSPEND } - #[doc = "Checks if the value of the field is `RESUME`"] + #[doc = "`10`"] #[inline(always)] pub fn is_resume(&self) -> bool { *self == CMD_TYPE_A::RESUME } - #[doc = "Checks if the value of the field is `ABORT`"] + #[doc = "`11`"] #[inline(always)] pub fn is_abort(&self) -> bool { *self == CMD_TYPE_A::ABORT } } #[doc = "Field `CMD_TYPE` writer - Type of command to be issued"] -pub type CMD_TYPE_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, CMDTM_SPEC, u8, CMD_TYPE_A, 2, O>; -impl<'a, const O: u8> CMD_TYPE_W<'a, O> { +pub type CMD_TYPE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, CMD_TYPE_A>; +impl<'a, REG, const O: u8> CMD_TYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(CMD_TYPE_A::NORMAL) } #[doc = "`1`"] #[inline(always)] - pub fn suspend(self) -> &'a mut W { + pub fn suspend(self) -> &'a mut crate::W { self.variant(CMD_TYPE_A::SUSPEND) } #[doc = "`10`"] #[inline(always)] - pub fn resume(self) -> &'a mut W { + pub fn resume(self) -> &'a mut crate::W { self.variant(CMD_TYPE_A::RESUME) } #[doc = "`11`"] #[inline(always)] - pub fn abort(self) -> &'a mut W { + pub fn abort(self) -> &'a mut crate::W { self.variant(CMD_TYPE_A::ABORT) } } #[doc = "Field `CMD_INDEX` reader - Command index to be issued"] -pub type CMD_INDEX_R = crate::FieldReader; +pub type CMD_INDEX_R = crate::FieldReader; #[doc = "Field `CMD_INDEX` writer - Command index to be issued"] -pub type CMD_INDEX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMDTM_SPEC, u8, u8, 6, O>; +pub type CMD_INDEX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bit 1 - Enable block counter"] #[inline(always)] @@ -431,86 +423,126 @@ impl R { CMD_INDEX_R::new(((self.bits >> 24) & 0x3f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CMDTM") + .field("cmd_index", &format_args!("{}", self.cmd_index().bits())) + .field("cmd_type", &format_args!("{}", self.cmd_type().bits())) + .field("cmd_isdata", &format_args!("{}", self.cmd_isdata().bit())) + .field( + "cmd_ixchk_en", + &format_args!("{}", self.cmd_ixchk_en().bit()), + ) + .field( + "cmd_crcchk_en", + &format_args!("{}", self.cmd_crcchk_en().bit()), + ) + .field( + "cmd_rspns_type", + &format_args!("{}", self.cmd_rspns_type().bits()), + ) + .field( + "tm_multi_block", + &format_args!("{}", self.tm_multi_block().bit()), + ) + .field("tm_dat_dir", &format_args!("{}", self.tm_dat_dir().bit())) + .field( + "tm_auto_cmd_en", + &format_args!("{}", self.tm_auto_cmd_en().bits()), + ) + .field( + "tm_blkcnt_en", + &format_args!("{}", self.tm_blkcnt_en().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Enable block counter"] #[inline(always)] #[must_use] - pub fn tm_blkcnt_en(&mut self) -> TM_BLKCNT_EN_W<1> { + pub fn tm_blkcnt_en(&mut self) -> TM_BLKCNT_EN_W { TM_BLKCNT_EN_W::new(self) } #[doc = "Bits 2:3 - Command after completion"] #[inline(always)] #[must_use] - pub fn tm_auto_cmd_en(&mut self) -> TM_AUTO_CMD_EN_W<2> { + pub fn tm_auto_cmd_en(&mut self) -> TM_AUTO_CMD_EN_W { TM_AUTO_CMD_EN_W::new(self) } #[doc = "Bit 4 - Direction of data transfer"] #[inline(always)] #[must_use] - pub fn tm_dat_dir(&mut self) -> TM_DAT_DIR_W<4> { + pub fn tm_dat_dir(&mut self) -> TM_DAT_DIR_W { TM_DAT_DIR_W::new(self) } #[doc = "Bit 5 - Type of data transfer"] #[inline(always)] #[must_use] - pub fn tm_multi_block(&mut self) -> TM_MULTI_BLOCK_W<5> { + pub fn tm_multi_block(&mut self) -> TM_MULTI_BLOCK_W { TM_MULTI_BLOCK_W::new(self) } #[doc = "Bits 16:17 - Type of expected response"] #[inline(always)] #[must_use] - pub fn cmd_rspns_type(&mut self) -> CMD_RSPNS_TYPE_W<16> { + pub fn cmd_rspns_type(&mut self) -> CMD_RSPNS_TYPE_W { CMD_RSPNS_TYPE_W::new(self) } #[doc = "Bit 19 - Check the responses CRC"] #[inline(always)] #[must_use] - pub fn cmd_crcchk_en(&mut self) -> CMD_CRCCHK_EN_W<19> { + pub fn cmd_crcchk_en(&mut self) -> CMD_CRCCHK_EN_W { CMD_CRCCHK_EN_W::new(self) } #[doc = "Bit 20 - Check that the response has the same command index"] #[inline(always)] #[must_use] - pub fn cmd_ixchk_en(&mut self) -> CMD_IXCHK_EN_W<20> { + pub fn cmd_ixchk_en(&mut self) -> CMD_IXCHK_EN_W { CMD_IXCHK_EN_W::new(self) } #[doc = "Bit 21 - Command involves data"] #[inline(always)] #[must_use] - pub fn cmd_isdata(&mut self) -> CMD_ISDATA_W<21> { + pub fn cmd_isdata(&mut self) -> CMD_ISDATA_W { CMD_ISDATA_W::new(self) } #[doc = "Bits 22:23 - Type of command to be issued"] #[inline(always)] #[must_use] - pub fn cmd_type(&mut self) -> CMD_TYPE_W<22> { + pub fn cmd_type(&mut self) -> CMD_TYPE_W { CMD_TYPE_W::new(self) } #[doc = "Bits 24:29 - Command index to be issued"] #[inline(always)] #[must_use] - pub fn cmd_index(&mut self) -> CMD_INDEX_W<24> { + pub fn cmd_index(&mut self) -> CMD_INDEX_W { CMD_INDEX_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Issue commands to the card\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmdtm](index.html) module"] +#[doc = "Issue commands to the card\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdtm::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdtm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMDTM_SPEC; impl crate::RegisterSpec for CMDTM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cmdtm::R](R) reader structure"] -impl crate::Readable for CMDTM_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cmdtm::W](W) writer structure"] +#[doc = "`read()` method returns [`cmdtm::R`](R) reader structure"] +impl crate::Readable for CMDTM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmdtm::W`](W) writer structure"] impl crate::Writable for CMDTM_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/control0.rs b/crates/bcm2835-lpa/src/emmc/control0.rs index 948b94b..47fb08f 100644 --- a/crates/bcm2835-lpa/src/emmc/control0.rs +++ b/crates/bcm2835-lpa/src/emmc/control0.rs @@ -1,79 +1,47 @@ #[doc = "Register `CONTROL0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONTROL0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HCTL_DWIDTH` reader - Use 4 data lines"] -pub type HCTL_DWIDTH_R = crate::BitReader; +pub type HCTL_DWIDTH_R = crate::BitReader; #[doc = "Field `HCTL_DWIDTH` writer - Use 4 data lines"] -pub type HCTL_DWIDTH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type HCTL_DWIDTH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HCTL_HS_EN` reader - Enable high speed mode"] -pub type HCTL_HS_EN_R = crate::BitReader; +pub type HCTL_HS_EN_R = crate::BitReader; #[doc = "Field `HCTL_HS_EN` writer - Enable high speed mode"] -pub type HCTL_HS_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type HCTL_HS_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HCTL_8BIT` reader - Use 8 data lines"] -pub type HCTL_8BIT_R = crate::BitReader; +pub type HCTL_8BIT_R = crate::BitReader; #[doc = "Field `HCTL_8BIT` writer - Use 8 data lines"] -pub type HCTL_8BIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type HCTL_8BIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAP_STOP` reader - Stop the current transaction at the next block gap"] -pub type GAP_STOP_R = crate::BitReader; +pub type GAP_STOP_R = crate::BitReader; #[doc = "Field `GAP_STOP` writer - Stop the current transaction at the next block gap"] -pub type GAP_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type GAP_STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAP_RESTART` reader - Restart a transaction stopped by GAP_STOP"] -pub type GAP_RESTART_R = crate::BitReader; +pub type GAP_RESTART_R = crate::BitReader; #[doc = "Field `GAP_RESTART` writer - Restart a transaction stopped by GAP_STOP"] -pub type GAP_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type GAP_RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READWAIT_EN` reader - Use DAT2 read/wait protocol"] -pub type READWAIT_EN_R = crate::BitReader; +pub type READWAIT_EN_R = crate::BitReader; #[doc = "Field `READWAIT_EN` writer - Use DAT2 read/wait protocol"] -pub type READWAIT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type READWAIT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAP_IEN` reader - Enable interrupt on block gap"] -pub type GAP_IEN_R = crate::BitReader; +pub type GAP_IEN_R = crate::BitReader; #[doc = "Field `GAP_IEN` writer - Enable interrupt on block gap"] -pub type GAP_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type GAP_IEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_MODE` reader - Enable SPI mode"] -pub type SPI_MODE_R = crate::BitReader; +pub type SPI_MODE_R = crate::BitReader; #[doc = "Field `SPI_MODE` writer - Enable SPI mode"] -pub type SPI_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type SPI_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOT_EN` reader - Boot mode enabled"] -pub type BOOT_EN_R = crate::BitReader; +pub type BOOT_EN_R = crate::BitReader; #[doc = "Field `BOOT_EN` writer - Boot mode enabled"] -pub type BOOT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type BOOT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ALT_BOOT_EN` reader - Enable alternate boot mode"] -pub type ALT_BOOT_EN_R = crate::BitReader; +pub type ALT_BOOT_EN_R = crate::BitReader; #[doc = "Field `ALT_BOOT_EN` writer - Enable alternate boot mode"] -pub type ALT_BOOT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type ALT_BOOT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - Use 4 data lines"] #[inline(always)] @@ -126,86 +94,108 @@ impl R { ALT_BOOT_EN_R::new(((self.bits >> 22) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONTROL0") + .field("alt_boot_en", &format_args!("{}", self.alt_boot_en().bit())) + .field("boot_en", &format_args!("{}", self.boot_en().bit())) + .field("spi_mode", &format_args!("{}", self.spi_mode().bit())) + .field("gap_ien", &format_args!("{}", self.gap_ien().bit())) + .field("readwait_en", &format_args!("{}", self.readwait_en().bit())) + .field("gap_restart", &format_args!("{}", self.gap_restart().bit())) + .field("gap_stop", &format_args!("{}", self.gap_stop().bit())) + .field("hctl_8bit", &format_args!("{}", self.hctl_8bit().bit())) + .field("hctl_hs_en", &format_args!("{}", self.hctl_hs_en().bit())) + .field("hctl_dwidth", &format_args!("{}", self.hctl_dwidth().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Use 4 data lines"] #[inline(always)] #[must_use] - pub fn hctl_dwidth(&mut self) -> HCTL_DWIDTH_W<1> { + pub fn hctl_dwidth(&mut self) -> HCTL_DWIDTH_W { HCTL_DWIDTH_W::new(self) } #[doc = "Bit 2 - Enable high speed mode"] #[inline(always)] #[must_use] - pub fn hctl_hs_en(&mut self) -> HCTL_HS_EN_W<2> { + pub fn hctl_hs_en(&mut self) -> HCTL_HS_EN_W { HCTL_HS_EN_W::new(self) } #[doc = "Bit 5 - Use 8 data lines"] #[inline(always)] #[must_use] - pub fn hctl_8bit(&mut self) -> HCTL_8BIT_W<5> { + pub fn hctl_8bit(&mut self) -> HCTL_8BIT_W { HCTL_8BIT_W::new(self) } #[doc = "Bit 16 - Stop the current transaction at the next block gap"] #[inline(always)] #[must_use] - pub fn gap_stop(&mut self) -> GAP_STOP_W<16> { + pub fn gap_stop(&mut self) -> GAP_STOP_W { GAP_STOP_W::new(self) } #[doc = "Bit 17 - Restart a transaction stopped by GAP_STOP"] #[inline(always)] #[must_use] - pub fn gap_restart(&mut self) -> GAP_RESTART_W<17> { + pub fn gap_restart(&mut self) -> GAP_RESTART_W { GAP_RESTART_W::new(self) } #[doc = "Bit 18 - Use DAT2 read/wait protocol"] #[inline(always)] #[must_use] - pub fn readwait_en(&mut self) -> READWAIT_EN_W<18> { + pub fn readwait_en(&mut self) -> READWAIT_EN_W { READWAIT_EN_W::new(self) } #[doc = "Bit 19 - Enable interrupt on block gap"] #[inline(always)] #[must_use] - pub fn gap_ien(&mut self) -> GAP_IEN_W<19> { + pub fn gap_ien(&mut self) -> GAP_IEN_W { GAP_IEN_W::new(self) } #[doc = "Bit 20 - Enable SPI mode"] #[inline(always)] #[must_use] - pub fn spi_mode(&mut self) -> SPI_MODE_W<20> { + pub fn spi_mode(&mut self) -> SPI_MODE_W { SPI_MODE_W::new(self) } #[doc = "Bit 21 - Boot mode enabled"] #[inline(always)] #[must_use] - pub fn boot_en(&mut self) -> BOOT_EN_W<21> { + pub fn boot_en(&mut self) -> BOOT_EN_W { BOOT_EN_W::new(self) } #[doc = "Bit 22 - Enable alternate boot mode"] #[inline(always)] #[must_use] - pub fn alt_boot_en(&mut self) -> ALT_BOOT_EN_W<22> { + pub fn alt_boot_en(&mut self) -> ALT_BOOT_EN_W { ALT_BOOT_EN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control0](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONTROL0_SPEC; impl crate::RegisterSpec for CONTROL0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [control0::R](R) reader structure"] -impl crate::Readable for CONTROL0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [control0::W](W) writer structure"] +#[doc = "`read()` method returns [`control0::R`](R) reader structure"] +impl crate::Readable for CONTROL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`control0::W`](W) writer structure"] impl crate::Writable for CONTROL0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/control1.rs b/crates/bcm2835-lpa/src/emmc/control1.rs index 1dc7cb3..40a8765 100644 --- a/crates/bcm2835-lpa/src/emmc/control1.rs +++ b/crates/bcm2835-lpa/src/emmc/control1.rs @@ -1,49 +1,17 @@ #[doc = "Register `CONTROL1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONTROL1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLK_INTLEN` reader - Enable internal clock"] -pub type CLK_INTLEN_R = crate::BitReader; +pub type CLK_INTLEN_R = crate::BitReader; #[doc = "Field `CLK_INTLEN` writer - Enable internal clock"] -pub type CLK_INTLEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type CLK_INTLEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLK_STABLE` reader - SD Clock stable"] -pub type CLK_STABLE_R = crate::BitReader; +pub type CLK_STABLE_R = crate::BitReader; #[doc = "Field `CLK_EN` reader - SD Clock enable"] -pub type CLK_EN_R = crate::BitReader; +pub type CLK_EN_R = crate::BitReader; #[doc = "Field `CLK_EN` writer - SD Clock enable"] -pub type CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type CLK_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLK_GENSEL` reader - Mode of clock generation"] pub type CLK_GENSEL_R = crate::BitReader; #[doc = "Mode of clock generation\n\nValue on reset: 0"] @@ -63,61 +31,64 @@ impl From for bool { impl CLK_GENSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> CLK_GENSEL_A { + pub const fn variant(&self) -> CLK_GENSEL_A { match self.bits { false => CLK_GENSEL_A::DIVIDED, true => CLK_GENSEL_A::PROGRAMMABLE, } } - #[doc = "Checks if the value of the field is `DIVIDED`"] + #[doc = "`0`"] #[inline(always)] pub fn is_divided(&self) -> bool { *self == CLK_GENSEL_A::DIVIDED } - #[doc = "Checks if the value of the field is `PROGRAMMABLE`"] + #[doc = "`1`"] #[inline(always)] pub fn is_programmable(&self) -> bool { *self == CLK_GENSEL_A::PROGRAMMABLE } } #[doc = "Field `CLK_GENSEL` writer - Mode of clock generation"] -pub type CLK_GENSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, CLK_GENSEL_A, O>; -impl<'a, const O: u8> CLK_GENSEL_W<'a, O> { +pub type CLK_GENSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CLK_GENSEL_A>; +impl<'a, REG, const O: u8> CLK_GENSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn divided(self) -> &'a mut W { + pub fn divided(self) -> &'a mut crate::W { self.variant(CLK_GENSEL_A::DIVIDED) } #[doc = "`1`"] #[inline(always)] - pub fn programmable(self) -> &'a mut W { + pub fn programmable(self) -> &'a mut crate::W { self.variant(CLK_GENSEL_A::PROGRAMMABLE) } } #[doc = "Field `CLK_FREQ_MS2` reader - Clock base divider MSBs"] -pub type CLK_FREQ_MS2_R = crate::FieldReader; +pub type CLK_FREQ_MS2_R = crate::FieldReader; #[doc = "Field `CLK_FREQ_MS2` writer - Clock base divider MSBs"] -pub type CLK_FREQ_MS2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 2, O>; +pub type CLK_FREQ_MS2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `CLK_FREQ8` reader - Clock base divider LSB"] -pub type CLK_FREQ8_R = crate::FieldReader; +pub type CLK_FREQ8_R = crate::FieldReader; #[doc = "Field `CLK_FREQ8` writer - Clock base divider LSB"] -pub type CLK_FREQ8_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 8, O>; +pub type CLK_FREQ8_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DATA_TOUNIT` reader - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] -pub type DATA_TOUNIT_R = crate::FieldReader; +pub type DATA_TOUNIT_R = crate::FieldReader; #[doc = "Field `DATA_TOUNIT` writer - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] -pub type DATA_TOUNIT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 4, O>; +pub type DATA_TOUNIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `SRST_HC` reader - Reset the complete host circuit"] -pub type SRST_HC_R = crate::BitReader; +pub type SRST_HC_R = crate::BitReader; #[doc = "Field `SRST_HC` writer - Reset the complete host circuit"] -pub type SRST_HC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type SRST_HC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRST_CMD` reader - Reset the command handling circuit"] -pub type SRST_CMD_R = crate::BitReader; +pub type SRST_CMD_R = crate::BitReader; #[doc = "Field `SRST_CMD` writer - Reset the command handling circuit"] -pub type SRST_CMD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type SRST_CMD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRST_DATA` reader - Reset the data handling circuit"] -pub type SRST_DATA_R = crate::BitReader; +pub type SRST_DATA_R = crate::BitReader; #[doc = "Field `SRST_DATA` writer - Reset the data handling circuit"] -pub type SRST_DATA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type SRST_DATA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable internal clock"] #[inline(always)] @@ -170,80 +141,108 @@ impl R { SRST_DATA_R::new(((self.bits >> 26) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONTROL1") + .field("srst_data", &format_args!("{}", self.srst_data().bit())) + .field("srst_cmd", &format_args!("{}", self.srst_cmd().bit())) + .field("srst_hc", &format_args!("{}", self.srst_hc().bit())) + .field( + "data_tounit", + &format_args!("{}", self.data_tounit().bits()), + ) + .field("clk_freq8", &format_args!("{}", self.clk_freq8().bits())) + .field( + "clk_freq_ms2", + &format_args!("{}", self.clk_freq_ms2().bits()), + ) + .field("clk_gensel", &format_args!("{}", self.clk_gensel().bit())) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .field("clk_stable", &format_args!("{}", self.clk_stable().bit())) + .field("clk_intlen", &format_args!("{}", self.clk_intlen().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable internal clock"] #[inline(always)] #[must_use] - pub fn clk_intlen(&mut self) -> CLK_INTLEN_W<0> { + pub fn clk_intlen(&mut self) -> CLK_INTLEN_W { CLK_INTLEN_W::new(self) } #[doc = "Bit 2 - SD Clock enable"] #[inline(always)] #[must_use] - pub fn clk_en(&mut self) -> CLK_EN_W<2> { + pub fn clk_en(&mut self) -> CLK_EN_W { CLK_EN_W::new(self) } #[doc = "Bit 5 - Mode of clock generation"] #[inline(always)] #[must_use] - pub fn clk_gensel(&mut self) -> CLK_GENSEL_W<5> { + pub fn clk_gensel(&mut self) -> CLK_GENSEL_W { CLK_GENSEL_W::new(self) } #[doc = "Bits 6:7 - Clock base divider MSBs"] #[inline(always)] #[must_use] - pub fn clk_freq_ms2(&mut self) -> CLK_FREQ_MS2_W<6> { + pub fn clk_freq_ms2(&mut self) -> CLK_FREQ_MS2_W { CLK_FREQ_MS2_W::new(self) } #[doc = "Bits 8:15 - Clock base divider LSB"] #[inline(always)] #[must_use] - pub fn clk_freq8(&mut self) -> CLK_FREQ8_W<8> { + pub fn clk_freq8(&mut self) -> CLK_FREQ8_W { CLK_FREQ8_W::new(self) } #[doc = "Bits 16:19 - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] #[inline(always)] #[must_use] - pub fn data_tounit(&mut self) -> DATA_TOUNIT_W<16> { + pub fn data_tounit(&mut self) -> DATA_TOUNIT_W { DATA_TOUNIT_W::new(self) } #[doc = "Bit 24 - Reset the complete host circuit"] #[inline(always)] #[must_use] - pub fn srst_hc(&mut self) -> SRST_HC_W<24> { + pub fn srst_hc(&mut self) -> SRST_HC_W { SRST_HC_W::new(self) } #[doc = "Bit 25 - Reset the command handling circuit"] #[inline(always)] #[must_use] - pub fn srst_cmd(&mut self) -> SRST_CMD_W<25> { + pub fn srst_cmd(&mut self) -> SRST_CMD_W { SRST_CMD_W::new(self) } #[doc = "Bit 26 - Reset the data handling circuit"] #[inline(always)] #[must_use] - pub fn srst_data(&mut self) -> SRST_DATA_W<26> { + pub fn srst_data(&mut self) -> SRST_DATA_W { SRST_DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Configure\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control1](index.html) module"] +#[doc = "Configure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONTROL1_SPEC; impl crate::RegisterSpec for CONTROL1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [control1::R](R) reader structure"] -impl crate::Readable for CONTROL1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [control1::W](W) writer structure"] +#[doc = "`read()` method returns [`control1::R`](R) reader structure"] +impl crate::Readable for CONTROL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`control1::W`](W) writer structure"] impl crate::Writable for CONTROL1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/control2.rs b/crates/bcm2835-lpa/src/emmc/control2.rs index 1bc9076..bb052fc 100644 --- a/crates/bcm2835-lpa/src/emmc/control2.rs +++ b/crates/bcm2835-lpa/src/emmc/control2.rs @@ -1,53 +1,21 @@ #[doc = "Register `CONTROL2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONTROL2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ACNOX_ERR` reader - Auto command not executed due to an error"] -pub type ACNOX_ERR_R = crate::BitReader; +pub type ACNOX_ERR_R = crate::BitReader; #[doc = "Field `ACTO_ERR` reader - Auto command timeout"] -pub type ACTO_ERR_R = crate::BitReader; +pub type ACTO_ERR_R = crate::BitReader; #[doc = "Field `ACCRC_ERR` reader - Command CRC error during auto command"] -pub type ACCRC_ERR_R = crate::BitReader; +pub type ACCRC_ERR_R = crate::BitReader; #[doc = "Field `ACEND_ERR` reader - End bit is not 1 during auto command"] -pub type ACEND_ERR_R = crate::BitReader; +pub type ACEND_ERR_R = crate::BitReader; #[doc = "Field `ACBAD_ERR` reader - Command index error during auto command"] -pub type ACBAD_ERR_R = crate::BitReader; +pub type ACBAD_ERR_R = crate::BitReader; #[doc = "Field `NOTC12_ERR` reader - Error during auto CMD12"] -pub type NOTC12_ERR_R = crate::BitReader; +pub type NOTC12_ERR_R = crate::BitReader; #[doc = "Field `UHSMODE` reader - Select the speed of the SD card"] -pub type UHSMODE_R = crate::FieldReader; +pub type UHSMODE_R = crate::FieldReader; #[doc = "Select the speed of the SD card\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -69,10 +37,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for UHSMODE_A { + type Ux = u8; +} impl UHSMODE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(UHSMODE_A::SDR12), 1 => Some(UHSMODE_A::SDR25), @@ -82,70 +53,73 @@ impl UHSMODE_R { _ => None, } } - #[doc = "Checks if the value of the field is `SDR12`"] + #[doc = "`0`"] #[inline(always)] pub fn is_sdr12(&self) -> bool { *self == UHSMODE_A::SDR12 } - #[doc = "Checks if the value of the field is `SDR25`"] + #[doc = "`1`"] #[inline(always)] pub fn is_sdr25(&self) -> bool { *self == UHSMODE_A::SDR25 } - #[doc = "Checks if the value of the field is `SDR50`"] + #[doc = "`10`"] #[inline(always)] pub fn is_sdr50(&self) -> bool { *self == UHSMODE_A::SDR50 } - #[doc = "Checks if the value of the field is `SDR104`"] + #[doc = "`11`"] #[inline(always)] pub fn is_sdr104(&self) -> bool { *self == UHSMODE_A::SDR104 } - #[doc = "Checks if the value of the field is `DDR50`"] + #[doc = "`100`"] #[inline(always)] pub fn is_ddr50(&self) -> bool { *self == UHSMODE_A::DDR50 } } #[doc = "Field `UHSMODE` writer - Select the speed of the SD card"] -pub type UHSMODE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, CONTROL2_SPEC, u8, UHSMODE_A, 3, O>; -impl<'a, const O: u8> UHSMODE_W<'a, O> { +pub type UHSMODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, UHSMODE_A>; +impl<'a, REG, const O: u8> UHSMODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn sdr12(self) -> &'a mut W { + pub fn sdr12(self) -> &'a mut crate::W { self.variant(UHSMODE_A::SDR12) } #[doc = "`1`"] #[inline(always)] - pub fn sdr25(self) -> &'a mut W { + pub fn sdr25(self) -> &'a mut crate::W { self.variant(UHSMODE_A::SDR25) } #[doc = "`10`"] #[inline(always)] - pub fn sdr50(self) -> &'a mut W { + pub fn sdr50(self) -> &'a mut crate::W { self.variant(UHSMODE_A::SDR50) } #[doc = "`11`"] #[inline(always)] - pub fn sdr104(self) -> &'a mut W { + pub fn sdr104(self) -> &'a mut crate::W { self.variant(UHSMODE_A::SDR104) } #[doc = "`100`"] #[inline(always)] - pub fn ddr50(self) -> &'a mut W { + pub fn ddr50(self) -> &'a mut crate::W { self.variant(UHSMODE_A::DDR50) } } #[doc = "Field `TUNEON` reader - SD Clock tune in progress"] -pub type TUNEON_R = crate::BitReader; +pub type TUNEON_R = crate::BitReader; #[doc = "Field `TUNEON` writer - SD Clock tune in progress"] -pub type TUNEON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL2_SPEC, bool, O>; +pub type TUNEON_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TUNED` reader - Tuned clock is used for sampling data"] -pub type TUNED_R = crate::BitReader; +pub type TUNED_R = crate::BitReader; #[doc = "Field `TUNED` writer - Tuned clock is used for sampling data"] -pub type TUNED_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL2_SPEC, bool, O>; +pub type TUNED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Auto command not executed due to an error"] #[inline(always)] @@ -193,44 +167,65 @@ impl R { TUNED_R::new(((self.bits >> 23) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONTROL2") + .field("tuned", &format_args!("{}", self.tuned().bit())) + .field("tuneon", &format_args!("{}", self.tuneon().bit())) + .field("uhsmode", &format_args!("{}", self.uhsmode().bits())) + .field("notc12_err", &format_args!("{}", self.notc12_err().bit())) + .field("acbad_err", &format_args!("{}", self.acbad_err().bit())) + .field("acend_err", &format_args!("{}", self.acend_err().bit())) + .field("accrc_err", &format_args!("{}", self.accrc_err().bit())) + .field("acto_err", &format_args!("{}", self.acto_err().bit())) + .field("acnox_err", &format_args!("{}", self.acnox_err().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 16:18 - Select the speed of the SD card"] #[inline(always)] #[must_use] - pub fn uhsmode(&mut self) -> UHSMODE_W<16> { + pub fn uhsmode(&mut self) -> UHSMODE_W { UHSMODE_W::new(self) } #[doc = "Bit 22 - SD Clock tune in progress"] #[inline(always)] #[must_use] - pub fn tuneon(&mut self) -> TUNEON_W<22> { + pub fn tuneon(&mut self) -> TUNEON_W { TUNEON_W::new(self) } #[doc = "Bit 23 - Tuned clock is used for sampling data"] #[inline(always)] #[must_use] - pub fn tuned(&mut self) -> TUNED_W<23> { + pub fn tuned(&mut self) -> TUNED_W { TUNED_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control2](index.html) module"] +#[doc = "Control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONTROL2_SPEC; impl crate::RegisterSpec for CONTROL2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [control2::R](R) reader structure"] -impl crate::Readable for CONTROL2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [control2::W](W) writer structure"] +#[doc = "`read()` method returns [`control2::R`](R) reader structure"] +impl crate::Readable for CONTROL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`control2::W`](W) writer structure"] impl crate::Writable for CONTROL2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/data.rs b/crates/bcm2835-lpa/src/emmc/data.rs index 8c082b8..ac2280f 100644 --- a/crates/bcm2835-lpa/src/emmc/data.rs +++ b/crates/bcm2835-lpa/src/emmc/data.rs @@ -1,59 +1,38 @@ #[doc = "Register `DATA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DATA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data to/from the card\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +#[doc = "Data to/from the card\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DATA_SPEC; impl crate::RegisterSpec for DATA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [data::R](R) reader structure"] -impl crate::Readable for DATA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] impl crate::Writable for DATA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/dbg_sel.rs b/crates/bcm2835-lpa/src/emmc/dbg_sel.rs index c489a27..343a4db 100644 --- a/crates/bcm2835-lpa/src/emmc/dbg_sel.rs +++ b/crates/bcm2835-lpa/src/emmc/dbg_sel.rs @@ -1,39 +1,7 @@ #[doc = "Register `DBG_SEL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DBG_SEL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SELECT` reader - "] pub type SELECT_R = crate::BitReader; #[doc = "\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl SELECT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SELECT_A { + pub const fn variant(&self) -> SELECT_A { match self.bits { false => SELECT_A::RECEIVER_FIFO, true => SELECT_A::OTHERS, } } - #[doc = "Checks if the value of the field is `RECEIVER_FIFO`"] + #[doc = "`0`"] #[inline(always)] pub fn is_receiver_fifo(&self) -> bool { *self == SELECT_A::RECEIVER_FIFO } - #[doc = "Checks if the value of the field is `OTHERS`"] + #[doc = "`1`"] #[inline(always)] pub fn is_others(&self) -> bool { *self == SELECT_A::OTHERS } } #[doc = "Field `SELECT` writer - "] -pub type SELECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DBG_SEL_SPEC, SELECT_A, O>; -impl<'a, const O: u8> SELECT_W<'a, O> { +pub type SELECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SELECT_A>; +impl<'a, REG, const O: u8> SELECT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn receiver_fifo(self) -> &'a mut W { + pub fn receiver_fifo(self) -> &'a mut crate::W { self.variant(SELECT_A::RECEIVER_FIFO) } #[doc = "`1`"] #[inline(always)] - pub fn others(self) -> &'a mut W { + pub fn others(self) -> &'a mut crate::W { self.variant(SELECT_A::OTHERS) } } @@ -91,32 +62,45 @@ impl R { SELECT_R::new((self.bits & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBG_SEL") + .field("select", &format_args!("{}", self.select().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn select(&mut self) -> SELECT_W<0> { + pub fn select(&mut self) -> SELECT_W { SELECT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "What submodules are accessed by the debug bus\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbg_sel](index.html) module"] +#[doc = "What submodules are accessed by the debug bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbg_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DBG_SEL_SPEC; impl crate::RegisterSpec for DBG_SEL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dbg_sel::R](R) reader structure"] -impl crate::Readable for DBG_SEL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dbg_sel::W](W) writer structure"] +#[doc = "`read()` method returns [`dbg_sel::R`](R) reader structure"] +impl crate::Readable for DBG_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbg_sel::W`](W) writer structure"] impl crate::Writable for DBG_SEL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/exrdfifo_cfg.rs b/crates/bcm2835-lpa/src/emmc/exrdfifo_cfg.rs index 1c7e3be..13440a1 100644 --- a/crates/bcm2835-lpa/src/emmc/exrdfifo_cfg.rs +++ b/crates/bcm2835-lpa/src/emmc/exrdfifo_cfg.rs @@ -1,43 +1,11 @@ #[doc = "Register `EXRDFIFO_CFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EXRDFIFO_CFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RD_THRSH` reader - Read threshold in 32 bit words"] -pub type RD_THRSH_R = crate::FieldReader; +pub type RD_THRSH_R = crate::FieldReader; #[doc = "Field `RD_THRSH` writer - Read threshold in 32 bit words"] -pub type RD_THRSH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXRDFIFO_CFG_SPEC, u8, u8, 3, O>; +pub type RD_THRSH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:2 - Read threshold in 32 bit words"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { RD_THRSH_R::new((self.bits & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXRDFIFO_CFG") + .field("rd_thrsh", &format_args!("{}", self.rd_thrsh().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Read threshold in 32 bit words"] #[inline(always)] #[must_use] - pub fn rd_thrsh(&mut self) -> RD_THRSH_W<0> { + pub fn rd_thrsh(&mut self) -> RD_THRSH_W { RD_THRSH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Fine tune DMA request generation\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exrdfifo_cfg](index.html) module"] +#[doc = "Fine tune DMA request generation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exrdfifo_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrdfifo_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EXRDFIFO_CFG_SPEC; impl crate::RegisterSpec for EXRDFIFO_CFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [exrdfifo_cfg::R](R) reader structure"] -impl crate::Readable for EXRDFIFO_CFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [exrdfifo_cfg::W](W) writer structure"] +#[doc = "`read()` method returns [`exrdfifo_cfg::R`](R) reader structure"] +impl crate::Readable for EXRDFIFO_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`exrdfifo_cfg::W`](W) writer structure"] impl crate::Writable for EXRDFIFO_CFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/exrdfifo_en.rs b/crates/bcm2835-lpa/src/emmc/exrdfifo_en.rs index 26c7adc..e6b6583 100644 --- a/crates/bcm2835-lpa/src/emmc/exrdfifo_en.rs +++ b/crates/bcm2835-lpa/src/emmc/exrdfifo_en.rs @@ -1,43 +1,11 @@ #[doc = "Register `EXRDFIFO_EN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EXRDFIFO_EN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ENABLE` reader - Enable the extension FIFO"] -pub type ENABLE_R = crate::BitReader; +pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Enable the extension FIFO"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXRDFIFO_EN_SPEC, bool, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable the extension FIFO"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { ENABLE_R::new((self.bits & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXRDFIFO_EN") + .field("enable", &format_args!("{}", self.enable().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable the extension FIFO"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<0> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable the extension data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exrdfifo_en](index.html) module"] +#[doc = "Enable the extension data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exrdfifo_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrdfifo_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EXRDFIFO_EN_SPEC; impl crate::RegisterSpec for EXRDFIFO_EN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [exrdfifo_en::R](R) reader structure"] -impl crate::Readable for EXRDFIFO_EN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [exrdfifo_en::W](W) writer structure"] +#[doc = "`read()` method returns [`exrdfifo_en::R`](R) reader structure"] +impl crate::Readable for EXRDFIFO_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`exrdfifo_en::W`](W) writer structure"] impl crate::Writable for EXRDFIFO_EN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/force_irpt.rs b/crates/bcm2835-lpa/src/emmc/force_irpt.rs index eca9ec6..682b8fe 100644 --- a/crates/bcm2835-lpa/src/emmc/force_irpt.rs +++ b/crates/bcm2835-lpa/src/emmc/force_irpt.rs @@ -1,107 +1,75 @@ #[doc = "Register `FORCE_IRPT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FORCE_IRPT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_DONE` reader - Command has finished"] -pub type CMD_DONE_R = crate::BitReader; +pub type CMD_DONE_R = crate::BitReader; #[doc = "Field `CMD_DONE` writer - Command has finished"] -pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CMD_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_DONE` reader - Data transfer has finished"] -pub type DATA_DONE_R = crate::BitReader; +pub type DATA_DONE_R = crate::BitReader; #[doc = "Field `DATA_DONE` writer - Data transfer has finished"] -pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type DATA_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_R = crate::BitReader; +pub type BLOCK_GAP_R = crate::BitReader; #[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type BLOCK_GAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_RDY` reader - DATA can be written to"] -pub type WRITE_RDY_R = crate::BitReader; +pub type WRITE_RDY_R = crate::BitReader; #[doc = "Field `WRITE_RDY` writer - DATA can be written to"] -pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type WRITE_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_RDY` reader - DATA contains data to be read"] -pub type READ_RDY_R = crate::BitReader; +pub type READ_RDY_R = crate::BitReader; #[doc = "Field `READ_RDY` writer - DATA contains data to be read"] -pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type READ_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CARD` reader - Card made interrupt request"] -pub type CARD_R = crate::BitReader; +pub type CARD_R = crate::BitReader; #[doc = "Field `CARD` writer - Card made interrupt request"] -pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CARD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RETUNE` reader - Clock retune request"] -pub type RETUNE_R = crate::BitReader; +pub type RETUNE_R = crate::BitReader; #[doc = "Field `RETUNE` writer - Clock retune request"] -pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type RETUNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] -pub type BOOTACK_R = crate::BitReader; +pub type BOOTACK_R = crate::BitReader; #[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] -pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type BOOTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] -pub type ENDBOOT_R = crate::BitReader; +pub type ENDBOOT_R = crate::BitReader; #[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] -pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type ENDBOOT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTO_ERR` reader - Command timeout"] -pub type CTO_ERR_R = crate::BitReader; +pub type CTO_ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` writer - Command timeout"] -pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CCRC_ERR` reader - Command CRC error"] -pub type CCRC_ERR_R = crate::BitReader; +pub type CCRC_ERR_R = crate::BitReader; #[doc = "Field `CCRC_ERR` writer - Command CRC error"] -pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] -pub type CEND_ERR_R = crate::BitReader; +pub type CEND_ERR_R = crate::BitReader; #[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] -pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] -pub type CBAD_ERR_R = crate::BitReader; +pub type CBAD_ERR_R = crate::BitReader; #[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] -pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CBAD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTO_ERR` reader - Data timeout"] -pub type DTO_ERR_R = crate::BitReader; +pub type DTO_ERR_R = crate::BitReader; #[doc = "Field `DTO_ERR` writer - Data timeout"] -pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type DTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRC_ERR` reader - Data CRC error"] -pub type DCRC_ERR_R = crate::BitReader; +pub type DCRC_ERR_R = crate::BitReader; #[doc = "Field `DCRC_ERR` writer - Data CRC error"] -pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type DCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] -pub type DEND_ERR_R = crate::BitReader; +pub type DEND_ERR_R = crate::BitReader; #[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] -pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type DEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMD_ERR` reader - Auto command error"] -pub type ACMD_ERR_R = crate::BitReader; +pub type ACMD_ERR_R = crate::BitReader; #[doc = "Field `ACMD_ERR` writer - Auto command error"] -pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type ACMD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Command has finished"] #[inline(always)] @@ -189,128 +157,157 @@ impl R { ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FORCE_IRPT") + .field("acmd_err", &format_args!("{}", self.acmd_err().bit())) + .field("dend_err", &format_args!("{}", self.dend_err().bit())) + .field("dcrc_err", &format_args!("{}", self.dcrc_err().bit())) + .field("dto_err", &format_args!("{}", self.dto_err().bit())) + .field("cbad_err", &format_args!("{}", self.cbad_err().bit())) + .field("cend_err", &format_args!("{}", self.cend_err().bit())) + .field("ccrc_err", &format_args!("{}", self.ccrc_err().bit())) + .field("cto_err", &format_args!("{}", self.cto_err().bit())) + .field("endboot", &format_args!("{}", self.endboot().bit())) + .field("bootack", &format_args!("{}", self.bootack().bit())) + .field("retune", &format_args!("{}", self.retune().bit())) + .field("card", &format_args!("{}", self.card().bit())) + .field("read_rdy", &format_args!("{}", self.read_rdy().bit())) + .field("write_rdy", &format_args!("{}", self.write_rdy().bit())) + .field("block_gap", &format_args!("{}", self.block_gap().bit())) + .field("data_done", &format_args!("{}", self.data_done().bit())) + .field("cmd_done", &format_args!("{}", self.cmd_done().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command has finished"] #[inline(always)] #[must_use] - pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + pub fn cmd_done(&mut self) -> CMD_DONE_W { CMD_DONE_W::new(self) } #[doc = "Bit 1 - Data transfer has finished"] #[inline(always)] #[must_use] - pub fn data_done(&mut self) -> DATA_DONE_W<1> { + pub fn data_done(&mut self) -> DATA_DONE_W { DATA_DONE_W::new(self) } #[doc = "Bit 2 - Data transfer has stopped at block gap"] #[inline(always)] #[must_use] - pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + pub fn block_gap(&mut self) -> BLOCK_GAP_W { BLOCK_GAP_W::new(self) } #[doc = "Bit 4 - DATA can be written to"] #[inline(always)] #[must_use] - pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + pub fn write_rdy(&mut self) -> WRITE_RDY_W { WRITE_RDY_W::new(self) } #[doc = "Bit 5 - DATA contains data to be read"] #[inline(always)] #[must_use] - pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + pub fn read_rdy(&mut self) -> READ_RDY_W { READ_RDY_W::new(self) } #[doc = "Bit 8 - Card made interrupt request"] #[inline(always)] #[must_use] - pub fn card(&mut self) -> CARD_W<8> { + pub fn card(&mut self) -> CARD_W { CARD_W::new(self) } #[doc = "Bit 12 - Clock retune request"] #[inline(always)] #[must_use] - pub fn retune(&mut self) -> RETUNE_W<12> { + pub fn retune(&mut self) -> RETUNE_W { RETUNE_W::new(self) } #[doc = "Bit 13 - Boot has been acknowledged"] #[inline(always)] #[must_use] - pub fn bootack(&mut self) -> BOOTACK_W<13> { + pub fn bootack(&mut self) -> BOOTACK_W { BOOTACK_W::new(self) } #[doc = "Bit 14 - Boot operation has terminated"] #[inline(always)] #[must_use] - pub fn endboot(&mut self) -> ENDBOOT_W<14> { + pub fn endboot(&mut self) -> ENDBOOT_W { ENDBOOT_W::new(self) } #[doc = "Bit 16 - Command timeout"] #[inline(always)] #[must_use] - pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + pub fn cto_err(&mut self) -> CTO_ERR_W { CTO_ERR_W::new(self) } #[doc = "Bit 17 - Command CRC error"] #[inline(always)] #[must_use] - pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + pub fn ccrc_err(&mut self) -> CCRC_ERR_W { CCRC_ERR_W::new(self) } #[doc = "Bit 18 - Command end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + pub fn cend_err(&mut self) -> CEND_ERR_W { CEND_ERR_W::new(self) } #[doc = "Bit 19 - Incorrect response command index"] #[inline(always)] #[must_use] - pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + pub fn cbad_err(&mut self) -> CBAD_ERR_W { CBAD_ERR_W::new(self) } #[doc = "Bit 20 - Data timeout"] #[inline(always)] #[must_use] - pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + pub fn dto_err(&mut self) -> DTO_ERR_W { DTO_ERR_W::new(self) } #[doc = "Bit 21 - Data CRC error"] #[inline(always)] #[must_use] - pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + pub fn dcrc_err(&mut self) -> DCRC_ERR_W { DCRC_ERR_W::new(self) } #[doc = "Bit 22 - Data end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + pub fn dend_err(&mut self) -> DEND_ERR_W { DEND_ERR_W::new(self) } #[doc = "Bit 24 - Auto command error"] #[inline(always)] #[must_use] - pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + pub fn acmd_err(&mut self) -> ACMD_ERR_W { ACMD_ERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Force an interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [force_irpt](index.html) module"] +#[doc = "Force an interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`force_irpt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`force_irpt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FORCE_IRPT_SPEC; impl crate::RegisterSpec for FORCE_IRPT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [force_irpt::R](R) reader structure"] -impl crate::Readable for FORCE_IRPT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [force_irpt::W](W) writer structure"] +#[doc = "`read()` method returns [`force_irpt::R`](R) reader structure"] +impl crate::Readable for FORCE_IRPT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`force_irpt::W`](W) writer structure"] impl crate::Writable for FORCE_IRPT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/interrupt.rs b/crates/bcm2835-lpa/src/emmc/interrupt.rs index c687814..c28598f 100644 --- a/crates/bcm2835-lpa/src/emmc/interrupt.rs +++ b/crates/bcm2835-lpa/src/emmc/interrupt.rs @@ -1,109 +1,77 @@ #[doc = "Register `INTERRUPT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERRUPT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_DONE` reader - Command has finished"] -pub type CMD_DONE_R = crate::BitReader; +pub type CMD_DONE_R = crate::BitReader; #[doc = "Field `CMD_DONE` writer - Command has finished"] -pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CMD_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_DONE` reader - Data transfer has finished"] -pub type DATA_DONE_R = crate::BitReader; +pub type DATA_DONE_R = crate::BitReader; #[doc = "Field `DATA_DONE` writer - Data transfer has finished"] -pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type DATA_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_R = crate::BitReader; +pub type BLOCK_GAP_R = crate::BitReader; #[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type BLOCK_GAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_RDY` reader - DATA can be written to"] -pub type WRITE_RDY_R = crate::BitReader; +pub type WRITE_RDY_R = crate::BitReader; #[doc = "Field `WRITE_RDY` writer - DATA can be written to"] -pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type WRITE_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_RDY` reader - DATA contains data to be read"] -pub type READ_RDY_R = crate::BitReader; +pub type READ_RDY_R = crate::BitReader; #[doc = "Field `READ_RDY` writer - DATA contains data to be read"] -pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type READ_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CARD` reader - Card made interrupt request"] -pub type CARD_R = crate::BitReader; +pub type CARD_R = crate::BitReader; #[doc = "Field `CARD` writer - Card made interrupt request"] -pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CARD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RETUNE` reader - Clock retune request"] -pub type RETUNE_R = crate::BitReader; +pub type RETUNE_R = crate::BitReader; #[doc = "Field `RETUNE` writer - Clock retune request"] -pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type RETUNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] -pub type BOOTACK_R = crate::BitReader; +pub type BOOTACK_R = crate::BitReader; #[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] -pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type BOOTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] -pub type ENDBOOT_R = crate::BitReader; +pub type ENDBOOT_R = crate::BitReader; #[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] -pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type ENDBOOT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERR` reader - An error has occured"] -pub type ERR_R = crate::BitReader; +pub type ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` reader - Command timeout"] -pub type CTO_ERR_R = crate::BitReader; +pub type CTO_ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` writer - Command timeout"] -pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CCRC_ERR` reader - Command CRC error"] -pub type CCRC_ERR_R = crate::BitReader; +pub type CCRC_ERR_R = crate::BitReader; #[doc = "Field `CCRC_ERR` writer - Command CRC error"] -pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] -pub type CEND_ERR_R = crate::BitReader; +pub type CEND_ERR_R = crate::BitReader; #[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] -pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] -pub type CBAD_ERR_R = crate::BitReader; +pub type CBAD_ERR_R = crate::BitReader; #[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] -pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CBAD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTO_ERR` reader - Data timeout"] -pub type DTO_ERR_R = crate::BitReader; +pub type DTO_ERR_R = crate::BitReader; #[doc = "Field `DTO_ERR` writer - Data timeout"] -pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type DTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRC_ERR` reader - Data CRC error"] -pub type DCRC_ERR_R = crate::BitReader; +pub type DCRC_ERR_R = crate::BitReader; #[doc = "Field `DCRC_ERR` writer - Data CRC error"] -pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type DCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] -pub type DEND_ERR_R = crate::BitReader; +pub type DEND_ERR_R = crate::BitReader; #[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] -pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type DEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMD_ERR` reader - Auto command error"] -pub type ACMD_ERR_R = crate::BitReader; +pub type ACMD_ERR_R = crate::BitReader; #[doc = "Field `ACMD_ERR` writer - Auto command error"] -pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type ACMD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Command has finished"] #[inline(always)] @@ -196,128 +164,158 @@ impl R { ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTERRUPT") + .field("acmd_err", &format_args!("{}", self.acmd_err().bit())) + .field("dend_err", &format_args!("{}", self.dend_err().bit())) + .field("dcrc_err", &format_args!("{}", self.dcrc_err().bit())) + .field("dto_err", &format_args!("{}", self.dto_err().bit())) + .field("cbad_err", &format_args!("{}", self.cbad_err().bit())) + .field("cend_err", &format_args!("{}", self.cend_err().bit())) + .field("ccrc_err", &format_args!("{}", self.ccrc_err().bit())) + .field("cto_err", &format_args!("{}", self.cto_err().bit())) + .field("err", &format_args!("{}", self.err().bit())) + .field("endboot", &format_args!("{}", self.endboot().bit())) + .field("bootack", &format_args!("{}", self.bootack().bit())) + .field("retune", &format_args!("{}", self.retune().bit())) + .field("card", &format_args!("{}", self.card().bit())) + .field("read_rdy", &format_args!("{}", self.read_rdy().bit())) + .field("write_rdy", &format_args!("{}", self.write_rdy().bit())) + .field("block_gap", &format_args!("{}", self.block_gap().bit())) + .field("data_done", &format_args!("{}", self.data_done().bit())) + .field("cmd_done", &format_args!("{}", self.cmd_done().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command has finished"] #[inline(always)] #[must_use] - pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + pub fn cmd_done(&mut self) -> CMD_DONE_W { CMD_DONE_W::new(self) } #[doc = "Bit 1 - Data transfer has finished"] #[inline(always)] #[must_use] - pub fn data_done(&mut self) -> DATA_DONE_W<1> { + pub fn data_done(&mut self) -> DATA_DONE_W { DATA_DONE_W::new(self) } #[doc = "Bit 2 - Data transfer has stopped at block gap"] #[inline(always)] #[must_use] - pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + pub fn block_gap(&mut self) -> BLOCK_GAP_W { BLOCK_GAP_W::new(self) } #[doc = "Bit 4 - DATA can be written to"] #[inline(always)] #[must_use] - pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + pub fn write_rdy(&mut self) -> WRITE_RDY_W { WRITE_RDY_W::new(self) } #[doc = "Bit 5 - DATA contains data to be read"] #[inline(always)] #[must_use] - pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + pub fn read_rdy(&mut self) -> READ_RDY_W { READ_RDY_W::new(self) } #[doc = "Bit 8 - Card made interrupt request"] #[inline(always)] #[must_use] - pub fn card(&mut self) -> CARD_W<8> { + pub fn card(&mut self) -> CARD_W { CARD_W::new(self) } #[doc = "Bit 12 - Clock retune request"] #[inline(always)] #[must_use] - pub fn retune(&mut self) -> RETUNE_W<12> { + pub fn retune(&mut self) -> RETUNE_W { RETUNE_W::new(self) } #[doc = "Bit 13 - Boot has been acknowledged"] #[inline(always)] #[must_use] - pub fn bootack(&mut self) -> BOOTACK_W<13> { + pub fn bootack(&mut self) -> BOOTACK_W { BOOTACK_W::new(self) } #[doc = "Bit 14 - Boot operation has terminated"] #[inline(always)] #[must_use] - pub fn endboot(&mut self) -> ENDBOOT_W<14> { + pub fn endboot(&mut self) -> ENDBOOT_W { ENDBOOT_W::new(self) } #[doc = "Bit 16 - Command timeout"] #[inline(always)] #[must_use] - pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + pub fn cto_err(&mut self) -> CTO_ERR_W { CTO_ERR_W::new(self) } #[doc = "Bit 17 - Command CRC error"] #[inline(always)] #[must_use] - pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + pub fn ccrc_err(&mut self) -> CCRC_ERR_W { CCRC_ERR_W::new(self) } #[doc = "Bit 18 - Command end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + pub fn cend_err(&mut self) -> CEND_ERR_W { CEND_ERR_W::new(self) } #[doc = "Bit 19 - Incorrect response command index"] #[inline(always)] #[must_use] - pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + pub fn cbad_err(&mut self) -> CBAD_ERR_W { CBAD_ERR_W::new(self) } #[doc = "Bit 20 - Data timeout"] #[inline(always)] #[must_use] - pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + pub fn dto_err(&mut self) -> DTO_ERR_W { DTO_ERR_W::new(self) } #[doc = "Bit 21 - Data CRC error"] #[inline(always)] #[must_use] - pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + pub fn dcrc_err(&mut self) -> DCRC_ERR_W { DCRC_ERR_W::new(self) } #[doc = "Bit 22 - Data end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + pub fn dend_err(&mut self) -> DEND_ERR_W { DEND_ERR_W::new(self) } #[doc = "Bit 24 - Auto command error"] #[inline(always)] #[must_use] - pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + pub fn acmd_err(&mut self) -> ACMD_ERR_W { ACMD_ERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt flags\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt](index.html) module"] +#[doc = "Interrupt flags\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERRUPT_SPEC; impl crate::RegisterSpec for INTERRUPT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interrupt::R](R) reader structure"] -impl crate::Readable for INTERRUPT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interrupt::W](W) writer structure"] +#[doc = "`read()` method returns [`interrupt::R`](R) reader structure"] +impl crate::Readable for INTERRUPT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interrupt::W`](W) writer structure"] impl crate::Writable for INTERRUPT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/irpt_en.rs b/crates/bcm2835-lpa/src/emmc/irpt_en.rs index 0e71317..af7bc80 100644 --- a/crates/bcm2835-lpa/src/emmc/irpt_en.rs +++ b/crates/bcm2835-lpa/src/emmc/irpt_en.rs @@ -1,107 +1,75 @@ #[doc = "Register `IRPT_EN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRPT_EN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_DONE` reader - Command has finished"] -pub type CMD_DONE_R = crate::BitReader; +pub type CMD_DONE_R = crate::BitReader; #[doc = "Field `CMD_DONE` writer - Command has finished"] -pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CMD_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_DONE` reader - Data transfer has finished"] -pub type DATA_DONE_R = crate::BitReader; +pub type DATA_DONE_R = crate::BitReader; #[doc = "Field `DATA_DONE` writer - Data transfer has finished"] -pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type DATA_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_R = crate::BitReader; +pub type BLOCK_GAP_R = crate::BitReader; #[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type BLOCK_GAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_RDY` reader - DATA can be written to"] -pub type WRITE_RDY_R = crate::BitReader; +pub type WRITE_RDY_R = crate::BitReader; #[doc = "Field `WRITE_RDY` writer - DATA can be written to"] -pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type WRITE_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_RDY` reader - DATA contains data to be read"] -pub type READ_RDY_R = crate::BitReader; +pub type READ_RDY_R = crate::BitReader; #[doc = "Field `READ_RDY` writer - DATA contains data to be read"] -pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type READ_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CARD` reader - Card made interrupt request"] -pub type CARD_R = crate::BitReader; +pub type CARD_R = crate::BitReader; #[doc = "Field `CARD` writer - Card made interrupt request"] -pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CARD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RETUNE` reader - Clock retune request"] -pub type RETUNE_R = crate::BitReader; +pub type RETUNE_R = crate::BitReader; #[doc = "Field `RETUNE` writer - Clock retune request"] -pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type RETUNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] -pub type BOOTACK_R = crate::BitReader; +pub type BOOTACK_R = crate::BitReader; #[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] -pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type BOOTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] -pub type ENDBOOT_R = crate::BitReader; +pub type ENDBOOT_R = crate::BitReader; #[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] -pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type ENDBOOT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTO_ERR` reader - Command timeout"] -pub type CTO_ERR_R = crate::BitReader; +pub type CTO_ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` writer - Command timeout"] -pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CCRC_ERR` reader - Command CRC error"] -pub type CCRC_ERR_R = crate::BitReader; +pub type CCRC_ERR_R = crate::BitReader; #[doc = "Field `CCRC_ERR` writer - Command CRC error"] -pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] -pub type CEND_ERR_R = crate::BitReader; +pub type CEND_ERR_R = crate::BitReader; #[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] -pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] -pub type CBAD_ERR_R = crate::BitReader; +pub type CBAD_ERR_R = crate::BitReader; #[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] -pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CBAD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTO_ERR` reader - Data timeout"] -pub type DTO_ERR_R = crate::BitReader; +pub type DTO_ERR_R = crate::BitReader; #[doc = "Field `DTO_ERR` writer - Data timeout"] -pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type DTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRC_ERR` reader - Data CRC error"] -pub type DCRC_ERR_R = crate::BitReader; +pub type DCRC_ERR_R = crate::BitReader; #[doc = "Field `DCRC_ERR` writer - Data CRC error"] -pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type DCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] -pub type DEND_ERR_R = crate::BitReader; +pub type DEND_ERR_R = crate::BitReader; #[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] -pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type DEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMD_ERR` reader - Auto command error"] -pub type ACMD_ERR_R = crate::BitReader; +pub type ACMD_ERR_R = crate::BitReader; #[doc = "Field `ACMD_ERR` writer - Auto command error"] -pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type ACMD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Command has finished"] #[inline(always)] @@ -189,128 +157,157 @@ impl R { ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IRPT_EN") + .field("acmd_err", &format_args!("{}", self.acmd_err().bit())) + .field("dend_err", &format_args!("{}", self.dend_err().bit())) + .field("dcrc_err", &format_args!("{}", self.dcrc_err().bit())) + .field("dto_err", &format_args!("{}", self.dto_err().bit())) + .field("cbad_err", &format_args!("{}", self.cbad_err().bit())) + .field("cend_err", &format_args!("{}", self.cend_err().bit())) + .field("ccrc_err", &format_args!("{}", self.ccrc_err().bit())) + .field("cto_err", &format_args!("{}", self.cto_err().bit())) + .field("endboot", &format_args!("{}", self.endboot().bit())) + .field("bootack", &format_args!("{}", self.bootack().bit())) + .field("retune", &format_args!("{}", self.retune().bit())) + .field("card", &format_args!("{}", self.card().bit())) + .field("read_rdy", &format_args!("{}", self.read_rdy().bit())) + .field("write_rdy", &format_args!("{}", self.write_rdy().bit())) + .field("block_gap", &format_args!("{}", self.block_gap().bit())) + .field("data_done", &format_args!("{}", self.data_done().bit())) + .field("cmd_done", &format_args!("{}", self.cmd_done().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command has finished"] #[inline(always)] #[must_use] - pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + pub fn cmd_done(&mut self) -> CMD_DONE_W { CMD_DONE_W::new(self) } #[doc = "Bit 1 - Data transfer has finished"] #[inline(always)] #[must_use] - pub fn data_done(&mut self) -> DATA_DONE_W<1> { + pub fn data_done(&mut self) -> DATA_DONE_W { DATA_DONE_W::new(self) } #[doc = "Bit 2 - Data transfer has stopped at block gap"] #[inline(always)] #[must_use] - pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + pub fn block_gap(&mut self) -> BLOCK_GAP_W { BLOCK_GAP_W::new(self) } #[doc = "Bit 4 - DATA can be written to"] #[inline(always)] #[must_use] - pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + pub fn write_rdy(&mut self) -> WRITE_RDY_W { WRITE_RDY_W::new(self) } #[doc = "Bit 5 - DATA contains data to be read"] #[inline(always)] #[must_use] - pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + pub fn read_rdy(&mut self) -> READ_RDY_W { READ_RDY_W::new(self) } #[doc = "Bit 8 - Card made interrupt request"] #[inline(always)] #[must_use] - pub fn card(&mut self) -> CARD_W<8> { + pub fn card(&mut self) -> CARD_W { CARD_W::new(self) } #[doc = "Bit 12 - Clock retune request"] #[inline(always)] #[must_use] - pub fn retune(&mut self) -> RETUNE_W<12> { + pub fn retune(&mut self) -> RETUNE_W { RETUNE_W::new(self) } #[doc = "Bit 13 - Boot has been acknowledged"] #[inline(always)] #[must_use] - pub fn bootack(&mut self) -> BOOTACK_W<13> { + pub fn bootack(&mut self) -> BOOTACK_W { BOOTACK_W::new(self) } #[doc = "Bit 14 - Boot operation has terminated"] #[inline(always)] #[must_use] - pub fn endboot(&mut self) -> ENDBOOT_W<14> { + pub fn endboot(&mut self) -> ENDBOOT_W { ENDBOOT_W::new(self) } #[doc = "Bit 16 - Command timeout"] #[inline(always)] #[must_use] - pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + pub fn cto_err(&mut self) -> CTO_ERR_W { CTO_ERR_W::new(self) } #[doc = "Bit 17 - Command CRC error"] #[inline(always)] #[must_use] - pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + pub fn ccrc_err(&mut self) -> CCRC_ERR_W { CCRC_ERR_W::new(self) } #[doc = "Bit 18 - Command end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + pub fn cend_err(&mut self) -> CEND_ERR_W { CEND_ERR_W::new(self) } #[doc = "Bit 19 - Incorrect response command index"] #[inline(always)] #[must_use] - pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + pub fn cbad_err(&mut self) -> CBAD_ERR_W { CBAD_ERR_W::new(self) } #[doc = "Bit 20 - Data timeout"] #[inline(always)] #[must_use] - pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + pub fn dto_err(&mut self) -> DTO_ERR_W { DTO_ERR_W::new(self) } #[doc = "Bit 21 - Data CRC error"] #[inline(always)] #[must_use] - pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + pub fn dcrc_err(&mut self) -> DCRC_ERR_W { DCRC_ERR_W::new(self) } #[doc = "Bit 22 - Data end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + pub fn dend_err(&mut self) -> DEND_ERR_W { DEND_ERR_W::new(self) } #[doc = "Bit 24 - Auto command error"] #[inline(always)] #[must_use] - pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + pub fn acmd_err(&mut self) -> ACMD_ERR_W { ACMD_ERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable interrupt to core\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irpt_en](index.html) module"] +#[doc = "Enable interrupt to core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irpt_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irpt_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRPT_EN_SPEC; impl crate::RegisterSpec for IRPT_EN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irpt_en::R](R) reader structure"] -impl crate::Readable for IRPT_EN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irpt_en::W](W) writer structure"] +#[doc = "`read()` method returns [`irpt_en::R`](R) reader structure"] +impl crate::Readable for IRPT_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irpt_en::W`](W) writer structure"] impl crate::Writable for IRPT_EN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/irpt_mask.rs b/crates/bcm2835-lpa/src/emmc/irpt_mask.rs index 87a9fdd..e8dc746 100644 --- a/crates/bcm2835-lpa/src/emmc/irpt_mask.rs +++ b/crates/bcm2835-lpa/src/emmc/irpt_mask.rs @@ -1,107 +1,75 @@ #[doc = "Register `IRPT_MASK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRPT_MASK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_DONE` reader - Command has finished"] -pub type CMD_DONE_R = crate::BitReader; +pub type CMD_DONE_R = crate::BitReader; #[doc = "Field `CMD_DONE` writer - Command has finished"] -pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CMD_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_DONE` reader - Data transfer has finished"] -pub type DATA_DONE_R = crate::BitReader; +pub type DATA_DONE_R = crate::BitReader; #[doc = "Field `DATA_DONE` writer - Data transfer has finished"] -pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type DATA_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_R = crate::BitReader; +pub type BLOCK_GAP_R = crate::BitReader; #[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type BLOCK_GAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_RDY` reader - DATA can be written to"] -pub type WRITE_RDY_R = crate::BitReader; +pub type WRITE_RDY_R = crate::BitReader; #[doc = "Field `WRITE_RDY` writer - DATA can be written to"] -pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type WRITE_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_RDY` reader - DATA contains data to be read"] -pub type READ_RDY_R = crate::BitReader; +pub type READ_RDY_R = crate::BitReader; #[doc = "Field `READ_RDY` writer - DATA contains data to be read"] -pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type READ_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CARD` reader - Card made interrupt request"] -pub type CARD_R = crate::BitReader; +pub type CARD_R = crate::BitReader; #[doc = "Field `CARD` writer - Card made interrupt request"] -pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CARD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RETUNE` reader - Clock retune request"] -pub type RETUNE_R = crate::BitReader; +pub type RETUNE_R = crate::BitReader; #[doc = "Field `RETUNE` writer - Clock retune request"] -pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type RETUNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] -pub type BOOTACK_R = crate::BitReader; +pub type BOOTACK_R = crate::BitReader; #[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] -pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type BOOTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] -pub type ENDBOOT_R = crate::BitReader; +pub type ENDBOOT_R = crate::BitReader; #[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] -pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type ENDBOOT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTO_ERR` reader - Command timeout"] -pub type CTO_ERR_R = crate::BitReader; +pub type CTO_ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` writer - Command timeout"] -pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CCRC_ERR` reader - Command CRC error"] -pub type CCRC_ERR_R = crate::BitReader; +pub type CCRC_ERR_R = crate::BitReader; #[doc = "Field `CCRC_ERR` writer - Command CRC error"] -pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] -pub type CEND_ERR_R = crate::BitReader; +pub type CEND_ERR_R = crate::BitReader; #[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] -pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] -pub type CBAD_ERR_R = crate::BitReader; +pub type CBAD_ERR_R = crate::BitReader; #[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] -pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CBAD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTO_ERR` reader - Data timeout"] -pub type DTO_ERR_R = crate::BitReader; +pub type DTO_ERR_R = crate::BitReader; #[doc = "Field `DTO_ERR` writer - Data timeout"] -pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type DTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRC_ERR` reader - Data CRC error"] -pub type DCRC_ERR_R = crate::BitReader; +pub type DCRC_ERR_R = crate::BitReader; #[doc = "Field `DCRC_ERR` writer - Data CRC error"] -pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type DCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] -pub type DEND_ERR_R = crate::BitReader; +pub type DEND_ERR_R = crate::BitReader; #[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] -pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type DEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMD_ERR` reader - Auto command error"] -pub type ACMD_ERR_R = crate::BitReader; +pub type ACMD_ERR_R = crate::BitReader; #[doc = "Field `ACMD_ERR` writer - Auto command error"] -pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type ACMD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Command has finished"] #[inline(always)] @@ -189,128 +157,157 @@ impl R { ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IRPT_MASK") + .field("acmd_err", &format_args!("{}", self.acmd_err().bit())) + .field("dend_err", &format_args!("{}", self.dend_err().bit())) + .field("dcrc_err", &format_args!("{}", self.dcrc_err().bit())) + .field("dto_err", &format_args!("{}", self.dto_err().bit())) + .field("cbad_err", &format_args!("{}", self.cbad_err().bit())) + .field("cend_err", &format_args!("{}", self.cend_err().bit())) + .field("ccrc_err", &format_args!("{}", self.ccrc_err().bit())) + .field("cto_err", &format_args!("{}", self.cto_err().bit())) + .field("endboot", &format_args!("{}", self.endboot().bit())) + .field("bootack", &format_args!("{}", self.bootack().bit())) + .field("retune", &format_args!("{}", self.retune().bit())) + .field("card", &format_args!("{}", self.card().bit())) + .field("read_rdy", &format_args!("{}", self.read_rdy().bit())) + .field("write_rdy", &format_args!("{}", self.write_rdy().bit())) + .field("block_gap", &format_args!("{}", self.block_gap().bit())) + .field("data_done", &format_args!("{}", self.data_done().bit())) + .field("cmd_done", &format_args!("{}", self.cmd_done().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command has finished"] #[inline(always)] #[must_use] - pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + pub fn cmd_done(&mut self) -> CMD_DONE_W { CMD_DONE_W::new(self) } #[doc = "Bit 1 - Data transfer has finished"] #[inline(always)] #[must_use] - pub fn data_done(&mut self) -> DATA_DONE_W<1> { + pub fn data_done(&mut self) -> DATA_DONE_W { DATA_DONE_W::new(self) } #[doc = "Bit 2 - Data transfer has stopped at block gap"] #[inline(always)] #[must_use] - pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + pub fn block_gap(&mut self) -> BLOCK_GAP_W { BLOCK_GAP_W::new(self) } #[doc = "Bit 4 - DATA can be written to"] #[inline(always)] #[must_use] - pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + pub fn write_rdy(&mut self) -> WRITE_RDY_W { WRITE_RDY_W::new(self) } #[doc = "Bit 5 - DATA contains data to be read"] #[inline(always)] #[must_use] - pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + pub fn read_rdy(&mut self) -> READ_RDY_W { READ_RDY_W::new(self) } #[doc = "Bit 8 - Card made interrupt request"] #[inline(always)] #[must_use] - pub fn card(&mut self) -> CARD_W<8> { + pub fn card(&mut self) -> CARD_W { CARD_W::new(self) } #[doc = "Bit 12 - Clock retune request"] #[inline(always)] #[must_use] - pub fn retune(&mut self) -> RETUNE_W<12> { + pub fn retune(&mut self) -> RETUNE_W { RETUNE_W::new(self) } #[doc = "Bit 13 - Boot has been acknowledged"] #[inline(always)] #[must_use] - pub fn bootack(&mut self) -> BOOTACK_W<13> { + pub fn bootack(&mut self) -> BOOTACK_W { BOOTACK_W::new(self) } #[doc = "Bit 14 - Boot operation has terminated"] #[inline(always)] #[must_use] - pub fn endboot(&mut self) -> ENDBOOT_W<14> { + pub fn endboot(&mut self) -> ENDBOOT_W { ENDBOOT_W::new(self) } #[doc = "Bit 16 - Command timeout"] #[inline(always)] #[must_use] - pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + pub fn cto_err(&mut self) -> CTO_ERR_W { CTO_ERR_W::new(self) } #[doc = "Bit 17 - Command CRC error"] #[inline(always)] #[must_use] - pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + pub fn ccrc_err(&mut self) -> CCRC_ERR_W { CCRC_ERR_W::new(self) } #[doc = "Bit 18 - Command end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + pub fn cend_err(&mut self) -> CEND_ERR_W { CEND_ERR_W::new(self) } #[doc = "Bit 19 - Incorrect response command index"] #[inline(always)] #[must_use] - pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + pub fn cbad_err(&mut self) -> CBAD_ERR_W { CBAD_ERR_W::new(self) } #[doc = "Bit 20 - Data timeout"] #[inline(always)] #[must_use] - pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + pub fn dto_err(&mut self) -> DTO_ERR_W { DTO_ERR_W::new(self) } #[doc = "Bit 21 - Data CRC error"] #[inline(always)] #[must_use] - pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + pub fn dcrc_err(&mut self) -> DCRC_ERR_W { DCRC_ERR_W::new(self) } #[doc = "Bit 22 - Data end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + pub fn dend_err(&mut self) -> DEND_ERR_W { DEND_ERR_W::new(self) } #[doc = "Bit 24 - Auto command error"] #[inline(always)] #[must_use] - pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + pub fn acmd_err(&mut self) -> ACMD_ERR_W { ACMD_ERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mask interrupts that change in INTERRUPT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irpt_mask](index.html) module"] +#[doc = "Mask interrupts that change in INTERRUPT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irpt_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irpt_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRPT_MASK_SPEC; impl crate::RegisterSpec for IRPT_MASK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irpt_mask::R](R) reader structure"] -impl crate::Readable for IRPT_MASK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irpt_mask::W](W) writer structure"] +#[doc = "`read()` method returns [`irpt_mask::R`](R) reader structure"] +impl crate::Readable for IRPT_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irpt_mask::W`](W) writer structure"] impl crate::Writable for IRPT_MASK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/resp0.rs b/crates/bcm2835-lpa/src/emmc/resp0.rs index 1022d1a..79ea5ca 100644 --- a/crates/bcm2835-lpa/src/emmc/resp0.rs +++ b/crates/bcm2835-lpa/src/emmc/resp0.rs @@ -1,59 +1,38 @@ #[doc = "Register `RESP0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RESP0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status bits of the response\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp0](index.html) module"] +#[doc = "Status bits of the response\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESP0_SPEC; impl crate::RegisterSpec for RESP0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [resp0::R](R) reader structure"] -impl crate::Readable for RESP0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [resp0::W](W) writer structure"] +#[doc = "`read()` method returns [`resp0::R`](R) reader structure"] +impl crate::Readable for RESP0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resp0::W`](W) writer structure"] impl crate::Writable for RESP0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/resp1.rs b/crates/bcm2835-lpa/src/emmc/resp1.rs index d1e9b42..12a2f9a 100644 --- a/crates/bcm2835-lpa/src/emmc/resp1.rs +++ b/crates/bcm2835-lpa/src/emmc/resp1.rs @@ -1,59 +1,38 @@ #[doc = "Register `RESP1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RESP1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Bits 63:32 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp1](index.html) module"] +#[doc = "Bits 63:32 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESP1_SPEC; impl crate::RegisterSpec for RESP1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [resp1::R](R) reader structure"] -impl crate::Readable for RESP1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [resp1::W](W) writer structure"] +#[doc = "`read()` method returns [`resp1::R`](R) reader structure"] +impl crate::Readable for RESP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resp1::W`](W) writer structure"] impl crate::Writable for RESP1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/resp2.rs b/crates/bcm2835-lpa/src/emmc/resp2.rs index 418942a..5a51d34 100644 --- a/crates/bcm2835-lpa/src/emmc/resp2.rs +++ b/crates/bcm2835-lpa/src/emmc/resp2.rs @@ -1,59 +1,38 @@ #[doc = "Register `RESP2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RESP2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Bits 95:64 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp2](index.html) module"] +#[doc = "Bits 95:64 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESP2_SPEC; impl crate::RegisterSpec for RESP2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [resp2::R](R) reader structure"] -impl crate::Readable for RESP2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [resp2::W](W) writer structure"] +#[doc = "`read()` method returns [`resp2::R`](R) reader structure"] +impl crate::Readable for RESP2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resp2::W`](W) writer structure"] impl crate::Writable for RESP2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/resp3.rs b/crates/bcm2835-lpa/src/emmc/resp3.rs index 36b2c80..65ef18f 100644 --- a/crates/bcm2835-lpa/src/emmc/resp3.rs +++ b/crates/bcm2835-lpa/src/emmc/resp3.rs @@ -1,59 +1,38 @@ #[doc = "Register `RESP3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RESP3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Bits 127:96 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp3](index.html) module"] +#[doc = "Bits 127:96 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESP3_SPEC; impl crate::RegisterSpec for RESP3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [resp3::R](R) reader structure"] -impl crate::Readable for RESP3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [resp3::W](W) writer structure"] +#[doc = "`read()` method returns [`resp3::R`](R) reader structure"] +impl crate::Readable for RESP3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resp3::W`](W) writer structure"] impl crate::Writable for RESP3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/slotisr_ver.rs b/crates/bcm2835-lpa/src/emmc/slotisr_ver.rs index 6016436..0db90df 100644 --- a/crates/bcm2835-lpa/src/emmc/slotisr_ver.rs +++ b/crates/bcm2835-lpa/src/emmc/slotisr_ver.rs @@ -1,52 +1,19 @@ #[doc = "Register `SLOTISR_VER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SLOTISR_VER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLOT_STATUS` reader - OR of interrupt and wakeup signals for each slot"] -pub type SLOT_STATUS_R = crate::FieldReader; +pub type SLOT_STATUS_R = crate::FieldReader; #[doc = "Field `SLOT_STATUS` writer - OR of interrupt and wakeup signals for each slot"] -pub type SLOT_STATUS_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +pub type SLOT_STATUS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SDVERSION` reader - Host controller specification version"] -pub type SDVERSION_R = crate::FieldReader; +pub type SDVERSION_R = crate::FieldReader; #[doc = "Field `SDVERSION` writer - Host controller specification version"] -pub type SDVERSION_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +pub type SDVERSION_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `VENDOR` reader - Vendor version number"] -pub type VENDOR_R = crate::FieldReader; +pub type VENDOR_R = crate::FieldReader; #[doc = "Field `VENDOR` writer - Vendor version number"] -pub type VENDOR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +pub type VENDOR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - OR of interrupt and wakeup signals for each slot"] #[inline(always)] @@ -64,44 +31,62 @@ impl R { VENDOR_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLOTISR_VER") + .field("vendor", &format_args!("{}", self.vendor().bits())) + .field("sdversion", &format_args!("{}", self.sdversion().bits())) + .field( + "slot_status", + &format_args!("{}", self.slot_status().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - OR of interrupt and wakeup signals for each slot"] #[inline(always)] #[must_use] - pub fn slot_status(&mut self) -> SLOT_STATUS_W<0> { + pub fn slot_status(&mut self) -> SLOT_STATUS_W { SLOT_STATUS_W::new(self) } #[doc = "Bits 16:23 - Host controller specification version"] #[inline(always)] #[must_use] - pub fn sdversion(&mut self) -> SDVERSION_W<16> { + pub fn sdversion(&mut self) -> SDVERSION_W { SDVERSION_W::new(self) } #[doc = "Bits 24:31 - Vendor version number"] #[inline(always)] #[must_use] - pub fn vendor(&mut self) -> VENDOR_W<24> { + pub fn vendor(&mut self) -> VENDOR_W { VENDOR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Version information and slot interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slotisr_ver](index.html) module"] +#[doc = "Version information and slot interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slotisr_ver::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slotisr_ver::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLOTISR_VER_SPEC; impl crate::RegisterSpec for SLOTISR_VER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [slotisr_ver::R](R) reader structure"] -impl crate::Readable for SLOTISR_VER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [slotisr_ver::W](W) writer structure"] +#[doc = "`read()` method returns [`slotisr_ver::R`](R) reader structure"] +impl crate::Readable for SLOTISR_VER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slotisr_ver::W`](W) writer structure"] impl crate::Writable for SLOTISR_VER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/spi_int_spt.rs b/crates/bcm2835-lpa/src/emmc/spi_int_spt.rs index bce7edc..ba304fe 100644 --- a/crates/bcm2835-lpa/src/emmc/spi_int_spt.rs +++ b/crates/bcm2835-lpa/src/emmc/spi_int_spt.rs @@ -1,43 +1,11 @@ #[doc = "Register `SPI_INT_SPT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SPI_INT_SPT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SELECT` reader - "] -pub type SELECT_R = crate::FieldReader; +pub type SELECT_R = crate::FieldReader; #[doc = "Field `SELECT` writer - "] -pub type SELECT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SPI_INT_SPT_SPEC, u8, u8, 8, O>; +pub type SELECT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { SELECT_R::new((self.bits & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_INT_SPT") + .field("select", &format_args!("{}", self.select().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7"] #[inline(always)] #[must_use] - pub fn select(&mut self) -> SELECT_W<0> { + pub fn select(&mut self) -> SELECT_W { SELECT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupts in SPI mode depend on CS\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_int_spt](index.html) module"] +#[doc = "Interrupts in SPI mode depend on CS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_int_spt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_int_spt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SPI_INT_SPT_SPEC; impl crate::RegisterSpec for SPI_INT_SPT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [spi_int_spt::R](R) reader structure"] -impl crate::Readable for SPI_INT_SPT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [spi_int_spt::W](W) writer structure"] +#[doc = "`read()` method returns [`spi_int_spt::R`](R) reader structure"] +impl crate::Readable for SPI_INT_SPT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_int_spt::W`](W) writer structure"] impl crate::Writable for SPI_INT_SPT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/status.rs b/crates/bcm2835-lpa/src/emmc/status.rs index 0b86ab0..2b07e21 100644 --- a/crates/bcm2835-lpa/src/emmc/status.rs +++ b/crates/bcm2835-lpa/src/emmc/status.rs @@ -1,79 +1,47 @@ #[doc = "Register `STATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STATUS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_INHIBIT` reader - Command line still in use"] -pub type CMD_INHIBIT_R = crate::BitReader; +pub type CMD_INHIBIT_R = crate::BitReader; #[doc = "Field `CMD_INHIBIT` writer - Command line still in use"] -pub type CMD_INHIBIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type CMD_INHIBIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAT_INHIBIT` reader - Data lines still in use"] -pub type DAT_INHIBIT_R = crate::BitReader; +pub type DAT_INHIBIT_R = crate::BitReader; #[doc = "Field `DAT_INHIBIT` writer - Data lines still in use"] -pub type DAT_INHIBIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type DAT_INHIBIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAT_ACTIVE` reader - At least one data line is active"] -pub type DAT_ACTIVE_R = crate::BitReader; +pub type DAT_ACTIVE_R = crate::BitReader; #[doc = "Field `DAT_ACTIVE` writer - At least one data line is active"] -pub type DAT_ACTIVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type DAT_ACTIVE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_TRANSFER` reader - Write transfer is active"] -pub type WRITE_TRANSFER_R = crate::BitReader; +pub type WRITE_TRANSFER_R = crate::BitReader; #[doc = "Field `WRITE_TRANSFER` writer - Write transfer is active"] -pub type WRITE_TRANSFER_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type WRITE_TRANSFER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_TRANSFER` reader - Read transfer is active"] -pub type READ_TRANSFER_R = crate::BitReader; +pub type READ_TRANSFER_R = crate::BitReader; #[doc = "Field `READ_TRANSFER` writer - Read transfer is active"] -pub type READ_TRANSFER_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type READ_TRANSFER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUFFER_WRITE_ENABLE` reader - The buffer has space for new data"] -pub type BUFFER_WRITE_ENABLE_R = crate::BitReader; +pub type BUFFER_WRITE_ENABLE_R = crate::BitReader; #[doc = "Field `BUFFER_WRITE_ENABLE` writer - The buffer has space for new data"] -pub type BUFFER_WRITE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type BUFFER_WRITE_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUFFER_READ_ENABLE` reader - New data is available to read"] -pub type BUFFER_READ_ENABLE_R = crate::BitReader; +pub type BUFFER_READ_ENABLE_R = crate::BitReader; #[doc = "Field `BUFFER_READ_ENABLE` writer - New data is available to read"] -pub type BUFFER_READ_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type BUFFER_READ_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAT_LEVEL0` reader - Value of DAT\\[3:0\\]"] -pub type DAT_LEVEL0_R = crate::FieldReader; +pub type DAT_LEVEL0_R = crate::FieldReader; #[doc = "Field `DAT_LEVEL0` writer - Value of DAT\\[3:0\\]"] -pub type DAT_LEVEL0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STATUS_SPEC, u8, u8, 4, O>; +pub type DAT_LEVEL0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CMD_LEVEL` reader - Value of CMD"] -pub type CMD_LEVEL_R = crate::BitReader; +pub type CMD_LEVEL_R = crate::BitReader; #[doc = "Field `CMD_LEVEL` writer - Value of CMD"] -pub type CMD_LEVEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type CMD_LEVEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAT_LEVEL1` reader - Value of DAT\\[7:4\\]"] -pub type DAT_LEVEL1_R = crate::FieldReader; +pub type DAT_LEVEL1_R = crate::FieldReader; #[doc = "Field `DAT_LEVEL1` writer - Value of DAT\\[7:4\\]"] -pub type DAT_LEVEL1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STATUS_SPEC, u8, u8, 4, O>; +pub type DAT_LEVEL1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bit 0 - Command line still in use"] #[inline(always)] @@ -126,86 +94,120 @@ impl R { DAT_LEVEL1_R::new(((self.bits >> 25) & 0x0f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS") + .field("dat_level1", &format_args!("{}", self.dat_level1().bits())) + .field("cmd_level", &format_args!("{}", self.cmd_level().bit())) + .field("dat_level0", &format_args!("{}", self.dat_level0().bits())) + .field( + "buffer_read_enable", + &format_args!("{}", self.buffer_read_enable().bit()), + ) + .field( + "buffer_write_enable", + &format_args!("{}", self.buffer_write_enable().bit()), + ) + .field( + "read_transfer", + &format_args!("{}", self.read_transfer().bit()), + ) + .field( + "write_transfer", + &format_args!("{}", self.write_transfer().bit()), + ) + .field("dat_active", &format_args!("{}", self.dat_active().bit())) + .field("dat_inhibit", &format_args!("{}", self.dat_inhibit().bit())) + .field("cmd_inhibit", &format_args!("{}", self.cmd_inhibit().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command line still in use"] #[inline(always)] #[must_use] - pub fn cmd_inhibit(&mut self) -> CMD_INHIBIT_W<0> { + pub fn cmd_inhibit(&mut self) -> CMD_INHIBIT_W { CMD_INHIBIT_W::new(self) } #[doc = "Bit 1 - Data lines still in use"] #[inline(always)] #[must_use] - pub fn dat_inhibit(&mut self) -> DAT_INHIBIT_W<1> { + pub fn dat_inhibit(&mut self) -> DAT_INHIBIT_W { DAT_INHIBIT_W::new(self) } #[doc = "Bit 2 - At least one data line is active"] #[inline(always)] #[must_use] - pub fn dat_active(&mut self) -> DAT_ACTIVE_W<2> { + pub fn dat_active(&mut self) -> DAT_ACTIVE_W { DAT_ACTIVE_W::new(self) } #[doc = "Bit 8 - Write transfer is active"] #[inline(always)] #[must_use] - pub fn write_transfer(&mut self) -> WRITE_TRANSFER_W<8> { + pub fn write_transfer(&mut self) -> WRITE_TRANSFER_W { WRITE_TRANSFER_W::new(self) } #[doc = "Bit 9 - Read transfer is active"] #[inline(always)] #[must_use] - pub fn read_transfer(&mut self) -> READ_TRANSFER_W<9> { + pub fn read_transfer(&mut self) -> READ_TRANSFER_W { READ_TRANSFER_W::new(self) } #[doc = "Bit 10 - The buffer has space for new data"] #[inline(always)] #[must_use] - pub fn buffer_write_enable(&mut self) -> BUFFER_WRITE_ENABLE_W<10> { + pub fn buffer_write_enable(&mut self) -> BUFFER_WRITE_ENABLE_W { BUFFER_WRITE_ENABLE_W::new(self) } #[doc = "Bit 11 - New data is available to read"] #[inline(always)] #[must_use] - pub fn buffer_read_enable(&mut self) -> BUFFER_READ_ENABLE_W<11> { + pub fn buffer_read_enable(&mut self) -> BUFFER_READ_ENABLE_W { BUFFER_READ_ENABLE_W::new(self) } #[doc = "Bits 20:23 - Value of DAT\\[3:0\\]"] #[inline(always)] #[must_use] - pub fn dat_level0(&mut self) -> DAT_LEVEL0_W<20> { + pub fn dat_level0(&mut self) -> DAT_LEVEL0_W { DAT_LEVEL0_W::new(self) } #[doc = "Bit 24 - Value of CMD"] #[inline(always)] #[must_use] - pub fn cmd_level(&mut self) -> CMD_LEVEL_W<24> { + pub fn cmd_level(&mut self) -> CMD_LEVEL_W { CMD_LEVEL_W::new(self) } #[doc = "Bits 25:28 - Value of DAT\\[7:4\\]"] #[inline(always)] #[must_use] - pub fn dat_level1(&mut self) -> DAT_LEVEL1_W<25> { + pub fn dat_level1(&mut self) -> DAT_LEVEL1_W { DAT_LEVEL1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status info for debugging\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +#[doc = "Status info for debugging\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STATUS_SPEC; impl crate::RegisterSpec for STATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [status::R](R) reader structure"] -impl crate::Readable for STATUS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"] impl crate::Writable for STATUS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/tune_step.rs b/crates/bcm2835-lpa/src/emmc/tune_step.rs index 2f0169b..aa0dd84 100644 --- a/crates/bcm2835-lpa/src/emmc/tune_step.rs +++ b/crates/bcm2835-lpa/src/emmc/tune_step.rs @@ -1,43 +1,11 @@ #[doc = "Register `TUNE_STEP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TUNE_STEP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DELAY` reader - "] -pub type DELAY_R = crate::FieldReader; +pub type DELAY_R = crate::FieldReader; #[doc = "Field `DELAY` writer - "] -pub type DELAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEP_SPEC, u8, u8, 3, O>; +pub type DELAY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:2"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DELAY_R::new((self.bits & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TUNE_STEP") + .field("delay", &format_args!("{}", self.delay().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2"] #[inline(always)] #[must_use] - pub fn delay(&mut self) -> DELAY_W<0> { + pub fn delay(&mut self) -> DELAY_W { DELAY_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Sample clock delay step duration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_step](index.html) module"] +#[doc = "Sample clock delay step duration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_step::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_step::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TUNE_STEP_SPEC; impl crate::RegisterSpec for TUNE_STEP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tune_step::R](R) reader structure"] -impl crate::Readable for TUNE_STEP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tune_step::W](W) writer structure"] +#[doc = "`read()` method returns [`tune_step::R`](R) reader structure"] +impl crate::Readable for TUNE_STEP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tune_step::W`](W) writer structure"] impl crate::Writable for TUNE_STEP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/tune_steps_ddr.rs b/crates/bcm2835-lpa/src/emmc/tune_steps_ddr.rs index a8fea76..c4f1dd8 100644 --- a/crates/bcm2835-lpa/src/emmc/tune_steps_ddr.rs +++ b/crates/bcm2835-lpa/src/emmc/tune_steps_ddr.rs @@ -1,43 +1,11 @@ #[doc = "Register `TUNE_STEPS_DDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TUNE_STEPS_DDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `STEPS` reader - "] -pub type STEPS_R = crate::FieldReader; +pub type STEPS_R = crate::FieldReader; #[doc = "Field `STEPS` writer - "] -pub type STEPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEPS_DDR_SPEC, u8, u8, 6, O>; +pub type STEPS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { STEPS_R::new((self.bits & 0x3f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TUNE_STEPS_DDR") + .field("steps", &format_args!("{}", self.steps().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn steps(&mut self) -> STEPS_W<0> { + pub fn steps(&mut self) -> STEPS_W { STEPS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Sample clock delay step count for DDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_steps_ddr](index.html) module"] +#[doc = "Sample clock delay step count for DDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_steps_ddr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_steps_ddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TUNE_STEPS_DDR_SPEC; impl crate::RegisterSpec for TUNE_STEPS_DDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tune_steps_ddr::R](R) reader structure"] -impl crate::Readable for TUNE_STEPS_DDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tune_steps_ddr::W](W) writer structure"] +#[doc = "`read()` method returns [`tune_steps_ddr::R`](R) reader structure"] +impl crate::Readable for TUNE_STEPS_DDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tune_steps_ddr::W`](W) writer structure"] impl crate::Writable for TUNE_STEPS_DDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/emmc/tune_steps_std.rs b/crates/bcm2835-lpa/src/emmc/tune_steps_std.rs index c04740c..cf65897 100644 --- a/crates/bcm2835-lpa/src/emmc/tune_steps_std.rs +++ b/crates/bcm2835-lpa/src/emmc/tune_steps_std.rs @@ -1,43 +1,11 @@ #[doc = "Register `TUNE_STEPS_STD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TUNE_STEPS_STD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `STEPS` reader - "] -pub type STEPS_R = crate::FieldReader; +pub type STEPS_R = crate::FieldReader; #[doc = "Field `STEPS` writer - "] -pub type STEPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEPS_STD_SPEC, u8, u8, 6, O>; +pub type STEPS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { STEPS_R::new((self.bits & 0x3f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TUNE_STEPS_STD") + .field("steps", &format_args!("{}", self.steps().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn steps(&mut self) -> STEPS_W<0> { + pub fn steps(&mut self) -> STEPS_W { STEPS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Sample clock delay step count for SDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_steps_std](index.html) module"] +#[doc = "Sample clock delay step count for SDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_steps_std::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_steps_std::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TUNE_STEPS_STD_SPEC; impl crate::RegisterSpec for TUNE_STEPS_STD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tune_steps_std::R](R) reader structure"] -impl crate::Readable for TUNE_STEPS_STD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tune_steps_std::W](W) writer structure"] +#[doc = "`read()` method returns [`tune_steps_std::R`](R) reader structure"] +impl crate::Readable for TUNE_STEPS_STD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tune_steps_std::W`](W) writer structure"] impl crate::Writable for TUNE_STEPS_STD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/generic.rs b/crates/bcm2835-lpa/src/generic.rs index f10ca73..a34573a 100644 --- a/crates/bcm2835-lpa/src/generic.rs +++ b/crates/bcm2835-lpa/src/generic.rs @@ -31,6 +31,9 @@ macro_rules! raw_reg { const fn $mask() -> $U { <$U>::MAX >> ($size - WI) } + impl FieldSpec for $U { + type Ux = $U; + } }; } raw_reg!(u8, 8, mask_u8); @@ -42,21 +45,21 @@ pub trait RegisterSpec { #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] type Ux: RawReg; } +#[doc = " Raw field type"] +pub trait FieldSpec: Sized { + #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy + PartialEq + From; +} #[doc = " Trait implemented by readable registers to enable the `read` method."] #[doc = ""] #[doc = " Registers marked with `Writable` can be also be `modify`'ed."] -pub trait Readable: RegisterSpec { - #[doc = " Result from a call to `read` and argument to `modify`."] - type Reader: From> + core::ops::Deref>; -} +pub trait Readable: RegisterSpec {} #[doc = " Trait implemented by writeable registers."] #[doc = ""] #[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] #[doc = ""] #[doc = " Registers marked with `Readable` can be also be `modify`'ed."] pub trait Writable: RegisterSpec { - #[doc = " Writer type argument to `write`, et al."] - type Writer: From> + core::ops::DerefMut>; #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] @@ -107,11 +110,11 @@ impl Reg { #[doc = " let flag = reader.field2().bit_is_set();"] #[doc = " ```"] #[inline(always)] - pub fn read(&self) -> REG::Reader { - REG::Reader::from(R { + pub fn read(&self) -> R { + R { bits: self.register.get(), _reg: marker::PhantomData, - }) + } } } impl Reg { @@ -148,14 +151,14 @@ impl Reg { #[inline(always)] pub fn write(&self, f: F) where - F: FnOnce(&mut REG::Writer) -> &mut W, + F: FnOnce(&mut W) -> &mut W, { self.register.set( - f(&mut REG::Writer::from(W { + f(&mut W { bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, _reg: marker::PhantomData, - })) + }) .bits, ); } @@ -171,13 +174,13 @@ impl Reg { #[inline(always)] pub unsafe fn write_with_zero(&self, f: F) where - F: FnOnce(&mut REG::Writer) -> &mut W, + F: FnOnce(&mut W) -> &mut W, { self.register.set( - f(&mut REG::Writer::from(W { + f(&mut W { bits: REG::Ux::default(), _reg: marker::PhantomData, - })) + }) .bits, ); } @@ -211,37 +214,36 @@ impl Reg { #[inline(always)] pub fn modify(&self, f: F) where - for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); self.register.set( f( - ®::Reader::from(R { + &R { bits, _reg: marker::PhantomData, - }), - &mut REG::Writer::from(W { + }, + &mut W { bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, _reg: marker::PhantomData, - }), + }, ) .bits, ); } } +#[doc(hidden)] +pub mod raw; #[doc = " Register reader."] #[doc = ""] #[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] #[doc = " method."] -pub struct R { - pub(crate) bits: REG::Ux, - _reg: marker::PhantomData, -} +pub type R = raw::R; impl R { #[doc = " Reads raw bits from register."] #[inline(always)] - pub fn bits(&self) -> REG::Ux { + pub const fn bits(&self) -> REG::Ux { self.bits } } @@ -259,83 +261,27 @@ where #[doc = " Register writer."] #[doc = ""] #[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] -pub struct W { - #[doc = "Writable bits"] - pub(crate) bits: REG::Ux, - _reg: marker::PhantomData, -} -impl W { - #[doc = " Writes raw bits to the register."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Read datasheet or reference manual to find what values are allowed to pass."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { - self.bits = bits; - self - } -} -#[doc(hidden)] -pub struct FieldReaderRaw { - pub(crate) bits: U, - _reg: marker::PhantomData, -} -impl FieldReaderRaw -where - U: Copy, -{ - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(bits: U) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} -#[doc(hidden)] -pub struct BitReaderRaw { - pub(crate) bits: bool, - _reg: marker::PhantomData, -} -impl BitReaderRaw { - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(bits: bool) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} +pub type W = raw::W; #[doc = " Field reader."] #[doc = ""] #[doc = " Result of the `read` methods of fields."] -pub type FieldReader = FieldReaderRaw; +pub type FieldReader = raw::FieldReader; #[doc = " Bit-wise field reader"] -pub type BitReader = BitReaderRaw; -impl FieldReader -where - U: Copy, -{ +pub type BitReader = raw::BitReader; +impl FieldReader { #[doc = " Reads raw bits from field."] #[inline(always)] - pub fn bits(&self) -> U { + pub const fn bits(&self) -> FI::Ux { self.bits } } -impl PartialEq for FieldReader +impl PartialEq for FieldReader where - U: PartialEq, - FI: Copy, - U: From, + FI: FieldSpec + Copy, { #[inline(always)] fn eq(&self, other: &FI) -> bool { - self.bits.eq(&U::from(*other)) + self.bits.eq(&FI::Ux::from(*other)) } } impl PartialEq for BitReader @@ -351,17 +297,17 @@ where impl BitReader { #[doc = " Value of the field as raw bits."] #[inline(always)] - pub fn bit(&self) -> bool { + pub const fn bit(&self) -> bool { self.bits } #[doc = " Returns `true` if the bit is clear (0)."] #[inline(always)] - pub fn bit_is_clear(&self) -> bool { + pub const fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = " Returns `true` if the bit is set (1)."] #[inline(always)] - pub fn bit_is_set(&self) -> bool { + pub const fn bit_is_set(&self) -> bool { self.bit() } } @@ -369,111 +315,81 @@ impl BitReader { pub struct Safe; #[doc(hidden)] pub struct Unsafe; -#[doc(hidden)] -pub struct FieldWriterRaw<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> -where - REG: Writable + RegisterSpec, - N: From, -{ - pub(crate) w: &'a mut REG::Writer, - _field: marker::PhantomData<(N, FI, Safety)>, -} -impl<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> - FieldWriterRaw<'a, U, REG, N, FI, Safety, WI, O> -where - REG: Writable + RegisterSpec, - N: From, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut REG::Writer) -> Self { - Self { - w, - _field: marker::PhantomData, - } - } -} -#[doc(hidden)] -pub struct BitWriterRaw<'a, U, REG, FI, M, const O: u8> -where - REG: Writable + RegisterSpec, - bool: From, -{ - pub(crate) w: &'a mut REG::Writer, - _field: marker::PhantomData<(FI, M)>, -} -impl<'a, U, REG, FI, M, const O: u8> BitWriterRaw<'a, U, REG, FI, M, O> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut REG::Writer) -> Self { - Self { - w, - _field: marker::PhantomData, - } - } -} #[doc = " Write field Proxy with unsafe `bits`"] -pub type FieldWriter<'a, U, REG, N, FI, const WI: u8, const O: u8> = - FieldWriterRaw<'a, U, REG, N, FI, Unsafe, WI, O>; +pub type FieldWriter<'a, REG, const WI: u8, const O: u8, FI = u8> = + raw::FieldWriter<'a, REG, WI, O, FI, Unsafe>; #[doc = " Write field Proxy with safe `bits`"] -pub type FieldWriterSafe<'a, U, REG, N, FI, const WI: u8, const O: u8> = - FieldWriterRaw<'a, U, REG, N, FI, Safe, WI, O>; -impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> +pub type FieldWriterSafe<'a, REG, const WI: u8, const O: u8, FI = u8> = + raw::FieldWriter<'a, REG, WI, O, FI, Safe>; +impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI> where - REG: Writable + RegisterSpec, - N: From, + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, { #[doc = " Field width"] pub const WIDTH: u8 = WI; + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << OF); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } } -impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> +impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI> where - REG: Writable + RegisterSpec, - N: From, + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, { #[doc = " Field width"] pub const WIDTH: u8 = WI; + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << OF); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bits(FI::Ux::from(variant)) + } } macro_rules! bit_proxy { ($ writer : ident , $ mwv : ident) => { #[doc(hidden)] pub struct $mwv; #[doc = " Bit-wise write field proxy"] - pub type $writer<'a, U, REG, FI, const O: u8> = BitWriterRaw<'a, U, REG, FI, $mwv, O>; - impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> + pub type $writer<'a, REG, const O: u8, FI = bool> = raw::BitWriter<'a, REG, O, FI, $mwv>; + impl<'a, REG, const OF: u8, FI> $writer<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, + REG: Writable + RegisterSpec, bool: From, { #[doc = " Field width"] pub const WIDTH: u8 = 1; - } - }; -} -macro_rules! impl_bit_proxy { - ($ writer : ident) => { - impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> - where - REG: Writable + RegisterSpec, - U: RawReg, - bool: From, - { #[doc = " Writes bit to the field"] #[inline(always)] - pub fn bit(self, value: bool) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); - self.w.bits |= (U::from(value) & U::one()) << OF; + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << OF; self.w } #[doc = " Writes `variant` to the field"] #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + pub fn variant(self, variant: FI) -> &'a mut W { self.bit(bool::from(variant)) } } @@ -486,210 +402,94 @@ bit_proxy!(BitWriter1C, Bit1C); bit_proxy!(BitWriter0S, Bit0S); bit_proxy!(BitWriter1T, Bit1T); bit_proxy!(BitWriter0T, Bit0T); -impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> -where - REG: Writable + RegisterSpec, - U: RawReg + From, - N: From, -{ - #[doc = " Writes raw bits to the field"] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(self, value: N) -> &'a mut REG::Writer { - self.w.bits &= !(U::mask::() << OF); - self.w.bits |= (U::from(value) & U::mask::()) << OF; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { - unsafe { self.bits(N::from(variant)) } - } -} -impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> -where - REG: Writable + RegisterSpec, - U: RawReg + From, - N: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn bits(self, value: N) -> &'a mut REG::Writer { - self.w.bits &= !(U::mask::() << OF); - self.w.bits |= (U::from(value) & U::mask::()) << OF; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { - self.bits(N::from(variant)) - } -} -impl_bit_proxy!(BitWriter); -impl_bit_proxy!(BitWriter1S); -impl_bit_proxy!(BitWriter0C); -impl_bit_proxy!(BitWriter1C); -impl_bit_proxy!(BitWriter0S); -impl_bit_proxy!(BitWriter1T); -impl_bit_proxy!(BitWriter0T); -impl<'a, U, REG, FI, const OF: u8> BitWriter<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = " Sets the field bit"] #[inline(always)] - pub fn set_bit(self) -> &'a mut REG::Writer { - self.w.bits |= U::one() << OF; + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << OF; self.w } #[doc = " Clears the field bit"] #[inline(always)] - pub fn clear_bit(self) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter1S<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter1S<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = " Sets the field bit"] #[inline(always)] - pub fn set_bit(self) -> &'a mut REG::Writer { - self.w.bits |= U::one() << OF; + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << OF; self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter0C<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter0C<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = " Clears the field bit"] #[inline(always)] - pub fn clear_bit(self) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter1C<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter1C<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = "Clears the field bit by passing one"] #[inline(always)] - pub fn clear_bit_by_one(self) -> &'a mut REG::Writer { - self.w.bits |= U::one() << OF; + pub fn clear_bit_by_one(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << OF; self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter0S<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter0S<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = "Sets the field bit by passing zero"] #[inline(always)] - pub fn set_bit_by_zero(self) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); + pub fn set_bit_by_zero(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter1T<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter1T<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = "Toggle the field bit by passing one"] #[inline(always)] - pub fn toggle_bit(self) -> &'a mut REG::Writer { - self.w.bits |= U::one() << OF; + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << OF; self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter0T<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter0T<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = "Toggle the field bit by passing zero"] #[inline(always)] - pub fn toggle_bit(self) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); self.w } } mod atomic; -use atomic::AtomicOperations; -impl Reg -where - REG::Ux: AtomicOperations + Default + core::ops::Not, -{ - #[doc = " Set high every bit in the register that was set in the write proxy. Leave other bits"] - #[doc = " untouched. The write is done in a single atomic instruction."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " The resultant bit pattern may not be valid for the register."] - #[inline(always)] - pub unsafe fn set_bits(&self, f: F) - where - F: FnOnce(&mut REG::Writer) -> &mut W, - { - let bits = f(&mut REG::Writer::from(W { - bits: Default::default(), - _reg: marker::PhantomData, - })) - .bits; - REG::Ux::atomic_or(self.register.as_ptr(), bits); - } - #[doc = " Clear every bit in the register that was cleared in the write proxy. Leave other bits"] - #[doc = " untouched. The write is done in a single atomic instruction."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " The resultant bit pattern may not be valid for the register."] - #[inline(always)] - pub unsafe fn clear_bits(&self, f: F) - where - F: FnOnce(&mut REG::Writer) -> &mut W, - { - let bits = f(&mut REG::Writer::from(W { - bits: !REG::Ux::default(), - _reg: marker::PhantomData, - })) - .bits; - REG::Ux::atomic_and(self.register.as_ptr(), bits); - } - #[doc = " Toggle every bit in the register that was set in the write proxy. Leave other bits"] - #[doc = " untouched. The write is done in a single atomic instruction."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " The resultant bit pattern may not be valid for the register."] - #[inline(always)] - pub unsafe fn toggle_bits(&self, f: F) - where - F: FnOnce(&mut REG::Writer) -> &mut W, - { - let bits = f(&mut REG::Writer::from(W { - bits: Default::default(), - _reg: marker::PhantomData, - })) - .bits; - REG::Ux::atomic_xor(self.register.as_ptr(), bits); - } -} diff --git a/crates/bcm2835-lpa/src/generic/atomic.rs b/crates/bcm2835-lpa/src/generic/atomic.rs index acee997..89d6c54 100644 --- a/crates/bcm2835-lpa/src/generic/atomic.rs +++ b/crates/bcm2835-lpa/src/generic/atomic.rs @@ -1,3 +1,4 @@ +use super::*; use portable_atomic::Ordering; pub trait AtomicOperations { unsafe fn atomic_or(ptr: *mut Self, val: Self); @@ -25,3 +26,62 @@ impl_atomics!(u16, portable_atomic::AtomicU16); impl_atomics!(u32, portable_atomic::AtomicU32); #[cfg(any(target_pointer_width = "64", target_has_atomic = "64"))] impl_atomics!(u64, portable_atomic::AtomicU64); +impl Reg +where + REG::Ux: AtomicOperations + Default + core::ops::Not, +{ + #[doc = " Set high every bit in the register that was set in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn set_bits(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + let bits = f(&mut W { + bits: Default::default(), + _reg: marker::PhantomData, + }) + .bits; + REG::Ux::atomic_or(self.register.as_ptr(), bits); + } + #[doc = " Clear every bit in the register that was cleared in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn clear_bits(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + let bits = f(&mut W { + bits: !REG::Ux::default(), + _reg: marker::PhantomData, + }) + .bits; + REG::Ux::atomic_and(self.register.as_ptr(), bits); + } + #[doc = " Toggle every bit in the register that was set in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn toggle_bits(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + let bits = f(&mut W { + bits: Default::default(), + _reg: marker::PhantomData, + }) + .bits; + REG::Ux::atomic_xor(self.register.as_ptr(), bits); + } +} diff --git a/crates/bcm2835-lpa/src/generic/raw.rs b/crates/bcm2835-lpa/src/generic/raw.rs new file mode 100644 index 0000000..4ab1635 --- /dev/null +++ b/crates/bcm2835-lpa/src/generic/raw.rs @@ -0,0 +1,89 @@ +use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; +pub struct R { + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct FieldReader +where + FI: FieldSpec, +{ + pub(crate) bits: FI::Ux, + _reg: marker::PhantomData, +} +impl FieldReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: FI::Ux) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct BitReader { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct FieldWriter<'a, REG, const WI: u8, const O: u8, FI = u8, Safety = Unsafe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + pub(crate) w: &'a mut W, + _field: marker::PhantomData<(FI, Safety)>, +} +impl<'a, REG, const WI: u8, const O: u8, FI, Safety> FieldWriter<'a, REG, WI, O, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +pub struct BitWriter<'a, REG, const O: u8, FI = bool, M = BitM> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut W, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, REG, const O: u8, FI, M> BitWriter<'a, REG, O, FI, M> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} diff --git a/crates/bcm2835-lpa/src/gpio.rs b/crates/bcm2835-lpa/src/gpio.rs index e643036..270dc41 100644 --- a/crates/bcm2835-lpa/src/gpio.rs +++ b/crates/bcm2835-lpa/src/gpio.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - GPIO Function Select 0"] pub gpfsel0: GPFSEL0, @@ -76,130 +77,161 @@ pub struct RegisterBlock { #[doc = "0xf0 - GPIO Pull-up / Pull-down Register 3"] pub gpio_pup_pdn_cntrl_reg3: GPIO_PUP_PDN_CNTRL_REG3, } -#[doc = "GPFSEL0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL0 (rw) register accessor: GPIO Function Select 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel0`] +module"] pub type GPFSEL0 = crate::Reg; #[doc = "GPIO Function Select 0"] pub mod gpfsel0; -#[doc = "GPFSEL1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL1 (rw) register accessor: GPIO Function Select 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel1`] +module"] pub type GPFSEL1 = crate::Reg; #[doc = "GPIO Function Select 1"] pub mod gpfsel1; -#[doc = "GPFSEL2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL2 (rw) register accessor: GPIO Function Select 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel2`] +module"] pub type GPFSEL2 = crate::Reg; #[doc = "GPIO Function Select 2"] pub mod gpfsel2; -#[doc = "GPFSEL3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL3 (rw) register accessor: GPIO Function Select 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel3`] +module"] pub type GPFSEL3 = crate::Reg; #[doc = "GPIO Function Select 3"] pub mod gpfsel3; -#[doc = "GPFSEL4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL4 (rw) register accessor: GPIO Function Select 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel4`] +module"] pub type GPFSEL4 = crate::Reg; #[doc = "GPIO Function Select 4"] pub mod gpfsel4; -#[doc = "GPFSEL5 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL5 (rw) register accessor: GPIO Function Select 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel5`] +module"] pub type GPFSEL5 = crate::Reg; #[doc = "GPIO Function Select 5"] pub mod gpfsel5; -#[doc = "GPSET0 (w) register accessor: an alias for `Reg`"] +#[doc = "GPSET0 (w) register accessor: GPIO Pin Output Set 0\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpset0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpset0`] +module"] pub type GPSET0 = crate::Reg; #[doc = "GPIO Pin Output Set 0"] pub mod gpset0; -#[doc = "GPSET1 (w) register accessor: an alias for `Reg`"] +#[doc = "GPSET1 (w) register accessor: GPIO Pin Output Set 1\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpset1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpset1`] +module"] pub type GPSET1 = crate::Reg; #[doc = "GPIO Pin Output Set 1"] pub mod gpset1; -#[doc = "GPCLR0 (w) register accessor: an alias for `Reg`"] +#[doc = "GPCLR0 (w) register accessor: GPIO Pin Output Clear 0\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpclr0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr0`] +module"] pub type GPCLR0 = crate::Reg; #[doc = "GPIO Pin Output Clear 0"] pub mod gpclr0; -#[doc = "GPCLR1 (w) register accessor: an alias for `Reg`"] +#[doc = "GPCLR1 (w) register accessor: GPIO Pin Output Clear 1\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpclr1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr1`] +module"] pub type GPCLR1 = crate::Reg; #[doc = "GPIO Pin Output Clear 1"] pub mod gpclr1; -#[doc = "GPLEV0 (r) register accessor: an alias for `Reg`"] +#[doc = "GPLEV0 (r) register accessor: GPIO Pin Level 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplev0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gplev0`] +module"] pub type GPLEV0 = crate::Reg; #[doc = "GPIO Pin Level 0"] pub mod gplev0; -#[doc = "GPLEV1 (r) register accessor: an alias for `Reg`"] +#[doc = "GPLEV1 (r) register accessor: GPIO Pin Level 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplev1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gplev1`] +module"] pub type GPLEV1 = crate::Reg; #[doc = "GPIO Pin Level 1"] pub mod gplev1; -#[doc = "GPEDS0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPEDS0 (rw) register accessor: GPIO Pin Event Detect Status 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpeds0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpeds0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpeds0`] +module"] pub type GPEDS0 = crate::Reg; #[doc = "GPIO Pin Event Detect Status 0"] pub mod gpeds0; -#[doc = "GPEDS1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPEDS1 (rw) register accessor: GPIO Pin Event Detect Status 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpeds1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpeds1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpeds1`] +module"] pub type GPEDS1 = crate::Reg; #[doc = "GPIO Pin Event Detect Status 1"] pub mod gpeds1; -#[doc = "GPREN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPREN0 (rw) register accessor: GPIO Pin Rising Edge Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpren0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpren0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpren0`] +module"] pub type GPREN0 = crate::Reg; #[doc = "GPIO Pin Rising Edge Detect Enable 0"] pub mod gpren0; -#[doc = "GPREN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPREN1 (rw) register accessor: GPIO Pin Rising Edge Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpren1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpren1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpren1`] +module"] pub type GPREN1 = crate::Reg; #[doc = "GPIO Pin Rising Edge Detect Enable 1"] pub mod gpren1; -#[doc = "GPFEN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFEN0 (rw) register accessor: GPIO Pin Falling Edge Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfen0`] +module"] pub type GPFEN0 = crate::Reg; #[doc = "GPIO Pin Falling Edge Detect Enable 0"] pub mod gpfen0; -#[doc = "GPFEN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFEN1 (rw) register accessor: GPIO Pin Falling Edge Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfen1`] +module"] pub type GPFEN1 = crate::Reg; #[doc = "GPIO Pin Falling Edge Detect Enable 1"] pub mod gpfen1; -#[doc = "GPHEN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPHEN0 (rw) register accessor: GPIO Pin High Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gphen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gphen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gphen0`] +module"] pub type GPHEN0 = crate::Reg; #[doc = "GPIO Pin High Detect Enable 0"] pub mod gphen0; -#[doc = "GPHEN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPHEN1 (rw) register accessor: GPIO Pin High Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gphen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gphen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gphen1`] +module"] pub type GPHEN1 = crate::Reg; #[doc = "GPIO Pin High Detect Enable 1"] pub mod gphen1; -#[doc = "GPLEN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPLEN0 (rw) register accessor: GPIO Pin Low Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gplen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gplen0`] +module"] pub type GPLEN0 = crate::Reg; #[doc = "GPIO Pin Low Detect Enable 0"] pub mod gplen0; -#[doc = "GPLEN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPLEN1 (rw) register accessor: GPIO Pin Low Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gplen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gplen1`] +module"] pub type GPLEN1 = crate::Reg; #[doc = "GPIO Pin Low Detect Enable 1"] pub mod gplen1; -#[doc = "GPAREN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPAREN0 (rw) register accessor: GPIO Pin Async. Rising Edge Detect 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gparen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gparen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gparen0`] +module"] pub type GPAREN0 = crate::Reg; #[doc = "GPIO Pin Async. Rising Edge Detect 0"] pub mod gparen0; -#[doc = "GPAREN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPAREN1 (rw) register accessor: GPIO Pin Async. Rising Edge Detect 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gparen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gparen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gparen1`] +module"] pub type GPAREN1 = crate::Reg; #[doc = "GPIO Pin Async. Rising Edge Detect 1"] pub mod gparen1; -#[doc = "GPAFEN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPAFEN0 (rw) register accessor: GPIO Pin Async. Falling Edge Detect 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpafen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpafen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpafen0`] +module"] pub type GPAFEN0 = crate::Reg; #[doc = "GPIO Pin Async. Falling Edge Detect 0"] pub mod gpafen0; -#[doc = "GPAFEN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPAFEN1 (rw) register accessor: GPIO Pin Async. Falling Edge Detect 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpafen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpafen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpafen1`] +module"] pub type GPAFEN1 = crate::Reg; #[doc = "GPIO Pin Async. Falling Edge Detect 1"] pub mod gpafen1; -#[doc = "EXTRA_MUX (rw) register accessor: an alias for `Reg`"] +#[doc = "EXTRA_MUX (rw) register accessor: Undocumented multiplexing bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extra_mux::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`extra_mux::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@extra_mux`] +module"] pub type EXTRA_MUX = crate::Reg; #[doc = "Undocumented multiplexing bits"] pub mod extra_mux; -#[doc = "GPIO_PUP_PDN_CNTRL_REG0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_PUP_PDN_CNTRL_REG0 (rw) register accessor: GPIO Pull-up / Pull-down Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pup_pdn_cntrl_reg0`] +module"] pub type GPIO_PUP_PDN_CNTRL_REG0 = crate::Reg; #[doc = "GPIO Pull-up / Pull-down Register 0"] pub mod gpio_pup_pdn_cntrl_reg0; -#[doc = "GPIO_PUP_PDN_CNTRL_REG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_PUP_PDN_CNTRL_REG1 (rw) register accessor: GPIO Pull-up / Pull-down Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pup_pdn_cntrl_reg1`] +module"] pub type GPIO_PUP_PDN_CNTRL_REG1 = crate::Reg; #[doc = "GPIO Pull-up / Pull-down Register 1"] pub mod gpio_pup_pdn_cntrl_reg1; -#[doc = "GPIO_PUP_PDN_CNTRL_REG2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_PUP_PDN_CNTRL_REG2 (rw) register accessor: GPIO Pull-up / Pull-down Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pup_pdn_cntrl_reg2`] +module"] pub type GPIO_PUP_PDN_CNTRL_REG2 = crate::Reg; #[doc = "GPIO Pull-up / Pull-down Register 2"] pub mod gpio_pup_pdn_cntrl_reg2; -#[doc = "GPIO_PUP_PDN_CNTRL_REG3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_PUP_PDN_CNTRL_REG3 (rw) register accessor: GPIO Pull-up / Pull-down Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pup_pdn_cntrl_reg3`] +module"] pub type GPIO_PUP_PDN_CNTRL_REG3 = crate::Reg; #[doc = "GPIO Pull-up / Pull-down Register 3"] diff --git a/crates/bcm2835-lpa/src/gpio/extra_mux.rs b/crates/bcm2835-lpa/src/gpio/extra_mux.rs index a35ba4f..bac06d5 100644 --- a/crates/bcm2835-lpa/src/gpio/extra_mux.rs +++ b/crates/bcm2835-lpa/src/gpio/extra_mux.rs @@ -1,39 +1,7 @@ #[doc = "Register `EXTRA_MUX` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EXTRA_MUX` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SDIO` reader - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] pub type SDIO_R = crate::BitReader; #[doc = "Switch peripheral connection to undocumented SDIO pins used on Pi 4"] @@ -53,34 +21,37 @@ impl From for bool { impl SDIO_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SDIO_A { + pub const fn variant(&self) -> SDIO_A { match self.bits { false => SDIO_A::SDHOST, true => SDIO_A::ARASAN, } } - #[doc = "Checks if the value of the field is `SDHOST`"] + #[doc = "Connect the newer SD host"] #[inline(always)] pub fn is_sdhost(&self) -> bool { *self == SDIO_A::SDHOST } - #[doc = "Checks if the value of the field is `ARASAN`"] + #[doc = "Connect Arasan SD/EMMC host"] #[inline(always)] pub fn is_arasan(&self) -> bool { *self == SDIO_A::ARASAN } } #[doc = "Field `SDIO` writer - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] -pub type SDIO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTRA_MUX_SPEC, SDIO_A, O>; -impl<'a, const O: u8> SDIO_W<'a, O> { +pub type SDIO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SDIO_A>; +impl<'a, REG, const O: u8> SDIO_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Connect the newer SD host"] #[inline(always)] - pub fn sdhost(self) -> &'a mut W { + pub fn sdhost(self) -> &'a mut crate::W { self.variant(SDIO_A::SDHOST) } #[doc = "Connect Arasan SD/EMMC host"] #[inline(always)] - pub fn arasan(self) -> &'a mut W { + pub fn arasan(self) -> &'a mut crate::W { self.variant(SDIO_A::ARASAN) } } @@ -91,32 +62,45 @@ impl R { SDIO_R::new(((self.bits >> 1) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXTRA_MUX") + .field("sdio", &format_args!("{}", self.sdio().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] #[inline(always)] #[must_use] - pub fn sdio(&mut self) -> SDIO_W<1> { + pub fn sdio(&mut self) -> SDIO_W { SDIO_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Undocumented multiplexing bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extra_mux](index.html) module"] +#[doc = "Undocumented multiplexing bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extra_mux::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`extra_mux::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EXTRA_MUX_SPEC; impl crate::RegisterSpec for EXTRA_MUX_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [extra_mux::R](R) reader structure"] -impl crate::Readable for EXTRA_MUX_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [extra_mux::W](W) writer structure"] +#[doc = "`read()` method returns [`extra_mux::R`](R) reader structure"] +impl crate::Readable for EXTRA_MUX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`extra_mux::W`](W) writer structure"] impl crate::Writable for EXTRA_MUX_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpafen0.rs b/crates/bcm2835-lpa/src/gpio/gpafen0.rs index 5c84fd8..44bf785 100644 --- a/crates/bcm2835-lpa/src/gpio/gpafen0.rs +++ b/crates/bcm2835-lpa/src/gpio/gpafen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPAFEN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPAFEN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AFEN0` reader - Async falling enabled 0"] -pub type AFEN0_R = crate::BitReader; +pub type AFEN0_R = crate::BitReader; #[doc = "Field `AFEN0` writer - Async falling enabled 0"] -pub type AFEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN1` reader - Async falling enabled 1"] -pub type AFEN1_R = crate::BitReader; +pub type AFEN1_R = crate::BitReader; #[doc = "Field `AFEN1` writer - Async falling enabled 1"] -pub type AFEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN2` reader - Async falling enabled 2"] -pub type AFEN2_R = crate::BitReader; +pub type AFEN2_R = crate::BitReader; #[doc = "Field `AFEN2` writer - Async falling enabled 2"] -pub type AFEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN3` reader - Async falling enabled 3"] -pub type AFEN3_R = crate::BitReader; +pub type AFEN3_R = crate::BitReader; #[doc = "Field `AFEN3` writer - Async falling enabled 3"] -pub type AFEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN4` reader - Async falling enabled 4"] -pub type AFEN4_R = crate::BitReader; +pub type AFEN4_R = crate::BitReader; #[doc = "Field `AFEN4` writer - Async falling enabled 4"] -pub type AFEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN5` reader - Async falling enabled 5"] -pub type AFEN5_R = crate::BitReader; +pub type AFEN5_R = crate::BitReader; #[doc = "Field `AFEN5` writer - Async falling enabled 5"] -pub type AFEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN6` reader - Async falling enabled 6"] -pub type AFEN6_R = crate::BitReader; +pub type AFEN6_R = crate::BitReader; #[doc = "Field `AFEN6` writer - Async falling enabled 6"] -pub type AFEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN7` reader - Async falling enabled 7"] -pub type AFEN7_R = crate::BitReader; +pub type AFEN7_R = crate::BitReader; #[doc = "Field `AFEN7` writer - Async falling enabled 7"] -pub type AFEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN8` reader - Async falling enabled 8"] -pub type AFEN8_R = crate::BitReader; +pub type AFEN8_R = crate::BitReader; #[doc = "Field `AFEN8` writer - Async falling enabled 8"] -pub type AFEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN9` reader - Async falling enabled 9"] -pub type AFEN9_R = crate::BitReader; +pub type AFEN9_R = crate::BitReader; #[doc = "Field `AFEN9` writer - Async falling enabled 9"] -pub type AFEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN10` reader - Async falling enabled 10"] -pub type AFEN10_R = crate::BitReader; +pub type AFEN10_R = crate::BitReader; #[doc = "Field `AFEN10` writer - Async falling enabled 10"] -pub type AFEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN11` reader - Async falling enabled 11"] -pub type AFEN11_R = crate::BitReader; +pub type AFEN11_R = crate::BitReader; #[doc = "Field `AFEN11` writer - Async falling enabled 11"] -pub type AFEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN12` reader - Async falling enabled 12"] -pub type AFEN12_R = crate::BitReader; +pub type AFEN12_R = crate::BitReader; #[doc = "Field `AFEN12` writer - Async falling enabled 12"] -pub type AFEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN13` reader - Async falling enabled 13"] -pub type AFEN13_R = crate::BitReader; +pub type AFEN13_R = crate::BitReader; #[doc = "Field `AFEN13` writer - Async falling enabled 13"] -pub type AFEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN14` reader - Async falling enabled 14"] -pub type AFEN14_R = crate::BitReader; +pub type AFEN14_R = crate::BitReader; #[doc = "Field `AFEN14` writer - Async falling enabled 14"] -pub type AFEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN15` reader - Async falling enabled 15"] -pub type AFEN15_R = crate::BitReader; +pub type AFEN15_R = crate::BitReader; #[doc = "Field `AFEN15` writer - Async falling enabled 15"] -pub type AFEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN16` reader - Async falling enabled 16"] -pub type AFEN16_R = crate::BitReader; +pub type AFEN16_R = crate::BitReader; #[doc = "Field `AFEN16` writer - Async falling enabled 16"] -pub type AFEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN17` reader - Async falling enabled 17"] -pub type AFEN17_R = crate::BitReader; +pub type AFEN17_R = crate::BitReader; #[doc = "Field `AFEN17` writer - Async falling enabled 17"] -pub type AFEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN18` reader - Async falling enabled 18"] -pub type AFEN18_R = crate::BitReader; +pub type AFEN18_R = crate::BitReader; #[doc = "Field `AFEN18` writer - Async falling enabled 18"] -pub type AFEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN19` reader - Async falling enabled 19"] -pub type AFEN19_R = crate::BitReader; +pub type AFEN19_R = crate::BitReader; #[doc = "Field `AFEN19` writer - Async falling enabled 19"] -pub type AFEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN20` reader - Async falling enabled 20"] -pub type AFEN20_R = crate::BitReader; +pub type AFEN20_R = crate::BitReader; #[doc = "Field `AFEN20` writer - Async falling enabled 20"] -pub type AFEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN21` reader - Async falling enabled 21"] -pub type AFEN21_R = crate::BitReader; +pub type AFEN21_R = crate::BitReader; #[doc = "Field `AFEN21` writer - Async falling enabled 21"] -pub type AFEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN22` reader - Async falling enabled 22"] -pub type AFEN22_R = crate::BitReader; +pub type AFEN22_R = crate::BitReader; #[doc = "Field `AFEN22` writer - Async falling enabled 22"] -pub type AFEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN23` reader - Async falling enabled 23"] -pub type AFEN23_R = crate::BitReader; +pub type AFEN23_R = crate::BitReader; #[doc = "Field `AFEN23` writer - Async falling enabled 23"] -pub type AFEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN24` reader - Async falling enabled 24"] -pub type AFEN24_R = crate::BitReader; +pub type AFEN24_R = crate::BitReader; #[doc = "Field `AFEN24` writer - Async falling enabled 24"] -pub type AFEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN25` reader - Async falling enabled 25"] -pub type AFEN25_R = crate::BitReader; +pub type AFEN25_R = crate::BitReader; #[doc = "Field `AFEN25` writer - Async falling enabled 25"] -pub type AFEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN26` reader - Async falling enabled 26"] -pub type AFEN26_R = crate::BitReader; +pub type AFEN26_R = crate::BitReader; #[doc = "Field `AFEN26` writer - Async falling enabled 26"] -pub type AFEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN27` reader - Async falling enabled 27"] -pub type AFEN27_R = crate::BitReader; +pub type AFEN27_R = crate::BitReader; #[doc = "Field `AFEN27` writer - Async falling enabled 27"] -pub type AFEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN28` reader - Async falling enabled 28"] -pub type AFEN28_R = crate::BitReader; +pub type AFEN28_R = crate::BitReader; #[doc = "Field `AFEN28` writer - Async falling enabled 28"] -pub type AFEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN29` reader - Async falling enabled 29"] -pub type AFEN29_R = crate::BitReader; +pub type AFEN29_R = crate::BitReader; #[doc = "Field `AFEN29` writer - Async falling enabled 29"] -pub type AFEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN30` reader - Async falling enabled 30"] -pub type AFEN30_R = crate::BitReader; +pub type AFEN30_R = crate::BitReader; #[doc = "Field `AFEN30` writer - Async falling enabled 30"] -pub type AFEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN31` reader - Async falling enabled 31"] -pub type AFEN31_R = crate::BitReader; +pub type AFEN31_R = crate::BitReader; #[doc = "Field `AFEN31` writer - Async falling enabled 31"] -pub type AFEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Async falling enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { AFEN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPAFEN0") + .field("afen0", &format_args!("{}", self.afen0().bit())) + .field("afen1", &format_args!("{}", self.afen1().bit())) + .field("afen2", &format_args!("{}", self.afen2().bit())) + .field("afen3", &format_args!("{}", self.afen3().bit())) + .field("afen4", &format_args!("{}", self.afen4().bit())) + .field("afen5", &format_args!("{}", self.afen5().bit())) + .field("afen6", &format_args!("{}", self.afen6().bit())) + .field("afen7", &format_args!("{}", self.afen7().bit())) + .field("afen8", &format_args!("{}", self.afen8().bit())) + .field("afen9", &format_args!("{}", self.afen9().bit())) + .field("afen10", &format_args!("{}", self.afen10().bit())) + .field("afen11", &format_args!("{}", self.afen11().bit())) + .field("afen12", &format_args!("{}", self.afen12().bit())) + .field("afen13", &format_args!("{}", self.afen13().bit())) + .field("afen14", &format_args!("{}", self.afen14().bit())) + .field("afen15", &format_args!("{}", self.afen15().bit())) + .field("afen16", &format_args!("{}", self.afen16().bit())) + .field("afen17", &format_args!("{}", self.afen17().bit())) + .field("afen18", &format_args!("{}", self.afen18().bit())) + .field("afen19", &format_args!("{}", self.afen19().bit())) + .field("afen20", &format_args!("{}", self.afen20().bit())) + .field("afen21", &format_args!("{}", self.afen21().bit())) + .field("afen22", &format_args!("{}", self.afen22().bit())) + .field("afen23", &format_args!("{}", self.afen23().bit())) + .field("afen24", &format_args!("{}", self.afen24().bit())) + .field("afen25", &format_args!("{}", self.afen25().bit())) + .field("afen26", &format_args!("{}", self.afen26().bit())) + .field("afen27", &format_args!("{}", self.afen27().bit())) + .field("afen28", &format_args!("{}", self.afen28().bit())) + .field("afen29", &format_args!("{}", self.afen29().bit())) + .field("afen30", &format_args!("{}", self.afen30().bit())) + .field("afen31", &format_args!("{}", self.afen31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Async falling enabled 0"] #[inline(always)] #[must_use] - pub fn afen0(&mut self) -> AFEN0_W<0> { + pub fn afen0(&mut self) -> AFEN0_W { AFEN0_W::new(self) } #[doc = "Bit 1 - Async falling enabled 1"] #[inline(always)] #[must_use] - pub fn afen1(&mut self) -> AFEN1_W<1> { + pub fn afen1(&mut self) -> AFEN1_W { AFEN1_W::new(self) } #[doc = "Bit 2 - Async falling enabled 2"] #[inline(always)] #[must_use] - pub fn afen2(&mut self) -> AFEN2_W<2> { + pub fn afen2(&mut self) -> AFEN2_W { AFEN2_W::new(self) } #[doc = "Bit 3 - Async falling enabled 3"] #[inline(always)] #[must_use] - pub fn afen3(&mut self) -> AFEN3_W<3> { + pub fn afen3(&mut self) -> AFEN3_W { AFEN3_W::new(self) } #[doc = "Bit 4 - Async falling enabled 4"] #[inline(always)] #[must_use] - pub fn afen4(&mut self) -> AFEN4_W<4> { + pub fn afen4(&mut self) -> AFEN4_W { AFEN4_W::new(self) } #[doc = "Bit 5 - Async falling enabled 5"] #[inline(always)] #[must_use] - pub fn afen5(&mut self) -> AFEN5_W<5> { + pub fn afen5(&mut self) -> AFEN5_W { AFEN5_W::new(self) } #[doc = "Bit 6 - Async falling enabled 6"] #[inline(always)] #[must_use] - pub fn afen6(&mut self) -> AFEN6_W<6> { + pub fn afen6(&mut self) -> AFEN6_W { AFEN6_W::new(self) } #[doc = "Bit 7 - Async falling enabled 7"] #[inline(always)] #[must_use] - pub fn afen7(&mut self) -> AFEN7_W<7> { + pub fn afen7(&mut self) -> AFEN7_W { AFEN7_W::new(self) } #[doc = "Bit 8 - Async falling enabled 8"] #[inline(always)] #[must_use] - pub fn afen8(&mut self) -> AFEN8_W<8> { + pub fn afen8(&mut self) -> AFEN8_W { AFEN8_W::new(self) } #[doc = "Bit 9 - Async falling enabled 9"] #[inline(always)] #[must_use] - pub fn afen9(&mut self) -> AFEN9_W<9> { + pub fn afen9(&mut self) -> AFEN9_W { AFEN9_W::new(self) } #[doc = "Bit 10 - Async falling enabled 10"] #[inline(always)] #[must_use] - pub fn afen10(&mut self) -> AFEN10_W<10> { + pub fn afen10(&mut self) -> AFEN10_W { AFEN10_W::new(self) } #[doc = "Bit 11 - Async falling enabled 11"] #[inline(always)] #[must_use] - pub fn afen11(&mut self) -> AFEN11_W<11> { + pub fn afen11(&mut self) -> AFEN11_W { AFEN11_W::new(self) } #[doc = "Bit 12 - Async falling enabled 12"] #[inline(always)] #[must_use] - pub fn afen12(&mut self) -> AFEN12_W<12> { + pub fn afen12(&mut self) -> AFEN12_W { AFEN12_W::new(self) } #[doc = "Bit 13 - Async falling enabled 13"] #[inline(always)] #[must_use] - pub fn afen13(&mut self) -> AFEN13_W<13> { + pub fn afen13(&mut self) -> AFEN13_W { AFEN13_W::new(self) } #[doc = "Bit 14 - Async falling enabled 14"] #[inline(always)] #[must_use] - pub fn afen14(&mut self) -> AFEN14_W<14> { + pub fn afen14(&mut self) -> AFEN14_W { AFEN14_W::new(self) } #[doc = "Bit 15 - Async falling enabled 15"] #[inline(always)] #[must_use] - pub fn afen15(&mut self) -> AFEN15_W<15> { + pub fn afen15(&mut self) -> AFEN15_W { AFEN15_W::new(self) } #[doc = "Bit 16 - Async falling enabled 16"] #[inline(always)] #[must_use] - pub fn afen16(&mut self) -> AFEN16_W<16> { + pub fn afen16(&mut self) -> AFEN16_W { AFEN16_W::new(self) } #[doc = "Bit 17 - Async falling enabled 17"] #[inline(always)] #[must_use] - pub fn afen17(&mut self) -> AFEN17_W<17> { + pub fn afen17(&mut self) -> AFEN17_W { AFEN17_W::new(self) } #[doc = "Bit 18 - Async falling enabled 18"] #[inline(always)] #[must_use] - pub fn afen18(&mut self) -> AFEN18_W<18> { + pub fn afen18(&mut self) -> AFEN18_W { AFEN18_W::new(self) } #[doc = "Bit 19 - Async falling enabled 19"] #[inline(always)] #[must_use] - pub fn afen19(&mut self) -> AFEN19_W<19> { + pub fn afen19(&mut self) -> AFEN19_W { AFEN19_W::new(self) } #[doc = "Bit 20 - Async falling enabled 20"] #[inline(always)] #[must_use] - pub fn afen20(&mut self) -> AFEN20_W<20> { + pub fn afen20(&mut self) -> AFEN20_W { AFEN20_W::new(self) } #[doc = "Bit 21 - Async falling enabled 21"] #[inline(always)] #[must_use] - pub fn afen21(&mut self) -> AFEN21_W<21> { + pub fn afen21(&mut self) -> AFEN21_W { AFEN21_W::new(self) } #[doc = "Bit 22 - Async falling enabled 22"] #[inline(always)] #[must_use] - pub fn afen22(&mut self) -> AFEN22_W<22> { + pub fn afen22(&mut self) -> AFEN22_W { AFEN22_W::new(self) } #[doc = "Bit 23 - Async falling enabled 23"] #[inline(always)] #[must_use] - pub fn afen23(&mut self) -> AFEN23_W<23> { + pub fn afen23(&mut self) -> AFEN23_W { AFEN23_W::new(self) } #[doc = "Bit 24 - Async falling enabled 24"] #[inline(always)] #[must_use] - pub fn afen24(&mut self) -> AFEN24_W<24> { + pub fn afen24(&mut self) -> AFEN24_W { AFEN24_W::new(self) } #[doc = "Bit 25 - Async falling enabled 25"] #[inline(always)] #[must_use] - pub fn afen25(&mut self) -> AFEN25_W<25> { + pub fn afen25(&mut self) -> AFEN25_W { AFEN25_W::new(self) } #[doc = "Bit 26 - Async falling enabled 26"] #[inline(always)] #[must_use] - pub fn afen26(&mut self) -> AFEN26_W<26> { + pub fn afen26(&mut self) -> AFEN26_W { AFEN26_W::new(self) } #[doc = "Bit 27 - Async falling enabled 27"] #[inline(always)] #[must_use] - pub fn afen27(&mut self) -> AFEN27_W<27> { + pub fn afen27(&mut self) -> AFEN27_W { AFEN27_W::new(self) } #[doc = "Bit 28 - Async falling enabled 28"] #[inline(always)] #[must_use] - pub fn afen28(&mut self) -> AFEN28_W<28> { + pub fn afen28(&mut self) -> AFEN28_W { AFEN28_W::new(self) } #[doc = "Bit 29 - Async falling enabled 29"] #[inline(always)] #[must_use] - pub fn afen29(&mut self) -> AFEN29_W<29> { + pub fn afen29(&mut self) -> AFEN29_W { AFEN29_W::new(self) } #[doc = "Bit 30 - Async falling enabled 30"] #[inline(always)] #[must_use] - pub fn afen30(&mut self) -> AFEN30_W<30> { + pub fn afen30(&mut self) -> AFEN30_W { AFEN30_W::new(self) } #[doc = "Bit 31 - Async falling enabled 31"] #[inline(always)] #[must_use] - pub fn afen31(&mut self) -> AFEN31_W<31> { + pub fn afen31(&mut self) -> AFEN31_W { AFEN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Async. Falling Edge Detect 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpafen0](index.html) module"] +#[doc = "GPIO Pin Async. Falling Edge Detect 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpafen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpafen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPAFEN0_SPEC; impl crate::RegisterSpec for GPAFEN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpafen0::R](R) reader structure"] -impl crate::Readable for GPAFEN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpafen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpafen0::R`](R) reader structure"] +impl crate::Readable for GPAFEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpafen0::W`](W) writer structure"] impl crate::Writable for GPAFEN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpafen1.rs b/crates/bcm2835-lpa/src/gpio/gpafen1.rs index a87edeb..83ed52d 100644 --- a/crates/bcm2835-lpa/src/gpio/gpafen1.rs +++ b/crates/bcm2835-lpa/src/gpio/gpafen1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPAFEN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPAFEN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AFEN32` reader - Async falling enabled 32"] -pub type AFEN32_R = crate::BitReader; +pub type AFEN32_R = crate::BitReader; #[doc = "Field `AFEN32` writer - Async falling enabled 32"] -pub type AFEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN33` reader - Async falling enabled 33"] -pub type AFEN33_R = crate::BitReader; +pub type AFEN33_R = crate::BitReader; #[doc = "Field `AFEN33` writer - Async falling enabled 33"] -pub type AFEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN34` reader - Async falling enabled 34"] -pub type AFEN34_R = crate::BitReader; +pub type AFEN34_R = crate::BitReader; #[doc = "Field `AFEN34` writer - Async falling enabled 34"] -pub type AFEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN35` reader - Async falling enabled 35"] -pub type AFEN35_R = crate::BitReader; +pub type AFEN35_R = crate::BitReader; #[doc = "Field `AFEN35` writer - Async falling enabled 35"] -pub type AFEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN36` reader - Async falling enabled 36"] -pub type AFEN36_R = crate::BitReader; +pub type AFEN36_R = crate::BitReader; #[doc = "Field `AFEN36` writer - Async falling enabled 36"] -pub type AFEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN37` reader - Async falling enabled 37"] -pub type AFEN37_R = crate::BitReader; +pub type AFEN37_R = crate::BitReader; #[doc = "Field `AFEN37` writer - Async falling enabled 37"] -pub type AFEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN38` reader - Async falling enabled 38"] -pub type AFEN38_R = crate::BitReader; +pub type AFEN38_R = crate::BitReader; #[doc = "Field `AFEN38` writer - Async falling enabled 38"] -pub type AFEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN39` reader - Async falling enabled 39"] -pub type AFEN39_R = crate::BitReader; +pub type AFEN39_R = crate::BitReader; #[doc = "Field `AFEN39` writer - Async falling enabled 39"] -pub type AFEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN40` reader - Async falling enabled 40"] -pub type AFEN40_R = crate::BitReader; +pub type AFEN40_R = crate::BitReader; #[doc = "Field `AFEN40` writer - Async falling enabled 40"] -pub type AFEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN41` reader - Async falling enabled 41"] -pub type AFEN41_R = crate::BitReader; +pub type AFEN41_R = crate::BitReader; #[doc = "Field `AFEN41` writer - Async falling enabled 41"] -pub type AFEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN42` reader - Async falling enabled 42"] -pub type AFEN42_R = crate::BitReader; +pub type AFEN42_R = crate::BitReader; #[doc = "Field `AFEN42` writer - Async falling enabled 42"] -pub type AFEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN43` reader - Async falling enabled 43"] -pub type AFEN43_R = crate::BitReader; +pub type AFEN43_R = crate::BitReader; #[doc = "Field `AFEN43` writer - Async falling enabled 43"] -pub type AFEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN44` reader - Async falling enabled 44"] -pub type AFEN44_R = crate::BitReader; +pub type AFEN44_R = crate::BitReader; #[doc = "Field `AFEN44` writer - Async falling enabled 44"] -pub type AFEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN45` reader - Async falling enabled 45"] -pub type AFEN45_R = crate::BitReader; +pub type AFEN45_R = crate::BitReader; #[doc = "Field `AFEN45` writer - Async falling enabled 45"] -pub type AFEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN46` reader - Async falling enabled 46"] -pub type AFEN46_R = crate::BitReader; +pub type AFEN46_R = crate::BitReader; #[doc = "Field `AFEN46` writer - Async falling enabled 46"] -pub type AFEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN47` reader - Async falling enabled 47"] -pub type AFEN47_R = crate::BitReader; +pub type AFEN47_R = crate::BitReader; #[doc = "Field `AFEN47` writer - Async falling enabled 47"] -pub type AFEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN48` reader - Async falling enabled 48"] -pub type AFEN48_R = crate::BitReader; +pub type AFEN48_R = crate::BitReader; #[doc = "Field `AFEN48` writer - Async falling enabled 48"] -pub type AFEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN49` reader - Async falling enabled 49"] -pub type AFEN49_R = crate::BitReader; +pub type AFEN49_R = crate::BitReader; #[doc = "Field `AFEN49` writer - Async falling enabled 49"] -pub type AFEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN50` reader - Async falling enabled 50"] -pub type AFEN50_R = crate::BitReader; +pub type AFEN50_R = crate::BitReader; #[doc = "Field `AFEN50` writer - Async falling enabled 50"] -pub type AFEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN51` reader - Async falling enabled 51"] -pub type AFEN51_R = crate::BitReader; +pub type AFEN51_R = crate::BitReader; #[doc = "Field `AFEN51` writer - Async falling enabled 51"] -pub type AFEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN52` reader - Async falling enabled 52"] -pub type AFEN52_R = crate::BitReader; +pub type AFEN52_R = crate::BitReader; #[doc = "Field `AFEN52` writer - Async falling enabled 52"] -pub type AFEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN53` reader - Async falling enabled 53"] -pub type AFEN53_R = crate::BitReader; +pub type AFEN53_R = crate::BitReader; #[doc = "Field `AFEN53` writer - Async falling enabled 53"] -pub type AFEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Async falling enabled 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { AFEN53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPAFEN1") + .field("afen32", &format_args!("{}", self.afen32().bit())) + .field("afen33", &format_args!("{}", self.afen33().bit())) + .field("afen34", &format_args!("{}", self.afen34().bit())) + .field("afen35", &format_args!("{}", self.afen35().bit())) + .field("afen36", &format_args!("{}", self.afen36().bit())) + .field("afen37", &format_args!("{}", self.afen37().bit())) + .field("afen38", &format_args!("{}", self.afen38().bit())) + .field("afen39", &format_args!("{}", self.afen39().bit())) + .field("afen40", &format_args!("{}", self.afen40().bit())) + .field("afen41", &format_args!("{}", self.afen41().bit())) + .field("afen42", &format_args!("{}", self.afen42().bit())) + .field("afen43", &format_args!("{}", self.afen43().bit())) + .field("afen44", &format_args!("{}", self.afen44().bit())) + .field("afen45", &format_args!("{}", self.afen45().bit())) + .field("afen46", &format_args!("{}", self.afen46().bit())) + .field("afen47", &format_args!("{}", self.afen47().bit())) + .field("afen48", &format_args!("{}", self.afen48().bit())) + .field("afen49", &format_args!("{}", self.afen49().bit())) + .field("afen50", &format_args!("{}", self.afen50().bit())) + .field("afen51", &format_args!("{}", self.afen51().bit())) + .field("afen52", &format_args!("{}", self.afen52().bit())) + .field("afen53", &format_args!("{}", self.afen53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Async falling enabled 32"] #[inline(always)] #[must_use] - pub fn afen32(&mut self) -> AFEN32_W<0> { + pub fn afen32(&mut self) -> AFEN32_W { AFEN32_W::new(self) } #[doc = "Bit 1 - Async falling enabled 33"] #[inline(always)] #[must_use] - pub fn afen33(&mut self) -> AFEN33_W<1> { + pub fn afen33(&mut self) -> AFEN33_W { AFEN33_W::new(self) } #[doc = "Bit 2 - Async falling enabled 34"] #[inline(always)] #[must_use] - pub fn afen34(&mut self) -> AFEN34_W<2> { + pub fn afen34(&mut self) -> AFEN34_W { AFEN34_W::new(self) } #[doc = "Bit 3 - Async falling enabled 35"] #[inline(always)] #[must_use] - pub fn afen35(&mut self) -> AFEN35_W<3> { + pub fn afen35(&mut self) -> AFEN35_W { AFEN35_W::new(self) } #[doc = "Bit 4 - Async falling enabled 36"] #[inline(always)] #[must_use] - pub fn afen36(&mut self) -> AFEN36_W<4> { + pub fn afen36(&mut self) -> AFEN36_W { AFEN36_W::new(self) } #[doc = "Bit 5 - Async falling enabled 37"] #[inline(always)] #[must_use] - pub fn afen37(&mut self) -> AFEN37_W<5> { + pub fn afen37(&mut self) -> AFEN37_W { AFEN37_W::new(self) } #[doc = "Bit 6 - Async falling enabled 38"] #[inline(always)] #[must_use] - pub fn afen38(&mut self) -> AFEN38_W<6> { + pub fn afen38(&mut self) -> AFEN38_W { AFEN38_W::new(self) } #[doc = "Bit 7 - Async falling enabled 39"] #[inline(always)] #[must_use] - pub fn afen39(&mut self) -> AFEN39_W<7> { + pub fn afen39(&mut self) -> AFEN39_W { AFEN39_W::new(self) } #[doc = "Bit 8 - Async falling enabled 40"] #[inline(always)] #[must_use] - pub fn afen40(&mut self) -> AFEN40_W<8> { + pub fn afen40(&mut self) -> AFEN40_W { AFEN40_W::new(self) } #[doc = "Bit 9 - Async falling enabled 41"] #[inline(always)] #[must_use] - pub fn afen41(&mut self) -> AFEN41_W<9> { + pub fn afen41(&mut self) -> AFEN41_W { AFEN41_W::new(self) } #[doc = "Bit 10 - Async falling enabled 42"] #[inline(always)] #[must_use] - pub fn afen42(&mut self) -> AFEN42_W<10> { + pub fn afen42(&mut self) -> AFEN42_W { AFEN42_W::new(self) } #[doc = "Bit 11 - Async falling enabled 43"] #[inline(always)] #[must_use] - pub fn afen43(&mut self) -> AFEN43_W<11> { + pub fn afen43(&mut self) -> AFEN43_W { AFEN43_W::new(self) } #[doc = "Bit 12 - Async falling enabled 44"] #[inline(always)] #[must_use] - pub fn afen44(&mut self) -> AFEN44_W<12> { + pub fn afen44(&mut self) -> AFEN44_W { AFEN44_W::new(self) } #[doc = "Bit 13 - Async falling enabled 45"] #[inline(always)] #[must_use] - pub fn afen45(&mut self) -> AFEN45_W<13> { + pub fn afen45(&mut self) -> AFEN45_W { AFEN45_W::new(self) } #[doc = "Bit 14 - Async falling enabled 46"] #[inline(always)] #[must_use] - pub fn afen46(&mut self) -> AFEN46_W<14> { + pub fn afen46(&mut self) -> AFEN46_W { AFEN46_W::new(self) } #[doc = "Bit 15 - Async falling enabled 47"] #[inline(always)] #[must_use] - pub fn afen47(&mut self) -> AFEN47_W<15> { + pub fn afen47(&mut self) -> AFEN47_W { AFEN47_W::new(self) } #[doc = "Bit 16 - Async falling enabled 48"] #[inline(always)] #[must_use] - pub fn afen48(&mut self) -> AFEN48_W<16> { + pub fn afen48(&mut self) -> AFEN48_W { AFEN48_W::new(self) } #[doc = "Bit 17 - Async falling enabled 49"] #[inline(always)] #[must_use] - pub fn afen49(&mut self) -> AFEN49_W<17> { + pub fn afen49(&mut self) -> AFEN49_W { AFEN49_W::new(self) } #[doc = "Bit 18 - Async falling enabled 50"] #[inline(always)] #[must_use] - pub fn afen50(&mut self) -> AFEN50_W<18> { + pub fn afen50(&mut self) -> AFEN50_W { AFEN50_W::new(self) } #[doc = "Bit 19 - Async falling enabled 51"] #[inline(always)] #[must_use] - pub fn afen51(&mut self) -> AFEN51_W<19> { + pub fn afen51(&mut self) -> AFEN51_W { AFEN51_W::new(self) } #[doc = "Bit 20 - Async falling enabled 52"] #[inline(always)] #[must_use] - pub fn afen52(&mut self) -> AFEN52_W<20> { + pub fn afen52(&mut self) -> AFEN52_W { AFEN52_W::new(self) } #[doc = "Bit 21 - Async falling enabled 53"] #[inline(always)] #[must_use] - pub fn afen53(&mut self) -> AFEN53_W<21> { + pub fn afen53(&mut self) -> AFEN53_W { AFEN53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Async. Falling Edge Detect 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpafen1](index.html) module"] +#[doc = "GPIO Pin Async. Falling Edge Detect 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpafen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpafen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPAFEN1_SPEC; impl crate::RegisterSpec for GPAFEN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpafen1::R](R) reader structure"] -impl crate::Readable for GPAFEN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpafen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpafen1::R`](R) reader structure"] +impl crate::Readable for GPAFEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpafen1::W`](W) writer structure"] impl crate::Writable for GPAFEN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gparen0.rs b/crates/bcm2835-lpa/src/gpio/gparen0.rs index f4ef746..ac719d0 100644 --- a/crates/bcm2835-lpa/src/gpio/gparen0.rs +++ b/crates/bcm2835-lpa/src/gpio/gparen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPAREN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPAREN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AREN0` reader - Async rising enabled 0"] -pub type AREN0_R = crate::BitReader; +pub type AREN0_R = crate::BitReader; #[doc = "Field `AREN0` writer - Async rising enabled 0"] -pub type AREN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN1` reader - Async rising enabled 1"] -pub type AREN1_R = crate::BitReader; +pub type AREN1_R = crate::BitReader; #[doc = "Field `AREN1` writer - Async rising enabled 1"] -pub type AREN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN2` reader - Async rising enabled 2"] -pub type AREN2_R = crate::BitReader; +pub type AREN2_R = crate::BitReader; #[doc = "Field `AREN2` writer - Async rising enabled 2"] -pub type AREN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN3` reader - Async rising enabled 3"] -pub type AREN3_R = crate::BitReader; +pub type AREN3_R = crate::BitReader; #[doc = "Field `AREN3` writer - Async rising enabled 3"] -pub type AREN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN4` reader - Async rising enabled 4"] -pub type AREN4_R = crate::BitReader; +pub type AREN4_R = crate::BitReader; #[doc = "Field `AREN4` writer - Async rising enabled 4"] -pub type AREN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN5` reader - Async rising enabled 5"] -pub type AREN5_R = crate::BitReader; +pub type AREN5_R = crate::BitReader; #[doc = "Field `AREN5` writer - Async rising enabled 5"] -pub type AREN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN6` reader - Async rising enabled 6"] -pub type AREN6_R = crate::BitReader; +pub type AREN6_R = crate::BitReader; #[doc = "Field `AREN6` writer - Async rising enabled 6"] -pub type AREN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN7` reader - Async rising enabled 7"] -pub type AREN7_R = crate::BitReader; +pub type AREN7_R = crate::BitReader; #[doc = "Field `AREN7` writer - Async rising enabled 7"] -pub type AREN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN8` reader - Async rising enabled 8"] -pub type AREN8_R = crate::BitReader; +pub type AREN8_R = crate::BitReader; #[doc = "Field `AREN8` writer - Async rising enabled 8"] -pub type AREN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN9` reader - Async rising enabled 9"] -pub type AREN9_R = crate::BitReader; +pub type AREN9_R = crate::BitReader; #[doc = "Field `AREN9` writer - Async rising enabled 9"] -pub type AREN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN10` reader - Async rising enabled 10"] -pub type AREN10_R = crate::BitReader; +pub type AREN10_R = crate::BitReader; #[doc = "Field `AREN10` writer - Async rising enabled 10"] -pub type AREN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN11` reader - Async rising enabled 11"] -pub type AREN11_R = crate::BitReader; +pub type AREN11_R = crate::BitReader; #[doc = "Field `AREN11` writer - Async rising enabled 11"] -pub type AREN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN12` reader - Async rising enabled 12"] -pub type AREN12_R = crate::BitReader; +pub type AREN12_R = crate::BitReader; #[doc = "Field `AREN12` writer - Async rising enabled 12"] -pub type AREN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN13` reader - Async rising enabled 13"] -pub type AREN13_R = crate::BitReader; +pub type AREN13_R = crate::BitReader; #[doc = "Field `AREN13` writer - Async rising enabled 13"] -pub type AREN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN14` reader - Async rising enabled 14"] -pub type AREN14_R = crate::BitReader; +pub type AREN14_R = crate::BitReader; #[doc = "Field `AREN14` writer - Async rising enabled 14"] -pub type AREN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN15` reader - Async rising enabled 15"] -pub type AREN15_R = crate::BitReader; +pub type AREN15_R = crate::BitReader; #[doc = "Field `AREN15` writer - Async rising enabled 15"] -pub type AREN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN16` reader - Async rising enabled 16"] -pub type AREN16_R = crate::BitReader; +pub type AREN16_R = crate::BitReader; #[doc = "Field `AREN16` writer - Async rising enabled 16"] -pub type AREN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN17` reader - Async rising enabled 17"] -pub type AREN17_R = crate::BitReader; +pub type AREN17_R = crate::BitReader; #[doc = "Field `AREN17` writer - Async rising enabled 17"] -pub type AREN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN18` reader - Async rising enabled 18"] -pub type AREN18_R = crate::BitReader; +pub type AREN18_R = crate::BitReader; #[doc = "Field `AREN18` writer - Async rising enabled 18"] -pub type AREN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN19` reader - Async rising enabled 19"] -pub type AREN19_R = crate::BitReader; +pub type AREN19_R = crate::BitReader; #[doc = "Field `AREN19` writer - Async rising enabled 19"] -pub type AREN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN20` reader - Async rising enabled 20"] -pub type AREN20_R = crate::BitReader; +pub type AREN20_R = crate::BitReader; #[doc = "Field `AREN20` writer - Async rising enabled 20"] -pub type AREN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN21` reader - Async rising enabled 21"] -pub type AREN21_R = crate::BitReader; +pub type AREN21_R = crate::BitReader; #[doc = "Field `AREN21` writer - Async rising enabled 21"] -pub type AREN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN22` reader - Async rising enabled 22"] -pub type AREN22_R = crate::BitReader; +pub type AREN22_R = crate::BitReader; #[doc = "Field `AREN22` writer - Async rising enabled 22"] -pub type AREN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN23` reader - Async rising enabled 23"] -pub type AREN23_R = crate::BitReader; +pub type AREN23_R = crate::BitReader; #[doc = "Field `AREN23` writer - Async rising enabled 23"] -pub type AREN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN24` reader - Async rising enabled 24"] -pub type AREN24_R = crate::BitReader; +pub type AREN24_R = crate::BitReader; #[doc = "Field `AREN24` writer - Async rising enabled 24"] -pub type AREN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN25` reader - Async rising enabled 25"] -pub type AREN25_R = crate::BitReader; +pub type AREN25_R = crate::BitReader; #[doc = "Field `AREN25` writer - Async rising enabled 25"] -pub type AREN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN26` reader - Async rising enabled 26"] -pub type AREN26_R = crate::BitReader; +pub type AREN26_R = crate::BitReader; #[doc = "Field `AREN26` writer - Async rising enabled 26"] -pub type AREN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN27` reader - Async rising enabled 27"] -pub type AREN27_R = crate::BitReader; +pub type AREN27_R = crate::BitReader; #[doc = "Field `AREN27` writer - Async rising enabled 27"] -pub type AREN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN28` reader - Async rising enabled 28"] -pub type AREN28_R = crate::BitReader; +pub type AREN28_R = crate::BitReader; #[doc = "Field `AREN28` writer - Async rising enabled 28"] -pub type AREN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN29` reader - Async rising enabled 29"] -pub type AREN29_R = crate::BitReader; +pub type AREN29_R = crate::BitReader; #[doc = "Field `AREN29` writer - Async rising enabled 29"] -pub type AREN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN30` reader - Async rising enabled 30"] -pub type AREN30_R = crate::BitReader; +pub type AREN30_R = crate::BitReader; #[doc = "Field `AREN30` writer - Async rising enabled 30"] -pub type AREN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN31` reader - Async rising enabled 31"] -pub type AREN31_R = crate::BitReader; +pub type AREN31_R = crate::BitReader; #[doc = "Field `AREN31` writer - Async rising enabled 31"] -pub type AREN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Async rising enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { AREN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPAREN0") + .field("aren0", &format_args!("{}", self.aren0().bit())) + .field("aren1", &format_args!("{}", self.aren1().bit())) + .field("aren2", &format_args!("{}", self.aren2().bit())) + .field("aren3", &format_args!("{}", self.aren3().bit())) + .field("aren4", &format_args!("{}", self.aren4().bit())) + .field("aren5", &format_args!("{}", self.aren5().bit())) + .field("aren6", &format_args!("{}", self.aren6().bit())) + .field("aren7", &format_args!("{}", self.aren7().bit())) + .field("aren8", &format_args!("{}", self.aren8().bit())) + .field("aren9", &format_args!("{}", self.aren9().bit())) + .field("aren10", &format_args!("{}", self.aren10().bit())) + .field("aren11", &format_args!("{}", self.aren11().bit())) + .field("aren12", &format_args!("{}", self.aren12().bit())) + .field("aren13", &format_args!("{}", self.aren13().bit())) + .field("aren14", &format_args!("{}", self.aren14().bit())) + .field("aren15", &format_args!("{}", self.aren15().bit())) + .field("aren16", &format_args!("{}", self.aren16().bit())) + .field("aren17", &format_args!("{}", self.aren17().bit())) + .field("aren18", &format_args!("{}", self.aren18().bit())) + .field("aren19", &format_args!("{}", self.aren19().bit())) + .field("aren20", &format_args!("{}", self.aren20().bit())) + .field("aren21", &format_args!("{}", self.aren21().bit())) + .field("aren22", &format_args!("{}", self.aren22().bit())) + .field("aren23", &format_args!("{}", self.aren23().bit())) + .field("aren24", &format_args!("{}", self.aren24().bit())) + .field("aren25", &format_args!("{}", self.aren25().bit())) + .field("aren26", &format_args!("{}", self.aren26().bit())) + .field("aren27", &format_args!("{}", self.aren27().bit())) + .field("aren28", &format_args!("{}", self.aren28().bit())) + .field("aren29", &format_args!("{}", self.aren29().bit())) + .field("aren30", &format_args!("{}", self.aren30().bit())) + .field("aren31", &format_args!("{}", self.aren31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Async rising enabled 0"] #[inline(always)] #[must_use] - pub fn aren0(&mut self) -> AREN0_W<0> { + pub fn aren0(&mut self) -> AREN0_W { AREN0_W::new(self) } #[doc = "Bit 1 - Async rising enabled 1"] #[inline(always)] #[must_use] - pub fn aren1(&mut self) -> AREN1_W<1> { + pub fn aren1(&mut self) -> AREN1_W { AREN1_W::new(self) } #[doc = "Bit 2 - Async rising enabled 2"] #[inline(always)] #[must_use] - pub fn aren2(&mut self) -> AREN2_W<2> { + pub fn aren2(&mut self) -> AREN2_W { AREN2_W::new(self) } #[doc = "Bit 3 - Async rising enabled 3"] #[inline(always)] #[must_use] - pub fn aren3(&mut self) -> AREN3_W<3> { + pub fn aren3(&mut self) -> AREN3_W { AREN3_W::new(self) } #[doc = "Bit 4 - Async rising enabled 4"] #[inline(always)] #[must_use] - pub fn aren4(&mut self) -> AREN4_W<4> { + pub fn aren4(&mut self) -> AREN4_W { AREN4_W::new(self) } #[doc = "Bit 5 - Async rising enabled 5"] #[inline(always)] #[must_use] - pub fn aren5(&mut self) -> AREN5_W<5> { + pub fn aren5(&mut self) -> AREN5_W { AREN5_W::new(self) } #[doc = "Bit 6 - Async rising enabled 6"] #[inline(always)] #[must_use] - pub fn aren6(&mut self) -> AREN6_W<6> { + pub fn aren6(&mut self) -> AREN6_W { AREN6_W::new(self) } #[doc = "Bit 7 - Async rising enabled 7"] #[inline(always)] #[must_use] - pub fn aren7(&mut self) -> AREN7_W<7> { + pub fn aren7(&mut self) -> AREN7_W { AREN7_W::new(self) } #[doc = "Bit 8 - Async rising enabled 8"] #[inline(always)] #[must_use] - pub fn aren8(&mut self) -> AREN8_W<8> { + pub fn aren8(&mut self) -> AREN8_W { AREN8_W::new(self) } #[doc = "Bit 9 - Async rising enabled 9"] #[inline(always)] #[must_use] - pub fn aren9(&mut self) -> AREN9_W<9> { + pub fn aren9(&mut self) -> AREN9_W { AREN9_W::new(self) } #[doc = "Bit 10 - Async rising enabled 10"] #[inline(always)] #[must_use] - pub fn aren10(&mut self) -> AREN10_W<10> { + pub fn aren10(&mut self) -> AREN10_W { AREN10_W::new(self) } #[doc = "Bit 11 - Async rising enabled 11"] #[inline(always)] #[must_use] - pub fn aren11(&mut self) -> AREN11_W<11> { + pub fn aren11(&mut self) -> AREN11_W { AREN11_W::new(self) } #[doc = "Bit 12 - Async rising enabled 12"] #[inline(always)] #[must_use] - pub fn aren12(&mut self) -> AREN12_W<12> { + pub fn aren12(&mut self) -> AREN12_W { AREN12_W::new(self) } #[doc = "Bit 13 - Async rising enabled 13"] #[inline(always)] #[must_use] - pub fn aren13(&mut self) -> AREN13_W<13> { + pub fn aren13(&mut self) -> AREN13_W { AREN13_W::new(self) } #[doc = "Bit 14 - Async rising enabled 14"] #[inline(always)] #[must_use] - pub fn aren14(&mut self) -> AREN14_W<14> { + pub fn aren14(&mut self) -> AREN14_W { AREN14_W::new(self) } #[doc = "Bit 15 - Async rising enabled 15"] #[inline(always)] #[must_use] - pub fn aren15(&mut self) -> AREN15_W<15> { + pub fn aren15(&mut self) -> AREN15_W { AREN15_W::new(self) } #[doc = "Bit 16 - Async rising enabled 16"] #[inline(always)] #[must_use] - pub fn aren16(&mut self) -> AREN16_W<16> { + pub fn aren16(&mut self) -> AREN16_W { AREN16_W::new(self) } #[doc = "Bit 17 - Async rising enabled 17"] #[inline(always)] #[must_use] - pub fn aren17(&mut self) -> AREN17_W<17> { + pub fn aren17(&mut self) -> AREN17_W { AREN17_W::new(self) } #[doc = "Bit 18 - Async rising enabled 18"] #[inline(always)] #[must_use] - pub fn aren18(&mut self) -> AREN18_W<18> { + pub fn aren18(&mut self) -> AREN18_W { AREN18_W::new(self) } #[doc = "Bit 19 - Async rising enabled 19"] #[inline(always)] #[must_use] - pub fn aren19(&mut self) -> AREN19_W<19> { + pub fn aren19(&mut self) -> AREN19_W { AREN19_W::new(self) } #[doc = "Bit 20 - Async rising enabled 20"] #[inline(always)] #[must_use] - pub fn aren20(&mut self) -> AREN20_W<20> { + pub fn aren20(&mut self) -> AREN20_W { AREN20_W::new(self) } #[doc = "Bit 21 - Async rising enabled 21"] #[inline(always)] #[must_use] - pub fn aren21(&mut self) -> AREN21_W<21> { + pub fn aren21(&mut self) -> AREN21_W { AREN21_W::new(self) } #[doc = "Bit 22 - Async rising enabled 22"] #[inline(always)] #[must_use] - pub fn aren22(&mut self) -> AREN22_W<22> { + pub fn aren22(&mut self) -> AREN22_W { AREN22_W::new(self) } #[doc = "Bit 23 - Async rising enabled 23"] #[inline(always)] #[must_use] - pub fn aren23(&mut self) -> AREN23_W<23> { + pub fn aren23(&mut self) -> AREN23_W { AREN23_W::new(self) } #[doc = "Bit 24 - Async rising enabled 24"] #[inline(always)] #[must_use] - pub fn aren24(&mut self) -> AREN24_W<24> { + pub fn aren24(&mut self) -> AREN24_W { AREN24_W::new(self) } #[doc = "Bit 25 - Async rising enabled 25"] #[inline(always)] #[must_use] - pub fn aren25(&mut self) -> AREN25_W<25> { + pub fn aren25(&mut self) -> AREN25_W { AREN25_W::new(self) } #[doc = "Bit 26 - Async rising enabled 26"] #[inline(always)] #[must_use] - pub fn aren26(&mut self) -> AREN26_W<26> { + pub fn aren26(&mut self) -> AREN26_W { AREN26_W::new(self) } #[doc = "Bit 27 - Async rising enabled 27"] #[inline(always)] #[must_use] - pub fn aren27(&mut self) -> AREN27_W<27> { + pub fn aren27(&mut self) -> AREN27_W { AREN27_W::new(self) } #[doc = "Bit 28 - Async rising enabled 28"] #[inline(always)] #[must_use] - pub fn aren28(&mut self) -> AREN28_W<28> { + pub fn aren28(&mut self) -> AREN28_W { AREN28_W::new(self) } #[doc = "Bit 29 - Async rising enabled 29"] #[inline(always)] #[must_use] - pub fn aren29(&mut self) -> AREN29_W<29> { + pub fn aren29(&mut self) -> AREN29_W { AREN29_W::new(self) } #[doc = "Bit 30 - Async rising enabled 30"] #[inline(always)] #[must_use] - pub fn aren30(&mut self) -> AREN30_W<30> { + pub fn aren30(&mut self) -> AREN30_W { AREN30_W::new(self) } #[doc = "Bit 31 - Async rising enabled 31"] #[inline(always)] #[must_use] - pub fn aren31(&mut self) -> AREN31_W<31> { + pub fn aren31(&mut self) -> AREN31_W { AREN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Async. Rising Edge Detect 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gparen0](index.html) module"] +#[doc = "GPIO Pin Async. Rising Edge Detect 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gparen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gparen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPAREN0_SPEC; impl crate::RegisterSpec for GPAREN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gparen0::R](R) reader structure"] -impl crate::Readable for GPAREN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gparen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gparen0::R`](R) reader structure"] +impl crate::Readable for GPAREN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gparen0::W`](W) writer structure"] impl crate::Writable for GPAREN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gparen1.rs b/crates/bcm2835-lpa/src/gpio/gparen1.rs index 158f1ef..f4a64ad 100644 --- a/crates/bcm2835-lpa/src/gpio/gparen1.rs +++ b/crates/bcm2835-lpa/src/gpio/gparen1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPAREN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPAREN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AREN32` reader - Async rising enabled 32"] -pub type AREN32_R = crate::BitReader; +pub type AREN32_R = crate::BitReader; #[doc = "Field `AREN32` writer - Async rising enabled 32"] -pub type AREN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN33` reader - Async rising enabled 33"] -pub type AREN33_R = crate::BitReader; +pub type AREN33_R = crate::BitReader; #[doc = "Field `AREN33` writer - Async rising enabled 33"] -pub type AREN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN34` reader - Async rising enabled 34"] -pub type AREN34_R = crate::BitReader; +pub type AREN34_R = crate::BitReader; #[doc = "Field `AREN34` writer - Async rising enabled 34"] -pub type AREN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN35` reader - Async rising enabled 35"] -pub type AREN35_R = crate::BitReader; +pub type AREN35_R = crate::BitReader; #[doc = "Field `AREN35` writer - Async rising enabled 35"] -pub type AREN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN36` reader - Async rising enabled 36"] -pub type AREN36_R = crate::BitReader; +pub type AREN36_R = crate::BitReader; #[doc = "Field `AREN36` writer - Async rising enabled 36"] -pub type AREN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN37` reader - Async rising enabled 37"] -pub type AREN37_R = crate::BitReader; +pub type AREN37_R = crate::BitReader; #[doc = "Field `AREN37` writer - Async rising enabled 37"] -pub type AREN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN38` reader - Async rising enabled 38"] -pub type AREN38_R = crate::BitReader; +pub type AREN38_R = crate::BitReader; #[doc = "Field `AREN38` writer - Async rising enabled 38"] -pub type AREN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN39` reader - Async rising enabled 39"] -pub type AREN39_R = crate::BitReader; +pub type AREN39_R = crate::BitReader; #[doc = "Field `AREN39` writer - Async rising enabled 39"] -pub type AREN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN40` reader - Async rising enabled 40"] -pub type AREN40_R = crate::BitReader; +pub type AREN40_R = crate::BitReader; #[doc = "Field `AREN40` writer - Async rising enabled 40"] -pub type AREN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN41` reader - Async rising enabled 41"] -pub type AREN41_R = crate::BitReader; +pub type AREN41_R = crate::BitReader; #[doc = "Field `AREN41` writer - Async rising enabled 41"] -pub type AREN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN42` reader - Async rising enabled 42"] -pub type AREN42_R = crate::BitReader; +pub type AREN42_R = crate::BitReader; #[doc = "Field `AREN42` writer - Async rising enabled 42"] -pub type AREN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN43` reader - Async rising enabled 43"] -pub type AREN43_R = crate::BitReader; +pub type AREN43_R = crate::BitReader; #[doc = "Field `AREN43` writer - Async rising enabled 43"] -pub type AREN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN44` reader - Async rising enabled 44"] -pub type AREN44_R = crate::BitReader; +pub type AREN44_R = crate::BitReader; #[doc = "Field `AREN44` writer - Async rising enabled 44"] -pub type AREN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN45` reader - Async rising enabled 45"] -pub type AREN45_R = crate::BitReader; +pub type AREN45_R = crate::BitReader; #[doc = "Field `AREN45` writer - Async rising enabled 45"] -pub type AREN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN46` reader - Async rising enabled 46"] -pub type AREN46_R = crate::BitReader; +pub type AREN46_R = crate::BitReader; #[doc = "Field `AREN46` writer - Async rising enabled 46"] -pub type AREN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN47` reader - Async rising enabled 47"] -pub type AREN47_R = crate::BitReader; +pub type AREN47_R = crate::BitReader; #[doc = "Field `AREN47` writer - Async rising enabled 47"] -pub type AREN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN48` reader - Async rising enabled 48"] -pub type AREN48_R = crate::BitReader; +pub type AREN48_R = crate::BitReader; #[doc = "Field `AREN48` writer - Async rising enabled 48"] -pub type AREN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN49` reader - Async rising enabled 49"] -pub type AREN49_R = crate::BitReader; +pub type AREN49_R = crate::BitReader; #[doc = "Field `AREN49` writer - Async rising enabled 49"] -pub type AREN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN50` reader - Async rising enabled 50"] -pub type AREN50_R = crate::BitReader; +pub type AREN50_R = crate::BitReader; #[doc = "Field `AREN50` writer - Async rising enabled 50"] -pub type AREN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN51` reader - Async rising enabled 51"] -pub type AREN51_R = crate::BitReader; +pub type AREN51_R = crate::BitReader; #[doc = "Field `AREN51` writer - Async rising enabled 51"] -pub type AREN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN52` reader - Async rising enabled 52"] -pub type AREN52_R = crate::BitReader; +pub type AREN52_R = crate::BitReader; #[doc = "Field `AREN52` writer - Async rising enabled 52"] -pub type AREN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN53` reader - Async rising enabled 53"] -pub type AREN53_R = crate::BitReader; +pub type AREN53_R = crate::BitReader; #[doc = "Field `AREN53` writer - Async rising enabled 53"] -pub type AREN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Async rising enabled 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { AREN53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPAREN1") + .field("aren32", &format_args!("{}", self.aren32().bit())) + .field("aren33", &format_args!("{}", self.aren33().bit())) + .field("aren34", &format_args!("{}", self.aren34().bit())) + .field("aren35", &format_args!("{}", self.aren35().bit())) + .field("aren36", &format_args!("{}", self.aren36().bit())) + .field("aren37", &format_args!("{}", self.aren37().bit())) + .field("aren38", &format_args!("{}", self.aren38().bit())) + .field("aren39", &format_args!("{}", self.aren39().bit())) + .field("aren40", &format_args!("{}", self.aren40().bit())) + .field("aren41", &format_args!("{}", self.aren41().bit())) + .field("aren42", &format_args!("{}", self.aren42().bit())) + .field("aren43", &format_args!("{}", self.aren43().bit())) + .field("aren44", &format_args!("{}", self.aren44().bit())) + .field("aren45", &format_args!("{}", self.aren45().bit())) + .field("aren46", &format_args!("{}", self.aren46().bit())) + .field("aren47", &format_args!("{}", self.aren47().bit())) + .field("aren48", &format_args!("{}", self.aren48().bit())) + .field("aren49", &format_args!("{}", self.aren49().bit())) + .field("aren50", &format_args!("{}", self.aren50().bit())) + .field("aren51", &format_args!("{}", self.aren51().bit())) + .field("aren52", &format_args!("{}", self.aren52().bit())) + .field("aren53", &format_args!("{}", self.aren53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Async rising enabled 32"] #[inline(always)] #[must_use] - pub fn aren32(&mut self) -> AREN32_W<0> { + pub fn aren32(&mut self) -> AREN32_W { AREN32_W::new(self) } #[doc = "Bit 1 - Async rising enabled 33"] #[inline(always)] #[must_use] - pub fn aren33(&mut self) -> AREN33_W<1> { + pub fn aren33(&mut self) -> AREN33_W { AREN33_W::new(self) } #[doc = "Bit 2 - Async rising enabled 34"] #[inline(always)] #[must_use] - pub fn aren34(&mut self) -> AREN34_W<2> { + pub fn aren34(&mut self) -> AREN34_W { AREN34_W::new(self) } #[doc = "Bit 3 - Async rising enabled 35"] #[inline(always)] #[must_use] - pub fn aren35(&mut self) -> AREN35_W<3> { + pub fn aren35(&mut self) -> AREN35_W { AREN35_W::new(self) } #[doc = "Bit 4 - Async rising enabled 36"] #[inline(always)] #[must_use] - pub fn aren36(&mut self) -> AREN36_W<4> { + pub fn aren36(&mut self) -> AREN36_W { AREN36_W::new(self) } #[doc = "Bit 5 - Async rising enabled 37"] #[inline(always)] #[must_use] - pub fn aren37(&mut self) -> AREN37_W<5> { + pub fn aren37(&mut self) -> AREN37_W { AREN37_W::new(self) } #[doc = "Bit 6 - Async rising enabled 38"] #[inline(always)] #[must_use] - pub fn aren38(&mut self) -> AREN38_W<6> { + pub fn aren38(&mut self) -> AREN38_W { AREN38_W::new(self) } #[doc = "Bit 7 - Async rising enabled 39"] #[inline(always)] #[must_use] - pub fn aren39(&mut self) -> AREN39_W<7> { + pub fn aren39(&mut self) -> AREN39_W { AREN39_W::new(self) } #[doc = "Bit 8 - Async rising enabled 40"] #[inline(always)] #[must_use] - pub fn aren40(&mut self) -> AREN40_W<8> { + pub fn aren40(&mut self) -> AREN40_W { AREN40_W::new(self) } #[doc = "Bit 9 - Async rising enabled 41"] #[inline(always)] #[must_use] - pub fn aren41(&mut self) -> AREN41_W<9> { + pub fn aren41(&mut self) -> AREN41_W { AREN41_W::new(self) } #[doc = "Bit 10 - Async rising enabled 42"] #[inline(always)] #[must_use] - pub fn aren42(&mut self) -> AREN42_W<10> { + pub fn aren42(&mut self) -> AREN42_W { AREN42_W::new(self) } #[doc = "Bit 11 - Async rising enabled 43"] #[inline(always)] #[must_use] - pub fn aren43(&mut self) -> AREN43_W<11> { + pub fn aren43(&mut self) -> AREN43_W { AREN43_W::new(self) } #[doc = "Bit 12 - Async rising enabled 44"] #[inline(always)] #[must_use] - pub fn aren44(&mut self) -> AREN44_W<12> { + pub fn aren44(&mut self) -> AREN44_W { AREN44_W::new(self) } #[doc = "Bit 13 - Async rising enabled 45"] #[inline(always)] #[must_use] - pub fn aren45(&mut self) -> AREN45_W<13> { + pub fn aren45(&mut self) -> AREN45_W { AREN45_W::new(self) } #[doc = "Bit 14 - Async rising enabled 46"] #[inline(always)] #[must_use] - pub fn aren46(&mut self) -> AREN46_W<14> { + pub fn aren46(&mut self) -> AREN46_W { AREN46_W::new(self) } #[doc = "Bit 15 - Async rising enabled 47"] #[inline(always)] #[must_use] - pub fn aren47(&mut self) -> AREN47_W<15> { + pub fn aren47(&mut self) -> AREN47_W { AREN47_W::new(self) } #[doc = "Bit 16 - Async rising enabled 48"] #[inline(always)] #[must_use] - pub fn aren48(&mut self) -> AREN48_W<16> { + pub fn aren48(&mut self) -> AREN48_W { AREN48_W::new(self) } #[doc = "Bit 17 - Async rising enabled 49"] #[inline(always)] #[must_use] - pub fn aren49(&mut self) -> AREN49_W<17> { + pub fn aren49(&mut self) -> AREN49_W { AREN49_W::new(self) } #[doc = "Bit 18 - Async rising enabled 50"] #[inline(always)] #[must_use] - pub fn aren50(&mut self) -> AREN50_W<18> { + pub fn aren50(&mut self) -> AREN50_W { AREN50_W::new(self) } #[doc = "Bit 19 - Async rising enabled 51"] #[inline(always)] #[must_use] - pub fn aren51(&mut self) -> AREN51_W<19> { + pub fn aren51(&mut self) -> AREN51_W { AREN51_W::new(self) } #[doc = "Bit 20 - Async rising enabled 52"] #[inline(always)] #[must_use] - pub fn aren52(&mut self) -> AREN52_W<20> { + pub fn aren52(&mut self) -> AREN52_W { AREN52_W::new(self) } #[doc = "Bit 21 - Async rising enabled 53"] #[inline(always)] #[must_use] - pub fn aren53(&mut self) -> AREN53_W<21> { + pub fn aren53(&mut self) -> AREN53_W { AREN53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Async. Rising Edge Detect 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gparen1](index.html) module"] +#[doc = "GPIO Pin Async. Rising Edge Detect 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gparen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gparen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPAREN1_SPEC; impl crate::RegisterSpec for GPAREN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gparen1::R](R) reader structure"] -impl crate::Readable for GPAREN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gparen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gparen1::R`](R) reader structure"] +impl crate::Readable for GPAREN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gparen1::W`](W) writer structure"] impl crate::Writable for GPAREN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpclr0.rs b/crates/bcm2835-lpa/src/gpio/gpclr0.rs index 1a6b2cd..210af7f 100644 --- a/crates/bcm2835-lpa/src/gpio/gpclr0.rs +++ b/crates/bcm2835-lpa/src/gpio/gpclr0.rs @@ -1,296 +1,285 @@ #[doc = "Register `GPCLR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLR0` writer - Clear 0"] -pub type CLR0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR1` writer - Clear 1"] -pub type CLR1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR2` writer - Clear 2"] -pub type CLR2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR3` writer - Clear 3"] -pub type CLR3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR4` writer - Clear 4"] -pub type CLR4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR5` writer - Clear 5"] -pub type CLR5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR6` writer - Clear 6"] -pub type CLR6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR7` writer - Clear 7"] -pub type CLR7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR8` writer - Clear 8"] -pub type CLR8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR9` writer - Clear 9"] -pub type CLR9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR9_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR10` writer - Clear 10"] -pub type CLR10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR11` writer - Clear 11"] -pub type CLR11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR12` writer - Clear 12"] -pub type CLR12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR13` writer - Clear 13"] -pub type CLR13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR14` writer - Clear 14"] -pub type CLR14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR15` writer - Clear 15"] -pub type CLR15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR16` writer - Clear 16"] -pub type CLR16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR16_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR17` writer - Clear 17"] -pub type CLR17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR17_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR18` writer - Clear 18"] -pub type CLR18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR18_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR19` writer - Clear 19"] -pub type CLR19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR19_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR20` writer - Clear 20"] -pub type CLR20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR20_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR21` writer - Clear 21"] -pub type CLR21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR21_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR22` writer - Clear 22"] -pub type CLR22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR22_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR23` writer - Clear 23"] -pub type CLR23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR23_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR24` writer - Clear 24"] -pub type CLR24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR24_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR25` writer - Clear 25"] -pub type CLR25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR25_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR26` writer - Clear 26"] -pub type CLR26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR26_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR27` writer - Clear 27"] -pub type CLR27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR27_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR28` writer - Clear 28"] -pub type CLR28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR28_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR29` writer - Clear 29"] -pub type CLR29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR29_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR30` writer - Clear 30"] -pub type CLR30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR30_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR31` writer - Clear 31"] -pub type CLR31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR31_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - Clear 0"] #[inline(always)] #[must_use] - pub fn clr0(&mut self) -> CLR0_W<0> { + pub fn clr0(&mut self) -> CLR0_W { CLR0_W::new(self) } #[doc = "Bit 1 - Clear 1"] #[inline(always)] #[must_use] - pub fn clr1(&mut self) -> CLR1_W<1> { + pub fn clr1(&mut self) -> CLR1_W { CLR1_W::new(self) } #[doc = "Bit 2 - Clear 2"] #[inline(always)] #[must_use] - pub fn clr2(&mut self) -> CLR2_W<2> { + pub fn clr2(&mut self) -> CLR2_W { CLR2_W::new(self) } #[doc = "Bit 3 - Clear 3"] #[inline(always)] #[must_use] - pub fn clr3(&mut self) -> CLR3_W<3> { + pub fn clr3(&mut self) -> CLR3_W { CLR3_W::new(self) } #[doc = "Bit 4 - Clear 4"] #[inline(always)] #[must_use] - pub fn clr4(&mut self) -> CLR4_W<4> { + pub fn clr4(&mut self) -> CLR4_W { CLR4_W::new(self) } #[doc = "Bit 5 - Clear 5"] #[inline(always)] #[must_use] - pub fn clr5(&mut self) -> CLR5_W<5> { + pub fn clr5(&mut self) -> CLR5_W { CLR5_W::new(self) } #[doc = "Bit 6 - Clear 6"] #[inline(always)] #[must_use] - pub fn clr6(&mut self) -> CLR6_W<6> { + pub fn clr6(&mut self) -> CLR6_W { CLR6_W::new(self) } #[doc = "Bit 7 - Clear 7"] #[inline(always)] #[must_use] - pub fn clr7(&mut self) -> CLR7_W<7> { + pub fn clr7(&mut self) -> CLR7_W { CLR7_W::new(self) } #[doc = "Bit 8 - Clear 8"] #[inline(always)] #[must_use] - pub fn clr8(&mut self) -> CLR8_W<8> { + pub fn clr8(&mut self) -> CLR8_W { CLR8_W::new(self) } #[doc = "Bit 9 - Clear 9"] #[inline(always)] #[must_use] - pub fn clr9(&mut self) -> CLR9_W<9> { + pub fn clr9(&mut self) -> CLR9_W { CLR9_W::new(self) } #[doc = "Bit 10 - Clear 10"] #[inline(always)] #[must_use] - pub fn clr10(&mut self) -> CLR10_W<10> { + pub fn clr10(&mut self) -> CLR10_W { CLR10_W::new(self) } #[doc = "Bit 11 - Clear 11"] #[inline(always)] #[must_use] - pub fn clr11(&mut self) -> CLR11_W<11> { + pub fn clr11(&mut self) -> CLR11_W { CLR11_W::new(self) } #[doc = "Bit 12 - Clear 12"] #[inline(always)] #[must_use] - pub fn clr12(&mut self) -> CLR12_W<12> { + pub fn clr12(&mut self) -> CLR12_W { CLR12_W::new(self) } #[doc = "Bit 13 - Clear 13"] #[inline(always)] #[must_use] - pub fn clr13(&mut self) -> CLR13_W<13> { + pub fn clr13(&mut self) -> CLR13_W { CLR13_W::new(self) } #[doc = "Bit 14 - Clear 14"] #[inline(always)] #[must_use] - pub fn clr14(&mut self) -> CLR14_W<14> { + pub fn clr14(&mut self) -> CLR14_W { CLR14_W::new(self) } #[doc = "Bit 15 - Clear 15"] #[inline(always)] #[must_use] - pub fn clr15(&mut self) -> CLR15_W<15> { + pub fn clr15(&mut self) -> CLR15_W { CLR15_W::new(self) } #[doc = "Bit 16 - Clear 16"] #[inline(always)] #[must_use] - pub fn clr16(&mut self) -> CLR16_W<16> { + pub fn clr16(&mut self) -> CLR16_W { CLR16_W::new(self) } #[doc = "Bit 17 - Clear 17"] #[inline(always)] #[must_use] - pub fn clr17(&mut self) -> CLR17_W<17> { + pub fn clr17(&mut self) -> CLR17_W { CLR17_W::new(self) } #[doc = "Bit 18 - Clear 18"] #[inline(always)] #[must_use] - pub fn clr18(&mut self) -> CLR18_W<18> { + pub fn clr18(&mut self) -> CLR18_W { CLR18_W::new(self) } #[doc = "Bit 19 - Clear 19"] #[inline(always)] #[must_use] - pub fn clr19(&mut self) -> CLR19_W<19> { + pub fn clr19(&mut self) -> CLR19_W { CLR19_W::new(self) } #[doc = "Bit 20 - Clear 20"] #[inline(always)] #[must_use] - pub fn clr20(&mut self) -> CLR20_W<20> { + pub fn clr20(&mut self) -> CLR20_W { CLR20_W::new(self) } #[doc = "Bit 21 - Clear 21"] #[inline(always)] #[must_use] - pub fn clr21(&mut self) -> CLR21_W<21> { + pub fn clr21(&mut self) -> CLR21_W { CLR21_W::new(self) } #[doc = "Bit 22 - Clear 22"] #[inline(always)] #[must_use] - pub fn clr22(&mut self) -> CLR22_W<22> { + pub fn clr22(&mut self) -> CLR22_W { CLR22_W::new(self) } #[doc = "Bit 23 - Clear 23"] #[inline(always)] #[must_use] - pub fn clr23(&mut self) -> CLR23_W<23> { + pub fn clr23(&mut self) -> CLR23_W { CLR23_W::new(self) } #[doc = "Bit 24 - Clear 24"] #[inline(always)] #[must_use] - pub fn clr24(&mut self) -> CLR24_W<24> { + pub fn clr24(&mut self) -> CLR24_W { CLR24_W::new(self) } #[doc = "Bit 25 - Clear 25"] #[inline(always)] #[must_use] - pub fn clr25(&mut self) -> CLR25_W<25> { + pub fn clr25(&mut self) -> CLR25_W { CLR25_W::new(self) } #[doc = "Bit 26 - Clear 26"] #[inline(always)] #[must_use] - pub fn clr26(&mut self) -> CLR26_W<26> { + pub fn clr26(&mut self) -> CLR26_W { CLR26_W::new(self) } #[doc = "Bit 27 - Clear 27"] #[inline(always)] #[must_use] - pub fn clr27(&mut self) -> CLR27_W<27> { + pub fn clr27(&mut self) -> CLR27_W { CLR27_W::new(self) } #[doc = "Bit 28 - Clear 28"] #[inline(always)] #[must_use] - pub fn clr28(&mut self) -> CLR28_W<28> { + pub fn clr28(&mut self) -> CLR28_W { CLR28_W::new(self) } #[doc = "Bit 29 - Clear 29"] #[inline(always)] #[must_use] - pub fn clr29(&mut self) -> CLR29_W<29> { + pub fn clr29(&mut self) -> CLR29_W { CLR29_W::new(self) } #[doc = "Bit 30 - Clear 30"] #[inline(always)] #[must_use] - pub fn clr30(&mut self) -> CLR30_W<30> { + pub fn clr30(&mut self) -> CLR30_W { CLR30_W::new(self) } #[doc = "Bit 31 - Clear 31"] #[inline(always)] #[must_use] - pub fn clr31(&mut self) -> CLR31_W<31> { + pub fn clr31(&mut self) -> CLR31_W { CLR31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Output Clear 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpclr0](index.html) module"] +#[doc = "GPIO Pin Output Clear 0\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpclr0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPCLR0_SPEC; impl crate::RegisterSpec for GPCLR0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpclr0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpclr0::W`](W) writer structure"] impl crate::Writable for GPCLR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2835-lpa/src/gpio/gpclr1.rs b/crates/bcm2835-lpa/src/gpio/gpclr1.rs index 84ce196..21e8c12 100644 --- a/crates/bcm2835-lpa/src/gpio/gpclr1.rs +++ b/crates/bcm2835-lpa/src/gpio/gpclr1.rs @@ -1,216 +1,205 @@ #[doc = "Register `GPCLR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLR32` writer - Clear 32"] -pub type CLR32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR32_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR33` writer - Clear 33"] -pub type CLR33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR33_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR34` writer - Clear 34"] -pub type CLR34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR34_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR35` writer - Clear 35"] -pub type CLR35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR35_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR36` writer - Clear 36"] -pub type CLR36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR36_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR37` writer - Clear 37"] -pub type CLR37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR37_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR38` writer - Clear 38"] -pub type CLR38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR38_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR39` writer - Clear 39"] -pub type CLR39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR39_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR40` writer - Clear 40"] -pub type CLR40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR40_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR41` writer - Clear 41"] -pub type CLR41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR41_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR42` writer - Clear 42"] -pub type CLR42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR42_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR43` writer - Clear 43"] -pub type CLR43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR43_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR44` writer - Clear 44"] -pub type CLR44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR44_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR45` writer - Clear 45"] -pub type CLR45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR45_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR46` writer - Clear 46"] -pub type CLR46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR46_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR47` writer - Clear 47"] -pub type CLR47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR47_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR48` writer - Clear 48"] -pub type CLR48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR48_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR49` writer - Clear 49"] -pub type CLR49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR49_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR50` writer - Clear 50"] -pub type CLR50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR50_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR51` writer - Clear 51"] -pub type CLR51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR51_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR52` writer - Clear 52"] -pub type CLR52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR52_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR53` writer - Clear 53"] -pub type CLR53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR53_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - Clear 32"] #[inline(always)] #[must_use] - pub fn clr32(&mut self) -> CLR32_W<0> { + pub fn clr32(&mut self) -> CLR32_W { CLR32_W::new(self) } #[doc = "Bit 1 - Clear 33"] #[inline(always)] #[must_use] - pub fn clr33(&mut self) -> CLR33_W<1> { + pub fn clr33(&mut self) -> CLR33_W { CLR33_W::new(self) } #[doc = "Bit 2 - Clear 34"] #[inline(always)] #[must_use] - pub fn clr34(&mut self) -> CLR34_W<2> { + pub fn clr34(&mut self) -> CLR34_W { CLR34_W::new(self) } #[doc = "Bit 3 - Clear 35"] #[inline(always)] #[must_use] - pub fn clr35(&mut self) -> CLR35_W<3> { + pub fn clr35(&mut self) -> CLR35_W { CLR35_W::new(self) } #[doc = "Bit 4 - Clear 36"] #[inline(always)] #[must_use] - pub fn clr36(&mut self) -> CLR36_W<4> { + pub fn clr36(&mut self) -> CLR36_W { CLR36_W::new(self) } #[doc = "Bit 5 - Clear 37"] #[inline(always)] #[must_use] - pub fn clr37(&mut self) -> CLR37_W<5> { + pub fn clr37(&mut self) -> CLR37_W { CLR37_W::new(self) } #[doc = "Bit 6 - Clear 38"] #[inline(always)] #[must_use] - pub fn clr38(&mut self) -> CLR38_W<6> { + pub fn clr38(&mut self) -> CLR38_W { CLR38_W::new(self) } #[doc = "Bit 7 - Clear 39"] #[inline(always)] #[must_use] - pub fn clr39(&mut self) -> CLR39_W<7> { + pub fn clr39(&mut self) -> CLR39_W { CLR39_W::new(self) } #[doc = "Bit 8 - Clear 40"] #[inline(always)] #[must_use] - pub fn clr40(&mut self) -> CLR40_W<8> { + pub fn clr40(&mut self) -> CLR40_W { CLR40_W::new(self) } #[doc = "Bit 9 - Clear 41"] #[inline(always)] #[must_use] - pub fn clr41(&mut self) -> CLR41_W<9> { + pub fn clr41(&mut self) -> CLR41_W { CLR41_W::new(self) } #[doc = "Bit 10 - Clear 42"] #[inline(always)] #[must_use] - pub fn clr42(&mut self) -> CLR42_W<10> { + pub fn clr42(&mut self) -> CLR42_W { CLR42_W::new(self) } #[doc = "Bit 11 - Clear 43"] #[inline(always)] #[must_use] - pub fn clr43(&mut self) -> CLR43_W<11> { + pub fn clr43(&mut self) -> CLR43_W { CLR43_W::new(self) } #[doc = "Bit 12 - Clear 44"] #[inline(always)] #[must_use] - pub fn clr44(&mut self) -> CLR44_W<12> { + pub fn clr44(&mut self) -> CLR44_W { CLR44_W::new(self) } #[doc = "Bit 13 - Clear 45"] #[inline(always)] #[must_use] - pub fn clr45(&mut self) -> CLR45_W<13> { + pub fn clr45(&mut self) -> CLR45_W { CLR45_W::new(self) } #[doc = "Bit 14 - Clear 46"] #[inline(always)] #[must_use] - pub fn clr46(&mut self) -> CLR46_W<14> { + pub fn clr46(&mut self) -> CLR46_W { CLR46_W::new(self) } #[doc = "Bit 15 - Clear 47"] #[inline(always)] #[must_use] - pub fn clr47(&mut self) -> CLR47_W<15> { + pub fn clr47(&mut self) -> CLR47_W { CLR47_W::new(self) } #[doc = "Bit 16 - Clear 48"] #[inline(always)] #[must_use] - pub fn clr48(&mut self) -> CLR48_W<16> { + pub fn clr48(&mut self) -> CLR48_W { CLR48_W::new(self) } #[doc = "Bit 17 - Clear 49"] #[inline(always)] #[must_use] - pub fn clr49(&mut self) -> CLR49_W<17> { + pub fn clr49(&mut self) -> CLR49_W { CLR49_W::new(self) } #[doc = "Bit 18 - Clear 50"] #[inline(always)] #[must_use] - pub fn clr50(&mut self) -> CLR50_W<18> { + pub fn clr50(&mut self) -> CLR50_W { CLR50_W::new(self) } #[doc = "Bit 19 - Clear 51"] #[inline(always)] #[must_use] - pub fn clr51(&mut self) -> CLR51_W<19> { + pub fn clr51(&mut self) -> CLR51_W { CLR51_W::new(self) } #[doc = "Bit 20 - Clear 52"] #[inline(always)] #[must_use] - pub fn clr52(&mut self) -> CLR52_W<20> { + pub fn clr52(&mut self) -> CLR52_W { CLR52_W::new(self) } #[doc = "Bit 21 - Clear 53"] #[inline(always)] #[must_use] - pub fn clr53(&mut self) -> CLR53_W<21> { + pub fn clr53(&mut self) -> CLR53_W { CLR53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Output Clear 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpclr1](index.html) module"] +#[doc = "GPIO Pin Output Clear 1\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpclr1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPCLR1_SPEC; impl crate::RegisterSpec for GPCLR1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpclr1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpclr1::W`](W) writer structure"] impl crate::Writable for GPCLR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x003f_ffff; } diff --git a/crates/bcm2835-lpa/src/gpio/gpeds0.rs b/crates/bcm2835-lpa/src/gpio/gpeds0.rs index 7aadf5b..caa11e1 100644 --- a/crates/bcm2835-lpa/src/gpio/gpeds0.rs +++ b/crates/bcm2835-lpa/src/gpio/gpeds0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPEDS0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPEDS0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EDS0` reader - Event detected 0"] -pub type EDS0_R = crate::BitReader; +pub type EDS0_R = crate::BitReader; #[doc = "Field `EDS0` writer - Event detected 0"] -pub type EDS0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS1` reader - Event detected 1"] -pub type EDS1_R = crate::BitReader; +pub type EDS1_R = crate::BitReader; #[doc = "Field `EDS1` writer - Event detected 1"] -pub type EDS1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS2` reader - Event detected 2"] -pub type EDS2_R = crate::BitReader; +pub type EDS2_R = crate::BitReader; #[doc = "Field `EDS2` writer - Event detected 2"] -pub type EDS2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS3` reader - Event detected 3"] -pub type EDS3_R = crate::BitReader; +pub type EDS3_R = crate::BitReader; #[doc = "Field `EDS3` writer - Event detected 3"] -pub type EDS3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS4` reader - Event detected 4"] -pub type EDS4_R = crate::BitReader; +pub type EDS4_R = crate::BitReader; #[doc = "Field `EDS4` writer - Event detected 4"] -pub type EDS4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS5` reader - Event detected 5"] -pub type EDS5_R = crate::BitReader; +pub type EDS5_R = crate::BitReader; #[doc = "Field `EDS5` writer - Event detected 5"] -pub type EDS5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS6` reader - Event detected 6"] -pub type EDS6_R = crate::BitReader; +pub type EDS6_R = crate::BitReader; #[doc = "Field `EDS6` writer - Event detected 6"] -pub type EDS6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS7` reader - Event detected 7"] -pub type EDS7_R = crate::BitReader; +pub type EDS7_R = crate::BitReader; #[doc = "Field `EDS7` writer - Event detected 7"] -pub type EDS7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS8` reader - Event detected 8"] -pub type EDS8_R = crate::BitReader; +pub type EDS8_R = crate::BitReader; #[doc = "Field `EDS8` writer - Event detected 8"] -pub type EDS8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS9` reader - Event detected 9"] -pub type EDS9_R = crate::BitReader; +pub type EDS9_R = crate::BitReader; #[doc = "Field `EDS9` writer - Event detected 9"] -pub type EDS9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS9_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS10` reader - Event detected 10"] -pub type EDS10_R = crate::BitReader; +pub type EDS10_R = crate::BitReader; #[doc = "Field `EDS10` writer - Event detected 10"] -pub type EDS10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS11` reader - Event detected 11"] -pub type EDS11_R = crate::BitReader; +pub type EDS11_R = crate::BitReader; #[doc = "Field `EDS11` writer - Event detected 11"] -pub type EDS11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS12` reader - Event detected 12"] -pub type EDS12_R = crate::BitReader; +pub type EDS12_R = crate::BitReader; #[doc = "Field `EDS12` writer - Event detected 12"] -pub type EDS12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS13` reader - Event detected 13"] -pub type EDS13_R = crate::BitReader; +pub type EDS13_R = crate::BitReader; #[doc = "Field `EDS13` writer - Event detected 13"] -pub type EDS13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS14` reader - Event detected 14"] -pub type EDS14_R = crate::BitReader; +pub type EDS14_R = crate::BitReader; #[doc = "Field `EDS14` writer - Event detected 14"] -pub type EDS14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS15` reader - Event detected 15"] -pub type EDS15_R = crate::BitReader; +pub type EDS15_R = crate::BitReader; #[doc = "Field `EDS15` writer - Event detected 15"] -pub type EDS15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS16` reader - Event detected 16"] -pub type EDS16_R = crate::BitReader; +pub type EDS16_R = crate::BitReader; #[doc = "Field `EDS16` writer - Event detected 16"] -pub type EDS16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS16_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS17` reader - Event detected 17"] -pub type EDS17_R = crate::BitReader; +pub type EDS17_R = crate::BitReader; #[doc = "Field `EDS17` writer - Event detected 17"] -pub type EDS17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS17_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS18` reader - Event detected 18"] -pub type EDS18_R = crate::BitReader; +pub type EDS18_R = crate::BitReader; #[doc = "Field `EDS18` writer - Event detected 18"] -pub type EDS18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS18_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS19` reader - Event detected 19"] -pub type EDS19_R = crate::BitReader; +pub type EDS19_R = crate::BitReader; #[doc = "Field `EDS19` writer - Event detected 19"] -pub type EDS19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS19_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS20` reader - Event detected 20"] -pub type EDS20_R = crate::BitReader; +pub type EDS20_R = crate::BitReader; #[doc = "Field `EDS20` writer - Event detected 20"] -pub type EDS20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS20_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS21` reader - Event detected 21"] -pub type EDS21_R = crate::BitReader; +pub type EDS21_R = crate::BitReader; #[doc = "Field `EDS21` writer - Event detected 21"] -pub type EDS21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS21_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS22` reader - Event detected 22"] -pub type EDS22_R = crate::BitReader; +pub type EDS22_R = crate::BitReader; #[doc = "Field `EDS22` writer - Event detected 22"] -pub type EDS22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS22_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS23` reader - Event detected 23"] -pub type EDS23_R = crate::BitReader; +pub type EDS23_R = crate::BitReader; #[doc = "Field `EDS23` writer - Event detected 23"] -pub type EDS23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS23_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS24` reader - Event detected 24"] -pub type EDS24_R = crate::BitReader; +pub type EDS24_R = crate::BitReader; #[doc = "Field `EDS24` writer - Event detected 24"] -pub type EDS24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS24_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS25` reader - Event detected 25"] -pub type EDS25_R = crate::BitReader; +pub type EDS25_R = crate::BitReader; #[doc = "Field `EDS25` writer - Event detected 25"] -pub type EDS25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS25_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS26` reader - Event detected 26"] -pub type EDS26_R = crate::BitReader; +pub type EDS26_R = crate::BitReader; #[doc = "Field `EDS26` writer - Event detected 26"] -pub type EDS26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS26_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS27` reader - Event detected 27"] -pub type EDS27_R = crate::BitReader; +pub type EDS27_R = crate::BitReader; #[doc = "Field `EDS27` writer - Event detected 27"] -pub type EDS27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS27_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS28` reader - Event detected 28"] -pub type EDS28_R = crate::BitReader; +pub type EDS28_R = crate::BitReader; #[doc = "Field `EDS28` writer - Event detected 28"] -pub type EDS28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS28_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS29` reader - Event detected 29"] -pub type EDS29_R = crate::BitReader; +pub type EDS29_R = crate::BitReader; #[doc = "Field `EDS29` writer - Event detected 29"] -pub type EDS29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS29_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS30` reader - Event detected 30"] -pub type EDS30_R = crate::BitReader; +pub type EDS30_R = crate::BitReader; #[doc = "Field `EDS30` writer - Event detected 30"] -pub type EDS30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS30_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS31` reader - Event detected 31"] -pub type EDS31_R = crate::BitReader; +pub type EDS31_R = crate::BitReader; #[doc = "Field `EDS31` writer - Event detected 31"] -pub type EDS31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS31_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Event detected 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { EDS31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPEDS0") + .field("eds0", &format_args!("{}", self.eds0().bit())) + .field("eds1", &format_args!("{}", self.eds1().bit())) + .field("eds2", &format_args!("{}", self.eds2().bit())) + .field("eds3", &format_args!("{}", self.eds3().bit())) + .field("eds4", &format_args!("{}", self.eds4().bit())) + .field("eds5", &format_args!("{}", self.eds5().bit())) + .field("eds6", &format_args!("{}", self.eds6().bit())) + .field("eds7", &format_args!("{}", self.eds7().bit())) + .field("eds8", &format_args!("{}", self.eds8().bit())) + .field("eds9", &format_args!("{}", self.eds9().bit())) + .field("eds10", &format_args!("{}", self.eds10().bit())) + .field("eds11", &format_args!("{}", self.eds11().bit())) + .field("eds12", &format_args!("{}", self.eds12().bit())) + .field("eds13", &format_args!("{}", self.eds13().bit())) + .field("eds14", &format_args!("{}", self.eds14().bit())) + .field("eds15", &format_args!("{}", self.eds15().bit())) + .field("eds16", &format_args!("{}", self.eds16().bit())) + .field("eds17", &format_args!("{}", self.eds17().bit())) + .field("eds18", &format_args!("{}", self.eds18().bit())) + .field("eds19", &format_args!("{}", self.eds19().bit())) + .field("eds20", &format_args!("{}", self.eds20().bit())) + .field("eds21", &format_args!("{}", self.eds21().bit())) + .field("eds22", &format_args!("{}", self.eds22().bit())) + .field("eds23", &format_args!("{}", self.eds23().bit())) + .field("eds24", &format_args!("{}", self.eds24().bit())) + .field("eds25", &format_args!("{}", self.eds25().bit())) + .field("eds26", &format_args!("{}", self.eds26().bit())) + .field("eds27", &format_args!("{}", self.eds27().bit())) + .field("eds28", &format_args!("{}", self.eds28().bit())) + .field("eds29", &format_args!("{}", self.eds29().bit())) + .field("eds30", &format_args!("{}", self.eds30().bit())) + .field("eds31", &format_args!("{}", self.eds31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Event detected 0"] #[inline(always)] #[must_use] - pub fn eds0(&mut self) -> EDS0_W<0> { + pub fn eds0(&mut self) -> EDS0_W { EDS0_W::new(self) } #[doc = "Bit 1 - Event detected 1"] #[inline(always)] #[must_use] - pub fn eds1(&mut self) -> EDS1_W<1> { + pub fn eds1(&mut self) -> EDS1_W { EDS1_W::new(self) } #[doc = "Bit 2 - Event detected 2"] #[inline(always)] #[must_use] - pub fn eds2(&mut self) -> EDS2_W<2> { + pub fn eds2(&mut self) -> EDS2_W { EDS2_W::new(self) } #[doc = "Bit 3 - Event detected 3"] #[inline(always)] #[must_use] - pub fn eds3(&mut self) -> EDS3_W<3> { + pub fn eds3(&mut self) -> EDS3_W { EDS3_W::new(self) } #[doc = "Bit 4 - Event detected 4"] #[inline(always)] #[must_use] - pub fn eds4(&mut self) -> EDS4_W<4> { + pub fn eds4(&mut self) -> EDS4_W { EDS4_W::new(self) } #[doc = "Bit 5 - Event detected 5"] #[inline(always)] #[must_use] - pub fn eds5(&mut self) -> EDS5_W<5> { + pub fn eds5(&mut self) -> EDS5_W { EDS5_W::new(self) } #[doc = "Bit 6 - Event detected 6"] #[inline(always)] #[must_use] - pub fn eds6(&mut self) -> EDS6_W<6> { + pub fn eds6(&mut self) -> EDS6_W { EDS6_W::new(self) } #[doc = "Bit 7 - Event detected 7"] #[inline(always)] #[must_use] - pub fn eds7(&mut self) -> EDS7_W<7> { + pub fn eds7(&mut self) -> EDS7_W { EDS7_W::new(self) } #[doc = "Bit 8 - Event detected 8"] #[inline(always)] #[must_use] - pub fn eds8(&mut self) -> EDS8_W<8> { + pub fn eds8(&mut self) -> EDS8_W { EDS8_W::new(self) } #[doc = "Bit 9 - Event detected 9"] #[inline(always)] #[must_use] - pub fn eds9(&mut self) -> EDS9_W<9> { + pub fn eds9(&mut self) -> EDS9_W { EDS9_W::new(self) } #[doc = "Bit 10 - Event detected 10"] #[inline(always)] #[must_use] - pub fn eds10(&mut self) -> EDS10_W<10> { + pub fn eds10(&mut self) -> EDS10_W { EDS10_W::new(self) } #[doc = "Bit 11 - Event detected 11"] #[inline(always)] #[must_use] - pub fn eds11(&mut self) -> EDS11_W<11> { + pub fn eds11(&mut self) -> EDS11_W { EDS11_W::new(self) } #[doc = "Bit 12 - Event detected 12"] #[inline(always)] #[must_use] - pub fn eds12(&mut self) -> EDS12_W<12> { + pub fn eds12(&mut self) -> EDS12_W { EDS12_W::new(self) } #[doc = "Bit 13 - Event detected 13"] #[inline(always)] #[must_use] - pub fn eds13(&mut self) -> EDS13_W<13> { + pub fn eds13(&mut self) -> EDS13_W { EDS13_W::new(self) } #[doc = "Bit 14 - Event detected 14"] #[inline(always)] #[must_use] - pub fn eds14(&mut self) -> EDS14_W<14> { + pub fn eds14(&mut self) -> EDS14_W { EDS14_W::new(self) } #[doc = "Bit 15 - Event detected 15"] #[inline(always)] #[must_use] - pub fn eds15(&mut self) -> EDS15_W<15> { + pub fn eds15(&mut self) -> EDS15_W { EDS15_W::new(self) } #[doc = "Bit 16 - Event detected 16"] #[inline(always)] #[must_use] - pub fn eds16(&mut self) -> EDS16_W<16> { + pub fn eds16(&mut self) -> EDS16_W { EDS16_W::new(self) } #[doc = "Bit 17 - Event detected 17"] #[inline(always)] #[must_use] - pub fn eds17(&mut self) -> EDS17_W<17> { + pub fn eds17(&mut self) -> EDS17_W { EDS17_W::new(self) } #[doc = "Bit 18 - Event detected 18"] #[inline(always)] #[must_use] - pub fn eds18(&mut self) -> EDS18_W<18> { + pub fn eds18(&mut self) -> EDS18_W { EDS18_W::new(self) } #[doc = "Bit 19 - Event detected 19"] #[inline(always)] #[must_use] - pub fn eds19(&mut self) -> EDS19_W<19> { + pub fn eds19(&mut self) -> EDS19_W { EDS19_W::new(self) } #[doc = "Bit 20 - Event detected 20"] #[inline(always)] #[must_use] - pub fn eds20(&mut self) -> EDS20_W<20> { + pub fn eds20(&mut self) -> EDS20_W { EDS20_W::new(self) } #[doc = "Bit 21 - Event detected 21"] #[inline(always)] #[must_use] - pub fn eds21(&mut self) -> EDS21_W<21> { + pub fn eds21(&mut self) -> EDS21_W { EDS21_W::new(self) } #[doc = "Bit 22 - Event detected 22"] #[inline(always)] #[must_use] - pub fn eds22(&mut self) -> EDS22_W<22> { + pub fn eds22(&mut self) -> EDS22_W { EDS22_W::new(self) } #[doc = "Bit 23 - Event detected 23"] #[inline(always)] #[must_use] - pub fn eds23(&mut self) -> EDS23_W<23> { + pub fn eds23(&mut self) -> EDS23_W { EDS23_W::new(self) } #[doc = "Bit 24 - Event detected 24"] #[inline(always)] #[must_use] - pub fn eds24(&mut self) -> EDS24_W<24> { + pub fn eds24(&mut self) -> EDS24_W { EDS24_W::new(self) } #[doc = "Bit 25 - Event detected 25"] #[inline(always)] #[must_use] - pub fn eds25(&mut self) -> EDS25_W<25> { + pub fn eds25(&mut self) -> EDS25_W { EDS25_W::new(self) } #[doc = "Bit 26 - Event detected 26"] #[inline(always)] #[must_use] - pub fn eds26(&mut self) -> EDS26_W<26> { + pub fn eds26(&mut self) -> EDS26_W { EDS26_W::new(self) } #[doc = "Bit 27 - Event detected 27"] #[inline(always)] #[must_use] - pub fn eds27(&mut self) -> EDS27_W<27> { + pub fn eds27(&mut self) -> EDS27_W { EDS27_W::new(self) } #[doc = "Bit 28 - Event detected 28"] #[inline(always)] #[must_use] - pub fn eds28(&mut self) -> EDS28_W<28> { + pub fn eds28(&mut self) -> EDS28_W { EDS28_W::new(self) } #[doc = "Bit 29 - Event detected 29"] #[inline(always)] #[must_use] - pub fn eds29(&mut self) -> EDS29_W<29> { + pub fn eds29(&mut self) -> EDS29_W { EDS29_W::new(self) } #[doc = "Bit 30 - Event detected 30"] #[inline(always)] #[must_use] - pub fn eds30(&mut self) -> EDS30_W<30> { + pub fn eds30(&mut self) -> EDS30_W { EDS30_W::new(self) } #[doc = "Bit 31 - Event detected 31"] #[inline(always)] #[must_use] - pub fn eds31(&mut self) -> EDS31_W<31> { + pub fn eds31(&mut self) -> EDS31_W { EDS31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Event Detect Status 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpeds0](index.html) module"] +#[doc = "GPIO Pin Event Detect Status 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpeds0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpeds0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPEDS0_SPEC; impl crate::RegisterSpec for GPEDS0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpeds0::R](R) reader structure"] -impl crate::Readable for GPEDS0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpeds0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpeds0::R`](R) reader structure"] +impl crate::Readable for GPEDS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpeds0::W`](W) writer structure"] impl crate::Writable for GPEDS0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2835-lpa/src/gpio/gpeds1.rs b/crates/bcm2835-lpa/src/gpio/gpeds1.rs index bcef23a..ac728c0 100644 --- a/crates/bcm2835-lpa/src/gpio/gpeds1.rs +++ b/crates/bcm2835-lpa/src/gpio/gpeds1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPEDS1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPEDS1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EDS32` reader - Event detected 32"] -pub type EDS32_R = crate::BitReader; +pub type EDS32_R = crate::BitReader; #[doc = "Field `EDS32` writer - Event detected 32"] -pub type EDS32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS32_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS33` reader - Event detected 33"] -pub type EDS33_R = crate::BitReader; +pub type EDS33_R = crate::BitReader; #[doc = "Field `EDS33` writer - Event detected 33"] -pub type EDS33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS33_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS34` reader - Event detected 34"] -pub type EDS34_R = crate::BitReader; +pub type EDS34_R = crate::BitReader; #[doc = "Field `EDS34` writer - Event detected 34"] -pub type EDS34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS34_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS35` reader - Event detected 35"] -pub type EDS35_R = crate::BitReader; +pub type EDS35_R = crate::BitReader; #[doc = "Field `EDS35` writer - Event detected 35"] -pub type EDS35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS35_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS36` reader - Event detected 36"] -pub type EDS36_R = crate::BitReader; +pub type EDS36_R = crate::BitReader; #[doc = "Field `EDS36` writer - Event detected 36"] -pub type EDS36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS36_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS37` reader - Event detected 37"] -pub type EDS37_R = crate::BitReader; +pub type EDS37_R = crate::BitReader; #[doc = "Field `EDS37` writer - Event detected 37"] -pub type EDS37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS37_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS38` reader - Event detected 38"] -pub type EDS38_R = crate::BitReader; +pub type EDS38_R = crate::BitReader; #[doc = "Field `EDS38` writer - Event detected 38"] -pub type EDS38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS38_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS39` reader - Event detected 39"] -pub type EDS39_R = crate::BitReader; +pub type EDS39_R = crate::BitReader; #[doc = "Field `EDS39` writer - Event detected 39"] -pub type EDS39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS39_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS40` reader - Event detected 40"] -pub type EDS40_R = crate::BitReader; +pub type EDS40_R = crate::BitReader; #[doc = "Field `EDS40` writer - Event detected 40"] -pub type EDS40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS40_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS41` reader - Event detected 41"] -pub type EDS41_R = crate::BitReader; +pub type EDS41_R = crate::BitReader; #[doc = "Field `EDS41` writer - Event detected 41"] -pub type EDS41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS41_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS42` reader - Event detected 42"] -pub type EDS42_R = crate::BitReader; +pub type EDS42_R = crate::BitReader; #[doc = "Field `EDS42` writer - Event detected 42"] -pub type EDS42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS42_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS43` reader - Event detected 43"] -pub type EDS43_R = crate::BitReader; +pub type EDS43_R = crate::BitReader; #[doc = "Field `EDS43` writer - Event detected 43"] -pub type EDS43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS43_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS44` reader - Event detected 44"] -pub type EDS44_R = crate::BitReader; +pub type EDS44_R = crate::BitReader; #[doc = "Field `EDS44` writer - Event detected 44"] -pub type EDS44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS44_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS45` reader - Event detected 45"] -pub type EDS45_R = crate::BitReader; +pub type EDS45_R = crate::BitReader; #[doc = "Field `EDS45` writer - Event detected 45"] -pub type EDS45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS45_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS46` reader - Event detected 46"] -pub type EDS46_R = crate::BitReader; +pub type EDS46_R = crate::BitReader; #[doc = "Field `EDS46` writer - Event detected 46"] -pub type EDS46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS46_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS47` reader - Event detected 47"] -pub type EDS47_R = crate::BitReader; +pub type EDS47_R = crate::BitReader; #[doc = "Field `EDS47` writer - Event detected 47"] -pub type EDS47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS47_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS48` reader - Event detected 48"] -pub type EDS48_R = crate::BitReader; +pub type EDS48_R = crate::BitReader; #[doc = "Field `EDS48` writer - Event detected 48"] -pub type EDS48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS48_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS49` reader - Event detected 49"] -pub type EDS49_R = crate::BitReader; +pub type EDS49_R = crate::BitReader; #[doc = "Field `EDS49` writer - Event detected 49"] -pub type EDS49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS49_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS50` reader - Event detected 50"] -pub type EDS50_R = crate::BitReader; +pub type EDS50_R = crate::BitReader; #[doc = "Field `EDS50` writer - Event detected 50"] -pub type EDS50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS50_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS51` reader - Event detected 51"] -pub type EDS51_R = crate::BitReader; +pub type EDS51_R = crate::BitReader; #[doc = "Field `EDS51` writer - Event detected 51"] -pub type EDS51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS51_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS52` reader - Event detected 52"] -pub type EDS52_R = crate::BitReader; +pub type EDS52_R = crate::BitReader; #[doc = "Field `EDS52` writer - Event detected 52"] -pub type EDS52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS52_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS53` reader - Event detected 53"] -pub type EDS53_R = crate::BitReader; +pub type EDS53_R = crate::BitReader; #[doc = "Field `EDS53` writer - Event detected 53"] -pub type EDS53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS53_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Event detected 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { EDS53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPEDS1") + .field("eds32", &format_args!("{}", self.eds32().bit())) + .field("eds33", &format_args!("{}", self.eds33().bit())) + .field("eds34", &format_args!("{}", self.eds34().bit())) + .field("eds35", &format_args!("{}", self.eds35().bit())) + .field("eds36", &format_args!("{}", self.eds36().bit())) + .field("eds37", &format_args!("{}", self.eds37().bit())) + .field("eds38", &format_args!("{}", self.eds38().bit())) + .field("eds39", &format_args!("{}", self.eds39().bit())) + .field("eds40", &format_args!("{}", self.eds40().bit())) + .field("eds41", &format_args!("{}", self.eds41().bit())) + .field("eds42", &format_args!("{}", self.eds42().bit())) + .field("eds43", &format_args!("{}", self.eds43().bit())) + .field("eds44", &format_args!("{}", self.eds44().bit())) + .field("eds45", &format_args!("{}", self.eds45().bit())) + .field("eds46", &format_args!("{}", self.eds46().bit())) + .field("eds47", &format_args!("{}", self.eds47().bit())) + .field("eds48", &format_args!("{}", self.eds48().bit())) + .field("eds49", &format_args!("{}", self.eds49().bit())) + .field("eds50", &format_args!("{}", self.eds50().bit())) + .field("eds51", &format_args!("{}", self.eds51().bit())) + .field("eds52", &format_args!("{}", self.eds52().bit())) + .field("eds53", &format_args!("{}", self.eds53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Event detected 32"] #[inline(always)] #[must_use] - pub fn eds32(&mut self) -> EDS32_W<0> { + pub fn eds32(&mut self) -> EDS32_W { EDS32_W::new(self) } #[doc = "Bit 1 - Event detected 33"] #[inline(always)] #[must_use] - pub fn eds33(&mut self) -> EDS33_W<1> { + pub fn eds33(&mut self) -> EDS33_W { EDS33_W::new(self) } #[doc = "Bit 2 - Event detected 34"] #[inline(always)] #[must_use] - pub fn eds34(&mut self) -> EDS34_W<2> { + pub fn eds34(&mut self) -> EDS34_W { EDS34_W::new(self) } #[doc = "Bit 3 - Event detected 35"] #[inline(always)] #[must_use] - pub fn eds35(&mut self) -> EDS35_W<3> { + pub fn eds35(&mut self) -> EDS35_W { EDS35_W::new(self) } #[doc = "Bit 4 - Event detected 36"] #[inline(always)] #[must_use] - pub fn eds36(&mut self) -> EDS36_W<4> { + pub fn eds36(&mut self) -> EDS36_W { EDS36_W::new(self) } #[doc = "Bit 5 - Event detected 37"] #[inline(always)] #[must_use] - pub fn eds37(&mut self) -> EDS37_W<5> { + pub fn eds37(&mut self) -> EDS37_W { EDS37_W::new(self) } #[doc = "Bit 6 - Event detected 38"] #[inline(always)] #[must_use] - pub fn eds38(&mut self) -> EDS38_W<6> { + pub fn eds38(&mut self) -> EDS38_W { EDS38_W::new(self) } #[doc = "Bit 7 - Event detected 39"] #[inline(always)] #[must_use] - pub fn eds39(&mut self) -> EDS39_W<7> { + pub fn eds39(&mut self) -> EDS39_W { EDS39_W::new(self) } #[doc = "Bit 8 - Event detected 40"] #[inline(always)] #[must_use] - pub fn eds40(&mut self) -> EDS40_W<8> { + pub fn eds40(&mut self) -> EDS40_W { EDS40_W::new(self) } #[doc = "Bit 9 - Event detected 41"] #[inline(always)] #[must_use] - pub fn eds41(&mut self) -> EDS41_W<9> { + pub fn eds41(&mut self) -> EDS41_W { EDS41_W::new(self) } #[doc = "Bit 10 - Event detected 42"] #[inline(always)] #[must_use] - pub fn eds42(&mut self) -> EDS42_W<10> { + pub fn eds42(&mut self) -> EDS42_W { EDS42_W::new(self) } #[doc = "Bit 11 - Event detected 43"] #[inline(always)] #[must_use] - pub fn eds43(&mut self) -> EDS43_W<11> { + pub fn eds43(&mut self) -> EDS43_W { EDS43_W::new(self) } #[doc = "Bit 12 - Event detected 44"] #[inline(always)] #[must_use] - pub fn eds44(&mut self) -> EDS44_W<12> { + pub fn eds44(&mut self) -> EDS44_W { EDS44_W::new(self) } #[doc = "Bit 13 - Event detected 45"] #[inline(always)] #[must_use] - pub fn eds45(&mut self) -> EDS45_W<13> { + pub fn eds45(&mut self) -> EDS45_W { EDS45_W::new(self) } #[doc = "Bit 14 - Event detected 46"] #[inline(always)] #[must_use] - pub fn eds46(&mut self) -> EDS46_W<14> { + pub fn eds46(&mut self) -> EDS46_W { EDS46_W::new(self) } #[doc = "Bit 15 - Event detected 47"] #[inline(always)] #[must_use] - pub fn eds47(&mut self) -> EDS47_W<15> { + pub fn eds47(&mut self) -> EDS47_W { EDS47_W::new(self) } #[doc = "Bit 16 - Event detected 48"] #[inline(always)] #[must_use] - pub fn eds48(&mut self) -> EDS48_W<16> { + pub fn eds48(&mut self) -> EDS48_W { EDS48_W::new(self) } #[doc = "Bit 17 - Event detected 49"] #[inline(always)] #[must_use] - pub fn eds49(&mut self) -> EDS49_W<17> { + pub fn eds49(&mut self) -> EDS49_W { EDS49_W::new(self) } #[doc = "Bit 18 - Event detected 50"] #[inline(always)] #[must_use] - pub fn eds50(&mut self) -> EDS50_W<18> { + pub fn eds50(&mut self) -> EDS50_W { EDS50_W::new(self) } #[doc = "Bit 19 - Event detected 51"] #[inline(always)] #[must_use] - pub fn eds51(&mut self) -> EDS51_W<19> { + pub fn eds51(&mut self) -> EDS51_W { EDS51_W::new(self) } #[doc = "Bit 20 - Event detected 52"] #[inline(always)] #[must_use] - pub fn eds52(&mut self) -> EDS52_W<20> { + pub fn eds52(&mut self) -> EDS52_W { EDS52_W::new(self) } #[doc = "Bit 21 - Event detected 53"] #[inline(always)] #[must_use] - pub fn eds53(&mut self) -> EDS53_W<21> { + pub fn eds53(&mut self) -> EDS53_W { EDS53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Event Detect Status 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpeds1](index.html) module"] +#[doc = "GPIO Pin Event Detect Status 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpeds1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpeds1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPEDS1_SPEC; impl crate::RegisterSpec for GPEDS1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpeds1::R](R) reader structure"] -impl crate::Readable for GPEDS1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpeds1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpeds1::R`](R) reader structure"] +impl crate::Readable for GPEDS1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpeds1::W`](W) writer structure"] impl crate::Writable for GPEDS1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x003f_ffff; } diff --git a/crates/bcm2835-lpa/src/gpio/gpfen0.rs b/crates/bcm2835-lpa/src/gpio/gpfen0.rs index 58ded22..abcf609 100644 --- a/crates/bcm2835-lpa/src/gpio/gpfen0.rs +++ b/crates/bcm2835-lpa/src/gpio/gpfen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPFEN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFEN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FEN0` reader - Falling edge enabled 0"] -pub type FEN0_R = crate::BitReader; +pub type FEN0_R = crate::BitReader; #[doc = "Field `FEN0` writer - Falling edge enabled 0"] -pub type FEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN1` reader - Falling edge enabled 1"] -pub type FEN1_R = crate::BitReader; +pub type FEN1_R = crate::BitReader; #[doc = "Field `FEN1` writer - Falling edge enabled 1"] -pub type FEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN2` reader - Falling edge enabled 2"] -pub type FEN2_R = crate::BitReader; +pub type FEN2_R = crate::BitReader; #[doc = "Field `FEN2` writer - Falling edge enabled 2"] -pub type FEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN3` reader - Falling edge enabled 3"] -pub type FEN3_R = crate::BitReader; +pub type FEN3_R = crate::BitReader; #[doc = "Field `FEN3` writer - Falling edge enabled 3"] -pub type FEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN4` reader - Falling edge enabled 4"] -pub type FEN4_R = crate::BitReader; +pub type FEN4_R = crate::BitReader; #[doc = "Field `FEN4` writer - Falling edge enabled 4"] -pub type FEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN5` reader - Falling edge enabled 5"] -pub type FEN5_R = crate::BitReader; +pub type FEN5_R = crate::BitReader; #[doc = "Field `FEN5` writer - Falling edge enabled 5"] -pub type FEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN6` reader - Falling edge enabled 6"] -pub type FEN6_R = crate::BitReader; +pub type FEN6_R = crate::BitReader; #[doc = "Field `FEN6` writer - Falling edge enabled 6"] -pub type FEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN7` reader - Falling edge enabled 7"] -pub type FEN7_R = crate::BitReader; +pub type FEN7_R = crate::BitReader; #[doc = "Field `FEN7` writer - Falling edge enabled 7"] -pub type FEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN8` reader - Falling edge enabled 8"] -pub type FEN8_R = crate::BitReader; +pub type FEN8_R = crate::BitReader; #[doc = "Field `FEN8` writer - Falling edge enabled 8"] -pub type FEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN9` reader - Falling edge enabled 9"] -pub type FEN9_R = crate::BitReader; +pub type FEN9_R = crate::BitReader; #[doc = "Field `FEN9` writer - Falling edge enabled 9"] -pub type FEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN10` reader - Falling edge enabled 10"] -pub type FEN10_R = crate::BitReader; +pub type FEN10_R = crate::BitReader; #[doc = "Field `FEN10` writer - Falling edge enabled 10"] -pub type FEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN11` reader - Falling edge enabled 11"] -pub type FEN11_R = crate::BitReader; +pub type FEN11_R = crate::BitReader; #[doc = "Field `FEN11` writer - Falling edge enabled 11"] -pub type FEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN12` reader - Falling edge enabled 12"] -pub type FEN12_R = crate::BitReader; +pub type FEN12_R = crate::BitReader; #[doc = "Field `FEN12` writer - Falling edge enabled 12"] -pub type FEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN13` reader - Falling edge enabled 13"] -pub type FEN13_R = crate::BitReader; +pub type FEN13_R = crate::BitReader; #[doc = "Field `FEN13` writer - Falling edge enabled 13"] -pub type FEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN14` reader - Falling edge enabled 14"] -pub type FEN14_R = crate::BitReader; +pub type FEN14_R = crate::BitReader; #[doc = "Field `FEN14` writer - Falling edge enabled 14"] -pub type FEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN15` reader - Falling edge enabled 15"] -pub type FEN15_R = crate::BitReader; +pub type FEN15_R = crate::BitReader; #[doc = "Field `FEN15` writer - Falling edge enabled 15"] -pub type FEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN16` reader - Falling edge enabled 16"] -pub type FEN16_R = crate::BitReader; +pub type FEN16_R = crate::BitReader; #[doc = "Field `FEN16` writer - Falling edge enabled 16"] -pub type FEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN17` reader - Falling edge enabled 17"] -pub type FEN17_R = crate::BitReader; +pub type FEN17_R = crate::BitReader; #[doc = "Field `FEN17` writer - Falling edge enabled 17"] -pub type FEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN18` reader - Falling edge enabled 18"] -pub type FEN18_R = crate::BitReader; +pub type FEN18_R = crate::BitReader; #[doc = "Field `FEN18` writer - Falling edge enabled 18"] -pub type FEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN19` reader - Falling edge enabled 19"] -pub type FEN19_R = crate::BitReader; +pub type FEN19_R = crate::BitReader; #[doc = "Field `FEN19` writer - Falling edge enabled 19"] -pub type FEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN20` reader - Falling edge enabled 20"] -pub type FEN20_R = crate::BitReader; +pub type FEN20_R = crate::BitReader; #[doc = "Field `FEN20` writer - Falling edge enabled 20"] -pub type FEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN21` reader - Falling edge enabled 21"] -pub type FEN21_R = crate::BitReader; +pub type FEN21_R = crate::BitReader; #[doc = "Field `FEN21` writer - Falling edge enabled 21"] -pub type FEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN22` reader - Falling edge enabled 22"] -pub type FEN22_R = crate::BitReader; +pub type FEN22_R = crate::BitReader; #[doc = "Field `FEN22` writer - Falling edge enabled 22"] -pub type FEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN23` reader - Falling edge enabled 23"] -pub type FEN23_R = crate::BitReader; +pub type FEN23_R = crate::BitReader; #[doc = "Field `FEN23` writer - Falling edge enabled 23"] -pub type FEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN24` reader - Falling edge enabled 24"] -pub type FEN24_R = crate::BitReader; +pub type FEN24_R = crate::BitReader; #[doc = "Field `FEN24` writer - Falling edge enabled 24"] -pub type FEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN25` reader - Falling edge enabled 25"] -pub type FEN25_R = crate::BitReader; +pub type FEN25_R = crate::BitReader; #[doc = "Field `FEN25` writer - Falling edge enabled 25"] -pub type FEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN26` reader - Falling edge enabled 26"] -pub type FEN26_R = crate::BitReader; +pub type FEN26_R = crate::BitReader; #[doc = "Field `FEN26` writer - Falling edge enabled 26"] -pub type FEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN27` reader - Falling edge enabled 27"] -pub type FEN27_R = crate::BitReader; +pub type FEN27_R = crate::BitReader; #[doc = "Field `FEN27` writer - Falling edge enabled 27"] -pub type FEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN28` reader - Falling edge enabled 28"] -pub type FEN28_R = crate::BitReader; +pub type FEN28_R = crate::BitReader; #[doc = "Field `FEN28` writer - Falling edge enabled 28"] -pub type FEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN29` reader - Falling edge enabled 29"] -pub type FEN29_R = crate::BitReader; +pub type FEN29_R = crate::BitReader; #[doc = "Field `FEN29` writer - Falling edge enabled 29"] -pub type FEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN30` reader - Falling edge enabled 30"] -pub type FEN30_R = crate::BitReader; +pub type FEN30_R = crate::BitReader; #[doc = "Field `FEN30` writer - Falling edge enabled 30"] -pub type FEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN31` reader - Falling edge enabled 31"] -pub type FEN31_R = crate::BitReader; +pub type FEN31_R = crate::BitReader; #[doc = "Field `FEN31` writer - Falling edge enabled 31"] -pub type FEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Falling edge enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { FEN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFEN0") + .field("fen0", &format_args!("{}", self.fen0().bit())) + .field("fen1", &format_args!("{}", self.fen1().bit())) + .field("fen2", &format_args!("{}", self.fen2().bit())) + .field("fen3", &format_args!("{}", self.fen3().bit())) + .field("fen4", &format_args!("{}", self.fen4().bit())) + .field("fen5", &format_args!("{}", self.fen5().bit())) + .field("fen6", &format_args!("{}", self.fen6().bit())) + .field("fen7", &format_args!("{}", self.fen7().bit())) + .field("fen8", &format_args!("{}", self.fen8().bit())) + .field("fen9", &format_args!("{}", self.fen9().bit())) + .field("fen10", &format_args!("{}", self.fen10().bit())) + .field("fen11", &format_args!("{}", self.fen11().bit())) + .field("fen12", &format_args!("{}", self.fen12().bit())) + .field("fen13", &format_args!("{}", self.fen13().bit())) + .field("fen14", &format_args!("{}", self.fen14().bit())) + .field("fen15", &format_args!("{}", self.fen15().bit())) + .field("fen16", &format_args!("{}", self.fen16().bit())) + .field("fen17", &format_args!("{}", self.fen17().bit())) + .field("fen18", &format_args!("{}", self.fen18().bit())) + .field("fen19", &format_args!("{}", self.fen19().bit())) + .field("fen20", &format_args!("{}", self.fen20().bit())) + .field("fen21", &format_args!("{}", self.fen21().bit())) + .field("fen22", &format_args!("{}", self.fen22().bit())) + .field("fen23", &format_args!("{}", self.fen23().bit())) + .field("fen24", &format_args!("{}", self.fen24().bit())) + .field("fen25", &format_args!("{}", self.fen25().bit())) + .field("fen26", &format_args!("{}", self.fen26().bit())) + .field("fen27", &format_args!("{}", self.fen27().bit())) + .field("fen28", &format_args!("{}", self.fen28().bit())) + .field("fen29", &format_args!("{}", self.fen29().bit())) + .field("fen30", &format_args!("{}", self.fen30().bit())) + .field("fen31", &format_args!("{}", self.fen31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Falling edge enabled 0"] #[inline(always)] #[must_use] - pub fn fen0(&mut self) -> FEN0_W<0> { + pub fn fen0(&mut self) -> FEN0_W { FEN0_W::new(self) } #[doc = "Bit 1 - Falling edge enabled 1"] #[inline(always)] #[must_use] - pub fn fen1(&mut self) -> FEN1_W<1> { + pub fn fen1(&mut self) -> FEN1_W { FEN1_W::new(self) } #[doc = "Bit 2 - Falling edge enabled 2"] #[inline(always)] #[must_use] - pub fn fen2(&mut self) -> FEN2_W<2> { + pub fn fen2(&mut self) -> FEN2_W { FEN2_W::new(self) } #[doc = "Bit 3 - Falling edge enabled 3"] #[inline(always)] #[must_use] - pub fn fen3(&mut self) -> FEN3_W<3> { + pub fn fen3(&mut self) -> FEN3_W { FEN3_W::new(self) } #[doc = "Bit 4 - Falling edge enabled 4"] #[inline(always)] #[must_use] - pub fn fen4(&mut self) -> FEN4_W<4> { + pub fn fen4(&mut self) -> FEN4_W { FEN4_W::new(self) } #[doc = "Bit 5 - Falling edge enabled 5"] #[inline(always)] #[must_use] - pub fn fen5(&mut self) -> FEN5_W<5> { + pub fn fen5(&mut self) -> FEN5_W { FEN5_W::new(self) } #[doc = "Bit 6 - Falling edge enabled 6"] #[inline(always)] #[must_use] - pub fn fen6(&mut self) -> FEN6_W<6> { + pub fn fen6(&mut self) -> FEN6_W { FEN6_W::new(self) } #[doc = "Bit 7 - Falling edge enabled 7"] #[inline(always)] #[must_use] - pub fn fen7(&mut self) -> FEN7_W<7> { + pub fn fen7(&mut self) -> FEN7_W { FEN7_W::new(self) } #[doc = "Bit 8 - Falling edge enabled 8"] #[inline(always)] #[must_use] - pub fn fen8(&mut self) -> FEN8_W<8> { + pub fn fen8(&mut self) -> FEN8_W { FEN8_W::new(self) } #[doc = "Bit 9 - Falling edge enabled 9"] #[inline(always)] #[must_use] - pub fn fen9(&mut self) -> FEN9_W<9> { + pub fn fen9(&mut self) -> FEN9_W { FEN9_W::new(self) } #[doc = "Bit 10 - Falling edge enabled 10"] #[inline(always)] #[must_use] - pub fn fen10(&mut self) -> FEN10_W<10> { + pub fn fen10(&mut self) -> FEN10_W { FEN10_W::new(self) } #[doc = "Bit 11 - Falling edge enabled 11"] #[inline(always)] #[must_use] - pub fn fen11(&mut self) -> FEN11_W<11> { + pub fn fen11(&mut self) -> FEN11_W { FEN11_W::new(self) } #[doc = "Bit 12 - Falling edge enabled 12"] #[inline(always)] #[must_use] - pub fn fen12(&mut self) -> FEN12_W<12> { + pub fn fen12(&mut self) -> FEN12_W { FEN12_W::new(self) } #[doc = "Bit 13 - Falling edge enabled 13"] #[inline(always)] #[must_use] - pub fn fen13(&mut self) -> FEN13_W<13> { + pub fn fen13(&mut self) -> FEN13_W { FEN13_W::new(self) } #[doc = "Bit 14 - Falling edge enabled 14"] #[inline(always)] #[must_use] - pub fn fen14(&mut self) -> FEN14_W<14> { + pub fn fen14(&mut self) -> FEN14_W { FEN14_W::new(self) } #[doc = "Bit 15 - Falling edge enabled 15"] #[inline(always)] #[must_use] - pub fn fen15(&mut self) -> FEN15_W<15> { + pub fn fen15(&mut self) -> FEN15_W { FEN15_W::new(self) } #[doc = "Bit 16 - Falling edge enabled 16"] #[inline(always)] #[must_use] - pub fn fen16(&mut self) -> FEN16_W<16> { + pub fn fen16(&mut self) -> FEN16_W { FEN16_W::new(self) } #[doc = "Bit 17 - Falling edge enabled 17"] #[inline(always)] #[must_use] - pub fn fen17(&mut self) -> FEN17_W<17> { + pub fn fen17(&mut self) -> FEN17_W { FEN17_W::new(self) } #[doc = "Bit 18 - Falling edge enabled 18"] #[inline(always)] #[must_use] - pub fn fen18(&mut self) -> FEN18_W<18> { + pub fn fen18(&mut self) -> FEN18_W { FEN18_W::new(self) } #[doc = "Bit 19 - Falling edge enabled 19"] #[inline(always)] #[must_use] - pub fn fen19(&mut self) -> FEN19_W<19> { + pub fn fen19(&mut self) -> FEN19_W { FEN19_W::new(self) } #[doc = "Bit 20 - Falling edge enabled 20"] #[inline(always)] #[must_use] - pub fn fen20(&mut self) -> FEN20_W<20> { + pub fn fen20(&mut self) -> FEN20_W { FEN20_W::new(self) } #[doc = "Bit 21 - Falling edge enabled 21"] #[inline(always)] #[must_use] - pub fn fen21(&mut self) -> FEN21_W<21> { + pub fn fen21(&mut self) -> FEN21_W { FEN21_W::new(self) } #[doc = "Bit 22 - Falling edge enabled 22"] #[inline(always)] #[must_use] - pub fn fen22(&mut self) -> FEN22_W<22> { + pub fn fen22(&mut self) -> FEN22_W { FEN22_W::new(self) } #[doc = "Bit 23 - Falling edge enabled 23"] #[inline(always)] #[must_use] - pub fn fen23(&mut self) -> FEN23_W<23> { + pub fn fen23(&mut self) -> FEN23_W { FEN23_W::new(self) } #[doc = "Bit 24 - Falling edge enabled 24"] #[inline(always)] #[must_use] - pub fn fen24(&mut self) -> FEN24_W<24> { + pub fn fen24(&mut self) -> FEN24_W { FEN24_W::new(self) } #[doc = "Bit 25 - Falling edge enabled 25"] #[inline(always)] #[must_use] - pub fn fen25(&mut self) -> FEN25_W<25> { + pub fn fen25(&mut self) -> FEN25_W { FEN25_W::new(self) } #[doc = "Bit 26 - Falling edge enabled 26"] #[inline(always)] #[must_use] - pub fn fen26(&mut self) -> FEN26_W<26> { + pub fn fen26(&mut self) -> FEN26_W { FEN26_W::new(self) } #[doc = "Bit 27 - Falling edge enabled 27"] #[inline(always)] #[must_use] - pub fn fen27(&mut self) -> FEN27_W<27> { + pub fn fen27(&mut self) -> FEN27_W { FEN27_W::new(self) } #[doc = "Bit 28 - Falling edge enabled 28"] #[inline(always)] #[must_use] - pub fn fen28(&mut self) -> FEN28_W<28> { + pub fn fen28(&mut self) -> FEN28_W { FEN28_W::new(self) } #[doc = "Bit 29 - Falling edge enabled 29"] #[inline(always)] #[must_use] - pub fn fen29(&mut self) -> FEN29_W<29> { + pub fn fen29(&mut self) -> FEN29_W { FEN29_W::new(self) } #[doc = "Bit 30 - Falling edge enabled 30"] #[inline(always)] #[must_use] - pub fn fen30(&mut self) -> FEN30_W<30> { + pub fn fen30(&mut self) -> FEN30_W { FEN30_W::new(self) } #[doc = "Bit 31 - Falling edge enabled 31"] #[inline(always)] #[must_use] - pub fn fen31(&mut self) -> FEN31_W<31> { + pub fn fen31(&mut self) -> FEN31_W { FEN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Falling Edge Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfen0](index.html) module"] +#[doc = "GPIO Pin Falling Edge Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFEN0_SPEC; impl crate::RegisterSpec for GPFEN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfen0::R](R) reader structure"] -impl crate::Readable for GPFEN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfen0::R`](R) reader structure"] +impl crate::Readable for GPFEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfen0::W`](W) writer structure"] impl crate::Writable for GPFEN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpfen1.rs b/crates/bcm2835-lpa/src/gpio/gpfen1.rs index 4e4498a..d0e94e8 100644 --- a/crates/bcm2835-lpa/src/gpio/gpfen1.rs +++ b/crates/bcm2835-lpa/src/gpio/gpfen1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPFEN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFEN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FEN32` reader - Falling edge enabled 32"] -pub type FEN32_R = crate::BitReader; +pub type FEN32_R = crate::BitReader; #[doc = "Field `FEN32` writer - Falling edge enabled 32"] -pub type FEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN33` reader - Falling edge enabled 33"] -pub type FEN33_R = crate::BitReader; +pub type FEN33_R = crate::BitReader; #[doc = "Field `FEN33` writer - Falling edge enabled 33"] -pub type FEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN34` reader - Falling edge enabled 34"] -pub type FEN34_R = crate::BitReader; +pub type FEN34_R = crate::BitReader; #[doc = "Field `FEN34` writer - Falling edge enabled 34"] -pub type FEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN35` reader - Falling edge enabled 35"] -pub type FEN35_R = crate::BitReader; +pub type FEN35_R = crate::BitReader; #[doc = "Field `FEN35` writer - Falling edge enabled 35"] -pub type FEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN36` reader - Falling edge enabled 36"] -pub type FEN36_R = crate::BitReader; +pub type FEN36_R = crate::BitReader; #[doc = "Field `FEN36` writer - Falling edge enabled 36"] -pub type FEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN37` reader - Falling edge enabled 37"] -pub type FEN37_R = crate::BitReader; +pub type FEN37_R = crate::BitReader; #[doc = "Field `FEN37` writer - Falling edge enabled 37"] -pub type FEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN38` reader - Falling edge enabled 38"] -pub type FEN38_R = crate::BitReader; +pub type FEN38_R = crate::BitReader; #[doc = "Field `FEN38` writer - Falling edge enabled 38"] -pub type FEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN39` reader - Falling edge enabled 39"] -pub type FEN39_R = crate::BitReader; +pub type FEN39_R = crate::BitReader; #[doc = "Field `FEN39` writer - Falling edge enabled 39"] -pub type FEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN40` reader - Falling edge enabled 40"] -pub type FEN40_R = crate::BitReader; +pub type FEN40_R = crate::BitReader; #[doc = "Field `FEN40` writer - Falling edge enabled 40"] -pub type FEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN41` reader - Falling edge enabled 41"] -pub type FEN41_R = crate::BitReader; +pub type FEN41_R = crate::BitReader; #[doc = "Field `FEN41` writer - Falling edge enabled 41"] -pub type FEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN42` reader - Falling edge enabled 42"] -pub type FEN42_R = crate::BitReader; +pub type FEN42_R = crate::BitReader; #[doc = "Field `FEN42` writer - Falling edge enabled 42"] -pub type FEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN43` reader - Falling edge enabled 43"] -pub type FEN43_R = crate::BitReader; +pub type FEN43_R = crate::BitReader; #[doc = "Field `FEN43` writer - Falling edge enabled 43"] -pub type FEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN44` reader - Falling edge enabled 44"] -pub type FEN44_R = crate::BitReader; +pub type FEN44_R = crate::BitReader; #[doc = "Field `FEN44` writer - Falling edge enabled 44"] -pub type FEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN45` reader - Falling edge enabled 45"] -pub type FEN45_R = crate::BitReader; +pub type FEN45_R = crate::BitReader; #[doc = "Field `FEN45` writer - Falling edge enabled 45"] -pub type FEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN46` reader - Falling edge enabled 46"] -pub type FEN46_R = crate::BitReader; +pub type FEN46_R = crate::BitReader; #[doc = "Field `FEN46` writer - Falling edge enabled 46"] -pub type FEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN47` reader - Falling edge enabled 47"] -pub type FEN47_R = crate::BitReader; +pub type FEN47_R = crate::BitReader; #[doc = "Field `FEN47` writer - Falling edge enabled 47"] -pub type FEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN48` reader - Falling edge enabled 48"] -pub type FEN48_R = crate::BitReader; +pub type FEN48_R = crate::BitReader; #[doc = "Field `FEN48` writer - Falling edge enabled 48"] -pub type FEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN49` reader - Falling edge enabled 49"] -pub type FEN49_R = crate::BitReader; +pub type FEN49_R = crate::BitReader; #[doc = "Field `FEN49` writer - Falling edge enabled 49"] -pub type FEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN50` reader - Falling edge enabled 50"] -pub type FEN50_R = crate::BitReader; +pub type FEN50_R = crate::BitReader; #[doc = "Field `FEN50` writer - Falling edge enabled 50"] -pub type FEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN51` reader - Falling edge enabled 51"] -pub type FEN51_R = crate::BitReader; +pub type FEN51_R = crate::BitReader; #[doc = "Field `FEN51` writer - Falling edge enabled 51"] -pub type FEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN52` reader - Falling edge enabled 52"] -pub type FEN52_R = crate::BitReader; +pub type FEN52_R = crate::BitReader; #[doc = "Field `FEN52` writer - Falling edge enabled 52"] -pub type FEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN53` reader - Falling edge enabled 53"] -pub type FEN53_R = crate::BitReader; +pub type FEN53_R = crate::BitReader; #[doc = "Field `FEN53` writer - Falling edge enabled 53"] -pub type FEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Falling edge enabled 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { FEN53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFEN1") + .field("fen32", &format_args!("{}", self.fen32().bit())) + .field("fen33", &format_args!("{}", self.fen33().bit())) + .field("fen34", &format_args!("{}", self.fen34().bit())) + .field("fen35", &format_args!("{}", self.fen35().bit())) + .field("fen36", &format_args!("{}", self.fen36().bit())) + .field("fen37", &format_args!("{}", self.fen37().bit())) + .field("fen38", &format_args!("{}", self.fen38().bit())) + .field("fen39", &format_args!("{}", self.fen39().bit())) + .field("fen40", &format_args!("{}", self.fen40().bit())) + .field("fen41", &format_args!("{}", self.fen41().bit())) + .field("fen42", &format_args!("{}", self.fen42().bit())) + .field("fen43", &format_args!("{}", self.fen43().bit())) + .field("fen44", &format_args!("{}", self.fen44().bit())) + .field("fen45", &format_args!("{}", self.fen45().bit())) + .field("fen46", &format_args!("{}", self.fen46().bit())) + .field("fen47", &format_args!("{}", self.fen47().bit())) + .field("fen48", &format_args!("{}", self.fen48().bit())) + .field("fen49", &format_args!("{}", self.fen49().bit())) + .field("fen50", &format_args!("{}", self.fen50().bit())) + .field("fen51", &format_args!("{}", self.fen51().bit())) + .field("fen52", &format_args!("{}", self.fen52().bit())) + .field("fen53", &format_args!("{}", self.fen53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Falling edge enabled 32"] #[inline(always)] #[must_use] - pub fn fen32(&mut self) -> FEN32_W<0> { + pub fn fen32(&mut self) -> FEN32_W { FEN32_W::new(self) } #[doc = "Bit 1 - Falling edge enabled 33"] #[inline(always)] #[must_use] - pub fn fen33(&mut self) -> FEN33_W<1> { + pub fn fen33(&mut self) -> FEN33_W { FEN33_W::new(self) } #[doc = "Bit 2 - Falling edge enabled 34"] #[inline(always)] #[must_use] - pub fn fen34(&mut self) -> FEN34_W<2> { + pub fn fen34(&mut self) -> FEN34_W { FEN34_W::new(self) } #[doc = "Bit 3 - Falling edge enabled 35"] #[inline(always)] #[must_use] - pub fn fen35(&mut self) -> FEN35_W<3> { + pub fn fen35(&mut self) -> FEN35_W { FEN35_W::new(self) } #[doc = "Bit 4 - Falling edge enabled 36"] #[inline(always)] #[must_use] - pub fn fen36(&mut self) -> FEN36_W<4> { + pub fn fen36(&mut self) -> FEN36_W { FEN36_W::new(self) } #[doc = "Bit 5 - Falling edge enabled 37"] #[inline(always)] #[must_use] - pub fn fen37(&mut self) -> FEN37_W<5> { + pub fn fen37(&mut self) -> FEN37_W { FEN37_W::new(self) } #[doc = "Bit 6 - Falling edge enabled 38"] #[inline(always)] #[must_use] - pub fn fen38(&mut self) -> FEN38_W<6> { + pub fn fen38(&mut self) -> FEN38_W { FEN38_W::new(self) } #[doc = "Bit 7 - Falling edge enabled 39"] #[inline(always)] #[must_use] - pub fn fen39(&mut self) -> FEN39_W<7> { + pub fn fen39(&mut self) -> FEN39_W { FEN39_W::new(self) } #[doc = "Bit 8 - Falling edge enabled 40"] #[inline(always)] #[must_use] - pub fn fen40(&mut self) -> FEN40_W<8> { + pub fn fen40(&mut self) -> FEN40_W { FEN40_W::new(self) } #[doc = "Bit 9 - Falling edge enabled 41"] #[inline(always)] #[must_use] - pub fn fen41(&mut self) -> FEN41_W<9> { + pub fn fen41(&mut self) -> FEN41_W { FEN41_W::new(self) } #[doc = "Bit 10 - Falling edge enabled 42"] #[inline(always)] #[must_use] - pub fn fen42(&mut self) -> FEN42_W<10> { + pub fn fen42(&mut self) -> FEN42_W { FEN42_W::new(self) } #[doc = "Bit 11 - Falling edge enabled 43"] #[inline(always)] #[must_use] - pub fn fen43(&mut self) -> FEN43_W<11> { + pub fn fen43(&mut self) -> FEN43_W { FEN43_W::new(self) } #[doc = "Bit 12 - Falling edge enabled 44"] #[inline(always)] #[must_use] - pub fn fen44(&mut self) -> FEN44_W<12> { + pub fn fen44(&mut self) -> FEN44_W { FEN44_W::new(self) } #[doc = "Bit 13 - Falling edge enabled 45"] #[inline(always)] #[must_use] - pub fn fen45(&mut self) -> FEN45_W<13> { + pub fn fen45(&mut self) -> FEN45_W { FEN45_W::new(self) } #[doc = "Bit 14 - Falling edge enabled 46"] #[inline(always)] #[must_use] - pub fn fen46(&mut self) -> FEN46_W<14> { + pub fn fen46(&mut self) -> FEN46_W { FEN46_W::new(self) } #[doc = "Bit 15 - Falling edge enabled 47"] #[inline(always)] #[must_use] - pub fn fen47(&mut self) -> FEN47_W<15> { + pub fn fen47(&mut self) -> FEN47_W { FEN47_W::new(self) } #[doc = "Bit 16 - Falling edge enabled 48"] #[inline(always)] #[must_use] - pub fn fen48(&mut self) -> FEN48_W<16> { + pub fn fen48(&mut self) -> FEN48_W { FEN48_W::new(self) } #[doc = "Bit 17 - Falling edge enabled 49"] #[inline(always)] #[must_use] - pub fn fen49(&mut self) -> FEN49_W<17> { + pub fn fen49(&mut self) -> FEN49_W { FEN49_W::new(self) } #[doc = "Bit 18 - Falling edge enabled 50"] #[inline(always)] #[must_use] - pub fn fen50(&mut self) -> FEN50_W<18> { + pub fn fen50(&mut self) -> FEN50_W { FEN50_W::new(self) } #[doc = "Bit 19 - Falling edge enabled 51"] #[inline(always)] #[must_use] - pub fn fen51(&mut self) -> FEN51_W<19> { + pub fn fen51(&mut self) -> FEN51_W { FEN51_W::new(self) } #[doc = "Bit 20 - Falling edge enabled 52"] #[inline(always)] #[must_use] - pub fn fen52(&mut self) -> FEN52_W<20> { + pub fn fen52(&mut self) -> FEN52_W { FEN52_W::new(self) } #[doc = "Bit 21 - Falling edge enabled 53"] #[inline(always)] #[must_use] - pub fn fen53(&mut self) -> FEN53_W<21> { + pub fn fen53(&mut self) -> FEN53_W { FEN53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Falling Edge Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfen1](index.html) module"] +#[doc = "GPIO Pin Falling Edge Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFEN1_SPEC; impl crate::RegisterSpec for GPFEN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfen1::R](R) reader structure"] -impl crate::Readable for GPFEN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfen1::R`](R) reader structure"] +impl crate::Readable for GPFEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfen1::W`](W) writer structure"] impl crate::Writable for GPFEN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpfsel0.rs b/crates/bcm2835-lpa/src/gpio/gpfsel0.rs index 4109144..dcdf15a 100644 --- a/crates/bcm2835-lpa/src/gpio/gpfsel0.rs +++ b/crates/bcm2835-lpa/src/gpio/gpfsel0.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL0` reader - Function Select 0"] -pub type FSEL0_R = crate::FieldReader; +pub type FSEL0_R = crate::FieldReader; #[doc = "Function Select 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL0_A { + type Ux = u8; +} impl FSEL0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL0_A { + pub const fn variant(&self) -> FSEL0_A { match self.bits { 0 => FSEL0_A::INPUT, 1 => FSEL0_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL0_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL0_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL0_A::OUTPUT } - #[doc = "Checks if the value of the field is `SDA0`"] + #[doc = "Pin is connected to SDA0"] #[inline(always)] pub fn is_sda0(&self) -> bool { *self == FSEL0_A::SDA0 } - #[doc = "Checks if the value of the field is `SA5`"] + #[doc = "Pin is connected to SA5"] #[inline(always)] pub fn is_sa5(&self) -> bool { *self == FSEL0_A::SA5 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL0_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL0_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL0_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL0_A::RESERVED5 } } #[doc = "Field `FSEL0` writer - Function Select 0"] -pub type FSEL0_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL0_A, 3, O>; -impl<'a, const O: u8> FSEL0_W<'a, O> { +pub type FSEL0_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL0_A>; +impl<'a, REG, const O: u8> FSEL0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL0_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL0_A::OUTPUT) } #[doc = "Pin is connected to SDA0"] #[inline(always)] - pub fn sda0(self) -> &'a mut W { + pub fn sda0(self) -> &'a mut crate::W { self.variant(FSEL0_A::SDA0) } #[doc = "Pin is connected to SA5"] #[inline(always)] - pub fn sa5(self) -> &'a mut W { + pub fn sa5(self) -> &'a mut crate::W { self.variant(FSEL0_A::SA5) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL0_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL0_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL0_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL0_A::RESERVED5) } } #[doc = "Field `FSEL1` reader - Function Select 1"] -pub type FSEL1_R = crate::FieldReader; +pub type FSEL1_R = crate::FieldReader; #[doc = "Function Select 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL1_A { + type Ux = u8; +} impl FSEL1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL1_A { + pub const fn variant(&self) -> FSEL1_A { match self.bits { 0 => FSEL1_A::INPUT, 1 => FSEL1_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL1_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL1_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL1_A::OUTPUT } - #[doc = "Checks if the value of the field is `SCL0`"] + #[doc = "Pin is connected to SCL0"] #[inline(always)] pub fn is_scl0(&self) -> bool { *self == FSEL1_A::SCL0 } - #[doc = "Checks if the value of the field is `SA4`"] + #[doc = "Pin is connected to SA4"] #[inline(always)] pub fn is_sa4(&self) -> bool { *self == FSEL1_A::SA4 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL1_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL1_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL1_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL1_A::RESERVED5 } } #[doc = "Field `FSEL1` writer - Function Select 1"] -pub type FSEL1_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL1_A, 3, O>; -impl<'a, const O: u8> FSEL1_W<'a, O> { +pub type FSEL1_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL1_A>; +impl<'a, REG, const O: u8> FSEL1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL1_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL1_A::OUTPUT) } #[doc = "Pin is connected to SCL0"] #[inline(always)] - pub fn scl0(self) -> &'a mut W { + pub fn scl0(self) -> &'a mut crate::W { self.variant(FSEL1_A::SCL0) } #[doc = "Pin is connected to SA4"] #[inline(always)] - pub fn sa4(self) -> &'a mut W { + pub fn sa4(self) -> &'a mut crate::W { self.variant(FSEL1_A::SA4) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL1_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL1_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL1_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL1_A::RESERVED5) } } #[doc = "Field `FSEL2` reader - Function Select 2"] -pub type FSEL2_R = crate::FieldReader; +pub type FSEL2_R = crate::FieldReader; #[doc = "Function Select 2"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL2_A { + type Ux = u8; +} impl FSEL2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL2_A { + pub const fn variant(&self) -> FSEL2_A { match self.bits { 0 => FSEL2_A::INPUT, 1 => FSEL2_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL2_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL2_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL2_A::OUTPUT } - #[doc = "Checks if the value of the field is `SDA1`"] + #[doc = "Pin is connected to SDA1"] #[inline(always)] pub fn is_sda1(&self) -> bool { *self == FSEL2_A::SDA1 } - #[doc = "Checks if the value of the field is `SA3`"] + #[doc = "Pin is connected to SA3"] #[inline(always)] pub fn is_sa3(&self) -> bool { *self == FSEL2_A::SA3 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL2_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL2_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL2_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL2_A::RESERVED5 } } #[doc = "Field `FSEL2` writer - Function Select 2"] -pub type FSEL2_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL2_A, 3, O>; -impl<'a, const O: u8> FSEL2_W<'a, O> { +pub type FSEL2_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL2_A>; +impl<'a, REG, const O: u8> FSEL2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL2_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL2_A::OUTPUT) } #[doc = "Pin is connected to SDA1"] #[inline(always)] - pub fn sda1(self) -> &'a mut W { + pub fn sda1(self) -> &'a mut crate::W { self.variant(FSEL2_A::SDA1) } #[doc = "Pin is connected to SA3"] #[inline(always)] - pub fn sa3(self) -> &'a mut W { + pub fn sa3(self) -> &'a mut crate::W { self.variant(FSEL2_A::SA3) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL2_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL2_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL2_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL2_A::RESERVED5) } } #[doc = "Field `FSEL3` reader - Function Select 3"] -pub type FSEL3_R = crate::FieldReader; +pub type FSEL3_R = crate::FieldReader; #[doc = "Function Select 3"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL3_A { + type Ux = u8; +} impl FSEL3_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL3_A { + pub const fn variant(&self) -> FSEL3_A { match self.bits { 0 => FSEL3_A::INPUT, 1 => FSEL3_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL3_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL3_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL3_A::OUTPUT } - #[doc = "Checks if the value of the field is `SCL1`"] + #[doc = "Pin is connected to SCL1"] #[inline(always)] pub fn is_scl1(&self) -> bool { *self == FSEL3_A::SCL1 } - #[doc = "Checks if the value of the field is `SA2`"] + #[doc = "Pin is connected to SA2"] #[inline(always)] pub fn is_sa2(&self) -> bool { *self == FSEL3_A::SA2 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL3_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL3_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL3_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL3_A::RESERVED5 } } #[doc = "Field `FSEL3` writer - Function Select 3"] -pub type FSEL3_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL3_A, 3, O>; -impl<'a, const O: u8> FSEL3_W<'a, O> { +pub type FSEL3_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL3_A>; +impl<'a, REG, const O: u8> FSEL3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL3_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL3_A::OUTPUT) } #[doc = "Pin is connected to SCL1"] #[inline(always)] - pub fn scl1(self) -> &'a mut W { + pub fn scl1(self) -> &'a mut crate::W { self.variant(FSEL3_A::SCL1) } #[doc = "Pin is connected to SA2"] #[inline(always)] - pub fn sa2(self) -> &'a mut W { + pub fn sa2(self) -> &'a mut crate::W { self.variant(FSEL3_A::SA2) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL3_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL3_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL3_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL3_A::RESERVED5) } } #[doc = "Field `FSEL4` reader - Function Select 4"] -pub type FSEL4_R = crate::FieldReader; +pub type FSEL4_R = crate::FieldReader; #[doc = "Function Select 4"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL4_A { + type Ux = u8; +} impl FSEL4_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL4_A { + pub const fn variant(&self) -> FSEL4_A { match self.bits { 0 => FSEL4_A::INPUT, 1 => FSEL4_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL4_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL4_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL4_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK0`"] + #[doc = "Pin is connected to GPCLK0"] #[inline(always)] pub fn is_gpclk0(&self) -> bool { *self == FSEL4_A::GPCLK0 } - #[doc = "Checks if the value of the field is `SA1`"] + #[doc = "Pin is connected to SA1"] #[inline(always)] pub fn is_sa1(&self) -> bool { *self == FSEL4_A::SA1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL4_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL4_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL4_A::RESERVED4 } - #[doc = "Checks if the value of the field is `ARM_TDI`"] + #[doc = "Pin is connected to ARM_TDI"] #[inline(always)] pub fn is_arm_tdi(&self) -> bool { *self == FSEL4_A::ARM_TDI } } #[doc = "Field `FSEL4` writer - Function Select 4"] -pub type FSEL4_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL4_A, 3, O>; -impl<'a, const O: u8> FSEL4_W<'a, O> { +pub type FSEL4_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL4_A>; +impl<'a, REG, const O: u8> FSEL4_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL4_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL4_A::OUTPUT) } #[doc = "Pin is connected to GPCLK0"] #[inline(always)] - pub fn gpclk0(self) -> &'a mut W { + pub fn gpclk0(self) -> &'a mut crate::W { self.variant(FSEL4_A::GPCLK0) } #[doc = "Pin is connected to SA1"] #[inline(always)] - pub fn sa1(self) -> &'a mut W { + pub fn sa1(self) -> &'a mut crate::W { self.variant(FSEL4_A::SA1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL4_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL4_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL4_A::RESERVED4) } #[doc = "Pin is connected to ARM_TDI"] #[inline(always)] - pub fn arm_tdi(self) -> &'a mut W { + pub fn arm_tdi(self) -> &'a mut crate::W { self.variant(FSEL4_A::ARM_TDI) } } #[doc = "Field `FSEL5` reader - Function Select 5"] -pub type FSEL5_R = crate::FieldReader; +pub type FSEL5_R = crate::FieldReader; #[doc = "Function Select 5"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL5_A { + type Ux = u8; +} impl FSEL5_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL5_A { + pub const fn variant(&self) -> FSEL5_A { match self.bits { 0 => FSEL5_A::INPUT, 1 => FSEL5_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL5_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL5_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL5_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK1`"] + #[doc = "Pin is connected to GPCLK1"] #[inline(always)] pub fn is_gpclk1(&self) -> bool { *self == FSEL5_A::GPCLK1 } - #[doc = "Checks if the value of the field is `SA0`"] + #[doc = "Pin is connected to SA0"] #[inline(always)] pub fn is_sa0(&self) -> bool { *self == FSEL5_A::SA0 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL5_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL5_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL5_A::RESERVED4 } - #[doc = "Checks if the value of the field is `ARM_TDO`"] + #[doc = "Pin is connected to ARM_TDO"] #[inline(always)] pub fn is_arm_tdo(&self) -> bool { *self == FSEL5_A::ARM_TDO } } #[doc = "Field `FSEL5` writer - Function Select 5"] -pub type FSEL5_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL5_A, 3, O>; -impl<'a, const O: u8> FSEL5_W<'a, O> { +pub type FSEL5_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL5_A>; +impl<'a, REG, const O: u8> FSEL5_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL5_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL5_A::OUTPUT) } #[doc = "Pin is connected to GPCLK1"] #[inline(always)] - pub fn gpclk1(self) -> &'a mut W { + pub fn gpclk1(self) -> &'a mut crate::W { self.variant(FSEL5_A::GPCLK1) } #[doc = "Pin is connected to SA0"] #[inline(always)] - pub fn sa0(self) -> &'a mut W { + pub fn sa0(self) -> &'a mut crate::W { self.variant(FSEL5_A::SA0) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL5_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL5_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL5_A::RESERVED4) } #[doc = "Pin is connected to ARM_TDO"] #[inline(always)] - pub fn arm_tdo(self) -> &'a mut W { + pub fn arm_tdo(self) -> &'a mut crate::W { self.variant(FSEL5_A::ARM_TDO) } } #[doc = "Field `FSEL6` reader - Function Select 6"] -pub type FSEL6_R = crate::FieldReader; +pub type FSEL6_R = crate::FieldReader; #[doc = "Function Select 6"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL6_A { + type Ux = u8; +} impl FSEL6_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL6_A { + pub const fn variant(&self) -> FSEL6_A { match self.bits { 0 => FSEL6_A::INPUT, 1 => FSEL6_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL6_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL6_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL6_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK2`"] + #[doc = "Pin is connected to GPCLK2"] #[inline(always)] pub fn is_gpclk2(&self) -> bool { *self == FSEL6_A::GPCLK2 } - #[doc = "Checks if the value of the field is `SOE_N`"] + #[doc = "Pin is connected to SOE_N"] #[inline(always)] pub fn is_soe_n(&self) -> bool { *self == FSEL6_A::SOE_N } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL6_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL6_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL6_A::RESERVED4 } - #[doc = "Checks if the value of the field is `ARM_RTCK`"] + #[doc = "Pin is connected to ARM_RTCK"] #[inline(always)] pub fn is_arm_rtck(&self) -> bool { *self == FSEL6_A::ARM_RTCK } } #[doc = "Field `FSEL6` writer - Function Select 6"] -pub type FSEL6_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL6_A, 3, O>; -impl<'a, const O: u8> FSEL6_W<'a, O> { +pub type FSEL6_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL6_A>; +impl<'a, REG, const O: u8> FSEL6_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL6_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL6_A::OUTPUT) } #[doc = "Pin is connected to GPCLK2"] #[inline(always)] - pub fn gpclk2(self) -> &'a mut W { + pub fn gpclk2(self) -> &'a mut crate::W { self.variant(FSEL6_A::GPCLK2) } #[doc = "Pin is connected to SOE_N"] #[inline(always)] - pub fn soe_n(self) -> &'a mut W { + pub fn soe_n(self) -> &'a mut crate::W { self.variant(FSEL6_A::SOE_N) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL6_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL6_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL6_A::RESERVED4) } #[doc = "Pin is connected to ARM_RTCK"] #[inline(always)] - pub fn arm_rtck(self) -> &'a mut W { + pub fn arm_rtck(self) -> &'a mut crate::W { self.variant(FSEL6_A::ARM_RTCK) } } #[doc = "Field `FSEL7` reader - Function Select 7"] -pub type FSEL7_R = crate::FieldReader; +pub type FSEL7_R = crate::FieldReader; #[doc = "Function Select 7"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL7_A { + type Ux = u8; +} impl FSEL7_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL7_A { + pub const fn variant(&self) -> FSEL7_A { match self.bits { 0 => FSEL7_A::INPUT, 1 => FSEL7_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL7_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL7_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL7_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_CE1_N`"] + #[doc = "Pin is connected to SPI0_CE1_N"] #[inline(always)] pub fn is_spi0_ce1_n(&self) -> bool { *self == FSEL7_A::SPI0_CE1_N } - #[doc = "Checks if the value of the field is `SWE_N`"] + #[doc = "Pin is connected to SWE_N"] #[inline(always)] pub fn is_swe_n(&self) -> bool { *self == FSEL7_A::SWE_N } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL7_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL7_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL7_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL7_A::RESERVED5 } } #[doc = "Field `FSEL7` writer - Function Select 7"] -pub type FSEL7_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL7_A, 3, O>; -impl<'a, const O: u8> FSEL7_W<'a, O> { +pub type FSEL7_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL7_A>; +impl<'a, REG, const O: u8> FSEL7_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL7_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL7_A::OUTPUT) } #[doc = "Pin is connected to SPI0_CE1_N"] #[inline(always)] - pub fn spi0_ce1_n(self) -> &'a mut W { + pub fn spi0_ce1_n(self) -> &'a mut crate::W { self.variant(FSEL7_A::SPI0_CE1_N) } #[doc = "Pin is connected to SWE_N"] #[inline(always)] - pub fn swe_n(self) -> &'a mut W { + pub fn swe_n(self) -> &'a mut crate::W { self.variant(FSEL7_A::SWE_N) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL7_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL7_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL7_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL7_A::RESERVED5) } } #[doc = "Field `FSEL8` reader - Function Select 8"] -pub type FSEL8_R = crate::FieldReader; +pub type FSEL8_R = crate::FieldReader; #[doc = "Function Select 8"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL8_A { + type Ux = u8; +} impl FSEL8_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL8_A { + pub const fn variant(&self) -> FSEL8_A { match self.bits { 0 => FSEL8_A::INPUT, 1 => FSEL8_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL8_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL8_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL8_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_CE0_N`"] + #[doc = "Pin is connected to SPI0_CE0_N"] #[inline(always)] pub fn is_spi0_ce0_n(&self) -> bool { *self == FSEL8_A::SPI0_CE0_N } - #[doc = "Checks if the value of the field is `SD0`"] + #[doc = "Pin is connected to SD0"] #[inline(always)] pub fn is_sd0(&self) -> bool { *self == FSEL8_A::SD0 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL8_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL8_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL8_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL8_A::RESERVED5 } } #[doc = "Field `FSEL8` writer - Function Select 8"] -pub type FSEL8_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL8_A, 3, O>; -impl<'a, const O: u8> FSEL8_W<'a, O> { +pub type FSEL8_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL8_A>; +impl<'a, REG, const O: u8> FSEL8_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL8_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL8_A::OUTPUT) } #[doc = "Pin is connected to SPI0_CE0_N"] #[inline(always)] - pub fn spi0_ce0_n(self) -> &'a mut W { + pub fn spi0_ce0_n(self) -> &'a mut crate::W { self.variant(FSEL8_A::SPI0_CE0_N) } #[doc = "Pin is connected to SD0"] #[inline(always)] - pub fn sd0(self) -> &'a mut W { + pub fn sd0(self) -> &'a mut crate::W { self.variant(FSEL8_A::SD0) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL8_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL8_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL8_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL8_A::RESERVED5) } } #[doc = "Field `FSEL9` reader - Function Select 9"] -pub type FSEL9_R = crate::FieldReader; +pub type FSEL9_R = crate::FieldReader; #[doc = "Function Select 9"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL9_A { + type Ux = u8; +} impl FSEL9_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL9_A { + pub const fn variant(&self) -> FSEL9_A { match self.bits { 0 => FSEL9_A::INPUT, 1 => FSEL9_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL9_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL9_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL9_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_MISO`"] + #[doc = "Pin is connected to SPI0_MISO"] #[inline(always)] pub fn is_spi0_miso(&self) -> bool { *self == FSEL9_A::SPI0_MISO } - #[doc = "Checks if the value of the field is `SD1`"] + #[doc = "Pin is connected to SD1"] #[inline(always)] pub fn is_sd1(&self) -> bool { *self == FSEL9_A::SD1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL9_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL9_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL9_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL9_A::RESERVED5 } } #[doc = "Field `FSEL9` writer - Function Select 9"] -pub type FSEL9_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL9_A, 3, O>; -impl<'a, const O: u8> FSEL9_W<'a, O> { +pub type FSEL9_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL9_A>; +impl<'a, REG, const O: u8> FSEL9_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL9_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL9_A::OUTPUT) } #[doc = "Pin is connected to SPI0_MISO"] #[inline(always)] - pub fn spi0_miso(self) -> &'a mut W { + pub fn spi0_miso(self) -> &'a mut crate::W { self.variant(FSEL9_A::SPI0_MISO) } #[doc = "Pin is connected to SD1"] #[inline(always)] - pub fn sd1(self) -> &'a mut W { + pub fn sd1(self) -> &'a mut crate::W { self.variant(FSEL9_A::SD1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL9_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL9_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL9_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL9_A::RESERVED5) } } @@ -1396,86 +1424,108 @@ impl R { FSEL9_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL0") + .field("fsel0", &format_args!("{}", self.fsel0().bits())) + .field("fsel1", &format_args!("{}", self.fsel1().bits())) + .field("fsel2", &format_args!("{}", self.fsel2().bits())) + .field("fsel3", &format_args!("{}", self.fsel3().bits())) + .field("fsel4", &format_args!("{}", self.fsel4().bits())) + .field("fsel5", &format_args!("{}", self.fsel5().bits())) + .field("fsel6", &format_args!("{}", self.fsel6().bits())) + .field("fsel7", &format_args!("{}", self.fsel7().bits())) + .field("fsel8", &format_args!("{}", self.fsel8().bits())) + .field("fsel9", &format_args!("{}", self.fsel9().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 0"] #[inline(always)] #[must_use] - pub fn fsel0(&mut self) -> FSEL0_W<0> { + pub fn fsel0(&mut self) -> FSEL0_W { FSEL0_W::new(self) } #[doc = "Bits 3:5 - Function Select 1"] #[inline(always)] #[must_use] - pub fn fsel1(&mut self) -> FSEL1_W<3> { + pub fn fsel1(&mut self) -> FSEL1_W { FSEL1_W::new(self) } #[doc = "Bits 6:8 - Function Select 2"] #[inline(always)] #[must_use] - pub fn fsel2(&mut self) -> FSEL2_W<6> { + pub fn fsel2(&mut self) -> FSEL2_W { FSEL2_W::new(self) } #[doc = "Bits 9:11 - Function Select 3"] #[inline(always)] #[must_use] - pub fn fsel3(&mut self) -> FSEL3_W<9> { + pub fn fsel3(&mut self) -> FSEL3_W { FSEL3_W::new(self) } #[doc = "Bits 12:14 - Function Select 4"] #[inline(always)] #[must_use] - pub fn fsel4(&mut self) -> FSEL4_W<12> { + pub fn fsel4(&mut self) -> FSEL4_W { FSEL4_W::new(self) } #[doc = "Bits 15:17 - Function Select 5"] #[inline(always)] #[must_use] - pub fn fsel5(&mut self) -> FSEL5_W<15> { + pub fn fsel5(&mut self) -> FSEL5_W { FSEL5_W::new(self) } #[doc = "Bits 18:20 - Function Select 6"] #[inline(always)] #[must_use] - pub fn fsel6(&mut self) -> FSEL6_W<18> { + pub fn fsel6(&mut self) -> FSEL6_W { FSEL6_W::new(self) } #[doc = "Bits 21:23 - Function Select 7"] #[inline(always)] #[must_use] - pub fn fsel7(&mut self) -> FSEL7_W<21> { + pub fn fsel7(&mut self) -> FSEL7_W { FSEL7_W::new(self) } #[doc = "Bits 24:26 - Function Select 8"] #[inline(always)] #[must_use] - pub fn fsel8(&mut self) -> FSEL8_W<24> { + pub fn fsel8(&mut self) -> FSEL8_W { FSEL8_W::new(self) } #[doc = "Bits 27:29 - Function Select 9"] #[inline(always)] #[must_use] - pub fn fsel9(&mut self) -> FSEL9_W<27> { + pub fn fsel9(&mut self) -> FSEL9_W { FSEL9_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel0](index.html) module"] +#[doc = "GPIO Function Select 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL0_SPEC; impl crate::RegisterSpec for GPFSEL0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel0::R](R) reader structure"] -impl crate::Readable for GPFSEL0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel0::R`](R) reader structure"] +impl crate::Readable for GPFSEL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel0::W`](W) writer structure"] impl crate::Writable for GPFSEL0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpfsel1.rs b/crates/bcm2835-lpa/src/gpio/gpfsel1.rs index 170dd75..acb33a1 100644 --- a/crates/bcm2835-lpa/src/gpio/gpfsel1.rs +++ b/crates/bcm2835-lpa/src/gpio/gpfsel1.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL10` reader - Function Select 10"] -pub type FSEL10_R = crate::FieldReader; +pub type FSEL10_R = crate::FieldReader; #[doc = "Function Select 10"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL10_A { + type Ux = u8; +} impl FSEL10_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL10_A { + pub const fn variant(&self) -> FSEL10_A { match self.bits { 0 => FSEL10_A::INPUT, 1 => FSEL10_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL10_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL10_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL10_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_MOSI`"] + #[doc = "Pin is connected to SPI0_MOSI"] #[inline(always)] pub fn is_spi0_mosi(&self) -> bool { *self == FSEL10_A::SPI0_MOSI } - #[doc = "Checks if the value of the field is `SD2`"] + #[doc = "Pin is connected to SD2"] #[inline(always)] pub fn is_sd2(&self) -> bool { *self == FSEL10_A::SD2 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL10_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL10_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL10_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL10_A::RESERVED5 } } #[doc = "Field `FSEL10` writer - Function Select 10"] -pub type FSEL10_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL10_A, 3, O>; -impl<'a, const O: u8> FSEL10_W<'a, O> { +pub type FSEL10_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL10_A>; +impl<'a, REG, const O: u8> FSEL10_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL10_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL10_A::OUTPUT) } #[doc = "Pin is connected to SPI0_MOSI"] #[inline(always)] - pub fn spi0_mosi(self) -> &'a mut W { + pub fn spi0_mosi(self) -> &'a mut crate::W { self.variant(FSEL10_A::SPI0_MOSI) } #[doc = "Pin is connected to SD2"] #[inline(always)] - pub fn sd2(self) -> &'a mut W { + pub fn sd2(self) -> &'a mut crate::W { self.variant(FSEL10_A::SD2) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL10_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL10_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL10_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL10_A::RESERVED5) } } #[doc = "Field `FSEL11` reader - Function Select 11"] -pub type FSEL11_R = crate::FieldReader; +pub type FSEL11_R = crate::FieldReader; #[doc = "Function Select 11"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL11_A { + type Ux = u8; +} impl FSEL11_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL11_A { + pub const fn variant(&self) -> FSEL11_A { match self.bits { 0 => FSEL11_A::INPUT, 1 => FSEL11_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL11_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL11_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL11_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_SCLK`"] + #[doc = "Pin is connected to SPI0_SCLK"] #[inline(always)] pub fn is_spi0_sclk(&self) -> bool { *self == FSEL11_A::SPI0_SCLK } - #[doc = "Checks if the value of the field is `SD3`"] + #[doc = "Pin is connected to SD3"] #[inline(always)] pub fn is_sd3(&self) -> bool { *self == FSEL11_A::SD3 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL11_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL11_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL11_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL11_A::RESERVED5 } } #[doc = "Field `FSEL11` writer - Function Select 11"] -pub type FSEL11_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL11_A, 3, O>; -impl<'a, const O: u8> FSEL11_W<'a, O> { +pub type FSEL11_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL11_A>; +impl<'a, REG, const O: u8> FSEL11_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL11_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL11_A::OUTPUT) } #[doc = "Pin is connected to SPI0_SCLK"] #[inline(always)] - pub fn spi0_sclk(self) -> &'a mut W { + pub fn spi0_sclk(self) -> &'a mut crate::W { self.variant(FSEL11_A::SPI0_SCLK) } #[doc = "Pin is connected to SD3"] #[inline(always)] - pub fn sd3(self) -> &'a mut W { + pub fn sd3(self) -> &'a mut crate::W { self.variant(FSEL11_A::SD3) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL11_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL11_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL11_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL11_A::RESERVED5) } } #[doc = "Field `FSEL12` reader - Function Select 12"] -pub type FSEL12_R = crate::FieldReader; +pub type FSEL12_R = crate::FieldReader; #[doc = "Function Select 12"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL12_A { + type Ux = u8; +} impl FSEL12_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL12_A { + pub const fn variant(&self) -> FSEL12_A { match self.bits { 0 => FSEL12_A::INPUT, 1 => FSEL12_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL12_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL12_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL12_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM0_0`"] + #[doc = "Pin is connected to PWM0_0"] #[inline(always)] pub fn is_pwm0_0(&self) -> bool { *self == FSEL12_A::PWM0_0 } - #[doc = "Checks if the value of the field is `SD4`"] + #[doc = "Pin is connected to SD4"] #[inline(always)] pub fn is_sd4(&self) -> bool { *self == FSEL12_A::SD4 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL12_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL12_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL12_A::RESERVED4 } - #[doc = "Checks if the value of the field is `ARM_TMS`"] + #[doc = "Pin is connected to ARM_TMS"] #[inline(always)] pub fn is_arm_tms(&self) -> bool { *self == FSEL12_A::ARM_TMS } } #[doc = "Field `FSEL12` writer - Function Select 12"] -pub type FSEL12_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL12_A, 3, O>; -impl<'a, const O: u8> FSEL12_W<'a, O> { +pub type FSEL12_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL12_A>; +impl<'a, REG, const O: u8> FSEL12_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL12_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL12_A::OUTPUT) } #[doc = "Pin is connected to PWM0_0"] #[inline(always)] - pub fn pwm0_0(self) -> &'a mut W { + pub fn pwm0_0(self) -> &'a mut crate::W { self.variant(FSEL12_A::PWM0_0) } #[doc = "Pin is connected to SD4"] #[inline(always)] - pub fn sd4(self) -> &'a mut W { + pub fn sd4(self) -> &'a mut crate::W { self.variant(FSEL12_A::SD4) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL12_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL12_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL12_A::RESERVED4) } #[doc = "Pin is connected to ARM_TMS"] #[inline(always)] - pub fn arm_tms(self) -> &'a mut W { + pub fn arm_tms(self) -> &'a mut crate::W { self.variant(FSEL12_A::ARM_TMS) } } #[doc = "Field `FSEL13` reader - Function Select 13"] -pub type FSEL13_R = crate::FieldReader; +pub type FSEL13_R = crate::FieldReader; #[doc = "Function Select 13"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL13_A { + type Ux = u8; +} impl FSEL13_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL13_A { + pub const fn variant(&self) -> FSEL13_A { match self.bits { 0 => FSEL13_A::INPUT, 1 => FSEL13_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL13_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL13_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL13_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM0_1`"] + #[doc = "Pin is connected to PWM0_1"] #[inline(always)] pub fn is_pwm0_1(&self) -> bool { *self == FSEL13_A::PWM0_1 } - #[doc = "Checks if the value of the field is `SD5`"] + #[doc = "Pin is connected to SD5"] #[inline(always)] pub fn is_sd5(&self) -> bool { *self == FSEL13_A::SD5 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL13_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL13_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL13_A::RESERVED4 } - #[doc = "Checks if the value of the field is `ARM_TCK`"] + #[doc = "Pin is connected to ARM_TCK"] #[inline(always)] pub fn is_arm_tck(&self) -> bool { *self == FSEL13_A::ARM_TCK } } #[doc = "Field `FSEL13` writer - Function Select 13"] -pub type FSEL13_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL13_A, 3, O>; -impl<'a, const O: u8> FSEL13_W<'a, O> { +pub type FSEL13_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL13_A>; +impl<'a, REG, const O: u8> FSEL13_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL13_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL13_A::OUTPUT) } #[doc = "Pin is connected to PWM0_1"] #[inline(always)] - pub fn pwm0_1(self) -> &'a mut W { + pub fn pwm0_1(self) -> &'a mut crate::W { self.variant(FSEL13_A::PWM0_1) } #[doc = "Pin is connected to SD5"] #[inline(always)] - pub fn sd5(self) -> &'a mut W { + pub fn sd5(self) -> &'a mut crate::W { self.variant(FSEL13_A::SD5) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL13_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL13_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL13_A::RESERVED4) } #[doc = "Pin is connected to ARM_TCK"] #[inline(always)] - pub fn arm_tck(self) -> &'a mut W { + pub fn arm_tck(self) -> &'a mut crate::W { self.variant(FSEL13_A::ARM_TCK) } } #[doc = "Field `FSEL14` reader - Function Select 14"] -pub type FSEL14_R = crate::FieldReader; +pub type FSEL14_R = crate::FieldReader; #[doc = "Function Select 14"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL14_A { + type Ux = u8; +} impl FSEL14_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL14_A { + pub const fn variant(&self) -> FSEL14_A { match self.bits { 0 => FSEL14_A::INPUT, 1 => FSEL14_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL14_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL14_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL14_A::OUTPUT } - #[doc = "Checks if the value of the field is `TXD0`"] + #[doc = "Pin is connected to TXD0"] #[inline(always)] pub fn is_txd0(&self) -> bool { *self == FSEL14_A::TXD0 } - #[doc = "Checks if the value of the field is `SD6`"] + #[doc = "Pin is connected to SD6"] #[inline(always)] pub fn is_sd6(&self) -> bool { *self == FSEL14_A::SD6 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL14_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL14_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL14_A::RESERVED4 } - #[doc = "Checks if the value of the field is `TXD1`"] + #[doc = "Pin is connected to TXD1"] #[inline(always)] pub fn is_txd1(&self) -> bool { *self == FSEL14_A::TXD1 } } #[doc = "Field `FSEL14` writer - Function Select 14"] -pub type FSEL14_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL14_A, 3, O>; -impl<'a, const O: u8> FSEL14_W<'a, O> { +pub type FSEL14_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL14_A>; +impl<'a, REG, const O: u8> FSEL14_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL14_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL14_A::OUTPUT) } #[doc = "Pin is connected to TXD0"] #[inline(always)] - pub fn txd0(self) -> &'a mut W { + pub fn txd0(self) -> &'a mut crate::W { self.variant(FSEL14_A::TXD0) } #[doc = "Pin is connected to SD6"] #[inline(always)] - pub fn sd6(self) -> &'a mut W { + pub fn sd6(self) -> &'a mut crate::W { self.variant(FSEL14_A::SD6) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL14_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL14_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL14_A::RESERVED4) } #[doc = "Pin is connected to TXD1"] #[inline(always)] - pub fn txd1(self) -> &'a mut W { + pub fn txd1(self) -> &'a mut crate::W { self.variant(FSEL14_A::TXD1) } } #[doc = "Field `FSEL15` reader - Function Select 15"] -pub type FSEL15_R = crate::FieldReader; +pub type FSEL15_R = crate::FieldReader; #[doc = "Function Select 15"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL15_A { + type Ux = u8; +} impl FSEL15_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL15_A { + pub const fn variant(&self) -> FSEL15_A { match self.bits { 0 => FSEL15_A::INPUT, 1 => FSEL15_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL15_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL15_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL15_A::OUTPUT } - #[doc = "Checks if the value of the field is `RXD0`"] + #[doc = "Pin is connected to RXD0"] #[inline(always)] pub fn is_rxd0(&self) -> bool { *self == FSEL15_A::RXD0 } - #[doc = "Checks if the value of the field is `SD7`"] + #[doc = "Pin is connected to SD7"] #[inline(always)] pub fn is_sd7(&self) -> bool { *self == FSEL15_A::SD7 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL15_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL15_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL15_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RXD1`"] + #[doc = "Pin is connected to RXD1"] #[inline(always)] pub fn is_rxd1(&self) -> bool { *self == FSEL15_A::RXD1 } } #[doc = "Field `FSEL15` writer - Function Select 15"] -pub type FSEL15_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL15_A, 3, O>; -impl<'a, const O: u8> FSEL15_W<'a, O> { +pub type FSEL15_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL15_A>; +impl<'a, REG, const O: u8> FSEL15_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL15_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL15_A::OUTPUT) } #[doc = "Pin is connected to RXD0"] #[inline(always)] - pub fn rxd0(self) -> &'a mut W { + pub fn rxd0(self) -> &'a mut crate::W { self.variant(FSEL15_A::RXD0) } #[doc = "Pin is connected to SD7"] #[inline(always)] - pub fn sd7(self) -> &'a mut W { + pub fn sd7(self) -> &'a mut crate::W { self.variant(FSEL15_A::SD7) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL15_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL15_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL15_A::RESERVED4) } #[doc = "Pin is connected to RXD1"] #[inline(always)] - pub fn rxd1(self) -> &'a mut W { + pub fn rxd1(self) -> &'a mut crate::W { self.variant(FSEL15_A::RXD1) } } #[doc = "Field `FSEL16` reader - Function Select 16"] -pub type FSEL16_R = crate::FieldReader; +pub type FSEL16_R = crate::FieldReader; #[doc = "Function Select 16"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL16_A { + type Ux = u8; +} impl FSEL16_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL16_A { + pub const fn variant(&self) -> FSEL16_A { match self.bits { 0 => FSEL16_A::INPUT, 1 => FSEL16_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL16_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL16_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL16_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL16_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD8`"] + #[doc = "Pin is connected to SD8"] #[inline(always)] pub fn is_sd8(&self) -> bool { *self == FSEL16_A::SD8 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL16_A::RESERVED2 } - #[doc = "Checks if the value of the field is `CTS0`"] + #[doc = "Pin is connected to CTS0"] #[inline(always)] pub fn is_cts0(&self) -> bool { *self == FSEL16_A::CTS0 } - #[doc = "Checks if the value of the field is `SPI1_CE2_N`"] + #[doc = "Pin is connected to SPI1_CE2_N"] #[inline(always)] pub fn is_spi1_ce2_n(&self) -> bool { *self == FSEL16_A::SPI1_CE2_N } - #[doc = "Checks if the value of the field is `CTS1`"] + #[doc = "Pin is connected to CTS1"] #[inline(always)] pub fn is_cts1(&self) -> bool { *self == FSEL16_A::CTS1 } } #[doc = "Field `FSEL16` writer - Function Select 16"] -pub type FSEL16_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL16_A, 3, O>; -impl<'a, const O: u8> FSEL16_W<'a, O> { +pub type FSEL16_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL16_A>; +impl<'a, REG, const O: u8> FSEL16_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL16_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL16_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL16_A::RESERVED0) } #[doc = "Pin is connected to SD8"] #[inline(always)] - pub fn sd8(self) -> &'a mut W { + pub fn sd8(self) -> &'a mut crate::W { self.variant(FSEL16_A::SD8) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL16_A::RESERVED2) } #[doc = "Pin is connected to CTS0"] #[inline(always)] - pub fn cts0(self) -> &'a mut W { + pub fn cts0(self) -> &'a mut crate::W { self.variant(FSEL16_A::CTS0) } #[doc = "Pin is connected to SPI1_CE2_N"] #[inline(always)] - pub fn spi1_ce2_n(self) -> &'a mut W { + pub fn spi1_ce2_n(self) -> &'a mut crate::W { self.variant(FSEL16_A::SPI1_CE2_N) } #[doc = "Pin is connected to CTS1"] #[inline(always)] - pub fn cts1(self) -> &'a mut W { + pub fn cts1(self) -> &'a mut crate::W { self.variant(FSEL16_A::CTS1) } } #[doc = "Field `FSEL17` reader - Function Select 17"] -pub type FSEL17_R = crate::FieldReader; +pub type FSEL17_R = crate::FieldReader; #[doc = "Function Select 17"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL17_A { + type Ux = u8; +} impl FSEL17_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL17_A { + pub const fn variant(&self) -> FSEL17_A { match self.bits { 0 => FSEL17_A::INPUT, 1 => FSEL17_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL17_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL17_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL17_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL17_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD9`"] + #[doc = "Pin is connected to SD9"] #[inline(always)] pub fn is_sd9(&self) -> bool { *self == FSEL17_A::SD9 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL17_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RTS0`"] + #[doc = "Pin is connected to RTS0"] #[inline(always)] pub fn is_rts0(&self) -> bool { *self == FSEL17_A::RTS0 } - #[doc = "Checks if the value of the field is `SPI1_CE1_N`"] + #[doc = "Pin is connected to SPI1_CE1_N"] #[inline(always)] pub fn is_spi1_ce1_n(&self) -> bool { *self == FSEL17_A::SPI1_CE1_N } - #[doc = "Checks if the value of the field is `RTS1`"] + #[doc = "Pin is connected to RTS1"] #[inline(always)] pub fn is_rts1(&self) -> bool { *self == FSEL17_A::RTS1 } } #[doc = "Field `FSEL17` writer - Function Select 17"] -pub type FSEL17_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL17_A, 3, O>; -impl<'a, const O: u8> FSEL17_W<'a, O> { +pub type FSEL17_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL17_A>; +impl<'a, REG, const O: u8> FSEL17_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL17_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL17_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL17_A::RESERVED0) } #[doc = "Pin is connected to SD9"] #[inline(always)] - pub fn sd9(self) -> &'a mut W { + pub fn sd9(self) -> &'a mut crate::W { self.variant(FSEL17_A::SD9) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL17_A::RESERVED2) } #[doc = "Pin is connected to RTS0"] #[inline(always)] - pub fn rts0(self) -> &'a mut W { + pub fn rts0(self) -> &'a mut crate::W { self.variant(FSEL17_A::RTS0) } #[doc = "Pin is connected to SPI1_CE1_N"] #[inline(always)] - pub fn spi1_ce1_n(self) -> &'a mut W { + pub fn spi1_ce1_n(self) -> &'a mut crate::W { self.variant(FSEL17_A::SPI1_CE1_N) } #[doc = "Pin is connected to RTS1"] #[inline(always)] - pub fn rts1(self) -> &'a mut W { + pub fn rts1(self) -> &'a mut crate::W { self.variant(FSEL17_A::RTS1) } } #[doc = "Field `FSEL18` reader - Function Select 18"] -pub type FSEL18_R = crate::FieldReader; +pub type FSEL18_R = crate::FieldReader; #[doc = "Function Select 18"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL18_A { + type Ux = u8; +} impl FSEL18_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL18_A { + pub const fn variant(&self) -> FSEL18_A { match self.bits { 0 => FSEL18_A::INPUT, 1 => FSEL18_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL18_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL18_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL18_A::OUTPUT } - #[doc = "Checks if the value of the field is `PCM_CLK`"] + #[doc = "Pin is connected to PCM_CLK"] #[inline(always)] pub fn is_pcm_clk(&self) -> bool { *self == FSEL18_A::PCM_CLK } - #[doc = "Checks if the value of the field is `SD10`"] + #[doc = "Pin is connected to SD10"] #[inline(always)] pub fn is_sd10(&self) -> bool { *self == FSEL18_A::SD10 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL18_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL18_A::RESERVED3 } - #[doc = "Checks if the value of the field is `SPI1_CE0_N`"] + #[doc = "Pin is connected to SPI1_CE0_N"] #[inline(always)] pub fn is_spi1_ce0_n(&self) -> bool { *self == FSEL18_A::SPI1_CE0_N } - #[doc = "Checks if the value of the field is `PWM0_0`"] + #[doc = "Pin is connected to PWM0_0"] #[inline(always)] pub fn is_pwm0_0(&self) -> bool { *self == FSEL18_A::PWM0_0 } } #[doc = "Field `FSEL18` writer - Function Select 18"] -pub type FSEL18_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL18_A, 3, O>; -impl<'a, const O: u8> FSEL18_W<'a, O> { +pub type FSEL18_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL18_A>; +impl<'a, REG, const O: u8> FSEL18_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL18_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL18_A::OUTPUT) } #[doc = "Pin is connected to PCM_CLK"] #[inline(always)] - pub fn pcm_clk(self) -> &'a mut W { + pub fn pcm_clk(self) -> &'a mut crate::W { self.variant(FSEL18_A::PCM_CLK) } #[doc = "Pin is connected to SD10"] #[inline(always)] - pub fn sd10(self) -> &'a mut W { + pub fn sd10(self) -> &'a mut crate::W { self.variant(FSEL18_A::SD10) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL18_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL18_A::RESERVED3) } #[doc = "Pin is connected to SPI1_CE0_N"] #[inline(always)] - pub fn spi1_ce0_n(self) -> &'a mut W { + pub fn spi1_ce0_n(self) -> &'a mut crate::W { self.variant(FSEL18_A::SPI1_CE0_N) } #[doc = "Pin is connected to PWM0_0"] #[inline(always)] - pub fn pwm0_0(self) -> &'a mut W { + pub fn pwm0_0(self) -> &'a mut crate::W { self.variant(FSEL18_A::PWM0_0) } } #[doc = "Field `FSEL19` reader - Function Select 19"] -pub type FSEL19_R = crate::FieldReader; +pub type FSEL19_R = crate::FieldReader; #[doc = "Function Select 19"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL19_A { + type Ux = u8; +} impl FSEL19_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL19_A { + pub const fn variant(&self) -> FSEL19_A { match self.bits { 0 => FSEL19_A::INPUT, 1 => FSEL19_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL19_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL19_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL19_A::OUTPUT } - #[doc = "Checks if the value of the field is `PCM_FS`"] + #[doc = "Pin is connected to PCM_FS"] #[inline(always)] pub fn is_pcm_fs(&self) -> bool { *self == FSEL19_A::PCM_FS } - #[doc = "Checks if the value of the field is `SD11`"] + #[doc = "Pin is connected to SD11"] #[inline(always)] pub fn is_sd11(&self) -> bool { *self == FSEL19_A::SD11 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL19_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL19_A::RESERVED3 } - #[doc = "Checks if the value of the field is `SPI1_MISO`"] + #[doc = "Pin is connected to SPI1_MISO"] #[inline(always)] pub fn is_spi1_miso(&self) -> bool { *self == FSEL19_A::SPI1_MISO } - #[doc = "Checks if the value of the field is `PWM0_1`"] + #[doc = "Pin is connected to PWM0_1"] #[inline(always)] pub fn is_pwm0_1(&self) -> bool { *self == FSEL19_A::PWM0_1 } } #[doc = "Field `FSEL19` writer - Function Select 19"] -pub type FSEL19_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL19_A, 3, O>; -impl<'a, const O: u8> FSEL19_W<'a, O> { +pub type FSEL19_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL19_A>; +impl<'a, REG, const O: u8> FSEL19_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL19_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL19_A::OUTPUT) } #[doc = "Pin is connected to PCM_FS"] #[inline(always)] - pub fn pcm_fs(self) -> &'a mut W { + pub fn pcm_fs(self) -> &'a mut crate::W { self.variant(FSEL19_A::PCM_FS) } #[doc = "Pin is connected to SD11"] #[inline(always)] - pub fn sd11(self) -> &'a mut W { + pub fn sd11(self) -> &'a mut crate::W { self.variant(FSEL19_A::SD11) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL19_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL19_A::RESERVED3) } #[doc = "Pin is connected to SPI1_MISO"] #[inline(always)] - pub fn spi1_miso(self) -> &'a mut W { + pub fn spi1_miso(self) -> &'a mut crate::W { self.variant(FSEL19_A::SPI1_MISO) } #[doc = "Pin is connected to PWM0_1"] #[inline(always)] - pub fn pwm0_1(self) -> &'a mut W { + pub fn pwm0_1(self) -> &'a mut crate::W { self.variant(FSEL19_A::PWM0_1) } } @@ -1396,86 +1424,108 @@ impl R { FSEL19_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL1") + .field("fsel10", &format_args!("{}", self.fsel10().bits())) + .field("fsel11", &format_args!("{}", self.fsel11().bits())) + .field("fsel12", &format_args!("{}", self.fsel12().bits())) + .field("fsel13", &format_args!("{}", self.fsel13().bits())) + .field("fsel14", &format_args!("{}", self.fsel14().bits())) + .field("fsel15", &format_args!("{}", self.fsel15().bits())) + .field("fsel16", &format_args!("{}", self.fsel16().bits())) + .field("fsel17", &format_args!("{}", self.fsel17().bits())) + .field("fsel18", &format_args!("{}", self.fsel18().bits())) + .field("fsel19", &format_args!("{}", self.fsel19().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 10"] #[inline(always)] #[must_use] - pub fn fsel10(&mut self) -> FSEL10_W<0> { + pub fn fsel10(&mut self) -> FSEL10_W { FSEL10_W::new(self) } #[doc = "Bits 3:5 - Function Select 11"] #[inline(always)] #[must_use] - pub fn fsel11(&mut self) -> FSEL11_W<3> { + pub fn fsel11(&mut self) -> FSEL11_W { FSEL11_W::new(self) } #[doc = "Bits 6:8 - Function Select 12"] #[inline(always)] #[must_use] - pub fn fsel12(&mut self) -> FSEL12_W<6> { + pub fn fsel12(&mut self) -> FSEL12_W { FSEL12_W::new(self) } #[doc = "Bits 9:11 - Function Select 13"] #[inline(always)] #[must_use] - pub fn fsel13(&mut self) -> FSEL13_W<9> { + pub fn fsel13(&mut self) -> FSEL13_W { FSEL13_W::new(self) } #[doc = "Bits 12:14 - Function Select 14"] #[inline(always)] #[must_use] - pub fn fsel14(&mut self) -> FSEL14_W<12> { + pub fn fsel14(&mut self) -> FSEL14_W { FSEL14_W::new(self) } #[doc = "Bits 15:17 - Function Select 15"] #[inline(always)] #[must_use] - pub fn fsel15(&mut self) -> FSEL15_W<15> { + pub fn fsel15(&mut self) -> FSEL15_W { FSEL15_W::new(self) } #[doc = "Bits 18:20 - Function Select 16"] #[inline(always)] #[must_use] - pub fn fsel16(&mut self) -> FSEL16_W<18> { + pub fn fsel16(&mut self) -> FSEL16_W { FSEL16_W::new(self) } #[doc = "Bits 21:23 - Function Select 17"] #[inline(always)] #[must_use] - pub fn fsel17(&mut self) -> FSEL17_W<21> { + pub fn fsel17(&mut self) -> FSEL17_W { FSEL17_W::new(self) } #[doc = "Bits 24:26 - Function Select 18"] #[inline(always)] #[must_use] - pub fn fsel18(&mut self) -> FSEL18_W<24> { + pub fn fsel18(&mut self) -> FSEL18_W { FSEL18_W::new(self) } #[doc = "Bits 27:29 - Function Select 19"] #[inline(always)] #[must_use] - pub fn fsel19(&mut self) -> FSEL19_W<27> { + pub fn fsel19(&mut self) -> FSEL19_W { FSEL19_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel1](index.html) module"] +#[doc = "GPIO Function Select 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL1_SPEC; impl crate::RegisterSpec for GPFSEL1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel1::R](R) reader structure"] -impl crate::Readable for GPFSEL1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel1::R`](R) reader structure"] +impl crate::Readable for GPFSEL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel1::W`](W) writer structure"] impl crate::Writable for GPFSEL1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpfsel2.rs b/crates/bcm2835-lpa/src/gpio/gpfsel2.rs index 8bc92dc..5704f8e 100644 --- a/crates/bcm2835-lpa/src/gpio/gpfsel2.rs +++ b/crates/bcm2835-lpa/src/gpio/gpfsel2.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL20` reader - Function Select 20"] -pub type FSEL20_R = crate::FieldReader; +pub type FSEL20_R = crate::FieldReader; #[doc = "Function Select 20"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL20_A { + type Ux = u8; +} impl FSEL20_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL20_A { + pub const fn variant(&self) -> FSEL20_A { match self.bits { 0 => FSEL20_A::INPUT, 1 => FSEL20_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL20_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL20_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL20_A::OUTPUT } - #[doc = "Checks if the value of the field is `PCM_DIN`"] + #[doc = "Pin is connected to PCM_DIN"] #[inline(always)] pub fn is_pcm_din(&self) -> bool { *self == FSEL20_A::PCM_DIN } - #[doc = "Checks if the value of the field is `SD12`"] + #[doc = "Pin is connected to SD12"] #[inline(always)] pub fn is_sd12(&self) -> bool { *self == FSEL20_A::SD12 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL20_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL20_A::RESERVED3 } - #[doc = "Checks if the value of the field is `SPI1_MOSI`"] + #[doc = "Pin is connected to SPI1_MOSI"] #[inline(always)] pub fn is_spi1_mosi(&self) -> bool { *self == FSEL20_A::SPI1_MOSI } - #[doc = "Checks if the value of the field is `GPCLK0`"] + #[doc = "Pin is connected to GPCLK0"] #[inline(always)] pub fn is_gpclk0(&self) -> bool { *self == FSEL20_A::GPCLK0 } } #[doc = "Field `FSEL20` writer - Function Select 20"] -pub type FSEL20_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL20_A, 3, O>; -impl<'a, const O: u8> FSEL20_W<'a, O> { +pub type FSEL20_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL20_A>; +impl<'a, REG, const O: u8> FSEL20_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL20_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL20_A::OUTPUT) } #[doc = "Pin is connected to PCM_DIN"] #[inline(always)] - pub fn pcm_din(self) -> &'a mut W { + pub fn pcm_din(self) -> &'a mut crate::W { self.variant(FSEL20_A::PCM_DIN) } #[doc = "Pin is connected to SD12"] #[inline(always)] - pub fn sd12(self) -> &'a mut W { + pub fn sd12(self) -> &'a mut crate::W { self.variant(FSEL20_A::SD12) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL20_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL20_A::RESERVED3) } #[doc = "Pin is connected to SPI1_MOSI"] #[inline(always)] - pub fn spi1_mosi(self) -> &'a mut W { + pub fn spi1_mosi(self) -> &'a mut crate::W { self.variant(FSEL20_A::SPI1_MOSI) } #[doc = "Pin is connected to GPCLK0"] #[inline(always)] - pub fn gpclk0(self) -> &'a mut W { + pub fn gpclk0(self) -> &'a mut crate::W { self.variant(FSEL20_A::GPCLK0) } } #[doc = "Field `FSEL21` reader - Function Select 21"] -pub type FSEL21_R = crate::FieldReader; +pub type FSEL21_R = crate::FieldReader; #[doc = "Function Select 21"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL21_A { + type Ux = u8; +} impl FSEL21_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL21_A { + pub const fn variant(&self) -> FSEL21_A { match self.bits { 0 => FSEL21_A::INPUT, 1 => FSEL21_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL21_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL21_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL21_A::OUTPUT } - #[doc = "Checks if the value of the field is `PCM_DOUT`"] + #[doc = "Pin is connected to PCM_DOUT"] #[inline(always)] pub fn is_pcm_dout(&self) -> bool { *self == FSEL21_A::PCM_DOUT } - #[doc = "Checks if the value of the field is `SD13`"] + #[doc = "Pin is connected to SD13"] #[inline(always)] pub fn is_sd13(&self) -> bool { *self == FSEL21_A::SD13 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL21_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL21_A::RESERVED3 } - #[doc = "Checks if the value of the field is `SPI1_SCLK`"] + #[doc = "Pin is connected to SPI1_SCLK"] #[inline(always)] pub fn is_spi1_sclk(&self) -> bool { *self == FSEL21_A::SPI1_SCLK } - #[doc = "Checks if the value of the field is `GPCLK1`"] + #[doc = "Pin is connected to GPCLK1"] #[inline(always)] pub fn is_gpclk1(&self) -> bool { *self == FSEL21_A::GPCLK1 } } #[doc = "Field `FSEL21` writer - Function Select 21"] -pub type FSEL21_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL21_A, 3, O>; -impl<'a, const O: u8> FSEL21_W<'a, O> { +pub type FSEL21_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL21_A>; +impl<'a, REG, const O: u8> FSEL21_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL21_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL21_A::OUTPUT) } #[doc = "Pin is connected to PCM_DOUT"] #[inline(always)] - pub fn pcm_dout(self) -> &'a mut W { + pub fn pcm_dout(self) -> &'a mut crate::W { self.variant(FSEL21_A::PCM_DOUT) } #[doc = "Pin is connected to SD13"] #[inline(always)] - pub fn sd13(self) -> &'a mut W { + pub fn sd13(self) -> &'a mut crate::W { self.variant(FSEL21_A::SD13) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL21_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL21_A::RESERVED3) } #[doc = "Pin is connected to SPI1_SCLK"] #[inline(always)] - pub fn spi1_sclk(self) -> &'a mut W { + pub fn spi1_sclk(self) -> &'a mut crate::W { self.variant(FSEL21_A::SPI1_SCLK) } #[doc = "Pin is connected to GPCLK1"] #[inline(always)] - pub fn gpclk1(self) -> &'a mut W { + pub fn gpclk1(self) -> &'a mut crate::W { self.variant(FSEL21_A::GPCLK1) } } #[doc = "Field `FSEL22` reader - Function Select 22"] -pub type FSEL22_R = crate::FieldReader; +pub type FSEL22_R = crate::FieldReader; #[doc = "Function Select 22"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL22_A { + type Ux = u8; +} impl FSEL22_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL22_A { + pub const fn variant(&self) -> FSEL22_A { match self.bits { 0 => FSEL22_A::INPUT, 1 => FSEL22_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL22_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL22_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL22_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL22_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD14`"] + #[doc = "Pin is connected to SD14"] #[inline(always)] pub fn is_sd14(&self) -> bool { *self == FSEL22_A::SD14 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL22_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] pub fn is_sd1_clk(&self) -> bool { *self == FSEL22_A::SD1_CLK } - #[doc = "Checks if the value of the field is `ARM_TRST`"] + #[doc = "Pin is connected to ARM_TRST"] #[inline(always)] pub fn is_arm_trst(&self) -> bool { *self == FSEL22_A::ARM_TRST } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL22_A::RESERVED5 } } #[doc = "Field `FSEL22` writer - Function Select 22"] -pub type FSEL22_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL22_A, 3, O>; -impl<'a, const O: u8> FSEL22_W<'a, O> { +pub type FSEL22_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL22_A>; +impl<'a, REG, const O: u8> FSEL22_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL22_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL22_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL22_A::RESERVED0) } #[doc = "Pin is connected to SD14"] #[inline(always)] - pub fn sd14(self) -> &'a mut W { + pub fn sd14(self) -> &'a mut crate::W { self.variant(FSEL22_A::SD14) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL22_A::RESERVED2) } #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] - pub fn sd1_clk(self) -> &'a mut W { + pub fn sd1_clk(self) -> &'a mut crate::W { self.variant(FSEL22_A::SD1_CLK) } #[doc = "Pin is connected to ARM_TRST"] #[inline(always)] - pub fn arm_trst(self) -> &'a mut W { + pub fn arm_trst(self) -> &'a mut crate::W { self.variant(FSEL22_A::ARM_TRST) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL22_A::RESERVED5) } } #[doc = "Field `FSEL23` reader - Function Select 23"] -pub type FSEL23_R = crate::FieldReader; +pub type FSEL23_R = crate::FieldReader; #[doc = "Function Select 23"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL23_A { + type Ux = u8; +} impl FSEL23_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL23_A { + pub const fn variant(&self) -> FSEL23_A { match self.bits { 0 => FSEL23_A::INPUT, 1 => FSEL23_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL23_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL23_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL23_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL23_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD15`"] + #[doc = "Pin is connected to SD15"] #[inline(always)] pub fn is_sd15(&self) -> bool { *self == FSEL23_A::SD15 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL23_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] pub fn is_sd1_cmd(&self) -> bool { *self == FSEL23_A::SD1_CMD } - #[doc = "Checks if the value of the field is `ARM_RTCK`"] + #[doc = "Pin is connected to ARM_RTCK"] #[inline(always)] pub fn is_arm_rtck(&self) -> bool { *self == FSEL23_A::ARM_RTCK } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL23_A::RESERVED5 } } #[doc = "Field `FSEL23` writer - Function Select 23"] -pub type FSEL23_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL23_A, 3, O>; -impl<'a, const O: u8> FSEL23_W<'a, O> { +pub type FSEL23_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL23_A>; +impl<'a, REG, const O: u8> FSEL23_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL23_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL23_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL23_A::RESERVED0) } #[doc = "Pin is connected to SD15"] #[inline(always)] - pub fn sd15(self) -> &'a mut W { + pub fn sd15(self) -> &'a mut crate::W { self.variant(FSEL23_A::SD15) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL23_A::RESERVED2) } #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] - pub fn sd1_cmd(self) -> &'a mut W { + pub fn sd1_cmd(self) -> &'a mut crate::W { self.variant(FSEL23_A::SD1_CMD) } #[doc = "Pin is connected to ARM_RTCK"] #[inline(always)] - pub fn arm_rtck(self) -> &'a mut W { + pub fn arm_rtck(self) -> &'a mut crate::W { self.variant(FSEL23_A::ARM_RTCK) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL23_A::RESERVED5) } } #[doc = "Field `FSEL24` reader - Function Select 24"] -pub type FSEL24_R = crate::FieldReader; +pub type FSEL24_R = crate::FieldReader; #[doc = "Function Select 24"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL24_A { + type Ux = u8; +} impl FSEL24_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL24_A { + pub const fn variant(&self) -> FSEL24_A { match self.bits { 0 => FSEL24_A::INPUT, 1 => FSEL24_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL24_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL24_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL24_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL24_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD16`"] + #[doc = "Pin is connected to SD16"] #[inline(always)] pub fn is_sd16(&self) -> bool { *self == FSEL24_A::SD16 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL24_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] pub fn is_sd1_dat0(&self) -> bool { *self == FSEL24_A::SD1_DAT0 } - #[doc = "Checks if the value of the field is `ARM_TDO`"] + #[doc = "Pin is connected to ARM_TDO"] #[inline(always)] pub fn is_arm_tdo(&self) -> bool { *self == FSEL24_A::ARM_TDO } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL24_A::RESERVED5 } } #[doc = "Field `FSEL24` writer - Function Select 24"] -pub type FSEL24_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL24_A, 3, O>; -impl<'a, const O: u8> FSEL24_W<'a, O> { +pub type FSEL24_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL24_A>; +impl<'a, REG, const O: u8> FSEL24_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL24_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL24_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL24_A::RESERVED0) } #[doc = "Pin is connected to SD16"] #[inline(always)] - pub fn sd16(self) -> &'a mut W { + pub fn sd16(self) -> &'a mut crate::W { self.variant(FSEL24_A::SD16) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL24_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] - pub fn sd1_dat0(self) -> &'a mut W { + pub fn sd1_dat0(self) -> &'a mut crate::W { self.variant(FSEL24_A::SD1_DAT0) } #[doc = "Pin is connected to ARM_TDO"] #[inline(always)] - pub fn arm_tdo(self) -> &'a mut W { + pub fn arm_tdo(self) -> &'a mut crate::W { self.variant(FSEL24_A::ARM_TDO) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL24_A::RESERVED5) } } #[doc = "Field `FSEL25` reader - Function Select 25"] -pub type FSEL25_R = crate::FieldReader; +pub type FSEL25_R = crate::FieldReader; #[doc = "Function Select 25"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL25_A { + type Ux = u8; +} impl FSEL25_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL25_A { + pub const fn variant(&self) -> FSEL25_A { match self.bits { 0 => FSEL25_A::INPUT, 1 => FSEL25_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL25_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL25_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL25_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL25_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD17`"] + #[doc = "Pin is connected to SD17"] #[inline(always)] pub fn is_sd17(&self) -> bool { *self == FSEL25_A::SD17 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL25_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] pub fn is_sd1_dat1(&self) -> bool { *self == FSEL25_A::SD1_DAT1 } - #[doc = "Checks if the value of the field is `ARM_TCK`"] + #[doc = "Pin is connected to ARM_TCK"] #[inline(always)] pub fn is_arm_tck(&self) -> bool { *self == FSEL25_A::ARM_TCK } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL25_A::RESERVED5 } } #[doc = "Field `FSEL25` writer - Function Select 25"] -pub type FSEL25_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL25_A, 3, O>; -impl<'a, const O: u8> FSEL25_W<'a, O> { +pub type FSEL25_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL25_A>; +impl<'a, REG, const O: u8> FSEL25_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL25_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL25_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL25_A::RESERVED0) } #[doc = "Pin is connected to SD17"] #[inline(always)] - pub fn sd17(self) -> &'a mut W { + pub fn sd17(self) -> &'a mut crate::W { self.variant(FSEL25_A::SD17) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL25_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] - pub fn sd1_dat1(self) -> &'a mut W { + pub fn sd1_dat1(self) -> &'a mut crate::W { self.variant(FSEL25_A::SD1_DAT1) } #[doc = "Pin is connected to ARM_TCK"] #[inline(always)] - pub fn arm_tck(self) -> &'a mut W { + pub fn arm_tck(self) -> &'a mut crate::W { self.variant(FSEL25_A::ARM_TCK) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL25_A::RESERVED5) } } #[doc = "Field `FSEL26` reader - Function Select 26"] -pub type FSEL26_R = crate::FieldReader; +pub type FSEL26_R = crate::FieldReader; #[doc = "Function Select 26"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL26_A { + type Ux = u8; +} impl FSEL26_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL26_A { + pub const fn variant(&self) -> FSEL26_A { match self.bits { 0 => FSEL26_A::INPUT, 1 => FSEL26_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL26_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL26_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL26_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL26_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL26_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL26_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] pub fn is_sd1_dat2(&self) -> bool { *self == FSEL26_A::SD1_DAT2 } - #[doc = "Checks if the value of the field is `ARM_TDI`"] + #[doc = "Pin is connected to ARM_TDI"] #[inline(always)] pub fn is_arm_tdi(&self) -> bool { *self == FSEL26_A::ARM_TDI } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL26_A::RESERVED5 } } #[doc = "Field `FSEL26` writer - Function Select 26"] -pub type FSEL26_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL26_A, 3, O>; -impl<'a, const O: u8> FSEL26_W<'a, O> { +pub type FSEL26_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL26_A>; +impl<'a, REG, const O: u8> FSEL26_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL26_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL26_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL26_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL26_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL26_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] - pub fn sd1_dat2(self) -> &'a mut W { + pub fn sd1_dat2(self) -> &'a mut crate::W { self.variant(FSEL26_A::SD1_DAT2) } #[doc = "Pin is connected to ARM_TDI"] #[inline(always)] - pub fn arm_tdi(self) -> &'a mut W { + pub fn arm_tdi(self) -> &'a mut crate::W { self.variant(FSEL26_A::ARM_TDI) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL26_A::RESERVED5) } } #[doc = "Field `FSEL27` reader - Function Select 27"] -pub type FSEL27_R = crate::FieldReader; +pub type FSEL27_R = crate::FieldReader; #[doc = "Function Select 27"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL27_A { + type Ux = u8; +} impl FSEL27_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL27_A { + pub const fn variant(&self) -> FSEL27_A { match self.bits { 0 => FSEL27_A::INPUT, 1 => FSEL27_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL27_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL27_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL27_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL27_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL27_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL27_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] pub fn is_sd1_dat3(&self) -> bool { *self == FSEL27_A::SD1_DAT3 } - #[doc = "Checks if the value of the field is `ARM_TMS`"] + #[doc = "Pin is connected to ARM_TMS"] #[inline(always)] pub fn is_arm_tms(&self) -> bool { *self == FSEL27_A::ARM_TMS } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL27_A::RESERVED5 } } #[doc = "Field `FSEL27` writer - Function Select 27"] -pub type FSEL27_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL27_A, 3, O>; -impl<'a, const O: u8> FSEL27_W<'a, O> { +pub type FSEL27_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL27_A>; +impl<'a, REG, const O: u8> FSEL27_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL27_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL27_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL27_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL27_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL27_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] - pub fn sd1_dat3(self) -> &'a mut W { + pub fn sd1_dat3(self) -> &'a mut crate::W { self.variant(FSEL27_A::SD1_DAT3) } #[doc = "Pin is connected to ARM_TMS"] #[inline(always)] - pub fn arm_tms(self) -> &'a mut W { + pub fn arm_tms(self) -> &'a mut crate::W { self.variant(FSEL27_A::ARM_TMS) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL27_A::RESERVED5) } } #[doc = "Field `FSEL28` reader - Function Select 28"] -pub type FSEL28_R = crate::FieldReader; +pub type FSEL28_R = crate::FieldReader; #[doc = "Function Select 28"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL28_A { + type Ux = u8; +} impl FSEL28_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL28_A { + pub const fn variant(&self) -> FSEL28_A { match self.bits { 0 => FSEL28_A::INPUT, 1 => FSEL28_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL28_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL28_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL28_A::OUTPUT } - #[doc = "Checks if the value of the field is `SDA0`"] + #[doc = "Pin is connected to SDA0"] #[inline(always)] pub fn is_sda0(&self) -> bool { *self == FSEL28_A::SDA0 } - #[doc = "Checks if the value of the field is `SA5`"] + #[doc = "Pin is connected to SA5"] #[inline(always)] pub fn is_sa5(&self) -> bool { *self == FSEL28_A::SA5 } - #[doc = "Checks if the value of the field is `PCM_CLK`"] + #[doc = "Pin is connected to PCM_CLK"] #[inline(always)] pub fn is_pcm_clk(&self) -> bool { *self == FSEL28_A::PCM_CLK } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL28_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL28_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL28_A::RESERVED5 } } #[doc = "Field `FSEL28` writer - Function Select 28"] -pub type FSEL28_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL28_A, 3, O>; -impl<'a, const O: u8> FSEL28_W<'a, O> { +pub type FSEL28_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL28_A>; +impl<'a, REG, const O: u8> FSEL28_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL28_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL28_A::OUTPUT) } #[doc = "Pin is connected to SDA0"] #[inline(always)] - pub fn sda0(self) -> &'a mut W { + pub fn sda0(self) -> &'a mut crate::W { self.variant(FSEL28_A::SDA0) } #[doc = "Pin is connected to SA5"] #[inline(always)] - pub fn sa5(self) -> &'a mut W { + pub fn sa5(self) -> &'a mut crate::W { self.variant(FSEL28_A::SA5) } #[doc = "Pin is connected to PCM_CLK"] #[inline(always)] - pub fn pcm_clk(self) -> &'a mut W { + pub fn pcm_clk(self) -> &'a mut crate::W { self.variant(FSEL28_A::PCM_CLK) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL28_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL28_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL28_A::RESERVED5) } } #[doc = "Field `FSEL29` reader - Function Select 29"] -pub type FSEL29_R = crate::FieldReader; +pub type FSEL29_R = crate::FieldReader; #[doc = "Function Select 29"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL29_A { + type Ux = u8; +} impl FSEL29_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL29_A { + pub const fn variant(&self) -> FSEL29_A { match self.bits { 0 => FSEL29_A::INPUT, 1 => FSEL29_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL29_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL29_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL29_A::OUTPUT } - #[doc = "Checks if the value of the field is `SCL0`"] + #[doc = "Pin is connected to SCL0"] #[inline(always)] pub fn is_scl0(&self) -> bool { *self == FSEL29_A::SCL0 } - #[doc = "Checks if the value of the field is `SA4`"] + #[doc = "Pin is connected to SA4"] #[inline(always)] pub fn is_sa4(&self) -> bool { *self == FSEL29_A::SA4 } - #[doc = "Checks if the value of the field is `PCM_FS`"] + #[doc = "Pin is connected to PCM_FS"] #[inline(always)] pub fn is_pcm_fs(&self) -> bool { *self == FSEL29_A::PCM_FS } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL29_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL29_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL29_A::RESERVED5 } } #[doc = "Field `FSEL29` writer - Function Select 29"] -pub type FSEL29_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL29_A, 3, O>; -impl<'a, const O: u8> FSEL29_W<'a, O> { +pub type FSEL29_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL29_A>; +impl<'a, REG, const O: u8> FSEL29_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL29_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL29_A::OUTPUT) } #[doc = "Pin is connected to SCL0"] #[inline(always)] - pub fn scl0(self) -> &'a mut W { + pub fn scl0(self) -> &'a mut crate::W { self.variant(FSEL29_A::SCL0) } #[doc = "Pin is connected to SA4"] #[inline(always)] - pub fn sa4(self) -> &'a mut W { + pub fn sa4(self) -> &'a mut crate::W { self.variant(FSEL29_A::SA4) } #[doc = "Pin is connected to PCM_FS"] #[inline(always)] - pub fn pcm_fs(self) -> &'a mut W { + pub fn pcm_fs(self) -> &'a mut crate::W { self.variant(FSEL29_A::PCM_FS) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL29_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL29_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL29_A::RESERVED5) } } @@ -1396,86 +1424,108 @@ impl R { FSEL29_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL2") + .field("fsel20", &format_args!("{}", self.fsel20().bits())) + .field("fsel21", &format_args!("{}", self.fsel21().bits())) + .field("fsel22", &format_args!("{}", self.fsel22().bits())) + .field("fsel23", &format_args!("{}", self.fsel23().bits())) + .field("fsel24", &format_args!("{}", self.fsel24().bits())) + .field("fsel25", &format_args!("{}", self.fsel25().bits())) + .field("fsel26", &format_args!("{}", self.fsel26().bits())) + .field("fsel27", &format_args!("{}", self.fsel27().bits())) + .field("fsel28", &format_args!("{}", self.fsel28().bits())) + .field("fsel29", &format_args!("{}", self.fsel29().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 20"] #[inline(always)] #[must_use] - pub fn fsel20(&mut self) -> FSEL20_W<0> { + pub fn fsel20(&mut self) -> FSEL20_W { FSEL20_W::new(self) } #[doc = "Bits 3:5 - Function Select 21"] #[inline(always)] #[must_use] - pub fn fsel21(&mut self) -> FSEL21_W<3> { + pub fn fsel21(&mut self) -> FSEL21_W { FSEL21_W::new(self) } #[doc = "Bits 6:8 - Function Select 22"] #[inline(always)] #[must_use] - pub fn fsel22(&mut self) -> FSEL22_W<6> { + pub fn fsel22(&mut self) -> FSEL22_W { FSEL22_W::new(self) } #[doc = "Bits 9:11 - Function Select 23"] #[inline(always)] #[must_use] - pub fn fsel23(&mut self) -> FSEL23_W<9> { + pub fn fsel23(&mut self) -> FSEL23_W { FSEL23_W::new(self) } #[doc = "Bits 12:14 - Function Select 24"] #[inline(always)] #[must_use] - pub fn fsel24(&mut self) -> FSEL24_W<12> { + pub fn fsel24(&mut self) -> FSEL24_W { FSEL24_W::new(self) } #[doc = "Bits 15:17 - Function Select 25"] #[inline(always)] #[must_use] - pub fn fsel25(&mut self) -> FSEL25_W<15> { + pub fn fsel25(&mut self) -> FSEL25_W { FSEL25_W::new(self) } #[doc = "Bits 18:20 - Function Select 26"] #[inline(always)] #[must_use] - pub fn fsel26(&mut self) -> FSEL26_W<18> { + pub fn fsel26(&mut self) -> FSEL26_W { FSEL26_W::new(self) } #[doc = "Bits 21:23 - Function Select 27"] #[inline(always)] #[must_use] - pub fn fsel27(&mut self) -> FSEL27_W<21> { + pub fn fsel27(&mut self) -> FSEL27_W { FSEL27_W::new(self) } #[doc = "Bits 24:26 - Function Select 28"] #[inline(always)] #[must_use] - pub fn fsel28(&mut self) -> FSEL28_W<24> { + pub fn fsel28(&mut self) -> FSEL28_W { FSEL28_W::new(self) } #[doc = "Bits 27:29 - Function Select 29"] #[inline(always)] #[must_use] - pub fn fsel29(&mut self) -> FSEL29_W<27> { + pub fn fsel29(&mut self) -> FSEL29_W { FSEL29_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel2](index.html) module"] +#[doc = "GPIO Function Select 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL2_SPEC; impl crate::RegisterSpec for GPFSEL2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel2::R](R) reader structure"] -impl crate::Readable for GPFSEL2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel2::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel2::R`](R) reader structure"] +impl crate::Readable for GPFSEL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel2::W`](W) writer structure"] impl crate::Writable for GPFSEL2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpfsel3.rs b/crates/bcm2835-lpa/src/gpio/gpfsel3.rs index d3f9c4f..ce2ef3a 100644 --- a/crates/bcm2835-lpa/src/gpio/gpfsel3.rs +++ b/crates/bcm2835-lpa/src/gpio/gpfsel3.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL30` reader - Function Select 30"] -pub type FSEL30_R = crate::FieldReader; +pub type FSEL30_R = crate::FieldReader; #[doc = "Function Select 30"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL30_A { + type Ux = u8; +} impl FSEL30_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL30_A { + pub const fn variant(&self) -> FSEL30_A { match self.bits { 0 => FSEL30_A::INPUT, 1 => FSEL30_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL30_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL30_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL30_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL30_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SA3`"] + #[doc = "Pin is connected to SA3"] #[inline(always)] pub fn is_sa3(&self) -> bool { *self == FSEL30_A::SA3 } - #[doc = "Checks if the value of the field is `PCM_DIN`"] + #[doc = "Pin is connected to PCM_DIN"] #[inline(always)] pub fn is_pcm_din(&self) -> bool { *self == FSEL30_A::PCM_DIN } - #[doc = "Checks if the value of the field is `CTS0`"] + #[doc = "Pin is connected to CTS0"] #[inline(always)] pub fn is_cts0(&self) -> bool { *self == FSEL30_A::CTS0 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL30_A::RESERVED4 } - #[doc = "Checks if the value of the field is `CTS1`"] + #[doc = "Pin is connected to CTS1"] #[inline(always)] pub fn is_cts1(&self) -> bool { *self == FSEL30_A::CTS1 } } #[doc = "Field `FSEL30` writer - Function Select 30"] -pub type FSEL30_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL30_A, 3, O>; -impl<'a, const O: u8> FSEL30_W<'a, O> { +pub type FSEL30_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL30_A>; +impl<'a, REG, const O: u8> FSEL30_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL30_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL30_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL30_A::RESERVED0) } #[doc = "Pin is connected to SA3"] #[inline(always)] - pub fn sa3(self) -> &'a mut W { + pub fn sa3(self) -> &'a mut crate::W { self.variant(FSEL30_A::SA3) } #[doc = "Pin is connected to PCM_DIN"] #[inline(always)] - pub fn pcm_din(self) -> &'a mut W { + pub fn pcm_din(self) -> &'a mut crate::W { self.variant(FSEL30_A::PCM_DIN) } #[doc = "Pin is connected to CTS0"] #[inline(always)] - pub fn cts0(self) -> &'a mut W { + pub fn cts0(self) -> &'a mut crate::W { self.variant(FSEL30_A::CTS0) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL30_A::RESERVED4) } #[doc = "Pin is connected to CTS1"] #[inline(always)] - pub fn cts1(self) -> &'a mut W { + pub fn cts1(self) -> &'a mut crate::W { self.variant(FSEL30_A::CTS1) } } #[doc = "Field `FSEL31` reader - Function Select 31"] -pub type FSEL31_R = crate::FieldReader; +pub type FSEL31_R = crate::FieldReader; #[doc = "Function Select 31"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL31_A { + type Ux = u8; +} impl FSEL31_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL31_A { + pub const fn variant(&self) -> FSEL31_A { match self.bits { 0 => FSEL31_A::INPUT, 1 => FSEL31_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL31_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL31_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL31_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL31_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SA2`"] + #[doc = "Pin is connected to SA2"] #[inline(always)] pub fn is_sa2(&self) -> bool { *self == FSEL31_A::SA2 } - #[doc = "Checks if the value of the field is `PCM_DOUT`"] + #[doc = "Pin is connected to PCM_DOUT"] #[inline(always)] pub fn is_pcm_dout(&self) -> bool { *self == FSEL31_A::PCM_DOUT } - #[doc = "Checks if the value of the field is `RTS0`"] + #[doc = "Pin is connected to RTS0"] #[inline(always)] pub fn is_rts0(&self) -> bool { *self == FSEL31_A::RTS0 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL31_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RTS1`"] + #[doc = "Pin is connected to RTS1"] #[inline(always)] pub fn is_rts1(&self) -> bool { *self == FSEL31_A::RTS1 } } #[doc = "Field `FSEL31` writer - Function Select 31"] -pub type FSEL31_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL31_A, 3, O>; -impl<'a, const O: u8> FSEL31_W<'a, O> { +pub type FSEL31_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL31_A>; +impl<'a, REG, const O: u8> FSEL31_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL31_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL31_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL31_A::RESERVED0) } #[doc = "Pin is connected to SA2"] #[inline(always)] - pub fn sa2(self) -> &'a mut W { + pub fn sa2(self) -> &'a mut crate::W { self.variant(FSEL31_A::SA2) } #[doc = "Pin is connected to PCM_DOUT"] #[inline(always)] - pub fn pcm_dout(self) -> &'a mut W { + pub fn pcm_dout(self) -> &'a mut crate::W { self.variant(FSEL31_A::PCM_DOUT) } #[doc = "Pin is connected to RTS0"] #[inline(always)] - pub fn rts0(self) -> &'a mut W { + pub fn rts0(self) -> &'a mut crate::W { self.variant(FSEL31_A::RTS0) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL31_A::RESERVED4) } #[doc = "Pin is connected to RTS1"] #[inline(always)] - pub fn rts1(self) -> &'a mut W { + pub fn rts1(self) -> &'a mut crate::W { self.variant(FSEL31_A::RTS1) } } #[doc = "Field `FSEL32` reader - Function Select 32"] -pub type FSEL32_R = crate::FieldReader; +pub type FSEL32_R = crate::FieldReader; #[doc = "Function Select 32"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL32_A { + type Ux = u8; +} impl FSEL32_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL32_A { + pub const fn variant(&self) -> FSEL32_A { match self.bits { 0 => FSEL32_A::INPUT, 1 => FSEL32_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL32_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL32_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL32_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK0`"] + #[doc = "Pin is connected to GPCLK0"] #[inline(always)] pub fn is_gpclk0(&self) -> bool { *self == FSEL32_A::GPCLK0 } - #[doc = "Checks if the value of the field is `SA1`"] + #[doc = "Pin is connected to SA1"] #[inline(always)] pub fn is_sa1(&self) -> bool { *self == FSEL32_A::SA1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL32_A::RESERVED2 } - #[doc = "Checks if the value of the field is `TXD0`"] + #[doc = "Pin is connected to TXD0"] #[inline(always)] pub fn is_txd0(&self) -> bool { *self == FSEL32_A::TXD0 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL32_A::RESERVED4 } - #[doc = "Checks if the value of the field is `TXD1`"] + #[doc = "Pin is connected to TXD1"] #[inline(always)] pub fn is_txd1(&self) -> bool { *self == FSEL32_A::TXD1 } } #[doc = "Field `FSEL32` writer - Function Select 32"] -pub type FSEL32_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL32_A, 3, O>; -impl<'a, const O: u8> FSEL32_W<'a, O> { +pub type FSEL32_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL32_A>; +impl<'a, REG, const O: u8> FSEL32_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL32_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL32_A::OUTPUT) } #[doc = "Pin is connected to GPCLK0"] #[inline(always)] - pub fn gpclk0(self) -> &'a mut W { + pub fn gpclk0(self) -> &'a mut crate::W { self.variant(FSEL32_A::GPCLK0) } #[doc = "Pin is connected to SA1"] #[inline(always)] - pub fn sa1(self) -> &'a mut W { + pub fn sa1(self) -> &'a mut crate::W { self.variant(FSEL32_A::SA1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL32_A::RESERVED2) } #[doc = "Pin is connected to TXD0"] #[inline(always)] - pub fn txd0(self) -> &'a mut W { + pub fn txd0(self) -> &'a mut crate::W { self.variant(FSEL32_A::TXD0) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL32_A::RESERVED4) } #[doc = "Pin is connected to TXD1"] #[inline(always)] - pub fn txd1(self) -> &'a mut W { + pub fn txd1(self) -> &'a mut crate::W { self.variant(FSEL32_A::TXD1) } } #[doc = "Field `FSEL33` reader - Function Select 33"] -pub type FSEL33_R = crate::FieldReader; +pub type FSEL33_R = crate::FieldReader; #[doc = "Function Select 33"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL33_A { + type Ux = u8; +} impl FSEL33_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL33_A { + pub const fn variant(&self) -> FSEL33_A { match self.bits { 0 => FSEL33_A::INPUT, 1 => FSEL33_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL33_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL33_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL33_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL33_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SA0`"] + #[doc = "Pin is connected to SA0"] #[inline(always)] pub fn is_sa0(&self) -> bool { *self == FSEL33_A::SA0 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL33_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RXD0`"] + #[doc = "Pin is connected to RXD0"] #[inline(always)] pub fn is_rxd0(&self) -> bool { *self == FSEL33_A::RXD0 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL33_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RXD1`"] + #[doc = "Pin is connected to RXD1"] #[inline(always)] pub fn is_rxd1(&self) -> bool { *self == FSEL33_A::RXD1 } } #[doc = "Field `FSEL33` writer - Function Select 33"] -pub type FSEL33_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL33_A, 3, O>; -impl<'a, const O: u8> FSEL33_W<'a, O> { +pub type FSEL33_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL33_A>; +impl<'a, REG, const O: u8> FSEL33_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL33_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL33_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL33_A::RESERVED0) } #[doc = "Pin is connected to SA0"] #[inline(always)] - pub fn sa0(self) -> &'a mut W { + pub fn sa0(self) -> &'a mut crate::W { self.variant(FSEL33_A::SA0) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL33_A::RESERVED2) } #[doc = "Pin is connected to RXD0"] #[inline(always)] - pub fn rxd0(self) -> &'a mut W { + pub fn rxd0(self) -> &'a mut crate::W { self.variant(FSEL33_A::RXD0) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL33_A::RESERVED4) } #[doc = "Pin is connected to RXD1"] #[inline(always)] - pub fn rxd1(self) -> &'a mut W { + pub fn rxd1(self) -> &'a mut crate::W { self.variant(FSEL33_A::RXD1) } } #[doc = "Field `FSEL34` reader - Function Select 34"] -pub type FSEL34_R = crate::FieldReader; +pub type FSEL34_R = crate::FieldReader; #[doc = "Function Select 34"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL34_A { + type Ux = u8; +} impl FSEL34_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL34_A { + pub const fn variant(&self) -> FSEL34_A { match self.bits { 0 => FSEL34_A::INPUT, 1 => FSEL34_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL34_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL34_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL34_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK0`"] + #[doc = "Pin is connected to GPCLK0"] #[inline(always)] pub fn is_gpclk0(&self) -> bool { *self == FSEL34_A::GPCLK0 } - #[doc = "Checks if the value of the field is `SOE_N`"] + #[doc = "Pin is connected to SOE_N"] #[inline(always)] pub fn is_soe_n(&self) -> bool { *self == FSEL34_A::SOE_N } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL34_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL34_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL34_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL34_A::RESERVED5 } } #[doc = "Field `FSEL34` writer - Function Select 34"] -pub type FSEL34_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL34_A, 3, O>; -impl<'a, const O: u8> FSEL34_W<'a, O> { +pub type FSEL34_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL34_A>; +impl<'a, REG, const O: u8> FSEL34_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL34_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL34_A::OUTPUT) } #[doc = "Pin is connected to GPCLK0"] #[inline(always)] - pub fn gpclk0(self) -> &'a mut W { + pub fn gpclk0(self) -> &'a mut crate::W { self.variant(FSEL34_A::GPCLK0) } #[doc = "Pin is connected to SOE_N"] #[inline(always)] - pub fn soe_n(self) -> &'a mut W { + pub fn soe_n(self) -> &'a mut crate::W { self.variant(FSEL34_A::SOE_N) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL34_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL34_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL34_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL34_A::RESERVED5) } } #[doc = "Field `FSEL35` reader - Function Select 35"] -pub type FSEL35_R = crate::FieldReader; +pub type FSEL35_R = crate::FieldReader; #[doc = "Function Select 35"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL35_A { + type Ux = u8; +} impl FSEL35_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL35_A { + pub const fn variant(&self) -> FSEL35_A { match self.bits { 0 => FSEL35_A::INPUT, 1 => FSEL35_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL35_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL35_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL35_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_CE1_N`"] + #[doc = "Pin is connected to SPI0_CE1_N"] #[inline(always)] pub fn is_spi0_ce1_n(&self) -> bool { *self == FSEL35_A::SPI0_CE1_N } - #[doc = "Checks if the value of the field is `SWE_N`"] + #[doc = "Pin is connected to SWE_N"] #[inline(always)] pub fn is_swe_n(&self) -> bool { *self == FSEL35_A::SWE_N } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL35_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL35_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL35_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL35_A::RESERVED5 } } #[doc = "Field `FSEL35` writer - Function Select 35"] -pub type FSEL35_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL35_A, 3, O>; -impl<'a, const O: u8> FSEL35_W<'a, O> { +pub type FSEL35_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL35_A>; +impl<'a, REG, const O: u8> FSEL35_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL35_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL35_A::OUTPUT) } #[doc = "Pin is connected to SPI0_CE1_N"] #[inline(always)] - pub fn spi0_ce1_n(self) -> &'a mut W { + pub fn spi0_ce1_n(self) -> &'a mut crate::W { self.variant(FSEL35_A::SPI0_CE1_N) } #[doc = "Pin is connected to SWE_N"] #[inline(always)] - pub fn swe_n(self) -> &'a mut W { + pub fn swe_n(self) -> &'a mut crate::W { self.variant(FSEL35_A::SWE_N) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL35_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL35_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL35_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL35_A::RESERVED5) } } #[doc = "Field `FSEL36` reader - Function Select 36"] -pub type FSEL36_R = crate::FieldReader; +pub type FSEL36_R = crate::FieldReader; #[doc = "Function Select 36"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL36_A { + type Ux = u8; +} impl FSEL36_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL36_A { + pub const fn variant(&self) -> FSEL36_A { match self.bits { 0 => FSEL36_A::INPUT, 1 => FSEL36_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL36_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL36_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL36_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_CE0_N`"] + #[doc = "Pin is connected to SPI0_CE0_N"] #[inline(always)] pub fn is_spi0_ce0_n(&self) -> bool { *self == FSEL36_A::SPI0_CE0_N } - #[doc = "Checks if the value of the field is `SD0`"] + #[doc = "Pin is connected to SD0"] #[inline(always)] pub fn is_sd0(&self) -> bool { *self == FSEL36_A::SD0 } - #[doc = "Checks if the value of the field is `TXD0`"] + #[doc = "Pin is connected to TXD0"] #[inline(always)] pub fn is_txd0(&self) -> bool { *self == FSEL36_A::TXD0 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL36_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL36_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL36_A::RESERVED5 } } #[doc = "Field `FSEL36` writer - Function Select 36"] -pub type FSEL36_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL36_A, 3, O>; -impl<'a, const O: u8> FSEL36_W<'a, O> { +pub type FSEL36_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL36_A>; +impl<'a, REG, const O: u8> FSEL36_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL36_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL36_A::OUTPUT) } #[doc = "Pin is connected to SPI0_CE0_N"] #[inline(always)] - pub fn spi0_ce0_n(self) -> &'a mut W { + pub fn spi0_ce0_n(self) -> &'a mut crate::W { self.variant(FSEL36_A::SPI0_CE0_N) } #[doc = "Pin is connected to SD0"] #[inline(always)] - pub fn sd0(self) -> &'a mut W { + pub fn sd0(self) -> &'a mut crate::W { self.variant(FSEL36_A::SD0) } #[doc = "Pin is connected to TXD0"] #[inline(always)] - pub fn txd0(self) -> &'a mut W { + pub fn txd0(self) -> &'a mut crate::W { self.variant(FSEL36_A::TXD0) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL36_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL36_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL36_A::RESERVED5) } } #[doc = "Field `FSEL37` reader - Function Select 37"] -pub type FSEL37_R = crate::FieldReader; +pub type FSEL37_R = crate::FieldReader; #[doc = "Function Select 37"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL37_A { + type Ux = u8; +} impl FSEL37_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL37_A { + pub const fn variant(&self) -> FSEL37_A { match self.bits { 0 => FSEL37_A::INPUT, 1 => FSEL37_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL37_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL37_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL37_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_MISO`"] + #[doc = "Pin is connected to SPI0_MISO"] #[inline(always)] pub fn is_spi0_miso(&self) -> bool { *self == FSEL37_A::SPI0_MISO } - #[doc = "Checks if the value of the field is `SD1`"] + #[doc = "Pin is connected to SD1"] #[inline(always)] pub fn is_sd1(&self) -> bool { *self == FSEL37_A::SD1 } - #[doc = "Checks if the value of the field is `RXD0`"] + #[doc = "Pin is connected to RXD0"] #[inline(always)] pub fn is_rxd0(&self) -> bool { *self == FSEL37_A::RXD0 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL37_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL37_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL37_A::RESERVED5 } } #[doc = "Field `FSEL37` writer - Function Select 37"] -pub type FSEL37_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL37_A, 3, O>; -impl<'a, const O: u8> FSEL37_W<'a, O> { +pub type FSEL37_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL37_A>; +impl<'a, REG, const O: u8> FSEL37_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL37_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL37_A::OUTPUT) } #[doc = "Pin is connected to SPI0_MISO"] #[inline(always)] - pub fn spi0_miso(self) -> &'a mut W { + pub fn spi0_miso(self) -> &'a mut crate::W { self.variant(FSEL37_A::SPI0_MISO) } #[doc = "Pin is connected to SD1"] #[inline(always)] - pub fn sd1(self) -> &'a mut W { + pub fn sd1(self) -> &'a mut crate::W { self.variant(FSEL37_A::SD1) } #[doc = "Pin is connected to RXD0"] #[inline(always)] - pub fn rxd0(self) -> &'a mut W { + pub fn rxd0(self) -> &'a mut crate::W { self.variant(FSEL37_A::RXD0) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL37_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL37_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL37_A::RESERVED5) } } #[doc = "Field `FSEL38` reader - Function Select 38"] -pub type FSEL38_R = crate::FieldReader; +pub type FSEL38_R = crate::FieldReader; #[doc = "Function Select 38"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL38_A { + type Ux = u8; +} impl FSEL38_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL38_A { + pub const fn variant(&self) -> FSEL38_A { match self.bits { 0 => FSEL38_A::INPUT, 1 => FSEL38_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL38_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL38_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL38_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_MOSI`"] + #[doc = "Pin is connected to SPI0_MOSI"] #[inline(always)] pub fn is_spi0_mosi(&self) -> bool { *self == FSEL38_A::SPI0_MOSI } - #[doc = "Checks if the value of the field is `SD2`"] + #[doc = "Pin is connected to SD2"] #[inline(always)] pub fn is_sd2(&self) -> bool { *self == FSEL38_A::SD2 } - #[doc = "Checks if the value of the field is `CTS0`"] + #[doc = "Pin is connected to CTS0"] #[inline(always)] pub fn is_cts0(&self) -> bool { *self == FSEL38_A::CTS0 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL38_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL38_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL38_A::RESERVED5 } } #[doc = "Field `FSEL38` writer - Function Select 38"] -pub type FSEL38_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL38_A, 3, O>; -impl<'a, const O: u8> FSEL38_W<'a, O> { +pub type FSEL38_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL38_A>; +impl<'a, REG, const O: u8> FSEL38_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL38_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL38_A::OUTPUT) } #[doc = "Pin is connected to SPI0_MOSI"] #[inline(always)] - pub fn spi0_mosi(self) -> &'a mut W { + pub fn spi0_mosi(self) -> &'a mut crate::W { self.variant(FSEL38_A::SPI0_MOSI) } #[doc = "Pin is connected to SD2"] #[inline(always)] - pub fn sd2(self) -> &'a mut W { + pub fn sd2(self) -> &'a mut crate::W { self.variant(FSEL38_A::SD2) } #[doc = "Pin is connected to CTS0"] #[inline(always)] - pub fn cts0(self) -> &'a mut W { + pub fn cts0(self) -> &'a mut crate::W { self.variant(FSEL38_A::CTS0) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL38_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL38_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL38_A::RESERVED5) } } #[doc = "Field `FSEL39` reader - Function Select 39"] -pub type FSEL39_R = crate::FieldReader; +pub type FSEL39_R = crate::FieldReader; #[doc = "Function Select 39"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL39_A { + type Ux = u8; +} impl FSEL39_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL39_A { + pub const fn variant(&self) -> FSEL39_A { match self.bits { 0 => FSEL39_A::INPUT, 1 => FSEL39_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL39_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL39_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL39_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_SCLK`"] + #[doc = "Pin is connected to SPI0_SCLK"] #[inline(always)] pub fn is_spi0_sclk(&self) -> bool { *self == FSEL39_A::SPI0_SCLK } - #[doc = "Checks if the value of the field is `SD3`"] + #[doc = "Pin is connected to SD3"] #[inline(always)] pub fn is_sd3(&self) -> bool { *self == FSEL39_A::SD3 } - #[doc = "Checks if the value of the field is `RTS0`"] + #[doc = "Pin is connected to RTS0"] #[inline(always)] pub fn is_rts0(&self) -> bool { *self == FSEL39_A::RTS0 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL39_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL39_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL39_A::RESERVED5 } } #[doc = "Field `FSEL39` writer - Function Select 39"] -pub type FSEL39_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL39_A, 3, O>; -impl<'a, const O: u8> FSEL39_W<'a, O> { +pub type FSEL39_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL39_A>; +impl<'a, REG, const O: u8> FSEL39_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL39_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL39_A::OUTPUT) } #[doc = "Pin is connected to SPI0_SCLK"] #[inline(always)] - pub fn spi0_sclk(self) -> &'a mut W { + pub fn spi0_sclk(self) -> &'a mut crate::W { self.variant(FSEL39_A::SPI0_SCLK) } #[doc = "Pin is connected to SD3"] #[inline(always)] - pub fn sd3(self) -> &'a mut W { + pub fn sd3(self) -> &'a mut crate::W { self.variant(FSEL39_A::SD3) } #[doc = "Pin is connected to RTS0"] #[inline(always)] - pub fn rts0(self) -> &'a mut W { + pub fn rts0(self) -> &'a mut crate::W { self.variant(FSEL39_A::RTS0) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL39_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL39_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL39_A::RESERVED5) } } @@ -1396,86 +1424,108 @@ impl R { FSEL39_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL3") + .field("fsel30", &format_args!("{}", self.fsel30().bits())) + .field("fsel31", &format_args!("{}", self.fsel31().bits())) + .field("fsel32", &format_args!("{}", self.fsel32().bits())) + .field("fsel33", &format_args!("{}", self.fsel33().bits())) + .field("fsel34", &format_args!("{}", self.fsel34().bits())) + .field("fsel35", &format_args!("{}", self.fsel35().bits())) + .field("fsel36", &format_args!("{}", self.fsel36().bits())) + .field("fsel37", &format_args!("{}", self.fsel37().bits())) + .field("fsel38", &format_args!("{}", self.fsel38().bits())) + .field("fsel39", &format_args!("{}", self.fsel39().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 30"] #[inline(always)] #[must_use] - pub fn fsel30(&mut self) -> FSEL30_W<0> { + pub fn fsel30(&mut self) -> FSEL30_W { FSEL30_W::new(self) } #[doc = "Bits 3:5 - Function Select 31"] #[inline(always)] #[must_use] - pub fn fsel31(&mut self) -> FSEL31_W<3> { + pub fn fsel31(&mut self) -> FSEL31_W { FSEL31_W::new(self) } #[doc = "Bits 6:8 - Function Select 32"] #[inline(always)] #[must_use] - pub fn fsel32(&mut self) -> FSEL32_W<6> { + pub fn fsel32(&mut self) -> FSEL32_W { FSEL32_W::new(self) } #[doc = "Bits 9:11 - Function Select 33"] #[inline(always)] #[must_use] - pub fn fsel33(&mut self) -> FSEL33_W<9> { + pub fn fsel33(&mut self) -> FSEL33_W { FSEL33_W::new(self) } #[doc = "Bits 12:14 - Function Select 34"] #[inline(always)] #[must_use] - pub fn fsel34(&mut self) -> FSEL34_W<12> { + pub fn fsel34(&mut self) -> FSEL34_W { FSEL34_W::new(self) } #[doc = "Bits 15:17 - Function Select 35"] #[inline(always)] #[must_use] - pub fn fsel35(&mut self) -> FSEL35_W<15> { + pub fn fsel35(&mut self) -> FSEL35_W { FSEL35_W::new(self) } #[doc = "Bits 18:20 - Function Select 36"] #[inline(always)] #[must_use] - pub fn fsel36(&mut self) -> FSEL36_W<18> { + pub fn fsel36(&mut self) -> FSEL36_W { FSEL36_W::new(self) } #[doc = "Bits 21:23 - Function Select 37"] #[inline(always)] #[must_use] - pub fn fsel37(&mut self) -> FSEL37_W<21> { + pub fn fsel37(&mut self) -> FSEL37_W { FSEL37_W::new(self) } #[doc = "Bits 24:26 - Function Select 38"] #[inline(always)] #[must_use] - pub fn fsel38(&mut self) -> FSEL38_W<24> { + pub fn fsel38(&mut self) -> FSEL38_W { FSEL38_W::new(self) } #[doc = "Bits 27:29 - Function Select 39"] #[inline(always)] #[must_use] - pub fn fsel39(&mut self) -> FSEL39_W<27> { + pub fn fsel39(&mut self) -> FSEL39_W { FSEL39_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel3](index.html) module"] +#[doc = "GPIO Function Select 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL3_SPEC; impl crate::RegisterSpec for GPFSEL3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel3::R](R) reader structure"] -impl crate::Readable for GPFSEL3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel3::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel3::R`](R) reader structure"] +impl crate::Readable for GPFSEL3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel3::W`](W) writer structure"] impl crate::Writable for GPFSEL3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpfsel4.rs b/crates/bcm2835-lpa/src/gpio/gpfsel4.rs index 16bf84a..50a568f 100644 --- a/crates/bcm2835-lpa/src/gpio/gpfsel4.rs +++ b/crates/bcm2835-lpa/src/gpio/gpfsel4.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL40` reader - Function Select 40"] -pub type FSEL40_R = crate::FieldReader; +pub type FSEL40_R = crate::FieldReader; #[doc = "Function Select 40"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL40_A { + type Ux = u8; +} impl FSEL40_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL40_A { + pub const fn variant(&self) -> FSEL40_A { match self.bits { 0 => FSEL40_A::INPUT, 1 => FSEL40_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL40_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL40_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL40_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM0_0`"] + #[doc = "Pin is connected to PWM0_0"] #[inline(always)] pub fn is_pwm0_0(&self) -> bool { *self == FSEL40_A::PWM0_0 } - #[doc = "Checks if the value of the field is `SD4`"] + #[doc = "Pin is connected to SD4"] #[inline(always)] pub fn is_sd4(&self) -> bool { *self == FSEL40_A::SD4 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL40_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL40_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL40_A::RESERVED4 } - #[doc = "Checks if the value of the field is `TXD1`"] + #[doc = "Pin is connected to TXD1"] #[inline(always)] pub fn is_txd1(&self) -> bool { *self == FSEL40_A::TXD1 } } #[doc = "Field `FSEL40` writer - Function Select 40"] -pub type FSEL40_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL40_A, 3, O>; -impl<'a, const O: u8> FSEL40_W<'a, O> { +pub type FSEL40_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL40_A>; +impl<'a, REG, const O: u8> FSEL40_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL40_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL40_A::OUTPUT) } #[doc = "Pin is connected to PWM0_0"] #[inline(always)] - pub fn pwm0_0(self) -> &'a mut W { + pub fn pwm0_0(self) -> &'a mut crate::W { self.variant(FSEL40_A::PWM0_0) } #[doc = "Pin is connected to SD4"] #[inline(always)] - pub fn sd4(self) -> &'a mut W { + pub fn sd4(self) -> &'a mut crate::W { self.variant(FSEL40_A::SD4) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL40_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL40_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL40_A::RESERVED4) } #[doc = "Pin is connected to TXD1"] #[inline(always)] - pub fn txd1(self) -> &'a mut W { + pub fn txd1(self) -> &'a mut crate::W { self.variant(FSEL40_A::TXD1) } } #[doc = "Field `FSEL41` reader - Function Select 41"] -pub type FSEL41_R = crate::FieldReader; +pub type FSEL41_R = crate::FieldReader; #[doc = "Function Select 41"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL41_A { + type Ux = u8; +} impl FSEL41_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL41_A { + pub const fn variant(&self) -> FSEL41_A { match self.bits { 0 => FSEL41_A::INPUT, 1 => FSEL41_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL41_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL41_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL41_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM0_1`"] + #[doc = "Pin is connected to PWM0_1"] #[inline(always)] pub fn is_pwm0_1(&self) -> bool { *self == FSEL41_A::PWM0_1 } - #[doc = "Checks if the value of the field is `SD5`"] + #[doc = "Pin is connected to SD5"] #[inline(always)] pub fn is_sd5(&self) -> bool { *self == FSEL41_A::SD5 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL41_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL41_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL41_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RXD1`"] + #[doc = "Pin is connected to RXD1"] #[inline(always)] pub fn is_rxd1(&self) -> bool { *self == FSEL41_A::RXD1 } } #[doc = "Field `FSEL41` writer - Function Select 41"] -pub type FSEL41_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL41_A, 3, O>; -impl<'a, const O: u8> FSEL41_W<'a, O> { +pub type FSEL41_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL41_A>; +impl<'a, REG, const O: u8> FSEL41_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL41_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL41_A::OUTPUT) } #[doc = "Pin is connected to PWM0_1"] #[inline(always)] - pub fn pwm0_1(self) -> &'a mut W { + pub fn pwm0_1(self) -> &'a mut crate::W { self.variant(FSEL41_A::PWM0_1) } #[doc = "Pin is connected to SD5"] #[inline(always)] - pub fn sd5(self) -> &'a mut W { + pub fn sd5(self) -> &'a mut crate::W { self.variant(FSEL41_A::SD5) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL41_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL41_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL41_A::RESERVED4) } #[doc = "Pin is connected to RXD1"] #[inline(always)] - pub fn rxd1(self) -> &'a mut W { + pub fn rxd1(self) -> &'a mut crate::W { self.variant(FSEL41_A::RXD1) } } #[doc = "Field `FSEL42` reader - Function Select 42"] -pub type FSEL42_R = crate::FieldReader; +pub type FSEL42_R = crate::FieldReader; #[doc = "Function Select 42"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL42_A { + type Ux = u8; +} impl FSEL42_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL42_A { + pub const fn variant(&self) -> FSEL42_A { match self.bits { 0 => FSEL42_A::INPUT, 1 => FSEL42_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL42_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL42_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL42_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK1`"] + #[doc = "Pin is connected to GPCLK1"] #[inline(always)] pub fn is_gpclk1(&self) -> bool { *self == FSEL42_A::GPCLK1 } - #[doc = "Checks if the value of the field is `SD6`"] + #[doc = "Pin is connected to SD6"] #[inline(always)] pub fn is_sd6(&self) -> bool { *self == FSEL42_A::SD6 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL42_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL42_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL42_A::RESERVED4 } - #[doc = "Checks if the value of the field is `CTS1`"] + #[doc = "Pin is connected to CTS1"] #[inline(always)] pub fn is_cts1(&self) -> bool { *self == FSEL42_A::CTS1 } } #[doc = "Field `FSEL42` writer - Function Select 42"] -pub type FSEL42_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL42_A, 3, O>; -impl<'a, const O: u8> FSEL42_W<'a, O> { +pub type FSEL42_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL42_A>; +impl<'a, REG, const O: u8> FSEL42_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL42_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL42_A::OUTPUT) } #[doc = "Pin is connected to GPCLK1"] #[inline(always)] - pub fn gpclk1(self) -> &'a mut W { + pub fn gpclk1(self) -> &'a mut crate::W { self.variant(FSEL42_A::GPCLK1) } #[doc = "Pin is connected to SD6"] #[inline(always)] - pub fn sd6(self) -> &'a mut W { + pub fn sd6(self) -> &'a mut crate::W { self.variant(FSEL42_A::SD6) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL42_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL42_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL42_A::RESERVED4) } #[doc = "Pin is connected to CTS1"] #[inline(always)] - pub fn cts1(self) -> &'a mut W { + pub fn cts1(self) -> &'a mut crate::W { self.variant(FSEL42_A::CTS1) } } #[doc = "Field `FSEL43` reader - Function Select 43"] -pub type FSEL43_R = crate::FieldReader; +pub type FSEL43_R = crate::FieldReader; #[doc = "Function Select 43"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL43_A { + type Ux = u8; +} impl FSEL43_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL43_A { + pub const fn variant(&self) -> FSEL43_A { match self.bits { 0 => FSEL43_A::INPUT, 1 => FSEL43_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL43_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL43_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL43_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK2`"] + #[doc = "Pin is connected to GPCLK2"] #[inline(always)] pub fn is_gpclk2(&self) -> bool { *self == FSEL43_A::GPCLK2 } - #[doc = "Checks if the value of the field is `SD7`"] + #[doc = "Pin is connected to SD7"] #[inline(always)] pub fn is_sd7(&self) -> bool { *self == FSEL43_A::SD7 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL43_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL43_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL43_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RTS1`"] + #[doc = "Pin is connected to RTS1"] #[inline(always)] pub fn is_rts1(&self) -> bool { *self == FSEL43_A::RTS1 } } #[doc = "Field `FSEL43` writer - Function Select 43"] -pub type FSEL43_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL43_A, 3, O>; -impl<'a, const O: u8> FSEL43_W<'a, O> { +pub type FSEL43_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL43_A>; +impl<'a, REG, const O: u8> FSEL43_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL43_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL43_A::OUTPUT) } #[doc = "Pin is connected to GPCLK2"] #[inline(always)] - pub fn gpclk2(self) -> &'a mut W { + pub fn gpclk2(self) -> &'a mut crate::W { self.variant(FSEL43_A::GPCLK2) } #[doc = "Pin is connected to SD7"] #[inline(always)] - pub fn sd7(self) -> &'a mut W { + pub fn sd7(self) -> &'a mut crate::W { self.variant(FSEL43_A::SD7) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL43_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL43_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL43_A::RESERVED4) } #[doc = "Pin is connected to RTS1"] #[inline(always)] - pub fn rts1(self) -> &'a mut W { + pub fn rts1(self) -> &'a mut crate::W { self.variant(FSEL43_A::RTS1) } } #[doc = "Field `FSEL44` reader - Function Select 44"] -pub type FSEL44_R = crate::FieldReader; +pub type FSEL44_R = crate::FieldReader; #[doc = "Function Select 44"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL44_A { + type Ux = u8; +} impl FSEL44_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL44_A { + pub const fn variant(&self) -> FSEL44_A { match self.bits { 0 => FSEL44_A::INPUT, 1 => FSEL44_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL44_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL44_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL44_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK1`"] + #[doc = "Pin is connected to GPCLK1"] #[inline(always)] pub fn is_gpclk1(&self) -> bool { *self == FSEL44_A::GPCLK1 } - #[doc = "Checks if the value of the field is `SDA0`"] + #[doc = "Pin is connected to SDA0"] #[inline(always)] pub fn is_sda0(&self) -> bool { *self == FSEL44_A::SDA0 } - #[doc = "Checks if the value of the field is `SDA1`"] + #[doc = "Pin is connected to SDA1"] #[inline(always)] pub fn is_sda1(&self) -> bool { *self == FSEL44_A::SDA1 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL44_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL44_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL44_A::RESERVED5 } } #[doc = "Field `FSEL44` writer - Function Select 44"] -pub type FSEL44_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL44_A, 3, O>; -impl<'a, const O: u8> FSEL44_W<'a, O> { +pub type FSEL44_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL44_A>; +impl<'a, REG, const O: u8> FSEL44_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL44_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL44_A::OUTPUT) } #[doc = "Pin is connected to GPCLK1"] #[inline(always)] - pub fn gpclk1(self) -> &'a mut W { + pub fn gpclk1(self) -> &'a mut crate::W { self.variant(FSEL44_A::GPCLK1) } #[doc = "Pin is connected to SDA0"] #[inline(always)] - pub fn sda0(self) -> &'a mut W { + pub fn sda0(self) -> &'a mut crate::W { self.variant(FSEL44_A::SDA0) } #[doc = "Pin is connected to SDA1"] #[inline(always)] - pub fn sda1(self) -> &'a mut W { + pub fn sda1(self) -> &'a mut crate::W { self.variant(FSEL44_A::SDA1) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL44_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL44_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL44_A::RESERVED5) } } #[doc = "Field `FSEL45` reader - Function Select 45"] -pub type FSEL45_R = crate::FieldReader; +pub type FSEL45_R = crate::FieldReader; #[doc = "Function Select 45"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL45_A { + type Ux = u8; +} impl FSEL45_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL45_A { + pub const fn variant(&self) -> FSEL45_A { match self.bits { 0 => FSEL45_A::INPUT, 1 => FSEL45_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL45_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL45_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL45_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM0_1`"] + #[doc = "Pin is connected to PWM0_1"] #[inline(always)] pub fn is_pwm0_1(&self) -> bool { *self == FSEL45_A::PWM0_1 } - #[doc = "Checks if the value of the field is `SCL0`"] + #[doc = "Pin is connected to SCL0"] #[inline(always)] pub fn is_scl0(&self) -> bool { *self == FSEL45_A::SCL0 } - #[doc = "Checks if the value of the field is `SCL1`"] + #[doc = "Pin is connected to SCL1"] #[inline(always)] pub fn is_scl1(&self) -> bool { *self == FSEL45_A::SCL1 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL45_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL45_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL45_A::RESERVED5 } } #[doc = "Field `FSEL45` writer - Function Select 45"] -pub type FSEL45_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL45_A, 3, O>; -impl<'a, const O: u8> FSEL45_W<'a, O> { +pub type FSEL45_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL45_A>; +impl<'a, REG, const O: u8> FSEL45_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL45_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL45_A::OUTPUT) } #[doc = "Pin is connected to PWM0_1"] #[inline(always)] - pub fn pwm0_1(self) -> &'a mut W { + pub fn pwm0_1(self) -> &'a mut crate::W { self.variant(FSEL45_A::PWM0_1) } #[doc = "Pin is connected to SCL0"] #[inline(always)] - pub fn scl0(self) -> &'a mut W { + pub fn scl0(self) -> &'a mut crate::W { self.variant(FSEL45_A::SCL0) } #[doc = "Pin is connected to SCL1"] #[inline(always)] - pub fn scl1(self) -> &'a mut W { + pub fn scl1(self) -> &'a mut crate::W { self.variant(FSEL45_A::SCL1) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL45_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL45_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL45_A::RESERVED5) } } #[doc = "Field `FSEL46` reader - Function Select 46"] -pub type FSEL46_R = crate::FieldReader; +pub type FSEL46_R = crate::FieldReader; #[doc = "Function Select 46"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL46_A { + type Ux = u8; +} impl FSEL46_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL46_A { + pub const fn variant(&self) -> FSEL46_A { match self.bits { 0 => FSEL46_A::INPUT, 1 => FSEL46_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL46_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL46_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL46_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL46_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL46_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL46_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL46_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL46_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL46_A::RESERVED5 } } #[doc = "Field `FSEL46` writer - Function Select 46"] -pub type FSEL46_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL46_A, 3, O>; -impl<'a, const O: u8> FSEL46_W<'a, O> { +pub type FSEL46_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL46_A>; +impl<'a, REG, const O: u8> FSEL46_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL46_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL46_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED5) } } #[doc = "Field `FSEL47` reader - Function Select 47"] -pub type FSEL47_R = crate::FieldReader; +pub type FSEL47_R = crate::FieldReader; #[doc = "Function Select 47"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL47_A { + type Ux = u8; +} impl FSEL47_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL47_A { + pub const fn variant(&self) -> FSEL47_A { match self.bits { 0 => FSEL47_A::INPUT, 1 => FSEL47_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL47_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL47_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL47_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL47_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL47_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL47_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL47_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL47_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL47_A::RESERVED5 } } #[doc = "Field `FSEL47` writer - Function Select 47"] -pub type FSEL47_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL47_A, 3, O>; -impl<'a, const O: u8> FSEL47_W<'a, O> { +pub type FSEL47_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL47_A>; +impl<'a, REG, const O: u8> FSEL47_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL47_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL47_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED5) } } #[doc = "Field `FSEL48` reader - Function Select 48"] -pub type FSEL48_R = crate::FieldReader; +pub type FSEL48_R = crate::FieldReader; #[doc = "Function Select 48"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL48_A { + type Ux = u8; +} impl FSEL48_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL48_A { + pub const fn variant(&self) -> FSEL48_A { match self.bits { 0 => FSEL48_A::INPUT, 1 => FSEL48_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL48_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL48_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL48_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL48_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL48_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL48_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] pub fn is_sd1_clk(&self) -> bool { *self == FSEL48_A::SD1_CLK } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL48_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL48_A::RESERVED5 } } #[doc = "Field `FSEL48` writer - Function Select 48"] -pub type FSEL48_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL48_A, 3, O>; -impl<'a, const O: u8> FSEL48_W<'a, O> { +pub type FSEL48_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL48_A>; +impl<'a, REG, const O: u8> FSEL48_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL48_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL48_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED2) } #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] - pub fn sd1_clk(self) -> &'a mut W { + pub fn sd1_clk(self) -> &'a mut crate::W { self.variant(FSEL48_A::SD1_CLK) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED5) } } #[doc = "Field `FSEL49` reader - Function Select 49"] -pub type FSEL49_R = crate::FieldReader; +pub type FSEL49_R = crate::FieldReader; #[doc = "Function Select 49"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL49_A { + type Ux = u8; +} impl FSEL49_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL49_A { + pub const fn variant(&self) -> FSEL49_A { match self.bits { 0 => FSEL49_A::INPUT, 1 => FSEL49_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL49_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL49_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL49_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL49_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL49_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL49_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] pub fn is_sd1_cmd(&self) -> bool { *self == FSEL49_A::SD1_CMD } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL49_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL49_A::RESERVED5 } } #[doc = "Field `FSEL49` writer - Function Select 49"] -pub type FSEL49_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL49_A, 3, O>; -impl<'a, const O: u8> FSEL49_W<'a, O> { +pub type FSEL49_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL49_A>; +impl<'a, REG, const O: u8> FSEL49_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL49_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL49_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED2) } #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] - pub fn sd1_cmd(self) -> &'a mut W { + pub fn sd1_cmd(self) -> &'a mut crate::W { self.variant(FSEL49_A::SD1_CMD) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED5) } } @@ -1396,86 +1424,108 @@ impl R { FSEL49_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL4") + .field("fsel40", &format_args!("{}", self.fsel40().bits())) + .field("fsel41", &format_args!("{}", self.fsel41().bits())) + .field("fsel42", &format_args!("{}", self.fsel42().bits())) + .field("fsel43", &format_args!("{}", self.fsel43().bits())) + .field("fsel44", &format_args!("{}", self.fsel44().bits())) + .field("fsel45", &format_args!("{}", self.fsel45().bits())) + .field("fsel46", &format_args!("{}", self.fsel46().bits())) + .field("fsel47", &format_args!("{}", self.fsel47().bits())) + .field("fsel48", &format_args!("{}", self.fsel48().bits())) + .field("fsel49", &format_args!("{}", self.fsel49().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 40"] #[inline(always)] #[must_use] - pub fn fsel40(&mut self) -> FSEL40_W<0> { + pub fn fsel40(&mut self) -> FSEL40_W { FSEL40_W::new(self) } #[doc = "Bits 3:5 - Function Select 41"] #[inline(always)] #[must_use] - pub fn fsel41(&mut self) -> FSEL41_W<3> { + pub fn fsel41(&mut self) -> FSEL41_W { FSEL41_W::new(self) } #[doc = "Bits 6:8 - Function Select 42"] #[inline(always)] #[must_use] - pub fn fsel42(&mut self) -> FSEL42_W<6> { + pub fn fsel42(&mut self) -> FSEL42_W { FSEL42_W::new(self) } #[doc = "Bits 9:11 - Function Select 43"] #[inline(always)] #[must_use] - pub fn fsel43(&mut self) -> FSEL43_W<9> { + pub fn fsel43(&mut self) -> FSEL43_W { FSEL43_W::new(self) } #[doc = "Bits 12:14 - Function Select 44"] #[inline(always)] #[must_use] - pub fn fsel44(&mut self) -> FSEL44_W<12> { + pub fn fsel44(&mut self) -> FSEL44_W { FSEL44_W::new(self) } #[doc = "Bits 15:17 - Function Select 45"] #[inline(always)] #[must_use] - pub fn fsel45(&mut self) -> FSEL45_W<15> { + pub fn fsel45(&mut self) -> FSEL45_W { FSEL45_W::new(self) } #[doc = "Bits 18:20 - Function Select 46"] #[inline(always)] #[must_use] - pub fn fsel46(&mut self) -> FSEL46_W<18> { + pub fn fsel46(&mut self) -> FSEL46_W { FSEL46_W::new(self) } #[doc = "Bits 21:23 - Function Select 47"] #[inline(always)] #[must_use] - pub fn fsel47(&mut self) -> FSEL47_W<21> { + pub fn fsel47(&mut self) -> FSEL47_W { FSEL47_W::new(self) } #[doc = "Bits 24:26 - Function Select 48"] #[inline(always)] #[must_use] - pub fn fsel48(&mut self) -> FSEL48_W<24> { + pub fn fsel48(&mut self) -> FSEL48_W { FSEL48_W::new(self) } #[doc = "Bits 27:29 - Function Select 49"] #[inline(always)] #[must_use] - pub fn fsel49(&mut self) -> FSEL49_W<27> { + pub fn fsel49(&mut self) -> FSEL49_W { FSEL49_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel4](index.html) module"] +#[doc = "GPIO Function Select 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel4::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL4_SPEC; impl crate::RegisterSpec for GPFSEL4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel4::R](R) reader structure"] -impl crate::Readable for GPFSEL4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel4::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel4::R`](R) reader structure"] +impl crate::Readable for GPFSEL4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel4::W`](W) writer structure"] impl crate::Writable for GPFSEL4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpfsel5.rs b/crates/bcm2835-lpa/src/gpio/gpfsel5.rs index 7195017..bb2d446 100644 --- a/crates/bcm2835-lpa/src/gpio/gpfsel5.rs +++ b/crates/bcm2835-lpa/src/gpio/gpfsel5.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL50` reader - Function Select 50"] -pub type FSEL50_R = crate::FieldReader; +pub type FSEL50_R = crate::FieldReader; #[doc = "Function Select 50"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL50_A { + type Ux = u8; +} impl FSEL50_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL50_A { + pub const fn variant(&self) -> FSEL50_A { match self.bits { 0 => FSEL50_A::INPUT, 1 => FSEL50_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL50_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL50_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL50_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL50_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL50_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL50_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] pub fn is_sd1_dat0(&self) -> bool { *self == FSEL50_A::SD1_DAT0 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL50_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL50_A::RESERVED5 } } #[doc = "Field `FSEL50` writer - Function Select 50"] -pub type FSEL50_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL50_A, 3, O>; -impl<'a, const O: u8> FSEL50_W<'a, O> { +pub type FSEL50_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL50_A>; +impl<'a, REG, const O: u8> FSEL50_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL50_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL50_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] - pub fn sd1_dat0(self) -> &'a mut W { + pub fn sd1_dat0(self) -> &'a mut crate::W { self.variant(FSEL50_A::SD1_DAT0) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED5) } } #[doc = "Field `FSEL51` reader - Function Select 51"] -pub type FSEL51_R = crate::FieldReader; +pub type FSEL51_R = crate::FieldReader; #[doc = "Function Select 51"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL51_A { + type Ux = u8; +} impl FSEL51_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL51_A { + pub const fn variant(&self) -> FSEL51_A { match self.bits { 0 => FSEL51_A::INPUT, 1 => FSEL51_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL51_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL51_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL51_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL51_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL51_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL51_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] pub fn is_sd1_dat1(&self) -> bool { *self == FSEL51_A::SD1_DAT1 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL51_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL51_A::RESERVED5 } } #[doc = "Field `FSEL51` writer - Function Select 51"] -pub type FSEL51_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL51_A, 3, O>; -impl<'a, const O: u8> FSEL51_W<'a, O> { +pub type FSEL51_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL51_A>; +impl<'a, REG, const O: u8> FSEL51_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL51_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL51_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] - pub fn sd1_dat1(self) -> &'a mut W { + pub fn sd1_dat1(self) -> &'a mut crate::W { self.variant(FSEL51_A::SD1_DAT1) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED5) } } #[doc = "Field `FSEL52` reader - Function Select 52"] -pub type FSEL52_R = crate::FieldReader; +pub type FSEL52_R = crate::FieldReader; #[doc = "Function Select 52"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL52_A { + type Ux = u8; +} impl FSEL52_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL52_A { + pub const fn variant(&self) -> FSEL52_A { match self.bits { 0 => FSEL52_A::INPUT, 1 => FSEL52_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL52_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL52_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL52_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL52_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL52_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL52_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] pub fn is_sd1_dat2(&self) -> bool { *self == FSEL52_A::SD1_DAT2 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL52_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL52_A::RESERVED5 } } #[doc = "Field `FSEL52` writer - Function Select 52"] -pub type FSEL52_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL52_A, 3, O>; -impl<'a, const O: u8> FSEL52_W<'a, O> { +pub type FSEL52_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL52_A>; +impl<'a, REG, const O: u8> FSEL52_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL52_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL52_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] - pub fn sd1_dat2(self) -> &'a mut W { + pub fn sd1_dat2(self) -> &'a mut crate::W { self.variant(FSEL52_A::SD1_DAT2) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED5) } } #[doc = "Field `FSEL53` reader - Function Select 53"] -pub type FSEL53_R = crate::FieldReader; +pub type FSEL53_R = crate::FieldReader; #[doc = "Function Select 53"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL53_A { + type Ux = u8; +} impl FSEL53_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL53_A { + pub const fn variant(&self) -> FSEL53_A { match self.bits { 0 => FSEL53_A::INPUT, 1 => FSEL53_A::OUTPUT, @@ -472,89 +461,92 @@ impl FSEL53_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL53_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL53_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL53_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL53_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL53_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] pub fn is_sd1_dat3(&self) -> bool { *self == FSEL53_A::SD1_DAT3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL53_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL53_A::RESERVED5 } } #[doc = "Field `FSEL53` writer - Function Select 53"] -pub type FSEL53_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL53_A, 3, O>; -impl<'a, const O: u8> FSEL53_W<'a, O> { +pub type FSEL53_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL53_A>; +impl<'a, REG, const O: u8> FSEL53_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL53_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL53_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] - pub fn sd1_dat3(self) -> &'a mut W { + pub fn sd1_dat3(self) -> &'a mut crate::W { self.variant(FSEL53_A::SD1_DAT3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED5) } } @@ -580,50 +572,66 @@ impl R { FSEL53_R::new(((self.bits >> 9) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL5") + .field("fsel50", &format_args!("{}", self.fsel50().bits())) + .field("fsel51", &format_args!("{}", self.fsel51().bits())) + .field("fsel52", &format_args!("{}", self.fsel52().bits())) + .field("fsel53", &format_args!("{}", self.fsel53().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 50"] #[inline(always)] #[must_use] - pub fn fsel50(&mut self) -> FSEL50_W<0> { + pub fn fsel50(&mut self) -> FSEL50_W { FSEL50_W::new(self) } #[doc = "Bits 3:5 - Function Select 51"] #[inline(always)] #[must_use] - pub fn fsel51(&mut self) -> FSEL51_W<3> { + pub fn fsel51(&mut self) -> FSEL51_W { FSEL51_W::new(self) } #[doc = "Bits 6:8 - Function Select 52"] #[inline(always)] #[must_use] - pub fn fsel52(&mut self) -> FSEL52_W<6> { + pub fn fsel52(&mut self) -> FSEL52_W { FSEL52_W::new(self) } #[doc = "Bits 9:11 - Function Select 53"] #[inline(always)] #[must_use] - pub fn fsel53(&mut self) -> FSEL53_W<9> { + pub fn fsel53(&mut self) -> FSEL53_W { FSEL53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel5](index.html) module"] +#[doc = "GPIO Function Select 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel5::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL5_SPEC; impl crate::RegisterSpec for GPFSEL5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel5::R](R) reader structure"] -impl crate::Readable for GPFSEL5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel5::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel5::R`](R) reader structure"] +impl crate::Readable for GPFSEL5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel5::W`](W) writer structure"] impl crate::Writable for GPFSEL5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gphen0.rs b/crates/bcm2835-lpa/src/gpio/gphen0.rs index b45a414..d788bbf 100644 --- a/crates/bcm2835-lpa/src/gpio/gphen0.rs +++ b/crates/bcm2835-lpa/src/gpio/gphen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPHEN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPHEN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HEN0` reader - High detect enabled 0"] -pub type HEN0_R = crate::BitReader; +pub type HEN0_R = crate::BitReader; #[doc = "Field `HEN0` writer - High detect enabled 0"] -pub type HEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN1` reader - High detect enabled 1"] -pub type HEN1_R = crate::BitReader; +pub type HEN1_R = crate::BitReader; #[doc = "Field `HEN1` writer - High detect enabled 1"] -pub type HEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN2` reader - High detect enabled 2"] -pub type HEN2_R = crate::BitReader; +pub type HEN2_R = crate::BitReader; #[doc = "Field `HEN2` writer - High detect enabled 2"] -pub type HEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN3` reader - High detect enabled 3"] -pub type HEN3_R = crate::BitReader; +pub type HEN3_R = crate::BitReader; #[doc = "Field `HEN3` writer - High detect enabled 3"] -pub type HEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN4` reader - High detect enabled 4"] -pub type HEN4_R = crate::BitReader; +pub type HEN4_R = crate::BitReader; #[doc = "Field `HEN4` writer - High detect enabled 4"] -pub type HEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN5` reader - High detect enabled 5"] -pub type HEN5_R = crate::BitReader; +pub type HEN5_R = crate::BitReader; #[doc = "Field `HEN5` writer - High detect enabled 5"] -pub type HEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN6` reader - High detect enabled 6"] -pub type HEN6_R = crate::BitReader; +pub type HEN6_R = crate::BitReader; #[doc = "Field `HEN6` writer - High detect enabled 6"] -pub type HEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN7` reader - High detect enabled 7"] -pub type HEN7_R = crate::BitReader; +pub type HEN7_R = crate::BitReader; #[doc = "Field `HEN7` writer - High detect enabled 7"] -pub type HEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN8` reader - High detect enabled 8"] -pub type HEN8_R = crate::BitReader; +pub type HEN8_R = crate::BitReader; #[doc = "Field `HEN8` writer - High detect enabled 8"] -pub type HEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN9` reader - High detect enabled 9"] -pub type HEN9_R = crate::BitReader; +pub type HEN9_R = crate::BitReader; #[doc = "Field `HEN9` writer - High detect enabled 9"] -pub type HEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN10` reader - High detect enabled 10"] -pub type HEN10_R = crate::BitReader; +pub type HEN10_R = crate::BitReader; #[doc = "Field `HEN10` writer - High detect enabled 10"] -pub type HEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN11` reader - High detect enabled 11"] -pub type HEN11_R = crate::BitReader; +pub type HEN11_R = crate::BitReader; #[doc = "Field `HEN11` writer - High detect enabled 11"] -pub type HEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN12` reader - High detect enabled 12"] -pub type HEN12_R = crate::BitReader; +pub type HEN12_R = crate::BitReader; #[doc = "Field `HEN12` writer - High detect enabled 12"] -pub type HEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN13` reader - High detect enabled 13"] -pub type HEN13_R = crate::BitReader; +pub type HEN13_R = crate::BitReader; #[doc = "Field `HEN13` writer - High detect enabled 13"] -pub type HEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN14` reader - High detect enabled 14"] -pub type HEN14_R = crate::BitReader; +pub type HEN14_R = crate::BitReader; #[doc = "Field `HEN14` writer - High detect enabled 14"] -pub type HEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN15` reader - High detect enabled 15"] -pub type HEN15_R = crate::BitReader; +pub type HEN15_R = crate::BitReader; #[doc = "Field `HEN15` writer - High detect enabled 15"] -pub type HEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN16` reader - High detect enabled 16"] -pub type HEN16_R = crate::BitReader; +pub type HEN16_R = crate::BitReader; #[doc = "Field `HEN16` writer - High detect enabled 16"] -pub type HEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN17` reader - High detect enabled 17"] -pub type HEN17_R = crate::BitReader; +pub type HEN17_R = crate::BitReader; #[doc = "Field `HEN17` writer - High detect enabled 17"] -pub type HEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN18` reader - High detect enabled 18"] -pub type HEN18_R = crate::BitReader; +pub type HEN18_R = crate::BitReader; #[doc = "Field `HEN18` writer - High detect enabled 18"] -pub type HEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN19` reader - High detect enabled 19"] -pub type HEN19_R = crate::BitReader; +pub type HEN19_R = crate::BitReader; #[doc = "Field `HEN19` writer - High detect enabled 19"] -pub type HEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN20` reader - High detect enabled 20"] -pub type HEN20_R = crate::BitReader; +pub type HEN20_R = crate::BitReader; #[doc = "Field `HEN20` writer - High detect enabled 20"] -pub type HEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN21` reader - High detect enabled 21"] -pub type HEN21_R = crate::BitReader; +pub type HEN21_R = crate::BitReader; #[doc = "Field `HEN21` writer - High detect enabled 21"] -pub type HEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN22` reader - High detect enabled 22"] -pub type HEN22_R = crate::BitReader; +pub type HEN22_R = crate::BitReader; #[doc = "Field `HEN22` writer - High detect enabled 22"] -pub type HEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN23` reader - High detect enabled 23"] -pub type HEN23_R = crate::BitReader; +pub type HEN23_R = crate::BitReader; #[doc = "Field `HEN23` writer - High detect enabled 23"] -pub type HEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN24` reader - High detect enabled 24"] -pub type HEN24_R = crate::BitReader; +pub type HEN24_R = crate::BitReader; #[doc = "Field `HEN24` writer - High detect enabled 24"] -pub type HEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN25` reader - High detect enabled 25"] -pub type HEN25_R = crate::BitReader; +pub type HEN25_R = crate::BitReader; #[doc = "Field `HEN25` writer - High detect enabled 25"] -pub type HEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN26` reader - High detect enabled 26"] -pub type HEN26_R = crate::BitReader; +pub type HEN26_R = crate::BitReader; #[doc = "Field `HEN26` writer - High detect enabled 26"] -pub type HEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN27` reader - High detect enabled 27"] -pub type HEN27_R = crate::BitReader; +pub type HEN27_R = crate::BitReader; #[doc = "Field `HEN27` writer - High detect enabled 27"] -pub type HEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN28` reader - High detect enabled 28"] -pub type HEN28_R = crate::BitReader; +pub type HEN28_R = crate::BitReader; #[doc = "Field `HEN28` writer - High detect enabled 28"] -pub type HEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN29` reader - High detect enabled 29"] -pub type HEN29_R = crate::BitReader; +pub type HEN29_R = crate::BitReader; #[doc = "Field `HEN29` writer - High detect enabled 29"] -pub type HEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN30` reader - High detect enabled 30"] -pub type HEN30_R = crate::BitReader; +pub type HEN30_R = crate::BitReader; #[doc = "Field `HEN30` writer - High detect enabled 30"] -pub type HEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN31` reader - High detect enabled 31"] -pub type HEN31_R = crate::BitReader; +pub type HEN31_R = crate::BitReader; #[doc = "Field `HEN31` writer - High detect enabled 31"] -pub type HEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - High detect enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { HEN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPHEN0") + .field("hen0", &format_args!("{}", self.hen0().bit())) + .field("hen1", &format_args!("{}", self.hen1().bit())) + .field("hen2", &format_args!("{}", self.hen2().bit())) + .field("hen3", &format_args!("{}", self.hen3().bit())) + .field("hen4", &format_args!("{}", self.hen4().bit())) + .field("hen5", &format_args!("{}", self.hen5().bit())) + .field("hen6", &format_args!("{}", self.hen6().bit())) + .field("hen7", &format_args!("{}", self.hen7().bit())) + .field("hen8", &format_args!("{}", self.hen8().bit())) + .field("hen9", &format_args!("{}", self.hen9().bit())) + .field("hen10", &format_args!("{}", self.hen10().bit())) + .field("hen11", &format_args!("{}", self.hen11().bit())) + .field("hen12", &format_args!("{}", self.hen12().bit())) + .field("hen13", &format_args!("{}", self.hen13().bit())) + .field("hen14", &format_args!("{}", self.hen14().bit())) + .field("hen15", &format_args!("{}", self.hen15().bit())) + .field("hen16", &format_args!("{}", self.hen16().bit())) + .field("hen17", &format_args!("{}", self.hen17().bit())) + .field("hen18", &format_args!("{}", self.hen18().bit())) + .field("hen19", &format_args!("{}", self.hen19().bit())) + .field("hen20", &format_args!("{}", self.hen20().bit())) + .field("hen21", &format_args!("{}", self.hen21().bit())) + .field("hen22", &format_args!("{}", self.hen22().bit())) + .field("hen23", &format_args!("{}", self.hen23().bit())) + .field("hen24", &format_args!("{}", self.hen24().bit())) + .field("hen25", &format_args!("{}", self.hen25().bit())) + .field("hen26", &format_args!("{}", self.hen26().bit())) + .field("hen27", &format_args!("{}", self.hen27().bit())) + .field("hen28", &format_args!("{}", self.hen28().bit())) + .field("hen29", &format_args!("{}", self.hen29().bit())) + .field("hen30", &format_args!("{}", self.hen30().bit())) + .field("hen31", &format_args!("{}", self.hen31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - High detect enabled 0"] #[inline(always)] #[must_use] - pub fn hen0(&mut self) -> HEN0_W<0> { + pub fn hen0(&mut self) -> HEN0_W { HEN0_W::new(self) } #[doc = "Bit 1 - High detect enabled 1"] #[inline(always)] #[must_use] - pub fn hen1(&mut self) -> HEN1_W<1> { + pub fn hen1(&mut self) -> HEN1_W { HEN1_W::new(self) } #[doc = "Bit 2 - High detect enabled 2"] #[inline(always)] #[must_use] - pub fn hen2(&mut self) -> HEN2_W<2> { + pub fn hen2(&mut self) -> HEN2_W { HEN2_W::new(self) } #[doc = "Bit 3 - High detect enabled 3"] #[inline(always)] #[must_use] - pub fn hen3(&mut self) -> HEN3_W<3> { + pub fn hen3(&mut self) -> HEN3_W { HEN3_W::new(self) } #[doc = "Bit 4 - High detect enabled 4"] #[inline(always)] #[must_use] - pub fn hen4(&mut self) -> HEN4_W<4> { + pub fn hen4(&mut self) -> HEN4_W { HEN4_W::new(self) } #[doc = "Bit 5 - High detect enabled 5"] #[inline(always)] #[must_use] - pub fn hen5(&mut self) -> HEN5_W<5> { + pub fn hen5(&mut self) -> HEN5_W { HEN5_W::new(self) } #[doc = "Bit 6 - High detect enabled 6"] #[inline(always)] #[must_use] - pub fn hen6(&mut self) -> HEN6_W<6> { + pub fn hen6(&mut self) -> HEN6_W { HEN6_W::new(self) } #[doc = "Bit 7 - High detect enabled 7"] #[inline(always)] #[must_use] - pub fn hen7(&mut self) -> HEN7_W<7> { + pub fn hen7(&mut self) -> HEN7_W { HEN7_W::new(self) } #[doc = "Bit 8 - High detect enabled 8"] #[inline(always)] #[must_use] - pub fn hen8(&mut self) -> HEN8_W<8> { + pub fn hen8(&mut self) -> HEN8_W { HEN8_W::new(self) } #[doc = "Bit 9 - High detect enabled 9"] #[inline(always)] #[must_use] - pub fn hen9(&mut self) -> HEN9_W<9> { + pub fn hen9(&mut self) -> HEN9_W { HEN9_W::new(self) } #[doc = "Bit 10 - High detect enabled 10"] #[inline(always)] #[must_use] - pub fn hen10(&mut self) -> HEN10_W<10> { + pub fn hen10(&mut self) -> HEN10_W { HEN10_W::new(self) } #[doc = "Bit 11 - High detect enabled 11"] #[inline(always)] #[must_use] - pub fn hen11(&mut self) -> HEN11_W<11> { + pub fn hen11(&mut self) -> HEN11_W { HEN11_W::new(self) } #[doc = "Bit 12 - High detect enabled 12"] #[inline(always)] #[must_use] - pub fn hen12(&mut self) -> HEN12_W<12> { + pub fn hen12(&mut self) -> HEN12_W { HEN12_W::new(self) } #[doc = "Bit 13 - High detect enabled 13"] #[inline(always)] #[must_use] - pub fn hen13(&mut self) -> HEN13_W<13> { + pub fn hen13(&mut self) -> HEN13_W { HEN13_W::new(self) } #[doc = "Bit 14 - High detect enabled 14"] #[inline(always)] #[must_use] - pub fn hen14(&mut self) -> HEN14_W<14> { + pub fn hen14(&mut self) -> HEN14_W { HEN14_W::new(self) } #[doc = "Bit 15 - High detect enabled 15"] #[inline(always)] #[must_use] - pub fn hen15(&mut self) -> HEN15_W<15> { + pub fn hen15(&mut self) -> HEN15_W { HEN15_W::new(self) } #[doc = "Bit 16 - High detect enabled 16"] #[inline(always)] #[must_use] - pub fn hen16(&mut self) -> HEN16_W<16> { + pub fn hen16(&mut self) -> HEN16_W { HEN16_W::new(self) } #[doc = "Bit 17 - High detect enabled 17"] #[inline(always)] #[must_use] - pub fn hen17(&mut self) -> HEN17_W<17> { + pub fn hen17(&mut self) -> HEN17_W { HEN17_W::new(self) } #[doc = "Bit 18 - High detect enabled 18"] #[inline(always)] #[must_use] - pub fn hen18(&mut self) -> HEN18_W<18> { + pub fn hen18(&mut self) -> HEN18_W { HEN18_W::new(self) } #[doc = "Bit 19 - High detect enabled 19"] #[inline(always)] #[must_use] - pub fn hen19(&mut self) -> HEN19_W<19> { + pub fn hen19(&mut self) -> HEN19_W { HEN19_W::new(self) } #[doc = "Bit 20 - High detect enabled 20"] #[inline(always)] #[must_use] - pub fn hen20(&mut self) -> HEN20_W<20> { + pub fn hen20(&mut self) -> HEN20_W { HEN20_W::new(self) } #[doc = "Bit 21 - High detect enabled 21"] #[inline(always)] #[must_use] - pub fn hen21(&mut self) -> HEN21_W<21> { + pub fn hen21(&mut self) -> HEN21_W { HEN21_W::new(self) } #[doc = "Bit 22 - High detect enabled 22"] #[inline(always)] #[must_use] - pub fn hen22(&mut self) -> HEN22_W<22> { + pub fn hen22(&mut self) -> HEN22_W { HEN22_W::new(self) } #[doc = "Bit 23 - High detect enabled 23"] #[inline(always)] #[must_use] - pub fn hen23(&mut self) -> HEN23_W<23> { + pub fn hen23(&mut self) -> HEN23_W { HEN23_W::new(self) } #[doc = "Bit 24 - High detect enabled 24"] #[inline(always)] #[must_use] - pub fn hen24(&mut self) -> HEN24_W<24> { + pub fn hen24(&mut self) -> HEN24_W { HEN24_W::new(self) } #[doc = "Bit 25 - High detect enabled 25"] #[inline(always)] #[must_use] - pub fn hen25(&mut self) -> HEN25_W<25> { + pub fn hen25(&mut self) -> HEN25_W { HEN25_W::new(self) } #[doc = "Bit 26 - High detect enabled 26"] #[inline(always)] #[must_use] - pub fn hen26(&mut self) -> HEN26_W<26> { + pub fn hen26(&mut self) -> HEN26_W { HEN26_W::new(self) } #[doc = "Bit 27 - High detect enabled 27"] #[inline(always)] #[must_use] - pub fn hen27(&mut self) -> HEN27_W<27> { + pub fn hen27(&mut self) -> HEN27_W { HEN27_W::new(self) } #[doc = "Bit 28 - High detect enabled 28"] #[inline(always)] #[must_use] - pub fn hen28(&mut self) -> HEN28_W<28> { + pub fn hen28(&mut self) -> HEN28_W { HEN28_W::new(self) } #[doc = "Bit 29 - High detect enabled 29"] #[inline(always)] #[must_use] - pub fn hen29(&mut self) -> HEN29_W<29> { + pub fn hen29(&mut self) -> HEN29_W { HEN29_W::new(self) } #[doc = "Bit 30 - High detect enabled 30"] #[inline(always)] #[must_use] - pub fn hen30(&mut self) -> HEN30_W<30> { + pub fn hen30(&mut self) -> HEN30_W { HEN30_W::new(self) } #[doc = "Bit 31 - High detect enabled 31"] #[inline(always)] #[must_use] - pub fn hen31(&mut self) -> HEN31_W<31> { + pub fn hen31(&mut self) -> HEN31_W { HEN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin High Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gphen0](index.html) module"] +#[doc = "GPIO Pin High Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gphen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gphen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPHEN0_SPEC; impl crate::RegisterSpec for GPHEN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gphen0::R](R) reader structure"] -impl crate::Readable for GPHEN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gphen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gphen0::R`](R) reader structure"] +impl crate::Readable for GPHEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gphen0::W`](W) writer structure"] impl crate::Writable for GPHEN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gphen1.rs b/crates/bcm2835-lpa/src/gpio/gphen1.rs index 23c512c..3d0aa21 100644 --- a/crates/bcm2835-lpa/src/gpio/gphen1.rs +++ b/crates/bcm2835-lpa/src/gpio/gphen1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPHEN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPHEN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HEN32` reader - High detect enabled 32"] -pub type HEN32_R = crate::BitReader; +pub type HEN32_R = crate::BitReader; #[doc = "Field `HEN32` writer - High detect enabled 32"] -pub type HEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN33` reader - High detect enabled 33"] -pub type HEN33_R = crate::BitReader; +pub type HEN33_R = crate::BitReader; #[doc = "Field `HEN33` writer - High detect enabled 33"] -pub type HEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN34` reader - High detect enabled 34"] -pub type HEN34_R = crate::BitReader; +pub type HEN34_R = crate::BitReader; #[doc = "Field `HEN34` writer - High detect enabled 34"] -pub type HEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN35` reader - High detect enabled 35"] -pub type HEN35_R = crate::BitReader; +pub type HEN35_R = crate::BitReader; #[doc = "Field `HEN35` writer - High detect enabled 35"] -pub type HEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN36` reader - High detect enabled 36"] -pub type HEN36_R = crate::BitReader; +pub type HEN36_R = crate::BitReader; #[doc = "Field `HEN36` writer - High detect enabled 36"] -pub type HEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN37` reader - High detect enabled 37"] -pub type HEN37_R = crate::BitReader; +pub type HEN37_R = crate::BitReader; #[doc = "Field `HEN37` writer - High detect enabled 37"] -pub type HEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN38` reader - High detect enabled 38"] -pub type HEN38_R = crate::BitReader; +pub type HEN38_R = crate::BitReader; #[doc = "Field `HEN38` writer - High detect enabled 38"] -pub type HEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN39` reader - High detect enabled 39"] -pub type HEN39_R = crate::BitReader; +pub type HEN39_R = crate::BitReader; #[doc = "Field `HEN39` writer - High detect enabled 39"] -pub type HEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN40` reader - High detect enabled 40"] -pub type HEN40_R = crate::BitReader; +pub type HEN40_R = crate::BitReader; #[doc = "Field `HEN40` writer - High detect enabled 40"] -pub type HEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN41` reader - High detect enabled 41"] -pub type HEN41_R = crate::BitReader; +pub type HEN41_R = crate::BitReader; #[doc = "Field `HEN41` writer - High detect enabled 41"] -pub type HEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN42` reader - High detect enabled 42"] -pub type HEN42_R = crate::BitReader; +pub type HEN42_R = crate::BitReader; #[doc = "Field `HEN42` writer - High detect enabled 42"] -pub type HEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN43` reader - High detect enabled 43"] -pub type HEN43_R = crate::BitReader; +pub type HEN43_R = crate::BitReader; #[doc = "Field `HEN43` writer - High detect enabled 43"] -pub type HEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN44` reader - High detect enabled 44"] -pub type HEN44_R = crate::BitReader; +pub type HEN44_R = crate::BitReader; #[doc = "Field `HEN44` writer - High detect enabled 44"] -pub type HEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN45` reader - High detect enabled 45"] -pub type HEN45_R = crate::BitReader; +pub type HEN45_R = crate::BitReader; #[doc = "Field `HEN45` writer - High detect enabled 45"] -pub type HEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN46` reader - High detect enabled 46"] -pub type HEN46_R = crate::BitReader; +pub type HEN46_R = crate::BitReader; #[doc = "Field `HEN46` writer - High detect enabled 46"] -pub type HEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN47` reader - High detect enabled 47"] -pub type HEN47_R = crate::BitReader; +pub type HEN47_R = crate::BitReader; #[doc = "Field `HEN47` writer - High detect enabled 47"] -pub type HEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN48` reader - High detect enabled 48"] -pub type HEN48_R = crate::BitReader; +pub type HEN48_R = crate::BitReader; #[doc = "Field `HEN48` writer - High detect enabled 48"] -pub type HEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN49` reader - High detect enabled 49"] -pub type HEN49_R = crate::BitReader; +pub type HEN49_R = crate::BitReader; #[doc = "Field `HEN49` writer - High detect enabled 49"] -pub type HEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN50` reader - High detect enabled 50"] -pub type HEN50_R = crate::BitReader; +pub type HEN50_R = crate::BitReader; #[doc = "Field `HEN50` writer - High detect enabled 50"] -pub type HEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN51` reader - High detect enabled 51"] -pub type HEN51_R = crate::BitReader; +pub type HEN51_R = crate::BitReader; #[doc = "Field `HEN51` writer - High detect enabled 51"] -pub type HEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN52` reader - High detect enabled 52"] -pub type HEN52_R = crate::BitReader; +pub type HEN52_R = crate::BitReader; #[doc = "Field `HEN52` writer - High detect enabled 52"] -pub type HEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN53` reader - High detect enabled 53"] -pub type HEN53_R = crate::BitReader; +pub type HEN53_R = crate::BitReader; #[doc = "Field `HEN53` writer - High detect enabled 53"] -pub type HEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - High detect enabled 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { HEN53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPHEN1") + .field("hen32", &format_args!("{}", self.hen32().bit())) + .field("hen33", &format_args!("{}", self.hen33().bit())) + .field("hen34", &format_args!("{}", self.hen34().bit())) + .field("hen35", &format_args!("{}", self.hen35().bit())) + .field("hen36", &format_args!("{}", self.hen36().bit())) + .field("hen37", &format_args!("{}", self.hen37().bit())) + .field("hen38", &format_args!("{}", self.hen38().bit())) + .field("hen39", &format_args!("{}", self.hen39().bit())) + .field("hen40", &format_args!("{}", self.hen40().bit())) + .field("hen41", &format_args!("{}", self.hen41().bit())) + .field("hen42", &format_args!("{}", self.hen42().bit())) + .field("hen43", &format_args!("{}", self.hen43().bit())) + .field("hen44", &format_args!("{}", self.hen44().bit())) + .field("hen45", &format_args!("{}", self.hen45().bit())) + .field("hen46", &format_args!("{}", self.hen46().bit())) + .field("hen47", &format_args!("{}", self.hen47().bit())) + .field("hen48", &format_args!("{}", self.hen48().bit())) + .field("hen49", &format_args!("{}", self.hen49().bit())) + .field("hen50", &format_args!("{}", self.hen50().bit())) + .field("hen51", &format_args!("{}", self.hen51().bit())) + .field("hen52", &format_args!("{}", self.hen52().bit())) + .field("hen53", &format_args!("{}", self.hen53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - High detect enabled 32"] #[inline(always)] #[must_use] - pub fn hen32(&mut self) -> HEN32_W<0> { + pub fn hen32(&mut self) -> HEN32_W { HEN32_W::new(self) } #[doc = "Bit 1 - High detect enabled 33"] #[inline(always)] #[must_use] - pub fn hen33(&mut self) -> HEN33_W<1> { + pub fn hen33(&mut self) -> HEN33_W { HEN33_W::new(self) } #[doc = "Bit 2 - High detect enabled 34"] #[inline(always)] #[must_use] - pub fn hen34(&mut self) -> HEN34_W<2> { + pub fn hen34(&mut self) -> HEN34_W { HEN34_W::new(self) } #[doc = "Bit 3 - High detect enabled 35"] #[inline(always)] #[must_use] - pub fn hen35(&mut self) -> HEN35_W<3> { + pub fn hen35(&mut self) -> HEN35_W { HEN35_W::new(self) } #[doc = "Bit 4 - High detect enabled 36"] #[inline(always)] #[must_use] - pub fn hen36(&mut self) -> HEN36_W<4> { + pub fn hen36(&mut self) -> HEN36_W { HEN36_W::new(self) } #[doc = "Bit 5 - High detect enabled 37"] #[inline(always)] #[must_use] - pub fn hen37(&mut self) -> HEN37_W<5> { + pub fn hen37(&mut self) -> HEN37_W { HEN37_W::new(self) } #[doc = "Bit 6 - High detect enabled 38"] #[inline(always)] #[must_use] - pub fn hen38(&mut self) -> HEN38_W<6> { + pub fn hen38(&mut self) -> HEN38_W { HEN38_W::new(self) } #[doc = "Bit 7 - High detect enabled 39"] #[inline(always)] #[must_use] - pub fn hen39(&mut self) -> HEN39_W<7> { + pub fn hen39(&mut self) -> HEN39_W { HEN39_W::new(self) } #[doc = "Bit 8 - High detect enabled 40"] #[inline(always)] #[must_use] - pub fn hen40(&mut self) -> HEN40_W<8> { + pub fn hen40(&mut self) -> HEN40_W { HEN40_W::new(self) } #[doc = "Bit 9 - High detect enabled 41"] #[inline(always)] #[must_use] - pub fn hen41(&mut self) -> HEN41_W<9> { + pub fn hen41(&mut self) -> HEN41_W { HEN41_W::new(self) } #[doc = "Bit 10 - High detect enabled 42"] #[inline(always)] #[must_use] - pub fn hen42(&mut self) -> HEN42_W<10> { + pub fn hen42(&mut self) -> HEN42_W { HEN42_W::new(self) } #[doc = "Bit 11 - High detect enabled 43"] #[inline(always)] #[must_use] - pub fn hen43(&mut self) -> HEN43_W<11> { + pub fn hen43(&mut self) -> HEN43_W { HEN43_W::new(self) } #[doc = "Bit 12 - High detect enabled 44"] #[inline(always)] #[must_use] - pub fn hen44(&mut self) -> HEN44_W<12> { + pub fn hen44(&mut self) -> HEN44_W { HEN44_W::new(self) } #[doc = "Bit 13 - High detect enabled 45"] #[inline(always)] #[must_use] - pub fn hen45(&mut self) -> HEN45_W<13> { + pub fn hen45(&mut self) -> HEN45_W { HEN45_W::new(self) } #[doc = "Bit 14 - High detect enabled 46"] #[inline(always)] #[must_use] - pub fn hen46(&mut self) -> HEN46_W<14> { + pub fn hen46(&mut self) -> HEN46_W { HEN46_W::new(self) } #[doc = "Bit 15 - High detect enabled 47"] #[inline(always)] #[must_use] - pub fn hen47(&mut self) -> HEN47_W<15> { + pub fn hen47(&mut self) -> HEN47_W { HEN47_W::new(self) } #[doc = "Bit 16 - High detect enabled 48"] #[inline(always)] #[must_use] - pub fn hen48(&mut self) -> HEN48_W<16> { + pub fn hen48(&mut self) -> HEN48_W { HEN48_W::new(self) } #[doc = "Bit 17 - High detect enabled 49"] #[inline(always)] #[must_use] - pub fn hen49(&mut self) -> HEN49_W<17> { + pub fn hen49(&mut self) -> HEN49_W { HEN49_W::new(self) } #[doc = "Bit 18 - High detect enabled 50"] #[inline(always)] #[must_use] - pub fn hen50(&mut self) -> HEN50_W<18> { + pub fn hen50(&mut self) -> HEN50_W { HEN50_W::new(self) } #[doc = "Bit 19 - High detect enabled 51"] #[inline(always)] #[must_use] - pub fn hen51(&mut self) -> HEN51_W<19> { + pub fn hen51(&mut self) -> HEN51_W { HEN51_W::new(self) } #[doc = "Bit 20 - High detect enabled 52"] #[inline(always)] #[must_use] - pub fn hen52(&mut self) -> HEN52_W<20> { + pub fn hen52(&mut self) -> HEN52_W { HEN52_W::new(self) } #[doc = "Bit 21 - High detect enabled 53"] #[inline(always)] #[must_use] - pub fn hen53(&mut self) -> HEN53_W<21> { + pub fn hen53(&mut self) -> HEN53_W { HEN53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin High Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gphen1](index.html) module"] +#[doc = "GPIO Pin High Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gphen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gphen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPHEN1_SPEC; impl crate::RegisterSpec for GPHEN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gphen1::R](R) reader structure"] -impl crate::Readable for GPHEN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gphen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gphen1::R`](R) reader structure"] +impl crate::Readable for GPHEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gphen1::W`](W) writer structure"] impl crate::Writable for GPHEN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs index 12b55c2..507543e 100644 --- a/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs +++ b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_PUP_PDN_CNTRL0` reader - Resistor select for 0"] -pub type GPIO_PUP_PDN_CNTRL0_R = crate::FieldReader; +pub type GPIO_PUP_PDN_CNTRL0_R = crate::FieldReader; #[doc = "Resistor select for 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -53,10 +21,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for BP_PULL_A { + type Ux = u8; +} impl GPIO_PUP_PDN_CNTRL0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(BP_PULL_A::NONE), 1 => Some(BP_PULL_A::UP), @@ -64,39 +35,42 @@ impl GPIO_PUP_PDN_CNTRL0_R { _ => None, } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "No pull"] #[inline(always)] pub fn is_none(&self) -> bool { *self == BP_PULL_A::NONE } - #[doc = "Checks if the value of the field is `UP`"] + #[doc = "Pull up"] #[inline(always)] pub fn is_up(&self) -> bool { *self == BP_PULL_A::UP } - #[doc = "Checks if the value of the field is `DOWN`"] + #[doc = "Pull down"] #[inline(always)] pub fn is_down(&self) -> bool { *self == BP_PULL_A::DOWN } } #[doc = "Field `GPIO_PUP_PDN_CNTRL0` writer - Resistor select for 0"] -pub type GPIO_PUP_PDN_CNTRL0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG0_SPEC, u8, BP_PULL_A, 2, O>; -impl<'a, const O: u8> GPIO_PUP_PDN_CNTRL0_W<'a, O> { +pub type GPIO_PUP_PDN_CNTRL0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, BP_PULL_A>; +impl<'a, REG, const O: u8> GPIO_PUP_PDN_CNTRL0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "No pull"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(BP_PULL_A::NONE) } #[doc = "Pull up"] #[inline(always)] - pub fn up(self) -> &'a mut W { + pub fn up(self) -> &'a mut crate::W { self.variant(BP_PULL_A::UP) } #[doc = "Pull down"] #[inline(always)] - pub fn down(self) -> &'a mut W { + pub fn down(self) -> &'a mut crate::W { self.variant(BP_PULL_A::DOWN) } } @@ -242,122 +216,230 @@ impl R { GPIO_PUP_PDN_CNTRL15_R::new(((self.bits >> 30) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PUP_PDN_CNTRL_REG0") + .field( + "gpio_pup_pdn_cntrl0", + &format_args!("{}", self.gpio_pup_pdn_cntrl0().bits()), + ) + .field( + "gpio_pup_pdn_cntrl1", + &format_args!("{}", self.gpio_pup_pdn_cntrl1().bits()), + ) + .field( + "gpio_pup_pdn_cntrl2", + &format_args!("{}", self.gpio_pup_pdn_cntrl2().bits()), + ) + .field( + "gpio_pup_pdn_cntrl3", + &format_args!("{}", self.gpio_pup_pdn_cntrl3().bits()), + ) + .field( + "gpio_pup_pdn_cntrl4", + &format_args!("{}", self.gpio_pup_pdn_cntrl4().bits()), + ) + .field( + "gpio_pup_pdn_cntrl5", + &format_args!("{}", self.gpio_pup_pdn_cntrl5().bits()), + ) + .field( + "gpio_pup_pdn_cntrl6", + &format_args!("{}", self.gpio_pup_pdn_cntrl6().bits()), + ) + .field( + "gpio_pup_pdn_cntrl7", + &format_args!("{}", self.gpio_pup_pdn_cntrl7().bits()), + ) + .field( + "gpio_pup_pdn_cntrl8", + &format_args!("{}", self.gpio_pup_pdn_cntrl8().bits()), + ) + .field( + "gpio_pup_pdn_cntrl9", + &format_args!("{}", self.gpio_pup_pdn_cntrl9().bits()), + ) + .field( + "gpio_pup_pdn_cntrl10", + &format_args!("{}", self.gpio_pup_pdn_cntrl10().bits()), + ) + .field( + "gpio_pup_pdn_cntrl11", + &format_args!("{}", self.gpio_pup_pdn_cntrl11().bits()), + ) + .field( + "gpio_pup_pdn_cntrl12", + &format_args!("{}", self.gpio_pup_pdn_cntrl12().bits()), + ) + .field( + "gpio_pup_pdn_cntrl13", + &format_args!("{}", self.gpio_pup_pdn_cntrl13().bits()), + ) + .field( + "gpio_pup_pdn_cntrl14", + &format_args!("{}", self.gpio_pup_pdn_cntrl14().bits()), + ) + .field( + "gpio_pup_pdn_cntrl15", + &format_args!("{}", self.gpio_pup_pdn_cntrl15().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Resistor select for 0"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl0(&mut self) -> GPIO_PUP_PDN_CNTRL0_W<0> { + pub fn gpio_pup_pdn_cntrl0( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL0_W { GPIO_PUP_PDN_CNTRL0_W::new(self) } #[doc = "Bits 2:3 - Resistor select for 1"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl1(&mut self) -> GPIO_PUP_PDN_CNTRL1_W<2> { + pub fn gpio_pup_pdn_cntrl1( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL1_W { GPIO_PUP_PDN_CNTRL1_W::new(self) } #[doc = "Bits 4:5 - Resistor select for 2"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl2(&mut self) -> GPIO_PUP_PDN_CNTRL2_W<4> { + pub fn gpio_pup_pdn_cntrl2( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL2_W { GPIO_PUP_PDN_CNTRL2_W::new(self) } #[doc = "Bits 6:7 - Resistor select for 3"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl3(&mut self) -> GPIO_PUP_PDN_CNTRL3_W<6> { + pub fn gpio_pup_pdn_cntrl3( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL3_W { GPIO_PUP_PDN_CNTRL3_W::new(self) } #[doc = "Bits 8:9 - Resistor select for 4"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl4(&mut self) -> GPIO_PUP_PDN_CNTRL4_W<8> { + pub fn gpio_pup_pdn_cntrl4( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL4_W { GPIO_PUP_PDN_CNTRL4_W::new(self) } #[doc = "Bits 10:11 - Resistor select for 5"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl5(&mut self) -> GPIO_PUP_PDN_CNTRL5_W<10> { + pub fn gpio_pup_pdn_cntrl5( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL5_W { GPIO_PUP_PDN_CNTRL5_W::new(self) } #[doc = "Bits 12:13 - Resistor select for 6"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl6(&mut self) -> GPIO_PUP_PDN_CNTRL6_W<12> { + pub fn gpio_pup_pdn_cntrl6( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL6_W { GPIO_PUP_PDN_CNTRL6_W::new(self) } #[doc = "Bits 14:15 - Resistor select for 7"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl7(&mut self) -> GPIO_PUP_PDN_CNTRL7_W<14> { + pub fn gpio_pup_pdn_cntrl7( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL7_W { GPIO_PUP_PDN_CNTRL7_W::new(self) } #[doc = "Bits 16:17 - Resistor select for 8"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl8(&mut self) -> GPIO_PUP_PDN_CNTRL8_W<16> { + pub fn gpio_pup_pdn_cntrl8( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL8_W { GPIO_PUP_PDN_CNTRL8_W::new(self) } #[doc = "Bits 18:19 - Resistor select for 9"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl9(&mut self) -> GPIO_PUP_PDN_CNTRL9_W<18> { + pub fn gpio_pup_pdn_cntrl9( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL9_W { GPIO_PUP_PDN_CNTRL9_W::new(self) } #[doc = "Bits 20:21 - Resistor select for 10"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl10(&mut self) -> GPIO_PUP_PDN_CNTRL10_W<20> { + pub fn gpio_pup_pdn_cntrl10( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL10_W { GPIO_PUP_PDN_CNTRL10_W::new(self) } #[doc = "Bits 22:23 - Resistor select for 11"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl11(&mut self) -> GPIO_PUP_PDN_CNTRL11_W<22> { + pub fn gpio_pup_pdn_cntrl11( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL11_W { GPIO_PUP_PDN_CNTRL11_W::new(self) } #[doc = "Bits 24:25 - Resistor select for 12"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl12(&mut self) -> GPIO_PUP_PDN_CNTRL12_W<24> { + pub fn gpio_pup_pdn_cntrl12( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL12_W { GPIO_PUP_PDN_CNTRL12_W::new(self) } #[doc = "Bits 26:27 - Resistor select for 13"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl13(&mut self) -> GPIO_PUP_PDN_CNTRL13_W<26> { + pub fn gpio_pup_pdn_cntrl13( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL13_W { GPIO_PUP_PDN_CNTRL13_W::new(self) } #[doc = "Bits 28:29 - Resistor select for 14"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl14(&mut self) -> GPIO_PUP_PDN_CNTRL14_W<28> { + pub fn gpio_pup_pdn_cntrl14( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL14_W { GPIO_PUP_PDN_CNTRL14_W::new(self) } #[doc = "Bits 30:31 - Resistor select for 15"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl15(&mut self) -> GPIO_PUP_PDN_CNTRL15_W<30> { + pub fn gpio_pup_pdn_cntrl15( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL15_W { GPIO_PUP_PDN_CNTRL15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pull-up / Pull-down Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg0](index.html) module"] +#[doc = "GPIO Pull-up / Pull-down Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_PUP_PDN_CNTRL_REG0_SPEC; impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg0::R](R) reader structure"] -impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_pup_pdn_cntrl_reg0::R`](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pup_pdn_cntrl_reg0::W`](W) writer structure"] impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs index 49faec3..877b1ae 100644 --- a/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs +++ b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs @@ -1,121 +1,73 @@ #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Resistor select for 16"] pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; #[doc = "Field `GPIO_PUP_PDN_CNTRL16` reader - Resistor select for 16"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL16_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL16` writer - Resistor select for 16"] -pub type GPIO_PUP_PDN_CNTRL16_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL17` reader - Resistor select for 17"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL17_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL17` writer - Resistor select for 17"] -pub type GPIO_PUP_PDN_CNTRL17_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL18` reader - Resistor select for 18"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL18_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL18` writer - Resistor select for 18"] -pub type GPIO_PUP_PDN_CNTRL18_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL19` reader - Resistor select for 19"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL19_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL19` writer - Resistor select for 19"] -pub type GPIO_PUP_PDN_CNTRL19_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL20` reader - Resistor select for 20"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL20_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL20` writer - Resistor select for 20"] -pub type GPIO_PUP_PDN_CNTRL20_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL21` reader - Resistor select for 21"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL21_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL21` writer - Resistor select for 21"] -pub type GPIO_PUP_PDN_CNTRL21_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL22` reader - Resistor select for 22"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL22_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL22` writer - Resistor select for 22"] -pub type GPIO_PUP_PDN_CNTRL22_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL23` reader - Resistor select for 23"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL23_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL23` writer - Resistor select for 23"] -pub type GPIO_PUP_PDN_CNTRL23_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL24` reader - Resistor select for 24"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL24_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL24` writer - Resistor select for 24"] -pub type GPIO_PUP_PDN_CNTRL24_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL25` reader - Resistor select for 25"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL25_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL25` writer - Resistor select for 25"] -pub type GPIO_PUP_PDN_CNTRL25_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL26` reader - Resistor select for 26"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL26_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL26` writer - Resistor select for 26"] -pub type GPIO_PUP_PDN_CNTRL26_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL27` reader - Resistor select for 27"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL27_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL27` writer - Resistor select for 27"] -pub type GPIO_PUP_PDN_CNTRL27_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL28` reader - Resistor select for 28"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL28_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL28` writer - Resistor select for 28"] -pub type GPIO_PUP_PDN_CNTRL28_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL29` reader - Resistor select for 29"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL29_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL29` writer - Resistor select for 29"] -pub type GPIO_PUP_PDN_CNTRL29_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL30` reader - Resistor select for 30"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL30_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL30` writer - Resistor select for 30"] -pub type GPIO_PUP_PDN_CNTRL30_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL31` reader - Resistor select for 31"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL31_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL16` writer - Resistor select for 16"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL16_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL17` writer - Resistor select for 17"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL17_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL18` writer - Resistor select for 18"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL18_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL19` writer - Resistor select for 19"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL19_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL20` writer - Resistor select for 20"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL20_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL21` writer - Resistor select for 21"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL21_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL22` writer - Resistor select for 22"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL22_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL23` writer - Resistor select for 23"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL23_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL24` writer - Resistor select for 24"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL24_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL25` writer - Resistor select for 25"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL25_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL26` writer - Resistor select for 26"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL26_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL27` writer - Resistor select for 27"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL27_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL28` writer - Resistor select for 28"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL28_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL29` writer - Resistor select for 29"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL29_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL30` writer - Resistor select for 30"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL30_W; #[doc = "Field `GPIO_PUP_PDN_CNTRL31` writer - Resistor select for 31"] -pub type GPIO_PUP_PDN_CNTRL31_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL31_W; impl R { #[doc = "Bits 0:1 - Resistor select for 16"] #[inline(always)] @@ -198,122 +150,230 @@ impl R { GPIO_PUP_PDN_CNTRL31_R::new(((self.bits >> 30) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PUP_PDN_CNTRL_REG1") + .field( + "gpio_pup_pdn_cntrl16", + &format_args!("{}", self.gpio_pup_pdn_cntrl16().bits()), + ) + .field( + "gpio_pup_pdn_cntrl17", + &format_args!("{}", self.gpio_pup_pdn_cntrl17().bits()), + ) + .field( + "gpio_pup_pdn_cntrl18", + &format_args!("{}", self.gpio_pup_pdn_cntrl18().bits()), + ) + .field( + "gpio_pup_pdn_cntrl19", + &format_args!("{}", self.gpio_pup_pdn_cntrl19().bits()), + ) + .field( + "gpio_pup_pdn_cntrl20", + &format_args!("{}", self.gpio_pup_pdn_cntrl20().bits()), + ) + .field( + "gpio_pup_pdn_cntrl21", + &format_args!("{}", self.gpio_pup_pdn_cntrl21().bits()), + ) + .field( + "gpio_pup_pdn_cntrl22", + &format_args!("{}", self.gpio_pup_pdn_cntrl22().bits()), + ) + .field( + "gpio_pup_pdn_cntrl23", + &format_args!("{}", self.gpio_pup_pdn_cntrl23().bits()), + ) + .field( + "gpio_pup_pdn_cntrl24", + &format_args!("{}", self.gpio_pup_pdn_cntrl24().bits()), + ) + .field( + "gpio_pup_pdn_cntrl25", + &format_args!("{}", self.gpio_pup_pdn_cntrl25().bits()), + ) + .field( + "gpio_pup_pdn_cntrl26", + &format_args!("{}", self.gpio_pup_pdn_cntrl26().bits()), + ) + .field( + "gpio_pup_pdn_cntrl27", + &format_args!("{}", self.gpio_pup_pdn_cntrl27().bits()), + ) + .field( + "gpio_pup_pdn_cntrl28", + &format_args!("{}", self.gpio_pup_pdn_cntrl28().bits()), + ) + .field( + "gpio_pup_pdn_cntrl29", + &format_args!("{}", self.gpio_pup_pdn_cntrl29().bits()), + ) + .field( + "gpio_pup_pdn_cntrl30", + &format_args!("{}", self.gpio_pup_pdn_cntrl30().bits()), + ) + .field( + "gpio_pup_pdn_cntrl31", + &format_args!("{}", self.gpio_pup_pdn_cntrl31().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Resistor select for 16"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl16(&mut self) -> GPIO_PUP_PDN_CNTRL16_W<0> { + pub fn gpio_pup_pdn_cntrl16( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL16_W { GPIO_PUP_PDN_CNTRL16_W::new(self) } #[doc = "Bits 2:3 - Resistor select for 17"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl17(&mut self) -> GPIO_PUP_PDN_CNTRL17_W<2> { + pub fn gpio_pup_pdn_cntrl17( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL17_W { GPIO_PUP_PDN_CNTRL17_W::new(self) } #[doc = "Bits 4:5 - Resistor select for 18"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl18(&mut self) -> GPIO_PUP_PDN_CNTRL18_W<4> { + pub fn gpio_pup_pdn_cntrl18( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL18_W { GPIO_PUP_PDN_CNTRL18_W::new(self) } #[doc = "Bits 6:7 - Resistor select for 19"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl19(&mut self) -> GPIO_PUP_PDN_CNTRL19_W<6> { + pub fn gpio_pup_pdn_cntrl19( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL19_W { GPIO_PUP_PDN_CNTRL19_W::new(self) } #[doc = "Bits 8:9 - Resistor select for 20"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl20(&mut self) -> GPIO_PUP_PDN_CNTRL20_W<8> { + pub fn gpio_pup_pdn_cntrl20( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL20_W { GPIO_PUP_PDN_CNTRL20_W::new(self) } #[doc = "Bits 10:11 - Resistor select for 21"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl21(&mut self) -> GPIO_PUP_PDN_CNTRL21_W<10> { + pub fn gpio_pup_pdn_cntrl21( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL21_W { GPIO_PUP_PDN_CNTRL21_W::new(self) } #[doc = "Bits 12:13 - Resistor select for 22"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl22(&mut self) -> GPIO_PUP_PDN_CNTRL22_W<12> { + pub fn gpio_pup_pdn_cntrl22( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL22_W { GPIO_PUP_PDN_CNTRL22_W::new(self) } #[doc = "Bits 14:15 - Resistor select for 23"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl23(&mut self) -> GPIO_PUP_PDN_CNTRL23_W<14> { + pub fn gpio_pup_pdn_cntrl23( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL23_W { GPIO_PUP_PDN_CNTRL23_W::new(self) } #[doc = "Bits 16:17 - Resistor select for 24"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl24(&mut self) -> GPIO_PUP_PDN_CNTRL24_W<16> { + pub fn gpio_pup_pdn_cntrl24( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL24_W { GPIO_PUP_PDN_CNTRL24_W::new(self) } #[doc = "Bits 18:19 - Resistor select for 25"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl25(&mut self) -> GPIO_PUP_PDN_CNTRL25_W<18> { + pub fn gpio_pup_pdn_cntrl25( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL25_W { GPIO_PUP_PDN_CNTRL25_W::new(self) } #[doc = "Bits 20:21 - Resistor select for 26"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl26(&mut self) -> GPIO_PUP_PDN_CNTRL26_W<20> { + pub fn gpio_pup_pdn_cntrl26( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL26_W { GPIO_PUP_PDN_CNTRL26_W::new(self) } #[doc = "Bits 22:23 - Resistor select for 27"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl27(&mut self) -> GPIO_PUP_PDN_CNTRL27_W<22> { + pub fn gpio_pup_pdn_cntrl27( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL27_W { GPIO_PUP_PDN_CNTRL27_W::new(self) } #[doc = "Bits 24:25 - Resistor select for 28"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl28(&mut self) -> GPIO_PUP_PDN_CNTRL28_W<24> { + pub fn gpio_pup_pdn_cntrl28( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL28_W { GPIO_PUP_PDN_CNTRL28_W::new(self) } #[doc = "Bits 26:27 - Resistor select for 29"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl29(&mut self) -> GPIO_PUP_PDN_CNTRL29_W<26> { + pub fn gpio_pup_pdn_cntrl29( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL29_W { GPIO_PUP_PDN_CNTRL29_W::new(self) } #[doc = "Bits 28:29 - Resistor select for 30"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl30(&mut self) -> GPIO_PUP_PDN_CNTRL30_W<28> { + pub fn gpio_pup_pdn_cntrl30( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL30_W { GPIO_PUP_PDN_CNTRL30_W::new(self) } #[doc = "Bits 30:31 - Resistor select for 31"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl31(&mut self) -> GPIO_PUP_PDN_CNTRL31_W<30> { + pub fn gpio_pup_pdn_cntrl31( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL31_W { GPIO_PUP_PDN_CNTRL31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pull-up / Pull-down Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg1](index.html) module"] +#[doc = "GPIO Pull-up / Pull-down Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_PUP_PDN_CNTRL_REG1_SPEC; impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg1::R](R) reader structure"] -impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_pup_pdn_cntrl_reg1::R`](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pup_pdn_cntrl_reg1::W`](W) writer structure"] impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs index 67047c9..dfd838d 100644 --- a/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs +++ b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs @@ -1,121 +1,73 @@ #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Resistor select for 32"] pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; #[doc = "Field `GPIO_PUP_PDN_CNTRL32` reader - Resistor select for 32"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL32_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL32` writer - Resistor select for 32"] -pub type GPIO_PUP_PDN_CNTRL32_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL33` reader - Resistor select for 33"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL33_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL33` writer - Resistor select for 33"] -pub type GPIO_PUP_PDN_CNTRL33_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL34` reader - Resistor select for 34"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL34_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL34` writer - Resistor select for 34"] -pub type GPIO_PUP_PDN_CNTRL34_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL35` reader - Resistor select for 35"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL35_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL35` writer - Resistor select for 35"] -pub type GPIO_PUP_PDN_CNTRL35_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL36` reader - Resistor select for 36"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL36_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL36` writer - Resistor select for 36"] -pub type GPIO_PUP_PDN_CNTRL36_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL37` reader - Resistor select for 37"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL37_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL37` writer - Resistor select for 37"] -pub type GPIO_PUP_PDN_CNTRL37_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL38` reader - Resistor select for 38"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL38_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL38` writer - Resistor select for 38"] -pub type GPIO_PUP_PDN_CNTRL38_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL39` reader - Resistor select for 39"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL39_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL39` writer - Resistor select for 39"] -pub type GPIO_PUP_PDN_CNTRL39_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL40` reader - Resistor select for 40"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL40_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL40` writer - Resistor select for 40"] -pub type GPIO_PUP_PDN_CNTRL40_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL41` reader - Resistor select for 41"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL41_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL41` writer - Resistor select for 41"] -pub type GPIO_PUP_PDN_CNTRL41_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL42` reader - Resistor select for 42"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL42_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL42` writer - Resistor select for 42"] -pub type GPIO_PUP_PDN_CNTRL42_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL43` reader - Resistor select for 43"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL43_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL43` writer - Resistor select for 43"] -pub type GPIO_PUP_PDN_CNTRL43_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL44` reader - Resistor select for 44"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL44_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL44` writer - Resistor select for 44"] -pub type GPIO_PUP_PDN_CNTRL44_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL45` reader - Resistor select for 45"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL45_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL45` writer - Resistor select for 45"] -pub type GPIO_PUP_PDN_CNTRL45_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL46` reader - Resistor select for 46"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL46_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL46` writer - Resistor select for 46"] -pub type GPIO_PUP_PDN_CNTRL46_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL47` reader - Resistor select for 47"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL47_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL32` writer - Resistor select for 32"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL32_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL33` writer - Resistor select for 33"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL33_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL34` writer - Resistor select for 34"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL34_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL35` writer - Resistor select for 35"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL35_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL36` writer - Resistor select for 36"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL36_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL37` writer - Resistor select for 37"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL37_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL38` writer - Resistor select for 38"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL38_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL39` writer - Resistor select for 39"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL39_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL40` writer - Resistor select for 40"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL40_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL41` writer - Resistor select for 41"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL41_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL42` writer - Resistor select for 42"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL42_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL43` writer - Resistor select for 43"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL43_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL44` writer - Resistor select for 44"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL44_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL45` writer - Resistor select for 45"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL45_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL46` writer - Resistor select for 46"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL46_W; #[doc = "Field `GPIO_PUP_PDN_CNTRL47` writer - Resistor select for 47"] -pub type GPIO_PUP_PDN_CNTRL47_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL47_W; impl R { #[doc = "Bits 0:1 - Resistor select for 32"] #[inline(always)] @@ -198,122 +150,230 @@ impl R { GPIO_PUP_PDN_CNTRL47_R::new(((self.bits >> 30) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PUP_PDN_CNTRL_REG2") + .field( + "gpio_pup_pdn_cntrl32", + &format_args!("{}", self.gpio_pup_pdn_cntrl32().bits()), + ) + .field( + "gpio_pup_pdn_cntrl33", + &format_args!("{}", self.gpio_pup_pdn_cntrl33().bits()), + ) + .field( + "gpio_pup_pdn_cntrl34", + &format_args!("{}", self.gpio_pup_pdn_cntrl34().bits()), + ) + .field( + "gpio_pup_pdn_cntrl35", + &format_args!("{}", self.gpio_pup_pdn_cntrl35().bits()), + ) + .field( + "gpio_pup_pdn_cntrl36", + &format_args!("{}", self.gpio_pup_pdn_cntrl36().bits()), + ) + .field( + "gpio_pup_pdn_cntrl37", + &format_args!("{}", self.gpio_pup_pdn_cntrl37().bits()), + ) + .field( + "gpio_pup_pdn_cntrl38", + &format_args!("{}", self.gpio_pup_pdn_cntrl38().bits()), + ) + .field( + "gpio_pup_pdn_cntrl39", + &format_args!("{}", self.gpio_pup_pdn_cntrl39().bits()), + ) + .field( + "gpio_pup_pdn_cntrl40", + &format_args!("{}", self.gpio_pup_pdn_cntrl40().bits()), + ) + .field( + "gpio_pup_pdn_cntrl41", + &format_args!("{}", self.gpio_pup_pdn_cntrl41().bits()), + ) + .field( + "gpio_pup_pdn_cntrl42", + &format_args!("{}", self.gpio_pup_pdn_cntrl42().bits()), + ) + .field( + "gpio_pup_pdn_cntrl43", + &format_args!("{}", self.gpio_pup_pdn_cntrl43().bits()), + ) + .field( + "gpio_pup_pdn_cntrl44", + &format_args!("{}", self.gpio_pup_pdn_cntrl44().bits()), + ) + .field( + "gpio_pup_pdn_cntrl45", + &format_args!("{}", self.gpio_pup_pdn_cntrl45().bits()), + ) + .field( + "gpio_pup_pdn_cntrl46", + &format_args!("{}", self.gpio_pup_pdn_cntrl46().bits()), + ) + .field( + "gpio_pup_pdn_cntrl47", + &format_args!("{}", self.gpio_pup_pdn_cntrl47().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Resistor select for 32"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl32(&mut self) -> GPIO_PUP_PDN_CNTRL32_W<0> { + pub fn gpio_pup_pdn_cntrl32( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL32_W { GPIO_PUP_PDN_CNTRL32_W::new(self) } #[doc = "Bits 2:3 - Resistor select for 33"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl33(&mut self) -> GPIO_PUP_PDN_CNTRL33_W<2> { + pub fn gpio_pup_pdn_cntrl33( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL33_W { GPIO_PUP_PDN_CNTRL33_W::new(self) } #[doc = "Bits 4:5 - Resistor select for 34"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl34(&mut self) -> GPIO_PUP_PDN_CNTRL34_W<4> { + pub fn gpio_pup_pdn_cntrl34( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL34_W { GPIO_PUP_PDN_CNTRL34_W::new(self) } #[doc = "Bits 6:7 - Resistor select for 35"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl35(&mut self) -> GPIO_PUP_PDN_CNTRL35_W<6> { + pub fn gpio_pup_pdn_cntrl35( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL35_W { GPIO_PUP_PDN_CNTRL35_W::new(self) } #[doc = "Bits 8:9 - Resistor select for 36"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl36(&mut self) -> GPIO_PUP_PDN_CNTRL36_W<8> { + pub fn gpio_pup_pdn_cntrl36( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL36_W { GPIO_PUP_PDN_CNTRL36_W::new(self) } #[doc = "Bits 10:11 - Resistor select for 37"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl37(&mut self) -> GPIO_PUP_PDN_CNTRL37_W<10> { + pub fn gpio_pup_pdn_cntrl37( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL37_W { GPIO_PUP_PDN_CNTRL37_W::new(self) } #[doc = "Bits 12:13 - Resistor select for 38"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl38(&mut self) -> GPIO_PUP_PDN_CNTRL38_W<12> { + pub fn gpio_pup_pdn_cntrl38( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL38_W { GPIO_PUP_PDN_CNTRL38_W::new(self) } #[doc = "Bits 14:15 - Resistor select for 39"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl39(&mut self) -> GPIO_PUP_PDN_CNTRL39_W<14> { + pub fn gpio_pup_pdn_cntrl39( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL39_W { GPIO_PUP_PDN_CNTRL39_W::new(self) } #[doc = "Bits 16:17 - Resistor select for 40"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl40(&mut self) -> GPIO_PUP_PDN_CNTRL40_W<16> { + pub fn gpio_pup_pdn_cntrl40( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL40_W { GPIO_PUP_PDN_CNTRL40_W::new(self) } #[doc = "Bits 18:19 - Resistor select for 41"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl41(&mut self) -> GPIO_PUP_PDN_CNTRL41_W<18> { + pub fn gpio_pup_pdn_cntrl41( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL41_W { GPIO_PUP_PDN_CNTRL41_W::new(self) } #[doc = "Bits 20:21 - Resistor select for 42"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl42(&mut self) -> GPIO_PUP_PDN_CNTRL42_W<20> { + pub fn gpio_pup_pdn_cntrl42( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL42_W { GPIO_PUP_PDN_CNTRL42_W::new(self) } #[doc = "Bits 22:23 - Resistor select for 43"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl43(&mut self) -> GPIO_PUP_PDN_CNTRL43_W<22> { + pub fn gpio_pup_pdn_cntrl43( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL43_W { GPIO_PUP_PDN_CNTRL43_W::new(self) } #[doc = "Bits 24:25 - Resistor select for 44"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl44(&mut self) -> GPIO_PUP_PDN_CNTRL44_W<24> { + pub fn gpio_pup_pdn_cntrl44( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL44_W { GPIO_PUP_PDN_CNTRL44_W::new(self) } #[doc = "Bits 26:27 - Resistor select for 45"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl45(&mut self) -> GPIO_PUP_PDN_CNTRL45_W<26> { + pub fn gpio_pup_pdn_cntrl45( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL45_W { GPIO_PUP_PDN_CNTRL45_W::new(self) } #[doc = "Bits 28:29 - Resistor select for 46"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl46(&mut self) -> GPIO_PUP_PDN_CNTRL46_W<28> { + pub fn gpio_pup_pdn_cntrl46( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL46_W { GPIO_PUP_PDN_CNTRL46_W::new(self) } #[doc = "Bits 30:31 - Resistor select for 47"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl47(&mut self) -> GPIO_PUP_PDN_CNTRL47_W<30> { + pub fn gpio_pup_pdn_cntrl47( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL47_W { GPIO_PUP_PDN_CNTRL47_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pull-up / Pull-down Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg2](index.html) module"] +#[doc = "GPIO Pull-up / Pull-down Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_PUP_PDN_CNTRL_REG2_SPEC; impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg2::R](R) reader structure"] -impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg2::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_pup_pdn_cntrl_reg2::R`](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pup_pdn_cntrl_reg2::W`](W) writer structure"] impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs index 61b9329..52b564a 100644 --- a/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs +++ b/crates/bcm2835-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs @@ -1,71 +1,33 @@ #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Resistor select for 48"] pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; #[doc = "Field `GPIO_PUP_PDN_CNTRL48` reader - Resistor select for 48"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL48_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL48` writer - Resistor select for 48"] -pub type GPIO_PUP_PDN_CNTRL48_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL49` reader - Resistor select for 49"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL49_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL49` writer - Resistor select for 49"] -pub type GPIO_PUP_PDN_CNTRL49_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL50` reader - Resistor select for 50"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL50_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL50` writer - Resistor select for 50"] -pub type GPIO_PUP_PDN_CNTRL50_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL51` reader - Resistor select for 51"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL51_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL51` writer - Resistor select for 51"] -pub type GPIO_PUP_PDN_CNTRL51_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL52` reader - Resistor select for 52"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL52_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL52` writer - Resistor select for 52"] -pub type GPIO_PUP_PDN_CNTRL52_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL53` reader - Resistor select for 53"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL53_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL48` writer - Resistor select for 48"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL48_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL49` writer - Resistor select for 49"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL49_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL50` writer - Resistor select for 50"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL50_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL51` writer - Resistor select for 51"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL51_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL52` writer - Resistor select for 52"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL52_W; #[doc = "Field `GPIO_PUP_PDN_CNTRL53` writer - Resistor select for 53"] -pub type GPIO_PUP_PDN_CNTRL53_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL53_W; impl R { #[doc = "Bits 0:1 - Resistor select for 48"] #[inline(always)] @@ -98,62 +60,110 @@ impl R { GPIO_PUP_PDN_CNTRL53_R::new(((self.bits >> 10) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PUP_PDN_CNTRL_REG3") + .field( + "gpio_pup_pdn_cntrl48", + &format_args!("{}", self.gpio_pup_pdn_cntrl48().bits()), + ) + .field( + "gpio_pup_pdn_cntrl49", + &format_args!("{}", self.gpio_pup_pdn_cntrl49().bits()), + ) + .field( + "gpio_pup_pdn_cntrl50", + &format_args!("{}", self.gpio_pup_pdn_cntrl50().bits()), + ) + .field( + "gpio_pup_pdn_cntrl51", + &format_args!("{}", self.gpio_pup_pdn_cntrl51().bits()), + ) + .field( + "gpio_pup_pdn_cntrl52", + &format_args!("{}", self.gpio_pup_pdn_cntrl52().bits()), + ) + .field( + "gpio_pup_pdn_cntrl53", + &format_args!("{}", self.gpio_pup_pdn_cntrl53().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Resistor select for 48"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl48(&mut self) -> GPIO_PUP_PDN_CNTRL48_W<0> { + pub fn gpio_pup_pdn_cntrl48( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL48_W { GPIO_PUP_PDN_CNTRL48_W::new(self) } #[doc = "Bits 2:3 - Resistor select for 49"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl49(&mut self) -> GPIO_PUP_PDN_CNTRL49_W<2> { + pub fn gpio_pup_pdn_cntrl49( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL49_W { GPIO_PUP_PDN_CNTRL49_W::new(self) } #[doc = "Bits 4:5 - Resistor select for 50"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl50(&mut self) -> GPIO_PUP_PDN_CNTRL50_W<4> { + pub fn gpio_pup_pdn_cntrl50( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL50_W { GPIO_PUP_PDN_CNTRL50_W::new(self) } #[doc = "Bits 6:7 - Resistor select for 51"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl51(&mut self) -> GPIO_PUP_PDN_CNTRL51_W<6> { + pub fn gpio_pup_pdn_cntrl51( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL51_W { GPIO_PUP_PDN_CNTRL51_W::new(self) } #[doc = "Bits 8:9 - Resistor select for 52"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl52(&mut self) -> GPIO_PUP_PDN_CNTRL52_W<8> { + pub fn gpio_pup_pdn_cntrl52( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL52_W { GPIO_PUP_PDN_CNTRL52_W::new(self) } #[doc = "Bits 10:11 - Resistor select for 53"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl53(&mut self) -> GPIO_PUP_PDN_CNTRL53_W<10> { + pub fn gpio_pup_pdn_cntrl53( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL53_W { GPIO_PUP_PDN_CNTRL53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pull-up / Pull-down Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg3](index.html) module"] +#[doc = "GPIO Pull-up / Pull-down Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_PUP_PDN_CNTRL_REG3_SPEC; impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg3::R](R) reader structure"] -impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg3::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_pup_pdn_cntrl_reg3::R`](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pup_pdn_cntrl_reg3::W`](W) writer structure"] impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gplen0.rs b/crates/bcm2835-lpa/src/gpio/gplen0.rs index 54f51bd..bfac268 100644 --- a/crates/bcm2835-lpa/src/gpio/gplen0.rs +++ b/crates/bcm2835-lpa/src/gpio/gplen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPLEN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPLEN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LEN0` reader - Low detect enabled 0"] -pub type LEN0_R = crate::BitReader; +pub type LEN0_R = crate::BitReader; #[doc = "Field `LEN0` writer - Low detect enabled 0"] -pub type LEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN1` reader - Low detect enabled 1"] -pub type LEN1_R = crate::BitReader; +pub type LEN1_R = crate::BitReader; #[doc = "Field `LEN1` writer - Low detect enabled 1"] -pub type LEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN2` reader - Low detect enabled 2"] -pub type LEN2_R = crate::BitReader; +pub type LEN2_R = crate::BitReader; #[doc = "Field `LEN2` writer - Low detect enabled 2"] -pub type LEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN3` reader - Low detect enabled 3"] -pub type LEN3_R = crate::BitReader; +pub type LEN3_R = crate::BitReader; #[doc = "Field `LEN3` writer - Low detect enabled 3"] -pub type LEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN4` reader - Low detect enabled 4"] -pub type LEN4_R = crate::BitReader; +pub type LEN4_R = crate::BitReader; #[doc = "Field `LEN4` writer - Low detect enabled 4"] -pub type LEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN5` reader - Low detect enabled 5"] -pub type LEN5_R = crate::BitReader; +pub type LEN5_R = crate::BitReader; #[doc = "Field `LEN5` writer - Low detect enabled 5"] -pub type LEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN6` reader - Low detect enabled 6"] -pub type LEN6_R = crate::BitReader; +pub type LEN6_R = crate::BitReader; #[doc = "Field `LEN6` writer - Low detect enabled 6"] -pub type LEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN7` reader - Low detect enabled 7"] -pub type LEN7_R = crate::BitReader; +pub type LEN7_R = crate::BitReader; #[doc = "Field `LEN7` writer - Low detect enabled 7"] -pub type LEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN8` reader - Low detect enabled 8"] -pub type LEN8_R = crate::BitReader; +pub type LEN8_R = crate::BitReader; #[doc = "Field `LEN8` writer - Low detect enabled 8"] -pub type LEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN9` reader - Low detect enabled 9"] -pub type LEN9_R = crate::BitReader; +pub type LEN9_R = crate::BitReader; #[doc = "Field `LEN9` writer - Low detect enabled 9"] -pub type LEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN10` reader - Low detect enabled 10"] -pub type LEN10_R = crate::BitReader; +pub type LEN10_R = crate::BitReader; #[doc = "Field `LEN10` writer - Low detect enabled 10"] -pub type LEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN11` reader - Low detect enabled 11"] -pub type LEN11_R = crate::BitReader; +pub type LEN11_R = crate::BitReader; #[doc = "Field `LEN11` writer - Low detect enabled 11"] -pub type LEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN12` reader - Low detect enabled 12"] -pub type LEN12_R = crate::BitReader; +pub type LEN12_R = crate::BitReader; #[doc = "Field `LEN12` writer - Low detect enabled 12"] -pub type LEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN13` reader - Low detect enabled 13"] -pub type LEN13_R = crate::BitReader; +pub type LEN13_R = crate::BitReader; #[doc = "Field `LEN13` writer - Low detect enabled 13"] -pub type LEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN14` reader - Low detect enabled 14"] -pub type LEN14_R = crate::BitReader; +pub type LEN14_R = crate::BitReader; #[doc = "Field `LEN14` writer - Low detect enabled 14"] -pub type LEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN15` reader - Low detect enabled 15"] -pub type LEN15_R = crate::BitReader; +pub type LEN15_R = crate::BitReader; #[doc = "Field `LEN15` writer - Low detect enabled 15"] -pub type LEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN16` reader - Low detect enabled 16"] -pub type LEN16_R = crate::BitReader; +pub type LEN16_R = crate::BitReader; #[doc = "Field `LEN16` writer - Low detect enabled 16"] -pub type LEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN17` reader - Low detect enabled 17"] -pub type LEN17_R = crate::BitReader; +pub type LEN17_R = crate::BitReader; #[doc = "Field `LEN17` writer - Low detect enabled 17"] -pub type LEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN18` reader - Low detect enabled 18"] -pub type LEN18_R = crate::BitReader; +pub type LEN18_R = crate::BitReader; #[doc = "Field `LEN18` writer - Low detect enabled 18"] -pub type LEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN19` reader - Low detect enabled 19"] -pub type LEN19_R = crate::BitReader; +pub type LEN19_R = crate::BitReader; #[doc = "Field `LEN19` writer - Low detect enabled 19"] -pub type LEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN20` reader - Low detect enabled 20"] -pub type LEN20_R = crate::BitReader; +pub type LEN20_R = crate::BitReader; #[doc = "Field `LEN20` writer - Low detect enabled 20"] -pub type LEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN21` reader - Low detect enabled 21"] -pub type LEN21_R = crate::BitReader; +pub type LEN21_R = crate::BitReader; #[doc = "Field `LEN21` writer - Low detect enabled 21"] -pub type LEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN22` reader - Low detect enabled 22"] -pub type LEN22_R = crate::BitReader; +pub type LEN22_R = crate::BitReader; #[doc = "Field `LEN22` writer - Low detect enabled 22"] -pub type LEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN23` reader - Low detect enabled 23"] -pub type LEN23_R = crate::BitReader; +pub type LEN23_R = crate::BitReader; #[doc = "Field `LEN23` writer - Low detect enabled 23"] -pub type LEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN24` reader - Low detect enabled 24"] -pub type LEN24_R = crate::BitReader; +pub type LEN24_R = crate::BitReader; #[doc = "Field `LEN24` writer - Low detect enabled 24"] -pub type LEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN25` reader - Low detect enabled 25"] -pub type LEN25_R = crate::BitReader; +pub type LEN25_R = crate::BitReader; #[doc = "Field `LEN25` writer - Low detect enabled 25"] -pub type LEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN26` reader - Low detect enabled 26"] -pub type LEN26_R = crate::BitReader; +pub type LEN26_R = crate::BitReader; #[doc = "Field `LEN26` writer - Low detect enabled 26"] -pub type LEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN27` reader - Low detect enabled 27"] -pub type LEN27_R = crate::BitReader; +pub type LEN27_R = crate::BitReader; #[doc = "Field `LEN27` writer - Low detect enabled 27"] -pub type LEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN28` reader - Low detect enabled 28"] -pub type LEN28_R = crate::BitReader; +pub type LEN28_R = crate::BitReader; #[doc = "Field `LEN28` writer - Low detect enabled 28"] -pub type LEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN29` reader - Low detect enabled 29"] -pub type LEN29_R = crate::BitReader; +pub type LEN29_R = crate::BitReader; #[doc = "Field `LEN29` writer - Low detect enabled 29"] -pub type LEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN30` reader - Low detect enabled 30"] -pub type LEN30_R = crate::BitReader; +pub type LEN30_R = crate::BitReader; #[doc = "Field `LEN30` writer - Low detect enabled 30"] -pub type LEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN31` reader - Low detect enabled 31"] -pub type LEN31_R = crate::BitReader; +pub type LEN31_R = crate::BitReader; #[doc = "Field `LEN31` writer - Low detect enabled 31"] -pub type LEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Low detect enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { LEN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPLEN0") + .field("len0", &format_args!("{}", self.len0().bit())) + .field("len1", &format_args!("{}", self.len1().bit())) + .field("len2", &format_args!("{}", self.len2().bit())) + .field("len3", &format_args!("{}", self.len3().bit())) + .field("len4", &format_args!("{}", self.len4().bit())) + .field("len5", &format_args!("{}", self.len5().bit())) + .field("len6", &format_args!("{}", self.len6().bit())) + .field("len7", &format_args!("{}", self.len7().bit())) + .field("len8", &format_args!("{}", self.len8().bit())) + .field("len9", &format_args!("{}", self.len9().bit())) + .field("len10", &format_args!("{}", self.len10().bit())) + .field("len11", &format_args!("{}", self.len11().bit())) + .field("len12", &format_args!("{}", self.len12().bit())) + .field("len13", &format_args!("{}", self.len13().bit())) + .field("len14", &format_args!("{}", self.len14().bit())) + .field("len15", &format_args!("{}", self.len15().bit())) + .field("len16", &format_args!("{}", self.len16().bit())) + .field("len17", &format_args!("{}", self.len17().bit())) + .field("len18", &format_args!("{}", self.len18().bit())) + .field("len19", &format_args!("{}", self.len19().bit())) + .field("len20", &format_args!("{}", self.len20().bit())) + .field("len21", &format_args!("{}", self.len21().bit())) + .field("len22", &format_args!("{}", self.len22().bit())) + .field("len23", &format_args!("{}", self.len23().bit())) + .field("len24", &format_args!("{}", self.len24().bit())) + .field("len25", &format_args!("{}", self.len25().bit())) + .field("len26", &format_args!("{}", self.len26().bit())) + .field("len27", &format_args!("{}", self.len27().bit())) + .field("len28", &format_args!("{}", self.len28().bit())) + .field("len29", &format_args!("{}", self.len29().bit())) + .field("len30", &format_args!("{}", self.len30().bit())) + .field("len31", &format_args!("{}", self.len31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Low detect enabled 0"] #[inline(always)] #[must_use] - pub fn len0(&mut self) -> LEN0_W<0> { + pub fn len0(&mut self) -> LEN0_W { LEN0_W::new(self) } #[doc = "Bit 1 - Low detect enabled 1"] #[inline(always)] #[must_use] - pub fn len1(&mut self) -> LEN1_W<1> { + pub fn len1(&mut self) -> LEN1_W { LEN1_W::new(self) } #[doc = "Bit 2 - Low detect enabled 2"] #[inline(always)] #[must_use] - pub fn len2(&mut self) -> LEN2_W<2> { + pub fn len2(&mut self) -> LEN2_W { LEN2_W::new(self) } #[doc = "Bit 3 - Low detect enabled 3"] #[inline(always)] #[must_use] - pub fn len3(&mut self) -> LEN3_W<3> { + pub fn len3(&mut self) -> LEN3_W { LEN3_W::new(self) } #[doc = "Bit 4 - Low detect enabled 4"] #[inline(always)] #[must_use] - pub fn len4(&mut self) -> LEN4_W<4> { + pub fn len4(&mut self) -> LEN4_W { LEN4_W::new(self) } #[doc = "Bit 5 - Low detect enabled 5"] #[inline(always)] #[must_use] - pub fn len5(&mut self) -> LEN5_W<5> { + pub fn len5(&mut self) -> LEN5_W { LEN5_W::new(self) } #[doc = "Bit 6 - Low detect enabled 6"] #[inline(always)] #[must_use] - pub fn len6(&mut self) -> LEN6_W<6> { + pub fn len6(&mut self) -> LEN6_W { LEN6_W::new(self) } #[doc = "Bit 7 - Low detect enabled 7"] #[inline(always)] #[must_use] - pub fn len7(&mut self) -> LEN7_W<7> { + pub fn len7(&mut self) -> LEN7_W { LEN7_W::new(self) } #[doc = "Bit 8 - Low detect enabled 8"] #[inline(always)] #[must_use] - pub fn len8(&mut self) -> LEN8_W<8> { + pub fn len8(&mut self) -> LEN8_W { LEN8_W::new(self) } #[doc = "Bit 9 - Low detect enabled 9"] #[inline(always)] #[must_use] - pub fn len9(&mut self) -> LEN9_W<9> { + pub fn len9(&mut self) -> LEN9_W { LEN9_W::new(self) } #[doc = "Bit 10 - Low detect enabled 10"] #[inline(always)] #[must_use] - pub fn len10(&mut self) -> LEN10_W<10> { + pub fn len10(&mut self) -> LEN10_W { LEN10_W::new(self) } #[doc = "Bit 11 - Low detect enabled 11"] #[inline(always)] #[must_use] - pub fn len11(&mut self) -> LEN11_W<11> { + pub fn len11(&mut self) -> LEN11_W { LEN11_W::new(self) } #[doc = "Bit 12 - Low detect enabled 12"] #[inline(always)] #[must_use] - pub fn len12(&mut self) -> LEN12_W<12> { + pub fn len12(&mut self) -> LEN12_W { LEN12_W::new(self) } #[doc = "Bit 13 - Low detect enabled 13"] #[inline(always)] #[must_use] - pub fn len13(&mut self) -> LEN13_W<13> { + pub fn len13(&mut self) -> LEN13_W { LEN13_W::new(self) } #[doc = "Bit 14 - Low detect enabled 14"] #[inline(always)] #[must_use] - pub fn len14(&mut self) -> LEN14_W<14> { + pub fn len14(&mut self) -> LEN14_W { LEN14_W::new(self) } #[doc = "Bit 15 - Low detect enabled 15"] #[inline(always)] #[must_use] - pub fn len15(&mut self) -> LEN15_W<15> { + pub fn len15(&mut self) -> LEN15_W { LEN15_W::new(self) } #[doc = "Bit 16 - Low detect enabled 16"] #[inline(always)] #[must_use] - pub fn len16(&mut self) -> LEN16_W<16> { + pub fn len16(&mut self) -> LEN16_W { LEN16_W::new(self) } #[doc = "Bit 17 - Low detect enabled 17"] #[inline(always)] #[must_use] - pub fn len17(&mut self) -> LEN17_W<17> { + pub fn len17(&mut self) -> LEN17_W { LEN17_W::new(self) } #[doc = "Bit 18 - Low detect enabled 18"] #[inline(always)] #[must_use] - pub fn len18(&mut self) -> LEN18_W<18> { + pub fn len18(&mut self) -> LEN18_W { LEN18_W::new(self) } #[doc = "Bit 19 - Low detect enabled 19"] #[inline(always)] #[must_use] - pub fn len19(&mut self) -> LEN19_W<19> { + pub fn len19(&mut self) -> LEN19_W { LEN19_W::new(self) } #[doc = "Bit 20 - Low detect enabled 20"] #[inline(always)] #[must_use] - pub fn len20(&mut self) -> LEN20_W<20> { + pub fn len20(&mut self) -> LEN20_W { LEN20_W::new(self) } #[doc = "Bit 21 - Low detect enabled 21"] #[inline(always)] #[must_use] - pub fn len21(&mut self) -> LEN21_W<21> { + pub fn len21(&mut self) -> LEN21_W { LEN21_W::new(self) } #[doc = "Bit 22 - Low detect enabled 22"] #[inline(always)] #[must_use] - pub fn len22(&mut self) -> LEN22_W<22> { + pub fn len22(&mut self) -> LEN22_W { LEN22_W::new(self) } #[doc = "Bit 23 - Low detect enabled 23"] #[inline(always)] #[must_use] - pub fn len23(&mut self) -> LEN23_W<23> { + pub fn len23(&mut self) -> LEN23_W { LEN23_W::new(self) } #[doc = "Bit 24 - Low detect enabled 24"] #[inline(always)] #[must_use] - pub fn len24(&mut self) -> LEN24_W<24> { + pub fn len24(&mut self) -> LEN24_W { LEN24_W::new(self) } #[doc = "Bit 25 - Low detect enabled 25"] #[inline(always)] #[must_use] - pub fn len25(&mut self) -> LEN25_W<25> { + pub fn len25(&mut self) -> LEN25_W { LEN25_W::new(self) } #[doc = "Bit 26 - Low detect enabled 26"] #[inline(always)] #[must_use] - pub fn len26(&mut self) -> LEN26_W<26> { + pub fn len26(&mut self) -> LEN26_W { LEN26_W::new(self) } #[doc = "Bit 27 - Low detect enabled 27"] #[inline(always)] #[must_use] - pub fn len27(&mut self) -> LEN27_W<27> { + pub fn len27(&mut self) -> LEN27_W { LEN27_W::new(self) } #[doc = "Bit 28 - Low detect enabled 28"] #[inline(always)] #[must_use] - pub fn len28(&mut self) -> LEN28_W<28> { + pub fn len28(&mut self) -> LEN28_W { LEN28_W::new(self) } #[doc = "Bit 29 - Low detect enabled 29"] #[inline(always)] #[must_use] - pub fn len29(&mut self) -> LEN29_W<29> { + pub fn len29(&mut self) -> LEN29_W { LEN29_W::new(self) } #[doc = "Bit 30 - Low detect enabled 30"] #[inline(always)] #[must_use] - pub fn len30(&mut self) -> LEN30_W<30> { + pub fn len30(&mut self) -> LEN30_W { LEN30_W::new(self) } #[doc = "Bit 31 - Low detect enabled 31"] #[inline(always)] #[must_use] - pub fn len31(&mut self) -> LEN31_W<31> { + pub fn len31(&mut self) -> LEN31_W { LEN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Low Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplen0](index.html) module"] +#[doc = "GPIO Pin Low Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gplen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPLEN0_SPEC; impl crate::RegisterSpec for GPLEN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gplen0::R](R) reader structure"] -impl crate::Readable for GPLEN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gplen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gplen0::R`](R) reader structure"] +impl crate::Readable for GPLEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gplen0::W`](W) writer structure"] impl crate::Writable for GPLEN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gplen1.rs b/crates/bcm2835-lpa/src/gpio/gplen1.rs index 070e4d4..bcf3f46 100644 --- a/crates/bcm2835-lpa/src/gpio/gplen1.rs +++ b/crates/bcm2835-lpa/src/gpio/gplen1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPLEN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPLEN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LEN32` reader - Low detect enabled 32"] -pub type LEN32_R = crate::BitReader; +pub type LEN32_R = crate::BitReader; #[doc = "Field `LEN32` writer - Low detect enabled 32"] -pub type LEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN33` reader - Low detect enabled 33"] -pub type LEN33_R = crate::BitReader; +pub type LEN33_R = crate::BitReader; #[doc = "Field `LEN33` writer - Low detect enabled 33"] -pub type LEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN34` reader - Low detect enabled 34"] -pub type LEN34_R = crate::BitReader; +pub type LEN34_R = crate::BitReader; #[doc = "Field `LEN34` writer - Low detect enabled 34"] -pub type LEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN35` reader - Low detect enabled 35"] -pub type LEN35_R = crate::BitReader; +pub type LEN35_R = crate::BitReader; #[doc = "Field `LEN35` writer - Low detect enabled 35"] -pub type LEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN36` reader - Low detect enabled 36"] -pub type LEN36_R = crate::BitReader; +pub type LEN36_R = crate::BitReader; #[doc = "Field `LEN36` writer - Low detect enabled 36"] -pub type LEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN37` reader - Low detect enabled 37"] -pub type LEN37_R = crate::BitReader; +pub type LEN37_R = crate::BitReader; #[doc = "Field `LEN37` writer - Low detect enabled 37"] -pub type LEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN38` reader - Low detect enabled 38"] -pub type LEN38_R = crate::BitReader; +pub type LEN38_R = crate::BitReader; #[doc = "Field `LEN38` writer - Low detect enabled 38"] -pub type LEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN39` reader - Low detect enabled 39"] -pub type LEN39_R = crate::BitReader; +pub type LEN39_R = crate::BitReader; #[doc = "Field `LEN39` writer - Low detect enabled 39"] -pub type LEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN40` reader - Low detect enabled 40"] -pub type LEN40_R = crate::BitReader; +pub type LEN40_R = crate::BitReader; #[doc = "Field `LEN40` writer - Low detect enabled 40"] -pub type LEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN41` reader - Low detect enabled 41"] -pub type LEN41_R = crate::BitReader; +pub type LEN41_R = crate::BitReader; #[doc = "Field `LEN41` writer - Low detect enabled 41"] -pub type LEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN42` reader - Low detect enabled 42"] -pub type LEN42_R = crate::BitReader; +pub type LEN42_R = crate::BitReader; #[doc = "Field `LEN42` writer - Low detect enabled 42"] -pub type LEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN43` reader - Low detect enabled 43"] -pub type LEN43_R = crate::BitReader; +pub type LEN43_R = crate::BitReader; #[doc = "Field `LEN43` writer - Low detect enabled 43"] -pub type LEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN44` reader - Low detect enabled 44"] -pub type LEN44_R = crate::BitReader; +pub type LEN44_R = crate::BitReader; #[doc = "Field `LEN44` writer - Low detect enabled 44"] -pub type LEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN45` reader - Low detect enabled 45"] -pub type LEN45_R = crate::BitReader; +pub type LEN45_R = crate::BitReader; #[doc = "Field `LEN45` writer - Low detect enabled 45"] -pub type LEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN46` reader - Low detect enabled 46"] -pub type LEN46_R = crate::BitReader; +pub type LEN46_R = crate::BitReader; #[doc = "Field `LEN46` writer - Low detect enabled 46"] -pub type LEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN47` reader - Low detect enabled 47"] -pub type LEN47_R = crate::BitReader; +pub type LEN47_R = crate::BitReader; #[doc = "Field `LEN47` writer - Low detect enabled 47"] -pub type LEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN48` reader - Low detect enabled 48"] -pub type LEN48_R = crate::BitReader; +pub type LEN48_R = crate::BitReader; #[doc = "Field `LEN48` writer - Low detect enabled 48"] -pub type LEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN49` reader - Low detect enabled 49"] -pub type LEN49_R = crate::BitReader; +pub type LEN49_R = crate::BitReader; #[doc = "Field `LEN49` writer - Low detect enabled 49"] -pub type LEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN50` reader - Low detect enabled 50"] -pub type LEN50_R = crate::BitReader; +pub type LEN50_R = crate::BitReader; #[doc = "Field `LEN50` writer - Low detect enabled 50"] -pub type LEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN51` reader - Low detect enabled 51"] -pub type LEN51_R = crate::BitReader; +pub type LEN51_R = crate::BitReader; #[doc = "Field `LEN51` writer - Low detect enabled 51"] -pub type LEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN52` reader - Low detect enabled 52"] -pub type LEN52_R = crate::BitReader; +pub type LEN52_R = crate::BitReader; #[doc = "Field `LEN52` writer - Low detect enabled 52"] -pub type LEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN53` reader - Low detect enabled 53"] -pub type LEN53_R = crate::BitReader; +pub type LEN53_R = crate::BitReader; #[doc = "Field `LEN53` writer - Low detect enabled 53"] -pub type LEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Low detect enabled 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { LEN53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPLEN1") + .field("len32", &format_args!("{}", self.len32().bit())) + .field("len33", &format_args!("{}", self.len33().bit())) + .field("len34", &format_args!("{}", self.len34().bit())) + .field("len35", &format_args!("{}", self.len35().bit())) + .field("len36", &format_args!("{}", self.len36().bit())) + .field("len37", &format_args!("{}", self.len37().bit())) + .field("len38", &format_args!("{}", self.len38().bit())) + .field("len39", &format_args!("{}", self.len39().bit())) + .field("len40", &format_args!("{}", self.len40().bit())) + .field("len41", &format_args!("{}", self.len41().bit())) + .field("len42", &format_args!("{}", self.len42().bit())) + .field("len43", &format_args!("{}", self.len43().bit())) + .field("len44", &format_args!("{}", self.len44().bit())) + .field("len45", &format_args!("{}", self.len45().bit())) + .field("len46", &format_args!("{}", self.len46().bit())) + .field("len47", &format_args!("{}", self.len47().bit())) + .field("len48", &format_args!("{}", self.len48().bit())) + .field("len49", &format_args!("{}", self.len49().bit())) + .field("len50", &format_args!("{}", self.len50().bit())) + .field("len51", &format_args!("{}", self.len51().bit())) + .field("len52", &format_args!("{}", self.len52().bit())) + .field("len53", &format_args!("{}", self.len53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Low detect enabled 32"] #[inline(always)] #[must_use] - pub fn len32(&mut self) -> LEN32_W<0> { + pub fn len32(&mut self) -> LEN32_W { LEN32_W::new(self) } #[doc = "Bit 1 - Low detect enabled 33"] #[inline(always)] #[must_use] - pub fn len33(&mut self) -> LEN33_W<1> { + pub fn len33(&mut self) -> LEN33_W { LEN33_W::new(self) } #[doc = "Bit 2 - Low detect enabled 34"] #[inline(always)] #[must_use] - pub fn len34(&mut self) -> LEN34_W<2> { + pub fn len34(&mut self) -> LEN34_W { LEN34_W::new(self) } #[doc = "Bit 3 - Low detect enabled 35"] #[inline(always)] #[must_use] - pub fn len35(&mut self) -> LEN35_W<3> { + pub fn len35(&mut self) -> LEN35_W { LEN35_W::new(self) } #[doc = "Bit 4 - Low detect enabled 36"] #[inline(always)] #[must_use] - pub fn len36(&mut self) -> LEN36_W<4> { + pub fn len36(&mut self) -> LEN36_W { LEN36_W::new(self) } #[doc = "Bit 5 - Low detect enabled 37"] #[inline(always)] #[must_use] - pub fn len37(&mut self) -> LEN37_W<5> { + pub fn len37(&mut self) -> LEN37_W { LEN37_W::new(self) } #[doc = "Bit 6 - Low detect enabled 38"] #[inline(always)] #[must_use] - pub fn len38(&mut self) -> LEN38_W<6> { + pub fn len38(&mut self) -> LEN38_W { LEN38_W::new(self) } #[doc = "Bit 7 - Low detect enabled 39"] #[inline(always)] #[must_use] - pub fn len39(&mut self) -> LEN39_W<7> { + pub fn len39(&mut self) -> LEN39_W { LEN39_W::new(self) } #[doc = "Bit 8 - Low detect enabled 40"] #[inline(always)] #[must_use] - pub fn len40(&mut self) -> LEN40_W<8> { + pub fn len40(&mut self) -> LEN40_W { LEN40_W::new(self) } #[doc = "Bit 9 - Low detect enabled 41"] #[inline(always)] #[must_use] - pub fn len41(&mut self) -> LEN41_W<9> { + pub fn len41(&mut self) -> LEN41_W { LEN41_W::new(self) } #[doc = "Bit 10 - Low detect enabled 42"] #[inline(always)] #[must_use] - pub fn len42(&mut self) -> LEN42_W<10> { + pub fn len42(&mut self) -> LEN42_W { LEN42_W::new(self) } #[doc = "Bit 11 - Low detect enabled 43"] #[inline(always)] #[must_use] - pub fn len43(&mut self) -> LEN43_W<11> { + pub fn len43(&mut self) -> LEN43_W { LEN43_W::new(self) } #[doc = "Bit 12 - Low detect enabled 44"] #[inline(always)] #[must_use] - pub fn len44(&mut self) -> LEN44_W<12> { + pub fn len44(&mut self) -> LEN44_W { LEN44_W::new(self) } #[doc = "Bit 13 - Low detect enabled 45"] #[inline(always)] #[must_use] - pub fn len45(&mut self) -> LEN45_W<13> { + pub fn len45(&mut self) -> LEN45_W { LEN45_W::new(self) } #[doc = "Bit 14 - Low detect enabled 46"] #[inline(always)] #[must_use] - pub fn len46(&mut self) -> LEN46_W<14> { + pub fn len46(&mut self) -> LEN46_W { LEN46_W::new(self) } #[doc = "Bit 15 - Low detect enabled 47"] #[inline(always)] #[must_use] - pub fn len47(&mut self) -> LEN47_W<15> { + pub fn len47(&mut self) -> LEN47_W { LEN47_W::new(self) } #[doc = "Bit 16 - Low detect enabled 48"] #[inline(always)] #[must_use] - pub fn len48(&mut self) -> LEN48_W<16> { + pub fn len48(&mut self) -> LEN48_W { LEN48_W::new(self) } #[doc = "Bit 17 - Low detect enabled 49"] #[inline(always)] #[must_use] - pub fn len49(&mut self) -> LEN49_W<17> { + pub fn len49(&mut self) -> LEN49_W { LEN49_W::new(self) } #[doc = "Bit 18 - Low detect enabled 50"] #[inline(always)] #[must_use] - pub fn len50(&mut self) -> LEN50_W<18> { + pub fn len50(&mut self) -> LEN50_W { LEN50_W::new(self) } #[doc = "Bit 19 - Low detect enabled 51"] #[inline(always)] #[must_use] - pub fn len51(&mut self) -> LEN51_W<19> { + pub fn len51(&mut self) -> LEN51_W { LEN51_W::new(self) } #[doc = "Bit 20 - Low detect enabled 52"] #[inline(always)] #[must_use] - pub fn len52(&mut self) -> LEN52_W<20> { + pub fn len52(&mut self) -> LEN52_W { LEN52_W::new(self) } #[doc = "Bit 21 - Low detect enabled 53"] #[inline(always)] #[must_use] - pub fn len53(&mut self) -> LEN53_W<21> { + pub fn len53(&mut self) -> LEN53_W { LEN53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Low Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplen1](index.html) module"] +#[doc = "GPIO Pin Low Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gplen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPLEN1_SPEC; impl crate::RegisterSpec for GPLEN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gplen1::R](R) reader structure"] -impl crate::Readable for GPLEN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gplen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gplen1::R`](R) reader structure"] +impl crate::Readable for GPLEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gplen1::W`](W) writer structure"] impl crate::Writable for GPLEN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gplev0.rs b/crates/bcm2835-lpa/src/gpio/gplev0.rs index e6f9b94..43e1e5c 100644 --- a/crates/bcm2835-lpa/src/gpio/gplev0.rs +++ b/crates/bcm2835-lpa/src/gpio/gplev0.rs @@ -1,82 +1,69 @@ #[doc = "Register `GPLEV0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LEV0` reader - Level 0"] -pub type LEV0_R = crate::BitReader; +pub type LEV0_R = crate::BitReader; #[doc = "Field `LEV1` reader - Level 1"] -pub type LEV1_R = crate::BitReader; +pub type LEV1_R = crate::BitReader; #[doc = "Field `LEV2` reader - Level 2"] -pub type LEV2_R = crate::BitReader; +pub type LEV2_R = crate::BitReader; #[doc = "Field `LEV3` reader - Level 3"] -pub type LEV3_R = crate::BitReader; +pub type LEV3_R = crate::BitReader; #[doc = "Field `LEV4` reader - Level 4"] -pub type LEV4_R = crate::BitReader; +pub type LEV4_R = crate::BitReader; #[doc = "Field `LEV5` reader - Level 5"] -pub type LEV5_R = crate::BitReader; +pub type LEV5_R = crate::BitReader; #[doc = "Field `LEV6` reader - Level 6"] -pub type LEV6_R = crate::BitReader; +pub type LEV6_R = crate::BitReader; #[doc = "Field `LEV7` reader - Level 7"] -pub type LEV7_R = crate::BitReader; +pub type LEV7_R = crate::BitReader; #[doc = "Field `LEV8` reader - Level 8"] -pub type LEV8_R = crate::BitReader; +pub type LEV8_R = crate::BitReader; #[doc = "Field `LEV9` reader - Level 9"] -pub type LEV9_R = crate::BitReader; +pub type LEV9_R = crate::BitReader; #[doc = "Field `LEV10` reader - Level 10"] -pub type LEV10_R = crate::BitReader; +pub type LEV10_R = crate::BitReader; #[doc = "Field `LEV11` reader - Level 11"] -pub type LEV11_R = crate::BitReader; +pub type LEV11_R = crate::BitReader; #[doc = "Field `LEV12` reader - Level 12"] -pub type LEV12_R = crate::BitReader; +pub type LEV12_R = crate::BitReader; #[doc = "Field `LEV13` reader - Level 13"] -pub type LEV13_R = crate::BitReader; +pub type LEV13_R = crate::BitReader; #[doc = "Field `LEV14` reader - Level 14"] -pub type LEV14_R = crate::BitReader; +pub type LEV14_R = crate::BitReader; #[doc = "Field `LEV15` reader - Level 15"] -pub type LEV15_R = crate::BitReader; +pub type LEV15_R = crate::BitReader; #[doc = "Field `LEV16` reader - Level 16"] -pub type LEV16_R = crate::BitReader; +pub type LEV16_R = crate::BitReader; #[doc = "Field `LEV17` reader - Level 17"] -pub type LEV17_R = crate::BitReader; +pub type LEV17_R = crate::BitReader; #[doc = "Field `LEV18` reader - Level 18"] -pub type LEV18_R = crate::BitReader; +pub type LEV18_R = crate::BitReader; #[doc = "Field `LEV19` reader - Level 19"] -pub type LEV19_R = crate::BitReader; +pub type LEV19_R = crate::BitReader; #[doc = "Field `LEV20` reader - Level 20"] -pub type LEV20_R = crate::BitReader; +pub type LEV20_R = crate::BitReader; #[doc = "Field `LEV21` reader - Level 21"] -pub type LEV21_R = crate::BitReader; +pub type LEV21_R = crate::BitReader; #[doc = "Field `LEV22` reader - Level 22"] -pub type LEV22_R = crate::BitReader; +pub type LEV22_R = crate::BitReader; #[doc = "Field `LEV23` reader - Level 23"] -pub type LEV23_R = crate::BitReader; +pub type LEV23_R = crate::BitReader; #[doc = "Field `LEV24` reader - Level 24"] -pub type LEV24_R = crate::BitReader; +pub type LEV24_R = crate::BitReader; #[doc = "Field `LEV25` reader - Level 25"] -pub type LEV25_R = crate::BitReader; +pub type LEV25_R = crate::BitReader; #[doc = "Field `LEV26` reader - Level 26"] -pub type LEV26_R = crate::BitReader; +pub type LEV26_R = crate::BitReader; #[doc = "Field `LEV27` reader - Level 27"] -pub type LEV27_R = crate::BitReader; +pub type LEV27_R = crate::BitReader; #[doc = "Field `LEV28` reader - Level 28"] -pub type LEV28_R = crate::BitReader; +pub type LEV28_R = crate::BitReader; #[doc = "Field `LEV29` reader - Level 29"] -pub type LEV29_R = crate::BitReader; +pub type LEV29_R = crate::BitReader; #[doc = "Field `LEV30` reader - Level 30"] -pub type LEV30_R = crate::BitReader; +pub type LEV30_R = crate::BitReader; #[doc = "Field `LEV31` reader - Level 31"] -pub type LEV31_R = crate::BitReader; +pub type LEV31_R = crate::BitReader; impl R { #[doc = "Bit 0 - Level 0"] #[inline(always)] @@ -239,12 +226,53 @@ impl R { LEV31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "GPIO Pin Level 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplev0](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPLEV0") + .field("lev0", &format_args!("{}", self.lev0().bit())) + .field("lev1", &format_args!("{}", self.lev1().bit())) + .field("lev2", &format_args!("{}", self.lev2().bit())) + .field("lev3", &format_args!("{}", self.lev3().bit())) + .field("lev4", &format_args!("{}", self.lev4().bit())) + .field("lev5", &format_args!("{}", self.lev5().bit())) + .field("lev6", &format_args!("{}", self.lev6().bit())) + .field("lev7", &format_args!("{}", self.lev7().bit())) + .field("lev8", &format_args!("{}", self.lev8().bit())) + .field("lev9", &format_args!("{}", self.lev9().bit())) + .field("lev10", &format_args!("{}", self.lev10().bit())) + .field("lev11", &format_args!("{}", self.lev11().bit())) + .field("lev12", &format_args!("{}", self.lev12().bit())) + .field("lev13", &format_args!("{}", self.lev13().bit())) + .field("lev14", &format_args!("{}", self.lev14().bit())) + .field("lev15", &format_args!("{}", self.lev15().bit())) + .field("lev16", &format_args!("{}", self.lev16().bit())) + .field("lev17", &format_args!("{}", self.lev17().bit())) + .field("lev18", &format_args!("{}", self.lev18().bit())) + .field("lev19", &format_args!("{}", self.lev19().bit())) + .field("lev20", &format_args!("{}", self.lev20().bit())) + .field("lev21", &format_args!("{}", self.lev21().bit())) + .field("lev22", &format_args!("{}", self.lev22().bit())) + .field("lev23", &format_args!("{}", self.lev23().bit())) + .field("lev24", &format_args!("{}", self.lev24().bit())) + .field("lev25", &format_args!("{}", self.lev25().bit())) + .field("lev26", &format_args!("{}", self.lev26().bit())) + .field("lev27", &format_args!("{}", self.lev27().bit())) + .field("lev28", &format_args!("{}", self.lev28().bit())) + .field("lev29", &format_args!("{}", self.lev29().bit())) + .field("lev30", &format_args!("{}", self.lev30().bit())) + .field("lev31", &format_args!("{}", self.lev31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "GPIO Pin Level 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplev0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPLEV0_SPEC; impl crate::RegisterSpec for GPLEV0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gplev0::R](R) reader structure"] -impl crate::Readable for GPLEV0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gplev0::R`](R) reader structure"] +impl crate::Readable for GPLEV0_SPEC {} diff --git a/crates/bcm2835-lpa/src/gpio/gplev1.rs b/crates/bcm2835-lpa/src/gpio/gplev1.rs index 5323ce3..e881649 100644 --- a/crates/bcm2835-lpa/src/gpio/gplev1.rs +++ b/crates/bcm2835-lpa/src/gpio/gplev1.rs @@ -1,62 +1,49 @@ #[doc = "Register `GPLEV1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LEV32` reader - Level 32"] -pub type LEV32_R = crate::BitReader; +pub type LEV32_R = crate::BitReader; #[doc = "Field `LEV33` reader - Level 33"] -pub type LEV33_R = crate::BitReader; +pub type LEV33_R = crate::BitReader; #[doc = "Field `LEV34` reader - Level 34"] -pub type LEV34_R = crate::BitReader; +pub type LEV34_R = crate::BitReader; #[doc = "Field `LEV35` reader - Level 35"] -pub type LEV35_R = crate::BitReader; +pub type LEV35_R = crate::BitReader; #[doc = "Field `LEV36` reader - Level 36"] -pub type LEV36_R = crate::BitReader; +pub type LEV36_R = crate::BitReader; #[doc = "Field `LEV37` reader - Level 37"] -pub type LEV37_R = crate::BitReader; +pub type LEV37_R = crate::BitReader; #[doc = "Field `LEV38` reader - Level 38"] -pub type LEV38_R = crate::BitReader; +pub type LEV38_R = crate::BitReader; #[doc = "Field `LEV39` reader - Level 39"] -pub type LEV39_R = crate::BitReader; +pub type LEV39_R = crate::BitReader; #[doc = "Field `LEV40` reader - Level 40"] -pub type LEV40_R = crate::BitReader; +pub type LEV40_R = crate::BitReader; #[doc = "Field `LEV41` reader - Level 41"] -pub type LEV41_R = crate::BitReader; +pub type LEV41_R = crate::BitReader; #[doc = "Field `LEV42` reader - Level 42"] -pub type LEV42_R = crate::BitReader; +pub type LEV42_R = crate::BitReader; #[doc = "Field `LEV43` reader - Level 43"] -pub type LEV43_R = crate::BitReader; +pub type LEV43_R = crate::BitReader; #[doc = "Field `LEV44` reader - Level 44"] -pub type LEV44_R = crate::BitReader; +pub type LEV44_R = crate::BitReader; #[doc = "Field `LEV45` reader - Level 45"] -pub type LEV45_R = crate::BitReader; +pub type LEV45_R = crate::BitReader; #[doc = "Field `LEV46` reader - Level 46"] -pub type LEV46_R = crate::BitReader; +pub type LEV46_R = crate::BitReader; #[doc = "Field `LEV47` reader - Level 47"] -pub type LEV47_R = crate::BitReader; +pub type LEV47_R = crate::BitReader; #[doc = "Field `LEV48` reader - Level 48"] -pub type LEV48_R = crate::BitReader; +pub type LEV48_R = crate::BitReader; #[doc = "Field `LEV49` reader - Level 49"] -pub type LEV49_R = crate::BitReader; +pub type LEV49_R = crate::BitReader; #[doc = "Field `LEV50` reader - Level 50"] -pub type LEV50_R = crate::BitReader; +pub type LEV50_R = crate::BitReader; #[doc = "Field `LEV51` reader - Level 51"] -pub type LEV51_R = crate::BitReader; +pub type LEV51_R = crate::BitReader; #[doc = "Field `LEV52` reader - Level 52"] -pub type LEV52_R = crate::BitReader; +pub type LEV52_R = crate::BitReader; #[doc = "Field `LEV53` reader - Level 53"] -pub type LEV53_R = crate::BitReader; +pub type LEV53_R = crate::BitReader; impl R { #[doc = "Bit 0 - Level 32"] #[inline(always)] @@ -169,12 +156,43 @@ impl R { LEV53_R::new(((self.bits >> 21) & 1) != 0) } } -#[doc = "GPIO Pin Level 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplev1](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPLEV1") + .field("lev32", &format_args!("{}", self.lev32().bit())) + .field("lev33", &format_args!("{}", self.lev33().bit())) + .field("lev34", &format_args!("{}", self.lev34().bit())) + .field("lev35", &format_args!("{}", self.lev35().bit())) + .field("lev36", &format_args!("{}", self.lev36().bit())) + .field("lev37", &format_args!("{}", self.lev37().bit())) + .field("lev38", &format_args!("{}", self.lev38().bit())) + .field("lev39", &format_args!("{}", self.lev39().bit())) + .field("lev40", &format_args!("{}", self.lev40().bit())) + .field("lev41", &format_args!("{}", self.lev41().bit())) + .field("lev42", &format_args!("{}", self.lev42().bit())) + .field("lev43", &format_args!("{}", self.lev43().bit())) + .field("lev44", &format_args!("{}", self.lev44().bit())) + .field("lev45", &format_args!("{}", self.lev45().bit())) + .field("lev46", &format_args!("{}", self.lev46().bit())) + .field("lev47", &format_args!("{}", self.lev47().bit())) + .field("lev48", &format_args!("{}", self.lev48().bit())) + .field("lev49", &format_args!("{}", self.lev49().bit())) + .field("lev50", &format_args!("{}", self.lev50().bit())) + .field("lev51", &format_args!("{}", self.lev51().bit())) + .field("lev52", &format_args!("{}", self.lev52().bit())) + .field("lev53", &format_args!("{}", self.lev53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "GPIO Pin Level 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplev1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPLEV1_SPEC; impl crate::RegisterSpec for GPLEV1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gplev1::R](R) reader structure"] -impl crate::Readable for GPLEV1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gplev1::R`](R) reader structure"] +impl crate::Readable for GPLEV1_SPEC {} diff --git a/crates/bcm2835-lpa/src/gpio/gpren0.rs b/crates/bcm2835-lpa/src/gpio/gpren0.rs index af4f16c..f4dfc2e 100644 --- a/crates/bcm2835-lpa/src/gpio/gpren0.rs +++ b/crates/bcm2835-lpa/src/gpio/gpren0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPREN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPREN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `REN0` reader - Rising edge enabled 0"] -pub type REN0_R = crate::BitReader; +pub type REN0_R = crate::BitReader; #[doc = "Field `REN0` writer - Rising edge enabled 0"] -pub type REN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN1` reader - Rising edge enabled 1"] -pub type REN1_R = crate::BitReader; +pub type REN1_R = crate::BitReader; #[doc = "Field `REN1` writer - Rising edge enabled 1"] -pub type REN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN2` reader - Rising edge enabled 2"] -pub type REN2_R = crate::BitReader; +pub type REN2_R = crate::BitReader; #[doc = "Field `REN2` writer - Rising edge enabled 2"] -pub type REN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN3` reader - Rising edge enabled 3"] -pub type REN3_R = crate::BitReader; +pub type REN3_R = crate::BitReader; #[doc = "Field `REN3` writer - Rising edge enabled 3"] -pub type REN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN4` reader - Rising edge enabled 4"] -pub type REN4_R = crate::BitReader; +pub type REN4_R = crate::BitReader; #[doc = "Field `REN4` writer - Rising edge enabled 4"] -pub type REN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN5` reader - Rising edge enabled 5"] -pub type REN5_R = crate::BitReader; +pub type REN5_R = crate::BitReader; #[doc = "Field `REN5` writer - Rising edge enabled 5"] -pub type REN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN6` reader - Rising edge enabled 6"] -pub type REN6_R = crate::BitReader; +pub type REN6_R = crate::BitReader; #[doc = "Field `REN6` writer - Rising edge enabled 6"] -pub type REN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN7` reader - Rising edge enabled 7"] -pub type REN7_R = crate::BitReader; +pub type REN7_R = crate::BitReader; #[doc = "Field `REN7` writer - Rising edge enabled 7"] -pub type REN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN8` reader - Rising edge enabled 8"] -pub type REN8_R = crate::BitReader; +pub type REN8_R = crate::BitReader; #[doc = "Field `REN8` writer - Rising edge enabled 8"] -pub type REN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN9` reader - Rising edge enabled 9"] -pub type REN9_R = crate::BitReader; +pub type REN9_R = crate::BitReader; #[doc = "Field `REN9` writer - Rising edge enabled 9"] -pub type REN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN10` reader - Rising edge enabled 10"] -pub type REN10_R = crate::BitReader; +pub type REN10_R = crate::BitReader; #[doc = "Field `REN10` writer - Rising edge enabled 10"] -pub type REN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN11` reader - Rising edge enabled 11"] -pub type REN11_R = crate::BitReader; +pub type REN11_R = crate::BitReader; #[doc = "Field `REN11` writer - Rising edge enabled 11"] -pub type REN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN12` reader - Rising edge enabled 12"] -pub type REN12_R = crate::BitReader; +pub type REN12_R = crate::BitReader; #[doc = "Field `REN12` writer - Rising edge enabled 12"] -pub type REN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN13` reader - Rising edge enabled 13"] -pub type REN13_R = crate::BitReader; +pub type REN13_R = crate::BitReader; #[doc = "Field `REN13` writer - Rising edge enabled 13"] -pub type REN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN14` reader - Rising edge enabled 14"] -pub type REN14_R = crate::BitReader; +pub type REN14_R = crate::BitReader; #[doc = "Field `REN14` writer - Rising edge enabled 14"] -pub type REN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN15` reader - Rising edge enabled 15"] -pub type REN15_R = crate::BitReader; +pub type REN15_R = crate::BitReader; #[doc = "Field `REN15` writer - Rising edge enabled 15"] -pub type REN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN16` reader - Rising edge enabled 16"] -pub type REN16_R = crate::BitReader; +pub type REN16_R = crate::BitReader; #[doc = "Field `REN16` writer - Rising edge enabled 16"] -pub type REN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN17` reader - Rising edge enabled 17"] -pub type REN17_R = crate::BitReader; +pub type REN17_R = crate::BitReader; #[doc = "Field `REN17` writer - Rising edge enabled 17"] -pub type REN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN18` reader - Rising edge enabled 18"] -pub type REN18_R = crate::BitReader; +pub type REN18_R = crate::BitReader; #[doc = "Field `REN18` writer - Rising edge enabled 18"] -pub type REN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN19` reader - Rising edge enabled 19"] -pub type REN19_R = crate::BitReader; +pub type REN19_R = crate::BitReader; #[doc = "Field `REN19` writer - Rising edge enabled 19"] -pub type REN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN20` reader - Rising edge enabled 20"] -pub type REN20_R = crate::BitReader; +pub type REN20_R = crate::BitReader; #[doc = "Field `REN20` writer - Rising edge enabled 20"] -pub type REN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN21` reader - Rising edge enabled 21"] -pub type REN21_R = crate::BitReader; +pub type REN21_R = crate::BitReader; #[doc = "Field `REN21` writer - Rising edge enabled 21"] -pub type REN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN22` reader - Rising edge enabled 22"] -pub type REN22_R = crate::BitReader; +pub type REN22_R = crate::BitReader; #[doc = "Field `REN22` writer - Rising edge enabled 22"] -pub type REN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN23` reader - Rising edge enabled 23"] -pub type REN23_R = crate::BitReader; +pub type REN23_R = crate::BitReader; #[doc = "Field `REN23` writer - Rising edge enabled 23"] -pub type REN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN24` reader - Rising edge enabled 24"] -pub type REN24_R = crate::BitReader; +pub type REN24_R = crate::BitReader; #[doc = "Field `REN24` writer - Rising edge enabled 24"] -pub type REN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN25` reader - Rising edge enabled 25"] -pub type REN25_R = crate::BitReader; +pub type REN25_R = crate::BitReader; #[doc = "Field `REN25` writer - Rising edge enabled 25"] -pub type REN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN26` reader - Rising edge enabled 26"] -pub type REN26_R = crate::BitReader; +pub type REN26_R = crate::BitReader; #[doc = "Field `REN26` writer - Rising edge enabled 26"] -pub type REN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN27` reader - Rising edge enabled 27"] -pub type REN27_R = crate::BitReader; +pub type REN27_R = crate::BitReader; #[doc = "Field `REN27` writer - Rising edge enabled 27"] -pub type REN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN28` reader - Rising edge enabled 28"] -pub type REN28_R = crate::BitReader; +pub type REN28_R = crate::BitReader; #[doc = "Field `REN28` writer - Rising edge enabled 28"] -pub type REN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN29` reader - Rising edge enabled 29"] -pub type REN29_R = crate::BitReader; +pub type REN29_R = crate::BitReader; #[doc = "Field `REN29` writer - Rising edge enabled 29"] -pub type REN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN30` reader - Rising edge enabled 30"] -pub type REN30_R = crate::BitReader; +pub type REN30_R = crate::BitReader; #[doc = "Field `REN30` writer - Rising edge enabled 30"] -pub type REN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN31` reader - Rising edge enabled 31"] -pub type REN31_R = crate::BitReader; +pub type REN31_R = crate::BitReader; #[doc = "Field `REN31` writer - Rising edge enabled 31"] -pub type REN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Rising edge enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { REN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPREN0") + .field("ren0", &format_args!("{}", self.ren0().bit())) + .field("ren1", &format_args!("{}", self.ren1().bit())) + .field("ren2", &format_args!("{}", self.ren2().bit())) + .field("ren3", &format_args!("{}", self.ren3().bit())) + .field("ren4", &format_args!("{}", self.ren4().bit())) + .field("ren5", &format_args!("{}", self.ren5().bit())) + .field("ren6", &format_args!("{}", self.ren6().bit())) + .field("ren7", &format_args!("{}", self.ren7().bit())) + .field("ren8", &format_args!("{}", self.ren8().bit())) + .field("ren9", &format_args!("{}", self.ren9().bit())) + .field("ren10", &format_args!("{}", self.ren10().bit())) + .field("ren11", &format_args!("{}", self.ren11().bit())) + .field("ren12", &format_args!("{}", self.ren12().bit())) + .field("ren13", &format_args!("{}", self.ren13().bit())) + .field("ren14", &format_args!("{}", self.ren14().bit())) + .field("ren15", &format_args!("{}", self.ren15().bit())) + .field("ren16", &format_args!("{}", self.ren16().bit())) + .field("ren17", &format_args!("{}", self.ren17().bit())) + .field("ren18", &format_args!("{}", self.ren18().bit())) + .field("ren19", &format_args!("{}", self.ren19().bit())) + .field("ren20", &format_args!("{}", self.ren20().bit())) + .field("ren21", &format_args!("{}", self.ren21().bit())) + .field("ren22", &format_args!("{}", self.ren22().bit())) + .field("ren23", &format_args!("{}", self.ren23().bit())) + .field("ren24", &format_args!("{}", self.ren24().bit())) + .field("ren25", &format_args!("{}", self.ren25().bit())) + .field("ren26", &format_args!("{}", self.ren26().bit())) + .field("ren27", &format_args!("{}", self.ren27().bit())) + .field("ren28", &format_args!("{}", self.ren28().bit())) + .field("ren29", &format_args!("{}", self.ren29().bit())) + .field("ren30", &format_args!("{}", self.ren30().bit())) + .field("ren31", &format_args!("{}", self.ren31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Rising edge enabled 0"] #[inline(always)] #[must_use] - pub fn ren0(&mut self) -> REN0_W<0> { + pub fn ren0(&mut self) -> REN0_W { REN0_W::new(self) } #[doc = "Bit 1 - Rising edge enabled 1"] #[inline(always)] #[must_use] - pub fn ren1(&mut self) -> REN1_W<1> { + pub fn ren1(&mut self) -> REN1_W { REN1_W::new(self) } #[doc = "Bit 2 - Rising edge enabled 2"] #[inline(always)] #[must_use] - pub fn ren2(&mut self) -> REN2_W<2> { + pub fn ren2(&mut self) -> REN2_W { REN2_W::new(self) } #[doc = "Bit 3 - Rising edge enabled 3"] #[inline(always)] #[must_use] - pub fn ren3(&mut self) -> REN3_W<3> { + pub fn ren3(&mut self) -> REN3_W { REN3_W::new(self) } #[doc = "Bit 4 - Rising edge enabled 4"] #[inline(always)] #[must_use] - pub fn ren4(&mut self) -> REN4_W<4> { + pub fn ren4(&mut self) -> REN4_W { REN4_W::new(self) } #[doc = "Bit 5 - Rising edge enabled 5"] #[inline(always)] #[must_use] - pub fn ren5(&mut self) -> REN5_W<5> { + pub fn ren5(&mut self) -> REN5_W { REN5_W::new(self) } #[doc = "Bit 6 - Rising edge enabled 6"] #[inline(always)] #[must_use] - pub fn ren6(&mut self) -> REN6_W<6> { + pub fn ren6(&mut self) -> REN6_W { REN6_W::new(self) } #[doc = "Bit 7 - Rising edge enabled 7"] #[inline(always)] #[must_use] - pub fn ren7(&mut self) -> REN7_W<7> { + pub fn ren7(&mut self) -> REN7_W { REN7_W::new(self) } #[doc = "Bit 8 - Rising edge enabled 8"] #[inline(always)] #[must_use] - pub fn ren8(&mut self) -> REN8_W<8> { + pub fn ren8(&mut self) -> REN8_W { REN8_W::new(self) } #[doc = "Bit 9 - Rising edge enabled 9"] #[inline(always)] #[must_use] - pub fn ren9(&mut self) -> REN9_W<9> { + pub fn ren9(&mut self) -> REN9_W { REN9_W::new(self) } #[doc = "Bit 10 - Rising edge enabled 10"] #[inline(always)] #[must_use] - pub fn ren10(&mut self) -> REN10_W<10> { + pub fn ren10(&mut self) -> REN10_W { REN10_W::new(self) } #[doc = "Bit 11 - Rising edge enabled 11"] #[inline(always)] #[must_use] - pub fn ren11(&mut self) -> REN11_W<11> { + pub fn ren11(&mut self) -> REN11_W { REN11_W::new(self) } #[doc = "Bit 12 - Rising edge enabled 12"] #[inline(always)] #[must_use] - pub fn ren12(&mut self) -> REN12_W<12> { + pub fn ren12(&mut self) -> REN12_W { REN12_W::new(self) } #[doc = "Bit 13 - Rising edge enabled 13"] #[inline(always)] #[must_use] - pub fn ren13(&mut self) -> REN13_W<13> { + pub fn ren13(&mut self) -> REN13_W { REN13_W::new(self) } #[doc = "Bit 14 - Rising edge enabled 14"] #[inline(always)] #[must_use] - pub fn ren14(&mut self) -> REN14_W<14> { + pub fn ren14(&mut self) -> REN14_W { REN14_W::new(self) } #[doc = "Bit 15 - Rising edge enabled 15"] #[inline(always)] #[must_use] - pub fn ren15(&mut self) -> REN15_W<15> { + pub fn ren15(&mut self) -> REN15_W { REN15_W::new(self) } #[doc = "Bit 16 - Rising edge enabled 16"] #[inline(always)] #[must_use] - pub fn ren16(&mut self) -> REN16_W<16> { + pub fn ren16(&mut self) -> REN16_W { REN16_W::new(self) } #[doc = "Bit 17 - Rising edge enabled 17"] #[inline(always)] #[must_use] - pub fn ren17(&mut self) -> REN17_W<17> { + pub fn ren17(&mut self) -> REN17_W { REN17_W::new(self) } #[doc = "Bit 18 - Rising edge enabled 18"] #[inline(always)] #[must_use] - pub fn ren18(&mut self) -> REN18_W<18> { + pub fn ren18(&mut self) -> REN18_W { REN18_W::new(self) } #[doc = "Bit 19 - Rising edge enabled 19"] #[inline(always)] #[must_use] - pub fn ren19(&mut self) -> REN19_W<19> { + pub fn ren19(&mut self) -> REN19_W { REN19_W::new(self) } #[doc = "Bit 20 - Rising edge enabled 20"] #[inline(always)] #[must_use] - pub fn ren20(&mut self) -> REN20_W<20> { + pub fn ren20(&mut self) -> REN20_W { REN20_W::new(self) } #[doc = "Bit 21 - Rising edge enabled 21"] #[inline(always)] #[must_use] - pub fn ren21(&mut self) -> REN21_W<21> { + pub fn ren21(&mut self) -> REN21_W { REN21_W::new(self) } #[doc = "Bit 22 - Rising edge enabled 22"] #[inline(always)] #[must_use] - pub fn ren22(&mut self) -> REN22_W<22> { + pub fn ren22(&mut self) -> REN22_W { REN22_W::new(self) } #[doc = "Bit 23 - Rising edge enabled 23"] #[inline(always)] #[must_use] - pub fn ren23(&mut self) -> REN23_W<23> { + pub fn ren23(&mut self) -> REN23_W { REN23_W::new(self) } #[doc = "Bit 24 - Rising edge enabled 24"] #[inline(always)] #[must_use] - pub fn ren24(&mut self) -> REN24_W<24> { + pub fn ren24(&mut self) -> REN24_W { REN24_W::new(self) } #[doc = "Bit 25 - Rising edge enabled 25"] #[inline(always)] #[must_use] - pub fn ren25(&mut self) -> REN25_W<25> { + pub fn ren25(&mut self) -> REN25_W { REN25_W::new(self) } #[doc = "Bit 26 - Rising edge enabled 26"] #[inline(always)] #[must_use] - pub fn ren26(&mut self) -> REN26_W<26> { + pub fn ren26(&mut self) -> REN26_W { REN26_W::new(self) } #[doc = "Bit 27 - Rising edge enabled 27"] #[inline(always)] #[must_use] - pub fn ren27(&mut self) -> REN27_W<27> { + pub fn ren27(&mut self) -> REN27_W { REN27_W::new(self) } #[doc = "Bit 28 - Rising edge enabled 28"] #[inline(always)] #[must_use] - pub fn ren28(&mut self) -> REN28_W<28> { + pub fn ren28(&mut self) -> REN28_W { REN28_W::new(self) } #[doc = "Bit 29 - Rising edge enabled 29"] #[inline(always)] #[must_use] - pub fn ren29(&mut self) -> REN29_W<29> { + pub fn ren29(&mut self) -> REN29_W { REN29_W::new(self) } #[doc = "Bit 30 - Rising edge enabled 30"] #[inline(always)] #[must_use] - pub fn ren30(&mut self) -> REN30_W<30> { + pub fn ren30(&mut self) -> REN30_W { REN30_W::new(self) } #[doc = "Bit 31 - Rising edge enabled 31"] #[inline(always)] #[must_use] - pub fn ren31(&mut self) -> REN31_W<31> { + pub fn ren31(&mut self) -> REN31_W { REN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Rising Edge Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpren0](index.html) module"] +#[doc = "GPIO Pin Rising Edge Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpren0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpren0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPREN0_SPEC; impl crate::RegisterSpec for GPREN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpren0::R](R) reader structure"] -impl crate::Readable for GPREN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpren0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpren0::R`](R) reader structure"] +impl crate::Readable for GPREN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpren0::W`](W) writer structure"] impl crate::Writable for GPREN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpren1.rs b/crates/bcm2835-lpa/src/gpio/gpren1.rs index 3e70995..9f78a23 100644 --- a/crates/bcm2835-lpa/src/gpio/gpren1.rs +++ b/crates/bcm2835-lpa/src/gpio/gpren1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPREN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPREN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `REN32` reader - Rising edge enabled 32"] -pub type REN32_R = crate::BitReader; +pub type REN32_R = crate::BitReader; #[doc = "Field `REN32` writer - Rising edge enabled 32"] -pub type REN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN33` reader - Rising edge enabled 33"] -pub type REN33_R = crate::BitReader; +pub type REN33_R = crate::BitReader; #[doc = "Field `REN33` writer - Rising edge enabled 33"] -pub type REN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN34` reader - Rising edge enabled 34"] -pub type REN34_R = crate::BitReader; +pub type REN34_R = crate::BitReader; #[doc = "Field `REN34` writer - Rising edge enabled 34"] -pub type REN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN35` reader - Rising edge enabled 35"] -pub type REN35_R = crate::BitReader; +pub type REN35_R = crate::BitReader; #[doc = "Field `REN35` writer - Rising edge enabled 35"] -pub type REN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN36` reader - Rising edge enabled 36"] -pub type REN36_R = crate::BitReader; +pub type REN36_R = crate::BitReader; #[doc = "Field `REN36` writer - Rising edge enabled 36"] -pub type REN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN37` reader - Rising edge enabled 37"] -pub type REN37_R = crate::BitReader; +pub type REN37_R = crate::BitReader; #[doc = "Field `REN37` writer - Rising edge enabled 37"] -pub type REN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN38` reader - Rising edge enabled 38"] -pub type REN38_R = crate::BitReader; +pub type REN38_R = crate::BitReader; #[doc = "Field `REN38` writer - Rising edge enabled 38"] -pub type REN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN39` reader - Rising edge enabled 39"] -pub type REN39_R = crate::BitReader; +pub type REN39_R = crate::BitReader; #[doc = "Field `REN39` writer - Rising edge enabled 39"] -pub type REN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN40` reader - Rising edge enabled 40"] -pub type REN40_R = crate::BitReader; +pub type REN40_R = crate::BitReader; #[doc = "Field `REN40` writer - Rising edge enabled 40"] -pub type REN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN41` reader - Rising edge enabled 41"] -pub type REN41_R = crate::BitReader; +pub type REN41_R = crate::BitReader; #[doc = "Field `REN41` writer - Rising edge enabled 41"] -pub type REN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN42` reader - Rising edge enabled 42"] -pub type REN42_R = crate::BitReader; +pub type REN42_R = crate::BitReader; #[doc = "Field `REN42` writer - Rising edge enabled 42"] -pub type REN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN43` reader - Rising edge enabled 43"] -pub type REN43_R = crate::BitReader; +pub type REN43_R = crate::BitReader; #[doc = "Field `REN43` writer - Rising edge enabled 43"] -pub type REN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN44` reader - Rising edge enabled 44"] -pub type REN44_R = crate::BitReader; +pub type REN44_R = crate::BitReader; #[doc = "Field `REN44` writer - Rising edge enabled 44"] -pub type REN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN45` reader - Rising edge enabled 45"] -pub type REN45_R = crate::BitReader; +pub type REN45_R = crate::BitReader; #[doc = "Field `REN45` writer - Rising edge enabled 45"] -pub type REN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN46` reader - Rising edge enabled 46"] -pub type REN46_R = crate::BitReader; +pub type REN46_R = crate::BitReader; #[doc = "Field `REN46` writer - Rising edge enabled 46"] -pub type REN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN47` reader - Rising edge enabled 47"] -pub type REN47_R = crate::BitReader; +pub type REN47_R = crate::BitReader; #[doc = "Field `REN47` writer - Rising edge enabled 47"] -pub type REN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN48` reader - Rising edge enabled 48"] -pub type REN48_R = crate::BitReader; +pub type REN48_R = crate::BitReader; #[doc = "Field `REN48` writer - Rising edge enabled 48"] -pub type REN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN49` reader - Rising edge enabled 49"] -pub type REN49_R = crate::BitReader; +pub type REN49_R = crate::BitReader; #[doc = "Field `REN49` writer - Rising edge enabled 49"] -pub type REN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN50` reader - Rising edge enabled 50"] -pub type REN50_R = crate::BitReader; +pub type REN50_R = crate::BitReader; #[doc = "Field `REN50` writer - Rising edge enabled 50"] -pub type REN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN51` reader - Rising edge enabled 51"] -pub type REN51_R = crate::BitReader; +pub type REN51_R = crate::BitReader; #[doc = "Field `REN51` writer - Rising edge enabled 51"] -pub type REN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN52` reader - Rising edge enabled 52"] -pub type REN52_R = crate::BitReader; +pub type REN52_R = crate::BitReader; #[doc = "Field `REN52` writer - Rising edge enabled 52"] -pub type REN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN53` reader - Rising edge enabled 53"] -pub type REN53_R = crate::BitReader; +pub type REN53_R = crate::BitReader; #[doc = "Field `REN53` writer - Rising edge enabled 53"] -pub type REN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Rising edge enabled 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { REN53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPREN1") + .field("ren32", &format_args!("{}", self.ren32().bit())) + .field("ren33", &format_args!("{}", self.ren33().bit())) + .field("ren34", &format_args!("{}", self.ren34().bit())) + .field("ren35", &format_args!("{}", self.ren35().bit())) + .field("ren36", &format_args!("{}", self.ren36().bit())) + .field("ren37", &format_args!("{}", self.ren37().bit())) + .field("ren38", &format_args!("{}", self.ren38().bit())) + .field("ren39", &format_args!("{}", self.ren39().bit())) + .field("ren40", &format_args!("{}", self.ren40().bit())) + .field("ren41", &format_args!("{}", self.ren41().bit())) + .field("ren42", &format_args!("{}", self.ren42().bit())) + .field("ren43", &format_args!("{}", self.ren43().bit())) + .field("ren44", &format_args!("{}", self.ren44().bit())) + .field("ren45", &format_args!("{}", self.ren45().bit())) + .field("ren46", &format_args!("{}", self.ren46().bit())) + .field("ren47", &format_args!("{}", self.ren47().bit())) + .field("ren48", &format_args!("{}", self.ren48().bit())) + .field("ren49", &format_args!("{}", self.ren49().bit())) + .field("ren50", &format_args!("{}", self.ren50().bit())) + .field("ren51", &format_args!("{}", self.ren51().bit())) + .field("ren52", &format_args!("{}", self.ren52().bit())) + .field("ren53", &format_args!("{}", self.ren53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Rising edge enabled 32"] #[inline(always)] #[must_use] - pub fn ren32(&mut self) -> REN32_W<0> { + pub fn ren32(&mut self) -> REN32_W { REN32_W::new(self) } #[doc = "Bit 1 - Rising edge enabled 33"] #[inline(always)] #[must_use] - pub fn ren33(&mut self) -> REN33_W<1> { + pub fn ren33(&mut self) -> REN33_W { REN33_W::new(self) } #[doc = "Bit 2 - Rising edge enabled 34"] #[inline(always)] #[must_use] - pub fn ren34(&mut self) -> REN34_W<2> { + pub fn ren34(&mut self) -> REN34_W { REN34_W::new(self) } #[doc = "Bit 3 - Rising edge enabled 35"] #[inline(always)] #[must_use] - pub fn ren35(&mut self) -> REN35_W<3> { + pub fn ren35(&mut self) -> REN35_W { REN35_W::new(self) } #[doc = "Bit 4 - Rising edge enabled 36"] #[inline(always)] #[must_use] - pub fn ren36(&mut self) -> REN36_W<4> { + pub fn ren36(&mut self) -> REN36_W { REN36_W::new(self) } #[doc = "Bit 5 - Rising edge enabled 37"] #[inline(always)] #[must_use] - pub fn ren37(&mut self) -> REN37_W<5> { + pub fn ren37(&mut self) -> REN37_W { REN37_W::new(self) } #[doc = "Bit 6 - Rising edge enabled 38"] #[inline(always)] #[must_use] - pub fn ren38(&mut self) -> REN38_W<6> { + pub fn ren38(&mut self) -> REN38_W { REN38_W::new(self) } #[doc = "Bit 7 - Rising edge enabled 39"] #[inline(always)] #[must_use] - pub fn ren39(&mut self) -> REN39_W<7> { + pub fn ren39(&mut self) -> REN39_W { REN39_W::new(self) } #[doc = "Bit 8 - Rising edge enabled 40"] #[inline(always)] #[must_use] - pub fn ren40(&mut self) -> REN40_W<8> { + pub fn ren40(&mut self) -> REN40_W { REN40_W::new(self) } #[doc = "Bit 9 - Rising edge enabled 41"] #[inline(always)] #[must_use] - pub fn ren41(&mut self) -> REN41_W<9> { + pub fn ren41(&mut self) -> REN41_W { REN41_W::new(self) } #[doc = "Bit 10 - Rising edge enabled 42"] #[inline(always)] #[must_use] - pub fn ren42(&mut self) -> REN42_W<10> { + pub fn ren42(&mut self) -> REN42_W { REN42_W::new(self) } #[doc = "Bit 11 - Rising edge enabled 43"] #[inline(always)] #[must_use] - pub fn ren43(&mut self) -> REN43_W<11> { + pub fn ren43(&mut self) -> REN43_W { REN43_W::new(self) } #[doc = "Bit 12 - Rising edge enabled 44"] #[inline(always)] #[must_use] - pub fn ren44(&mut self) -> REN44_W<12> { + pub fn ren44(&mut self) -> REN44_W { REN44_W::new(self) } #[doc = "Bit 13 - Rising edge enabled 45"] #[inline(always)] #[must_use] - pub fn ren45(&mut self) -> REN45_W<13> { + pub fn ren45(&mut self) -> REN45_W { REN45_W::new(self) } #[doc = "Bit 14 - Rising edge enabled 46"] #[inline(always)] #[must_use] - pub fn ren46(&mut self) -> REN46_W<14> { + pub fn ren46(&mut self) -> REN46_W { REN46_W::new(self) } #[doc = "Bit 15 - Rising edge enabled 47"] #[inline(always)] #[must_use] - pub fn ren47(&mut self) -> REN47_W<15> { + pub fn ren47(&mut self) -> REN47_W { REN47_W::new(self) } #[doc = "Bit 16 - Rising edge enabled 48"] #[inline(always)] #[must_use] - pub fn ren48(&mut self) -> REN48_W<16> { + pub fn ren48(&mut self) -> REN48_W { REN48_W::new(self) } #[doc = "Bit 17 - Rising edge enabled 49"] #[inline(always)] #[must_use] - pub fn ren49(&mut self) -> REN49_W<17> { + pub fn ren49(&mut self) -> REN49_W { REN49_W::new(self) } #[doc = "Bit 18 - Rising edge enabled 50"] #[inline(always)] #[must_use] - pub fn ren50(&mut self) -> REN50_W<18> { + pub fn ren50(&mut self) -> REN50_W { REN50_W::new(self) } #[doc = "Bit 19 - Rising edge enabled 51"] #[inline(always)] #[must_use] - pub fn ren51(&mut self) -> REN51_W<19> { + pub fn ren51(&mut self) -> REN51_W { REN51_W::new(self) } #[doc = "Bit 20 - Rising edge enabled 52"] #[inline(always)] #[must_use] - pub fn ren52(&mut self) -> REN52_W<20> { + pub fn ren52(&mut self) -> REN52_W { REN52_W::new(self) } #[doc = "Bit 21 - Rising edge enabled 53"] #[inline(always)] #[must_use] - pub fn ren53(&mut self) -> REN53_W<21> { + pub fn ren53(&mut self) -> REN53_W { REN53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Rising Edge Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpren1](index.html) module"] +#[doc = "GPIO Pin Rising Edge Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpren1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpren1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPREN1_SPEC; impl crate::RegisterSpec for GPREN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpren1::R](R) reader structure"] -impl crate::Readable for GPREN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpren1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpren1::R`](R) reader structure"] +impl crate::Readable for GPREN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpren1::W`](W) writer structure"] impl crate::Writable for GPREN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/gpio/gpset0.rs b/crates/bcm2835-lpa/src/gpio/gpset0.rs index 49e2659..513781b 100644 --- a/crates/bcm2835-lpa/src/gpio/gpset0.rs +++ b/crates/bcm2835-lpa/src/gpio/gpset0.rs @@ -1,296 +1,285 @@ #[doc = "Register `GPSET0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SET0` writer - Set 0"] -pub type SET0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET1` writer - Set 1"] -pub type SET1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET2` writer - Set 2"] -pub type SET2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET3` writer - Set 3"] -pub type SET3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET4` writer - Set 4"] -pub type SET4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET5` writer - Set 5"] -pub type SET5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET6` writer - Set 6"] -pub type SET6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET7` writer - Set 7"] -pub type SET7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET7_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET8` writer - Set 8"] -pub type SET8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET8_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET9` writer - Set 9"] -pub type SET9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET9_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET10` writer - Set 10"] -pub type SET10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET10_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET11` writer - Set 11"] -pub type SET11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET11_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET12` writer - Set 12"] -pub type SET12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET12_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET13` writer - Set 13"] -pub type SET13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET13_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET14` writer - Set 14"] -pub type SET14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET14_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET15` writer - Set 15"] -pub type SET15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET15_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET16` writer - Set 16"] -pub type SET16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET16_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET17` writer - Set 17"] -pub type SET17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET17_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET18` writer - Set 18"] -pub type SET18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET18_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET19` writer - Set 19"] -pub type SET19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET19_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET20` writer - Set 20"] -pub type SET20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET20_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET21` writer - Set 21"] -pub type SET21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET21_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET22` writer - Set 22"] -pub type SET22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET22_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET23` writer - Set 23"] -pub type SET23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET23_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET24` writer - Set 24"] -pub type SET24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET24_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET25` writer - Set 25"] -pub type SET25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET25_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET26` writer - Set 26"] -pub type SET26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET26_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET27` writer - Set 27"] -pub type SET27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET27_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET28` writer - Set 28"] -pub type SET28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET28_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET29` writer - Set 29"] -pub type SET29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET29_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET30` writer - Set 30"] -pub type SET30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET30_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET31` writer - Set 31"] -pub type SET31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET31_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - Set 0"] #[inline(always)] #[must_use] - pub fn set0(&mut self) -> SET0_W<0> { + pub fn set0(&mut self) -> SET0_W { SET0_W::new(self) } #[doc = "Bit 1 - Set 1"] #[inline(always)] #[must_use] - pub fn set1(&mut self) -> SET1_W<1> { + pub fn set1(&mut self) -> SET1_W { SET1_W::new(self) } #[doc = "Bit 2 - Set 2"] #[inline(always)] #[must_use] - pub fn set2(&mut self) -> SET2_W<2> { + pub fn set2(&mut self) -> SET2_W { SET2_W::new(self) } #[doc = "Bit 3 - Set 3"] #[inline(always)] #[must_use] - pub fn set3(&mut self) -> SET3_W<3> { + pub fn set3(&mut self) -> SET3_W { SET3_W::new(self) } #[doc = "Bit 4 - Set 4"] #[inline(always)] #[must_use] - pub fn set4(&mut self) -> SET4_W<4> { + pub fn set4(&mut self) -> SET4_W { SET4_W::new(self) } #[doc = "Bit 5 - Set 5"] #[inline(always)] #[must_use] - pub fn set5(&mut self) -> SET5_W<5> { + pub fn set5(&mut self) -> SET5_W { SET5_W::new(self) } #[doc = "Bit 6 - Set 6"] #[inline(always)] #[must_use] - pub fn set6(&mut self) -> SET6_W<6> { + pub fn set6(&mut self) -> SET6_W { SET6_W::new(self) } #[doc = "Bit 7 - Set 7"] #[inline(always)] #[must_use] - pub fn set7(&mut self) -> SET7_W<7> { + pub fn set7(&mut self) -> SET7_W { SET7_W::new(self) } #[doc = "Bit 8 - Set 8"] #[inline(always)] #[must_use] - pub fn set8(&mut self) -> SET8_W<8> { + pub fn set8(&mut self) -> SET8_W { SET8_W::new(self) } #[doc = "Bit 9 - Set 9"] #[inline(always)] #[must_use] - pub fn set9(&mut self) -> SET9_W<9> { + pub fn set9(&mut self) -> SET9_W { SET9_W::new(self) } #[doc = "Bit 10 - Set 10"] #[inline(always)] #[must_use] - pub fn set10(&mut self) -> SET10_W<10> { + pub fn set10(&mut self) -> SET10_W { SET10_W::new(self) } #[doc = "Bit 11 - Set 11"] #[inline(always)] #[must_use] - pub fn set11(&mut self) -> SET11_W<11> { + pub fn set11(&mut self) -> SET11_W { SET11_W::new(self) } #[doc = "Bit 12 - Set 12"] #[inline(always)] #[must_use] - pub fn set12(&mut self) -> SET12_W<12> { + pub fn set12(&mut self) -> SET12_W { SET12_W::new(self) } #[doc = "Bit 13 - Set 13"] #[inline(always)] #[must_use] - pub fn set13(&mut self) -> SET13_W<13> { + pub fn set13(&mut self) -> SET13_W { SET13_W::new(self) } #[doc = "Bit 14 - Set 14"] #[inline(always)] #[must_use] - pub fn set14(&mut self) -> SET14_W<14> { + pub fn set14(&mut self) -> SET14_W { SET14_W::new(self) } #[doc = "Bit 15 - Set 15"] #[inline(always)] #[must_use] - pub fn set15(&mut self) -> SET15_W<15> { + pub fn set15(&mut self) -> SET15_W { SET15_W::new(self) } #[doc = "Bit 16 - Set 16"] #[inline(always)] #[must_use] - pub fn set16(&mut self) -> SET16_W<16> { + pub fn set16(&mut self) -> SET16_W { SET16_W::new(self) } #[doc = "Bit 17 - Set 17"] #[inline(always)] #[must_use] - pub fn set17(&mut self) -> SET17_W<17> { + pub fn set17(&mut self) -> SET17_W { SET17_W::new(self) } #[doc = "Bit 18 - Set 18"] #[inline(always)] #[must_use] - pub fn set18(&mut self) -> SET18_W<18> { + pub fn set18(&mut self) -> SET18_W { SET18_W::new(self) } #[doc = "Bit 19 - Set 19"] #[inline(always)] #[must_use] - pub fn set19(&mut self) -> SET19_W<19> { + pub fn set19(&mut self) -> SET19_W { SET19_W::new(self) } #[doc = "Bit 20 - Set 20"] #[inline(always)] #[must_use] - pub fn set20(&mut self) -> SET20_W<20> { + pub fn set20(&mut self) -> SET20_W { SET20_W::new(self) } #[doc = "Bit 21 - Set 21"] #[inline(always)] #[must_use] - pub fn set21(&mut self) -> SET21_W<21> { + pub fn set21(&mut self) -> SET21_W { SET21_W::new(self) } #[doc = "Bit 22 - Set 22"] #[inline(always)] #[must_use] - pub fn set22(&mut self) -> SET22_W<22> { + pub fn set22(&mut self) -> SET22_W { SET22_W::new(self) } #[doc = "Bit 23 - Set 23"] #[inline(always)] #[must_use] - pub fn set23(&mut self) -> SET23_W<23> { + pub fn set23(&mut self) -> SET23_W { SET23_W::new(self) } #[doc = "Bit 24 - Set 24"] #[inline(always)] #[must_use] - pub fn set24(&mut self) -> SET24_W<24> { + pub fn set24(&mut self) -> SET24_W { SET24_W::new(self) } #[doc = "Bit 25 - Set 25"] #[inline(always)] #[must_use] - pub fn set25(&mut self) -> SET25_W<25> { + pub fn set25(&mut self) -> SET25_W { SET25_W::new(self) } #[doc = "Bit 26 - Set 26"] #[inline(always)] #[must_use] - pub fn set26(&mut self) -> SET26_W<26> { + pub fn set26(&mut self) -> SET26_W { SET26_W::new(self) } #[doc = "Bit 27 - Set 27"] #[inline(always)] #[must_use] - pub fn set27(&mut self) -> SET27_W<27> { + pub fn set27(&mut self) -> SET27_W { SET27_W::new(self) } #[doc = "Bit 28 - Set 28"] #[inline(always)] #[must_use] - pub fn set28(&mut self) -> SET28_W<28> { + pub fn set28(&mut self) -> SET28_W { SET28_W::new(self) } #[doc = "Bit 29 - Set 29"] #[inline(always)] #[must_use] - pub fn set29(&mut self) -> SET29_W<29> { + pub fn set29(&mut self) -> SET29_W { SET29_W::new(self) } #[doc = "Bit 30 - Set 30"] #[inline(always)] #[must_use] - pub fn set30(&mut self) -> SET30_W<30> { + pub fn set30(&mut self) -> SET30_W { SET30_W::new(self) } #[doc = "Bit 31 - Set 31"] #[inline(always)] #[must_use] - pub fn set31(&mut self) -> SET31_W<31> { + pub fn set31(&mut self) -> SET31_W { SET31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Output Set 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpset0](index.html) module"] +#[doc = "GPIO Pin Output Set 0\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpset0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPSET0_SPEC; impl crate::RegisterSpec for GPSET0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpset0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpset0::W`](W) writer structure"] impl crate::Writable for GPSET0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2835-lpa/src/gpio/gpset1.rs b/crates/bcm2835-lpa/src/gpio/gpset1.rs index 84f73e5..b6b4b3f 100644 --- a/crates/bcm2835-lpa/src/gpio/gpset1.rs +++ b/crates/bcm2835-lpa/src/gpio/gpset1.rs @@ -1,216 +1,205 @@ #[doc = "Register `GPSET1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SET32` writer - Set 32"] -pub type SET32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET32_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET33` writer - Set 33"] -pub type SET33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET33_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET34` writer - Set 34"] -pub type SET34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET34_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET35` writer - Set 35"] -pub type SET35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET35_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET36` writer - Set 36"] -pub type SET36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET36_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET37` writer - Set 37"] -pub type SET37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET37_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET38` writer - Set 38"] -pub type SET38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET38_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET39` writer - Set 39"] -pub type SET39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET39_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET40` writer - Set 40"] -pub type SET40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET40_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET41` writer - Set 41"] -pub type SET41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET41_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET42` writer - Set 42"] -pub type SET42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET42_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET43` writer - Set 43"] -pub type SET43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET43_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET44` writer - Set 44"] -pub type SET44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET44_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET45` writer - Set 45"] -pub type SET45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET45_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET46` writer - Set 46"] -pub type SET46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET46_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET47` writer - Set 47"] -pub type SET47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET47_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET48` writer - Set 48"] -pub type SET48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET48_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET49` writer - Set 49"] -pub type SET49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET49_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET50` writer - Set 50"] -pub type SET50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET50_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET51` writer - Set 51"] -pub type SET51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET51_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET52` writer - Set 52"] -pub type SET52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET52_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET53` writer - Set 53"] -pub type SET53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET53_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - Set 32"] #[inline(always)] #[must_use] - pub fn set32(&mut self) -> SET32_W<0> { + pub fn set32(&mut self) -> SET32_W { SET32_W::new(self) } #[doc = "Bit 1 - Set 33"] #[inline(always)] #[must_use] - pub fn set33(&mut self) -> SET33_W<1> { + pub fn set33(&mut self) -> SET33_W { SET33_W::new(self) } #[doc = "Bit 2 - Set 34"] #[inline(always)] #[must_use] - pub fn set34(&mut self) -> SET34_W<2> { + pub fn set34(&mut self) -> SET34_W { SET34_W::new(self) } #[doc = "Bit 3 - Set 35"] #[inline(always)] #[must_use] - pub fn set35(&mut self) -> SET35_W<3> { + pub fn set35(&mut self) -> SET35_W { SET35_W::new(self) } #[doc = "Bit 4 - Set 36"] #[inline(always)] #[must_use] - pub fn set36(&mut self) -> SET36_W<4> { + pub fn set36(&mut self) -> SET36_W { SET36_W::new(self) } #[doc = "Bit 5 - Set 37"] #[inline(always)] #[must_use] - pub fn set37(&mut self) -> SET37_W<5> { + pub fn set37(&mut self) -> SET37_W { SET37_W::new(self) } #[doc = "Bit 6 - Set 38"] #[inline(always)] #[must_use] - pub fn set38(&mut self) -> SET38_W<6> { + pub fn set38(&mut self) -> SET38_W { SET38_W::new(self) } #[doc = "Bit 7 - Set 39"] #[inline(always)] #[must_use] - pub fn set39(&mut self) -> SET39_W<7> { + pub fn set39(&mut self) -> SET39_W { SET39_W::new(self) } #[doc = "Bit 8 - Set 40"] #[inline(always)] #[must_use] - pub fn set40(&mut self) -> SET40_W<8> { + pub fn set40(&mut self) -> SET40_W { SET40_W::new(self) } #[doc = "Bit 9 - Set 41"] #[inline(always)] #[must_use] - pub fn set41(&mut self) -> SET41_W<9> { + pub fn set41(&mut self) -> SET41_W { SET41_W::new(self) } #[doc = "Bit 10 - Set 42"] #[inline(always)] #[must_use] - pub fn set42(&mut self) -> SET42_W<10> { + pub fn set42(&mut self) -> SET42_W { SET42_W::new(self) } #[doc = "Bit 11 - Set 43"] #[inline(always)] #[must_use] - pub fn set43(&mut self) -> SET43_W<11> { + pub fn set43(&mut self) -> SET43_W { SET43_W::new(self) } #[doc = "Bit 12 - Set 44"] #[inline(always)] #[must_use] - pub fn set44(&mut self) -> SET44_W<12> { + pub fn set44(&mut self) -> SET44_W { SET44_W::new(self) } #[doc = "Bit 13 - Set 45"] #[inline(always)] #[must_use] - pub fn set45(&mut self) -> SET45_W<13> { + pub fn set45(&mut self) -> SET45_W { SET45_W::new(self) } #[doc = "Bit 14 - Set 46"] #[inline(always)] #[must_use] - pub fn set46(&mut self) -> SET46_W<14> { + pub fn set46(&mut self) -> SET46_W { SET46_W::new(self) } #[doc = "Bit 15 - Set 47"] #[inline(always)] #[must_use] - pub fn set47(&mut self) -> SET47_W<15> { + pub fn set47(&mut self) -> SET47_W { SET47_W::new(self) } #[doc = "Bit 16 - Set 48"] #[inline(always)] #[must_use] - pub fn set48(&mut self) -> SET48_W<16> { + pub fn set48(&mut self) -> SET48_W { SET48_W::new(self) } #[doc = "Bit 17 - Set 49"] #[inline(always)] #[must_use] - pub fn set49(&mut self) -> SET49_W<17> { + pub fn set49(&mut self) -> SET49_W { SET49_W::new(self) } #[doc = "Bit 18 - Set 50"] #[inline(always)] #[must_use] - pub fn set50(&mut self) -> SET50_W<18> { + pub fn set50(&mut self) -> SET50_W { SET50_W::new(self) } #[doc = "Bit 19 - Set 51"] #[inline(always)] #[must_use] - pub fn set51(&mut self) -> SET51_W<19> { + pub fn set51(&mut self) -> SET51_W { SET51_W::new(self) } #[doc = "Bit 20 - Set 52"] #[inline(always)] #[must_use] - pub fn set52(&mut self) -> SET52_W<20> { + pub fn set52(&mut self) -> SET52_W { SET52_W::new(self) } #[doc = "Bit 21 - Set 53"] #[inline(always)] #[must_use] - pub fn set53(&mut self) -> SET53_W<21> { + pub fn set53(&mut self) -> SET53_W { SET53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Output Set 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpset1](index.html) module"] +#[doc = "GPIO Pin Output Set 1\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpset1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPSET1_SPEC; impl crate::RegisterSpec for GPSET1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpset1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpset1::W`](W) writer structure"] impl crate::Writable for GPSET1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x003f_ffff; } diff --git a/crates/bcm2835-lpa/src/lib.rs b/crates/bcm2835-lpa/src/lib.rs index 076b9d0..b6592f3 100644 --- a/crates/bcm2835-lpa/src/lib.rs +++ b/crates/bcm2835-lpa/src/lib.rs @@ -1,5 +1,5 @@ -#![doc = "Peripheral access API for BCM2835_LPA microcontrollers (generated using svd2rust v0.28.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] -svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.28.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![doc = "Peripheral access API for BCM2835_LPA microcontrollers (generated using svd2rust v0.30.2 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.30.2/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -8,7 +8,8 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] +#![deny(private_bounds)] +#![deny(private_interfaces)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] @@ -41,6 +42,24 @@ impl VCMAILBOX { pub const fn ptr() -> *const vcmailbox::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for VCMAILBOX { type Target = vcmailbox::RegisterBlock; @@ -69,6 +88,24 @@ impl PM { pub const fn ptr() -> *const pm::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PM { type Target = pm::RegisterBlock; @@ -97,6 +134,24 @@ impl CM_PCM { pub const fn ptr() -> *const cm_pcm::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for CM_PCM { type Target = cm_pcm::RegisterBlock; @@ -125,6 +180,24 @@ impl CM_PWM { pub const fn ptr() -> *const cm_pcm::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for CM_PWM { type Target = cm_pcm::RegisterBlock; @@ -153,6 +226,24 @@ impl GPIO { pub const fn ptr() -> *const gpio::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for GPIO { type Target = gpio::RegisterBlock; @@ -181,6 +272,24 @@ impl SYSTMR { pub const fn ptr() -> *const systmr::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SYSTMR { type Target = systmr::RegisterBlock; @@ -209,6 +318,24 @@ impl UART0 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART0 { type Target = uart0::RegisterBlock; @@ -237,6 +364,24 @@ impl SPI0 { pub const fn ptr() -> *const spi0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI0 { type Target = spi0::RegisterBlock; @@ -265,6 +410,24 @@ impl BSC0 { pub const fn ptr() -> *const bsc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for BSC0 { type Target = bsc0::RegisterBlock; @@ -293,6 +456,24 @@ impl PWM0 { pub const fn ptr() -> *const pwm0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PWM0 { type Target = pwm0::RegisterBlock; @@ -321,6 +502,24 @@ impl BSC1 { pub const fn ptr() -> *const bsc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for BSC1 { type Target = bsc0::RegisterBlock; @@ -349,6 +548,24 @@ impl BSC2 { pub const fn ptr() -> *const bsc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for BSC2 { type Target = bsc0::RegisterBlock; @@ -377,6 +594,24 @@ impl AUX { pub const fn ptr() -> *const aux::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for AUX { type Target = aux::RegisterBlock; @@ -405,6 +640,24 @@ impl UART1 { pub const fn ptr() -> *const uart1::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART1 { type Target = uart1::RegisterBlock; @@ -433,6 +686,24 @@ impl SPI1 { pub const fn ptr() -> *const spi1::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI1 { type Target = spi1::RegisterBlock; @@ -461,6 +732,24 @@ impl SPI2 { pub const fn ptr() -> *const spi1::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI2 { type Target = spi1::RegisterBlock; @@ -489,6 +778,24 @@ impl LIC { pub const fn ptr() -> *const lic::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for LIC { type Target = lic::RegisterBlock; @@ -517,6 +824,24 @@ impl USB_OTG_GLOBAL { pub const fn ptr() -> *const usb_otg_global::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USB_OTG_GLOBAL { type Target = usb_otg_global::RegisterBlock; @@ -545,6 +870,24 @@ impl USB_OTG_HOST { pub const fn ptr() -> *const usb_otg_host::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USB_OTG_HOST { type Target = usb_otg_host::RegisterBlock; @@ -573,6 +916,24 @@ impl USB_OTG_DEVICE { pub const fn ptr() -> *const usb_otg_device::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USB_OTG_DEVICE { type Target = usb_otg_device::RegisterBlock; @@ -601,6 +962,24 @@ impl USB_OTG_PWRCLK { pub const fn ptr() -> *const usb_otg_pwrclk::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USB_OTG_PWRCLK { type Target = usb_otg_pwrclk::RegisterBlock; @@ -629,6 +1008,24 @@ impl EMMC { pub const fn ptr() -> *const emmc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for EMMC { type Target = emmc::RegisterBlock; diff --git a/crates/bcm2835-lpa/src/lic.rs b/crates/bcm2835-lpa/src/lic.rs index bc15cd4..36d6423 100644 --- a/crates/bcm2835-lpa/src/lic.rs +++ b/crates/bcm2835-lpa/src/lic.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { _reserved0: [u8; 0x0200], #[doc = "0x200 - Basic pending info"] @@ -23,43 +24,53 @@ pub struct RegisterBlock { #[doc = "0x224 - Disable basic interrupts"] pub disable_basic: DISABLE_BASIC, } -#[doc = "BASIC_PENDING (r) register accessor: an alias for `Reg`"] +#[doc = "BASIC_PENDING (r) register accessor: Basic pending info\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`basic_pending::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@basic_pending`] +module"] pub type BASIC_PENDING = crate::Reg; #[doc = "Basic pending info"] pub mod basic_pending; -#[doc = "PENDING_1 (r) register accessor: an alias for `Reg`"] +#[doc = "PENDING_1 (r) register accessor: Pending state for interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_1`] +module"] pub type PENDING_1 = crate::Reg; #[doc = "Pending state for interrupts 1 - 31"] pub mod pending_1; -#[doc = "PENDING_2 (r) register accessor: an alias for `Reg`"] +#[doc = "PENDING_2 (r) register accessor: Pending state for interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_2`] +module"] pub type PENDING_2 = crate::Reg; #[doc = "Pending state for interrupts 32 - 63"] pub mod pending_2; -#[doc = "FIQ_CONTROL (rw) register accessor: an alias for `Reg`"] +#[doc = "FIQ_CONTROL (rw) register accessor: FIQ control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fiq_control::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fiq_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fiq_control`] +module"] pub type FIQ_CONTROL = crate::Reg; #[doc = "FIQ control"] pub mod fiq_control; -#[doc = "ENABLE_1 (rw) register accessor: an alias for `Reg`"] +#[doc = "ENABLE_1 (rw) register accessor: Enable interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_1`] +module"] pub type ENABLE_1 = crate::Reg; #[doc = "Enable interrupts 1 - 31"] pub mod enable_1; -#[doc = "ENABLE_2 (rw) register accessor: an alias for `Reg`"] +#[doc = "ENABLE_2 (rw) register accessor: Enable interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_2`] +module"] pub type ENABLE_2 = crate::Reg; #[doc = "Enable interrupts 32 - 63"] pub mod enable_2; -#[doc = "ENABLE_BASIC (rw) register accessor: an alias for `Reg`"] +#[doc = "ENABLE_BASIC (rw) register accessor: Enable basic interrupts\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_basic::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_basic::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_basic`] +module"] pub type ENABLE_BASIC = crate::Reg; #[doc = "Enable basic interrupts"] pub mod enable_basic; -#[doc = "DISABLE_1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DISABLE_1 (rw) register accessor: Disable interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@disable_1`] +module"] pub type DISABLE_1 = crate::Reg; #[doc = "Disable interrupts 1 - 31"] pub mod disable_1; -#[doc = "DISABLE_2 (rw) register accessor: an alias for `Reg`"] +#[doc = "DISABLE_2 (rw) register accessor: Disable interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@disable_2`] +module"] pub type DISABLE_2 = crate::Reg; #[doc = "Disable interrupts 32 - 63"] pub mod disable_2; -#[doc = "DISABLE_BASIC (rw) register accessor: an alias for `Reg`"] +#[doc = "DISABLE_BASIC (rw) register accessor: Disable basic interrupts\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_basic::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_basic::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@disable_basic`] +module"] pub type DISABLE_BASIC = crate::Reg; #[doc = "Disable basic interrupts"] pub mod disable_basic; diff --git a/crates/bcm2835-lpa/src/lic/basic_pending.rs b/crates/bcm2835-lpa/src/lic/basic_pending.rs index c7dcea2..a88fcb1 100644 --- a/crates/bcm2835-lpa/src/lic/basic_pending.rs +++ b/crates/bcm2835-lpa/src/lic/basic_pending.rs @@ -1,60 +1,47 @@ #[doc = "Register `BASIC_PENDING` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `PENDING_1` reader - One or more bits are set in PENDING_1 (ignores 7, 9, 10, 18, 19)"] -pub type PENDING_1_R = crate::BitReader; +pub type PENDING_1_R = crate::BitReader; #[doc = "Field `PENDING_2` reader - One or more bits are set in PENDING_2 (ignores 53 - 57, 62)"] -pub type PENDING_2_R = crate::BitReader; +pub type PENDING_2_R = crate::BitReader; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -162,15 +149,51 @@ impl R { EMMC_R::new(((self.bits >> 20) & 1) != 0) } } -#[doc = "Basic pending info\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [basic_pending](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BASIC_PENDING") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .field("pending_1", &format_args!("{}", self.pending_1().bit())) + .field("pending_2", &format_args!("{}", self.pending_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Basic pending info\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`basic_pending::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BASIC_PENDING_SPEC; impl crate::RegisterSpec for BASIC_PENDING_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [basic_pending::R](R) reader structure"] -impl crate::Readable for BASIC_PENDING_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`basic_pending::R`](R) reader structure"] +impl crate::Readable for BASIC_PENDING_SPEC {} #[doc = "`reset()` method sets BASIC_PENDING to value 0"] impl crate::Resettable for BASIC_PENDING_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/lic/disable_1.rs b/crates/bcm2835-lpa/src/lic/disable_1.rs index 5c8027d..efd5fcf 100644 --- a/crates/bcm2835-lpa/src/lic/disable_1.rs +++ b/crates/bcm2835-lpa/src/lic/disable_1.rs @@ -1,167 +1,135 @@ #[doc = "Register `DISABLE_1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DISABLE_1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -324,218 +292,274 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DISABLE_1") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bit 1 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<1> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bit 2 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<2> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bit 3 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<3> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } #[doc = "Bit 4 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<4> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bit 5 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<5> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bit 6 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<6> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bit 7 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<7> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } #[doc = "Bit 8 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<8> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bit 9 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<9> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 10 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<10> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bit 11 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } #[doc = "Bit 12 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bit 13 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bit 14 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bit 15 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } #[doc = "Bit 16 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<16> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bit 17 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<17> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 18 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<18> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 19 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<19> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 20 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<20> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 21 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<21> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 22 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<22> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 23 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } #[doc = "Bit 24 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bit 25 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<25> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bit 26 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<26> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bit 27 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<27> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } #[doc = "Bit 28 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<28> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<29> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bit 30 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<30> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bit 31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<31> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Disable interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_1](index.html) module"] +#[doc = "Disable interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DISABLE_1_SPEC; impl crate::RegisterSpec for DISABLE_1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [disable_1::R](R) reader structure"] -impl crate::Readable for DISABLE_1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [disable_1::W](W) writer structure"] +#[doc = "`read()` method returns [`disable_1::R`](R) reader structure"] +impl crate::Readable for DISABLE_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`disable_1::W`](W) writer structure"] impl crate::Writable for DISABLE_1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2835-lpa/src/lic/disable_2.rs b/crates/bcm2835-lpa/src/lic/disable_2.rs index 9334cf8..05263c3 100644 --- a/crates/bcm2835-lpa/src/lic/disable_2.rs +++ b/crates/bcm2835-lpa/src/lic/disable_2.rs @@ -1,167 +1,135 @@ #[doc = "Register `DISABLE_2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DISABLE_2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type UART_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -324,218 +292,280 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DISABLE_2") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bit 1 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<1> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bit 2 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<2> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bit 3 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<3> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } #[doc = "Bit 4 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<4> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bit 5 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bit 6 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bit 7 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } #[doc = "Bit 8 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bit 9 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bit 10 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bit 11 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } #[doc = "Bit 12 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<12> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bit 13 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bit 15 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<15> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } #[doc = "Bit 16 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<16> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bit 17 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bit 18 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bit 19 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } #[doc = "Bit 20 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bit 21 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<21> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bit 22 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<22> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bit 23 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } #[doc = "Bit 24 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<24> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bit 25 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<25> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bit 26 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bit 27 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<27> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } #[doc = "Bit 28 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<28> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bit 29 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<29> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bit 30 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<30> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bit 31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Disable interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_2](index.html) module"] +#[doc = "Disable interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DISABLE_2_SPEC; impl crate::RegisterSpec for DISABLE_2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [disable_2::R](R) reader structure"] -impl crate::Readable for DISABLE_2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [disable_2::W](W) writer structure"] +#[doc = "`read()` method returns [`disable_2::R`](R) reader structure"] +impl crate::Readable for DISABLE_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`disable_2::W`](W) writer structure"] impl crate::Writable for DISABLE_2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2835-lpa/src/lic/disable_basic.rs b/crates/bcm2835-lpa/src/lic/disable_basic.rs index df73f14..da28ed6 100644 --- a/crates/bcm2835-lpa/src/lic/disable_basic.rs +++ b/crates/bcm2835-lpa/src/lic/disable_basic.rs @@ -1,73 +1,39 @@ #[doc = "Register `DISABLE_BASIC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DISABLE_BASIC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -110,74 +76,100 @@ impl R { ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DISABLE_BASIC") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Disable basic interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_basic](index.html) module"] +#[doc = "Disable basic interrupts\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_basic::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_basic::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DISABLE_BASIC_SPEC; impl crate::RegisterSpec for DISABLE_BASIC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [disable_basic::R](R) reader structure"] -impl crate::Readable for DISABLE_BASIC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [disable_basic::W](W) writer structure"] +#[doc = "`read()` method returns [`disable_basic::R`](R) reader structure"] +impl crate::Readable for DISABLE_BASIC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`disable_basic::W`](W) writer structure"] impl crate::Writable for DISABLE_BASIC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; } diff --git a/crates/bcm2835-lpa/src/lic/enable_1.rs b/crates/bcm2835-lpa/src/lic/enable_1.rs index e9aa7ce..d55fb6e 100644 --- a/crates/bcm2835-lpa/src/lic/enable_1.rs +++ b/crates/bcm2835-lpa/src/lic/enable_1.rs @@ -1,167 +1,135 @@ #[doc = "Register `ENABLE_1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ENABLE_1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -324,218 +292,274 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLE_1") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bit 1 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<1> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bit 2 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<2> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bit 3 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<3> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } #[doc = "Bit 4 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<4> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bit 5 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<5> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bit 6 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<6> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bit 7 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<7> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } #[doc = "Bit 8 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<8> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bit 9 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<9> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 10 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<10> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bit 11 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } #[doc = "Bit 12 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bit 13 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bit 14 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bit 15 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } #[doc = "Bit 16 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<16> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bit 17 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<17> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 18 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<18> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 19 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<19> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 20 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<20> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 21 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<21> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 22 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<22> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 23 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } #[doc = "Bit 24 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bit 25 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<25> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bit 26 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<26> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bit 27 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<27> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } #[doc = "Bit 28 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<28> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<29> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bit 30 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<30> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bit 31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<31> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_1](index.html) module"] +#[doc = "Enable interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLE_1_SPEC; impl crate::RegisterSpec for ENABLE_1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enable_1::R](R) reader structure"] -impl crate::Readable for ENABLE_1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [enable_1::W](W) writer structure"] +#[doc = "`read()` method returns [`enable_1::R`](R) reader structure"] +impl crate::Readable for ENABLE_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enable_1::W`](W) writer structure"] impl crate::Writable for ENABLE_1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2835-lpa/src/lic/enable_2.rs b/crates/bcm2835-lpa/src/lic/enable_2.rs index 45e156d..43769aa 100644 --- a/crates/bcm2835-lpa/src/lic/enable_2.rs +++ b/crates/bcm2835-lpa/src/lic/enable_2.rs @@ -1,167 +1,135 @@ #[doc = "Register `ENABLE_2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ENABLE_2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type UART_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -324,218 +292,280 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLE_2") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bit 1 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<1> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bit 2 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<2> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bit 3 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<3> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } #[doc = "Bit 4 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<4> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bit 5 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bit 6 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bit 7 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } #[doc = "Bit 8 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bit 9 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bit 10 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bit 11 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } #[doc = "Bit 12 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<12> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bit 13 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bit 15 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<15> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } #[doc = "Bit 16 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<16> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bit 17 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bit 18 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bit 19 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } #[doc = "Bit 20 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bit 21 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<21> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bit 22 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<22> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bit 23 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } #[doc = "Bit 24 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<24> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bit 25 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<25> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bit 26 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bit 27 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<27> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } #[doc = "Bit 28 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<28> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bit 29 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<29> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bit 30 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<30> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bit 31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_2](index.html) module"] +#[doc = "Enable interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLE_2_SPEC; impl crate::RegisterSpec for ENABLE_2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enable_2::R](R) reader structure"] -impl crate::Readable for ENABLE_2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [enable_2::W](W) writer structure"] +#[doc = "`read()` method returns [`enable_2::R`](R) reader structure"] +impl crate::Readable for ENABLE_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enable_2::W`](W) writer structure"] impl crate::Writable for ENABLE_2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2835-lpa/src/lic/enable_basic.rs b/crates/bcm2835-lpa/src/lic/enable_basic.rs index b401deb..3533529 100644 --- a/crates/bcm2835-lpa/src/lic/enable_basic.rs +++ b/crates/bcm2835-lpa/src/lic/enable_basic.rs @@ -1,72 +1,39 @@ #[doc = "Register `ENABLE_BASIC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ENABLE_BASIC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -109,74 +76,100 @@ impl R { ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLE_BASIC") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable basic interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_basic](index.html) module"] +#[doc = "Enable basic interrupts\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_basic::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_basic::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLE_BASIC_SPEC; impl crate::RegisterSpec for ENABLE_BASIC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enable_basic::R](R) reader structure"] -impl crate::Readable for ENABLE_BASIC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [enable_basic::W](W) writer structure"] +#[doc = "`read()` method returns [`enable_basic::R`](R) reader structure"] +impl crate::Readable for ENABLE_BASIC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enable_basic::W`](W) writer structure"] impl crate::Writable for ENABLE_BASIC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; } diff --git a/crates/bcm2835-lpa/src/lic/fiq_control.rs b/crates/bcm2835-lpa/src/lic/fiq_control.rs index d1b5d51..e7bc947 100644 --- a/crates/bcm2835-lpa/src/lic/fiq_control.rs +++ b/crates/bcm2835-lpa/src/lic/fiq_control.rs @@ -1,41 +1,9 @@ #[doc = "Register `FIQ_CONTROL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FIQ_CONTROL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SOURCE` reader - FIQ Source"] -pub type SOURCE_R = crate::FieldReader; +pub type SOURCE_R = crate::FieldReader; #[doc = "FIQ Source\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -191,10 +159,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for SOURCE_A { + type Ux = u8; +} impl SOURCE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(SOURCE_A::TIMER_0), 1 => Some(SOURCE_A::TIMER_1), @@ -271,736 +242,739 @@ impl SOURCE_R { _ => None, } } - #[doc = "Checks if the value of the field is `TIMER_0`"] + #[doc = "Timer 0"] #[inline(always)] pub fn is_timer_0(&self) -> bool { *self == SOURCE_A::TIMER_0 } - #[doc = "Checks if the value of the field is `TIMER_1`"] + #[doc = "Timer 1"] #[inline(always)] pub fn is_timer_1(&self) -> bool { *self == SOURCE_A::TIMER_1 } - #[doc = "Checks if the value of the field is `TIMER_2`"] + #[doc = "Timer 2"] #[inline(always)] pub fn is_timer_2(&self) -> bool { *self == SOURCE_A::TIMER_2 } - #[doc = "Checks if the value of the field is `TIMER_3`"] + #[doc = "Timer 3"] #[inline(always)] pub fn is_timer_3(&self) -> bool { *self == SOURCE_A::TIMER_3 } - #[doc = "Checks if the value of the field is `H264_0`"] + #[doc = "H264 0"] #[inline(always)] pub fn is_h264_0(&self) -> bool { *self == SOURCE_A::H264_0 } - #[doc = "Checks if the value of the field is `H264_1`"] + #[doc = "H264 1"] #[inline(always)] pub fn is_h264_1(&self) -> bool { *self == SOURCE_A::H264_1 } - #[doc = "Checks if the value of the field is `H264_2`"] + #[doc = "H264 2"] #[inline(always)] pub fn is_h264_2(&self) -> bool { *self == SOURCE_A::H264_2 } - #[doc = "Checks if the value of the field is `JPEG`"] + #[doc = "JPEG"] #[inline(always)] pub fn is_jpeg(&self) -> bool { *self == SOURCE_A::JPEG } - #[doc = "Checks if the value of the field is `ISP`"] + #[doc = "ISP"] #[inline(always)] pub fn is_isp(&self) -> bool { *self == SOURCE_A::ISP } - #[doc = "Checks if the value of the field is `USB`"] + #[doc = "USB"] #[inline(always)] pub fn is_usb(&self) -> bool { *self == SOURCE_A::USB } - #[doc = "Checks if the value of the field is `V3D`"] + #[doc = "V3D"] #[inline(always)] pub fn is_v3d(&self) -> bool { *self == SOURCE_A::V3D } - #[doc = "Checks if the value of the field is `TRANSPOSER`"] + #[doc = "Transposer"] #[inline(always)] pub fn is_transposer(&self) -> bool { *self == SOURCE_A::TRANSPOSER } - #[doc = "Checks if the value of the field is `MULTICORE_SYNC_0`"] + #[doc = "Multicore Sync 0"] #[inline(always)] pub fn is_multicore_sync_0(&self) -> bool { *self == SOURCE_A::MULTICORE_SYNC_0 } - #[doc = "Checks if the value of the field is `MULTICORE_SYNC_1`"] + #[doc = "Multicore Sync 1"] #[inline(always)] pub fn is_multicore_sync_1(&self) -> bool { *self == SOURCE_A::MULTICORE_SYNC_1 } - #[doc = "Checks if the value of the field is `MULTICORE_SYNC_2`"] + #[doc = "Multicore Sync 2"] #[inline(always)] pub fn is_multicore_sync_2(&self) -> bool { *self == SOURCE_A::MULTICORE_SYNC_2 } - #[doc = "Checks if the value of the field is `MULTICORE_SYNC_3`"] + #[doc = "Multicore Sync 3"] #[inline(always)] pub fn is_multicore_sync_3(&self) -> bool { *self == SOURCE_A::MULTICORE_SYNC_3 } - #[doc = "Checks if the value of the field is `DMA_0`"] + #[doc = "DMA 0"] #[inline(always)] pub fn is_dma_0(&self) -> bool { *self == SOURCE_A::DMA_0 } - #[doc = "Checks if the value of the field is `DMA_1`"] + #[doc = "DMA 1"] #[inline(always)] pub fn is_dma_1(&self) -> bool { *self == SOURCE_A::DMA_1 } - #[doc = "Checks if the value of the field is `DMA_2`"] + #[doc = "DMA 2"] #[inline(always)] pub fn is_dma_2(&self) -> bool { *self == SOURCE_A::DMA_2 } - #[doc = "Checks if the value of the field is `DMA_3`"] + #[doc = "DMA 3"] #[inline(always)] pub fn is_dma_3(&self) -> bool { *self == SOURCE_A::DMA_3 } - #[doc = "Checks if the value of the field is `DMA_4`"] + #[doc = "DMA 4"] #[inline(always)] pub fn is_dma_4(&self) -> bool { *self == SOURCE_A::DMA_4 } - #[doc = "Checks if the value of the field is `DMA_5`"] + #[doc = "DMA 5"] #[inline(always)] pub fn is_dma_5(&self) -> bool { *self == SOURCE_A::DMA_5 } - #[doc = "Checks if the value of the field is `DMA_6`"] + #[doc = "DMA 6"] #[inline(always)] pub fn is_dma_6(&self) -> bool { *self == SOURCE_A::DMA_6 } - #[doc = "Checks if the value of the field is `DMA_7_8`"] + #[doc = "OR of DMA 7 and 8"] #[inline(always)] pub fn is_dma_7_8(&self) -> bool { *self == SOURCE_A::DMA_7_8 } - #[doc = "Checks if the value of the field is `DMA_9_10`"] + #[doc = "OR of DMA 9 and 10"] #[inline(always)] pub fn is_dma_9_10(&self) -> bool { *self == SOURCE_A::DMA_9_10 } - #[doc = "Checks if the value of the field is `DMA_11`"] + #[doc = "DMA 11"] #[inline(always)] pub fn is_dma_11(&self) -> bool { *self == SOURCE_A::DMA_11 } - #[doc = "Checks if the value of the field is `DMA_12`"] + #[doc = "DMA 12"] #[inline(always)] pub fn is_dma_12(&self) -> bool { *self == SOURCE_A::DMA_12 } - #[doc = "Checks if the value of the field is `DMA_13`"] + #[doc = "DMA 13"] #[inline(always)] pub fn is_dma_13(&self) -> bool { *self == SOURCE_A::DMA_13 } - #[doc = "Checks if the value of the field is `DMA_14`"] + #[doc = "DMA 14"] #[inline(always)] pub fn is_dma_14(&self) -> bool { *self == SOURCE_A::DMA_14 } - #[doc = "Checks if the value of the field is `AUX`"] + #[doc = "OR of UART1, SPI1 and SPI2"] #[inline(always)] pub fn is_aux(&self) -> bool { *self == SOURCE_A::AUX } - #[doc = "Checks if the value of the field is `ARM`"] + #[doc = "ARM"] #[inline(always)] pub fn is_arm(&self) -> bool { *self == SOURCE_A::ARM } - #[doc = "Checks if the value of the field is `DMA_15`"] + #[doc = "DMA 15"] #[inline(always)] pub fn is_dma_15(&self) -> bool { *self == SOURCE_A::DMA_15 } - #[doc = "Checks if the value of the field is `HDMI_CEC`"] + #[doc = "HDMI CEC"] #[inline(always)] pub fn is_hdmi_cec(&self) -> bool { *self == SOURCE_A::HDMI_CEC } - #[doc = "Checks if the value of the field is `HVS`"] + #[doc = "HVS"] #[inline(always)] pub fn is_hvs(&self) -> bool { *self == SOURCE_A::HVS } - #[doc = "Checks if the value of the field is `RPIVID`"] + #[doc = "RPIVID"] #[inline(always)] pub fn is_rpivid(&self) -> bool { *self == SOURCE_A::RPIVID } - #[doc = "Checks if the value of the field is `SDC`"] + #[doc = "SDC"] #[inline(always)] pub fn is_sdc(&self) -> bool { *self == SOURCE_A::SDC } - #[doc = "Checks if the value of the field is `DSI_0`"] + #[doc = "DSI 0"] #[inline(always)] pub fn is_dsi_0(&self) -> bool { *self == SOURCE_A::DSI_0 } - #[doc = "Checks if the value of the field is `PIXEL_VALVE_2`"] + #[doc = "Pixel Valve 2"] #[inline(always)] pub fn is_pixel_valve_2(&self) -> bool { *self == SOURCE_A::PIXEL_VALVE_2 } - #[doc = "Checks if the value of the field is `CAMERA_0`"] + #[doc = "Camera 0"] #[inline(always)] pub fn is_camera_0(&self) -> bool { *self == SOURCE_A::CAMERA_0 } - #[doc = "Checks if the value of the field is `CAMERA_1`"] + #[doc = "Camera 1"] #[inline(always)] pub fn is_camera_1(&self) -> bool { *self == SOURCE_A::CAMERA_1 } - #[doc = "Checks if the value of the field is `HDMI_0`"] + #[doc = "HDMI 0"] #[inline(always)] pub fn is_hdmi_0(&self) -> bool { *self == SOURCE_A::HDMI_0 } - #[doc = "Checks if the value of the field is `HDMI_1`"] + #[doc = "HDMI 1"] #[inline(always)] pub fn is_hdmi_1(&self) -> bool { *self == SOURCE_A::HDMI_1 } - #[doc = "Checks if the value of the field is `PIXEL_VALVE_3`"] + #[doc = "Pixel Valve 3"] #[inline(always)] pub fn is_pixel_valve_3(&self) -> bool { *self == SOURCE_A::PIXEL_VALVE_3 } - #[doc = "Checks if the value of the field is `SPI_BSC_SLAVE`"] + #[doc = "SPI/BSC Slave"] #[inline(always)] pub fn is_spi_bsc_slave(&self) -> bool { *self == SOURCE_A::SPI_BSC_SLAVE } - #[doc = "Checks if the value of the field is `DSI_1`"] + #[doc = "DSI 1"] #[inline(always)] pub fn is_dsi_1(&self) -> bool { *self == SOURCE_A::DSI_1 } - #[doc = "Checks if the value of the field is `PIXEL_VALVE_0`"] + #[doc = "Pixel Valve 0"] #[inline(always)] pub fn is_pixel_valve_0(&self) -> bool { *self == SOURCE_A::PIXEL_VALVE_0 } - #[doc = "Checks if the value of the field is `PIXEL_VALVE_1_2`"] + #[doc = "OR of Pixel Valve 1 and 2"] #[inline(always)] pub fn is_pixel_valve_1_2(&self) -> bool { *self == SOURCE_A::PIXEL_VALVE_1_2 } - #[doc = "Checks if the value of the field is `CPR`"] + #[doc = "CPR"] #[inline(always)] pub fn is_cpr(&self) -> bool { *self == SOURCE_A::CPR } - #[doc = "Checks if the value of the field is `SMI`"] + #[doc = "SMI"] #[inline(always)] pub fn is_smi(&self) -> bool { *self == SOURCE_A::SMI } - #[doc = "Checks if the value of the field is `GPIO_0`"] + #[doc = "GPIO 0"] #[inline(always)] pub fn is_gpio_0(&self) -> bool { *self == SOURCE_A::GPIO_0 } - #[doc = "Checks if the value of the field is `GPIO_1`"] + #[doc = "GPIO 1"] #[inline(always)] pub fn is_gpio_1(&self) -> bool { *self == SOURCE_A::GPIO_1 } - #[doc = "Checks if the value of the field is `GPIO_2`"] + #[doc = "GPIO 2"] #[inline(always)] pub fn is_gpio_2(&self) -> bool { *self == SOURCE_A::GPIO_2 } - #[doc = "Checks if the value of the field is `GPIO_3`"] + #[doc = "GPIO 3"] #[inline(always)] pub fn is_gpio_3(&self) -> bool { *self == SOURCE_A::GPIO_3 } - #[doc = "Checks if the value of the field is `I2C`"] + #[doc = "OR of all I2C"] #[inline(always)] pub fn is_i2c(&self) -> bool { *self == SOURCE_A::I2C } - #[doc = "Checks if the value of the field is `SPI`"] + #[doc = "OR of all SPI"] #[inline(always)] pub fn is_spi(&self) -> bool { *self == SOURCE_A::SPI } - #[doc = "Checks if the value of the field is `PCM_I2S`"] + #[doc = "PCM/I2S"] #[inline(always)] pub fn is_pcm_i2s(&self) -> bool { *self == SOURCE_A::PCM_I2S } - #[doc = "Checks if the value of the field is `SDHOST`"] + #[doc = "SDHOST"] #[inline(always)] pub fn is_sdhost(&self) -> bool { *self == SOURCE_A::SDHOST } - #[doc = "Checks if the value of the field is `UART`"] + #[doc = "OR of all PL011 UARTs"] #[inline(always)] pub fn is_uart(&self) -> bool { *self == SOURCE_A::UART } - #[doc = "Checks if the value of the field is `ETH_PCIE`"] + #[doc = "OR of all ETH_PCIe L2"] #[inline(always)] pub fn is_eth_pcie(&self) -> bool { *self == SOURCE_A::ETH_PCIE } - #[doc = "Checks if the value of the field is `VEC`"] + #[doc = "VEC"] #[inline(always)] pub fn is_vec(&self) -> bool { *self == SOURCE_A::VEC } - #[doc = "Checks if the value of the field is `CPG`"] + #[doc = "CPG"] #[inline(always)] pub fn is_cpg(&self) -> bool { *self == SOURCE_A::CPG } - #[doc = "Checks if the value of the field is `RNG`"] + #[doc = "RNG"] #[inline(always)] pub fn is_rng(&self) -> bool { *self == SOURCE_A::RNG } - #[doc = "Checks if the value of the field is `EMMC`"] + #[doc = "OR of EMMC and EMMC2"] #[inline(always)] pub fn is_emmc(&self) -> bool { *self == SOURCE_A::EMMC } - #[doc = "Checks if the value of the field is `ETH_PCIE_SECURE`"] + #[doc = "ETH_PCIe secure"] #[inline(always)] pub fn is_eth_pcie_secure(&self) -> bool { *self == SOURCE_A::ETH_PCIE_SECURE } - #[doc = "Checks if the value of the field is `TIMER`"] + #[doc = "ARMC Timer"] #[inline(always)] pub fn is_timer(&self) -> bool { *self == SOURCE_A::TIMER } - #[doc = "Checks if the value of the field is `MAILBOX`"] + #[doc = "Mailbox"] #[inline(always)] pub fn is_mailbox(&self) -> bool { *self == SOURCE_A::MAILBOX } - #[doc = "Checks if the value of the field is `DOORBELL0`"] + #[doc = "Doorbell 0"] #[inline(always)] pub fn is_doorbell0(&self) -> bool { *self == SOURCE_A::DOORBELL0 } - #[doc = "Checks if the value of the field is `DOORBELL1`"] + #[doc = "Doorbell 1"] #[inline(always)] pub fn is_doorbell1(&self) -> bool { *self == SOURCE_A::DOORBELL1 } - #[doc = "Checks if the value of the field is `VPU0_HALTED`"] + #[doc = "VPU0 halted"] #[inline(always)] pub fn is_vpu0_halted(&self) -> bool { *self == SOURCE_A::VPU0_HALTED } - #[doc = "Checks if the value of the field is `VPU1_HALTED`"] + #[doc = "VPU1 halted"] #[inline(always)] pub fn is_vpu1_halted(&self) -> bool { *self == SOURCE_A::VPU1_HALTED } - #[doc = "Checks if the value of the field is `ARM_ADDRESS_ERROR`"] + #[doc = "ARM address error"] #[inline(always)] pub fn is_arm_address_error(&self) -> bool { *self == SOURCE_A::ARM_ADDRESS_ERROR } - #[doc = "Checks if the value of the field is `ARM_AXI_ERROR`"] + #[doc = "ARM AXI error"] #[inline(always)] pub fn is_arm_axi_error(&self) -> bool { *self == SOURCE_A::ARM_AXI_ERROR } } #[doc = "Field `SOURCE` writer - FIQ Source"] -pub type SOURCE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, FIQ_CONTROL_SPEC, u8, SOURCE_A, 7, O>; -impl<'a, const O: u8> SOURCE_W<'a, O> { +pub type SOURCE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O, SOURCE_A>; +impl<'a, REG, const O: u8> SOURCE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Timer 0"] #[inline(always)] - pub fn timer_0(self) -> &'a mut W { + pub fn timer_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::TIMER_0) } #[doc = "Timer 1"] #[inline(always)] - pub fn timer_1(self) -> &'a mut W { + pub fn timer_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::TIMER_1) } #[doc = "Timer 2"] #[inline(always)] - pub fn timer_2(self) -> &'a mut W { + pub fn timer_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::TIMER_2) } #[doc = "Timer 3"] #[inline(always)] - pub fn timer_3(self) -> &'a mut W { + pub fn timer_3(self) -> &'a mut crate::W { self.variant(SOURCE_A::TIMER_3) } #[doc = "H264 0"] #[inline(always)] - pub fn h264_0(self) -> &'a mut W { + pub fn h264_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::H264_0) } #[doc = "H264 1"] #[inline(always)] - pub fn h264_1(self) -> &'a mut W { + pub fn h264_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::H264_1) } #[doc = "H264 2"] #[inline(always)] - pub fn h264_2(self) -> &'a mut W { + pub fn h264_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::H264_2) } #[doc = "JPEG"] #[inline(always)] - pub fn jpeg(self) -> &'a mut W { + pub fn jpeg(self) -> &'a mut crate::W { self.variant(SOURCE_A::JPEG) } #[doc = "ISP"] #[inline(always)] - pub fn isp(self) -> &'a mut W { + pub fn isp(self) -> &'a mut crate::W { self.variant(SOURCE_A::ISP) } #[doc = "USB"] #[inline(always)] - pub fn usb(self) -> &'a mut W { + pub fn usb(self) -> &'a mut crate::W { self.variant(SOURCE_A::USB) } #[doc = "V3D"] #[inline(always)] - pub fn v3d(self) -> &'a mut W { + pub fn v3d(self) -> &'a mut crate::W { self.variant(SOURCE_A::V3D) } #[doc = "Transposer"] #[inline(always)] - pub fn transposer(self) -> &'a mut W { + pub fn transposer(self) -> &'a mut crate::W { self.variant(SOURCE_A::TRANSPOSER) } #[doc = "Multicore Sync 0"] #[inline(always)] - pub fn multicore_sync_0(self) -> &'a mut W { + pub fn multicore_sync_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::MULTICORE_SYNC_0) } #[doc = "Multicore Sync 1"] #[inline(always)] - pub fn multicore_sync_1(self) -> &'a mut W { + pub fn multicore_sync_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::MULTICORE_SYNC_1) } #[doc = "Multicore Sync 2"] #[inline(always)] - pub fn multicore_sync_2(self) -> &'a mut W { + pub fn multicore_sync_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::MULTICORE_SYNC_2) } #[doc = "Multicore Sync 3"] #[inline(always)] - pub fn multicore_sync_3(self) -> &'a mut W { + pub fn multicore_sync_3(self) -> &'a mut crate::W { self.variant(SOURCE_A::MULTICORE_SYNC_3) } #[doc = "DMA 0"] #[inline(always)] - pub fn dma_0(self) -> &'a mut W { + pub fn dma_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_0) } #[doc = "DMA 1"] #[inline(always)] - pub fn dma_1(self) -> &'a mut W { + pub fn dma_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_1) } #[doc = "DMA 2"] #[inline(always)] - pub fn dma_2(self) -> &'a mut W { + pub fn dma_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_2) } #[doc = "DMA 3"] #[inline(always)] - pub fn dma_3(self) -> &'a mut W { + pub fn dma_3(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_3) } #[doc = "DMA 4"] #[inline(always)] - pub fn dma_4(self) -> &'a mut W { + pub fn dma_4(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_4) } #[doc = "DMA 5"] #[inline(always)] - pub fn dma_5(self) -> &'a mut W { + pub fn dma_5(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_5) } #[doc = "DMA 6"] #[inline(always)] - pub fn dma_6(self) -> &'a mut W { + pub fn dma_6(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_6) } #[doc = "OR of DMA 7 and 8"] #[inline(always)] - pub fn dma_7_8(self) -> &'a mut W { + pub fn dma_7_8(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_7_8) } #[doc = "OR of DMA 9 and 10"] #[inline(always)] - pub fn dma_9_10(self) -> &'a mut W { + pub fn dma_9_10(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_9_10) } #[doc = "DMA 11"] #[inline(always)] - pub fn dma_11(self) -> &'a mut W { + pub fn dma_11(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_11) } #[doc = "DMA 12"] #[inline(always)] - pub fn dma_12(self) -> &'a mut W { + pub fn dma_12(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_12) } #[doc = "DMA 13"] #[inline(always)] - pub fn dma_13(self) -> &'a mut W { + pub fn dma_13(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_13) } #[doc = "DMA 14"] #[inline(always)] - pub fn dma_14(self) -> &'a mut W { + pub fn dma_14(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_14) } #[doc = "OR of UART1, SPI1 and SPI2"] #[inline(always)] - pub fn aux(self) -> &'a mut W { + pub fn aux(self) -> &'a mut crate::W { self.variant(SOURCE_A::AUX) } #[doc = "ARM"] #[inline(always)] - pub fn arm(self) -> &'a mut W { + pub fn arm(self) -> &'a mut crate::W { self.variant(SOURCE_A::ARM) } #[doc = "DMA 15"] #[inline(always)] - pub fn dma_15(self) -> &'a mut W { + pub fn dma_15(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_15) } #[doc = "HDMI CEC"] #[inline(always)] - pub fn hdmi_cec(self) -> &'a mut W { + pub fn hdmi_cec(self) -> &'a mut crate::W { self.variant(SOURCE_A::HDMI_CEC) } #[doc = "HVS"] #[inline(always)] - pub fn hvs(self) -> &'a mut W { + pub fn hvs(self) -> &'a mut crate::W { self.variant(SOURCE_A::HVS) } #[doc = "RPIVID"] #[inline(always)] - pub fn rpivid(self) -> &'a mut W { + pub fn rpivid(self) -> &'a mut crate::W { self.variant(SOURCE_A::RPIVID) } #[doc = "SDC"] #[inline(always)] - pub fn sdc(self) -> &'a mut W { + pub fn sdc(self) -> &'a mut crate::W { self.variant(SOURCE_A::SDC) } #[doc = "DSI 0"] #[inline(always)] - pub fn dsi_0(self) -> &'a mut W { + pub fn dsi_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::DSI_0) } #[doc = "Pixel Valve 2"] #[inline(always)] - pub fn pixel_valve_2(self) -> &'a mut W { + pub fn pixel_valve_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::PIXEL_VALVE_2) } #[doc = "Camera 0"] #[inline(always)] - pub fn camera_0(self) -> &'a mut W { + pub fn camera_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::CAMERA_0) } #[doc = "Camera 1"] #[inline(always)] - pub fn camera_1(self) -> &'a mut W { + pub fn camera_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::CAMERA_1) } #[doc = "HDMI 0"] #[inline(always)] - pub fn hdmi_0(self) -> &'a mut W { + pub fn hdmi_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::HDMI_0) } #[doc = "HDMI 1"] #[inline(always)] - pub fn hdmi_1(self) -> &'a mut W { + pub fn hdmi_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::HDMI_1) } #[doc = "Pixel Valve 3"] #[inline(always)] - pub fn pixel_valve_3(self) -> &'a mut W { + pub fn pixel_valve_3(self) -> &'a mut crate::W { self.variant(SOURCE_A::PIXEL_VALVE_3) } #[doc = "SPI/BSC Slave"] #[inline(always)] - pub fn spi_bsc_slave(self) -> &'a mut W { + pub fn spi_bsc_slave(self) -> &'a mut crate::W { self.variant(SOURCE_A::SPI_BSC_SLAVE) } #[doc = "DSI 1"] #[inline(always)] - pub fn dsi_1(self) -> &'a mut W { + pub fn dsi_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::DSI_1) } #[doc = "Pixel Valve 0"] #[inline(always)] - pub fn pixel_valve_0(self) -> &'a mut W { + pub fn pixel_valve_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::PIXEL_VALVE_0) } #[doc = "OR of Pixel Valve 1 and 2"] #[inline(always)] - pub fn pixel_valve_1_2(self) -> &'a mut W { + pub fn pixel_valve_1_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::PIXEL_VALVE_1_2) } #[doc = "CPR"] #[inline(always)] - pub fn cpr(self) -> &'a mut W { + pub fn cpr(self) -> &'a mut crate::W { self.variant(SOURCE_A::CPR) } #[doc = "SMI"] #[inline(always)] - pub fn smi(self) -> &'a mut W { + pub fn smi(self) -> &'a mut crate::W { self.variant(SOURCE_A::SMI) } #[doc = "GPIO 0"] #[inline(always)] - pub fn gpio_0(self) -> &'a mut W { + pub fn gpio_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::GPIO_0) } #[doc = "GPIO 1"] #[inline(always)] - pub fn gpio_1(self) -> &'a mut W { + pub fn gpio_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::GPIO_1) } #[doc = "GPIO 2"] #[inline(always)] - pub fn gpio_2(self) -> &'a mut W { + pub fn gpio_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::GPIO_2) } #[doc = "GPIO 3"] #[inline(always)] - pub fn gpio_3(self) -> &'a mut W { + pub fn gpio_3(self) -> &'a mut crate::W { self.variant(SOURCE_A::GPIO_3) } #[doc = "OR of all I2C"] #[inline(always)] - pub fn i2c(self) -> &'a mut W { + pub fn i2c(self) -> &'a mut crate::W { self.variant(SOURCE_A::I2C) } #[doc = "OR of all SPI"] #[inline(always)] - pub fn spi(self) -> &'a mut W { + pub fn spi(self) -> &'a mut crate::W { self.variant(SOURCE_A::SPI) } #[doc = "PCM/I2S"] #[inline(always)] - pub fn pcm_i2s(self) -> &'a mut W { + pub fn pcm_i2s(self) -> &'a mut crate::W { self.variant(SOURCE_A::PCM_I2S) } #[doc = "SDHOST"] #[inline(always)] - pub fn sdhost(self) -> &'a mut W { + pub fn sdhost(self) -> &'a mut crate::W { self.variant(SOURCE_A::SDHOST) } #[doc = "OR of all PL011 UARTs"] #[inline(always)] - pub fn uart(self) -> &'a mut W { + pub fn uart(self) -> &'a mut crate::W { self.variant(SOURCE_A::UART) } #[doc = "OR of all ETH_PCIe L2"] #[inline(always)] - pub fn eth_pcie(self) -> &'a mut W { + pub fn eth_pcie(self) -> &'a mut crate::W { self.variant(SOURCE_A::ETH_PCIE) } #[doc = "VEC"] #[inline(always)] - pub fn vec(self) -> &'a mut W { + pub fn vec(self) -> &'a mut crate::W { self.variant(SOURCE_A::VEC) } #[doc = "CPG"] #[inline(always)] - pub fn cpg(self) -> &'a mut W { + pub fn cpg(self) -> &'a mut crate::W { self.variant(SOURCE_A::CPG) } #[doc = "RNG"] #[inline(always)] - pub fn rng(self) -> &'a mut W { + pub fn rng(self) -> &'a mut crate::W { self.variant(SOURCE_A::RNG) } #[doc = "OR of EMMC and EMMC2"] #[inline(always)] - pub fn emmc(self) -> &'a mut W { + pub fn emmc(self) -> &'a mut crate::W { self.variant(SOURCE_A::EMMC) } #[doc = "ETH_PCIe secure"] #[inline(always)] - pub fn eth_pcie_secure(self) -> &'a mut W { + pub fn eth_pcie_secure(self) -> &'a mut crate::W { self.variant(SOURCE_A::ETH_PCIE_SECURE) } #[doc = "ARMC Timer"] #[inline(always)] - pub fn timer(self) -> &'a mut W { + pub fn timer(self) -> &'a mut crate::W { self.variant(SOURCE_A::TIMER) } #[doc = "Mailbox"] #[inline(always)] - pub fn mailbox(self) -> &'a mut W { + pub fn mailbox(self) -> &'a mut crate::W { self.variant(SOURCE_A::MAILBOX) } #[doc = "Doorbell 0"] #[inline(always)] - pub fn doorbell0(self) -> &'a mut W { + pub fn doorbell0(self) -> &'a mut crate::W { self.variant(SOURCE_A::DOORBELL0) } #[doc = "Doorbell 1"] #[inline(always)] - pub fn doorbell1(self) -> &'a mut W { + pub fn doorbell1(self) -> &'a mut crate::W { self.variant(SOURCE_A::DOORBELL1) } #[doc = "VPU0 halted"] #[inline(always)] - pub fn vpu0_halted(self) -> &'a mut W { + pub fn vpu0_halted(self) -> &'a mut crate::W { self.variant(SOURCE_A::VPU0_HALTED) } #[doc = "VPU1 halted"] #[inline(always)] - pub fn vpu1_halted(self) -> &'a mut W { + pub fn vpu1_halted(self) -> &'a mut crate::W { self.variant(SOURCE_A::VPU1_HALTED) } #[doc = "ARM address error"] #[inline(always)] - pub fn arm_address_error(self) -> &'a mut W { + pub fn arm_address_error(self) -> &'a mut crate::W { self.variant(SOURCE_A::ARM_ADDRESS_ERROR) } #[doc = "ARM AXI error"] #[inline(always)] - pub fn arm_axi_error(self) -> &'a mut W { + pub fn arm_axi_error(self) -> &'a mut crate::W { self.variant(SOURCE_A::ARM_AXI_ERROR) } } #[doc = "Field `ENABLE` reader - FIQ Enable"] -pub type ENABLE_R = crate::BitReader; +pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - FIQ Enable"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIQ_CONTROL_SPEC, bool, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - FIQ Source"] #[inline(always)] @@ -1013,38 +987,52 @@ impl R { ENABLE_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIQ_CONTROL") + .field("enable", &format_args!("{}", self.enable().bit())) + .field("source", &format_args!("{}", self.source().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - FIQ Source"] #[inline(always)] #[must_use] - pub fn source(&mut self) -> SOURCE_W<0> { + pub fn source(&mut self) -> SOURCE_W { SOURCE_W::new(self) } #[doc = "Bit 7 - FIQ Enable"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<7> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "FIQ control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fiq_control](index.html) module"] +#[doc = "FIQ control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fiq_control::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fiq_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIQ_CONTROL_SPEC; impl crate::RegisterSpec for FIQ_CONTROL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fiq_control::R](R) reader structure"] -impl crate::Readable for FIQ_CONTROL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fiq_control::W](W) writer structure"] +#[doc = "`read()` method returns [`fiq_control::R`](R) reader structure"] +impl crate::Readable for FIQ_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fiq_control::W`](W) writer structure"] impl crate::Writable for FIQ_CONTROL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/lic/pending_1.rs b/crates/bcm2835-lpa/src/lic/pending_1.rs index e4ae642..8c9286e 100644 --- a/crates/bcm2835-lpa/src/lic/pending_1.rs +++ b/crates/bcm2835-lpa/src/lic/pending_1.rs @@ -1,82 +1,69 @@ #[doc = "Register `PENDING_1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -239,15 +226,68 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Pending state for interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending_1](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PENDING_1") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Pending state for interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PENDING_1_SPEC; impl crate::RegisterSpec for PENDING_1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pending_1::R](R) reader structure"] -impl crate::Readable for PENDING_1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pending_1::R`](R) reader structure"] +impl crate::Readable for PENDING_1_SPEC {} #[doc = "`reset()` method sets PENDING_1 to value 0"] impl crate::Resettable for PENDING_1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/lic/pending_2.rs b/crates/bcm2835-lpa/src/lic/pending_2.rs index f9a32c7..fcd18af 100644 --- a/crates/bcm2835-lpa/src/lic/pending_2.rs +++ b/crates/bcm2835-lpa/src/lic/pending_2.rs @@ -1,82 +1,69 @@ #[doc = "Register `PENDING_2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -239,15 +226,74 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Pending state for interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending_2](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PENDING_2") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Pending state for interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PENDING_2_SPEC; impl crate::RegisterSpec for PENDING_2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pending_2::R](R) reader structure"] -impl crate::Readable for PENDING_2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pending_2::R`](R) reader structure"] +impl crate::Readable for PENDING_2_SPEC {} #[doc = "`reset()` method sets PENDING_2 to value 0"] impl crate::Resettable for PENDING_2_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/pm.rs b/crates/bcm2835-lpa/src/pm.rs index 00ca6ac..2666514 100644 --- a/crates/bcm2835-lpa/src/pm.rs +++ b/crates/bcm2835-lpa/src/pm.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { _reserved0: [u8; 0x1c], #[doc = "0x1c - Reset Control"] @@ -8,11 +9,13 @@ pub struct RegisterBlock { #[doc = "0x24 - Watchdog control"] pub wdog: WDOG, } -#[doc = "RSTC (rw) register accessor: an alias for `Reg`"] +#[doc = "RSTC (rw) register accessor: Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstc`] +module"] pub type RSTC = crate::Reg; #[doc = "Reset Control"] pub mod rstc; -#[doc = "WDOG (rw) register accessor: an alias for `Reg`"] +#[doc = "WDOG (rw) register accessor: Watchdog control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdog::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdog::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdog`] +module"] pub type WDOG = crate::Reg; #[doc = "Watchdog control"] pub mod wdog; diff --git a/crates/bcm2835-lpa/src/pm/rstc.rs b/crates/bcm2835-lpa/src/pm/rstc.rs index 1903b76..ffd81ba 100644 --- a/crates/bcm2835-lpa/src/pm/rstc.rs +++ b/crates/bcm2835-lpa/src/pm/rstc.rs @@ -1,41 +1,9 @@ #[doc = "Register `RSTC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RSTC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WRCFG` reader - Watchdog reset config"] -pub type WRCFG_R = crate::FieldReader; +pub type WRCFG_R = crate::FieldReader; #[doc = "Watchdog reset config\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -49,27 +17,34 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for WRCFG_A { + type Ux = u8; +} impl WRCFG_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 2 => Some(WRCFG_A::FULL_RESET), _ => None, } } - #[doc = "Checks if the value of the field is `FULL_RESET`"] + #[doc = "`10`"] #[inline(always)] pub fn is_full_reset(&self) -> bool { *self == WRCFG_A::FULL_RESET } } #[doc = "Field `WRCFG` writer - Watchdog reset config"] -pub type WRCFG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSTC_SPEC, u8, WRCFG_A, 2, O>; -impl<'a, const O: u8> WRCFG_W<'a, O> { +pub type WRCFG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, WRCFG_A>; +impl<'a, REG, const O: u8> WRCFG_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`10`"] #[inline(always)] - pub fn full_reset(self) -> &'a mut W { + pub fn full_reset(self) -> &'a mut crate::W { self.variant(WRCFG_A::FULL_RESET) } } @@ -86,12 +61,19 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for PASSWD_AW { + type Ux = u8; +} #[doc = "Field `PASSWD` writer - Password. Always 0x5a"] -pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RSTC_SPEC, u8, PASSWD_AW, 8, O>; -impl<'a, const O: u8> PASSWD_W<'a, O> { +pub type PASSWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, PASSWD_AW>; +impl<'a, REG, const O: u8> PASSWD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1011010`"] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(PASSWD_AW::PASSWD) } } @@ -102,38 +84,51 @@ impl R { WRCFG_R::new(((self.bits >> 4) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSTC") + .field("wrcfg", &format_args!("{}", self.wrcfg().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 4:5 - Watchdog reset config"] #[inline(always)] #[must_use] - pub fn wrcfg(&mut self) -> WRCFG_W<4> { + pub fn wrcfg(&mut self) -> WRCFG_W { WRCFG_W::new(self) } #[doc = "Bits 24:31 - Password. Always 0x5a"] #[inline(always)] #[must_use] - pub fn passwd(&mut self) -> PASSWD_W<24> { + pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Reset Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rstc](index.html) module"] +#[doc = "Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSTC_SPEC; impl crate::RegisterSpec for RSTC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rstc::R](R) reader structure"] -impl crate::Readable for RSTC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rstc::W](W) writer structure"] +#[doc = "`read()` method returns [`rstc::R`](R) reader structure"] +impl crate::Readable for RSTC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rstc::W`](W) writer structure"] impl crate::Writable for RSTC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/pm/wdog.rs b/crates/bcm2835-lpa/src/pm/wdog.rs index d599781..ff92afc 100644 --- a/crates/bcm2835-lpa/src/pm/wdog.rs +++ b/crates/bcm2835-lpa/src/pm/wdog.rs @@ -1,43 +1,11 @@ #[doc = "Register `WDOG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WDOG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIME` reader - Time until watchdog alarm"] -pub type TIME_R = crate::FieldReader; +pub type TIME_R = crate::FieldReader; #[doc = "Field `TIME` writer - Time until watchdog alarm"] -pub type TIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WDOG_SPEC, u32, u32, 20, O>; +pub type TIME_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 20, O, u32>; #[doc = "Password. Always 0x5a\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -51,12 +19,19 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for PASSWD_AW { + type Ux = u8; +} #[doc = "Field `PASSWD` writer - Password. Always 0x5a"] -pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WDOG_SPEC, u8, PASSWD_AW, 8, O>; -impl<'a, const O: u8> PASSWD_W<'a, O> { +pub type PASSWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, PASSWD_AW>; +impl<'a, REG, const O: u8> PASSWD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1011010`"] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(PASSWD_AW::PASSWD) } } @@ -67,38 +42,51 @@ impl R { TIME_R::new(self.bits & 0x000f_ffff) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDOG") + .field("time", &format_args!("{}", self.time().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:19 - Time until watchdog alarm"] #[inline(always)] #[must_use] - pub fn time(&mut self) -> TIME_W<0> { + pub fn time(&mut self) -> TIME_W { TIME_W::new(self) } #[doc = "Bits 24:31 - Password. Always 0x5a"] #[inline(always)] #[must_use] - pub fn passwd(&mut self) -> PASSWD_W<24> { + pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Watchdog control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdog](index.html) module"] +#[doc = "Watchdog control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdog::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdog::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WDOG_SPEC; impl crate::RegisterSpec for WDOG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wdog::R](R) reader structure"] -impl crate::Readable for WDOG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wdog::W](W) writer structure"] +#[doc = "`read()` method returns [`wdog::R`](R) reader structure"] +impl crate::Readable for WDOG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdog::W`](W) writer structure"] impl crate::Writable for WDOG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/pwm0.rs b/crates/bcm2835-lpa/src/pwm0.rs index 4270433..4306916 100644 --- a/crates/bcm2835-lpa/src/pwm0.rs +++ b/crates/bcm2835-lpa/src/pwm0.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control"] pub ctl: CTL, @@ -20,35 +21,43 @@ pub struct RegisterBlock { #[doc = "0x24 - Channel 2 data"] pub dat2: DAT2, } -#[doc = "CTL (rw) register accessor: an alias for `Reg`"] +#[doc = "CTL (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl`] +module"] pub type CTL = crate::Reg; #[doc = "Control"] pub mod ctl; -#[doc = "STA (rw) register accessor: an alias for `Reg`"] +#[doc = "STA (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sta`] +module"] pub type STA = crate::Reg; #[doc = "Status"] pub mod sta; -#[doc = "DMAC (rw) register accessor: an alias for `Reg`"] +#[doc = "DMAC (rw) register accessor: DMA control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmac::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmac::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac`] +module"] pub type DMAC = crate::Reg; #[doc = "DMA control"] pub mod dmac; -#[doc = "RNG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "RNG1 (rw) register accessor: Range for channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rng1`] +module"] pub type RNG1 = crate::Reg; #[doc = "Range for channel 1"] pub mod rng1; -#[doc = "DAT1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DAT1 (rw) register accessor: Channel 1 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dat1`] +module"] pub type DAT1 = crate::Reg; #[doc = "Channel 1 data"] pub mod dat1; -#[doc = "FIF1 (w) register accessor: an alias for `Reg`"] +#[doc = "FIF1 (w) register accessor: FIFO input\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fif1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fif1`] +module"] pub type FIF1 = crate::Reg; #[doc = "FIFO input"] pub mod fif1; -#[doc = "RNG2 (rw) register accessor: an alias for `Reg`"] +#[doc = "RNG2 (rw) register accessor: Range for channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rng2`] +module"] pub type RNG2 = crate::Reg; #[doc = "Range for channel 2"] pub mod rng2; -#[doc = "DAT2 (rw) register accessor: an alias for `Reg`"] +#[doc = "DAT2 (rw) register accessor: Channel 2 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dat2`] +module"] pub type DAT2 = crate::Reg; #[doc = "Channel 2 data"] pub mod dat2; diff --git a/crates/bcm2835-lpa/src/pwm0/ctl.rs b/crates/bcm2835-lpa/src/pwm0/ctl.rs index b41b326..d1b9d57 100644 --- a/crates/bcm2835-lpa/src/pwm0/ctl.rs +++ b/crates/bcm2835-lpa/src/pwm0/ctl.rs @@ -1,43 +1,11 @@ #[doc = "Register `CTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PWEN1` reader - Enable channel 1"] -pub type PWEN1_R = crate::BitReader; +pub type PWEN1_R = crate::BitReader; #[doc = "Field `PWEN1` writer - Enable channel 1"] -pub type PWEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type PWEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MODE1` reader - Channel 1 mode"] pub type MODE1_R = crate::BitReader; #[doc = "Channel 1 mode\n\nValue on reset: 0"] @@ -57,65 +25,68 @@ impl From for bool { impl MODE1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> MODE1_A { + pub const fn variant(&self) -> MODE1_A { match self.bits { false => MODE1_A::PWM, true => MODE1_A::SERIAL, } } - #[doc = "Checks if the value of the field is `PWM`"] + #[doc = "`0`"] #[inline(always)] pub fn is_pwm(&self) -> bool { *self == MODE1_A::PWM } - #[doc = "Checks if the value of the field is `SERIAL`"] + #[doc = "`1`"] #[inline(always)] pub fn is_serial(&self) -> bool { *self == MODE1_A::SERIAL } } #[doc = "Field `MODE1` writer - Channel 1 mode"] -pub type MODE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, MODE1_A, O>; -impl<'a, const O: u8> MODE1_W<'a, O> { +pub type MODE1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MODE1_A>; +impl<'a, REG, const O: u8> MODE1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn pwm(self) -> &'a mut W { + pub fn pwm(self) -> &'a mut crate::W { self.variant(MODE1_A::PWM) } #[doc = "`1`"] #[inline(always)] - pub fn serial(self) -> &'a mut W { + pub fn serial(self) -> &'a mut crate::W { self.variant(MODE1_A::SERIAL) } } #[doc = "Field `RPTL1` reader - Repeat last value from FIFO for channel 1"] -pub type RPTL1_R = crate::BitReader; +pub type RPTL1_R = crate::BitReader; #[doc = "Field `RPTL1` writer - Repeat last value from FIFO for channel 1"] -pub type RPTL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type RPTL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SBIT1` reader - State when not transmitting on channel 1"] -pub type SBIT1_R = crate::BitReader; +pub type SBIT1_R = crate::BitReader; #[doc = "Field `SBIT1` writer - State when not transmitting on channel 1"] -pub type SBIT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type SBIT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POLA1` reader - Channel 1 polarity inverted"] -pub type POLA1_R = crate::BitReader; +pub type POLA1_R = crate::BitReader; #[doc = "Field `POLA1` writer - Channel 1 polarity inverted"] -pub type POLA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type POLA1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USEF1` reader - Use FIFO for channel 1"] -pub type USEF1_R = crate::BitReader; +pub type USEF1_R = crate::BitReader; #[doc = "Field `USEF1` writer - Use FIFO for channel 1"] -pub type USEF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type USEF1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLRF1` reader - Clear FIFO"] -pub type CLRF1_R = crate::BitReader; +pub type CLRF1_R = crate::BitReader; #[doc = "Field `CLRF1` writer - Clear FIFO"] -pub type CLRF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type CLRF1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSEN1` reader - M/S mode for channel 1"] -pub type MSEN1_R = crate::BitReader; +pub type MSEN1_R = crate::BitReader; #[doc = "Field `MSEN1` writer - M/S mode for channel 1"] -pub type MSEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type MSEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWEN2` reader - Enable channel 2"] -pub type PWEN2_R = crate::BitReader; +pub type PWEN2_R = crate::BitReader; #[doc = "Field `PWEN2` writer - Enable channel 2"] -pub type PWEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type PWEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MODE2` reader - Channel 2 mode"] pub type MODE2_R = crate::BitReader; #[doc = "Channel 2 mode\n\nValue on reset: 0"] @@ -135,57 +106,60 @@ impl From for bool { impl MODE2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> MODE2_A { + pub const fn variant(&self) -> MODE2_A { match self.bits { false => MODE2_A::PWM, true => MODE2_A::SERIAL, } } - #[doc = "Checks if the value of the field is `PWM`"] + #[doc = "`0`"] #[inline(always)] pub fn is_pwm(&self) -> bool { *self == MODE2_A::PWM } - #[doc = "Checks if the value of the field is `SERIAL`"] + #[doc = "`1`"] #[inline(always)] pub fn is_serial(&self) -> bool { *self == MODE2_A::SERIAL } } #[doc = "Field `MODE2` writer - Channel 2 mode"] -pub type MODE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, MODE2_A, O>; -impl<'a, const O: u8> MODE2_W<'a, O> { +pub type MODE2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MODE2_A>; +impl<'a, REG, const O: u8> MODE2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn pwm(self) -> &'a mut W { + pub fn pwm(self) -> &'a mut crate::W { self.variant(MODE2_A::PWM) } #[doc = "`1`"] #[inline(always)] - pub fn serial(self) -> &'a mut W { + pub fn serial(self) -> &'a mut crate::W { self.variant(MODE2_A::SERIAL) } } #[doc = "Field `RPTL2` reader - Repeat last value from FIFO for channel 2"] -pub type RPTL2_R = crate::BitReader; +pub type RPTL2_R = crate::BitReader; #[doc = "Field `RPTL2` writer - Repeat last value from FIFO for channel 2"] -pub type RPTL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type RPTL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SBIT2` reader - State when not transmitting on channel 2"] -pub type SBIT2_R = crate::BitReader; +pub type SBIT2_R = crate::BitReader; #[doc = "Field `SBIT2` writer - State when not transmitting on channel 2"] -pub type SBIT2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type SBIT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POLA2` reader - Channel 2 polarity inverted"] -pub type POLA2_R = crate::BitReader; +pub type POLA2_R = crate::BitReader; #[doc = "Field `POLA2` writer - Channel 2 polarity inverted"] -pub type POLA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type POLA2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USEF2` reader - Use FIFO for channel 2"] -pub type USEF2_R = crate::BitReader; +pub type USEF2_R = crate::BitReader; #[doc = "Field `USEF2` writer - Use FIFO for channel 2"] -pub type USEF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type USEF2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSEN2` reader - M/S mode for channel 2"] -pub type MSEN2_R = crate::BitReader; +pub type MSEN2_R = crate::BitReader; #[doc = "Field `MSEN2` writer - M/S mode for channel 2"] -pub type MSEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type MSEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable channel 1"] #[inline(always)] @@ -263,116 +237,143 @@ impl R { MSEN2_R::new(((self.bits >> 15) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTL") + .field("msen2", &format_args!("{}", self.msen2().bit())) + .field("usef2", &format_args!("{}", self.usef2().bit())) + .field("pola2", &format_args!("{}", self.pola2().bit())) + .field("sbit2", &format_args!("{}", self.sbit2().bit())) + .field("rptl2", &format_args!("{}", self.rptl2().bit())) + .field("mode2", &format_args!("{}", self.mode2().bit())) + .field("pwen2", &format_args!("{}", self.pwen2().bit())) + .field("msen1", &format_args!("{}", self.msen1().bit())) + .field("clrf1", &format_args!("{}", self.clrf1().bit())) + .field("usef1", &format_args!("{}", self.usef1().bit())) + .field("pola1", &format_args!("{}", self.pola1().bit())) + .field("sbit1", &format_args!("{}", self.sbit1().bit())) + .field("rptl1", &format_args!("{}", self.rptl1().bit())) + .field("mode1", &format_args!("{}", self.mode1().bit())) + .field("pwen1", &format_args!("{}", self.pwen1().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable channel 1"] #[inline(always)] #[must_use] - pub fn pwen1(&mut self) -> PWEN1_W<0> { + pub fn pwen1(&mut self) -> PWEN1_W { PWEN1_W::new(self) } #[doc = "Bit 1 - Channel 1 mode"] #[inline(always)] #[must_use] - pub fn mode1(&mut self) -> MODE1_W<1> { + pub fn mode1(&mut self) -> MODE1_W { MODE1_W::new(self) } #[doc = "Bit 2 - Repeat last value from FIFO for channel 1"] #[inline(always)] #[must_use] - pub fn rptl1(&mut self) -> RPTL1_W<2> { + pub fn rptl1(&mut self) -> RPTL1_W { RPTL1_W::new(self) } #[doc = "Bit 3 - State when not transmitting on channel 1"] #[inline(always)] #[must_use] - pub fn sbit1(&mut self) -> SBIT1_W<3> { + pub fn sbit1(&mut self) -> SBIT1_W { SBIT1_W::new(self) } #[doc = "Bit 4 - Channel 1 polarity inverted"] #[inline(always)] #[must_use] - pub fn pola1(&mut self) -> POLA1_W<4> { + pub fn pola1(&mut self) -> POLA1_W { POLA1_W::new(self) } #[doc = "Bit 5 - Use FIFO for channel 1"] #[inline(always)] #[must_use] - pub fn usef1(&mut self) -> USEF1_W<5> { + pub fn usef1(&mut self) -> USEF1_W { USEF1_W::new(self) } #[doc = "Bit 6 - Clear FIFO"] #[inline(always)] #[must_use] - pub fn clrf1(&mut self) -> CLRF1_W<6> { + pub fn clrf1(&mut self) -> CLRF1_W { CLRF1_W::new(self) } #[doc = "Bit 7 - M/S mode for channel 1"] #[inline(always)] #[must_use] - pub fn msen1(&mut self) -> MSEN1_W<7> { + pub fn msen1(&mut self) -> MSEN1_W { MSEN1_W::new(self) } #[doc = "Bit 8 - Enable channel 2"] #[inline(always)] #[must_use] - pub fn pwen2(&mut self) -> PWEN2_W<8> { + pub fn pwen2(&mut self) -> PWEN2_W { PWEN2_W::new(self) } #[doc = "Bit 9 - Channel 2 mode"] #[inline(always)] #[must_use] - pub fn mode2(&mut self) -> MODE2_W<9> { + pub fn mode2(&mut self) -> MODE2_W { MODE2_W::new(self) } #[doc = "Bit 10 - Repeat last value from FIFO for channel 2"] #[inline(always)] #[must_use] - pub fn rptl2(&mut self) -> RPTL2_W<10> { + pub fn rptl2(&mut self) -> RPTL2_W { RPTL2_W::new(self) } #[doc = "Bit 11 - State when not transmitting on channel 2"] #[inline(always)] #[must_use] - pub fn sbit2(&mut self) -> SBIT2_W<11> { + pub fn sbit2(&mut self) -> SBIT2_W { SBIT2_W::new(self) } #[doc = "Bit 12 - Channel 2 polarity inverted"] #[inline(always)] #[must_use] - pub fn pola2(&mut self) -> POLA2_W<12> { + pub fn pola2(&mut self) -> POLA2_W { POLA2_W::new(self) } #[doc = "Bit 13 - Use FIFO for channel 2"] #[inline(always)] #[must_use] - pub fn usef2(&mut self) -> USEF2_W<13> { + pub fn usef2(&mut self) -> USEF2_W { USEF2_W::new(self) } #[doc = "Bit 15 - M/S mode for channel 2"] #[inline(always)] #[must_use] - pub fn msen2(&mut self) -> MSEN2_W<15> { + pub fn msen2(&mut self) -> MSEN2_W { MSEN2_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL_SPEC; impl crate::RegisterSpec for CTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctl::R](R) reader structure"] -impl crate::Readable for CTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctl::W](W) writer structure"] +#[doc = "`read()` method returns [`ctl::R`](R) reader structure"] +impl crate::Readable for CTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] impl crate::Writable for CTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/pwm0/dat1.rs b/crates/bcm2835-lpa/src/pwm0/dat1.rs index c197492..b70672a 100644 --- a/crates/bcm2835-lpa/src/pwm0/dat1.rs +++ b/crates/bcm2835-lpa/src/pwm0/dat1.rs @@ -1,59 +1,38 @@ #[doc = "Register `DAT1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DAT1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel 1 data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dat1](index.html) module"] +#[doc = "Channel 1 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DAT1_SPEC; impl crate::RegisterSpec for DAT1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dat1::R](R) reader structure"] -impl crate::Readable for DAT1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dat1::W](W) writer structure"] +#[doc = "`read()` method returns [`dat1::R`](R) reader structure"] +impl crate::Readable for DAT1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dat1::W`](W) writer structure"] impl crate::Writable for DAT1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/pwm0/dat2.rs b/crates/bcm2835-lpa/src/pwm0/dat2.rs index b9e07a3..00bb85f 100644 --- a/crates/bcm2835-lpa/src/pwm0/dat2.rs +++ b/crates/bcm2835-lpa/src/pwm0/dat2.rs @@ -1,59 +1,38 @@ #[doc = "Register `DAT2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DAT2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel 2 data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dat2](index.html) module"] +#[doc = "Channel 2 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DAT2_SPEC; impl crate::RegisterSpec for DAT2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dat2::R](R) reader structure"] -impl crate::Readable for DAT2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dat2::W](W) writer structure"] +#[doc = "`read()` method returns [`dat2::R`](R) reader structure"] +impl crate::Readable for DAT2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dat2::W`](W) writer structure"] impl crate::Writable for DAT2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/pwm0/dmac.rs b/crates/bcm2835-lpa/src/pwm0/dmac.rs index b201822..d73ccfd 100644 --- a/crates/bcm2835-lpa/src/pwm0/dmac.rs +++ b/crates/bcm2835-lpa/src/pwm0/dmac.rs @@ -1,51 +1,19 @@ #[doc = "Register `DMAC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMAC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DREQ` reader - DMA threshold for DREQ signal"] -pub type DREQ_R = crate::FieldReader; +pub type DREQ_R = crate::FieldReader; #[doc = "Field `DREQ` writer - DMA threshold for DREQ signal"] -pub type DREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAC_SPEC, u8, u8, 8, O>; +pub type DREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PANIC` reader - DMA threshold for panic signal"] -pub type PANIC_R = crate::FieldReader; +pub type PANIC_R = crate::FieldReader; #[doc = "Field `PANIC` writer - DMA threshold for panic signal"] -pub type PANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAC_SPEC, u8, u8, 8, O>; +pub type PANIC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ENAB` reader - DMA enabled"] -pub type ENAB_R = crate::BitReader; +pub type ENAB_R = crate::BitReader; #[doc = "Field `ENAB` writer - DMA enabled"] -pub type ENAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAC_SPEC, bool, O>; +pub type ENAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:7 - DMA threshold for DREQ signal"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { ENAB_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC") + .field("enab", &format_args!("{}", self.enab().bit())) + .field("panic", &format_args!("{}", self.panic().bits())) + .field("dreq", &format_args!("{}", self.dreq().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DMA threshold for DREQ signal"] #[inline(always)] #[must_use] - pub fn dreq(&mut self) -> DREQ_W<0> { + pub fn dreq(&mut self) -> DREQ_W { DREQ_W::new(self) } #[doc = "Bits 8:15 - DMA threshold for panic signal"] #[inline(always)] #[must_use] - pub fn panic(&mut self) -> PANIC_W<8> { + pub fn panic(&mut self) -> PANIC_W { PANIC_W::new(self) } #[doc = "Bit 31 - DMA enabled"] #[inline(always)] #[must_use] - pub fn enab(&mut self) -> ENAB_W<31> { + pub fn enab(&mut self) -> ENAB_W { ENAB_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmac](index.html) module"] +#[doc = "DMA control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmac::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmac::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMAC_SPEC; impl crate::RegisterSpec for DMAC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dmac::R](R) reader structure"] -impl crate::Readable for DMAC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dmac::W](W) writer structure"] +#[doc = "`read()` method returns [`dmac::R`](R) reader structure"] +impl crate::Readable for DMAC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dmac::W`](W) writer structure"] impl crate::Writable for DMAC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/pwm0/fif1.rs b/crates/bcm2835-lpa/src/pwm0/fif1.rs index e786328..9cf85c2 100644 --- a/crates/bcm2835-lpa/src/pwm0/fif1.rs +++ b/crates/bcm2835-lpa/src/pwm0/fif1.rs @@ -1,40 +1,29 @@ #[doc = "Register `FIF1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +pub type W = crate::W; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "FIFO input\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fif1](index.html) module"] +#[doc = "FIFO input\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fif1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIF1_SPEC; impl crate::RegisterSpec for FIF1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [fif1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`fif1::W`](W) writer structure"] impl crate::Writable for FIF1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/pwm0/rng1.rs b/crates/bcm2835-lpa/src/pwm0/rng1.rs index b6f5446..2a01d68 100644 --- a/crates/bcm2835-lpa/src/pwm0/rng1.rs +++ b/crates/bcm2835-lpa/src/pwm0/rng1.rs @@ -1,59 +1,38 @@ #[doc = "Register `RNG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RNG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Range for channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rng1](index.html) module"] +#[doc = "Range for channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RNG1_SPEC; impl crate::RegisterSpec for RNG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rng1::R](R) reader structure"] -impl crate::Readable for RNG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rng1::W](W) writer structure"] +#[doc = "`read()` method returns [`rng1::R`](R) reader structure"] +impl crate::Readable for RNG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng1::W`](W) writer structure"] impl crate::Writable for RNG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/pwm0/rng2.rs b/crates/bcm2835-lpa/src/pwm0/rng2.rs index 0cc95d5..c7a9f74 100644 --- a/crates/bcm2835-lpa/src/pwm0/rng2.rs +++ b/crates/bcm2835-lpa/src/pwm0/rng2.rs @@ -1,59 +1,38 @@ #[doc = "Register `RNG2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RNG2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Range for channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rng2](index.html) module"] +#[doc = "Range for channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RNG2_SPEC; impl crate::RegisterSpec for RNG2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rng2::R](R) reader structure"] -impl crate::Readable for RNG2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rng2::W](W) writer structure"] +#[doc = "`read()` method returns [`rng2::R`](R) reader structure"] +impl crate::Readable for RNG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng2::W`](W) writer structure"] impl crate::Writable for RNG2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/pwm0/sta.rs b/crates/bcm2835-lpa/src/pwm0/sta.rs index f0b99b7..a0076a9 100644 --- a/crates/bcm2835-lpa/src/pwm0/sta.rs +++ b/crates/bcm2835-lpa/src/pwm0/sta.rs @@ -1,91 +1,59 @@ #[doc = "Register `STA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FULL1` reader - FIFO full"] -pub type FULL1_R = crate::BitReader; +pub type FULL1_R = crate::BitReader; #[doc = "Field `FULL1` writer - FIFO full"] -pub type FULL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type FULL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EMPT1` reader - FIFO empty"] -pub type EMPT1_R = crate::BitReader; +pub type EMPT1_R = crate::BitReader; #[doc = "Field `EMPT1` writer - FIFO empty"] -pub type EMPT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type EMPT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WERR1` reader - FIFO write error"] -pub type WERR1_R = crate::BitReader; +pub type WERR1_R = crate::BitReader; #[doc = "Field `WERR1` writer - FIFO write error"] -pub type WERR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type WERR1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RERR1` reader - FIFO read error"] -pub type RERR1_R = crate::BitReader; +pub type RERR1_R = crate::BitReader; #[doc = "Field `RERR1` writer - FIFO read error"] -pub type RERR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type RERR1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAPO1` reader - Channel 1 gap occurred"] -pub type GAPO1_R = crate::BitReader; +pub type GAPO1_R = crate::BitReader; #[doc = "Field `GAPO1` writer - Channel 1 gap occurred"] -pub type GAPO1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type GAPO1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAPO2` reader - Channel 2 gap occurred"] -pub type GAPO2_R = crate::BitReader; +pub type GAPO2_R = crate::BitReader; #[doc = "Field `GAPO2` writer - Channel 2 gap occurred"] -pub type GAPO2_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type GAPO2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAPO3` reader - Channel 3 gap occurred"] -pub type GAPO3_R = crate::BitReader; +pub type GAPO3_R = crate::BitReader; #[doc = "Field `GAPO3` writer - Channel 3 gap occurred"] -pub type GAPO3_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type GAPO3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAPO4` reader - Channel 4 gap occurred"] -pub type GAPO4_R = crate::BitReader; +pub type GAPO4_R = crate::BitReader; #[doc = "Field `GAPO4` writer - Channel 4 gap occurred"] -pub type GAPO4_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type GAPO4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BERR` reader - Bus error"] -pub type BERR_R = crate::BitReader; +pub type BERR_R = crate::BitReader; #[doc = "Field `BERR` writer - Bus error"] -pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type BERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STA1` reader - Channel 1 state"] -pub type STA1_R = crate::BitReader; +pub type STA1_R = crate::BitReader; #[doc = "Field `STA1` writer - Channel 1 state"] -pub type STA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type STA1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STA2` reader - Channel 2 state"] -pub type STA2_R = crate::BitReader; +pub type STA2_R = crate::BitReader; #[doc = "Field `STA2` writer - Channel 2 state"] -pub type STA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type STA2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STA3` reader - Channel 3 state"] -pub type STA3_R = crate::BitReader; +pub type STA3_R = crate::BitReader; #[doc = "Field `STA3` writer - Channel 3 state"] -pub type STA3_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type STA3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STA4` reader - Channel 4 state"] -pub type STA4_R = crate::BitReader; +pub type STA4_R = crate::BitReader; #[doc = "Field `STA4` writer - Channel 4 state"] -pub type STA4_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type STA4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - FIFO full"] #[inline(always)] @@ -153,104 +121,129 @@ impl R { STA4_R::new(((self.bits >> 12) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STA") + .field("sta4", &format_args!("{}", self.sta4().bit())) + .field("sta3", &format_args!("{}", self.sta3().bit())) + .field("sta2", &format_args!("{}", self.sta2().bit())) + .field("sta1", &format_args!("{}", self.sta1().bit())) + .field("berr", &format_args!("{}", self.berr().bit())) + .field("gapo4", &format_args!("{}", self.gapo4().bit())) + .field("gapo3", &format_args!("{}", self.gapo3().bit())) + .field("gapo2", &format_args!("{}", self.gapo2().bit())) + .field("gapo1", &format_args!("{}", self.gapo1().bit())) + .field("rerr1", &format_args!("{}", self.rerr1().bit())) + .field("werr1", &format_args!("{}", self.werr1().bit())) + .field("empt1", &format_args!("{}", self.empt1().bit())) + .field("full1", &format_args!("{}", self.full1().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - FIFO full"] #[inline(always)] #[must_use] - pub fn full1(&mut self) -> FULL1_W<0> { + pub fn full1(&mut self) -> FULL1_W { FULL1_W::new(self) } #[doc = "Bit 1 - FIFO empty"] #[inline(always)] #[must_use] - pub fn empt1(&mut self) -> EMPT1_W<1> { + pub fn empt1(&mut self) -> EMPT1_W { EMPT1_W::new(self) } #[doc = "Bit 2 - FIFO write error"] #[inline(always)] #[must_use] - pub fn werr1(&mut self) -> WERR1_W<2> { + pub fn werr1(&mut self) -> WERR1_W { WERR1_W::new(self) } #[doc = "Bit 3 - FIFO read error"] #[inline(always)] #[must_use] - pub fn rerr1(&mut self) -> RERR1_W<3> { + pub fn rerr1(&mut self) -> RERR1_W { RERR1_W::new(self) } #[doc = "Bit 4 - Channel 1 gap occurred"] #[inline(always)] #[must_use] - pub fn gapo1(&mut self) -> GAPO1_W<4> { + pub fn gapo1(&mut self) -> GAPO1_W { GAPO1_W::new(self) } #[doc = "Bit 5 - Channel 2 gap occurred"] #[inline(always)] #[must_use] - pub fn gapo2(&mut self) -> GAPO2_W<5> { + pub fn gapo2(&mut self) -> GAPO2_W { GAPO2_W::new(self) } #[doc = "Bit 6 - Channel 3 gap occurred"] #[inline(always)] #[must_use] - pub fn gapo3(&mut self) -> GAPO3_W<6> { + pub fn gapo3(&mut self) -> GAPO3_W { GAPO3_W::new(self) } #[doc = "Bit 7 - Channel 4 gap occurred"] #[inline(always)] #[must_use] - pub fn gapo4(&mut self) -> GAPO4_W<7> { + pub fn gapo4(&mut self) -> GAPO4_W { GAPO4_W::new(self) } #[doc = "Bit 8 - Bus error"] #[inline(always)] #[must_use] - pub fn berr(&mut self) -> BERR_W<8> { + pub fn berr(&mut self) -> BERR_W { BERR_W::new(self) } #[doc = "Bit 9 - Channel 1 state"] #[inline(always)] #[must_use] - pub fn sta1(&mut self) -> STA1_W<9> { + pub fn sta1(&mut self) -> STA1_W { STA1_W::new(self) } #[doc = "Bit 10 - Channel 2 state"] #[inline(always)] #[must_use] - pub fn sta2(&mut self) -> STA2_W<10> { + pub fn sta2(&mut self) -> STA2_W { STA2_W::new(self) } #[doc = "Bit 11 - Channel 3 state"] #[inline(always)] #[must_use] - pub fn sta3(&mut self) -> STA3_W<11> { + pub fn sta3(&mut self) -> STA3_W { STA3_W::new(self) } #[doc = "Bit 12 - Channel 4 state"] #[inline(always)] #[must_use] - pub fn sta4(&mut self) -> STA4_W<12> { + pub fn sta4(&mut self) -> STA4_W { STA4_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sta](index.html) module"] +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STA_SPEC; impl crate::RegisterSpec for STA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sta::R](R) reader structure"] -impl crate::Readable for STA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sta::W](W) writer structure"] +#[doc = "`read()` method returns [`sta::R`](R) reader structure"] +impl crate::Readable for STA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sta::W`](W) writer structure"] impl crate::Writable for STA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/spi0.rs b/crates/bcm2835-lpa/src/spi0.rs index 88737df..66be9b6 100644 --- a/crates/bcm2835-lpa/src/spi0.rs +++ b/crates/bcm2835-lpa/src/spi0.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control and Status"] pub cs: CS, @@ -14,27 +15,33 @@ pub struct RegisterBlock { #[doc = "0x14 - "] pub dc: DC, } -#[doc = "CS (rw) register accessor: an alias for `Reg`"] +#[doc = "CS (rw) register accessor: Control and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cs`] +module"] pub type CS = crate::Reg; #[doc = "Control and Status"] pub mod cs; -#[doc = "FIFO (rw) register accessor: an alias for `Reg`"] +#[doc = "FIFO (rw) register accessor: FIFO access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`] +module"] pub type FIFO = crate::Reg; #[doc = "FIFO access"] pub mod fifo; -#[doc = "CLK (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK (rw) register accessor: Clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk`] +module"] pub type CLK = crate::Reg; #[doc = "Clock divider"] pub mod clk; -#[doc = "DLEN (rw) register accessor: an alias for `Reg`"] +#[doc = "DLEN (rw) register accessor: Data length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlen`] +module"] pub type DLEN = crate::Reg; #[doc = "Data length"] pub mod dlen; -#[doc = "LTOH (rw) register accessor: an alias for `Reg`"] +#[doc = "LTOH (rw) register accessor: LoSSI output hold delay\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ltoh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ltoh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ltoh`] +module"] pub type LTOH = crate::Reg; #[doc = "LoSSI output hold delay"] pub mod ltoh; -#[doc = "DC (rw) register accessor: an alias for `Reg`"] +#[doc = "DC (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc`] +module"] pub type DC = crate::Reg; #[doc = ""] pub mod dc; diff --git a/crates/bcm2835-lpa/src/spi0/clk.rs b/crates/bcm2835-lpa/src/spi0/clk.rs index ef3272e..54ce877 100644 --- a/crates/bcm2835-lpa/src/spi0/clk.rs +++ b/crates/bcm2835-lpa/src/spi0/clk.rs @@ -1,43 +1,11 @@ #[doc = "Register `CLK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CDIV` reader - Clock divider"] -pub type CDIV_R = crate::FieldReader; +pub type CDIV_R = crate::FieldReader; #[doc = "Field `CDIV` writer - Clock divider"] -pub type CDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_SPEC, u16, u16, 16, O>; +pub type CDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Clock divider"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { CDIV_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK") + .field("cdiv", &format_args!("{}", self.cdiv().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Clock divider"] #[inline(always)] #[must_use] - pub fn cdiv(&mut self) -> CDIV_W<0> { + pub fn cdiv(&mut self) -> CDIV_W { CDIV_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk](index.html) module"] +#[doc = "Clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_SPEC; impl crate::RegisterSpec for CLK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk::R](R) reader structure"] -impl crate::Readable for CLK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk::W](W) writer structure"] +#[doc = "`read()` method returns [`clk::R`](R) reader structure"] +impl crate::Readable for CLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk::W`](W) writer structure"] impl crate::Writable for CLK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/spi0/cs.rs b/crates/bcm2835-lpa/src/spi0/cs.rs index 50227aa..06511e6 100644 --- a/crates/bcm2835-lpa/src/spi0/cs.rs +++ b/crates/bcm2835-lpa/src/spi0/cs.rs @@ -1,53 +1,21 @@ #[doc = "Register `CS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CS` reader - Chip select"] -pub type CS_R = crate::FieldReader; +pub type CS_R = crate::FieldReader; #[doc = "Field `CS` writer - Chip select"] -pub type CS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, u8, 2, O>; +pub type CS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `CPHA` reader - Clock phase"] -pub type CPHA_R = crate::BitReader; +pub type CPHA_R = crate::BitReader; #[doc = "Field `CPHA` writer - Clock phase"] -pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CPHA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPOL` reader - Clock polarity"] -pub type CPOL_R = crate::BitReader; +pub type CPOL_R = crate::BitReader; #[doc = "Field `CPOL` writer - Clock polarity"] -pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLEAR` reader - Clear the FIFO(s)"] -pub type CLEAR_R = crate::FieldReader; +pub type CLEAR_R = crate::FieldReader; #[doc = "Clear the FIFO(s)\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -65,10 +33,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for CLEAR_A { + type Ux = u8; +} impl CLEAR_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 1 => Some(CLEAR_A::TX), 2 => Some(CLEAR_A::RX), @@ -76,111 +47,115 @@ impl CLEAR_R { _ => None, } } - #[doc = "Checks if the value of the field is `TX`"] + #[doc = "`1`"] #[inline(always)] pub fn is_tx(&self) -> bool { *self == CLEAR_A::TX } - #[doc = "Checks if the value of the field is `RX`"] + #[doc = "`10`"] #[inline(always)] pub fn is_rx(&self) -> bool { *self == CLEAR_A::RX } - #[doc = "Checks if the value of the field is `BOTH`"] + #[doc = "`11`"] #[inline(always)] pub fn is_both(&self) -> bool { *self == CLEAR_A::BOTH } } #[doc = "Field `CLEAR` writer - Clear the FIFO(s)"] -pub type CLEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, CLEAR_A, 2, O>; -impl<'a, const O: u8> CLEAR_W<'a, O> { +pub type CLEAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, CLEAR_A>; +impl<'a, REG, const O: u8> CLEAR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1`"] #[inline(always)] - pub fn tx(self) -> &'a mut W { + pub fn tx(self) -> &'a mut crate::W { self.variant(CLEAR_A::TX) } #[doc = "`10`"] #[inline(always)] - pub fn rx(self) -> &'a mut W { + pub fn rx(self) -> &'a mut crate::W { self.variant(CLEAR_A::RX) } #[doc = "`11`"] #[inline(always)] - pub fn both(self) -> &'a mut W { + pub fn both(self) -> &'a mut crate::W { self.variant(CLEAR_A::BOTH) } } #[doc = "Field `CSPOL` reader - Chip select polarity"] -pub type CSPOL_R = crate::BitReader; +pub type CSPOL_R = crate::BitReader; #[doc = "Field `CSPOL` writer - Chip select polarity"] -pub type CSPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CSPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TA` reader - Transfer active"] -pub type TA_R = crate::BitReader; +pub type TA_R = crate::BitReader; #[doc = "Field `TA` writer - Transfer active"] -pub type TA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type TA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMAEN` reader - Enable DMA"] -pub type DMAEN_R = crate::BitReader; +pub type DMAEN_R = crate::BitReader; #[doc = "Field `DMAEN` writer - Enable DMA"] -pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type DMAEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTD` reader - Interrupt on done"] -pub type INTD_R = crate::BitReader; +pub type INTD_R = crate::BitReader; #[doc = "Field `INTD` writer - Interrupt on done"] -pub type INTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type INTD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTR` reader - Interrupt on RX"] -pub type INTR_R = crate::BitReader; +pub type INTR_R = crate::BitReader; #[doc = "Field `INTR` writer - Interrupt on RX"] -pub type INTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type INTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ADCS` reader - Automatically deassert chip select"] -pub type ADCS_R = crate::BitReader; +pub type ADCS_R = crate::BitReader; #[doc = "Field `ADCS` writer - Automatically deassert chip select"] -pub type ADCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type ADCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN` reader - Read enable"] -pub type REN_R = crate::BitReader; +pub type REN_R = crate::BitReader; #[doc = "Field `REN` writer - Read enable"] -pub type REN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type REN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN` reader - LoSSI enable"] -pub type LEN_R = crate::BitReader; +pub type LEN_R = crate::BitReader; #[doc = "Field `LEN` writer - LoSSI enable"] -pub type LEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type LEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LMONO` reader - "] -pub type LMONO_R = crate::BitReader; +pub type LMONO_R = crate::BitReader; #[doc = "Field `LMONO` writer - "] -pub type LMONO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type LMONO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TE_EN` reader - "] -pub type TE_EN_R = crate::BitReader; +pub type TE_EN_R = crate::BitReader; #[doc = "Field `TE_EN` writer - "] -pub type TE_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type TE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DONE` reader - Transfer is done"] -pub type DONE_R = crate::BitReader; +pub type DONE_R = crate::BitReader; #[doc = "Field `RXD` reader - RX FIFO contains data"] -pub type RXD_R = crate::BitReader; +pub type RXD_R = crate::BitReader; #[doc = "Field `TXD` reader - TX FIFO can accept data"] -pub type TXD_R = crate::BitReader; +pub type TXD_R = crate::BitReader; #[doc = "Field `RXR` reader - RX FIFO has data to be read"] -pub type RXR_R = crate::BitReader; +pub type RXR_R = crate::BitReader; #[doc = "Field `RXF` reader - RX FIFO full"] -pub type RXF_R = crate::BitReader; +pub type RXF_R = crate::BitReader; #[doc = "Field `CSPOL0` reader - Chip select 0 polarity"] -pub type CSPOL0_R = crate::BitReader; +pub type CSPOL0_R = crate::BitReader; #[doc = "Field `CSPOL0` writer - Chip select 0 polarity"] -pub type CSPOL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CSPOL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSPOL1` reader - Chip select 1 polarity"] -pub type CSPOL1_R = crate::BitReader; +pub type CSPOL1_R = crate::BitReader; #[doc = "Field `CSPOL1` writer - Chip select 1 polarity"] -pub type CSPOL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CSPOL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSPOL2` reader - Chip select 2 polarity"] -pub type CSPOL2_R = crate::BitReader; +pub type CSPOL2_R = crate::BitReader; #[doc = "Field `CSPOL2` writer - Chip select 2 polarity"] -pub type CSPOL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CSPOL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_LEN` reader - Enable DMA in LoSSI mode"] -pub type DMA_LEN_R = crate::BitReader; +pub type DMA_LEN_R = crate::BitReader; #[doc = "Field `DMA_LEN` writer - Enable DMA in LoSSI mode"] -pub type DMA_LEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type DMA_LEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN_LONG` reader - Enable long data word in LoSSI mode"] -pub type LEN_LONG_R = crate::BitReader; +pub type LEN_LONG_R = crate::BitReader; #[doc = "Field `LEN_LONG` writer - Enable long data word in LoSSI mode"] -pub type LEN_LONG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type LEN_LONG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:1 - Chip select"] #[inline(always)] @@ -303,140 +278,176 @@ impl R { LEN_LONG_R::new(((self.bits >> 25) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CS") + .field("len_long", &format_args!("{}", self.len_long().bit())) + .field("dma_len", &format_args!("{}", self.dma_len().bit())) + .field("cspol2", &format_args!("{}", self.cspol2().bit())) + .field("cspol1", &format_args!("{}", self.cspol1().bit())) + .field("cspol0", &format_args!("{}", self.cspol0().bit())) + .field("rxf", &format_args!("{}", self.rxf().bit())) + .field("rxr", &format_args!("{}", self.rxr().bit())) + .field("txd", &format_args!("{}", self.txd().bit())) + .field("rxd", &format_args!("{}", self.rxd().bit())) + .field("done", &format_args!("{}", self.done().bit())) + .field("te_en", &format_args!("{}", self.te_en().bit())) + .field("lmono", &format_args!("{}", self.lmono().bit())) + .field("len", &format_args!("{}", self.len().bit())) + .field("ren", &format_args!("{}", self.ren().bit())) + .field("adcs", &format_args!("{}", self.adcs().bit())) + .field("intr", &format_args!("{}", self.intr().bit())) + .field("intd", &format_args!("{}", self.intd().bit())) + .field("dmaen", &format_args!("{}", self.dmaen().bit())) + .field("ta", &format_args!("{}", self.ta().bit())) + .field("cspol", &format_args!("{}", self.cspol().bit())) + .field("clear", &format_args!("{}", self.clear().bits())) + .field("cpol", &format_args!("{}", self.cpol().bit())) + .field("cpha", &format_args!("{}", self.cpha().bit())) + .field("cs", &format_args!("{}", self.cs().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Chip select"] #[inline(always)] #[must_use] - pub fn cs(&mut self) -> CS_W<0> { + pub fn cs(&mut self) -> CS_W { CS_W::new(self) } #[doc = "Bit 2 - Clock phase"] #[inline(always)] #[must_use] - pub fn cpha(&mut self) -> CPHA_W<2> { + pub fn cpha(&mut self) -> CPHA_W { CPHA_W::new(self) } #[doc = "Bit 3 - Clock polarity"] #[inline(always)] #[must_use] - pub fn cpol(&mut self) -> CPOL_W<3> { + pub fn cpol(&mut self) -> CPOL_W { CPOL_W::new(self) } #[doc = "Bits 4:5 - Clear the FIFO(s)"] #[inline(always)] #[must_use] - pub fn clear(&mut self) -> CLEAR_W<4> { + pub fn clear(&mut self) -> CLEAR_W { CLEAR_W::new(self) } #[doc = "Bit 6 - Chip select polarity"] #[inline(always)] #[must_use] - pub fn cspol(&mut self) -> CSPOL_W<6> { + pub fn cspol(&mut self) -> CSPOL_W { CSPOL_W::new(self) } #[doc = "Bit 7 - Transfer active"] #[inline(always)] #[must_use] - pub fn ta(&mut self) -> TA_W<7> { + pub fn ta(&mut self) -> TA_W { TA_W::new(self) } #[doc = "Bit 8 - Enable DMA"] #[inline(always)] #[must_use] - pub fn dmaen(&mut self) -> DMAEN_W<8> { + pub fn dmaen(&mut self) -> DMAEN_W { DMAEN_W::new(self) } #[doc = "Bit 9 - Interrupt on done"] #[inline(always)] #[must_use] - pub fn intd(&mut self) -> INTD_W<9> { + pub fn intd(&mut self) -> INTD_W { INTD_W::new(self) } #[doc = "Bit 10 - Interrupt on RX"] #[inline(always)] #[must_use] - pub fn intr(&mut self) -> INTR_W<10> { + pub fn intr(&mut self) -> INTR_W { INTR_W::new(self) } #[doc = "Bit 11 - Automatically deassert chip select"] #[inline(always)] #[must_use] - pub fn adcs(&mut self) -> ADCS_W<11> { + pub fn adcs(&mut self) -> ADCS_W { ADCS_W::new(self) } #[doc = "Bit 12 - Read enable"] #[inline(always)] #[must_use] - pub fn ren(&mut self) -> REN_W<12> { + pub fn ren(&mut self) -> REN_W { REN_W::new(self) } #[doc = "Bit 13 - LoSSI enable"] #[inline(always)] #[must_use] - pub fn len(&mut self) -> LEN_W<13> { + pub fn len(&mut self) -> LEN_W { LEN_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn lmono(&mut self) -> LMONO_W<14> { + pub fn lmono(&mut self) -> LMONO_W { LMONO_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn te_en(&mut self) -> TE_EN_W<15> { + pub fn te_en(&mut self) -> TE_EN_W { TE_EN_W::new(self) } #[doc = "Bit 21 - Chip select 0 polarity"] #[inline(always)] #[must_use] - pub fn cspol0(&mut self) -> CSPOL0_W<21> { + pub fn cspol0(&mut self) -> CSPOL0_W { CSPOL0_W::new(self) } #[doc = "Bit 22 - Chip select 1 polarity"] #[inline(always)] #[must_use] - pub fn cspol1(&mut self) -> CSPOL1_W<22> { + pub fn cspol1(&mut self) -> CSPOL1_W { CSPOL1_W::new(self) } #[doc = "Bit 23 - Chip select 2 polarity"] #[inline(always)] #[must_use] - pub fn cspol2(&mut self) -> CSPOL2_W<23> { + pub fn cspol2(&mut self) -> CSPOL2_W { CSPOL2_W::new(self) } #[doc = "Bit 24 - Enable DMA in LoSSI mode"] #[inline(always)] #[must_use] - pub fn dma_len(&mut self) -> DMA_LEN_W<24> { + pub fn dma_len(&mut self) -> DMA_LEN_W { DMA_LEN_W::new(self) } #[doc = "Bit 25 - Enable long data word in LoSSI mode"] #[inline(always)] #[must_use] - pub fn len_long(&mut self) -> LEN_LONG_W<25> { + pub fn len_long(&mut self) -> LEN_LONG_W { LEN_LONG_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control and Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +#[doc = "Control and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CS_SPEC; impl crate::RegisterSpec for CS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cs::R](R) reader structure"] -impl crate::Readable for CS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/spi0/dc.rs b/crates/bcm2835-lpa/src/spi0/dc.rs index 281dd71..23813da 100644 --- a/crates/bcm2835-lpa/src/spi0/dc.rs +++ b/crates/bcm2835-lpa/src/spi0/dc.rs @@ -1,55 +1,23 @@ #[doc = "Register `DC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TDREQ` reader - DMA Write request threshold"] -pub type TDREQ_R = crate::FieldReader; +pub type TDREQ_R = crate::FieldReader; #[doc = "Field `TDREQ` writer - DMA Write request threshold"] -pub type TDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +pub type TDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `TPANIC` reader - DMA write panic threshold"] -pub type TPANIC_R = crate::FieldReader; +pub type TPANIC_R = crate::FieldReader; #[doc = "Field `TPANIC` writer - DMA write panic threshold"] -pub type TPANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +pub type TPANIC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `RDREQ` reader - DMA read request threshold"] -pub type RDREQ_R = crate::FieldReader; +pub type RDREQ_R = crate::FieldReader; #[doc = "Field `RDREQ` writer - DMA read request threshold"] -pub type RDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +pub type RDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `RPANIC` reader - DMA read panic threshold"] -pub type RPANIC_R = crate::FieldReader; +pub type RPANIC_R = crate::FieldReader; #[doc = "Field `RPANIC` writer - DMA read panic threshold"] -pub type RPANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +pub type RPANIC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - DMA Write request threshold"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { RPANIC_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DC") + .field("rpanic", &format_args!("{}", self.rpanic().bits())) + .field("rdreq", &format_args!("{}", self.rdreq().bits())) + .field("tpanic", &format_args!("{}", self.tpanic().bits())) + .field("tdreq", &format_args!("{}", self.tdreq().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DMA Write request threshold"] #[inline(always)] #[must_use] - pub fn tdreq(&mut self) -> TDREQ_W<0> { + pub fn tdreq(&mut self) -> TDREQ_W { TDREQ_W::new(self) } #[doc = "Bits 8:15 - DMA write panic threshold"] #[inline(always)] #[must_use] - pub fn tpanic(&mut self) -> TPANIC_W<8> { + pub fn tpanic(&mut self) -> TPANIC_W { TPANIC_W::new(self) } #[doc = "Bits 16:23 - DMA read request threshold"] #[inline(always)] #[must_use] - pub fn rdreq(&mut self) -> RDREQ_W<16> { + pub fn rdreq(&mut self) -> RDREQ_W { RDREQ_W::new(self) } #[doc = "Bits 24:31 - DMA read panic threshold"] #[inline(always)] #[must_use] - pub fn rpanic(&mut self) -> RPANIC_W<24> { + pub fn rpanic(&mut self) -> RPANIC_W { RPANIC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dc](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DC_SPEC; impl crate::RegisterSpec for DC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dc::R](R) reader structure"] -impl crate::Readable for DC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dc::W](W) writer structure"] +#[doc = "`read()` method returns [`dc::R`](R) reader structure"] +impl crate::Readable for DC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dc::W`](W) writer structure"] impl crate::Writable for DC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/spi0/dlen.rs b/crates/bcm2835-lpa/src/spi0/dlen.rs index 25e2771..5c7bb83 100644 --- a/crates/bcm2835-lpa/src/spi0/dlen.rs +++ b/crates/bcm2835-lpa/src/spi0/dlen.rs @@ -1,43 +1,11 @@ #[doc = "Register `DLEN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DLEN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DLEN` reader - Data length"] -pub type DLEN_R = crate::FieldReader; +pub type DLEN_R = crate::FieldReader; #[doc = "Field `DLEN` writer - Data length"] -pub type DLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLEN_SPEC, u16, u16, 16, O>; +pub type DLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Data length"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DLEN_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DLEN") + .field("dlen", &format_args!("{}", self.dlen().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Data length"] #[inline(always)] #[must_use] - pub fn dlen(&mut self) -> DLEN_W<0> { + pub fn dlen(&mut self) -> DLEN_W { DLEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlen](index.html) module"] +#[doc = "Data length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DLEN_SPEC; impl crate::RegisterSpec for DLEN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dlen::R](R) reader structure"] -impl crate::Readable for DLEN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dlen::W](W) writer structure"] +#[doc = "`read()` method returns [`dlen::R`](R) reader structure"] +impl crate::Readable for DLEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dlen::W`](W) writer structure"] impl crate::Writable for DLEN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/spi0/fifo.rs b/crates/bcm2835-lpa/src/spi0/fifo.rs index 46d2ece..937c27b 100644 --- a/crates/bcm2835-lpa/src/spi0/fifo.rs +++ b/crates/bcm2835-lpa/src/spi0/fifo.rs @@ -1,43 +1,11 @@ #[doc = "Register `FIFO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FIFO` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - Data"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - Data"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u32, u32, 32, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Data"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - Data"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "FIFO access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"] +#[doc = "FIFO access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_SPEC; impl crate::RegisterSpec for FIFO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fifo::R](R) reader structure"] -impl crate::Readable for FIFO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"] +#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] +impl crate::Readable for FIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"] impl crate::Writable for FIFO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/spi0/ltoh.rs b/crates/bcm2835-lpa/src/spi0/ltoh.rs index 5d0ab3f..15d66d8 100644 --- a/crates/bcm2835-lpa/src/spi0/ltoh.rs +++ b/crates/bcm2835-lpa/src/spi0/ltoh.rs @@ -1,43 +1,11 @@ #[doc = "Register `LTOH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LTOH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TOH` reader - Output hold delay"] -pub type TOH_R = crate::FieldReader; +pub type TOH_R = crate::FieldReader; #[doc = "Field `TOH` writer - Output hold delay"] -pub type TOH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LTOH_SPEC, u8, u8, 4, O>; +pub type TOH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - Output hold delay"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { TOH_R::new((self.bits & 0x0f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LTOH") + .field("toh", &format_args!("{}", self.toh().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:3 - Output hold delay"] #[inline(always)] #[must_use] - pub fn toh(&mut self) -> TOH_W<0> { + pub fn toh(&mut self) -> TOH_W { TOH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LoSSI output hold delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ltoh](index.html) module"] +#[doc = "LoSSI output hold delay\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ltoh::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ltoh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LTOH_SPEC; impl crate::RegisterSpec for LTOH_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ltoh::R](R) reader structure"] -impl crate::Readable for LTOH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ltoh::W](W) writer structure"] +#[doc = "`read()` method returns [`ltoh::R`](R) reader structure"] +impl crate::Readable for LTOH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ltoh::W`](W) writer structure"] impl crate::Writable for LTOH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/spi1.rs b/crates/bcm2835-lpa/src/spi1.rs index 1547fcc..0031aa9 100644 --- a/crates/bcm2835-lpa/src/spi1.rs +++ b/crates/bcm2835-lpa/src/spi1.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control 0"] pub cntl0: CNTL0, @@ -14,27 +15,33 @@ pub struct RegisterBlock { #[doc = "0x20..0x30 - Writing to the FIFO will maintain CS at the end of the access"] pub txhold: [TXHOLD; 4], } -#[doc = "CNTL0 (rw) register accessor: an alias for `Reg`"] +#[doc = "CNTL0 (rw) register accessor: Control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntl0`] +module"] pub type CNTL0 = crate::Reg; #[doc = "Control 0"] pub mod cntl0; -#[doc = "CNTL1 (rw) register accessor: an alias for `Reg`"] +#[doc = "CNTL1 (rw) register accessor: Control 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntl1`] +module"] pub type CNTL1 = crate::Reg; #[doc = "Control 1"] pub mod cntl1; -#[doc = "STAT (rw) register accessor: an alias for `Reg`"] +#[doc = "STAT (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] +module"] pub type STAT = crate::Reg; #[doc = "Status"] pub mod stat; -#[doc = "PEEK (r) register accessor: an alias for `Reg`"] +#[doc = "PEEK (r) register accessor: Read the RXFIFO without removing an entry\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peek`] +module"] pub type PEEK = crate::Reg; #[doc = "Read the RXFIFO without removing an entry"] pub mod peek; -#[doc = "IO (rw) register accessor: an alias for `Reg`"] +#[doc = "IO (rw) register accessor: Writing to the FIFO will deassert CS at the end of the access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io`] +module"] pub type IO = crate::Reg; #[doc = "Writing to the FIFO will deassert CS at the end of the access"] pub mod io; -#[doc = "TXHOLD (rw) register accessor: an alias for `Reg`"] +#[doc = "TXHOLD (rw) register accessor: Writing to the FIFO will maintain CS at the end of the access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txhold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txhold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txhold`] +module"] pub type TXHOLD = crate::Reg; #[doc = "Writing to the FIFO will maintain CS at the end of the access"] pub mod txhold; diff --git a/crates/bcm2835-lpa/src/spi1/cntl0.rs b/crates/bcm2835-lpa/src/spi1/cntl0.rs index b9354b5..df7d957 100644 --- a/crates/bcm2835-lpa/src/spi1/cntl0.rs +++ b/crates/bcm2835-lpa/src/spi1/cntl0.rs @@ -1,69 +1,37 @@ #[doc = "Register `CNTL0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CNTL0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SHIFT_LENGTH` reader - Number of bits to shift"] -pub type SHIFT_LENGTH_R = crate::FieldReader; +pub type SHIFT_LENGTH_R = crate::FieldReader; #[doc = "Field `SHIFT_LENGTH` writer - Number of bits to shift"] -pub type SHIFT_LENGTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u8, u8, 6, O>; +pub type SHIFT_LENGTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `MSB_FIRST` reader - Shift out the most significant bit (MSB) first"] -pub type MSB_FIRST_R = crate::BitReader; +pub type MSB_FIRST_R = crate::BitReader; #[doc = "Field `MSB_FIRST` writer - Shift out the most significant bit (MSB) first"] -pub type MSB_FIRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type MSB_FIRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INVERT_CLK` reader - Idle clock high"] -pub type INVERT_CLK_R = crate::BitReader; +pub type INVERT_CLK_R = crate::BitReader; #[doc = "Field `INVERT_CLK` writer - Idle clock high"] -pub type INVERT_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type INVERT_CLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OUT_RISING` reader - Data is clocked out on rising edge of CLK"] -pub type OUT_RISING_R = crate::BitReader; +pub type OUT_RISING_R = crate::BitReader; #[doc = "Field `OUT_RISING` writer - Data is clocked out on rising edge of CLK"] -pub type OUT_RISING_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type OUT_RISING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLEAR_FIFOS` reader - Clear FIFOs"] -pub type CLEAR_FIFOS_R = crate::BitReader; +pub type CLEAR_FIFOS_R = crate::BitReader; #[doc = "Field `CLEAR_FIFOS` writer - Clear FIFOs"] -pub type CLEAR_FIFOS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type CLEAR_FIFOS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IN_RISING` reader - Data is clocked in on rising edge of CLK"] -pub type IN_RISING_R = crate::BitReader; +pub type IN_RISING_R = crate::BitReader; #[doc = "Field `IN_RISING` writer - Data is clocked in on rising edge of CLK"] -pub type IN_RISING_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type IN_RISING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - Enable the interface"] -pub type ENABLE_R = crate::BitReader; +pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Enable the interface"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOUT_HOLD_TIME` reader - Controls extra DOUT hold time in system clock cycles"] -pub type DOUT_HOLD_TIME_R = crate::FieldReader; +pub type DOUT_HOLD_TIME_R = crate::FieldReader; #[doc = "Controls extra DOUT hold time in system clock cycles\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -83,10 +51,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for DOUT_HOLD_TIME_A { + type Ux = u8; +} impl DOUT_HOLD_TIME_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DOUT_HOLD_TIME_A { + pub const fn variant(&self) -> DOUT_HOLD_TIME_A { match self.bits { 0 => DOUT_HOLD_TIME_A::_0, 1 => DOUT_HOLD_TIME_A::_1, @@ -95,72 +66,76 @@ impl DOUT_HOLD_TIME_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_0`"] + #[doc = "`0`"] #[inline(always)] pub fn is_0(&self) -> bool { *self == DOUT_HOLD_TIME_A::_0 } - #[doc = "Checks if the value of the field is `_1`"] + #[doc = "`1`"] #[inline(always)] pub fn is_1(&self) -> bool { *self == DOUT_HOLD_TIME_A::_1 } - #[doc = "Checks if the value of the field is `_4`"] + #[doc = "`10`"] #[inline(always)] pub fn is_4(&self) -> bool { *self == DOUT_HOLD_TIME_A::_4 } - #[doc = "Checks if the value of the field is `_7`"] + #[doc = "`11`"] #[inline(always)] pub fn is_7(&self) -> bool { *self == DOUT_HOLD_TIME_A::_7 } } #[doc = "Field `DOUT_HOLD_TIME` writer - Controls extra DOUT hold time in system clock cycles"] -pub type DOUT_HOLD_TIME_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, CNTL0_SPEC, u8, DOUT_HOLD_TIME_A, 2, O>; -impl<'a, const O: u8> DOUT_HOLD_TIME_W<'a, O> { +pub type DOUT_HOLD_TIME_W<'a, REG, const O: u8> = + crate::FieldWriterSafe<'a, REG, 2, O, DOUT_HOLD_TIME_A>; +impl<'a, REG, const O: u8> DOUT_HOLD_TIME_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _0(self) -> &'a mut W { + pub fn _0(self) -> &'a mut crate::W { self.variant(DOUT_HOLD_TIME_A::_0) } #[doc = "`1`"] #[inline(always)] - pub fn _1(self) -> &'a mut W { + pub fn _1(self) -> &'a mut crate::W { self.variant(DOUT_HOLD_TIME_A::_1) } #[doc = "`10`"] #[inline(always)] - pub fn _4(self) -> &'a mut W { + pub fn _4(self) -> &'a mut crate::W { self.variant(DOUT_HOLD_TIME_A::_4) } #[doc = "`11`"] #[inline(always)] - pub fn _7(self) -> &'a mut W { + pub fn _7(self) -> &'a mut crate::W { self.variant(DOUT_HOLD_TIME_A::_7) } } #[doc = "Field `VARIABLE_WIDTH` reader - Take shift length and data from FIFO"] -pub type VARIABLE_WIDTH_R = crate::BitReader; +pub type VARIABLE_WIDTH_R = crate::BitReader; #[doc = "Field `VARIABLE_WIDTH` writer - Take shift length and data from FIFO"] -pub type VARIABLE_WIDTH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type VARIABLE_WIDTH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VARIABLE_CS` reader - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] -pub type VARIABLE_CS_R = crate::BitReader; +pub type VARIABLE_CS_R = crate::BitReader; #[doc = "Field `VARIABLE_CS` writer - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] -pub type VARIABLE_CS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type VARIABLE_CS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POST_INPUT` reader - Post input mode"] -pub type POST_INPUT_R = crate::BitReader; +pub type POST_INPUT_R = crate::BitReader; #[doc = "Field `POST_INPUT` writer - Post input mode"] -pub type POST_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type POST_INPUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHIP_SELECTS` reader - The CS pattern when active"] -pub type CHIP_SELECTS_R = crate::FieldReader; +pub type CHIP_SELECTS_R = crate::FieldReader; #[doc = "Field `CHIP_SELECTS` writer - The CS pattern when active"] -pub type CHIP_SELECTS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u8, u8, 3, O>; +pub type CHIP_SELECTS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `SPEED` reader - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] -pub type SPEED_R = crate::FieldReader; +pub type SPEED_R = crate::FieldReader; #[doc = "Field `SPEED` writer - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] -pub type SPEED_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u16, u16, 12, O>; +pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; impl R { #[doc = "Bits 0:5 - Number of bits to shift"] #[inline(always)] @@ -228,104 +203,141 @@ impl R { SPEED_R::new(((self.bits >> 20) & 0x0fff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CNTL0") + .field("speed", &format_args!("{}", self.speed().bits())) + .field( + "chip_selects", + &format_args!("{}", self.chip_selects().bits()), + ) + .field("post_input", &format_args!("{}", self.post_input().bit())) + .field("variable_cs", &format_args!("{}", self.variable_cs().bit())) + .field( + "variable_width", + &format_args!("{}", self.variable_width().bit()), + ) + .field( + "dout_hold_time", + &format_args!("{}", self.dout_hold_time().bits()), + ) + .field("enable", &format_args!("{}", self.enable().bit())) + .field("in_rising", &format_args!("{}", self.in_rising().bit())) + .field("clear_fifos", &format_args!("{}", self.clear_fifos().bit())) + .field("out_rising", &format_args!("{}", self.out_rising().bit())) + .field("invert_clk", &format_args!("{}", self.invert_clk().bit())) + .field("msb_first", &format_args!("{}", self.msb_first().bit())) + .field( + "shift_length", + &format_args!("{}", self.shift_length().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5 - Number of bits to shift"] #[inline(always)] #[must_use] - pub fn shift_length(&mut self) -> SHIFT_LENGTH_W<0> { + pub fn shift_length(&mut self) -> SHIFT_LENGTH_W { SHIFT_LENGTH_W::new(self) } #[doc = "Bit 6 - Shift out the most significant bit (MSB) first"] #[inline(always)] #[must_use] - pub fn msb_first(&mut self) -> MSB_FIRST_W<6> { + pub fn msb_first(&mut self) -> MSB_FIRST_W { MSB_FIRST_W::new(self) } #[doc = "Bit 7 - Idle clock high"] #[inline(always)] #[must_use] - pub fn invert_clk(&mut self) -> INVERT_CLK_W<7> { + pub fn invert_clk(&mut self) -> INVERT_CLK_W { INVERT_CLK_W::new(self) } #[doc = "Bit 8 - Data is clocked out on rising edge of CLK"] #[inline(always)] #[must_use] - pub fn out_rising(&mut self) -> OUT_RISING_W<8> { + pub fn out_rising(&mut self) -> OUT_RISING_W { OUT_RISING_W::new(self) } #[doc = "Bit 9 - Clear FIFOs"] #[inline(always)] #[must_use] - pub fn clear_fifos(&mut self) -> CLEAR_FIFOS_W<9> { + pub fn clear_fifos(&mut self) -> CLEAR_FIFOS_W { CLEAR_FIFOS_W::new(self) } #[doc = "Bit 10 - Data is clocked in on rising edge of CLK"] #[inline(always)] #[must_use] - pub fn in_rising(&mut self) -> IN_RISING_W<10> { + pub fn in_rising(&mut self) -> IN_RISING_W { IN_RISING_W::new(self) } #[doc = "Bit 11 - Enable the interface"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<11> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bits 12:13 - Controls extra DOUT hold time in system clock cycles"] #[inline(always)] #[must_use] - pub fn dout_hold_time(&mut self) -> DOUT_HOLD_TIME_W<12> { + pub fn dout_hold_time(&mut self) -> DOUT_HOLD_TIME_W { DOUT_HOLD_TIME_W::new(self) } #[doc = "Bit 14 - Take shift length and data from FIFO"] #[inline(always)] #[must_use] - pub fn variable_width(&mut self) -> VARIABLE_WIDTH_W<14> { + pub fn variable_width(&mut self) -> VARIABLE_WIDTH_W { VARIABLE_WIDTH_W::new(self) } #[doc = "Bit 15 - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] #[inline(always)] #[must_use] - pub fn variable_cs(&mut self) -> VARIABLE_CS_W<15> { + pub fn variable_cs(&mut self) -> VARIABLE_CS_W { VARIABLE_CS_W::new(self) } #[doc = "Bit 16 - Post input mode"] #[inline(always)] #[must_use] - pub fn post_input(&mut self) -> POST_INPUT_W<16> { + pub fn post_input(&mut self) -> POST_INPUT_W { POST_INPUT_W::new(self) } #[doc = "Bits 17:19 - The CS pattern when active"] #[inline(always)] #[must_use] - pub fn chip_selects(&mut self) -> CHIP_SELECTS_W<17> { + pub fn chip_selects(&mut self) -> CHIP_SELECTS_W { CHIP_SELECTS_W::new(self) } #[doc = "Bits 20:31 - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W<20> { + pub fn speed(&mut self) -> SPEED_W { SPEED_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl0](index.html) module"] +#[doc = "Control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CNTL0_SPEC; impl crate::RegisterSpec for CNTL0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cntl0::R](R) reader structure"] -impl crate::Readable for CNTL0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cntl0::W](W) writer structure"] +#[doc = "`read()` method returns [`cntl0::R`](R) reader structure"] +impl crate::Readable for CNTL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cntl0::W`](W) writer structure"] impl crate::Writable for CNTL0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/spi1/cntl1.rs b/crates/bcm2835-lpa/src/spi1/cntl1.rs index c7d627b..c1f0228 100644 --- a/crates/bcm2835-lpa/src/spi1/cntl1.rs +++ b/crates/bcm2835-lpa/src/spi1/cntl1.rs @@ -1,59 +1,27 @@ #[doc = "Register `CNTL1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CNTL1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `KEEP_INPUT` reader - Don't clear the RX shift register before a new transaction"] -pub type KEEP_INPUT_R = crate::BitReader; +pub type KEEP_INPUT_R = crate::BitReader; #[doc = "Field `KEEP_INPUT` writer - Don't clear the RX shift register before a new transaction"] -pub type KEEP_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +pub type KEEP_INPUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSB_FIRST` reader - Shift the most significant bit first (MSB)"] -pub type MSB_FIRST_R = crate::BitReader; +pub type MSB_FIRST_R = crate::BitReader; #[doc = "Field `MSB_FIRST` writer - Shift the most significant bit first (MSB)"] -pub type MSB_FIRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +pub type MSB_FIRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DONE_ENABLE` reader - Enable DONE interrupt"] -pub type DONE_ENABLE_R = crate::BitReader; +pub type DONE_ENABLE_R = crate::BitReader; #[doc = "Field `DONE_ENABLE` writer - Enable DONE interrupt"] -pub type DONE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +pub type DONE_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXE_ENABLE` reader - Enable TX empty interrupt"] -pub type TXE_ENABLE_R = crate::BitReader; +pub type TXE_ENABLE_R = crate::BitReader; #[doc = "Field `TXE_ENABLE` writer - Enable TX empty interrupt"] -pub type TXE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +pub type TXE_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CS_HIGH_TIME` reader - Additional SPI clock cycles where CS is high"] -pub type CS_HIGH_TIME_R = crate::FieldReader; +pub type CS_HIGH_TIME_R = crate::FieldReader; #[doc = "Field `CS_HIGH_TIME` writer - Additional SPI clock cycles where CS is high"] -pub type CS_HIGH_TIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL1_SPEC, u8, u8, 3, O>; +pub type CS_HIGH_TIME_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bit 0 - Don't clear the RX shift register before a new transaction"] #[inline(always)] @@ -81,56 +49,76 @@ impl R { CS_HIGH_TIME_R::new(((self.bits >> 8) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CNTL1") + .field( + "cs_high_time", + &format_args!("{}", self.cs_high_time().bits()), + ) + .field("txe_enable", &format_args!("{}", self.txe_enable().bit())) + .field("done_enable", &format_args!("{}", self.done_enable().bit())) + .field("msb_first", &format_args!("{}", self.msb_first().bit())) + .field("keep_input", &format_args!("{}", self.keep_input().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Don't clear the RX shift register before a new transaction"] #[inline(always)] #[must_use] - pub fn keep_input(&mut self) -> KEEP_INPUT_W<0> { + pub fn keep_input(&mut self) -> KEEP_INPUT_W { KEEP_INPUT_W::new(self) } #[doc = "Bit 1 - Shift the most significant bit first (MSB)"] #[inline(always)] #[must_use] - pub fn msb_first(&mut self) -> MSB_FIRST_W<1> { + pub fn msb_first(&mut self) -> MSB_FIRST_W { MSB_FIRST_W::new(self) } #[doc = "Bit 6 - Enable DONE interrupt"] #[inline(always)] #[must_use] - pub fn done_enable(&mut self) -> DONE_ENABLE_W<6> { + pub fn done_enable(&mut self) -> DONE_ENABLE_W { DONE_ENABLE_W::new(self) } #[doc = "Bit 7 - Enable TX empty interrupt"] #[inline(always)] #[must_use] - pub fn txe_enable(&mut self) -> TXE_ENABLE_W<7> { + pub fn txe_enable(&mut self) -> TXE_ENABLE_W { TXE_ENABLE_W::new(self) } #[doc = "Bits 8:10 - Additional SPI clock cycles where CS is high"] #[inline(always)] #[must_use] - pub fn cs_high_time(&mut self) -> CS_HIGH_TIME_W<8> { + pub fn cs_high_time(&mut self) -> CS_HIGH_TIME_W { CS_HIGH_TIME_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl1](index.html) module"] +#[doc = "Control 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CNTL1_SPEC; impl crate::RegisterSpec for CNTL1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cntl1::R](R) reader structure"] -impl crate::Readable for CNTL1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cntl1::W](W) writer structure"] +#[doc = "`read()` method returns [`cntl1::R`](R) reader structure"] +impl crate::Readable for CNTL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cntl1::W`](W) writer structure"] impl crate::Writable for CNTL1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/spi1/io.rs b/crates/bcm2835-lpa/src/spi1/io.rs index 365004d..6564875 100644 --- a/crates/bcm2835-lpa/src/spi1/io.rs +++ b/crates/bcm2835-lpa/src/spi1/io.rs @@ -1,43 +1,11 @@ #[doc = "Register `IO%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IO%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - FIFO data access"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - FIFO data access"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO_SPEC, u16, u16, 16, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IO") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Writing to the FIFO will deassert CS at the end of the access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](index.html) module"] +#[doc = "Writing to the FIFO will deassert CS at the end of the access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IO_SPEC; impl crate::RegisterSpec for IO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [io::R](R) reader structure"] -impl crate::Readable for IO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [io::W](W) writer structure"] +#[doc = "`read()` method returns [`io::R`](R) reader structure"] +impl crate::Readable for IO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`io::W`](W) writer structure"] impl crate::Writable for IO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/spi1/peek.rs b/crates/bcm2835-lpa/src/spi1/peek.rs index b4a7333..7ceeb4a 100644 --- a/crates/bcm2835-lpa/src/spi1/peek.rs +++ b/crates/bcm2835-lpa/src/spi1/peek.rs @@ -1,20 +1,7 @@ #[doc = "Register `PEEK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DATA` reader - FIFO data access"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] @@ -22,15 +9,25 @@ impl R { DATA_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Read the RXFIFO without removing an entry\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PEEK") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Read the RXFIFO without removing an entry\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEEK_SPEC; impl crate::RegisterSpec for PEEK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [peek::R](R) reader structure"] -impl crate::Readable for PEEK_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`peek::R`](R) reader structure"] +impl crate::Readable for PEEK_SPEC {} #[doc = "`reset()` method sets PEEK to value 0"] impl crate::Resettable for PEEK_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/spi1/stat.rs b/crates/bcm2835-lpa/src/spi1/stat.rs index 0dd56f6..9fe3977 100644 --- a/crates/bcm2835-lpa/src/spi1/stat.rs +++ b/crates/bcm2835-lpa/src/spi1/stat.rs @@ -1,71 +1,39 @@ #[doc = "Register `STAT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STAT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BIT_COUNT` reader - Number of bits left to be processed."] -pub type BIT_COUNT_R = crate::FieldReader; +pub type BIT_COUNT_R = crate::FieldReader; #[doc = "Field `BIT_COUNT` writer - Number of bits left to be processed."] -pub type BIT_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 6, O>; +pub type BIT_COUNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `BUSY` reader - Indicates a transfer is ongoing"] -pub type BUSY_R = crate::BitReader; +pub type BUSY_R = crate::BitReader; #[doc = "Field `BUSY` writer - Indicates a transfer is ongoing"] -pub type BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type BUSY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_EMPTY` reader - RX FIFO is empty"] -pub type RX_EMPTY_R = crate::BitReader; +pub type RX_EMPTY_R = crate::BitReader; #[doc = "Field `RX_EMPTY` writer - RX FIFO is empty"] -pub type RX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_FULL` reader - RX FIFO is full"] -pub type RX_FULL_R = crate::BitReader; +pub type RX_FULL_R = crate::BitReader; #[doc = "Field `RX_FULL` writer - RX FIFO is full"] -pub type RX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_EMPTY` reader - TX FIFO is empty"] -pub type TX_EMPTY_R = crate::BitReader; +pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `TX_EMPTY` writer - TX FIFO is empty"] -pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_FULL` reader - TX FIFO is full"] -pub type TX_FULL_R = crate::BitReader; +pub type TX_FULL_R = crate::BitReader; #[doc = "Field `TX_FULL` writer - TX FIFO is full"] -pub type TX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_LEVEL` reader - Number of entries in RX FIFO"] -pub type RX_LEVEL_R = crate::FieldReader; +pub type RX_LEVEL_R = crate::FieldReader; #[doc = "Field `RX_LEVEL` writer - Number of entries in RX FIFO"] -pub type RX_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +pub type RX_LEVEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TX_LEVEL` reader - Number of entries in TX FIFO"] -pub type TX_LEVEL_R = crate::FieldReader; +pub type TX_LEVEL_R = crate::FieldReader; #[doc = "Field `TX_LEVEL` writer - Number of entries in TX FIFO"] -pub type TX_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +pub type TX_LEVEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:5 - Number of bits left to be processed."] #[inline(always)] @@ -108,74 +76,94 @@ impl R { TX_LEVEL_R::new(((self.bits >> 24) & 0x0f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STAT") + .field("tx_level", &format_args!("{}", self.tx_level().bits())) + .field("rx_level", &format_args!("{}", self.rx_level().bits())) + .field("tx_full", &format_args!("{}", self.tx_full().bit())) + .field("tx_empty", &format_args!("{}", self.tx_empty().bit())) + .field("rx_full", &format_args!("{}", self.rx_full().bit())) + .field("rx_empty", &format_args!("{}", self.rx_empty().bit())) + .field("busy", &format_args!("{}", self.busy().bit())) + .field("bit_count", &format_args!("{}", self.bit_count().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5 - Number of bits left to be processed."] #[inline(always)] #[must_use] - pub fn bit_count(&mut self) -> BIT_COUNT_W<0> { + pub fn bit_count(&mut self) -> BIT_COUNT_W { BIT_COUNT_W::new(self) } #[doc = "Bit 6 - Indicates a transfer is ongoing"] #[inline(always)] #[must_use] - pub fn busy(&mut self) -> BUSY_W<6> { + pub fn busy(&mut self) -> BUSY_W { BUSY_W::new(self) } #[doc = "Bit 7 - RX FIFO is empty"] #[inline(always)] #[must_use] - pub fn rx_empty(&mut self) -> RX_EMPTY_W<7> { + pub fn rx_empty(&mut self) -> RX_EMPTY_W { RX_EMPTY_W::new(self) } #[doc = "Bit 8 - RX FIFO is full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W<8> { + pub fn rx_full(&mut self) -> RX_FULL_W { RX_FULL_W::new(self) } #[doc = "Bit 9 - TX FIFO is empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W<9> { + pub fn tx_empty(&mut self) -> TX_EMPTY_W { TX_EMPTY_W::new(self) } #[doc = "Bit 10 - TX FIFO is full"] #[inline(always)] #[must_use] - pub fn tx_full(&mut self) -> TX_FULL_W<10> { + pub fn tx_full(&mut self) -> TX_FULL_W { TX_FULL_W::new(self) } #[doc = "Bits 16:19 - Number of entries in RX FIFO"] #[inline(always)] #[must_use] - pub fn rx_level(&mut self) -> RX_LEVEL_W<16> { + pub fn rx_level(&mut self) -> RX_LEVEL_W { RX_LEVEL_W::new(self) } #[doc = "Bits 24:27 - Number of entries in TX FIFO"] #[inline(always)] #[must_use] - pub fn tx_level(&mut self) -> TX_LEVEL_W<24> { + pub fn tx_level(&mut self) -> TX_LEVEL_W { TX_LEVEL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"] +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STAT_SPEC; impl crate::RegisterSpec for STAT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [stat::R](R) reader structure"] -impl crate::Readable for STAT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"] +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] impl crate::Writable for STAT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/spi1/txhold.rs b/crates/bcm2835-lpa/src/spi1/txhold.rs index a2ca31b..8c29938 100644 --- a/crates/bcm2835-lpa/src/spi1/txhold.rs +++ b/crates/bcm2835-lpa/src/spi1/txhold.rs @@ -1,43 +1,11 @@ #[doc = "Register `TXHOLD%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TXHOLD%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - FIFO data access"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - FIFO data access"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXHOLD_SPEC, u16, u16, 16, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TXHOLD") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Writing to the FIFO will maintain CS at the end of the access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txhold](index.html) module"] +#[doc = "Writing to the FIFO will maintain CS at the end of the access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txhold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txhold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXHOLD_SPEC; impl crate::RegisterSpec for TXHOLD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txhold::R](R) reader structure"] -impl crate::Readable for TXHOLD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [txhold::W](W) writer structure"] +#[doc = "`read()` method returns [`txhold::R`](R) reader structure"] +impl crate::Readable for TXHOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txhold::W`](W) writer structure"] impl crate::Writable for TXHOLD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/systmr.rs b/crates/bcm2835-lpa/src/systmr.rs index 859ea09..31647d3 100644 --- a/crates/bcm2835-lpa/src/systmr.rs +++ b/crates/bcm2835-lpa/src/systmr.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control / Status"] pub cs: CS, @@ -16,31 +17,38 @@ pub struct RegisterBlock { #[doc = "0x18 - Compare channel 3"] pub c3: C3, } -#[doc = "CS (rw) register accessor: an alias for `Reg`"] +#[doc = "CS (rw) register accessor: Control / Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cs`] +module"] pub type CS = crate::Reg; #[doc = "Control / Status"] pub mod cs; -#[doc = "CLO (r) register accessor: an alias for `Reg`"] +#[doc = "CLO (r) register accessor: Lower 32 bits for the free running counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clo`] +module"] pub type CLO = crate::Reg; #[doc = "Lower 32 bits for the free running counter"] pub mod clo; -#[doc = "CHI (r) register accessor: an alias for `Reg`"] +#[doc = "CHI (r) register accessor: Higher 32 bits for the free running counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chi`] +module"] pub type CHI = crate::Reg; #[doc = "Higher 32 bits for the free running counter"] pub mod chi; -#[doc = "C0 (rw) register accessor: an alias for `Reg`"] +#[doc = "C0 (rw) register accessor: Compare channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c0`] +module"] pub type C0 = crate::Reg; #[doc = "Compare channel 0"] pub mod c0; -#[doc = "C1 (rw) register accessor: an alias for `Reg`"] +#[doc = "C1 (rw) register accessor: Compare channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c1`] +module"] pub type C1 = crate::Reg; #[doc = "Compare channel 1"] pub mod c1; -#[doc = "C2 (rw) register accessor: an alias for `Reg`"] +#[doc = "C2 (rw) register accessor: Compare channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c2`] +module"] pub type C2 = crate::Reg; #[doc = "Compare channel 2"] pub mod c2; -#[doc = "C3 (rw) register accessor: an alias for `Reg`"] +#[doc = "C3 (rw) register accessor: Compare channel 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c3`] +module"] pub type C3 = crate::Reg; #[doc = "Compare channel 3"] pub mod c3; diff --git a/crates/bcm2835-lpa/src/systmr/c0.rs b/crates/bcm2835-lpa/src/systmr/c0.rs index 20b09d2..18be8a7 100644 --- a/crates/bcm2835-lpa/src/systmr/c0.rs +++ b/crates/bcm2835-lpa/src/systmr/c0.rs @@ -1,59 +1,38 @@ #[doc = "Register `C0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Compare channel 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c0](index.html) module"] +#[doc = "Compare channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C0_SPEC; impl crate::RegisterSpec for C0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c0::R](R) reader structure"] -impl crate::Readable for C0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c0::W](W) writer structure"] +#[doc = "`read()` method returns [`c0::R`](R) reader structure"] +impl crate::Readable for C0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c0::W`](W) writer structure"] impl crate::Writable for C0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/systmr/c1.rs b/crates/bcm2835-lpa/src/systmr/c1.rs index 87cf5ed..bcf565c 100644 --- a/crates/bcm2835-lpa/src/systmr/c1.rs +++ b/crates/bcm2835-lpa/src/systmr/c1.rs @@ -1,59 +1,38 @@ #[doc = "Register `C1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Compare channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c1](index.html) module"] +#[doc = "Compare channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C1_SPEC; impl crate::RegisterSpec for C1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c1::R](R) reader structure"] -impl crate::Readable for C1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c1::W](W) writer structure"] +#[doc = "`read()` method returns [`c1::R`](R) reader structure"] +impl crate::Readable for C1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c1::W`](W) writer structure"] impl crate::Writable for C1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/systmr/c2.rs b/crates/bcm2835-lpa/src/systmr/c2.rs index 8c9c84b..e91e152 100644 --- a/crates/bcm2835-lpa/src/systmr/c2.rs +++ b/crates/bcm2835-lpa/src/systmr/c2.rs @@ -1,59 +1,38 @@ #[doc = "Register `C2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Compare channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c2](index.html) module"] +#[doc = "Compare channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C2_SPEC; impl crate::RegisterSpec for C2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c2::R](R) reader structure"] -impl crate::Readable for C2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c2::W](W) writer structure"] +#[doc = "`read()` method returns [`c2::R`](R) reader structure"] +impl crate::Readable for C2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c2::W`](W) writer structure"] impl crate::Writable for C2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/systmr/c3.rs b/crates/bcm2835-lpa/src/systmr/c3.rs index 0ac0aa2..a33918f 100644 --- a/crates/bcm2835-lpa/src/systmr/c3.rs +++ b/crates/bcm2835-lpa/src/systmr/c3.rs @@ -1,59 +1,38 @@ #[doc = "Register `C3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Compare channel 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c3](index.html) module"] +#[doc = "Compare channel 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C3_SPEC; impl crate::RegisterSpec for C3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c3::R](R) reader structure"] -impl crate::Readable for C3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c3::W](W) writer structure"] +#[doc = "`read()` method returns [`c3::R`](R) reader structure"] +impl crate::Readable for C3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c3::W`](W) writer structure"] impl crate::Writable for C3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/systmr/chi.rs b/crates/bcm2835-lpa/src/systmr/chi.rs index 9f162ef..7313db2 100644 --- a/crates/bcm2835-lpa/src/systmr/chi.rs +++ b/crates/bcm2835-lpa/src/systmr/chi.rs @@ -1,27 +1,22 @@ #[doc = "Register `CHI` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } -#[doc = "Higher 32 bits for the free running counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chi](index.html) module"] +#[doc = "Higher 32 bits for the free running counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CHI_SPEC; impl crate::RegisterSpec for CHI_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [chi::R](R) reader structure"] -impl crate::Readable for CHI_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`chi::R`](R) reader structure"] +impl crate::Readable for CHI_SPEC {} #[doc = "`reset()` method sets CHI to value 0"] impl crate::Resettable for CHI_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/systmr/clo.rs b/crates/bcm2835-lpa/src/systmr/clo.rs index 0a4b01f..43986b1 100644 --- a/crates/bcm2835-lpa/src/systmr/clo.rs +++ b/crates/bcm2835-lpa/src/systmr/clo.rs @@ -1,27 +1,22 @@ #[doc = "Register `CLO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } -#[doc = "Lower 32 bits for the free running counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clo](index.html) module"] +#[doc = "Lower 32 bits for the free running counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLO_SPEC; impl crate::RegisterSpec for CLO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clo::R](R) reader structure"] -impl crate::Readable for CLO_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clo::R`](R) reader structure"] +impl crate::Readable for CLO_SPEC {} #[doc = "`reset()` method sets CLO to value 0"] impl crate::Resettable for CLO_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/systmr/cs.rs b/crates/bcm2835-lpa/src/systmr/cs.rs index dcb8ec2..3e1660d 100644 --- a/crates/bcm2835-lpa/src/systmr/cs.rs +++ b/crates/bcm2835-lpa/src/systmr/cs.rs @@ -1,55 +1,23 @@ #[doc = "Register `CS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `M0` reader - System timer match 0"] -pub type M0_R = crate::BitReader; +pub type M0_R = crate::BitReader; #[doc = "Field `M0` writer - System timer match 0"] -pub type M0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +pub type M0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `M1` reader - System timer match 1"] -pub type M1_R = crate::BitReader; +pub type M1_R = crate::BitReader; #[doc = "Field `M1` writer - System timer match 1"] -pub type M1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +pub type M1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `M2` reader - System timer match 2"] -pub type M2_R = crate::BitReader; +pub type M2_R = crate::BitReader; #[doc = "Field `M2` writer - System timer match 2"] -pub type M2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +pub type M2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `M3` reader - System timer match 3"] -pub type M3_R = crate::BitReader; +pub type M3_R = crate::BitReader; #[doc = "Field `M3` writer - System timer match 3"] -pub type M3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +pub type M3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - System timer match 0"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { M3_R::new(((self.bits >> 3) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CS") + .field("m3", &format_args!("{}", self.m3().bit())) + .field("m2", &format_args!("{}", self.m2().bit())) + .field("m1", &format_args!("{}", self.m1().bit())) + .field("m0", &format_args!("{}", self.m0().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - System timer match 0"] #[inline(always)] #[must_use] - pub fn m0(&mut self) -> M0_W<0> { + pub fn m0(&mut self) -> M0_W { M0_W::new(self) } #[doc = "Bit 1 - System timer match 1"] #[inline(always)] #[must_use] - pub fn m1(&mut self) -> M1_W<1> { + pub fn m1(&mut self) -> M1_W { M1_W::new(self) } #[doc = "Bit 2 - System timer match 2"] #[inline(always)] #[must_use] - pub fn m2(&mut self) -> M2_W<2> { + pub fn m2(&mut self) -> M2_W { M2_W::new(self) } #[doc = "Bit 3 - System timer match 3"] #[inline(always)] #[must_use] - pub fn m3(&mut self) -> M3_W<3> { + pub fn m3(&mut self) -> M3_W { M3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control / Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +#[doc = "Control / Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CS_SPEC; impl crate::RegisterSpec for CS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cs::R](R) reader structure"] -impl crate::Readable for CS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0f; } diff --git a/crates/bcm2835-lpa/src/uart0.rs b/crates/bcm2835-lpa/src/uart0.rs index aade8a9..a12a501 100644 --- a/crates/bcm2835-lpa/src/uart0.rs +++ b/crates/bcm2835-lpa/src/uart0.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Data Register"] pub dr: DR, @@ -41,59 +42,73 @@ impl RegisterBlock { unsafe { &*(self as *const Self).cast::().add(4usize).cast() } } } -#[doc = "DR (rw) register accessor: an alias for `Reg`"] +#[doc = "DR (rw) register accessor: Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`] +module"] pub type DR = crate::Reg; #[doc = "Data Register"] pub mod dr; -#[doc = "RSR (r) register accessor: an alias for `Reg`"] +#[doc = "RSR (r) register accessor: Receive Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsr`] +module"] pub type RSR = crate::Reg; #[doc = "Receive Status Register"] pub mod rsr; -#[doc = "ECR (w) register accessor: an alias for `Reg`"] +#[doc = "ECR (w) register accessor: Error Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr`] +module"] pub type ECR = crate::Reg; #[doc = "Error Clear Register"] pub mod ecr; -#[doc = "FR (rw) register accessor: an alias for `Reg`"] +#[doc = "FR (rw) register accessor: Flag Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fr`] +module"] pub type FR = crate::Reg; #[doc = "Flag Register"] pub mod fr; -#[doc = "IBRD (rw) register accessor: an alias for `Reg`"] +#[doc = "IBRD (rw) register accessor: Integer Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibrd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibrd`] +module"] pub type IBRD = crate::Reg; #[doc = "Integer Baud Rate Register"] pub mod ibrd; -#[doc = "FBRD (rw) register accessor: an alias for `Reg`"] +#[doc = "FBRD (rw) register accessor: Fractional Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fbrd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fbrd`] +module"] pub type FBRD = crate::Reg; #[doc = "Fractional Baud Rate Register"] pub mod fbrd; -#[doc = "LCR_H (rw) register accessor: an alias for `Reg`"] +#[doc = "LCR_H (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr_h::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr_h::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr_h`] +module"] pub type LCR_H = crate::Reg; #[doc = "Line Control Register"] pub mod lcr_h; -#[doc = "CR (rw) register accessor: an alias for `Reg`"] +#[doc = "CR (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "IFLS (rw) register accessor: an alias for `Reg`"] +#[doc = "IFLS (rw) register accessor: Interrupt FIFO Level Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifls::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifls::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ifls`] +module"] pub type IFLS = crate::Reg; #[doc = "Interrupt FIFO Level Select Register"] pub mod ifls; -#[doc = "IMSC (rw) register accessor: an alias for `Reg`"] +#[doc = "IMSC (rw) register accessor: Interrupt Mask set_Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imsc`] +module"] pub type IMSC = crate::Reg; #[doc = "Interrupt Mask set_Clear Register"] pub mod imsc; -#[doc = "RIS (r) register accessor: an alias for `Reg`"] +#[doc = "RIS (r) register accessor: Raw Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`] +module"] pub type RIS = crate::Reg; #[doc = "Raw Interrupt Status Register"] pub mod ris; -#[doc = "MIS (r) register accessor: an alias for `Reg`"] +#[doc = "MIS (r) register accessor: Masked Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`] +module"] pub type MIS = crate::Reg; #[doc = "Masked Interrupt Status Register"] pub mod mis; -#[doc = "ICR (w) register accessor: an alias for `Reg`"] +#[doc = "ICR (w) register accessor: Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`] +module"] pub type ICR = crate::Reg; #[doc = "Interrupt Clear Register"] pub mod icr; -#[doc = "DMACR (rw) register accessor: an alias for `Reg`"] +#[doc = "DMACR (rw) register accessor: DMA Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmacr`] +module"] pub type DMACR = crate::Reg; #[doc = "DMA Control Register"] pub mod dmacr; diff --git a/crates/bcm2835-lpa/src/uart0/cr.rs b/crates/bcm2835-lpa/src/uart0/cr.rs index 6c47a00..bfbc283 100644 --- a/crates/bcm2835-lpa/src/uart0/cr.rs +++ b/crates/bcm2835-lpa/src/uart0/cr.rs @@ -1,75 +1,43 @@ #[doc = "Register `CR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UARTEN` reader - UARTEN"] -pub type UARTEN_R = crate::BitReader; +pub type UARTEN_R = crate::BitReader; #[doc = "Field `UARTEN` writer - UARTEN"] -pub type UARTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type UARTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SIREN` reader - SIREN"] -pub type SIREN_R = crate::BitReader; +pub type SIREN_R = crate::BitReader; #[doc = "Field `SIREN` writer - SIREN"] -pub type SIREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type SIREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SIRLP` reader - SIRLP"] -pub type SIRLP_R = crate::BitReader; +pub type SIRLP_R = crate::BitReader; #[doc = "Field `SIRLP` writer - SIRLP"] -pub type SIRLP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type SIRLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXE` reader - TXE"] -pub type TXE_R = crate::BitReader; +pub type TXE_R = crate::BitReader; #[doc = "Field `TXE` writer - TXE"] -pub type TXE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type TXE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXE` reader - RXE"] -pub type RXE_R = crate::BitReader; +pub type RXE_R = crate::BitReader; #[doc = "Field `RXE` writer - RXE"] -pub type RXE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type RXE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTR` reader - DTR"] -pub type DTR_R = crate::BitReader; +pub type DTR_R = crate::BitReader; #[doc = "Field `DTR` writer - DTR"] -pub type DTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTS` reader - RTS"] -pub type RTS_R = crate::BitReader; +pub type RTS_R = crate::BitReader; #[doc = "Field `RTS` writer - RTS"] -pub type RTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTSEN` reader - RTSEN"] -pub type RTSEN_R = crate::BitReader; +pub type RTSEN_R = crate::BitReader; #[doc = "Field `RTSEN` writer - RTSEN"] -pub type RTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type RTSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTSEN` reader - CTSEN"] -pub type CTSEN_R = crate::BitReader; +pub type CTSEN_R = crate::BitReader; #[doc = "Field `CTSEN` writer - CTSEN"] -pub type CTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type CTSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - UARTEN"] #[inline(always)] @@ -117,80 +85,101 @@ impl R { CTSEN_R::new(((self.bits >> 15) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CR") + .field("uarten", &format_args!("{}", self.uarten().bit())) + .field("siren", &format_args!("{}", self.siren().bit())) + .field("sirlp", &format_args!("{}", self.sirlp().bit())) + .field("txe", &format_args!("{}", self.txe().bit())) + .field("rxe", &format_args!("{}", self.rxe().bit())) + .field("dtr", &format_args!("{}", self.dtr().bit())) + .field("rts", &format_args!("{}", self.rts().bit())) + .field("rtsen", &format_args!("{}", self.rtsen().bit())) + .field("ctsen", &format_args!("{}", self.ctsen().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - UARTEN"] #[inline(always)] #[must_use] - pub fn uarten(&mut self) -> UARTEN_W<0> { + pub fn uarten(&mut self) -> UARTEN_W { UARTEN_W::new(self) } #[doc = "Bit 1 - SIREN"] #[inline(always)] #[must_use] - pub fn siren(&mut self) -> SIREN_W<1> { + pub fn siren(&mut self) -> SIREN_W { SIREN_W::new(self) } #[doc = "Bit 2 - SIRLP"] #[inline(always)] #[must_use] - pub fn sirlp(&mut self) -> SIRLP_W<2> { + pub fn sirlp(&mut self) -> SIRLP_W { SIRLP_W::new(self) } #[doc = "Bit 8 - TXE"] #[inline(always)] #[must_use] - pub fn txe(&mut self) -> TXE_W<8> { + pub fn txe(&mut self) -> TXE_W { TXE_W::new(self) } #[doc = "Bit 9 - RXE"] #[inline(always)] #[must_use] - pub fn rxe(&mut self) -> RXE_W<9> { + pub fn rxe(&mut self) -> RXE_W { RXE_W::new(self) } #[doc = "Bit 10 - DTR"] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W<10> { + pub fn dtr(&mut self) -> DTR_W { DTR_W::new(self) } #[doc = "Bit 11 - RTS"] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W<11> { + pub fn rts(&mut self) -> RTS_W { RTS_W::new(self) } #[doc = "Bit 14 - RTSEN"] #[inline(always)] #[must_use] - pub fn rtsen(&mut self) -> RTSEN_W<14> { + pub fn rtsen(&mut self) -> RTSEN_W { RTSEN_W::new(self) } #[doc = "Bit 15 - CTSEN"] #[inline(always)] #[must_use] - pub fn ctsen(&mut self) -> CTSEN_W<15> { + pub fn ctsen(&mut self) -> CTSEN_W { CTSEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cr::R](R) reader structure"] -impl crate::Readable for CR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`read()` method returns [`cr::R`](R) reader structure"] +impl crate::Readable for CR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart0/dmacr.rs b/crates/bcm2835-lpa/src/uart0/dmacr.rs index 8bd3632..40efa50 100644 --- a/crates/bcm2835-lpa/src/uart0/dmacr.rs +++ b/crates/bcm2835-lpa/src/uart0/dmacr.rs @@ -1,51 +1,19 @@ #[doc = "Register `DMACR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMACR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXDMAE` reader - RXDMAE"] -pub type RXDMAE_R = crate::BitReader; +pub type RXDMAE_R = crate::BitReader; #[doc = "Field `RXDMAE` writer - RXDMAE"] -pub type RXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXDMAE` reader - TXDMAE"] -pub type TXDMAE_R = crate::BitReader; +pub type TXDMAE_R = crate::BitReader; #[doc = "Field `TXDMAE` writer - TXDMAE"] -pub type TXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMAONERR` reader - DMAONERR"] -pub type DMAONERR_R = crate::BitReader; +pub type DMAONERR_R = crate::BitReader; #[doc = "Field `DMAONERR` writer - DMAONERR"] -pub type DMAONERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +pub type DMAONERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - RXDMAE"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { DMAONERR_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMACR") + .field("rxdmae", &format_args!("{}", self.rxdmae().bit())) + .field("txdmae", &format_args!("{}", self.txdmae().bit())) + .field("dmaonerr", &format_args!("{}", self.dmaonerr().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - RXDMAE"] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W<0> { + pub fn rxdmae(&mut self) -> RXDMAE_W { RXDMAE_W::new(self) } #[doc = "Bit 1 - TXDMAE"] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W<1> { + pub fn txdmae(&mut self) -> TXDMAE_W { TXDMAE_W::new(self) } #[doc = "Bit 2 - DMAONERR"] #[inline(always)] #[must_use] - pub fn dmaonerr(&mut self) -> DMAONERR_W<2> { + pub fn dmaonerr(&mut self) -> DMAONERR_W { DMAONERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacr](index.html) module"] +#[doc = "DMA Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMACR_SPEC; impl crate::RegisterSpec for DMACR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dmacr::R](R) reader structure"] -impl crate::Readable for DMACR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dmacr::W](W) writer structure"] +#[doc = "`read()` method returns [`dmacr::R`](R) reader structure"] +impl crate::Readable for DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dmacr::W`](W) writer structure"] impl crate::Writable for DMACR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart0/dr.rs b/crates/bcm2835-lpa/src/uart0/dr.rs index 236d30b..3c7f81e 100644 --- a/crates/bcm2835-lpa/src/uart0/dr.rs +++ b/crates/bcm2835-lpa/src/uart0/dr.rs @@ -1,59 +1,27 @@ #[doc = "Register `DR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - DATA"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - DATA"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DR_SPEC, u8, u8, 8, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `FE` reader - FE"] -pub type FE_R = crate::BitReader; +pub type FE_R = crate::BitReader; #[doc = "Field `FE` writer - FE"] -pub type FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +pub type FE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PE` reader - PE"] -pub type PE_R = crate::BitReader; +pub type PE_R = crate::BitReader; #[doc = "Field `PE` writer - PE"] -pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +pub type PE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BE` reader - BE"] -pub type BE_R = crate::BitReader; +pub type BE_R = crate::BitReader; #[doc = "Field `BE` writer - BE"] -pub type BE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +pub type BE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OE` reader - OE"] -pub type OE_R = crate::BitReader; +pub type OE_R = crate::BitReader; #[doc = "Field `OE` writer - OE"] -pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +pub type OE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:7 - DATA"] #[inline(always)] @@ -81,56 +49,73 @@ impl R { OE_R::new(((self.bits >> 11) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DR") + .field("data", &format_args!("{}", self.data().bits())) + .field("fe", &format_args!("{}", self.fe().bit())) + .field("pe", &format_args!("{}", self.pe().bit())) + .field("be", &format_args!("{}", self.be().bit())) + .field("oe", &format_args!("{}", self.oe().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DATA"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } #[doc = "Bit 8 - FE"] #[inline(always)] #[must_use] - pub fn fe(&mut self) -> FE_W<8> { + pub fn fe(&mut self) -> FE_W { FE_W::new(self) } #[doc = "Bit 9 - PE"] #[inline(always)] #[must_use] - pub fn pe(&mut self) -> PE_W<9> { + pub fn pe(&mut self) -> PE_W { PE_W::new(self) } #[doc = "Bit 10 - BE"] #[inline(always)] #[must_use] - pub fn be(&mut self) -> BE_W<10> { + pub fn be(&mut self) -> BE_W { BE_W::new(self) } #[doc = "Bit 11 - OE"] #[inline(always)] #[must_use] - pub fn oe(&mut self) -> OE_W<11> { + pub fn oe(&mut self) -> OE_W { OE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"] +#[doc = "Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DR_SPEC; impl crate::RegisterSpec for DR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dr::R](R) reader structure"] -impl crate::Readable for DR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"] +#[doc = "`read()` method returns [`dr::R`](R) reader structure"] +impl crate::Readable for DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"] impl crate::Writable for DR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart0/ecr.rs b/crates/bcm2835-lpa/src/uart0/ecr.rs index f469e97..97efb0b 100644 --- a/crates/bcm2835-lpa/src/uart0/ecr.rs +++ b/crates/bcm2835-lpa/src/uart0/ecr.rs @@ -1,72 +1,61 @@ #[doc = "Register `ECR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FE` writer - FE"] -pub type FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +pub type FE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PE` writer - PE"] -pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +pub type PE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BE` writer - BE"] -pub type BE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +pub type BE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OE` writer - OE"] -pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +pub type OE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - FE"] #[inline(always)] #[must_use] - pub fn fe(&mut self) -> FE_W<0> { + pub fn fe(&mut self) -> FE_W { FE_W::new(self) } #[doc = "Bit 1 - PE"] #[inline(always)] #[must_use] - pub fn pe(&mut self) -> PE_W<1> { + pub fn pe(&mut self) -> PE_W { PE_W::new(self) } #[doc = "Bit 2 - BE"] #[inline(always)] #[must_use] - pub fn be(&mut self) -> BE_W<2> { + pub fn be(&mut self) -> BE_W { BE_W::new(self) } #[doc = "Bit 3 - OE"] #[inline(always)] #[must_use] - pub fn oe(&mut self) -> OE_W<3> { + pub fn oe(&mut self) -> OE_W { OE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Error Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecr](index.html) module"] +#[doc = "Error Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ECR_SPEC; impl crate::RegisterSpec for ECR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ecr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ecr::W`](W) writer structure"] impl crate::Writable for ECR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart0/fbrd.rs b/crates/bcm2835-lpa/src/uart0/fbrd.rs index 14ae9a3..e0fe228 100644 --- a/crates/bcm2835-lpa/src/uart0/fbrd.rs +++ b/crates/bcm2835-lpa/src/uart0/fbrd.rs @@ -1,43 +1,11 @@ #[doc = "Register `FBRD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FBRD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BAUDDIVFRAC` reader - BAUDDIVFRAC"] -pub type BAUDDIVFRAC_R = crate::FieldReader; +pub type BAUDDIVFRAC_R = crate::FieldReader; #[doc = "Field `BAUDDIVFRAC` writer - BAUDDIVFRAC"] -pub type BAUDDIVFRAC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FBRD_SPEC, u8, u8, 6, O>; +pub type BAUDDIVFRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5 - BAUDDIVFRAC"] #[inline(always)] @@ -45,32 +13,48 @@ impl R { BAUDDIVFRAC_R::new((self.bits & 0x3f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FBRD") + .field( + "bauddivfrac", + &format_args!("{}", self.bauddivfrac().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5 - BAUDDIVFRAC"] #[inline(always)] #[must_use] - pub fn bauddivfrac(&mut self) -> BAUDDIVFRAC_W<0> { + pub fn bauddivfrac(&mut self) -> BAUDDIVFRAC_W { BAUDDIVFRAC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Fractional Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fbrd](index.html) module"] +#[doc = "Fractional Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fbrd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FBRD_SPEC; impl crate::RegisterSpec for FBRD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fbrd::R](R) reader structure"] -impl crate::Readable for FBRD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fbrd::W](W) writer structure"] +#[doc = "`read()` method returns [`fbrd::R`](R) reader structure"] +impl crate::Readable for FBRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fbrd::W`](W) writer structure"] impl crate::Writable for FBRD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart0/fr.rs b/crates/bcm2835-lpa/src/uart0/fr.rs index 641becc..d70703c 100644 --- a/crates/bcm2835-lpa/src/uart0/fr.rs +++ b/crates/bcm2835-lpa/src/uart0/fr.rs @@ -1,75 +1,43 @@ #[doc = "Register `FR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CTS` reader - CTS"] -pub type CTS_R = crate::BitReader; +pub type CTS_R = crate::BitReader; #[doc = "Field `CTS` writer - CTS"] -pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type CTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSR` reader - DSR"] -pub type DSR_R = crate::BitReader; +pub type DSR_R = crate::BitReader; #[doc = "Field `DSR` writer - DSR"] -pub type DSR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type DSR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCD` reader - DCD"] -pub type DCD_R = crate::BitReader; +pub type DCD_R = crate::BitReader; #[doc = "Field `DCD` writer - DCD"] -pub type DCD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type DCD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUSY` reader - BUSY"] -pub type BUSY_R = crate::BitReader; +pub type BUSY_R = crate::BitReader; #[doc = "Field `BUSY` writer - BUSY"] -pub type BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type BUSY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFE` reader - RXFE"] -pub type RXFE_R = crate::BitReader; +pub type RXFE_R = crate::BitReader; #[doc = "Field `RXFE` writer - RXFE"] -pub type RXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type RXFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFF` reader - TXFF"] -pub type TXFF_R = crate::BitReader; +pub type TXFF_R = crate::BitReader; #[doc = "Field `TXFF` writer - TXFF"] -pub type TXFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type TXFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFF` reader - RXFF"] -pub type RXFF_R = crate::BitReader; +pub type RXFF_R = crate::BitReader; #[doc = "Field `RXFF` writer - RXFF"] -pub type RXFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type RXFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFE` reader - TXFE"] -pub type TXFE_R = crate::BitReader; +pub type TXFE_R = crate::BitReader; #[doc = "Field `TXFE` writer - TXFE"] -pub type TXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type TXFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RI` reader - RI"] -pub type RI_R = crate::BitReader; +pub type RI_R = crate::BitReader; #[doc = "Field `RI` writer - RI"] -pub type RI_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type RI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - CTS"] #[inline(always)] @@ -117,80 +85,101 @@ impl R { RI_R::new(((self.bits >> 8) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FR") + .field("cts", &format_args!("{}", self.cts().bit())) + .field("dsr", &format_args!("{}", self.dsr().bit())) + .field("dcd", &format_args!("{}", self.dcd().bit())) + .field("busy", &format_args!("{}", self.busy().bit())) + .field("rxfe", &format_args!("{}", self.rxfe().bit())) + .field("txff", &format_args!("{}", self.txff().bit())) + .field("rxff", &format_args!("{}", self.rxff().bit())) + .field("txfe", &format_args!("{}", self.txfe().bit())) + .field("ri", &format_args!("{}", self.ri().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - CTS"] #[inline(always)] #[must_use] - pub fn cts(&mut self) -> CTS_W<0> { + pub fn cts(&mut self) -> CTS_W { CTS_W::new(self) } #[doc = "Bit 1 - DSR"] #[inline(always)] #[must_use] - pub fn dsr(&mut self) -> DSR_W<1> { + pub fn dsr(&mut self) -> DSR_W { DSR_W::new(self) } #[doc = "Bit 2 - DCD"] #[inline(always)] #[must_use] - pub fn dcd(&mut self) -> DCD_W<2> { + pub fn dcd(&mut self) -> DCD_W { DCD_W::new(self) } #[doc = "Bit 3 - BUSY"] #[inline(always)] #[must_use] - pub fn busy(&mut self) -> BUSY_W<3> { + pub fn busy(&mut self) -> BUSY_W { BUSY_W::new(self) } #[doc = "Bit 4 - RXFE"] #[inline(always)] #[must_use] - pub fn rxfe(&mut self) -> RXFE_W<4> { + pub fn rxfe(&mut self) -> RXFE_W { RXFE_W::new(self) } #[doc = "Bit 5 - TXFF"] #[inline(always)] #[must_use] - pub fn txff(&mut self) -> TXFF_W<5> { + pub fn txff(&mut self) -> TXFF_W { TXFF_W::new(self) } #[doc = "Bit 6 - RXFF"] #[inline(always)] #[must_use] - pub fn rxff(&mut self) -> RXFF_W<6> { + pub fn rxff(&mut self) -> RXFF_W { RXFF_W::new(self) } #[doc = "Bit 7 - TXFE"] #[inline(always)] #[must_use] - pub fn txfe(&mut self) -> TXFE_W<7> { + pub fn txfe(&mut self) -> TXFE_W { TXFE_W::new(self) } #[doc = "Bit 8 - RI"] #[inline(always)] #[must_use] - pub fn ri(&mut self) -> RI_W<8> { + pub fn ri(&mut self) -> RI_W { RI_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fr](index.html) module"] +#[doc = "Flag Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FR_SPEC; impl crate::RegisterSpec for FR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fr::R](R) reader structure"] -impl crate::Readable for FR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fr::W](W) writer structure"] +#[doc = "`read()` method returns [`fr::R`](R) reader structure"] +impl crate::Readable for FR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fr::W`](W) writer structure"] impl crate::Writable for FR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart0/ibrd.rs b/crates/bcm2835-lpa/src/uart0/ibrd.rs index 65af80e..07441c8 100644 --- a/crates/bcm2835-lpa/src/uart0/ibrd.rs +++ b/crates/bcm2835-lpa/src/uart0/ibrd.rs @@ -1,43 +1,11 @@ #[doc = "Register `IBRD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IBRD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BAUDDIVINT` reader - BAUDDIVINT"] -pub type BAUDDIVINT_R = crate::FieldReader; +pub type BAUDDIVINT_R = crate::FieldReader; #[doc = "Field `BAUDDIVINT` writer - BAUDDIVINT"] -pub type BAUDDIVINT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IBRD_SPEC, u16, u16, 16, O>; +pub type BAUDDIVINT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - BAUDDIVINT"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { BAUDDIVINT_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IBRD") + .field("bauddivint", &format_args!("{}", self.bauddivint().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - BAUDDIVINT"] #[inline(always)] #[must_use] - pub fn bauddivint(&mut self) -> BAUDDIVINT_W<0> { + pub fn bauddivint(&mut self) -> BAUDDIVINT_W { BAUDDIVINT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Integer Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ibrd](index.html) module"] +#[doc = "Integer Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibrd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IBRD_SPEC; impl crate::RegisterSpec for IBRD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ibrd::R](R) reader structure"] -impl crate::Readable for IBRD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ibrd::W](W) writer structure"] +#[doc = "`read()` method returns [`ibrd::R`](R) reader structure"] +impl crate::Readable for IBRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ibrd::W`](W) writer structure"] impl crate::Writable for IBRD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart0/icr.rs b/crates/bcm2835-lpa/src/uart0/icr.rs index 509869e..e69a3e9 100644 --- a/crates/bcm2835-lpa/src/uart0/icr.rs +++ b/crates/bcm2835-lpa/src/uart0/icr.rs @@ -1,128 +1,117 @@ #[doc = "Register `ICR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RIMIC` writer - RIMIC"] -pub type RIMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type RIMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTSMIC` writer - CTSMIC"] -pub type CTSMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type CTSMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCDMIC` writer - DCDMIC"] -pub type DCDMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type DCDMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSRMIC` writer - DSRMIC"] -pub type DSRMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type DSRMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXIC` writer - RXIC"] -pub type RXIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type RXIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXIC` writer - TXIC"] -pub type TXIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type TXIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTIC` writer - RTIC"] -pub type RTIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEIC` writer - FEIC"] -pub type FEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type FEIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEIC` writer - PEIC"] -pub type PEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type PEIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BEIC` writer - BEIC"] -pub type BEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type BEIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEIC` writer - OEIC"] -pub type OEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type OEIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - RIMIC"] #[inline(always)] #[must_use] - pub fn rimic(&mut self) -> RIMIC_W<0> { + pub fn rimic(&mut self) -> RIMIC_W { RIMIC_W::new(self) } #[doc = "Bit 1 - CTSMIC"] #[inline(always)] #[must_use] - pub fn ctsmic(&mut self) -> CTSMIC_W<1> { + pub fn ctsmic(&mut self) -> CTSMIC_W { CTSMIC_W::new(self) } #[doc = "Bit 2 - DCDMIC"] #[inline(always)] #[must_use] - pub fn dcdmic(&mut self) -> DCDMIC_W<2> { + pub fn dcdmic(&mut self) -> DCDMIC_W { DCDMIC_W::new(self) } #[doc = "Bit 3 - DSRMIC"] #[inline(always)] #[must_use] - pub fn dsrmic(&mut self) -> DSRMIC_W<3> { + pub fn dsrmic(&mut self) -> DSRMIC_W { DSRMIC_W::new(self) } #[doc = "Bit 4 - RXIC"] #[inline(always)] #[must_use] - pub fn rxic(&mut self) -> RXIC_W<4> { + pub fn rxic(&mut self) -> RXIC_W { RXIC_W::new(self) } #[doc = "Bit 5 - TXIC"] #[inline(always)] #[must_use] - pub fn txic(&mut self) -> TXIC_W<5> { + pub fn txic(&mut self) -> TXIC_W { TXIC_W::new(self) } #[doc = "Bit 6 - RTIC"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W<6> { + pub fn rtic(&mut self) -> RTIC_W { RTIC_W::new(self) } #[doc = "Bit 7 - FEIC"] #[inline(always)] #[must_use] - pub fn feic(&mut self) -> FEIC_W<7> { + pub fn feic(&mut self) -> FEIC_W { FEIC_W::new(self) } #[doc = "Bit 8 - PEIC"] #[inline(always)] #[must_use] - pub fn peic(&mut self) -> PEIC_W<8> { + pub fn peic(&mut self) -> PEIC_W { PEIC_W::new(self) } #[doc = "Bit 9 - BEIC"] #[inline(always)] #[must_use] - pub fn beic(&mut self) -> BEIC_W<9> { + pub fn beic(&mut self) -> BEIC_W { BEIC_W::new(self) } #[doc = "Bit 10 - OEIC"] #[inline(always)] #[must_use] - pub fn oeic(&mut self) -> OEIC_W<10> { + pub fn oeic(&mut self) -> OEIC_W { OEIC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"] +#[doc = "Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ICR_SPEC; impl crate::RegisterSpec for ICR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [icr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] impl crate::Writable for ICR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart0/ifls.rs b/crates/bcm2835-lpa/src/uart0/ifls.rs index 0cfe8d5..5119af0 100644 --- a/crates/bcm2835-lpa/src/uart0/ifls.rs +++ b/crates/bcm2835-lpa/src/uart0/ifls.rs @@ -1,47 +1,15 @@ #[doc = "Register `IFLS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IFLS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXIFLSEL` reader - TXIFLSEL"] -pub type TXIFLSEL_R = crate::FieldReader; +pub type TXIFLSEL_R = crate::FieldReader; #[doc = "Field `TXIFLSEL` writer - TXIFLSEL"] -pub type TXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFLS_SPEC, u8, u8, 3, O>; +pub type TXIFLSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `RXIFLSEL` reader - RXIFLSEL"] -pub type RXIFLSEL_R = crate::FieldReader; +pub type RXIFLSEL_R = crate::FieldReader; #[doc = "Field `RXIFLSEL` writer - RXIFLSEL"] -pub type RXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFLS_SPEC, u8, u8, 3, O>; +pub type RXIFLSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:2 - TXIFLSEL"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { RXIFLSEL_R::new(((self.bits >> 3) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IFLS") + .field("txiflsel", &format_args!("{}", self.txiflsel().bits())) + .field("rxiflsel", &format_args!("{}", self.rxiflsel().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - TXIFLSEL"] #[inline(always)] #[must_use] - pub fn txiflsel(&mut self) -> TXIFLSEL_W<0> { + pub fn txiflsel(&mut self) -> TXIFLSEL_W { TXIFLSEL_W::new(self) } #[doc = "Bits 3:5 - RXIFLSEL"] #[inline(always)] #[must_use] - pub fn rxiflsel(&mut self) -> RXIFLSEL_W<3> { + pub fn rxiflsel(&mut self) -> RXIFLSEL_W { RXIFLSEL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt FIFO Level Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifls](index.html) module"] +#[doc = "Interrupt FIFO Level Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifls::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifls::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IFLS_SPEC; impl crate::RegisterSpec for IFLS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ifls::R](R) reader structure"] -impl crate::Readable for IFLS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ifls::W](W) writer structure"] +#[doc = "`read()` method returns [`ifls::R`](R) reader structure"] +impl crate::Readable for IFLS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ifls::W`](W) writer structure"] impl crate::Writable for IFLS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart0/imsc.rs b/crates/bcm2835-lpa/src/uart0/imsc.rs index 1b0fb46..80b23a4 100644 --- a/crates/bcm2835-lpa/src/uart0/imsc.rs +++ b/crates/bcm2835-lpa/src/uart0/imsc.rs @@ -1,83 +1,51 @@ #[doc = "Register `IMSC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IMSC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RIMIM` reader - RIMIM"] -pub type RIMIM_R = crate::BitReader; +pub type RIMIM_R = crate::BitReader; #[doc = "Field `RIMIM` writer - RIMIM"] -pub type RIMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type RIMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTSMIM` reader - CTSMIM"] -pub type CTSMIM_R = crate::BitReader; +pub type CTSMIM_R = crate::BitReader; #[doc = "Field `CTSMIM` writer - CTSMIM"] -pub type CTSMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type CTSMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCDMIM` reader - DCDMIM"] -pub type DCDMIM_R = crate::BitReader; +pub type DCDMIM_R = crate::BitReader; #[doc = "Field `DCDMIM` writer - DCDMIM"] -pub type DCDMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type DCDMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSRMIM` reader - DSRMIM"] -pub type DSRMIM_R = crate::BitReader; +pub type DSRMIM_R = crate::BitReader; #[doc = "Field `DSRMIM` writer - DSRMIM"] -pub type DSRMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type DSRMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXIM` reader - RXIM"] -pub type RXIM_R = crate::BitReader; +pub type RXIM_R = crate::BitReader; #[doc = "Field `RXIM` writer - RXIM"] -pub type RXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXIM` reader - TXIM"] -pub type TXIM_R = crate::BitReader; +pub type TXIM_R = crate::BitReader; #[doc = "Field `TXIM` writer - TXIM"] -pub type TXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTIM` reader - RTIM"] -pub type RTIM_R = crate::BitReader; +pub type RTIM_R = crate::BitReader; #[doc = "Field `RTIM` writer - RTIM"] -pub type RTIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEIM` reader - FEIM"] -pub type FEIM_R = crate::BitReader; +pub type FEIM_R = crate::BitReader; #[doc = "Field `FEIM` writer - FEIM"] -pub type FEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type FEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEIM` reader - PEIM"] -pub type PEIM_R = crate::BitReader; +pub type PEIM_R = crate::BitReader; #[doc = "Field `PEIM` writer - PEIM"] -pub type PEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type PEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BEIM` reader - BEIM"] -pub type BEIM_R = crate::BitReader; +pub type BEIM_R = crate::BitReader; #[doc = "Field `BEIM` writer - BEIM"] -pub type BEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type BEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEIM` reader - OEIM"] -pub type OEIM_R = crate::BitReader; +pub type OEIM_R = crate::BitReader; #[doc = "Field `OEIM` writer - OEIM"] -pub type OEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type OEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - RIMIM"] #[inline(always)] @@ -135,92 +103,115 @@ impl R { OEIM_R::new(((self.bits >> 10) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IMSC") + .field("rimim", &format_args!("{}", self.rimim().bit())) + .field("ctsmim", &format_args!("{}", self.ctsmim().bit())) + .field("dcdmim", &format_args!("{}", self.dcdmim().bit())) + .field("dsrmim", &format_args!("{}", self.dsrmim().bit())) + .field("rxim", &format_args!("{}", self.rxim().bit())) + .field("txim", &format_args!("{}", self.txim().bit())) + .field("rtim", &format_args!("{}", self.rtim().bit())) + .field("feim", &format_args!("{}", self.feim().bit())) + .field("peim", &format_args!("{}", self.peim().bit())) + .field("beim", &format_args!("{}", self.beim().bit())) + .field("oeim", &format_args!("{}", self.oeim().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - RIMIM"] #[inline(always)] #[must_use] - pub fn rimim(&mut self) -> RIMIM_W<0> { + pub fn rimim(&mut self) -> RIMIM_W { RIMIM_W::new(self) } #[doc = "Bit 1 - CTSMIM"] #[inline(always)] #[must_use] - pub fn ctsmim(&mut self) -> CTSMIM_W<1> { + pub fn ctsmim(&mut self) -> CTSMIM_W { CTSMIM_W::new(self) } #[doc = "Bit 2 - DCDMIM"] #[inline(always)] #[must_use] - pub fn dcdmim(&mut self) -> DCDMIM_W<2> { + pub fn dcdmim(&mut self) -> DCDMIM_W { DCDMIM_W::new(self) } #[doc = "Bit 3 - DSRMIM"] #[inline(always)] #[must_use] - pub fn dsrmim(&mut self) -> DSRMIM_W<3> { + pub fn dsrmim(&mut self) -> DSRMIM_W { DSRMIM_W::new(self) } #[doc = "Bit 4 - RXIM"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W<4> { + pub fn rxim(&mut self) -> RXIM_W { RXIM_W::new(self) } #[doc = "Bit 5 - TXIM"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W<5> { + pub fn txim(&mut self) -> TXIM_W { TXIM_W::new(self) } #[doc = "Bit 6 - RTIM"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W<6> { + pub fn rtim(&mut self) -> RTIM_W { RTIM_W::new(self) } #[doc = "Bit 7 - FEIM"] #[inline(always)] #[must_use] - pub fn feim(&mut self) -> FEIM_W<7> { + pub fn feim(&mut self) -> FEIM_W { FEIM_W::new(self) } #[doc = "Bit 8 - PEIM"] #[inline(always)] #[must_use] - pub fn peim(&mut self) -> PEIM_W<8> { + pub fn peim(&mut self) -> PEIM_W { PEIM_W::new(self) } #[doc = "Bit 9 - BEIM"] #[inline(always)] #[must_use] - pub fn beim(&mut self) -> BEIM_W<9> { + pub fn beim(&mut self) -> BEIM_W { BEIM_W::new(self) } #[doc = "Bit 10 - OEIM"] #[inline(always)] #[must_use] - pub fn oeim(&mut self) -> OEIM_W<10> { + pub fn oeim(&mut self) -> OEIM_W { OEIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Mask set_Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imsc](index.html) module"] +#[doc = "Interrupt Mask set_Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imsc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMSC_SPEC; impl crate::RegisterSpec for IMSC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imsc::R](R) reader structure"] -impl crate::Readable for IMSC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [imsc::W](W) writer structure"] +#[doc = "`read()` method returns [`imsc::R`](R) reader structure"] +impl crate::Readable for IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`imsc::W`](W) writer structure"] impl crate::Writable for IMSC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart0/lcr_h.rs b/crates/bcm2835-lpa/src/uart0/lcr_h.rs index 6e02317..b6c85cc 100644 --- a/crates/bcm2835-lpa/src/uart0/lcr_h.rs +++ b/crates/bcm2835-lpa/src/uart0/lcr_h.rs @@ -1,67 +1,35 @@ #[doc = "Register `LCR_H` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LCR_H` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BRK` reader - BRK"] -pub type BRK_R = crate::BitReader; +pub type BRK_R = crate::BitReader; #[doc = "Field `BRK` writer - BRK"] -pub type BRK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type BRK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEN` reader - PEN"] -pub type PEN_R = crate::BitReader; +pub type PEN_R = crate::BitReader; #[doc = "Field `PEN` writer - PEN"] -pub type PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPS` reader - EPS"] -pub type EPS_R = crate::BitReader; +pub type EPS_R = crate::BitReader; #[doc = "Field `EPS` writer - EPS"] -pub type EPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STP2` reader - STP2"] -pub type STP2_R = crate::BitReader; +pub type STP2_R = crate::BitReader; #[doc = "Field `STP2` writer - STP2"] -pub type STP2_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type STP2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN` reader - FEN"] -pub type FEN_R = crate::BitReader; +pub type FEN_R = crate::BitReader; #[doc = "Field `FEN` writer - FEN"] -pub type FEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type FEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WLEN` reader - WLEN"] -pub type WLEN_R = crate::FieldReader; +pub type WLEN_R = crate::FieldReader; #[doc = "Field `WLEN` writer - WLEN"] -pub type WLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LCR_H_SPEC, u8, u8, 2, O>; +pub type WLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `SPS` reader - SPS"] -pub type SPS_R = crate::BitReader; +pub type SPS_R = crate::BitReader; #[doc = "Field `SPS` writer - SPS"] -pub type SPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type SPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - BRK"] #[inline(always)] @@ -99,68 +67,87 @@ impl R { SPS_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCR_H") + .field("brk", &format_args!("{}", self.brk().bit())) + .field("pen", &format_args!("{}", self.pen().bit())) + .field("eps", &format_args!("{}", self.eps().bit())) + .field("stp2", &format_args!("{}", self.stp2().bit())) + .field("fen", &format_args!("{}", self.fen().bit())) + .field("wlen", &format_args!("{}", self.wlen().bits())) + .field("sps", &format_args!("{}", self.sps().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - BRK"] #[inline(always)] #[must_use] - pub fn brk(&mut self) -> BRK_W<0> { + pub fn brk(&mut self) -> BRK_W { BRK_W::new(self) } #[doc = "Bit 1 - PEN"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W<1> { + pub fn pen(&mut self) -> PEN_W { PEN_W::new(self) } #[doc = "Bit 2 - EPS"] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W<2> { + pub fn eps(&mut self) -> EPS_W { EPS_W::new(self) } #[doc = "Bit 3 - STP2"] #[inline(always)] #[must_use] - pub fn stp2(&mut self) -> STP2_W<3> { + pub fn stp2(&mut self) -> STP2_W { STP2_W::new(self) } #[doc = "Bit 4 - FEN"] #[inline(always)] #[must_use] - pub fn fen(&mut self) -> FEN_W<4> { + pub fn fen(&mut self) -> FEN_W { FEN_W::new(self) } #[doc = "Bits 5:6 - WLEN"] #[inline(always)] #[must_use] - pub fn wlen(&mut self) -> WLEN_W<5> { + pub fn wlen(&mut self) -> WLEN_W { WLEN_W::new(self) } #[doc = "Bit 7 - SPS"] #[inline(always)] #[must_use] - pub fn sps(&mut self) -> SPS_W<7> { + pub fn sps(&mut self) -> SPS_W { SPS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Line Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr_h](index.html) module"] +#[doc = "Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr_h::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr_h::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LCR_H_SPEC; impl crate::RegisterSpec for LCR_H_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lcr_h::R](R) reader structure"] -impl crate::Readable for LCR_H_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [lcr_h::W](W) writer structure"] +#[doc = "`read()` method returns [`lcr_h::R`](R) reader structure"] +impl crate::Readable for LCR_H_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcr_h::W`](W) writer structure"] impl crate::Writable for LCR_H_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart0/mis.rs b/crates/bcm2835-lpa/src/uart0/mis.rs index ce802e5..8ecfc00 100644 --- a/crates/bcm2835-lpa/src/uart0/mis.rs +++ b/crates/bcm2835-lpa/src/uart0/mis.rs @@ -1,40 +1,27 @@ #[doc = "Register `MIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RIMMIS` reader - RIMMIS"] -pub type RIMMIS_R = crate::BitReader; +pub type RIMMIS_R = crate::BitReader; #[doc = "Field `CTSMMIS` reader - CTSMMIS"] -pub type CTSMMIS_R = crate::BitReader; +pub type CTSMMIS_R = crate::BitReader; #[doc = "Field `DCDMMIS` reader - DCDMMIS"] -pub type DCDMMIS_R = crate::BitReader; +pub type DCDMMIS_R = crate::BitReader; #[doc = "Field `DSRMMIS` reader - DSRMMIS"] -pub type DSRMMIS_R = crate::BitReader; +pub type DSRMMIS_R = crate::BitReader; #[doc = "Field `RXMIS` reader - RXMIS"] -pub type RXMIS_R = crate::BitReader; +pub type RXMIS_R = crate::BitReader; #[doc = "Field `TXMIS` reader - TXMIS"] -pub type TXMIS_R = crate::BitReader; +pub type TXMIS_R = crate::BitReader; #[doc = "Field `RTMIS` reader - RTMIS"] -pub type RTMIS_R = crate::BitReader; +pub type RTMIS_R = crate::BitReader; #[doc = "Field `FEMIS` reader - FEMIS"] -pub type FEMIS_R = crate::BitReader; +pub type FEMIS_R = crate::BitReader; #[doc = "Field `PEMIS` reader - PEMIS"] -pub type PEMIS_R = crate::BitReader; +pub type PEMIS_R = crate::BitReader; #[doc = "Field `BEMIS` reader - BEMIS"] -pub type BEMIS_R = crate::BitReader; +pub type BEMIS_R = crate::BitReader; #[doc = "Field `OEMIS` reader - OEMIS"] -pub type OEMIS_R = crate::BitReader; +pub type OEMIS_R = crate::BitReader; impl R { #[doc = "Bit 0 - RIMMIS"] #[inline(always)] @@ -92,15 +79,35 @@ impl R { OEMIS_R::new(((self.bits >> 10) & 1) != 0) } } -#[doc = "Masked Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mis](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MIS") + .field("rimmis", &format_args!("{}", self.rimmis().bit())) + .field("ctsmmis", &format_args!("{}", self.ctsmmis().bit())) + .field("dcdmmis", &format_args!("{}", self.dcdmmis().bit())) + .field("dsrmmis", &format_args!("{}", self.dsrmmis().bit())) + .field("rxmis", &format_args!("{}", self.rxmis().bit())) + .field("txmis", &format_args!("{}", self.txmis().bit())) + .field("rtmis", &format_args!("{}", self.rtmis().bit())) + .field("femis", &format_args!("{}", self.femis().bit())) + .field("pemis", &format_args!("{}", self.pemis().bit())) + .field("bemis", &format_args!("{}", self.bemis().bit())) + .field("oemis", &format_args!("{}", self.oemis().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Masked Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MIS_SPEC; impl crate::RegisterSpec for MIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mis::R](R) reader structure"] -impl crate::Readable for MIS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`mis::R`](R) reader structure"] +impl crate::Readable for MIS_SPEC {} #[doc = "`reset()` method sets MIS to value 0"] impl crate::Resettable for MIS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/uart0/ris.rs b/crates/bcm2835-lpa/src/uart0/ris.rs index 0ab6b9d..9da59ba 100644 --- a/crates/bcm2835-lpa/src/uart0/ris.rs +++ b/crates/bcm2835-lpa/src/uart0/ris.rs @@ -1,40 +1,27 @@ #[doc = "Register `RIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RIRMIS` reader - RIRMIS"] -pub type RIRMIS_R = crate::BitReader; +pub type RIRMIS_R = crate::BitReader; #[doc = "Field `CTSRMIS` reader - CTSRMIS"] -pub type CTSRMIS_R = crate::BitReader; +pub type CTSRMIS_R = crate::BitReader; #[doc = "Field `DCDRMIS` reader - DCDRMIS"] -pub type DCDRMIS_R = crate::BitReader; +pub type DCDRMIS_R = crate::BitReader; #[doc = "Field `DSRRMIS` reader - DSRRMIS"] -pub type DSRRMIS_R = crate::BitReader; +pub type DSRRMIS_R = crate::BitReader; #[doc = "Field `RXRIS` reader - RXRIS"] -pub type RXRIS_R = crate::BitReader; +pub type RXRIS_R = crate::BitReader; #[doc = "Field `TXRIS` reader - TXRIS"] -pub type TXRIS_R = crate::BitReader; +pub type TXRIS_R = crate::BitReader; #[doc = "Field `RTRIS` reader - RTRIS"] -pub type RTRIS_R = crate::BitReader; +pub type RTRIS_R = crate::BitReader; #[doc = "Field `FERIS` reader - FERIS"] -pub type FERIS_R = crate::BitReader; +pub type FERIS_R = crate::BitReader; #[doc = "Field `PERIS` reader - PERIS"] -pub type PERIS_R = crate::BitReader; +pub type PERIS_R = crate::BitReader; #[doc = "Field `BERIS` reader - BERIS"] -pub type BERIS_R = crate::BitReader; +pub type BERIS_R = crate::BitReader; #[doc = "Field `OERIS` reader - OERIS"] -pub type OERIS_R = crate::BitReader; +pub type OERIS_R = crate::BitReader; impl R { #[doc = "Bit 0 - RIRMIS"] #[inline(always)] @@ -92,15 +79,35 @@ impl R { OERIS_R::new(((self.bits >> 10) & 1) != 0) } } -#[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ris](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RIS") + .field("rirmis", &format_args!("{}", self.rirmis().bit())) + .field("ctsrmis", &format_args!("{}", self.ctsrmis().bit())) + .field("dcdrmis", &format_args!("{}", self.dcdrmis().bit())) + .field("dsrrmis", &format_args!("{}", self.dsrrmis().bit())) + .field("rxris", &format_args!("{}", self.rxris().bit())) + .field("txris", &format_args!("{}", self.txris().bit())) + .field("rtris", &format_args!("{}", self.rtris().bit())) + .field("feris", &format_args!("{}", self.feris().bit())) + .field("peris", &format_args!("{}", self.peris().bit())) + .field("beris", &format_args!("{}", self.beris().bit())) + .field("oeris", &format_args!("{}", self.oeris().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Raw Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RIS_SPEC; impl crate::RegisterSpec for RIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ris::R](R) reader structure"] -impl crate::Readable for RIS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ris::R`](R) reader structure"] +impl crate::Readable for RIS_SPEC {} #[doc = "`reset()` method sets RIS to value 0"] impl crate::Resettable for RIS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/uart0/rsr.rs b/crates/bcm2835-lpa/src/uart0/rsr.rs index 90a9e0d..524d503 100644 --- a/crates/bcm2835-lpa/src/uart0/rsr.rs +++ b/crates/bcm2835-lpa/src/uart0/rsr.rs @@ -1,26 +1,13 @@ #[doc = "Register `RSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FE` reader - FE"] -pub type FE_R = crate::BitReader; +pub type FE_R = crate::BitReader; #[doc = "Field `PE` reader - PE"] -pub type PE_R = crate::BitReader; +pub type PE_R = crate::BitReader; #[doc = "Field `BE` reader - BE"] -pub type BE_R = crate::BitReader; +pub type BE_R = crate::BitReader; #[doc = "Field `OE` reader - OE"] -pub type OE_R = crate::BitReader; +pub type OE_R = crate::BitReader; impl R { #[doc = "Bit 0 - FE"] #[inline(always)] @@ -43,15 +30,28 @@ impl R { OE_R::new(((self.bits >> 3) & 1) != 0) } } -#[doc = "Receive Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rsr](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSR") + .field("fe", &format_args!("{}", self.fe().bit())) + .field("pe", &format_args!("{}", self.pe().bit())) + .field("be", &format_args!("{}", self.be().bit())) + .field("oe", &format_args!("{}", self.oe().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Receive Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSR_SPEC; impl crate::RegisterSpec for RSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rsr::R](R) reader structure"] -impl crate::Readable for RSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rsr::R`](R) reader structure"] +impl crate::Readable for RSR_SPEC {} #[doc = "`reset()` method sets RSR to value 0"] impl crate::Resettable for RSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/uart1.rs b/crates/bcm2835-lpa/src/uart1.rs index a87a1e5..7cc03cc 100644 --- a/crates/bcm2835-lpa/src/uart1.rs +++ b/crates/bcm2835-lpa/src/uart1.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { _reserved_0_io: [u8; 0x04], _reserved_1_ier: [u8; 0x04], @@ -45,55 +46,68 @@ impl RegisterBlock { unsafe { &*(self as *const Self).cast::().add(4usize).cast() } } } -#[doc = "IO (rw) register accessor: an alias for `Reg`"] +#[doc = "IO (rw) register accessor: I/O Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io`] +module"] pub type IO = crate::Reg; #[doc = "I/O Data"] pub mod io; -#[doc = "BAUDL (rw) register accessor: an alias for `Reg`"] +#[doc = "BAUDL (rw) register accessor: Lower bits of baudrate when DLAB is set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baudl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baudl`] +module"] pub type BAUDL = crate::Reg; #[doc = "Lower bits of baudrate when DLAB is set"] pub mod baudl; -#[doc = "IER (rw) register accessor: an alias for `Reg`"] +#[doc = "IER (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable"] pub mod ier; -#[doc = "BAUDH (rw) register accessor: an alias for `Reg`"] +#[doc = "BAUDH (rw) register accessor: High bits of baudrate when DLAB is set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baudh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baudh`] +module"] pub type BAUDH = crate::Reg; #[doc = "High bits of baudrate when DLAB is set"] pub mod baudh; -#[doc = "IIR (rw) register accessor: an alias for `Reg`"] +#[doc = "IIR (rw) register accessor: Interrupt Identify\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] +module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identify"] pub mod iir; -#[doc = "LCR (rw) register accessor: an alias for `Reg`"] +#[doc = "LCR (rw) register accessor: Line control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] +module"] pub type LCR = crate::Reg; #[doc = "Line control"] pub mod lcr; -#[doc = "MCR (rw) register accessor: an alias for `Reg`"] +#[doc = "MCR (rw) register accessor: Modem Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] +module"] pub type MCR = crate::Reg; #[doc = "Modem Control"] pub mod mcr; -#[doc = "LSR (rw) register accessor: an alias for `Reg`"] +#[doc = "LSR (rw) register accessor: Line Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] +module"] pub type LSR = crate::Reg; #[doc = "Line Status"] pub mod lsr; -#[doc = "MSR (rw) register accessor: an alias for `Reg`"] +#[doc = "MSR (rw) register accessor: Modem Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] +module"] pub type MSR = crate::Reg; #[doc = "Modem Status"] pub mod msr; -#[doc = "SCRATCH (rw) register accessor: an alias for `Reg`"] +#[doc = "SCRATCH (rw) register accessor: Scratch\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scratch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scratch`] +module"] pub type SCRATCH = crate::Reg; #[doc = "Scratch"] pub mod scratch; -#[doc = "CNTL (rw) register accessor: an alias for `Reg`"] +#[doc = "CNTL (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntl`] +module"] pub type CNTL = crate::Reg; #[doc = "Control"] pub mod cntl; -#[doc = "STAT (rw) register accessor: an alias for `Reg`"] +#[doc = "STAT (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] +module"] pub type STAT = crate::Reg; #[doc = "Status"] pub mod stat; -#[doc = "BAUD (rw) register accessor: an alias for `Reg`"] +#[doc = "BAUD (rw) register accessor: Baudrate\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baud::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baud::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baud`] +module"] pub type BAUD = crate::Reg; #[doc = "Baudrate"] pub mod baud; diff --git a/crates/bcm2835-lpa/src/uart1/baud.rs b/crates/bcm2835-lpa/src/uart1/baud.rs index 088c774..4cc37c7 100644 --- a/crates/bcm2835-lpa/src/uart1/baud.rs +++ b/crates/bcm2835-lpa/src/uart1/baud.rs @@ -1,59 +1,38 @@ #[doc = "Register `BAUD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BAUD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Baudrate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +#[doc = "Baudrate\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baud::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baud::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BAUD_SPEC; impl crate::RegisterSpec for BAUD_SPEC { type Ux = u16; } -#[doc = "`read()` method returns [baud::R](R) reader structure"] -impl crate::Readable for BAUD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +#[doc = "`read()` method returns [`baud::R`](R) reader structure"] +impl crate::Readable for BAUD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`baud::W`](W) writer structure"] impl crate::Writable for BAUD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart1/baudh.rs b/crates/bcm2835-lpa/src/uart1/baudh.rs index 8c30695..aa2fa88 100644 --- a/crates/bcm2835-lpa/src/uart1/baudh.rs +++ b/crates/bcm2835-lpa/src/uart1/baudh.rs @@ -1,59 +1,38 @@ #[doc = "Register `BAUDH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BAUDH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "High bits of baudrate when DLAB is set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudh](index.html) module"] +#[doc = "High bits of baudrate when DLAB is set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baudh::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BAUDH_SPEC; impl crate::RegisterSpec for BAUDH_SPEC { type Ux = u8; } -#[doc = "`read()` method returns [baudh::R](R) reader structure"] -impl crate::Readable for BAUDH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [baudh::W](W) writer structure"] +#[doc = "`read()` method returns [`baudh::R`](R) reader structure"] +impl crate::Readable for BAUDH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`baudh::W`](W) writer structure"] impl crate::Writable for BAUDH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart1/baudl.rs b/crates/bcm2835-lpa/src/uart1/baudl.rs index ca7c9f0..a9c9850 100644 --- a/crates/bcm2835-lpa/src/uart1/baudl.rs +++ b/crates/bcm2835-lpa/src/uart1/baudl.rs @@ -1,59 +1,38 @@ #[doc = "Register `BAUDL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BAUDL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Lower bits of baudrate when DLAB is set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudl](index.html) module"] +#[doc = "Lower bits of baudrate when DLAB is set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baudl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BAUDL_SPEC; impl crate::RegisterSpec for BAUDL_SPEC { type Ux = u8; } -#[doc = "`read()` method returns [baudl::R](R) reader structure"] -impl crate::Readable for BAUDL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [baudl::W](W) writer structure"] +#[doc = "`read()` method returns [`baudl::R`](R) reader structure"] +impl crate::Readable for BAUDL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`baudl::W`](W) writer structure"] impl crate::Writable for BAUDL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart1/cntl.rs b/crates/bcm2835-lpa/src/uart1/cntl.rs index 4125093..ca942f3 100644 --- a/crates/bcm2835-lpa/src/uart1/cntl.rs +++ b/crates/bcm2835-lpa/src/uart1/cntl.rs @@ -1,57 +1,25 @@ #[doc = "Register `CNTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CNTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RX_ENABLE` reader - Enable receive"] -pub type RX_ENABLE_R = crate::BitReader; +pub type RX_ENABLE_R = crate::BitReader; #[doc = "Field `RX_ENABLE` writer - Enable receive"] -pub type RX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +pub type RX_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_ENABLE` reader - Enable transmit"] -pub type TX_ENABLE_R = crate::BitReader; +pub type TX_ENABLE_R = crate::BitReader; #[doc = "Field `TX_ENABLE` writer - Enable transmit"] -pub type TX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +pub type TX_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTS_ENABLE` reader - Enable auto receive flow control with RTS"] -pub type RTS_ENABLE_R = crate::BitReader; +pub type RTS_ENABLE_R = crate::BitReader; #[doc = "Field `RTS_ENABLE` writer - Enable auto receive flow control with RTS"] -pub type RTS_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +pub type RTS_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTS_ENABLE` reader - Enable auto transmit flow control with CTS"] -pub type CTS_ENABLE_R = crate::BitReader; +pub type CTS_ENABLE_R = crate::BitReader; #[doc = "Field `CTS_ENABLE` writer - Enable auto transmit flow control with CTS"] -pub type CTS_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +pub type CTS_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTS_FIFO_LEVEL` reader - FIFO level to de-assert RTS"] -pub type RTS_FIFO_LEVEL_R = crate::FieldReader; +pub type RTS_FIFO_LEVEL_R = crate::FieldReader; #[doc = "FIFO level to de-assert RTS\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -71,10 +39,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FIFO_LEVEL_A { + type Ux = u8; +} impl RTS_FIFO_LEVEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FIFO_LEVEL_A { + pub const fn variant(&self) -> FIFO_LEVEL_A { match self.bits { 0 => FIFO_LEVEL_A::_3EMPTY, 1 => FIFO_LEVEL_A::_2EMPTY, @@ -83,49 +54,53 @@ impl RTS_FIFO_LEVEL_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_3EMPTY`"] + #[doc = "3 empty spaces"] #[inline(always)] pub fn is_3empty(&self) -> bool { *self == FIFO_LEVEL_A::_3EMPTY } - #[doc = "Checks if the value of the field is `_2EMPTY`"] + #[doc = "2 empty spaces"] #[inline(always)] pub fn is_2empty(&self) -> bool { *self == FIFO_LEVEL_A::_2EMPTY } - #[doc = "Checks if the value of the field is `_1EMPTY`"] + #[doc = "1 empty spaces"] #[inline(always)] pub fn is_1empty(&self) -> bool { *self == FIFO_LEVEL_A::_1EMPTY } - #[doc = "Checks if the value of the field is `_4EMPTY`"] + #[doc = "4 empty spaces"] #[inline(always)] pub fn is_4empty(&self) -> bool { *self == FIFO_LEVEL_A::_4EMPTY } } #[doc = "Field `RTS_FIFO_LEVEL` writer - FIFO level to de-assert RTS"] -pub type RTS_FIFO_LEVEL_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, CNTL_SPEC, u8, FIFO_LEVEL_A, 2, O>; -impl<'a, const O: u8> RTS_FIFO_LEVEL_W<'a, O> { +pub type RTS_FIFO_LEVEL_W<'a, REG, const O: u8> = + crate::FieldWriterSafe<'a, REG, 2, O, FIFO_LEVEL_A>; +impl<'a, REG, const O: u8> RTS_FIFO_LEVEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "3 empty spaces"] #[inline(always)] - pub fn _3empty(self) -> &'a mut W { + pub fn _3empty(self) -> &'a mut crate::W { self.variant(FIFO_LEVEL_A::_3EMPTY) } #[doc = "2 empty spaces"] #[inline(always)] - pub fn _2empty(self) -> &'a mut W { + pub fn _2empty(self) -> &'a mut crate::W { self.variant(FIFO_LEVEL_A::_2EMPTY) } #[doc = "1 empty spaces"] #[inline(always)] - pub fn _1empty(self) -> &'a mut W { + pub fn _1empty(self) -> &'a mut crate::W { self.variant(FIFO_LEVEL_A::_1EMPTY) } #[doc = "4 empty spaces"] #[inline(always)] - pub fn _4empty(self) -> &'a mut W { + pub fn _4empty(self) -> &'a mut crate::W { self.variant(FIFO_LEVEL_A::_4EMPTY) } } @@ -152,34 +127,37 @@ impl From for bool { impl CTS_ASSERT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ASSERT_LEVEL_A { + pub const fn variant(&self) -> ASSERT_LEVEL_A { match self.bits { false => ASSERT_LEVEL_A::HIGH, true => ASSERT_LEVEL_A::LOW, } } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "Assert high"] #[inline(always)] pub fn is_high(&self) -> bool { *self == ASSERT_LEVEL_A::HIGH } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "Assert low"] #[inline(always)] pub fn is_low(&self) -> bool { *self == ASSERT_LEVEL_A::LOW } } #[doc = "Field `CTS_ASSERT` writer - CTS assert level"] -pub type CTS_ASSERT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, ASSERT_LEVEL_A, O>; -impl<'a, const O: u8> CTS_ASSERT_W<'a, O> { +pub type CTS_ASSERT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ASSERT_LEVEL_A>; +impl<'a, REG, const O: u8> CTS_ASSERT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Assert high"] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(ASSERT_LEVEL_A::HIGH) } #[doc = "Assert low"] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(ASSERT_LEVEL_A::LOW) } } @@ -220,68 +198,90 @@ impl R { CTS_ASSERT_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CNTL") + .field("cts_assert", &format_args!("{}", self.cts_assert().bit())) + .field("rts_assert", &format_args!("{}", self.rts_assert().bit())) + .field( + "rts_fifo_level", + &format_args!("{}", self.rts_fifo_level().bits()), + ) + .field("cts_enable", &format_args!("{}", self.cts_enable().bit())) + .field("rts_enable", &format_args!("{}", self.rts_enable().bit())) + .field("tx_enable", &format_args!("{}", self.tx_enable().bit())) + .field("rx_enable", &format_args!("{}", self.rx_enable().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable receive"] #[inline(always)] #[must_use] - pub fn rx_enable(&mut self) -> RX_ENABLE_W<0> { + pub fn rx_enable(&mut self) -> RX_ENABLE_W { RX_ENABLE_W::new(self) } #[doc = "Bit 1 - Enable transmit"] #[inline(always)] #[must_use] - pub fn tx_enable(&mut self) -> TX_ENABLE_W<1> { + pub fn tx_enable(&mut self) -> TX_ENABLE_W { TX_ENABLE_W::new(self) } #[doc = "Bit 2 - Enable auto receive flow control with RTS"] #[inline(always)] #[must_use] - pub fn rts_enable(&mut self) -> RTS_ENABLE_W<2> { + pub fn rts_enable(&mut self) -> RTS_ENABLE_W { RTS_ENABLE_W::new(self) } #[doc = "Bit 3 - Enable auto transmit flow control with CTS"] #[inline(always)] #[must_use] - pub fn cts_enable(&mut self) -> CTS_ENABLE_W<3> { + pub fn cts_enable(&mut self) -> CTS_ENABLE_W { CTS_ENABLE_W::new(self) } #[doc = "Bits 4:5 - FIFO level to de-assert RTS"] #[inline(always)] #[must_use] - pub fn rts_fifo_level(&mut self) -> RTS_FIFO_LEVEL_W<4> { + pub fn rts_fifo_level(&mut self) -> RTS_FIFO_LEVEL_W { RTS_FIFO_LEVEL_W::new(self) } #[doc = "Bit 6 - RTS assert level"] #[inline(always)] #[must_use] - pub fn rts_assert(&mut self) -> RTS_ASSERT_W<6> { + pub fn rts_assert(&mut self) -> RTS_ASSERT_W { RTS_ASSERT_W::new(self) } #[doc = "Bit 7 - CTS assert level"] #[inline(always)] #[must_use] - pub fn cts_assert(&mut self) -> CTS_ASSERT_W<7> { + pub fn cts_assert(&mut self) -> CTS_ASSERT_W { CTS_ASSERT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CNTL_SPEC; impl crate::RegisterSpec for CNTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cntl::R](R) reader structure"] -impl crate::Readable for CNTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cntl::W](W) writer structure"] +#[doc = "`read()` method returns [`cntl::R`](R) reader structure"] +impl crate::Readable for CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cntl::W`](W) writer structure"] impl crate::Writable for CNTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart1/ier.rs b/crates/bcm2835-lpa/src/uart1/ier.rs index 450afd5..f3188e7 100644 --- a/crates/bcm2835-lpa/src/uart1/ier.rs +++ b/crates/bcm2835-lpa/src/uart1/ier.rs @@ -1,47 +1,15 @@ #[doc = "Register `IER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA_READY` reader - Receive FIFO has at least 1 byte"] -pub type DATA_READY_R = crate::BitReader; +pub type DATA_READY_R = crate::BitReader; #[doc = "Field `DATA_READY` writer - Receive FIFO has at least 1 byte"] -pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>; +pub type DATA_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_READY` reader - Transmit FIFO is empty"] -pub type TX_READY_R = crate::BitReader; +pub type TX_READY_R = crate::BitReader; #[doc = "Field `TX_READY` writer - Transmit FIFO is empty"] -pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>; +pub type TX_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Receive FIFO has at least 1 byte"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { TX_READY_R::new(((self.bits >> 1) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IER") + .field("tx_ready", &format_args!("{}", self.tx_ready().bit())) + .field("data_ready", &format_args!("{}", self.data_ready().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Receive FIFO has at least 1 byte"] #[inline(always)] #[must_use] - pub fn data_ready(&mut self) -> DATA_READY_W<0> { + pub fn data_ready(&mut self) -> DATA_READY_W { DATA_READY_W::new(self) } #[doc = "Bit 1 - Transmit FIFO is empty"] #[inline(always)] #[must_use] - pub fn tx_ready(&mut self) -> TX_READY_W<1> { + pub fn tx_ready(&mut self) -> TX_READY_W { TX_READY_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ier::R](R) reader structure"] -impl crate::Readable for IER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`read()` method returns [`ier::R`](R) reader structure"] +impl crate::Readable for IER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart1/iir.rs b/crates/bcm2835-lpa/src/uart1/iir.rs index 6f66eac..b7a876b 100644 --- a/crates/bcm2835-lpa/src/uart1/iir.rs +++ b/crates/bcm2835-lpa/src/uart1/iir.rs @@ -1,51 +1,19 @@ #[doc = "Register `IIR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IIR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `nPENDING` reader - No pending interrupt"] -pub type N_PENDING_R = crate::BitReader; +pub type N_PENDING_R = crate::BitReader; #[doc = "Field `nPENDING` writer - No pending interrupt"] -pub type N_PENDING_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +pub type N_PENDING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_READY` reader - Receive FIFO has at least 1 byte"] -pub type DATA_READY_R = crate::BitReader; +pub type DATA_READY_R = crate::BitReader; #[doc = "Field `DATA_READY` writer - Receive FIFO has at least 1 byte"] -pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +pub type DATA_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_READY` reader - Transmit FIFO is empty"] -pub type TX_READY_R = crate::BitReader; +pub type TX_READY_R = crate::BitReader; #[doc = "Field `TX_READY` writer - Transmit FIFO is empty"] -pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +pub type TX_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - No pending interrupt"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { TX_READY_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IIR") + .field("tx_ready", &format_args!("{}", self.tx_ready().bit())) + .field("data_ready", &format_args!("{}", self.data_ready().bit())) + .field("n_pending", &format_args!("{}", self.n_pending().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - No pending interrupt"] #[inline(always)] #[must_use] - pub fn n_pending(&mut self) -> N_PENDING_W<0> { + pub fn n_pending(&mut self) -> N_PENDING_W { N_PENDING_W::new(self) } #[doc = "Bit 1 - Receive FIFO has at least 1 byte"] #[inline(always)] #[must_use] - pub fn data_ready(&mut self) -> DATA_READY_W<1> { + pub fn data_ready(&mut self) -> DATA_READY_W { DATA_READY_W::new(self) } #[doc = "Bit 2 - Transmit FIFO is empty"] #[inline(always)] #[must_use] - pub fn tx_ready(&mut self) -> TX_READY_W<2> { + pub fn tx_ready(&mut self) -> TX_READY_W { TX_READY_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Identify\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iir](index.html) module"] +#[doc = "Interrupt Identify\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IIR_SPEC; impl crate::RegisterSpec for IIR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [iir::R](R) reader structure"] -impl crate::Readable for IIR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [iir::W](W) writer structure"] +#[doc = "`read()` method returns [`iir::R`](R) reader structure"] +impl crate::Readable for IIR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`iir::W`](W) writer structure"] impl crate::Writable for IIR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart1/io.rs b/crates/bcm2835-lpa/src/uart1/io.rs index 84cd075..1873e08 100644 --- a/crates/bcm2835-lpa/src/uart1/io.rs +++ b/crates/bcm2835-lpa/src/uart1/io.rs @@ -1,43 +1,11 @@ #[doc = "Register `IO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IO` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - FIFO access"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - FIFO access"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO_SPEC, u8, u8, 8, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - FIFO access"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new((self.bits & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IO") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - FIFO access"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "I/O Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](index.html) module"] +#[doc = "I/O Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IO_SPEC; impl crate::RegisterSpec for IO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [io::R](R) reader structure"] -impl crate::Readable for IO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [io::W](W) writer structure"] +#[doc = "`read()` method returns [`io::R`](R) reader structure"] +impl crate::Readable for IO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`io::W`](W) writer structure"] impl crate::Writable for IO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart1/lcr.rs b/crates/bcm2835-lpa/src/uart1/lcr.rs index 16b3c2b..38e7d1e 100644 --- a/crates/bcm2835-lpa/src/uart1/lcr.rs +++ b/crates/bcm2835-lpa/src/uart1/lcr.rs @@ -1,41 +1,9 @@ #[doc = "Register `LCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA_SIZE` reader - UART word size"] -pub type DATA_SIZE_R = crate::FieldReader; +pub type DATA_SIZE_R = crate::FieldReader; #[doc = "UART word size\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -51,49 +19,56 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for MODE_A { + type Ux = u8; +} impl DATA_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(MODE_A::_7BIT), 3 => Some(MODE_A::_8BIT), _ => None, } } - #[doc = "Checks if the value of the field is `_7BIT`"] + #[doc = "7 bit"] #[inline(always)] pub fn is_7bit(&self) -> bool { *self == MODE_A::_7BIT } - #[doc = "Checks if the value of the field is `_8BIT`"] + #[doc = "8 bit"] #[inline(always)] pub fn is_8bit(&self) -> bool { *self == MODE_A::_8BIT } } #[doc = "Field `DATA_SIZE` writer - UART word size"] -pub type DATA_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LCR_SPEC, u8, MODE_A, 2, O>; -impl<'a, const O: u8> DATA_SIZE_W<'a, O> { +pub type DATA_SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, MODE_A>; +impl<'a, REG, const O: u8> DATA_SIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "7 bit"] #[inline(always)] - pub fn _7bit(self) -> &'a mut W { + pub fn _7bit(self) -> &'a mut crate::W { self.variant(MODE_A::_7BIT) } #[doc = "8 bit"] #[inline(always)] - pub fn _8bit(self) -> &'a mut W { + pub fn _8bit(self) -> &'a mut crate::W { self.variant(MODE_A::_8BIT) } } #[doc = "Field `BREAK` reader - Pull TX low continuously to send break"] -pub type BREAK_R = crate::BitReader; +pub type BREAK_R = crate::BitReader; #[doc = "Field `BREAK` writer - Pull TX low continuously to send break"] -pub type BREAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_SPEC, bool, O>; +pub type BREAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DLAB` reader - First two registers are baudrate"] -pub type DLAB_R = crate::BitReader; +pub type DLAB_R = crate::BitReader; #[doc = "Field `DLAB` writer - First two registers are baudrate"] -pub type DLAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_SPEC, bool, O>; +pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:1 - UART word size"] #[inline(always)] @@ -111,44 +86,59 @@ impl R { DLAB_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCR") + .field("dlab", &format_args!("{}", self.dlab().bit())) + .field("break_", &format_args!("{}", self.break_().bit())) + .field("data_size", &format_args!("{}", self.data_size().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - UART word size"] #[inline(always)] #[must_use] - pub fn data_size(&mut self) -> DATA_SIZE_W<0> { + pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W::new(self) } #[doc = "Bit 6 - Pull TX low continuously to send break"] #[inline(always)] #[must_use] - pub fn break_(&mut self) -> BREAK_W<6> { + pub fn break_(&mut self) -> BREAK_W { BREAK_W::new(self) } #[doc = "Bit 7 - First two registers are baudrate"] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W<7> { + pub fn dlab(&mut self) -> DLAB_W { DLAB_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Line control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr](index.html) module"] +#[doc = "Line control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LCR_SPEC; impl crate::RegisterSpec for LCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lcr::R](R) reader structure"] -impl crate::Readable for LCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [lcr::W](W) writer structure"] +#[doc = "`read()` method returns [`lcr::R`](R) reader structure"] +impl crate::Readable for LCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcr::W`](W) writer structure"] impl crate::Writable for LCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart1/lsr.rs b/crates/bcm2835-lpa/src/uart1/lsr.rs index ba34ba7..83455e7 100644 --- a/crates/bcm2835-lpa/src/uart1/lsr.rs +++ b/crates/bcm2835-lpa/src/uart1/lsr.rs @@ -1,55 +1,23 @@ #[doc = "Register `LSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA_READY` reader - Receive FIFO has at least one byte"] -pub type DATA_READY_R = crate::BitReader; +pub type DATA_READY_R = crate::BitReader; #[doc = "Field `DATA_READY` writer - Receive FIFO has at least one byte"] -pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +pub type DATA_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_OVERRUN` reader - Receive FIFO overrun"] -pub type RX_OVERRUN_R = crate::BitReader; +pub type RX_OVERRUN_R = crate::BitReader; #[doc = "Field `RX_OVERRUN` writer - Receive FIFO overrun"] -pub type RX_OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +pub type RX_OVERRUN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_EMPTY` reader - Transmit FIFO has room for at least one byte"] -pub type TX_EMPTY_R = crate::BitReader; +pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `TX_EMPTY` writer - Transmit FIFO has room for at least one byte"] -pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_IDLE` reader - Transmit FIFO empty and all bits shifted out"] -pub type TX_IDLE_R = crate::BitReader; +pub type TX_IDLE_R = crate::BitReader; #[doc = "Field `TX_IDLE` writer - Transmit FIFO empty and all bits shifted out"] -pub type TX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +pub type TX_IDLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Receive FIFO has at least one byte"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { TX_IDLE_R::new(((self.bits >> 6) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LSR") + .field("tx_idle", &format_args!("{}", self.tx_idle().bit())) + .field("tx_empty", &format_args!("{}", self.tx_empty().bit())) + .field("rx_overrun", &format_args!("{}", self.rx_overrun().bit())) + .field("data_ready", &format_args!("{}", self.data_ready().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Receive FIFO has at least one byte"] #[inline(always)] #[must_use] - pub fn data_ready(&mut self) -> DATA_READY_W<0> { + pub fn data_ready(&mut self) -> DATA_READY_W { DATA_READY_W::new(self) } #[doc = "Bit 1 - Receive FIFO overrun"] #[inline(always)] #[must_use] - pub fn rx_overrun(&mut self) -> RX_OVERRUN_W<1> { + pub fn rx_overrun(&mut self) -> RX_OVERRUN_W { RX_OVERRUN_W::new(self) } #[doc = "Bit 5 - Transmit FIFO has room for at least one byte"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W<5> { + pub fn tx_empty(&mut self) -> TX_EMPTY_W { TX_EMPTY_W::new(self) } #[doc = "Bit 6 - Transmit FIFO empty and all bits shifted out"] #[inline(always)] #[must_use] - pub fn tx_idle(&mut self) -> TX_IDLE_W<6> { + pub fn tx_idle(&mut self) -> TX_IDLE_W { TX_IDLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Line Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lsr](index.html) module"] +#[doc = "Line Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LSR_SPEC; impl crate::RegisterSpec for LSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lsr::R](R) reader structure"] -impl crate::Readable for LSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [lsr::W](W) writer structure"] +#[doc = "`read()` method returns [`lsr::R`](R) reader structure"] +impl crate::Readable for LSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lsr::W`](W) writer structure"] impl crate::Writable for LSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart1/mcr.rs b/crates/bcm2835-lpa/src/uart1/mcr.rs index 89de0a8..26a7cb4 100644 --- a/crates/bcm2835-lpa/src/uart1/mcr.rs +++ b/crates/bcm2835-lpa/src/uart1/mcr.rs @@ -1,43 +1,11 @@ #[doc = "Register `MCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RTS` reader - RTS is low"] -pub type RTS_R = crate::BitReader; +pub type RTS_R = crate::BitReader; #[doc = "Field `RTS` writer - RTS is low"] -pub type RTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>; +pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - RTS is low"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { RTS_R::new(((self.bits >> 1) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCR") + .field("rts", &format_args!("{}", self.rts().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - RTS is low"] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W<1> { + pub fn rts(&mut self) -> RTS_W { RTS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Modem Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr](index.html) module"] +#[doc = "Modem Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCR_SPEC; impl crate::RegisterSpec for MCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mcr::R](R) reader structure"] -impl crate::Readable for MCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mcr::W](W) writer structure"] +#[doc = "`read()` method returns [`mcr::R`](R) reader structure"] +impl crate::Readable for MCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] impl crate::Writable for MCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart1/msr.rs b/crates/bcm2835-lpa/src/uart1/msr.rs index 3960539..c6e81af 100644 --- a/crates/bcm2835-lpa/src/uart1/msr.rs +++ b/crates/bcm2835-lpa/src/uart1/msr.rs @@ -1,43 +1,11 @@ #[doc = "Register `MSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CTS` reader - CTS is low"] -pub type CTS_R = crate::BitReader; +pub type CTS_R = crate::BitReader; #[doc = "Field `CTS` writer - CTS is low"] -pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSR_SPEC, bool, O>; +pub type CTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 4 - CTS is low"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { CTS_R::new(((self.bits >> 4) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MSR") + .field("cts", &format_args!("{}", self.cts().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 4 - CTS is low"] #[inline(always)] #[must_use] - pub fn cts(&mut self) -> CTS_W<4> { + pub fn cts(&mut self) -> CTS_W { CTS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Modem Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msr](index.html) module"] +#[doc = "Modem Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MSR_SPEC; impl crate::RegisterSpec for MSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [msr::R](R) reader structure"] -impl crate::Readable for MSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [msr::W](W) writer structure"] +#[doc = "`read()` method returns [`msr::R`](R) reader structure"] +impl crate::Readable for MSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`msr::W`](W) writer structure"] impl crate::Writable for MSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart1/scratch.rs b/crates/bcm2835-lpa/src/uart1/scratch.rs index c85f068..bd73381 100644 --- a/crates/bcm2835-lpa/src/uart1/scratch.rs +++ b/crates/bcm2835-lpa/src/uart1/scratch.rs @@ -1,59 +1,38 @@ #[doc = "Register `SCRATCH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCRATCH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Scratch\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scratch](index.html) module"] +#[doc = "Scratch\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scratch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCRATCH_SPEC; impl crate::RegisterSpec for SCRATCH_SPEC { type Ux = u8; } -#[doc = "`read()` method returns [scratch::R](R) reader structure"] -impl crate::Readable for SCRATCH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scratch::W](W) writer structure"] +#[doc = "`read()` method returns [`scratch::R`](R) reader structure"] +impl crate::Readable for SCRATCH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch::W`](W) writer structure"] impl crate::Writable for SCRATCH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/uart1/stat.rs b/crates/bcm2835-lpa/src/uart1/stat.rs index 114015e..b876fef 100644 --- a/crates/bcm2835-lpa/src/uart1/stat.rs +++ b/crates/bcm2835-lpa/src/uart1/stat.rs @@ -1,87 +1,55 @@ #[doc = "Register `STAT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STAT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA_READY` reader - Receive FIFO has at least one symbol"] -pub type DATA_READY_R = crate::BitReader; +pub type DATA_READY_R = crate::BitReader; #[doc = "Field `DATA_READY` writer - Receive FIFO has at least one symbol"] -pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type DATA_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_READY` reader - Transmit FIFO has space for at least one symbol"] -pub type TX_READY_R = crate::BitReader; +pub type TX_READY_R = crate::BitReader; #[doc = "Field `TX_READY` writer - Transmit FIFO has space for at least one symbol"] -pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_IDLE` reader - Receiver is idle"] -pub type RX_IDLE_R = crate::BitReader; +pub type RX_IDLE_R = crate::BitReader; #[doc = "Field `RX_IDLE` writer - Receiver is idle"] -pub type RX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RX_IDLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_IDLE` reader - Transmitter is idle"] -pub type TX_IDLE_R = crate::BitReader; +pub type TX_IDLE_R = crate::BitReader; #[doc = "Field `TX_IDLE` writer - Transmitter is idle"] -pub type TX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_IDLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_OVERRUN` reader - Receive FIFO overrun"] -pub type RX_OVERRUN_R = crate::BitReader; +pub type RX_OVERRUN_R = crate::BitReader; #[doc = "Field `RX_OVERRUN` writer - Receive FIFO overrun"] -pub type RX_OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RX_OVERRUN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_FULL` reader - Transmit FIFO is full"] -pub type TX_FULL_R = crate::BitReader; +pub type TX_FULL_R = crate::BitReader; #[doc = "Field `TX_FULL` writer - Transmit FIFO is full"] -pub type TX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTS_STATUS` reader - RTS state"] -pub type RTS_STATUS_R = crate::BitReader; +pub type RTS_STATUS_R = crate::BitReader; #[doc = "Field `RTS_STATUS` writer - RTS state"] -pub type RTS_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RTS_STATUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTS_STATUS` reader - CTS state"] -pub type CTS_STATUS_R = crate::BitReader; +pub type CTS_STATUS_R = crate::BitReader; #[doc = "Field `CTS_STATUS` writer - CTS state"] -pub type CTS_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type CTS_STATUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_EMPTY` reader - Transmit FIFO is completely empty"] -pub type TX_EMPTY_R = crate::BitReader; +pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `TX_EMPTY` writer - Transmit FIFO is completely empty"] -pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_DONE` reader - Transmit FIFO is empty and transmitter is idle"] -pub type TX_DONE_R = crate::BitReader; +pub type TX_DONE_R = crate::BitReader; #[doc = "Field `TX_DONE` writer - Transmit FIFO is empty and transmitter is idle"] -pub type TX_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_FIFO_LEVEL` reader - How many entries are filled in the RX FIFO"] -pub type RX_FIFO_LEVEL_R = crate::FieldReader; +pub type RX_FIFO_LEVEL_R = crate::FieldReader; #[doc = "Field `RX_FIFO_LEVEL` writer - How many entries are filled in the RX FIFO"] -pub type RX_FIFO_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +pub type RX_FIFO_LEVEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TX_FIFO_LEVEL` reader - How many entries are filled in the TX FIFO"] -pub type TX_FIFO_LEVEL_R = crate::FieldReader; +pub type TX_FIFO_LEVEL_R = crate::FieldReader; #[doc = "Field `TX_FIFO_LEVEL` writer - How many entries are filled in the TX FIFO"] -pub type TX_FIFO_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +pub type TX_FIFO_LEVEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bit 0 - Receive FIFO has at least one symbol"] #[inline(always)] @@ -144,98 +112,128 @@ impl R { TX_FIFO_LEVEL_R::new(((self.bits >> 24) & 0x0f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STAT") + .field( + "tx_fifo_level", + &format_args!("{}", self.tx_fifo_level().bits()), + ) + .field( + "rx_fifo_level", + &format_args!("{}", self.rx_fifo_level().bits()), + ) + .field("tx_done", &format_args!("{}", self.tx_done().bit())) + .field("tx_empty", &format_args!("{}", self.tx_empty().bit())) + .field("cts_status", &format_args!("{}", self.cts_status().bit())) + .field("rts_status", &format_args!("{}", self.rts_status().bit())) + .field("tx_full", &format_args!("{}", self.tx_full().bit())) + .field("rx_overrun", &format_args!("{}", self.rx_overrun().bit())) + .field("tx_idle", &format_args!("{}", self.tx_idle().bit())) + .field("rx_idle", &format_args!("{}", self.rx_idle().bit())) + .field("tx_ready", &format_args!("{}", self.tx_ready().bit())) + .field("data_ready", &format_args!("{}", self.data_ready().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Receive FIFO has at least one symbol"] #[inline(always)] #[must_use] - pub fn data_ready(&mut self) -> DATA_READY_W<0> { + pub fn data_ready(&mut self) -> DATA_READY_W { DATA_READY_W::new(self) } #[doc = "Bit 1 - Transmit FIFO has space for at least one symbol"] #[inline(always)] #[must_use] - pub fn tx_ready(&mut self) -> TX_READY_W<1> { + pub fn tx_ready(&mut self) -> TX_READY_W { TX_READY_W::new(self) } #[doc = "Bit 2 - Receiver is idle"] #[inline(always)] #[must_use] - pub fn rx_idle(&mut self) -> RX_IDLE_W<2> { + pub fn rx_idle(&mut self) -> RX_IDLE_W { RX_IDLE_W::new(self) } #[doc = "Bit 3 - Transmitter is idle"] #[inline(always)] #[must_use] - pub fn tx_idle(&mut self) -> TX_IDLE_W<3> { + pub fn tx_idle(&mut self) -> TX_IDLE_W { TX_IDLE_W::new(self) } #[doc = "Bit 4 - Receive FIFO overrun"] #[inline(always)] #[must_use] - pub fn rx_overrun(&mut self) -> RX_OVERRUN_W<4> { + pub fn rx_overrun(&mut self) -> RX_OVERRUN_W { RX_OVERRUN_W::new(self) } #[doc = "Bit 5 - Transmit FIFO is full"] #[inline(always)] #[must_use] - pub fn tx_full(&mut self) -> TX_FULL_W<5> { + pub fn tx_full(&mut self) -> TX_FULL_W { TX_FULL_W::new(self) } #[doc = "Bit 6 - RTS state"] #[inline(always)] #[must_use] - pub fn rts_status(&mut self) -> RTS_STATUS_W<6> { + pub fn rts_status(&mut self) -> RTS_STATUS_W { RTS_STATUS_W::new(self) } #[doc = "Bit 7 - CTS state"] #[inline(always)] #[must_use] - pub fn cts_status(&mut self) -> CTS_STATUS_W<7> { + pub fn cts_status(&mut self) -> CTS_STATUS_W { CTS_STATUS_W::new(self) } #[doc = "Bit 8 - Transmit FIFO is completely empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W<8> { + pub fn tx_empty(&mut self) -> TX_EMPTY_W { TX_EMPTY_W::new(self) } #[doc = "Bit 9 - Transmit FIFO is empty and transmitter is idle"] #[inline(always)] #[must_use] - pub fn tx_done(&mut self) -> TX_DONE_W<9> { + pub fn tx_done(&mut self) -> TX_DONE_W { TX_DONE_W::new(self) } #[doc = "Bits 16:19 - How many entries are filled in the RX FIFO"] #[inline(always)] #[must_use] - pub fn rx_fifo_level(&mut self) -> RX_FIFO_LEVEL_W<16> { + pub fn rx_fifo_level(&mut self) -> RX_FIFO_LEVEL_W { RX_FIFO_LEVEL_W::new(self) } #[doc = "Bits 24:27 - How many entries are filled in the TX FIFO"] #[inline(always)] #[must_use] - pub fn tx_fifo_level(&mut self) -> TX_FIFO_LEVEL_W<24> { + pub fn tx_fifo_level(&mut self) -> TX_FIFO_LEVEL_W { TX_FIFO_LEVEL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"] +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STAT_SPEC; impl crate::RegisterSpec for STAT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [stat::R](R) reader structure"] -impl crate::Readable for STAT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"] +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] impl crate::Writable for STAT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device.rs b/crates/bcm2835-lpa/src/usb_otg_device.rs index 8050e54..d432f5d 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - OTG_HS device configuration register"] pub dcfg: DCFG, @@ -107,63 +108,78 @@ pub struct RegisterBlock { #[doc = "0x460..0x478 - OUT Endpoint %s"] pub out_endpoint11: OUT_ENDPOINT, } -#[doc = "DCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "DCFG (rw) register accessor: OTG_HS device configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcfg`] +module"] pub type DCFG = crate::Reg; #[doc = "OTG_HS device configuration register"] pub mod dcfg; -#[doc = "DCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "DCTL (rw) register accessor: OTG_HS device control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dctl`] +module"] pub type DCTL = crate::Reg; #[doc = "OTG_HS device control register"] pub mod dctl; -#[doc = "DSTS (r) register accessor: an alias for `Reg`"] +#[doc = "DSTS (r) register accessor: OTG_HS device status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsts::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsts`] +module"] pub type DSTS = crate::Reg; #[doc = "OTG_HS device status register"] pub mod dsts; -#[doc = "DIEPMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPMSK (rw) register accessor: OTG_HS device IN endpoint common interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepmsk`] +module"] pub type DIEPMSK = crate::Reg; #[doc = "OTG_HS device IN endpoint common interrupt mask register"] pub mod diepmsk; -#[doc = "DOEPMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPMSK (rw) register accessor: OTG_HS device OUT endpoint common interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepmsk`] +module"] pub type DOEPMSK = crate::Reg; #[doc = "OTG_HS device OUT endpoint common interrupt mask register"] pub mod doepmsk; -#[doc = "DAINT (r) register accessor: an alias for `Reg`"] +#[doc = "DAINT (r) register accessor: OTG_HS device all endpoints interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daint::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daint`] +module"] pub type DAINT = crate::Reg; #[doc = "OTG_HS device all endpoints interrupt register"] pub mod daint; -#[doc = "DAINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DAINTMSK (rw) register accessor: OTG_HS all endpoints interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`daintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daintmsk`] +module"] pub type DAINTMSK = crate::Reg; #[doc = "OTG_HS all endpoints interrupt mask register"] pub mod daintmsk; -#[doc = "DVBUSDIS (rw) register accessor: an alias for `Reg`"] +#[doc = "DVBUSDIS (rw) register accessor: OTG_HS device VBUS discharge time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dvbusdis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dvbusdis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dvbusdis`] +module"] pub type DVBUSDIS = crate::Reg; #[doc = "OTG_HS device VBUS discharge time register"] pub mod dvbusdis; -#[doc = "DVBUSPULSE (rw) register accessor: an alias for `Reg`"] +#[doc = "DVBUSPULSE (rw) register accessor: OTG_HS device VBUS pulsing time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dvbuspulse::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dvbuspulse::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dvbuspulse`] +module"] pub type DVBUSPULSE = crate::Reg; #[doc = "OTG_HS device VBUS pulsing time register"] pub mod dvbuspulse; -#[doc = "DTHRCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "DTHRCTL (rw) register accessor: OTG_HS Device threshold control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dthrctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dthrctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dthrctl`] +module"] pub type DTHRCTL = crate::Reg; #[doc = "OTG_HS Device threshold control register"] pub mod dthrctl; -#[doc = "DIEPEMPMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPEMPMSK (rw) register accessor: OTG_HS device IN endpoint FIFO empty interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepempmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepempmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepempmsk`] +module"] pub type DIEPEMPMSK = crate::Reg; #[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register"] pub mod diepempmsk; -#[doc = "DEACHINT (rw) register accessor: an alias for `Reg`"] +#[doc = "DEACHINT (rw) register accessor: OTG_HS device each endpoint interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deachint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deachint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@deachint`] +module"] pub type DEACHINT = crate::Reg; #[doc = "OTG_HS device each endpoint interrupt register"] pub mod deachint; -#[doc = "DEACHINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DEACHINTMSK (rw) register accessor: OTG_HS device each endpoint interrupt register mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deachintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deachintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@deachintmsk`] +module"] pub type DEACHINTMSK = crate::Reg; #[doc = "OTG_HS device each endpoint interrupt register mask"] pub mod deachintmsk; -#[doc = "DIEPEACHMSK1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPEACHMSK1 (rw) register accessor: OTG_HS device each in endpoint-1 interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepeachmsk1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepeachmsk1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepeachmsk1`] +module"] pub type DIEPEACHMSK1 = crate::Reg; #[doc = "OTG_HS device each in endpoint-1 interrupt register"] pub mod diepeachmsk1; -#[doc = "DOEPEACHMSK1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPEACHMSK1 (rw) register accessor: OTG_HS device each OUT endpoint-1 interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepeachmsk1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepeachmsk1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepeachmsk1`] +module"] pub type DOEPEACHMSK1 = crate::Reg; #[doc = "OTG_HS device each OUT endpoint-1 interrupt register"] pub mod doepeachmsk1; diff --git a/crates/bcm2835-lpa/src/usb_otg_device/daint.rs b/crates/bcm2835-lpa/src/usb_otg_device/daint.rs index 14c25b3..3210b36 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/daint.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/daint.rs @@ -1,22 +1,9 @@ #[doc = "Register `DAINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `IEPINT` reader - IN endpoint interrupt bits"] -pub type IEPINT_R = crate::FieldReader; +pub type IEPINT_R = crate::FieldReader; #[doc = "Field `OEPINT` reader - OUT endpoint interrupt bits"] -pub type OEPINT_R = crate::FieldReader; +pub type OEPINT_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - IN endpoint interrupt bits"] #[inline(always)] @@ -29,15 +16,26 @@ impl R { OEPINT_R::new(((self.bits >> 16) & 0xffff) as u16) } } -#[doc = "OTG_HS device all endpoints interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daint](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAINT") + .field("iepint", &format_args!("{}", self.iepint().bits())) + .field("oepint", &format_args!("{}", self.oepint().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS device all endpoints interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daint::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DAINT_SPEC; impl crate::RegisterSpec for DAINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [daint::R](R) reader structure"] -impl crate::Readable for DAINT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`daint::R`](R) reader structure"] +impl crate::Readable for DAINT_SPEC {} #[doc = "`reset()` method sets DAINT to value 0"] impl crate::Resettable for DAINT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/usb_otg_device/daintmsk.rs b/crates/bcm2835-lpa/src/usb_otg_device/daintmsk.rs index bf7c858..44196aa 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/daintmsk.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/daintmsk.rs @@ -1,47 +1,15 @@ #[doc = "Register `DAINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DAINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IEPM` reader - IN EP interrupt mask bits"] -pub type IEPM_R = crate::FieldReader; +pub type IEPM_R = crate::FieldReader; #[doc = "Field `IEPM` writer - IN EP interrupt mask bits"] -pub type IEPM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DAINTMSK_SPEC, u16, u16, 16, O>; +pub type IEPM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `OEPM` reader - OUT EP interrupt mask bits"] -pub type OEPM_R = crate::FieldReader; +pub type OEPM_R = crate::FieldReader; #[doc = "Field `OEPM` writer - OUT EP interrupt mask bits"] -pub type OEPM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DAINTMSK_SPEC, u16, u16, 16, O>; +pub type OEPM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN EP interrupt mask bits"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { OEPM_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAINTMSK") + .field("iepm", &format_args!("{}", self.iepm().bits())) + .field("oepm", &format_args!("{}", self.oepm().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN EP interrupt mask bits"] #[inline(always)] #[must_use] - pub fn iepm(&mut self) -> IEPM_W<0> { + pub fn iepm(&mut self) -> IEPM_W { IEPM_W::new(self) } #[doc = "Bits 16:31 - OUT EP interrupt mask bits"] #[inline(always)] #[must_use] - pub fn oepm(&mut self) -> OEPM_W<16> { + pub fn oepm(&mut self) -> OEPM_W { OEPM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS all endpoints interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daintmsk](index.html) module"] +#[doc = "OTG_HS all endpoints interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`daintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DAINTMSK_SPEC; impl crate::RegisterSpec for DAINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [daintmsk::R](R) reader structure"] -impl crate::Readable for DAINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [daintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`daintmsk::R`](R) reader structure"] +impl crate::Readable for DAINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`daintmsk::W`](W) writer structure"] impl crate::Writable for DAINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/dcfg.rs b/crates/bcm2835-lpa/src/usb_otg_device/dcfg.rs index ad6ef16..fc2bbc8 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/dcfg.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/dcfg.rs @@ -1,59 +1,27 @@ #[doc = "Register `DCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DSPD` reader - Device speed"] -pub type DSPD_R = crate::FieldReader; +pub type DSPD_R = crate::FieldReader; #[doc = "Field `DSPD` writer - Device speed"] -pub type DSPD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +pub type DSPD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `NZLSOHSK` reader - Nonzero-length status OUT handshake"] -pub type NZLSOHSK_R = crate::BitReader; +pub type NZLSOHSK_R = crate::BitReader; #[doc = "Field `NZLSOHSK` writer - Nonzero-length status OUT handshake"] -pub type NZLSOHSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCFG_SPEC, bool, O>; +pub type NZLSOHSK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAD` reader - Device address"] -pub type DAD_R = crate::FieldReader; +pub type DAD_R = crate::FieldReader; #[doc = "Field `DAD` writer - Device address"] -pub type DAD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 7, O>; +pub type DAD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `PFIVL` reader - Periodic (micro)frame interval"] -pub type PFIVL_R = crate::FieldReader; +pub type PFIVL_R = crate::FieldReader; #[doc = "Field `PFIVL` writer - Periodic (micro)frame interval"] -pub type PFIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +pub type PFIVL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `PERSCHIVL` reader - Periodic scheduling interval"] -pub type PERSCHIVL_R = crate::FieldReader; +pub type PERSCHIVL_R = crate::FieldReader; #[doc = "Field `PERSCHIVL` writer - Periodic scheduling interval"] -pub type PERSCHIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +pub type PERSCHIVL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:1 - Device speed"] #[inline(always)] @@ -81,56 +49,73 @@ impl R { PERSCHIVL_R::new(((self.bits >> 24) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DCFG") + .field("dspd", &format_args!("{}", self.dspd().bits())) + .field("nzlsohsk", &format_args!("{}", self.nzlsohsk().bit())) + .field("dad", &format_args!("{}", self.dad().bits())) + .field("pfivl", &format_args!("{}", self.pfivl().bits())) + .field("perschivl", &format_args!("{}", self.perschivl().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Device speed"] #[inline(always)] #[must_use] - pub fn dspd(&mut self) -> DSPD_W<0> { + pub fn dspd(&mut self) -> DSPD_W { DSPD_W::new(self) } #[doc = "Bit 2 - Nonzero-length status OUT handshake"] #[inline(always)] #[must_use] - pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<2> { + pub fn nzlsohsk(&mut self) -> NZLSOHSK_W { NZLSOHSK_W::new(self) } #[doc = "Bits 4:10 - Device address"] #[inline(always)] #[must_use] - pub fn dad(&mut self) -> DAD_W<4> { + pub fn dad(&mut self) -> DAD_W { DAD_W::new(self) } #[doc = "Bits 11:12 - Periodic (micro)frame interval"] #[inline(always)] #[must_use] - pub fn pfivl(&mut self) -> PFIVL_W<11> { + pub fn pfivl(&mut self) -> PFIVL_W { PFIVL_W::new(self) } #[doc = "Bits 24:25 - Periodic scheduling interval"] #[inline(always)] #[must_use] - pub fn perschivl(&mut self) -> PERSCHIVL_W<24> { + pub fn perschivl(&mut self) -> PERSCHIVL_W { PERSCHIVL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +#[doc = "OTG_HS device configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DCFG_SPEC; impl crate::RegisterSpec for DCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dcfg::R](R) reader structure"] -impl crate::Readable for DCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`dcfg::R`](R) reader structure"] +impl crate::Readable for DCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dcfg::W`](W) writer structure"] impl crate::Writable for DCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/dctl.rs b/crates/bcm2835-lpa/src/usb_otg_device/dctl.rs index ed73ebd..42ffebd 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/dctl.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/dctl.rs @@ -1,67 +1,35 @@ #[doc = "Register `DCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RWUSIG` reader - Remote wakeup signaling"] -pub type RWUSIG_R = crate::BitReader; +pub type RWUSIG_R = crate::BitReader; #[doc = "Field `RWUSIG` writer - Remote wakeup signaling"] -pub type RWUSIG_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type RWUSIG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SDIS` reader - Soft disconnect"] -pub type SDIS_R = crate::BitReader; +pub type SDIS_R = crate::BitReader; #[doc = "Field `SDIS` writer - Soft disconnect"] -pub type SDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type SDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GINSTS` reader - Global IN NAK status"] -pub type GINSTS_R = crate::BitReader; +pub type GINSTS_R = crate::BitReader; #[doc = "Field `GONSTS` reader - Global OUT NAK status"] -pub type GONSTS_R = crate::BitReader; +pub type GONSTS_R = crate::BitReader; #[doc = "Field `TCTL` reader - Test control"] -pub type TCTL_R = crate::FieldReader; +pub type TCTL_R = crate::FieldReader; #[doc = "Field `TCTL` writer - Test control"] -pub type TCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCTL_SPEC, u8, u8, 3, O>; +pub type TCTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `SGINAK` writer - Set global IN NAK"] -pub type SGINAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type SGINAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CGINAK` writer - Clear global IN NAK"] -pub type CGINAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type CGINAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SGONAK` writer - Set global OUT NAK"] -pub type SGONAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type SGONAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CGONAK` writer - Clear global OUT NAK"] -pub type CGONAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type CGONAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POPRGDNE` reader - Power-on programming done"] -pub type POPRGDNE_R = crate::BitReader; +pub type POPRGDNE_R = crate::BitReader; #[doc = "Field `POPRGDNE` writer - Power-on programming done"] -pub type POPRGDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type POPRGDNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Remote wakeup signaling"] #[inline(always)] @@ -94,74 +62,92 @@ impl R { POPRGDNE_R::new(((self.bits >> 11) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DCTL") + .field("rwusig", &format_args!("{}", self.rwusig().bit())) + .field("sdis", &format_args!("{}", self.sdis().bit())) + .field("ginsts", &format_args!("{}", self.ginsts().bit())) + .field("gonsts", &format_args!("{}", self.gonsts().bit())) + .field("tctl", &format_args!("{}", self.tctl().bits())) + .field("poprgdne", &format_args!("{}", self.poprgdne().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Remote wakeup signaling"] #[inline(always)] #[must_use] - pub fn rwusig(&mut self) -> RWUSIG_W<0> { + pub fn rwusig(&mut self) -> RWUSIG_W { RWUSIG_W::new(self) } #[doc = "Bit 1 - Soft disconnect"] #[inline(always)] #[must_use] - pub fn sdis(&mut self) -> SDIS_W<1> { + pub fn sdis(&mut self) -> SDIS_W { SDIS_W::new(self) } #[doc = "Bits 4:6 - Test control"] #[inline(always)] #[must_use] - pub fn tctl(&mut self) -> TCTL_W<4> { + pub fn tctl(&mut self) -> TCTL_W { TCTL_W::new(self) } #[doc = "Bit 7 - Set global IN NAK"] #[inline(always)] #[must_use] - pub fn sginak(&mut self) -> SGINAK_W<7> { + pub fn sginak(&mut self) -> SGINAK_W { SGINAK_W::new(self) } #[doc = "Bit 8 - Clear global IN NAK"] #[inline(always)] #[must_use] - pub fn cginak(&mut self) -> CGINAK_W<8> { + pub fn cginak(&mut self) -> CGINAK_W { CGINAK_W::new(self) } #[doc = "Bit 9 - Set global OUT NAK"] #[inline(always)] #[must_use] - pub fn sgonak(&mut self) -> SGONAK_W<9> { + pub fn sgonak(&mut self) -> SGONAK_W { SGONAK_W::new(self) } #[doc = "Bit 10 - Clear global OUT NAK"] #[inline(always)] #[must_use] - pub fn cgonak(&mut self) -> CGONAK_W<10> { + pub fn cgonak(&mut self) -> CGONAK_W { CGONAK_W::new(self) } #[doc = "Bit 11 - Power-on programming done"] #[inline(always)] #[must_use] - pub fn poprgdne(&mut self) -> POPRGDNE_W<11> { + pub fn poprgdne(&mut self) -> POPRGDNE_W { POPRGDNE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dctl](index.html) module"] +#[doc = "OTG_HS device control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DCTL_SPEC; impl crate::RegisterSpec for DCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dctl::R](R) reader structure"] -impl crate::Readable for DCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dctl::W](W) writer structure"] +#[doc = "`read()` method returns [`dctl::R`](R) reader structure"] +impl crate::Readable for DCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dctl::W`](W) writer structure"] impl crate::Writable for DCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/deachint.rs b/crates/bcm2835-lpa/src/usb_otg_device/deachint.rs index b2e2a0b..f8f0c35 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/deachint.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/deachint.rs @@ -1,47 +1,15 @@ #[doc = "Register `DEACHINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEACHINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IEP1INT` reader - IN endpoint 1interrupt bit"] -pub type IEP1INT_R = crate::BitReader; +pub type IEP1INT_R = crate::BitReader; #[doc = "Field `IEP1INT` writer - IN endpoint 1interrupt bit"] -pub type IEP1INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINT_SPEC, bool, O>; +pub type IEP1INT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEP1INT` reader - OUT endpoint 1 interrupt bit"] -pub type OEP1INT_R = crate::BitReader; +pub type OEP1INT_R = crate::BitReader; #[doc = "Field `OEP1INT` writer - OUT endpoint 1 interrupt bit"] -pub type OEP1INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINT_SPEC, bool, O>; +pub type OEP1INT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - IN endpoint 1interrupt bit"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { OEP1INT_R::new(((self.bits >> 17) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEACHINT") + .field("iep1int", &format_args!("{}", self.iep1int().bit())) + .field("oep1int", &format_args!("{}", self.oep1int().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - IN endpoint 1interrupt bit"] #[inline(always)] #[must_use] - pub fn iep1int(&mut self) -> IEP1INT_W<1> { + pub fn iep1int(&mut self) -> IEP1INT_W { IEP1INT_W::new(self) } #[doc = "Bit 17 - OUT endpoint 1 interrupt bit"] #[inline(always)] #[must_use] - pub fn oep1int(&mut self) -> OEP1INT_W<17> { + pub fn oep1int(&mut self) -> OEP1INT_W { OEP1INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device each endpoint interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deachint](index.html) module"] +#[doc = "OTG_HS device each endpoint interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deachint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deachint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEACHINT_SPEC; impl crate::RegisterSpec for DEACHINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deachint::R](R) reader structure"] -impl crate::Readable for DEACHINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [deachint::W](W) writer structure"] +#[doc = "`read()` method returns [`deachint::R`](R) reader structure"] +impl crate::Readable for DEACHINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`deachint::W`](W) writer structure"] impl crate::Writable for DEACHINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/deachintmsk.rs b/crates/bcm2835-lpa/src/usb_otg_device/deachintmsk.rs index 635cecf..8979089 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/deachintmsk.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/deachintmsk.rs @@ -1,47 +1,15 @@ #[doc = "Register `DEACHINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEACHINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IEP1INTM` reader - IN Endpoint 1 interrupt mask bit"] -pub type IEP1INTM_R = crate::BitReader; +pub type IEP1INTM_R = crate::BitReader; #[doc = "Field `IEP1INTM` writer - IN Endpoint 1 interrupt mask bit"] -pub type IEP1INTM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINTMSK_SPEC, bool, O>; +pub type IEP1INTM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEP1INTM` reader - OUT Endpoint 1 interrupt mask bit"] -pub type OEP1INTM_R = crate::BitReader; +pub type OEP1INTM_R = crate::BitReader; #[doc = "Field `OEP1INTM` writer - OUT Endpoint 1 interrupt mask bit"] -pub type OEP1INTM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINTMSK_SPEC, bool, O>; +pub type OEP1INTM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - IN Endpoint 1 interrupt mask bit"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { OEP1INTM_R::new(((self.bits >> 17) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEACHINTMSK") + .field("iep1intm", &format_args!("{}", self.iep1intm().bit())) + .field("oep1intm", &format_args!("{}", self.oep1intm().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - IN Endpoint 1 interrupt mask bit"] #[inline(always)] #[must_use] - pub fn iep1intm(&mut self) -> IEP1INTM_W<1> { + pub fn iep1intm(&mut self) -> IEP1INTM_W { IEP1INTM_W::new(self) } #[doc = "Bit 17 - OUT Endpoint 1 interrupt mask bit"] #[inline(always)] #[must_use] - pub fn oep1intm(&mut self) -> OEP1INTM_W<17> { + pub fn oep1intm(&mut self) -> OEP1INTM_W { OEP1INTM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device each endpoint interrupt register mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deachintmsk](index.html) module"] +#[doc = "OTG_HS device each endpoint interrupt register mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deachintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deachintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEACHINTMSK_SPEC; impl crate::RegisterSpec for DEACHINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deachintmsk::R](R) reader structure"] -impl crate::Readable for DEACHINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [deachintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`deachintmsk::R`](R) reader structure"] +impl crate::Readable for DEACHINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`deachintmsk::W`](W) writer structure"] impl crate::Writable for DEACHINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/diepeachmsk1.rs b/crates/bcm2835-lpa/src/usb_otg_device/diepeachmsk1.rs index 6e00947..b6d85a8 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/diepeachmsk1.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/diepeachmsk1.rs @@ -1,75 +1,43 @@ #[doc = "Register `DIEPEACHMSK1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPEACHMSK1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] -pub type EPDM_R = crate::BitReader; +pub type EPDM_R = crate::BitReader; #[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] -pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type EPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOM` reader - Timeout condition mask (nonisochronous endpoints)"] -pub type TOM_R = crate::BitReader; +pub type TOM_R = crate::BitReader; #[doc = "Field `TOM` writer - Timeout condition mask (nonisochronous endpoints)"] -pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type TOM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_R = crate::BitReader; +pub type ITTXFEMSK_R = crate::BitReader; #[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type ITTXFEMSK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] -pub type INEPNMM_R = crate::BitReader; +pub type INEPNMM_R = crate::BitReader; #[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] -pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type INEPNMM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] -pub type INEPNEM_R = crate::BitReader; +pub type INEPNEM_R = crate::BitReader; #[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] -pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type INEPNEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFURM` reader - FIFO underrun mask"] -pub type TXFURM_R = crate::BitReader; +pub type TXFURM_R = crate::BitReader; #[doc = "Field `TXFURM` writer - FIFO underrun mask"] -pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type TXFURM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BIM` reader - BNA interrupt mask"] -pub type BIM_R = crate::BitReader; +pub type BIM_R = crate::BitReader; #[doc = "Field `BIM` writer - BNA interrupt mask"] -pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type BIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKM` reader - NAK interrupt mask"] -pub type NAKM_R = crate::BitReader; +pub type NAKM_R = crate::BitReader; #[doc = "Field `NAKM` writer - NAK interrupt mask"] -pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type NAKM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] @@ -117,80 +85,101 @@ impl R { NAKM_R::new(((self.bits >> 13) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPEACHMSK1") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("epdm", &format_args!("{}", self.epdm().bit())) + .field("tom", &format_args!("{}", self.tom().bit())) + .field("ittxfemsk", &format_args!("{}", self.ittxfemsk().bit())) + .field("inepnmm", &format_args!("{}", self.inepnmm().bit())) + .field("inepnem", &format_args!("{}", self.inepnem().bit())) + .field("txfurm", &format_args!("{}", self.txfurm().bit())) + .field("bim", &format_args!("{}", self.bim().bit())) + .field("nakm", &format_args!("{}", self.nakm().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt mask"] #[inline(always)] #[must_use] - pub fn epdm(&mut self) -> EPDM_W<1> { + pub fn epdm(&mut self) -> EPDM_W { EPDM_W::new(self) } #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] #[inline(always)] #[must_use] - pub fn tom(&mut self) -> TOM_W<3> { + pub fn tom(&mut self) -> TOM_W { TOM_W::new(self) } #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W { ITTXFEMSK_W::new(self) } #[doc = "Bit 5 - IN token received with EP mismatch mask"] #[inline(always)] #[must_use] - pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + pub fn inepnmm(&mut self) -> INEPNMM_W { INEPNMM_W::new(self) } #[doc = "Bit 6 - IN endpoint NAK effective mask"] #[inline(always)] #[must_use] - pub fn inepnem(&mut self) -> INEPNEM_W<6> { + pub fn inepnem(&mut self) -> INEPNEM_W { INEPNEM_W::new(self) } #[doc = "Bit 8 - FIFO underrun mask"] #[inline(always)] #[must_use] - pub fn txfurm(&mut self) -> TXFURM_W<8> { + pub fn txfurm(&mut self) -> TXFURM_W { TXFURM_W::new(self) } #[doc = "Bit 9 - BNA interrupt mask"] #[inline(always)] #[must_use] - pub fn bim(&mut self) -> BIM_W<9> { + pub fn bim(&mut self) -> BIM_W { BIM_W::new(self) } #[doc = "Bit 13 - NAK interrupt mask"] #[inline(always)] #[must_use] - pub fn nakm(&mut self) -> NAKM_W<13> { + pub fn nakm(&mut self) -> NAKM_W { NAKM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device each in endpoint-1 interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepeachmsk1](index.html) module"] +#[doc = "OTG_HS device each in endpoint-1 interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepeachmsk1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepeachmsk1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPEACHMSK1_SPEC; impl crate::RegisterSpec for DIEPEACHMSK1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepeachmsk1::R](R) reader structure"] -impl crate::Readable for DIEPEACHMSK1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepeachmsk1::W](W) writer structure"] +#[doc = "`read()` method returns [`diepeachmsk1::R`](R) reader structure"] +impl crate::Readable for DIEPEACHMSK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepeachmsk1::W`](W) writer structure"] impl crate::Writable for DIEPEACHMSK1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/diepempmsk.rs b/crates/bcm2835-lpa/src/usb_otg_device/diepempmsk.rs index 8e5b978..89831f3 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/diepempmsk.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/diepempmsk.rs @@ -1,44 +1,11 @@ #[doc = "Register `DIEPEMPMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPEMPMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXFEM` reader - IN EP Tx FIFO empty interrupt mask bits"] -pub type INEPTXFEM_R = crate::FieldReader; +pub type INEPTXFEM_R = crate::FieldReader; #[doc = "Field `INEPTXFEM` writer - IN EP Tx FIFO empty interrupt mask bits"] -pub type INEPTXFEM_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, DIEPEMPMSK_SPEC, u16, u16, 16, O>; +pub type INEPTXFEM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits"] #[inline(always)] @@ -46,32 +13,45 @@ impl R { INEPTXFEM_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPEMPMSK") + .field("ineptxfem", &format_args!("{}", self.ineptxfem().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits"] #[inline(always)] #[must_use] - pub fn ineptxfem(&mut self) -> INEPTXFEM_W<0> { + pub fn ineptxfem(&mut self) -> INEPTXFEM_W { INEPTXFEM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepempmsk](index.html) module"] +#[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepempmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepempmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPEMPMSK_SPEC; impl crate::RegisterSpec for DIEPEMPMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepempmsk::R](R) reader structure"] -impl crate::Readable for DIEPEMPMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepempmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`diepempmsk::R`](R) reader structure"] +impl crate::Readable for DIEPEMPMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepempmsk::W`](W) writer structure"] impl crate::Writable for DIEPEMPMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/diepmsk.rs b/crates/bcm2835-lpa/src/usb_otg_device/diepmsk.rs index 6411ce9..8bd397c 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/diepmsk.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/diepmsk.rs @@ -1,71 +1,39 @@ #[doc = "Register `DIEPMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] -pub type EPDM_R = crate::BitReader; +pub type EPDM_R = crate::BitReader; #[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] -pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type EPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOM` reader - Timeout condition mask (nonisochronous endpoints)"] -pub type TOM_R = crate::BitReader; +pub type TOM_R = crate::BitReader; #[doc = "Field `TOM` writer - Timeout condition mask (nonisochronous endpoints)"] -pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type TOM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_R = crate::BitReader; +pub type ITTXFEMSK_R = crate::BitReader; #[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type ITTXFEMSK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] -pub type INEPNMM_R = crate::BitReader; +pub type INEPNMM_R = crate::BitReader; #[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] -pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type INEPNMM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] -pub type INEPNEM_R = crate::BitReader; +pub type INEPNEM_R = crate::BitReader; #[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] -pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type INEPNEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFURM` reader - FIFO underrun mask"] -pub type TXFURM_R = crate::BitReader; +pub type TXFURM_R = crate::BitReader; #[doc = "Field `TXFURM` writer - FIFO underrun mask"] -pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type TXFURM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BIM` reader - BNA interrupt mask"] -pub type BIM_R = crate::BitReader; +pub type BIM_R = crate::BitReader; #[doc = "Field `BIM` writer - BNA interrupt mask"] -pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type BIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] @@ -108,74 +76,94 @@ impl R { BIM_R::new(((self.bits >> 9) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPMSK") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("epdm", &format_args!("{}", self.epdm().bit())) + .field("tom", &format_args!("{}", self.tom().bit())) + .field("ittxfemsk", &format_args!("{}", self.ittxfemsk().bit())) + .field("inepnmm", &format_args!("{}", self.inepnmm().bit())) + .field("inepnem", &format_args!("{}", self.inepnem().bit())) + .field("txfurm", &format_args!("{}", self.txfurm().bit())) + .field("bim", &format_args!("{}", self.bim().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt mask"] #[inline(always)] #[must_use] - pub fn epdm(&mut self) -> EPDM_W<1> { + pub fn epdm(&mut self) -> EPDM_W { EPDM_W::new(self) } #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] #[inline(always)] #[must_use] - pub fn tom(&mut self) -> TOM_W<3> { + pub fn tom(&mut self) -> TOM_W { TOM_W::new(self) } #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W { ITTXFEMSK_W::new(self) } #[doc = "Bit 5 - IN token received with EP mismatch mask"] #[inline(always)] #[must_use] - pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + pub fn inepnmm(&mut self) -> INEPNMM_W { INEPNMM_W::new(self) } #[doc = "Bit 6 - IN endpoint NAK effective mask"] #[inline(always)] #[must_use] - pub fn inepnem(&mut self) -> INEPNEM_W<6> { + pub fn inepnem(&mut self) -> INEPNEM_W { INEPNEM_W::new(self) } #[doc = "Bit 8 - FIFO underrun mask"] #[inline(always)] #[must_use] - pub fn txfurm(&mut self) -> TXFURM_W<8> { + pub fn txfurm(&mut self) -> TXFURM_W { TXFURM_W::new(self) } #[doc = "Bit 9 - BNA interrupt mask"] #[inline(always)] #[must_use] - pub fn bim(&mut self) -> BIM_W<9> { + pub fn bim(&mut self) -> BIM_W { BIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint common interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepmsk](index.html) module"] +#[doc = "OTG_HS device IN endpoint common interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPMSK_SPEC; impl crate::RegisterSpec for DIEPMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepmsk::R](R) reader structure"] -impl crate::Readable for DIEPMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`diepmsk::R`](R) reader structure"] +impl crate::Readable for DIEPMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepmsk::W`](W) writer structure"] impl crate::Writable for DIEPMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/doepeachmsk1.rs b/crates/bcm2835-lpa/src/usb_otg_device/doepeachmsk1.rs index 31a5ab1..7c60dcc 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/doepeachmsk1.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/doepeachmsk1.rs @@ -1,83 +1,51 @@ #[doc = "Register `DOEPEACHMSK1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPEACHMSK1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] -pub type EPDM_R = crate::BitReader; +pub type EPDM_R = crate::BitReader; #[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] -pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type EPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOM` reader - Timeout condition mask"] -pub type TOM_R = crate::BitReader; +pub type TOM_R = crate::BitReader; #[doc = "Field `TOM` writer - Timeout condition mask"] -pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type TOM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_R = crate::BitReader; +pub type ITTXFEMSK_R = crate::BitReader; #[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type ITTXFEMSK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] -pub type INEPNMM_R = crate::BitReader; +pub type INEPNMM_R = crate::BitReader; #[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] -pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type INEPNMM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] -pub type INEPNEM_R = crate::BitReader; +pub type INEPNEM_R = crate::BitReader; #[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] -pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type INEPNEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFURM` reader - OUT packet error mask"] -pub type TXFURM_R = crate::BitReader; +pub type TXFURM_R = crate::BitReader; #[doc = "Field `TXFURM` writer - OUT packet error mask"] -pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type TXFURM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BIM` reader - BNA interrupt mask"] -pub type BIM_R = crate::BitReader; +pub type BIM_R = crate::BitReader; #[doc = "Field `BIM` writer - BNA interrupt mask"] -pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type BIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BERRM` reader - Bubble error interrupt mask"] -pub type BERRM_R = crate::BitReader; +pub type BERRM_R = crate::BitReader; #[doc = "Field `BERRM` writer - Bubble error interrupt mask"] -pub type BERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type BERRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKM` reader - NAK interrupt mask"] -pub type NAKM_R = crate::BitReader; +pub type NAKM_R = crate::BitReader; #[doc = "Field `NAKM` writer - NAK interrupt mask"] -pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type NAKM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYETM` reader - NYET interrupt mask"] -pub type NYETM_R = crate::BitReader; +pub type NYETM_R = crate::BitReader; #[doc = "Field `NYETM` writer - NYET interrupt mask"] -pub type NYETM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type NYETM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] @@ -135,92 +103,115 @@ impl R { NYETM_R::new(((self.bits >> 14) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPEACHMSK1") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("epdm", &format_args!("{}", self.epdm().bit())) + .field("tom", &format_args!("{}", self.tom().bit())) + .field("ittxfemsk", &format_args!("{}", self.ittxfemsk().bit())) + .field("inepnmm", &format_args!("{}", self.inepnmm().bit())) + .field("inepnem", &format_args!("{}", self.inepnem().bit())) + .field("txfurm", &format_args!("{}", self.txfurm().bit())) + .field("bim", &format_args!("{}", self.bim().bit())) + .field("berrm", &format_args!("{}", self.berrm().bit())) + .field("nakm", &format_args!("{}", self.nakm().bit())) + .field("nyetm", &format_args!("{}", self.nyetm().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt mask"] #[inline(always)] #[must_use] - pub fn epdm(&mut self) -> EPDM_W<1> { + pub fn epdm(&mut self) -> EPDM_W { EPDM_W::new(self) } #[doc = "Bit 3 - Timeout condition mask"] #[inline(always)] #[must_use] - pub fn tom(&mut self) -> TOM_W<3> { + pub fn tom(&mut self) -> TOM_W { TOM_W::new(self) } #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W { ITTXFEMSK_W::new(self) } #[doc = "Bit 5 - IN token received with EP mismatch mask"] #[inline(always)] #[must_use] - pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + pub fn inepnmm(&mut self) -> INEPNMM_W { INEPNMM_W::new(self) } #[doc = "Bit 6 - IN endpoint NAK effective mask"] #[inline(always)] #[must_use] - pub fn inepnem(&mut self) -> INEPNEM_W<6> { + pub fn inepnem(&mut self) -> INEPNEM_W { INEPNEM_W::new(self) } #[doc = "Bit 8 - OUT packet error mask"] #[inline(always)] #[must_use] - pub fn txfurm(&mut self) -> TXFURM_W<8> { + pub fn txfurm(&mut self) -> TXFURM_W { TXFURM_W::new(self) } #[doc = "Bit 9 - BNA interrupt mask"] #[inline(always)] #[must_use] - pub fn bim(&mut self) -> BIM_W<9> { + pub fn bim(&mut self) -> BIM_W { BIM_W::new(self) } #[doc = "Bit 12 - Bubble error interrupt mask"] #[inline(always)] #[must_use] - pub fn berrm(&mut self) -> BERRM_W<12> { + pub fn berrm(&mut self) -> BERRM_W { BERRM_W::new(self) } #[doc = "Bit 13 - NAK interrupt mask"] #[inline(always)] #[must_use] - pub fn nakm(&mut self) -> NAKM_W<13> { + pub fn nakm(&mut self) -> NAKM_W { NAKM_W::new(self) } #[doc = "Bit 14 - NYET interrupt mask"] #[inline(always)] #[must_use] - pub fn nyetm(&mut self) -> NYETM_W<14> { + pub fn nyetm(&mut self) -> NYETM_W { NYETM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device each OUT endpoint-1 interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepeachmsk1](index.html) module"] +#[doc = "OTG_HS device each OUT endpoint-1 interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepeachmsk1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepeachmsk1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPEACHMSK1_SPEC; impl crate::RegisterSpec for DOEPEACHMSK1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepeachmsk1::R](R) reader structure"] -impl crate::Readable for DOEPEACHMSK1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepeachmsk1::W](W) writer structure"] +#[doc = "`read()` method returns [`doepeachmsk1::R`](R) reader structure"] +impl crate::Readable for DOEPEACHMSK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepeachmsk1::W`](W) writer structure"] impl crate::Writable for DOEPEACHMSK1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/doepmsk.rs b/crates/bcm2835-lpa/src/usb_otg_device/doepmsk.rs index 46e5ca8..dbed437 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/doepmsk.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/doepmsk.rs @@ -1,67 +1,35 @@ #[doc = "Register `DOEPMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] -pub type EPDM_R = crate::BitReader; +pub type EPDM_R = crate::BitReader; #[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] -pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type EPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STUPM` reader - SETUP phase done mask"] -pub type STUPM_R = crate::BitReader; +pub type STUPM_R = crate::BitReader; #[doc = "Field `STUPM` writer - SETUP phase done mask"] -pub type STUPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type STUPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OTEPDM` reader - OUT token received when endpoint disabled mask"] -pub type OTEPDM_R = crate::BitReader; +pub type OTEPDM_R = crate::BitReader; #[doc = "Field `OTEPDM` writer - OUT token received when endpoint disabled mask"] -pub type OTEPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type OTEPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `B2BSTUP` reader - Back-to-back SETUP packets received mask"] -pub type B2BSTUP_R = crate::BitReader; +pub type B2BSTUP_R = crate::BitReader; #[doc = "Field `B2BSTUP` writer - Back-to-back SETUP packets received mask"] -pub type B2BSTUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type B2BSTUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OPEM` reader - OUT packet error mask"] -pub type OPEM_R = crate::BitReader; +pub type OPEM_R = crate::BitReader; #[doc = "Field `OPEM` writer - OUT packet error mask"] -pub type OPEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type OPEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOIM` reader - BNA interrupt mask"] -pub type BOIM_R = crate::BitReader; +pub type BOIM_R = crate::BitReader; #[doc = "Field `BOIM` writer - BNA interrupt mask"] -pub type BOIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type BOIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] @@ -99,68 +67,87 @@ impl R { BOIM_R::new(((self.bits >> 9) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPMSK") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("epdm", &format_args!("{}", self.epdm().bit())) + .field("stupm", &format_args!("{}", self.stupm().bit())) + .field("otepdm", &format_args!("{}", self.otepdm().bit())) + .field("b2bstup", &format_args!("{}", self.b2bstup().bit())) + .field("opem", &format_args!("{}", self.opem().bit())) + .field("boim", &format_args!("{}", self.boim().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt mask"] #[inline(always)] #[must_use] - pub fn epdm(&mut self) -> EPDM_W<1> { + pub fn epdm(&mut self) -> EPDM_W { EPDM_W::new(self) } #[doc = "Bit 3 - SETUP phase done mask"] #[inline(always)] #[must_use] - pub fn stupm(&mut self) -> STUPM_W<3> { + pub fn stupm(&mut self) -> STUPM_W { STUPM_W::new(self) } #[doc = "Bit 4 - OUT token received when endpoint disabled mask"] #[inline(always)] #[must_use] - pub fn otepdm(&mut self) -> OTEPDM_W<4> { + pub fn otepdm(&mut self) -> OTEPDM_W { OTEPDM_W::new(self) } #[doc = "Bit 6 - Back-to-back SETUP packets received mask"] #[inline(always)] #[must_use] - pub fn b2bstup(&mut self) -> B2BSTUP_W<6> { + pub fn b2bstup(&mut self) -> B2BSTUP_W { B2BSTUP_W::new(self) } #[doc = "Bit 8 - OUT packet error mask"] #[inline(always)] #[must_use] - pub fn opem(&mut self) -> OPEM_W<8> { + pub fn opem(&mut self) -> OPEM_W { OPEM_W::new(self) } #[doc = "Bit 9 - BNA interrupt mask"] #[inline(always)] #[must_use] - pub fn boim(&mut self) -> BOIM_W<9> { + pub fn boim(&mut self) -> BOIM_W { BOIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device OUT endpoint common interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepmsk](index.html) module"] +#[doc = "OTG_HS device OUT endpoint common interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPMSK_SPEC; impl crate::RegisterSpec for DOEPMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepmsk::R](R) reader structure"] -impl crate::Readable for DOEPMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`doepmsk::R`](R) reader structure"] +impl crate::Readable for DOEPMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepmsk::W`](W) writer structure"] impl crate::Writable for DOEPMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/dsts.rs b/crates/bcm2835-lpa/src/usb_otg_device/dsts.rs index ddf0900..3d4bf4f 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/dsts.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/dsts.rs @@ -1,26 +1,13 @@ #[doc = "Register `DSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SUSPSTS` reader - Suspend status"] -pub type SUSPSTS_R = crate::BitReader; +pub type SUSPSTS_R = crate::BitReader; #[doc = "Field `ENUMSPD` reader - Enumerated speed"] -pub type ENUMSPD_R = crate::FieldReader; +pub type ENUMSPD_R = crate::FieldReader; #[doc = "Field `EERR` reader - Erratic error"] -pub type EERR_R = crate::BitReader; +pub type EERR_R = crate::BitReader; #[doc = "Field `FNSOF` reader - Frame number of the received SOF"] -pub type FNSOF_R = crate::FieldReader; +pub type FNSOF_R = crate::FieldReader; impl R { #[doc = "Bit 0 - Suspend status"] #[inline(always)] @@ -43,15 +30,28 @@ impl R { FNSOF_R::new(((self.bits >> 8) & 0x3fff) as u16) } } -#[doc = "OTG_HS device status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dsts](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSTS") + .field("suspsts", &format_args!("{}", self.suspsts().bit())) + .field("enumspd", &format_args!("{}", self.enumspd().bits())) + .field("eerr", &format_args!("{}", self.eerr().bit())) + .field("fnsof", &format_args!("{}", self.fnsof().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS device status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsts::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DSTS_SPEC; impl crate::RegisterSpec for DSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dsts::R](R) reader structure"] -impl crate::Readable for DSTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`dsts::R`](R) reader structure"] +impl crate::Readable for DSTS_SPEC {} #[doc = "`reset()` method sets DSTS to value 0x10"] impl crate::Resettable for DSTS_SPEC { const RESET_VALUE: Self::Ux = 0x10; diff --git a/crates/bcm2835-lpa/src/usb_otg_device/dthrctl.rs b/crates/bcm2835-lpa/src/usb_otg_device/dthrctl.rs index ea85092..5044505 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/dthrctl.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/dthrctl.rs @@ -1,63 +1,31 @@ #[doc = "Register `DTHRCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DTHRCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NONISOTHREN` reader - Nonisochronous IN endpoints threshold enable"] -pub type NONISOTHREN_R = crate::BitReader; +pub type NONISOTHREN_R = crate::BitReader; #[doc = "Field `NONISOTHREN` writer - Nonisochronous IN endpoints threshold enable"] -pub type NONISOTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +pub type NONISOTHREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISOTHREN` reader - ISO IN endpoint threshold enable"] -pub type ISOTHREN_R = crate::BitReader; +pub type ISOTHREN_R = crate::BitReader; #[doc = "Field `ISOTHREN` writer - ISO IN endpoint threshold enable"] -pub type ISOTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +pub type ISOTHREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXTHRLEN` reader - Transmit threshold length"] -pub type TXTHRLEN_R = crate::FieldReader; +pub type TXTHRLEN_R = crate::FieldReader; #[doc = "Field `TXTHRLEN` writer - Transmit threshold length"] -pub type TXTHRLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DTHRCTL_SPEC, u16, u16, 9, O>; +pub type TXTHRLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 9, O, u16>; #[doc = "Field `RXTHREN` reader - Receive threshold enable"] -pub type RXTHREN_R = crate::BitReader; +pub type RXTHREN_R = crate::BitReader; #[doc = "Field `RXTHREN` writer - Receive threshold enable"] -pub type RXTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +pub type RXTHREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXTHRLEN` reader - Receive threshold length"] -pub type RXTHRLEN_R = crate::FieldReader; +pub type RXTHRLEN_R = crate::FieldReader; #[doc = "Field `RXTHRLEN` writer - Receive threshold length"] -pub type RXTHRLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DTHRCTL_SPEC, u16, u16, 9, O>; +pub type RXTHRLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 9, O, u16>; #[doc = "Field `ARPEN` reader - Arbiter parking enable"] -pub type ARPEN_R = crate::BitReader; +pub type ARPEN_R = crate::BitReader; #[doc = "Field `ARPEN` writer - Arbiter parking enable"] -pub type ARPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +pub type ARPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Nonisochronous IN endpoints threshold enable"] #[inline(always)] @@ -90,62 +58,80 @@ impl R { ARPEN_R::new(((self.bits >> 27) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DTHRCTL") + .field("nonisothren", &format_args!("{}", self.nonisothren().bit())) + .field("isothren", &format_args!("{}", self.isothren().bit())) + .field("txthrlen", &format_args!("{}", self.txthrlen().bits())) + .field("rxthren", &format_args!("{}", self.rxthren().bit())) + .field("rxthrlen", &format_args!("{}", self.rxthrlen().bits())) + .field("arpen", &format_args!("{}", self.arpen().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Nonisochronous IN endpoints threshold enable"] #[inline(always)] #[must_use] - pub fn nonisothren(&mut self) -> NONISOTHREN_W<0> { + pub fn nonisothren(&mut self) -> NONISOTHREN_W { NONISOTHREN_W::new(self) } #[doc = "Bit 1 - ISO IN endpoint threshold enable"] #[inline(always)] #[must_use] - pub fn isothren(&mut self) -> ISOTHREN_W<1> { + pub fn isothren(&mut self) -> ISOTHREN_W { ISOTHREN_W::new(self) } #[doc = "Bits 2:10 - Transmit threshold length"] #[inline(always)] #[must_use] - pub fn txthrlen(&mut self) -> TXTHRLEN_W<2> { + pub fn txthrlen(&mut self) -> TXTHRLEN_W { TXTHRLEN_W::new(self) } #[doc = "Bit 16 - Receive threshold enable"] #[inline(always)] #[must_use] - pub fn rxthren(&mut self) -> RXTHREN_W<16> { + pub fn rxthren(&mut self) -> RXTHREN_W { RXTHREN_W::new(self) } #[doc = "Bits 17:25 - Receive threshold length"] #[inline(always)] #[must_use] - pub fn rxthrlen(&mut self) -> RXTHRLEN_W<17> { + pub fn rxthrlen(&mut self) -> RXTHRLEN_W { RXTHRLEN_W::new(self) } #[doc = "Bit 27 - Arbiter parking enable"] #[inline(always)] #[must_use] - pub fn arpen(&mut self) -> ARPEN_W<27> { + pub fn arpen(&mut self) -> ARPEN_W { ARPEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS Device threshold control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dthrctl](index.html) module"] +#[doc = "OTG_HS Device threshold control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dthrctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dthrctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DTHRCTL_SPEC; impl crate::RegisterSpec for DTHRCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dthrctl::R](R) reader structure"] -impl crate::Readable for DTHRCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dthrctl::W](W) writer structure"] +#[doc = "`read()` method returns [`dthrctl::R`](R) reader structure"] +impl crate::Readable for DTHRCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dthrctl::W`](W) writer structure"] impl crate::Writable for DTHRCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/dvbusdis.rs b/crates/bcm2835-lpa/src/usb_otg_device/dvbusdis.rs index 403e00a..06b297e 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/dvbusdis.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/dvbusdis.rs @@ -1,43 +1,11 @@ #[doc = "Register `DVBUSDIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DVBUSDIS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VBUSDT` reader - Device VBUS discharge time"] -pub type VBUSDT_R = crate::FieldReader; +pub type VBUSDT_R = crate::FieldReader; #[doc = "Field `VBUSDT` writer - Device VBUS discharge time"] -pub type VBUSDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DVBUSDIS_SPEC, u16, u16, 16, O>; +pub type VBUSDT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Device VBUS discharge time"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { VBUSDT_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DVBUSDIS") + .field("vbusdt", &format_args!("{}", self.vbusdt().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Device VBUS discharge time"] #[inline(always)] #[must_use] - pub fn vbusdt(&mut self) -> VBUSDT_W<0> { + pub fn vbusdt(&mut self) -> VBUSDT_W { VBUSDT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device VBUS discharge time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbusdis](index.html) module"] +#[doc = "OTG_HS device VBUS discharge time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dvbusdis::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dvbusdis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DVBUSDIS_SPEC; impl crate::RegisterSpec for DVBUSDIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dvbusdis::R](R) reader structure"] -impl crate::Readable for DVBUSDIS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dvbusdis::W](W) writer structure"] +#[doc = "`read()` method returns [`dvbusdis::R`](R) reader structure"] +impl crate::Readable for DVBUSDIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dvbusdis::W`](W) writer structure"] impl crate::Writable for DVBUSDIS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/dvbuspulse.rs b/crates/bcm2835-lpa/src/usb_otg_device/dvbuspulse.rs index 4871f7b..52acecf 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/dvbuspulse.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/dvbuspulse.rs @@ -1,43 +1,11 @@ #[doc = "Register `DVBUSPULSE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DVBUSPULSE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DVBUSP` reader - Device VBUS pulsing time"] -pub type DVBUSP_R = crate::FieldReader; +pub type DVBUSP_R = crate::FieldReader; #[doc = "Field `DVBUSP` writer - Device VBUS pulsing time"] -pub type DVBUSP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DVBUSPULSE_SPEC, u16, u16, 12, O>; +pub type DVBUSP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; impl R { #[doc = "Bits 0:11 - Device VBUS pulsing time"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DVBUSP_R::new((self.bits & 0x0fff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DVBUSPULSE") + .field("dvbusp", &format_args!("{}", self.dvbusp().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:11 - Device VBUS pulsing time"] #[inline(always)] #[must_use] - pub fn dvbusp(&mut self) -> DVBUSP_W<0> { + pub fn dvbusp(&mut self) -> DVBUSP_W { DVBUSP_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device VBUS pulsing time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbuspulse](index.html) module"] +#[doc = "OTG_HS device VBUS pulsing time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dvbuspulse::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dvbuspulse::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DVBUSPULSE_SPEC; impl crate::RegisterSpec for DVBUSPULSE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dvbuspulse::R](R) reader structure"] -impl crate::Readable for DVBUSPULSE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dvbuspulse::W](W) writer structure"] +#[doc = "`read()` method returns [`dvbuspulse::R`](R) reader structure"] +impl crate::Readable for DVBUSPULSE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dvbuspulse::W`](W) writer structure"] impl crate::Writable for DVBUSPULSE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint.rs b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint.rs index 5fd5349..0e94feb 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct IN_ENDPOINT { #[doc = "0x00 - Control"] pub diepctl0: DIEPCTL0, @@ -14,23 +15,28 @@ pub struct IN_ENDPOINT { #[doc = "0x18 - Transmit FIFO status"] pub dtxfsts: DTXFSTS, } -#[doc = "DIEPCTL0 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPCTL0 (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepctl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepctl0`] +module"] pub type DIEPCTL0 = crate::Reg; #[doc = "Control"] pub mod diepctl0; -#[doc = "DIEPINT (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPINT (rw) register accessor: Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepint`] +module"] pub type DIEPINT = crate::Reg; #[doc = "Interrupt"] pub mod diepint; -#[doc = "DIEPTSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTSIZ (rw) register accessor: Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptsiz`] +module"] pub type DIEPTSIZ = crate::Reg; #[doc = "Transfer size"] pub mod dieptsiz; -#[doc = "DIEPDMA (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPDMA (rw) register accessor: DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepdma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepdma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepdma`] +module"] pub type DIEPDMA = crate::Reg; #[doc = "DMA address"] pub mod diepdma; -#[doc = "DTXFSTS (r) register accessor: an alias for `Reg`"] +#[doc = "DTXFSTS (r) register accessor: Transmit FIFO status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtxfsts::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtxfsts`] +module"] pub type DTXFSTS = crate::Reg; #[doc = "Transmit FIFO status"] pub mod dtxfsts; diff --git a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs index b8fa051..899b0d7 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs @@ -1,79 +1,47 @@ #[doc = "Register `DIEPCTL0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPCTL0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MPSIZ` reader - Maximum packet size"] -pub type MPSIZ_R = crate::FieldReader; +pub type MPSIZ_R = crate::FieldReader; #[doc = "Field `MPSIZ` writer - Maximum packet size"] -pub type MPSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u16, u16, 11, O>; +pub type MPSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 11, O, u16>; #[doc = "Field `USBAEP` reader - USB active endpoint"] -pub type USBAEP_R = crate::BitReader; +pub type USBAEP_R = crate::BitReader; #[doc = "Field `USBAEP` writer - USB active endpoint"] -pub type USBAEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type USBAEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EONUM_DPID` reader - Even/odd frame"] -pub type EONUM_DPID_R = crate::BitReader; +pub type EONUM_DPID_R = crate::BitReader; #[doc = "Field `NAKSTS` reader - NAK status"] -pub type NAKSTS_R = crate::BitReader; +pub type NAKSTS_R = crate::BitReader; #[doc = "Field `EPTYP` reader - Endpoint type"] -pub type EPTYP_R = crate::FieldReader; +pub type EPTYP_R = crate::FieldReader; #[doc = "Field `EPTYP` writer - Endpoint type"] -pub type EPTYP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u8, u8, 2, O>; +pub type EPTYP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `Stall` reader - STALL handshake"] -pub type STALL_R = crate::BitReader; +pub type STALL_R = crate::BitReader; #[doc = "Field `Stall` writer - STALL handshake"] -pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFNUM` reader - TxFIFO number"] -pub type TXFNUM_R = crate::FieldReader; +pub type TXFNUM_R = crate::FieldReader; #[doc = "Field `TXFNUM` writer - TxFIFO number"] -pub type TXFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u8, u8, 4, O>; +pub type TXFNUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CNAK` writer - Clear NAK"] -pub type CNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type CNAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SNAK` writer - Set NAK"] -pub type SNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type SNAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SD0PID_SEVNFRM` writer - Set DATA0 PID"] -pub type SD0PID_SEVNFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type SD0PID_SEVNFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SODDFRM` writer - Set odd frame"] -pub type SODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type SODDFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDIS` reader - Endpoint disable"] -pub type EPDIS_R = crate::BitReader; +pub type EPDIS_R = crate::BitReader; #[doc = "Field `EPDIS` writer - Endpoint disable"] -pub type EPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type EPDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPENA` reader - Endpoint enable"] -pub type EPENA_R = crate::BitReader; +pub type EPENA_R = crate::BitReader; #[doc = "Field `EPENA` writer - Endpoint enable"] -pub type EPENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type EPENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] @@ -121,92 +89,113 @@ impl R { EPENA_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPCTL0") + .field("mpsiz", &format_args!("{}", self.mpsiz().bits())) + .field("usbaep", &format_args!("{}", self.usbaep().bit())) + .field("eonum_dpid", &format_args!("{}", self.eonum_dpid().bit())) + .field("naksts", &format_args!("{}", self.naksts().bit())) + .field("eptyp", &format_args!("{}", self.eptyp().bits())) + .field("stall", &format_args!("{}", self.stall().bit())) + .field("txfnum", &format_args!("{}", self.txfnum().bits())) + .field("epdis", &format_args!("{}", self.epdis().bit())) + .field("epena", &format_args!("{}", self.epena().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] #[must_use] - pub fn mpsiz(&mut self) -> MPSIZ_W<0> { + pub fn mpsiz(&mut self) -> MPSIZ_W { MPSIZ_W::new(self) } #[doc = "Bit 15 - USB active endpoint"] #[inline(always)] #[must_use] - pub fn usbaep(&mut self) -> USBAEP_W<15> { + pub fn usbaep(&mut self) -> USBAEP_W { USBAEP_W::new(self) } #[doc = "Bits 18:19 - Endpoint type"] #[inline(always)] #[must_use] - pub fn eptyp(&mut self) -> EPTYP_W<18> { + pub fn eptyp(&mut self) -> EPTYP_W { EPTYP_W::new(self) } #[doc = "Bit 21 - STALL handshake"] #[inline(always)] #[must_use] - pub fn stall(&mut self) -> STALL_W<21> { + pub fn stall(&mut self) -> STALL_W { STALL_W::new(self) } #[doc = "Bits 22:25 - TxFIFO number"] #[inline(always)] #[must_use] - pub fn txfnum(&mut self) -> TXFNUM_W<22> { + pub fn txfnum(&mut self) -> TXFNUM_W { TXFNUM_W::new(self) } #[doc = "Bit 26 - Clear NAK"] #[inline(always)] #[must_use] - pub fn cnak(&mut self) -> CNAK_W<26> { + pub fn cnak(&mut self) -> CNAK_W { CNAK_W::new(self) } #[doc = "Bit 27 - Set NAK"] #[inline(always)] #[must_use] - pub fn snak(&mut self) -> SNAK_W<27> { + pub fn snak(&mut self) -> SNAK_W { SNAK_W::new(self) } #[doc = "Bit 28 - Set DATA0 PID"] #[inline(always)] #[must_use] - pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<28> { + pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W { SD0PID_SEVNFRM_W::new(self) } #[doc = "Bit 29 - Set odd frame"] #[inline(always)] #[must_use] - pub fn soddfrm(&mut self) -> SODDFRM_W<29> { + pub fn soddfrm(&mut self) -> SODDFRM_W { SODDFRM_W::new(self) } #[doc = "Bit 30 - Endpoint disable"] #[inline(always)] #[must_use] - pub fn epdis(&mut self) -> EPDIS_W<30> { + pub fn epdis(&mut self) -> EPDIS_W { EPDIS_W::new(self) } #[doc = "Bit 31 - Endpoint enable"] #[inline(always)] #[must_use] - pub fn epena(&mut self) -> EPENA_W<31> { + pub fn epena(&mut self) -> EPENA_W { EPENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepctl0](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPCTL0_SPEC; impl crate::RegisterSpec for DIEPCTL0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepctl0::R](R) reader structure"] -impl crate::Readable for DIEPCTL0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepctl0::W](W) writer structure"] +#[doc = "`read()` method returns [`diepctl0::R`](R) reader structure"] +impl crate::Readable for DIEPCTL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepctl0::W`](W) writer structure"] impl crate::Writable for DIEPCTL0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepdma.rs b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepdma.rs index 321905e..18f13ad 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepdma.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepdma.rs @@ -1,43 +1,11 @@ #[doc = "Register `DIEPDMA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPDMA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMAADDR` reader - DMA address"] -pub type DMAADDR_R = crate::FieldReader; +pub type DMAADDR_R = crate::FieldReader; #[doc = "Field `DMAADDR` writer - DMA address"] -pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPDMA_SPEC, u32, u32, 32, O>; +pub type DMAADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DMAADDR_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPDMA") + .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] #[must_use] - pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + pub fn dmaaddr(&mut self) -> DMAADDR_W { DMAADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepdma](index.html) module"] +#[doc = "DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepdma::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepdma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPDMA_SPEC; impl crate::RegisterSpec for DIEPDMA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepdma::R](R) reader structure"] -impl crate::Readable for DIEPDMA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepdma::W](W) writer structure"] +#[doc = "`read()` method returns [`diepdma::R`](R) reader structure"] +impl crate::Readable for DIEPDMA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepdma::W`](W) writer structure"] impl crate::Writable for DIEPDMA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepint.rs b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepint.rs index f85ca85..bd21aa2 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepint.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/diepint.rs @@ -1,81 +1,49 @@ #[doc = "Register `DIEPINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRC` reader - Transfer completed interrupt"] -pub type XFRC_R = crate::BitReader; +pub type XFRC_R = crate::BitReader; #[doc = "Field `XFRC` writer - Transfer completed interrupt"] -pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type XFRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISD` reader - Endpoint disabled interrupt"] -pub type EPDISD_R = crate::BitReader; +pub type EPDISD_R = crate::BitReader; #[doc = "Field `EPDISD` writer - Endpoint disabled interrupt"] -pub type EPDISD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type EPDISD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOC` reader - Timeout condition"] -pub type TOC_R = crate::BitReader; +pub type TOC_R = crate::BitReader; #[doc = "Field `TOC` writer - Timeout condition"] -pub type TOC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type TOC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITTXFE` reader - IN token received when TxFIFO is empty"] -pub type ITTXFE_R = crate::BitReader; +pub type ITTXFE_R = crate::BitReader; #[doc = "Field `ITTXFE` writer - IN token received when TxFIFO is empty"] -pub type ITTXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type ITTXFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNE` reader - IN endpoint NAK effective"] -pub type INEPNE_R = crate::BitReader; +pub type INEPNE_R = crate::BitReader; #[doc = "Field `INEPNE` writer - IN endpoint NAK effective"] -pub type INEPNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type INEPNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFE` reader - Transmit FIFO empty"] -pub type TXFE_R = crate::BitReader; +pub type TXFE_R = crate::BitReader; #[doc = "Field `TXFIFOUDRN` reader - Transmit Fifo Underrun"] -pub type TXFIFOUDRN_R = crate::BitReader; +pub type TXFIFOUDRN_R = crate::BitReader; #[doc = "Field `TXFIFOUDRN` writer - Transmit Fifo Underrun"] -pub type TXFIFOUDRN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type TXFIFOUDRN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BNA` reader - Buffer not available interrupt"] -pub type BNA_R = crate::BitReader; +pub type BNA_R = crate::BitReader; #[doc = "Field `BNA` writer - Buffer not available interrupt"] -pub type BNA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type BNA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PKTDRPSTS` reader - Packet dropped status"] -pub type PKTDRPSTS_R = crate::BitReader; +pub type PKTDRPSTS_R = crate::BitReader; #[doc = "Field `PKTDRPSTS` writer - Packet dropped status"] -pub type PKTDRPSTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type PKTDRPSTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BERR` reader - Babble error interrupt"] -pub type BERR_R = crate::BitReader; +pub type BERR_R = crate::BitReader; #[doc = "Field `BERR` writer - Babble error interrupt"] -pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type BERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAK` reader - NAK interrupt"] -pub type NAK_R = crate::BitReader; +pub type NAK_R = crate::BitReader; #[doc = "Field `NAK` writer - NAK interrupt"] -pub type NAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type NAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt"] #[inline(always)] @@ -133,86 +101,109 @@ impl R { NAK_R::new(((self.bits >> 13) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPINT") + .field("xfrc", &format_args!("{}", self.xfrc().bit())) + .field("epdisd", &format_args!("{}", self.epdisd().bit())) + .field("toc", &format_args!("{}", self.toc().bit())) + .field("ittxfe", &format_args!("{}", self.ittxfe().bit())) + .field("inepne", &format_args!("{}", self.inepne().bit())) + .field("txfe", &format_args!("{}", self.txfe().bit())) + .field("txfifoudrn", &format_args!("{}", self.txfifoudrn().bit())) + .field("bna", &format_args!("{}", self.bna().bit())) + .field("pktdrpsts", &format_args!("{}", self.pktdrpsts().bit())) + .field("berr", &format_args!("{}", self.berr().bit())) + .field("nak", &format_args!("{}", self.nak().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt"] #[inline(always)] #[must_use] - pub fn xfrc(&mut self) -> XFRC_W<0> { + pub fn xfrc(&mut self) -> XFRC_W { XFRC_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt"] #[inline(always)] #[must_use] - pub fn epdisd(&mut self) -> EPDISD_W<1> { + pub fn epdisd(&mut self) -> EPDISD_W { EPDISD_W::new(self) } #[doc = "Bit 3 - Timeout condition"] #[inline(always)] #[must_use] - pub fn toc(&mut self) -> TOC_W<3> { + pub fn toc(&mut self) -> TOC_W { TOC_W::new(self) } #[doc = "Bit 4 - IN token received when TxFIFO is empty"] #[inline(always)] #[must_use] - pub fn ittxfe(&mut self) -> ITTXFE_W<4> { + pub fn ittxfe(&mut self) -> ITTXFE_W { ITTXFE_W::new(self) } #[doc = "Bit 6 - IN endpoint NAK effective"] #[inline(always)] #[must_use] - pub fn inepne(&mut self) -> INEPNE_W<6> { + pub fn inepne(&mut self) -> INEPNE_W { INEPNE_W::new(self) } #[doc = "Bit 8 - Transmit Fifo Underrun"] #[inline(always)] #[must_use] - pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<8> { + pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W { TXFIFOUDRN_W::new(self) } #[doc = "Bit 9 - Buffer not available interrupt"] #[inline(always)] #[must_use] - pub fn bna(&mut self) -> BNA_W<9> { + pub fn bna(&mut self) -> BNA_W { BNA_W::new(self) } #[doc = "Bit 11 - Packet dropped status"] #[inline(always)] #[must_use] - pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<11> { + pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W { PKTDRPSTS_W::new(self) } #[doc = "Bit 12 - Babble error interrupt"] #[inline(always)] #[must_use] - pub fn berr(&mut self) -> BERR_W<12> { + pub fn berr(&mut self) -> BERR_W { BERR_W::new(self) } #[doc = "Bit 13 - NAK interrupt"] #[inline(always)] #[must_use] - pub fn nak(&mut self) -> NAK_W<13> { + pub fn nak(&mut self) -> NAK_W { NAK_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepint](index.html) module"] +#[doc = "Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPINT_SPEC; impl crate::RegisterSpec for DIEPINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepint::R](R) reader structure"] -impl crate::Readable for DIEPINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepint::W](W) writer structure"] +#[doc = "`read()` method returns [`diepint::R`](R) reader structure"] +impl crate::Readable for DIEPINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepint::W`](W) writer structure"] impl crate::Writable for DIEPINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs index 7f94dcb..72226f2 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRSIZ` reader - Transfer size"] -pub type XFRSIZ_R = crate::FieldReader; +pub type XFRSIZ_R = crate::FieldReader; #[doc = "Field `XFRSIZ` writer - Transfer size"] -pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTSIZ_SPEC, u8, u8, 7, O>; +pub type XFRSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `PKTCNT` reader - Packet count"] -pub type PKTCNT_R = crate::FieldReader; +pub type PKTCNT_R = crate::FieldReader; #[doc = "Field `PKTCNT` writer - Packet count"] -pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTSIZ_SPEC, u8, u8, 2, O>; +pub type PKTCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:6 - Transfer size"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { PKTCNT_R::new(((self.bits >> 19) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTSIZ") + .field("xfrsiz", &format_args!("{}", self.xfrsiz().bits())) + .field("pktcnt", &format_args!("{}", self.pktcnt().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - Transfer size"] #[inline(always)] #[must_use] - pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + pub fn xfrsiz(&mut self) -> XFRSIZ_W { XFRSIZ_W::new(self) } #[doc = "Bits 19:20 - Packet count"] #[inline(always)] #[must_use] - pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + pub fn pktcnt(&mut self) -> PKTCNT_W { PKTCNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptsiz](index.html) module"] +#[doc = "Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTSIZ_SPEC; impl crate::RegisterSpec for DIEPTSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptsiz::R](R) reader structure"] -impl crate::Readable for DIEPTSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptsiz::R`](R) reader structure"] +impl crate::Readable for DIEPTSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptsiz::W`](W) writer structure"] impl crate::Writable for DIEPTSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs index c962826..abe4eef 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs @@ -1,20 +1,7 @@ #[doc = "Register `DTXFSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `INEPTFSAV` reader - IN endpoint TxFIFO space avail"] -pub type INEPTFSAV_R = crate::FieldReader; +pub type INEPTFSAV_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - IN endpoint TxFIFO space avail"] #[inline(always)] @@ -22,15 +9,25 @@ impl R { INEPTFSAV_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Transmit FIFO status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dtxfsts](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DTXFSTS") + .field("ineptfsav", &format_args!("{}", self.ineptfsav().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Transmit FIFO status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtxfsts::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DTXFSTS_SPEC; impl crate::RegisterSpec for DTXFSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dtxfsts::R](R) reader structure"] -impl crate::Readable for DTXFSTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`dtxfsts::R`](R) reader structure"] +impl crate::Readable for DTXFSTS_SPEC {} #[doc = "`reset()` method sets DTXFSTS to value 0"] impl crate::Resettable for DTXFSTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint.rs b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint.rs index a3a9e56..360b7f9 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct OUT_ENDPOINT { #[doc = "0x00 - Control"] pub doepctl: DOEPCTL, @@ -12,19 +13,23 @@ pub struct OUT_ENDPOINT { #[doc = "0x14 - DMA address"] pub doepdma: DOEPDMA, } -#[doc = "DOEPCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPCTL (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepctl`] +module"] pub type DOEPCTL = crate::Reg; #[doc = "Control"] pub mod doepctl; -#[doc = "DOEPINT (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPINT (rw) register accessor: Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepint`] +module"] pub type DOEPINT = crate::Reg; #[doc = "Interrupt"] pub mod doepint; -#[doc = "DOEPTSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPTSIZ (rw) register accessor: Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doeptsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doeptsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doeptsiz`] +module"] pub type DOEPTSIZ = crate::Reg; #[doc = "Transfer size"] pub mod doeptsiz; -#[doc = "DOEPDMA (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPDMA (rw) register accessor: DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepdma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepdma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepdma`] +module"] pub type DOEPDMA = crate::Reg; #[doc = "DMA address"] pub mod doepdma; diff --git a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepctl.rs b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepctl.rs index 2f6baf5..47f7dd2 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepctl.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepctl.rs @@ -1,63 +1,31 @@ #[doc = "Register `DOEPCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MPSIZ` reader - Maximum packet size"] -pub type MPSIZ_R = crate::FieldReader; +pub type MPSIZ_R = crate::FieldReader; #[doc = "Field `USBAEP` reader - USB active endpoint"] -pub type USBAEP_R = crate::BitReader; +pub type USBAEP_R = crate::BitReader; #[doc = "Field `NAKSTS` reader - NAK status"] -pub type NAKSTS_R = crate::BitReader; +pub type NAKSTS_R = crate::BitReader; #[doc = "Field `EPTYP` reader - Endpoint type"] -pub type EPTYP_R = crate::FieldReader; +pub type EPTYP_R = crate::FieldReader; #[doc = "Field `SNPM` reader - Snoop mode"] -pub type SNPM_R = crate::BitReader; +pub type SNPM_R = crate::BitReader; #[doc = "Field `SNPM` writer - Snoop mode"] -pub type SNPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type SNPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `Stall` reader - STALL handshake"] -pub type STALL_R = crate::BitReader; +pub type STALL_R = crate::BitReader; #[doc = "Field `Stall` writer - STALL handshake"] -pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CNAK` writer - Clear NAK"] -pub type CNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type CNAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SNAK` writer - Set NAK"] -pub type SNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type SNAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDIS` reader - Endpoint disable"] -pub type EPDIS_R = crate::BitReader; +pub type EPDIS_R = crate::BitReader; #[doc = "Field `EPENA` writer - Endpoint enable"] -pub type EPENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type EPENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:1 - Maximum packet size"] #[inline(always)] @@ -95,56 +63,75 @@ impl R { EPDIS_R::new(((self.bits >> 30) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPCTL") + .field("mpsiz", &format_args!("{}", self.mpsiz().bits())) + .field("usbaep", &format_args!("{}", self.usbaep().bit())) + .field("naksts", &format_args!("{}", self.naksts().bit())) + .field("eptyp", &format_args!("{}", self.eptyp().bits())) + .field("snpm", &format_args!("{}", self.snpm().bit())) + .field("stall", &format_args!("{}", self.stall().bit())) + .field("epdis", &format_args!("{}", self.epdis().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 20 - Snoop mode"] #[inline(always)] #[must_use] - pub fn snpm(&mut self) -> SNPM_W<20> { + pub fn snpm(&mut self) -> SNPM_W { SNPM_W::new(self) } #[doc = "Bit 21 - STALL handshake"] #[inline(always)] #[must_use] - pub fn stall(&mut self) -> STALL_W<21> { + pub fn stall(&mut self) -> STALL_W { STALL_W::new(self) } #[doc = "Bit 26 - Clear NAK"] #[inline(always)] #[must_use] - pub fn cnak(&mut self) -> CNAK_W<26> { + pub fn cnak(&mut self) -> CNAK_W { CNAK_W::new(self) } #[doc = "Bit 27 - Set NAK"] #[inline(always)] #[must_use] - pub fn snak(&mut self) -> SNAK_W<27> { + pub fn snak(&mut self) -> SNAK_W { SNAK_W::new(self) } #[doc = "Bit 31 - Endpoint enable"] #[inline(always)] #[must_use] - pub fn epena(&mut self) -> EPENA_W<31> { + pub fn epena(&mut self) -> EPENA_W { EPENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepctl](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPCTL_SPEC; impl crate::RegisterSpec for DOEPCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepctl::R](R) reader structure"] -impl crate::Readable for DOEPCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepctl::W](W) writer structure"] +#[doc = "`read()` method returns [`doepctl::R`](R) reader structure"] +impl crate::Readable for DOEPCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepctl::W`](W) writer structure"] impl crate::Writable for DOEPCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepdma.rs b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepdma.rs index 92089f0..ab7d95d 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepdma.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepdma.rs @@ -1,43 +1,11 @@ #[doc = "Register `DOEPDMA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPDMA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMAADDR` reader - DMA address"] -pub type DMAADDR_R = crate::FieldReader; +pub type DMAADDR_R = crate::FieldReader; #[doc = "Field `DMAADDR` writer - DMA address"] -pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPDMA_SPEC, u32, u32, 32, O>; +pub type DMAADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DMAADDR_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPDMA") + .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] #[must_use] - pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + pub fn dmaaddr(&mut self) -> DMAADDR_W { DMAADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepdma](index.html) module"] +#[doc = "DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepdma::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepdma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPDMA_SPEC; impl crate::RegisterSpec for DOEPDMA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepdma::R](R) reader structure"] -impl crate::Readable for DOEPDMA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepdma::W](W) writer structure"] +#[doc = "`read()` method returns [`doepdma::R`](R) reader structure"] +impl crate::Readable for DOEPDMA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepdma::W`](W) writer structure"] impl crate::Writable for DOEPDMA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepint.rs b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepint.rs index 365d667..0552c9b 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepint.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doepint.rs @@ -1,63 +1,31 @@ #[doc = "Register `DOEPINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRC` reader - Transfer completed interrupt"] -pub type XFRC_R = crate::BitReader; +pub type XFRC_R = crate::BitReader; #[doc = "Field `XFRC` writer - Transfer completed interrupt"] -pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type XFRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISD` reader - Endpoint disabled interrupt"] -pub type EPDISD_R = crate::BitReader; +pub type EPDISD_R = crate::BitReader; #[doc = "Field `EPDISD` writer - Endpoint disabled interrupt"] -pub type EPDISD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type EPDISD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STUP` reader - SETUP phase done"] -pub type STUP_R = crate::BitReader; +pub type STUP_R = crate::BitReader; #[doc = "Field `STUP` writer - SETUP phase done"] -pub type STUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type STUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OTEPDIS` reader - OUT token received when endpoint disabled"] -pub type OTEPDIS_R = crate::BitReader; +pub type OTEPDIS_R = crate::BitReader; #[doc = "Field `OTEPDIS` writer - OUT token received when endpoint disabled"] -pub type OTEPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type OTEPDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `B2BSTUP` reader - Back-to-back SETUP packets received"] -pub type B2BSTUP_R = crate::BitReader; +pub type B2BSTUP_R = crate::BitReader; #[doc = "Field `B2BSTUP` writer - Back-to-back SETUP packets received"] -pub type B2BSTUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type B2BSTUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYET` reader - NYET interrupt"] -pub type NYET_R = crate::BitReader; +pub type NYET_R = crate::BitReader; #[doc = "Field `NYET` writer - NYET interrupt"] -pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type NYET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt"] #[inline(always)] @@ -90,62 +58,80 @@ impl R { NYET_R::new(((self.bits >> 14) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPINT") + .field("xfrc", &format_args!("{}", self.xfrc().bit())) + .field("epdisd", &format_args!("{}", self.epdisd().bit())) + .field("stup", &format_args!("{}", self.stup().bit())) + .field("otepdis", &format_args!("{}", self.otepdis().bit())) + .field("b2bstup", &format_args!("{}", self.b2bstup().bit())) + .field("nyet", &format_args!("{}", self.nyet().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt"] #[inline(always)] #[must_use] - pub fn xfrc(&mut self) -> XFRC_W<0> { + pub fn xfrc(&mut self) -> XFRC_W { XFRC_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt"] #[inline(always)] #[must_use] - pub fn epdisd(&mut self) -> EPDISD_W<1> { + pub fn epdisd(&mut self) -> EPDISD_W { EPDISD_W::new(self) } #[doc = "Bit 3 - SETUP phase done"] #[inline(always)] #[must_use] - pub fn stup(&mut self) -> STUP_W<3> { + pub fn stup(&mut self) -> STUP_W { STUP_W::new(self) } #[doc = "Bit 4 - OUT token received when endpoint disabled"] #[inline(always)] #[must_use] - pub fn otepdis(&mut self) -> OTEPDIS_W<4> { + pub fn otepdis(&mut self) -> OTEPDIS_W { OTEPDIS_W::new(self) } #[doc = "Bit 6 - Back-to-back SETUP packets received"] #[inline(always)] #[must_use] - pub fn b2bstup(&mut self) -> B2BSTUP_W<6> { + pub fn b2bstup(&mut self) -> B2BSTUP_W { B2BSTUP_W::new(self) } #[doc = "Bit 14 - NYET interrupt"] #[inline(always)] #[must_use] - pub fn nyet(&mut self) -> NYET_W<14> { + pub fn nyet(&mut self) -> NYET_W { NYET_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepint](index.html) module"] +#[doc = "Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPINT_SPEC; impl crate::RegisterSpec for DOEPINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepint::R](R) reader structure"] -impl crate::Readable for DOEPINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepint::W](W) writer structure"] +#[doc = "`read()` method returns [`doepint::R`](R) reader structure"] +impl crate::Readable for DOEPINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepint::W`](W) writer structure"] impl crate::Writable for DOEPINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs index 0f78e4d..4606c37 100644 --- a/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs +++ b/crates/bcm2835-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs @@ -1,51 +1,19 @@ #[doc = "Register `DOEPTSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPTSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRSIZ` reader - Transfer size"] -pub type XFRSIZ_R = crate::FieldReader; +pub type XFRSIZ_R = crate::FieldReader; #[doc = "Field `XFRSIZ` writer - Transfer size"] -pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPTSIZ_SPEC, u8, u8, 7, O>; +pub type XFRSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `PKTCNT` reader - Packet count"] -pub type PKTCNT_R = crate::BitReader; +pub type PKTCNT_R = crate::BitReader; #[doc = "Field `PKTCNT` writer - Packet count"] -pub type PKTCNT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPTSIZ_SPEC, bool, O>; +pub type PKTCNT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STUPCNT` reader - SETUP packet count"] -pub type STUPCNT_R = crate::FieldReader; +pub type STUPCNT_R = crate::FieldReader; #[doc = "Field `STUPCNT` writer - SETUP packet count"] -pub type STUPCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPTSIZ_SPEC, u8, u8, 2, O>; +pub type STUPCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:6 - Transfer size"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { STUPCNT_R::new(((self.bits >> 29) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPTSIZ") + .field("xfrsiz", &format_args!("{}", self.xfrsiz().bits())) + .field("pktcnt", &format_args!("{}", self.pktcnt().bit())) + .field("stupcnt", &format_args!("{}", self.stupcnt().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - Transfer size"] #[inline(always)] #[must_use] - pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + pub fn xfrsiz(&mut self) -> XFRSIZ_W { XFRSIZ_W::new(self) } #[doc = "Bit 19 - Packet count"] #[inline(always)] #[must_use] - pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + pub fn pktcnt(&mut self) -> PKTCNT_W { PKTCNT_W::new(self) } #[doc = "Bits 29:30 - SETUP packet count"] #[inline(always)] #[must_use] - pub fn stupcnt(&mut self) -> STUPCNT_W<29> { + pub fn stupcnt(&mut self) -> STUPCNT_W { STUPCNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doeptsiz](index.html) module"] +#[doc = "Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doeptsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doeptsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPTSIZ_SPEC; impl crate::RegisterSpec for DOEPTSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doeptsiz::R](R) reader structure"] -impl crate::Readable for DOEPTSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doeptsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`doeptsiz::R`](R) reader structure"] +impl crate::Readable for DOEPTSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doeptsiz::W`](W) writer structure"] impl crate::Writable for DOEPTSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global.rs b/crates/bcm2835-lpa/src/usb_otg_global.rs index a6b35cb..d8a5a57 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - OTG_HS control and status register"] pub gotgctl: GOTGCTL, @@ -84,115 +85,143 @@ impl RegisterBlock { unsafe { &*(self as *const Self).cast::().add(40usize).cast() } } } -#[doc = "GOTGCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "GOTGCTL (rw) register accessor: OTG_HS control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gotgctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gotgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gotgctl`] +module"] pub type GOTGCTL = crate::Reg; #[doc = "OTG_HS control and status register"] pub mod gotgctl; -#[doc = "GOTGINT (rw) register accessor: an alias for `Reg`"] +#[doc = "GOTGINT (rw) register accessor: OTG_HS interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gotgint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gotgint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gotgint`] +module"] pub type GOTGINT = crate::Reg; #[doc = "OTG_HS interrupt register"] pub mod gotgint; -#[doc = "GAHBCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "GAHBCFG (rw) register accessor: OTG_HS AHB configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gahbcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gahbcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gahbcfg`] +module"] pub type GAHBCFG = crate::Reg; #[doc = "OTG_HS AHB configuration register"] pub mod gahbcfg; -#[doc = "GUSBCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "GUSBCFG (rw) register accessor: OTG_HS USB configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gusbcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gusbcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gusbcfg`] +module"] pub type GUSBCFG = crate::Reg; #[doc = "OTG_HS USB configuration register"] pub mod gusbcfg; -#[doc = "GRSTCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "GRSTCTL (rw) register accessor: OTG_HS reset register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grstctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grstctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grstctl`] +module"] pub type GRSTCTL = crate::Reg; #[doc = "OTG_HS reset register"] pub mod grstctl; -#[doc = "GINTSTS (rw) register accessor: an alias for `Reg`"] +#[doc = "GINTSTS (rw) register accessor: OTG_HS core interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gintsts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gintsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gintsts`] +module"] pub type GINTSTS = crate::Reg; #[doc = "OTG_HS core interrupt register"] pub mod gintsts; -#[doc = "GINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "GINTMSK (rw) register accessor: OTG_HS interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gintmsk`] +module"] pub type GINTMSK = crate::Reg; #[doc = "OTG_HS interrupt mask register"] pub mod gintmsk; -#[doc = "GRXSTSR_Host (r) register accessor: an alias for `Reg`"] +#[doc = "GRXSTSR_Host (r) register accessor: OTG_HS Receive status debug read register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr_host::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsr_host`] +module"] pub type GRXSTSR_HOST = crate::Reg; #[doc = "OTG_HS Receive status debug read register (host mode)"] pub mod grxstsr_host; -#[doc = "GRXSTSP_Host (r) register accessor: an alias for `Reg`"] +#[doc = "GRXSTSP_Host (r) register accessor: OTG_HS status read and pop register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp_host::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsp_host`] +module"] pub type GRXSTSP_HOST = crate::Reg; #[doc = "OTG_HS status read and pop register (host mode)"] pub mod grxstsp_host; -#[doc = "GRXFSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "GRXFSIZ (rw) register accessor: OTG_HS Receive FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxfsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grxfsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxfsiz`] +module"] pub type GRXFSIZ = crate::Reg; #[doc = "OTG_HS Receive FIFO size register"] pub mod grxfsiz; -#[doc = "GNPTXFSIZ_Host (rw) register accessor: an alias for `Reg`"] +#[doc = "GNPTXFSIZ_Host (rw) register accessor: OTG_HS nonperiodic transmit FIFO size register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxfsiz_host::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gnptxfsiz_host::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gnptxfsiz_host`] +module"] pub type GNPTXFSIZ_HOST = crate::Reg; #[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)"] pub mod gnptxfsiz_host; -#[doc = "TX0FSIZ_Peripheral (rw) register accessor: an alias for `Reg`"] +#[doc = "TX0FSIZ_Peripheral (rw) register accessor: Endpoint 0 transmit FIFO size (peripheral mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx0fsiz_peripheral::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx0fsiz_peripheral::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx0fsiz_peripheral`] +module"] pub type TX0FSIZ_PERIPHERAL = crate::Reg; #[doc = "Endpoint 0 transmit FIFO size (peripheral mode)"] pub mod tx0fsiz_peripheral; -#[doc = "GNPTXSTS (r) register accessor: an alias for `Reg`"] +#[doc = "GNPTXSTS (r) register accessor: OTG_HS nonperiodic transmit FIFO/queue status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxsts::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gnptxsts`] +module"] pub type GNPTXSTS = crate::Reg; #[doc = "OTG_HS nonperiodic transmit FIFO/queue status register"] pub mod gnptxsts; -#[doc = "GCCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "GCCFG (rw) register accessor: OTG_HS general core configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gccfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gccfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gccfg`] +module"] pub type GCCFG = crate::Reg; #[doc = "OTG_HS general core configuration register"] pub mod gccfg; -#[doc = "CID (rw) register accessor: an alias for `Reg`"] +#[doc = "CID (rw) register accessor: OTG_HS core ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cid::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cid::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cid`] +module"] pub type CID = crate::Reg; #[doc = "OTG_HS core ID register"] pub mod cid; -#[doc = "VID (r) register accessor: an alias for `Reg`"] +#[doc = "VID (r) register accessor: OTG_HS vendor ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid`] +module"] pub type VID = crate::Reg; #[doc = "OTG_HS vendor ID register"] pub mod vid; -#[doc = "HW_DIRECTION (r) register accessor: an alias for `Reg`"] +#[doc = "HW_DIRECTION (r) register accessor: Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_direction::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_direction`] +module"] pub type HW_DIRECTION = crate::Reg; #[doc = "Direction"] pub mod hw_direction; -#[doc = "HW_CONFIG0 (r) register accessor: an alias for `Reg`"] +#[doc = "HW_CONFIG0 (r) register accessor: Hardware Config 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_config0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_config0`] +module"] pub type HW_CONFIG0 = crate::Reg; #[doc = "Hardware Config 0"] pub mod hw_config0; -#[doc = "HPTXFSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "HPTXFSIZ (rw) register accessor: OTG_HS Host periodic transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxfsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hptxfsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hptxfsiz`] +module"] pub type HPTXFSIZ = crate::Reg; #[doc = "OTG_HS Host periodic transmit FIFO size register"] pub mod hptxfsiz; -#[doc = "DIEPTXF1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF1 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf1`] +module"] pub type DIEPTXF1 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf1; -#[doc = "DIEPTXF2 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF2 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf2`] +module"] pub type DIEPTXF2 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf2; -#[doc = "DIEPTXF3 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF3 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf3`] +module"] pub type DIEPTXF3 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf3; -#[doc = "DIEPTXF4 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF4 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf4`] +module"] pub type DIEPTXF4 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf4; -#[doc = "DIEPTXF5 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF5 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf5`] +module"] pub type DIEPTXF5 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf5; -#[doc = "DIEPTXF6 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF6 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf6`] +module"] pub type DIEPTXF6 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf6; -#[doc = "DIEPTXF7 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF7 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf7`] +module"] pub type DIEPTXF7 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf7; -#[doc = "GRXSTSR_Peripheral (r) register accessor: an alias for `Reg`"] +#[doc = "GRXSTSR_Peripheral (r) register accessor: OTG_HS Receive status debug read register (peripheral mode mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr_peripheral::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsr_peripheral`] +module"] pub type GRXSTSR_PERIPHERAL = crate::Reg; #[doc = "OTG_HS Receive status debug read register (peripheral mode mode)"] pub mod grxstsr_peripheral; -#[doc = "GRXSTSP_Peripheral (r) register accessor: an alias for `Reg`"] +#[doc = "GRXSTSP_Peripheral (r) register accessor: OTG_HS status read and pop register (peripheral mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp_peripheral::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsp_peripheral`] +module"] pub type GRXSTSP_PERIPHERAL = crate::Reg; #[doc = "OTG_HS status read and pop register (peripheral mode)"] pub mod grxstsp_peripheral; diff --git a/crates/bcm2835-lpa/src/usb_otg_global/cid.rs b/crates/bcm2835-lpa/src/usb_otg_global/cid.rs index 5a8ef55..c840ab9 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/cid.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/cid.rs @@ -1,43 +1,11 @@ #[doc = "Register `CID` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CID` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PRODUCT_ID` reader - Product ID field"] -pub type PRODUCT_ID_R = crate::FieldReader; +pub type PRODUCT_ID_R = crate::FieldReader; #[doc = "Field `PRODUCT_ID` writer - Product ID field"] -pub type PRODUCT_ID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CID_SPEC, u32, u32, 32, O>; +pub type PRODUCT_ID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Product ID field"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { PRODUCT_ID_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CID") + .field("product_id", &format_args!("{}", self.product_id().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - Product ID field"] #[inline(always)] #[must_use] - pub fn product_id(&mut self) -> PRODUCT_ID_W<0> { + pub fn product_id(&mut self) -> PRODUCT_ID_W { PRODUCT_ID_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS core ID register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid](index.html) module"] +#[doc = "OTG_HS core ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cid::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cid::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CID_SPEC; impl crate::RegisterSpec for CID_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cid::R](R) reader structure"] -impl crate::Readable for CID_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cid::W](W) writer structure"] +#[doc = "`read()` method returns [`cid::R`](R) reader structure"] +impl crate::Readable for CID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cid::W`](W) writer structure"] impl crate::Writable for CID_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf1.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf1.rs index b79803c..52be8d1 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf1.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf1.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF1_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF1_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF1") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf1](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF1_SPEC; impl crate::RegisterSpec for DIEPTXF1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf1::R](R) reader structure"] -impl crate::Readable for DIEPTXF1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf1::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf1::R`](R) reader structure"] +impl crate::Readable for DIEPTXF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf1::W`](W) writer structure"] impl crate::Writable for DIEPTXF1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf2.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf2.rs index cdf9d1b..ce63253 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf2.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf2.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF2_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF2_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF2") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf2](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF2_SPEC; impl crate::RegisterSpec for DIEPTXF2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf2::R](R) reader structure"] -impl crate::Readable for DIEPTXF2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf2::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf2::R`](R) reader structure"] +impl crate::Readable for DIEPTXF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf2::W`](W) writer structure"] impl crate::Writable for DIEPTXF2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf3.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf3.rs index 8eaba75..18a518c 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf3.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf3.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF3_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF3_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF3") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf3](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF3_SPEC; impl crate::RegisterSpec for DIEPTXF3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf3::R](R) reader structure"] -impl crate::Readable for DIEPTXF3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf3::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf3::R`](R) reader structure"] +impl crate::Readable for DIEPTXF3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf3::W`](W) writer structure"] impl crate::Writable for DIEPTXF3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf4.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf4.rs index 6b30646..9b23f1d 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf4.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf4.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF4_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF4_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF4") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf4](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF4_SPEC; impl crate::RegisterSpec for DIEPTXF4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf4::R](R) reader structure"] -impl crate::Readable for DIEPTXF4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf4::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf4::R`](R) reader structure"] +impl crate::Readable for DIEPTXF4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf4::W`](W) writer structure"] impl crate::Writable for DIEPTXF4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf5.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf5.rs index e2b7d98..03b144c 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf5.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf5.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF5_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF5_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF5") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf5](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF5_SPEC; impl crate::RegisterSpec for DIEPTXF5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf5::R](R) reader structure"] -impl crate::Readable for DIEPTXF5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf5::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf5::R`](R) reader structure"] +impl crate::Readable for DIEPTXF5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf5::W`](W) writer structure"] impl crate::Writable for DIEPTXF5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf6.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf6.rs index da38751..57dcb25 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf6.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf6.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF6_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF6_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF6") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf6](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF6_SPEC; impl crate::RegisterSpec for DIEPTXF6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf6::R](R) reader structure"] -impl crate::Readable for DIEPTXF6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf6::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf6::R`](R) reader structure"] +impl crate::Readable for DIEPTXF6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf6::W`](W) writer structure"] impl crate::Writable for DIEPTXF6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf7.rs b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf7.rs index 811d528..7a99ea4 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/dieptxf7.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/dieptxf7.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF7` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF7` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF7_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF7_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF7") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf7](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF7_SPEC; impl crate::RegisterSpec for DIEPTXF7_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf7::R](R) reader structure"] -impl crate::Readable for DIEPTXF7_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf7::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf7::R`](R) reader structure"] +impl crate::Readable for DIEPTXF7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf7::W`](W) writer structure"] impl crate::Writable for DIEPTXF7_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gahbcfg.rs b/crates/bcm2835-lpa/src/usb_otg_global/gahbcfg.rs index 987d389..a135db6 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/gahbcfg.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/gahbcfg.rs @@ -1,45 +1,13 @@ #[doc = "Register `GAHBCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GAHBCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GINT` reader - Global interrupt mask"] -pub type GINT_R = crate::BitReader; +pub type GINT_R = crate::BitReader; #[doc = "Field `GINT` writer - Global interrupt mask"] -pub type GINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type GINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AXI_BURST` reader - Maximum AXI burst length"] -pub type AXI_BURST_R = crate::FieldReader; +pub type AXI_BURST_R = crate::FieldReader; #[doc = "Maximum AXI burst length\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -59,10 +27,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for BURST_A { + type Ux = u8; +} impl AXI_BURST_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> BURST_A { + pub const fn variant(&self) -> BURST_A { match self.bits { 0 => BURST_A::_4, 1 => BURST_A::_3, @@ -71,68 +42,71 @@ impl AXI_BURST_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_4`"] + #[doc = "`0`"] #[inline(always)] pub fn is_4(&self) -> bool { *self == BURST_A::_4 } - #[doc = "Checks if the value of the field is `_3`"] + #[doc = "`1`"] #[inline(always)] pub fn is_3(&self) -> bool { *self == BURST_A::_3 } - #[doc = "Checks if the value of the field is `_2`"] + #[doc = "`10`"] #[inline(always)] pub fn is_2(&self) -> bool { *self == BURST_A::_2 } - #[doc = "Checks if the value of the field is `_1`"] + #[doc = "`11`"] #[inline(always)] pub fn is_1(&self) -> bool { *self == BURST_A::_1 } } #[doc = "Field `AXI_BURST` writer - Maximum AXI burst length"] -pub type AXI_BURST_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GAHBCFG_SPEC, u8, BURST_A, 2, O>; -impl<'a, const O: u8> AXI_BURST_W<'a, O> { +pub type AXI_BURST_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, BURST_A>; +impl<'a, REG, const O: u8> AXI_BURST_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _4(self) -> &'a mut W { + pub fn _4(self) -> &'a mut crate::W { self.variant(BURST_A::_4) } #[doc = "`1`"] #[inline(always)] - pub fn _3(self) -> &'a mut W { + pub fn _3(self) -> &'a mut crate::W { self.variant(BURST_A::_3) } #[doc = "`10`"] #[inline(always)] - pub fn _2(self) -> &'a mut W { + pub fn _2(self) -> &'a mut crate::W { self.variant(BURST_A::_2) } #[doc = "`11`"] #[inline(always)] - pub fn _1(self) -> &'a mut W { + pub fn _1(self) -> &'a mut crate::W { self.variant(BURST_A::_1) } } #[doc = "Field `AXI_WAIT` reader - Wait for all AXI writes before signaling DMA"] -pub type AXI_WAIT_R = crate::BitReader; +pub type AXI_WAIT_R = crate::BitReader; #[doc = "Field `AXI_WAIT` writer - Wait for all AXI writes before signaling DMA"] -pub type AXI_WAIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type AXI_WAIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMAEN` reader - DMA enable"] -pub type DMAEN_R = crate::BitReader; +pub type DMAEN_R = crate::BitReader; #[doc = "Field `DMAEN` writer - DMA enable"] -pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type DMAEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFELVL` reader - TxFIFO empty level"] -pub type TXFELVL_R = crate::BitReader; +pub type TXFELVL_R = crate::BitReader; #[doc = "Field `TXFELVL` writer - TxFIFO empty level"] -pub type TXFELVL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type TXFELVL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTXFELVL` reader - Periodic TxFIFO empty level"] -pub type PTXFELVL_R = crate::BitReader; +pub type PTXFELVL_R = crate::BitReader; #[doc = "Field `PTXFELVL` writer - Periodic TxFIFO empty level"] -pub type PTXFELVL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type PTXFELVL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Global interrupt mask"] #[inline(always)] @@ -165,62 +139,80 @@ impl R { PTXFELVL_R::new(((self.bits >> 8) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAHBCFG") + .field("gint", &format_args!("{}", self.gint().bit())) + .field("axi_wait", &format_args!("{}", self.axi_wait().bit())) + .field("axi_burst", &format_args!("{}", self.axi_burst().bits())) + .field("dmaen", &format_args!("{}", self.dmaen().bit())) + .field("txfelvl", &format_args!("{}", self.txfelvl().bit())) + .field("ptxfelvl", &format_args!("{}", self.ptxfelvl().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Global interrupt mask"] #[inline(always)] #[must_use] - pub fn gint(&mut self) -> GINT_W<0> { + pub fn gint(&mut self) -> GINT_W { GINT_W::new(self) } #[doc = "Bits 1:2 - Maximum AXI burst length"] #[inline(always)] #[must_use] - pub fn axi_burst(&mut self) -> AXI_BURST_W<1> { + pub fn axi_burst(&mut self) -> AXI_BURST_W { AXI_BURST_W::new(self) } #[doc = "Bit 4 - Wait for all AXI writes before signaling DMA"] #[inline(always)] #[must_use] - pub fn axi_wait(&mut self) -> AXI_WAIT_W<4> { + pub fn axi_wait(&mut self) -> AXI_WAIT_W { AXI_WAIT_W::new(self) } #[doc = "Bit 5 - DMA enable"] #[inline(always)] #[must_use] - pub fn dmaen(&mut self) -> DMAEN_W<5> { + pub fn dmaen(&mut self) -> DMAEN_W { DMAEN_W::new(self) } #[doc = "Bit 7 - TxFIFO empty level"] #[inline(always)] #[must_use] - pub fn txfelvl(&mut self) -> TXFELVL_W<7> { + pub fn txfelvl(&mut self) -> TXFELVL_W { TXFELVL_W::new(self) } #[doc = "Bit 8 - Periodic TxFIFO empty level"] #[inline(always)] #[must_use] - pub fn ptxfelvl(&mut self) -> PTXFELVL_W<8> { + pub fn ptxfelvl(&mut self) -> PTXFELVL_W { PTXFELVL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS AHB configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gahbcfg](index.html) module"] +#[doc = "OTG_HS AHB configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gahbcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gahbcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GAHBCFG_SPEC; impl crate::RegisterSpec for GAHBCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gahbcfg::R](R) reader structure"] -impl crate::Readable for GAHBCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gahbcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`gahbcfg::R`](R) reader structure"] +impl crate::Readable for GAHBCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gahbcfg::W`](W) writer structure"] impl crate::Writable for GAHBCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gccfg.rs b/crates/bcm2835-lpa/src/usb_otg_global/gccfg.rs index 4dbbf5c..6612077 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/gccfg.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/gccfg.rs @@ -1,63 +1,31 @@ #[doc = "Register `GCCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GCCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PWRDWN` reader - Power down"] -pub type PWRDWN_R = crate::BitReader; +pub type PWRDWN_R = crate::BitReader; #[doc = "Field `PWRDWN` writer - Power down"] -pub type PWRDWN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type PWRDWN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2CPADEN` reader - Enable I2C bus connection for the external I2C PHY interface"] -pub type I2CPADEN_R = crate::BitReader; +pub type I2CPADEN_R = crate::BitReader; #[doc = "Field `I2CPADEN` writer - Enable I2C bus connection for the external I2C PHY interface"] -pub type I2CPADEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type I2CPADEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUSASEN` reader - Enable the VBUS sensing device"] -pub type VBUSASEN_R = crate::BitReader; +pub type VBUSASEN_R = crate::BitReader; #[doc = "Field `VBUSASEN` writer - Enable the VBUS sensing device"] -pub type VBUSASEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type VBUSASEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUSBSEN` reader - Enable the VBUS sensing device"] -pub type VBUSBSEN_R = crate::BitReader; +pub type VBUSBSEN_R = crate::BitReader; #[doc = "Field `VBUSBSEN` writer - Enable the VBUS sensing device"] -pub type VBUSBSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type VBUSBSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOFOUTEN` reader - SOF output enable"] -pub type SOFOUTEN_R = crate::BitReader; +pub type SOFOUTEN_R = crate::BitReader; #[doc = "Field `SOFOUTEN` writer - SOF output enable"] -pub type SOFOUTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type SOFOUTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NOVBUSSENS` reader - VBUS sensing disable option"] -pub type NOVBUSSENS_R = crate::BitReader; +pub type NOVBUSSENS_R = crate::BitReader; #[doc = "Field `NOVBUSSENS` writer - VBUS sensing disable option"] -pub type NOVBUSSENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type NOVBUSSENS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 16 - Power down"] #[inline(always)] @@ -90,62 +58,80 @@ impl R { NOVBUSSENS_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCCFG") + .field("pwrdwn", &format_args!("{}", self.pwrdwn().bit())) + .field("i2cpaden", &format_args!("{}", self.i2cpaden().bit())) + .field("vbusasen", &format_args!("{}", self.vbusasen().bit())) + .field("vbusbsen", &format_args!("{}", self.vbusbsen().bit())) + .field("sofouten", &format_args!("{}", self.sofouten().bit())) + .field("novbussens", &format_args!("{}", self.novbussens().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 16 - Power down"] #[inline(always)] #[must_use] - pub fn pwrdwn(&mut self) -> PWRDWN_W<16> { + pub fn pwrdwn(&mut self) -> PWRDWN_W { PWRDWN_W::new(self) } #[doc = "Bit 17 - Enable I2C bus connection for the external I2C PHY interface"] #[inline(always)] #[must_use] - pub fn i2cpaden(&mut self) -> I2CPADEN_W<17> { + pub fn i2cpaden(&mut self) -> I2CPADEN_W { I2CPADEN_W::new(self) } #[doc = "Bit 18 - Enable the VBUS sensing device"] #[inline(always)] #[must_use] - pub fn vbusasen(&mut self) -> VBUSASEN_W<18> { + pub fn vbusasen(&mut self) -> VBUSASEN_W { VBUSASEN_W::new(self) } #[doc = "Bit 19 - Enable the VBUS sensing device"] #[inline(always)] #[must_use] - pub fn vbusbsen(&mut self) -> VBUSBSEN_W<19> { + pub fn vbusbsen(&mut self) -> VBUSBSEN_W { VBUSBSEN_W::new(self) } #[doc = "Bit 20 - SOF output enable"] #[inline(always)] #[must_use] - pub fn sofouten(&mut self) -> SOFOUTEN_W<20> { + pub fn sofouten(&mut self) -> SOFOUTEN_W { SOFOUTEN_W::new(self) } #[doc = "Bit 21 - VBUS sensing disable option"] #[inline(always)] #[must_use] - pub fn novbussens(&mut self) -> NOVBUSSENS_W<21> { + pub fn novbussens(&mut self) -> NOVBUSSENS_W { NOVBUSSENS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS general core configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gccfg](index.html) module"] +#[doc = "OTG_HS general core configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gccfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gccfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GCCFG_SPEC; impl crate::RegisterSpec for GCCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gccfg::R](R) reader structure"] -impl crate::Readable for GCCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gccfg::W](W) writer structure"] +#[doc = "`read()` method returns [`gccfg::R`](R) reader structure"] +impl crate::Readable for GCCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gccfg::W`](W) writer structure"] impl crate::Writable for GCCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gintmsk.rs b/crates/bcm2835-lpa/src/usb_otg_global/gintmsk.rs index d3fdb2d..1a856d7 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/gintmsk.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/gintmsk.rs @@ -1,141 +1,109 @@ #[doc = "Register `GINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MMISM` reader - Mode mismatch interrupt mask"] -pub type MMISM_R = crate::BitReader; +pub type MMISM_R = crate::BitReader; #[doc = "Field `MMISM` writer - Mode mismatch interrupt mask"] -pub type MMISM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type MMISM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OTGINT` reader - OTG interrupt mask"] -pub type OTGINT_R = crate::BitReader; +pub type OTGINT_R = crate::BitReader; #[doc = "Field `OTGINT` writer - OTG interrupt mask"] -pub type OTGINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type OTGINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOFM` reader - Start of frame mask"] -pub type SOFM_R = crate::BitReader; +pub type SOFM_R = crate::BitReader; #[doc = "Field `SOFM` writer - Start of frame mask"] -pub type SOFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type SOFM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFLVLM` reader - Receive FIFO nonempty mask"] -pub type RXFLVLM_R = crate::BitReader; +pub type RXFLVLM_R = crate::BitReader; #[doc = "Field `RXFLVLM` writer - Receive FIFO nonempty mask"] -pub type RXFLVLM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type RXFLVLM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NPTXFEM` reader - Nonperiodic TxFIFO empty mask"] -pub type NPTXFEM_R = crate::BitReader; +pub type NPTXFEM_R = crate::BitReader; #[doc = "Field `NPTXFEM` writer - Nonperiodic TxFIFO empty mask"] -pub type NPTXFEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type NPTXFEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GINAKEFFM` reader - Global nonperiodic IN NAK effective mask"] -pub type GINAKEFFM_R = crate::BitReader; +pub type GINAKEFFM_R = crate::BitReader; #[doc = "Field `GINAKEFFM` writer - Global nonperiodic IN NAK effective mask"] -pub type GINAKEFFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type GINAKEFFM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GONAKEFFM` reader - Global OUT NAK effective mask"] -pub type GONAKEFFM_R = crate::BitReader; +pub type GONAKEFFM_R = crate::BitReader; #[doc = "Field `GONAKEFFM` writer - Global OUT NAK effective mask"] -pub type GONAKEFFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type GONAKEFFM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ESUSPM` reader - Early suspend mask"] -pub type ESUSPM_R = crate::BitReader; +pub type ESUSPM_R = crate::BitReader; #[doc = "Field `ESUSPM` writer - Early suspend mask"] -pub type ESUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type ESUSPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBSUSPM` reader - USB suspend mask"] -pub type USBSUSPM_R = crate::BitReader; +pub type USBSUSPM_R = crate::BitReader; #[doc = "Field `USBSUSPM` writer - USB suspend mask"] -pub type USBSUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type USBSUSPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBRST` reader - USB reset mask"] -pub type USBRST_R = crate::BitReader; +pub type USBRST_R = crate::BitReader; #[doc = "Field `USBRST` writer - USB reset mask"] -pub type USBRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type USBRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENUMDNEM` reader - Enumeration done mask"] -pub type ENUMDNEM_R = crate::BitReader; +pub type ENUMDNEM_R = crate::BitReader; #[doc = "Field `ENUMDNEM` writer - Enumeration done mask"] -pub type ENUMDNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type ENUMDNEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISOODRPM` reader - Isochronous OUT packet dropped interrupt mask"] -pub type ISOODRPM_R = crate::BitReader; +pub type ISOODRPM_R = crate::BitReader; #[doc = "Field `ISOODRPM` writer - Isochronous OUT packet dropped interrupt mask"] -pub type ISOODRPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type ISOODRPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOPFM` reader - End of periodic frame interrupt mask"] -pub type EOPFM_R = crate::BitReader; +pub type EOPFM_R = crate::BitReader; #[doc = "Field `EOPFM` writer - End of periodic frame interrupt mask"] -pub type EOPFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type EOPFM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPMISM` reader - Endpoint mismatch interrupt mask"] -pub type EPMISM_R = crate::BitReader; +pub type EPMISM_R = crate::BitReader; #[doc = "Field `EPMISM` writer - Endpoint mismatch interrupt mask"] -pub type EPMISM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type EPMISM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IEPINT` reader - IN endpoints interrupt mask"] -pub type IEPINT_R = crate::BitReader; +pub type IEPINT_R = crate::BitReader; #[doc = "Field `IEPINT` writer - IN endpoints interrupt mask"] -pub type IEPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type IEPINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEPINT` reader - OUT endpoints interrupt mask"] -pub type OEPINT_R = crate::BitReader; +pub type OEPINT_R = crate::BitReader; #[doc = "Field `OEPINT` writer - OUT endpoints interrupt mask"] -pub type OEPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type OEPINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IISOIXFRM` reader - Incomplete isochronous IN transfer mask"] -pub type IISOIXFRM_R = crate::BitReader; +pub type IISOIXFRM_R = crate::BitReader; #[doc = "Field `IISOIXFRM` writer - Incomplete isochronous IN transfer mask"] -pub type IISOIXFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type IISOIXFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PXFRM_IISOOXFRM` reader - Incomplete periodic transfer mask"] -pub type PXFRM_IISOOXFRM_R = crate::BitReader; +pub type PXFRM_IISOOXFRM_R = crate::BitReader; #[doc = "Field `PXFRM_IISOOXFRM` writer - Incomplete periodic transfer mask"] -pub type PXFRM_IISOOXFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type PXFRM_IISOOXFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSUSPM` reader - Data fetch suspended mask"] -pub type FSUSPM_R = crate::BitReader; +pub type FSUSPM_R = crate::BitReader; #[doc = "Field `FSUSPM` writer - Data fetch suspended mask"] -pub type FSUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type FSUSPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRTIM` reader - Host port interrupt mask"] -pub type PRTIM_R = crate::BitReader; +pub type PRTIM_R = crate::BitReader; #[doc = "Field `HCIM` reader - Host channels interrupt mask"] -pub type HCIM_R = crate::BitReader; +pub type HCIM_R = crate::BitReader; #[doc = "Field `HCIM` writer - Host channels interrupt mask"] -pub type HCIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type HCIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTXFEM` reader - Periodic TxFIFO empty mask"] -pub type PTXFEM_R = crate::BitReader; +pub type PTXFEM_R = crate::BitReader; #[doc = "Field `PTXFEM` writer - Periodic TxFIFO empty mask"] -pub type PTXFEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type PTXFEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CIDSCHGM` reader - Connector ID status change mask"] -pub type CIDSCHGM_R = crate::BitReader; +pub type CIDSCHGM_R = crate::BitReader; #[doc = "Field `CIDSCHGM` writer - Connector ID status change mask"] -pub type CIDSCHGM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type CIDSCHGM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISCINT` reader - Disconnect detected interrupt mask"] -pub type DISCINT_R = crate::BitReader; +pub type DISCINT_R = crate::BitReader; #[doc = "Field `DISCINT` writer - Disconnect detected interrupt mask"] -pub type DISCINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type DISCINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRQIM` reader - Session request/new session detected interrupt mask"] -pub type SRQIM_R = crate::BitReader; +pub type SRQIM_R = crate::BitReader; #[doc = "Field `SRQIM` writer - Session request/new session detected interrupt mask"] -pub type SRQIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type SRQIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WUIM` reader - Resume/remote wakeup detected interrupt mask"] -pub type WUIM_R = crate::BitReader; +pub type WUIM_R = crate::BitReader; #[doc = "Field `WUIM` writer - Resume/remote wakeup detected interrupt mask"] -pub type WUIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type WUIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - Mode mismatch interrupt mask"] #[inline(always)] @@ -268,176 +236,217 @@ impl R { WUIM_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GINTMSK") + .field("mmism", &format_args!("{}", self.mmism().bit())) + .field("otgint", &format_args!("{}", self.otgint().bit())) + .field("sofm", &format_args!("{}", self.sofm().bit())) + .field("rxflvlm", &format_args!("{}", self.rxflvlm().bit())) + .field("nptxfem", &format_args!("{}", self.nptxfem().bit())) + .field("ginakeffm", &format_args!("{}", self.ginakeffm().bit())) + .field("gonakeffm", &format_args!("{}", self.gonakeffm().bit())) + .field("esuspm", &format_args!("{}", self.esuspm().bit())) + .field("usbsuspm", &format_args!("{}", self.usbsuspm().bit())) + .field("usbrst", &format_args!("{}", self.usbrst().bit())) + .field("enumdnem", &format_args!("{}", self.enumdnem().bit())) + .field("isoodrpm", &format_args!("{}", self.isoodrpm().bit())) + .field("eopfm", &format_args!("{}", self.eopfm().bit())) + .field("epmism", &format_args!("{}", self.epmism().bit())) + .field("iepint", &format_args!("{}", self.iepint().bit())) + .field("oepint", &format_args!("{}", self.oepint().bit())) + .field("iisoixfrm", &format_args!("{}", self.iisoixfrm().bit())) + .field( + "pxfrm_iisooxfrm", + &format_args!("{}", self.pxfrm_iisooxfrm().bit()), + ) + .field("fsuspm", &format_args!("{}", self.fsuspm().bit())) + .field("prtim", &format_args!("{}", self.prtim().bit())) + .field("hcim", &format_args!("{}", self.hcim().bit())) + .field("ptxfem", &format_args!("{}", self.ptxfem().bit())) + .field("cidschgm", &format_args!("{}", self.cidschgm().bit())) + .field("discint", &format_args!("{}", self.discint().bit())) + .field("srqim", &format_args!("{}", self.srqim().bit())) + .field("wuim", &format_args!("{}", self.wuim().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Mode mismatch interrupt mask"] #[inline(always)] #[must_use] - pub fn mmism(&mut self) -> MMISM_W<1> { + pub fn mmism(&mut self) -> MMISM_W { MMISM_W::new(self) } #[doc = "Bit 2 - OTG interrupt mask"] #[inline(always)] #[must_use] - pub fn otgint(&mut self) -> OTGINT_W<2> { + pub fn otgint(&mut self) -> OTGINT_W { OTGINT_W::new(self) } #[doc = "Bit 3 - Start of frame mask"] #[inline(always)] #[must_use] - pub fn sofm(&mut self) -> SOFM_W<3> { + pub fn sofm(&mut self) -> SOFM_W { SOFM_W::new(self) } #[doc = "Bit 4 - Receive FIFO nonempty mask"] #[inline(always)] #[must_use] - pub fn rxflvlm(&mut self) -> RXFLVLM_W<4> { + pub fn rxflvlm(&mut self) -> RXFLVLM_W { RXFLVLM_W::new(self) } #[doc = "Bit 5 - Nonperiodic TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn nptxfem(&mut self) -> NPTXFEM_W<5> { + pub fn nptxfem(&mut self) -> NPTXFEM_W { NPTXFEM_W::new(self) } #[doc = "Bit 6 - Global nonperiodic IN NAK effective mask"] #[inline(always)] #[must_use] - pub fn ginakeffm(&mut self) -> GINAKEFFM_W<6> { + pub fn ginakeffm(&mut self) -> GINAKEFFM_W { GINAKEFFM_W::new(self) } #[doc = "Bit 7 - Global OUT NAK effective mask"] #[inline(always)] #[must_use] - pub fn gonakeffm(&mut self) -> GONAKEFFM_W<7> { + pub fn gonakeffm(&mut self) -> GONAKEFFM_W { GONAKEFFM_W::new(self) } #[doc = "Bit 10 - Early suspend mask"] #[inline(always)] #[must_use] - pub fn esuspm(&mut self) -> ESUSPM_W<10> { + pub fn esuspm(&mut self) -> ESUSPM_W { ESUSPM_W::new(self) } #[doc = "Bit 11 - USB suspend mask"] #[inline(always)] #[must_use] - pub fn usbsuspm(&mut self) -> USBSUSPM_W<11> { + pub fn usbsuspm(&mut self) -> USBSUSPM_W { USBSUSPM_W::new(self) } #[doc = "Bit 12 - USB reset mask"] #[inline(always)] #[must_use] - pub fn usbrst(&mut self) -> USBRST_W<12> { + pub fn usbrst(&mut self) -> USBRST_W { USBRST_W::new(self) } #[doc = "Bit 13 - Enumeration done mask"] #[inline(always)] #[must_use] - pub fn enumdnem(&mut self) -> ENUMDNEM_W<13> { + pub fn enumdnem(&mut self) -> ENUMDNEM_W { ENUMDNEM_W::new(self) } #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt mask"] #[inline(always)] #[must_use] - pub fn isoodrpm(&mut self) -> ISOODRPM_W<14> { + pub fn isoodrpm(&mut self) -> ISOODRPM_W { ISOODRPM_W::new(self) } #[doc = "Bit 15 - End of periodic frame interrupt mask"] #[inline(always)] #[must_use] - pub fn eopfm(&mut self) -> EOPFM_W<15> { + pub fn eopfm(&mut self) -> EOPFM_W { EOPFM_W::new(self) } #[doc = "Bit 17 - Endpoint mismatch interrupt mask"] #[inline(always)] #[must_use] - pub fn epmism(&mut self) -> EPMISM_W<17> { + pub fn epmism(&mut self) -> EPMISM_W { EPMISM_W::new(self) } #[doc = "Bit 18 - IN endpoints interrupt mask"] #[inline(always)] #[must_use] - pub fn iepint(&mut self) -> IEPINT_W<18> { + pub fn iepint(&mut self) -> IEPINT_W { IEPINT_W::new(self) } #[doc = "Bit 19 - OUT endpoints interrupt mask"] #[inline(always)] #[must_use] - pub fn oepint(&mut self) -> OEPINT_W<19> { + pub fn oepint(&mut self) -> OEPINT_W { OEPINT_W::new(self) } #[doc = "Bit 20 - Incomplete isochronous IN transfer mask"] #[inline(always)] #[must_use] - pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<20> { + pub fn iisoixfrm(&mut self) -> IISOIXFRM_W { IISOIXFRM_W::new(self) } #[doc = "Bit 21 - Incomplete periodic transfer mask"] #[inline(always)] #[must_use] - pub fn pxfrm_iisooxfrm(&mut self) -> PXFRM_IISOOXFRM_W<21> { + pub fn pxfrm_iisooxfrm(&mut self) -> PXFRM_IISOOXFRM_W { PXFRM_IISOOXFRM_W::new(self) } #[doc = "Bit 22 - Data fetch suspended mask"] #[inline(always)] #[must_use] - pub fn fsuspm(&mut self) -> FSUSPM_W<22> { + pub fn fsuspm(&mut self) -> FSUSPM_W { FSUSPM_W::new(self) } #[doc = "Bit 25 - Host channels interrupt mask"] #[inline(always)] #[must_use] - pub fn hcim(&mut self) -> HCIM_W<25> { + pub fn hcim(&mut self) -> HCIM_W { HCIM_W::new(self) } #[doc = "Bit 26 - Periodic TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn ptxfem(&mut self) -> PTXFEM_W<26> { + pub fn ptxfem(&mut self) -> PTXFEM_W { PTXFEM_W::new(self) } #[doc = "Bit 28 - Connector ID status change mask"] #[inline(always)] #[must_use] - pub fn cidschgm(&mut self) -> CIDSCHGM_W<28> { + pub fn cidschgm(&mut self) -> CIDSCHGM_W { CIDSCHGM_W::new(self) } #[doc = "Bit 29 - Disconnect detected interrupt mask"] #[inline(always)] #[must_use] - pub fn discint(&mut self) -> DISCINT_W<29> { + pub fn discint(&mut self) -> DISCINT_W { DISCINT_W::new(self) } #[doc = "Bit 30 - Session request/new session detected interrupt mask"] #[inline(always)] #[must_use] - pub fn srqim(&mut self) -> SRQIM_W<30> { + pub fn srqim(&mut self) -> SRQIM_W { SRQIM_W::new(self) } #[doc = "Bit 31 - Resume/remote wakeup detected interrupt mask"] #[inline(always)] #[must_use] - pub fn wuim(&mut self) -> WUIM_W<31> { + pub fn wuim(&mut self) -> WUIM_W { WUIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintmsk](index.html) module"] +#[doc = "OTG_HS interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GINTMSK_SPEC; impl crate::RegisterSpec for GINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gintmsk::R](R) reader structure"] -impl crate::Readable for GINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`gintmsk::R`](R) reader structure"] +impl crate::Readable for GINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gintmsk::W`](W) writer structure"] impl crate::Writable for GINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gintsts.rs b/crates/bcm2835-lpa/src/usb_otg_global/gintsts.rs index 4dd3aa9..513d718 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/gintsts.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/gintsts.rs @@ -1,121 +1,89 @@ #[doc = "Register `GINTSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GINTSTS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMOD` reader - Current mode of operation"] -pub type CMOD_R = crate::BitReader; +pub type CMOD_R = crate::BitReader; #[doc = "Field `MMIS` reader - Mode mismatch interrupt"] -pub type MMIS_R = crate::BitReader; +pub type MMIS_R = crate::BitReader; #[doc = "Field `MMIS` writer - Mode mismatch interrupt"] -pub type MMIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type MMIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OTGINT` reader - OTG interrupt"] -pub type OTGINT_R = crate::BitReader; +pub type OTGINT_R = crate::BitReader; #[doc = "Field `SOF` reader - Start of frame"] -pub type SOF_R = crate::BitReader; +pub type SOF_R = crate::BitReader; #[doc = "Field `SOF` writer - Start of frame"] -pub type SOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type SOF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFLVL` reader - RxFIFO nonempty"] -pub type RXFLVL_R = crate::BitReader; +pub type RXFLVL_R = crate::BitReader; #[doc = "Field `NPTXFE` reader - Nonperiodic TxFIFO empty"] -pub type NPTXFE_R = crate::BitReader; +pub type NPTXFE_R = crate::BitReader; #[doc = "Field `GINAKEFF` reader - Global IN nonperiodic NAK effective"] -pub type GINAKEFF_R = crate::BitReader; +pub type GINAKEFF_R = crate::BitReader; #[doc = "Field `BOUTNAKEFF` reader - Global OUT NAK effective"] -pub type BOUTNAKEFF_R = crate::BitReader; +pub type BOUTNAKEFF_R = crate::BitReader; #[doc = "Field `ESUSP` reader - Early suspend"] -pub type ESUSP_R = crate::BitReader; +pub type ESUSP_R = crate::BitReader; #[doc = "Field `ESUSP` writer - Early suspend"] -pub type ESUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type ESUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBSUSP` reader - USB suspend"] -pub type USBSUSP_R = crate::BitReader; +pub type USBSUSP_R = crate::BitReader; #[doc = "Field `USBSUSP` writer - USB suspend"] -pub type USBSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type USBSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBRST` reader - USB reset"] -pub type USBRST_R = crate::BitReader; +pub type USBRST_R = crate::BitReader; #[doc = "Field `USBRST` writer - USB reset"] -pub type USBRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type USBRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENUMDNE` reader - Enumeration done"] -pub type ENUMDNE_R = crate::BitReader; +pub type ENUMDNE_R = crate::BitReader; #[doc = "Field `ENUMDNE` writer - Enumeration done"] -pub type ENUMDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type ENUMDNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISOODRP` reader - Isochronous OUT packet dropped interrupt"] -pub type ISOODRP_R = crate::BitReader; +pub type ISOODRP_R = crate::BitReader; #[doc = "Field `ISOODRP` writer - Isochronous OUT packet dropped interrupt"] -pub type ISOODRP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type ISOODRP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOPF` reader - End of periodic frame interrupt"] -pub type EOPF_R = crate::BitReader; +pub type EOPF_R = crate::BitReader; #[doc = "Field `EOPF` writer - End of periodic frame interrupt"] -pub type EOPF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type EOPF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IEPINT` reader - IN endpoint interrupt"] -pub type IEPINT_R = crate::BitReader; +pub type IEPINT_R = crate::BitReader; #[doc = "Field `OEPINT` reader - OUT endpoint interrupt"] -pub type OEPINT_R = crate::BitReader; +pub type OEPINT_R = crate::BitReader; #[doc = "Field `IISOIXFR` reader - Incomplete isochronous IN transfer"] -pub type IISOIXFR_R = crate::BitReader; +pub type IISOIXFR_R = crate::BitReader; #[doc = "Field `IISOIXFR` writer - Incomplete isochronous IN transfer"] -pub type IISOIXFR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type IISOIXFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PXFR_INCOMPISOOUT` reader - Incomplete periodic transfer"] -pub type PXFR_INCOMPISOOUT_R = crate::BitReader; +pub type PXFR_INCOMPISOOUT_R = crate::BitReader; #[doc = "Field `PXFR_INCOMPISOOUT` writer - Incomplete periodic transfer"] -pub type PXFR_INCOMPISOOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type PXFR_INCOMPISOOUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATAFSUSP` reader - Data fetch suspended"] -pub type DATAFSUSP_R = crate::BitReader; +pub type DATAFSUSP_R = crate::BitReader; #[doc = "Field `DATAFSUSP` writer - Data fetch suspended"] -pub type DATAFSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type DATAFSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HPRTINT` reader - Host port interrupt"] -pub type HPRTINT_R = crate::BitReader; +pub type HPRTINT_R = crate::BitReader; #[doc = "Field `HCINT` reader - Host channels interrupt"] -pub type HCINT_R = crate::BitReader; +pub type HCINT_R = crate::BitReader; #[doc = "Field `PTXFE` reader - Periodic TxFIFO empty"] -pub type PTXFE_R = crate::BitReader; +pub type PTXFE_R = crate::BitReader; #[doc = "Field `CIDSCHG` reader - Connector ID status change"] -pub type CIDSCHG_R = crate::BitReader; +pub type CIDSCHG_R = crate::BitReader; #[doc = "Field `CIDSCHG` writer - Connector ID status change"] -pub type CIDSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type CIDSCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISCINT` reader - Disconnect detected interrupt"] -pub type DISCINT_R = crate::BitReader; +pub type DISCINT_R = crate::BitReader; #[doc = "Field `DISCINT` writer - Disconnect detected interrupt"] -pub type DISCINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type DISCINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRQINT` reader - Session request/new session detected interrupt"] -pub type SRQINT_R = crate::BitReader; +pub type SRQINT_R = crate::BitReader; #[doc = "Field `SRQINT` writer - Session request/new session detected interrupt"] -pub type SRQINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type SRQINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WKUINT` reader - Resume/remote wakeup detected interrupt"] -pub type WKUINT_R = crate::BitReader; +pub type WKUINT_R = crate::BitReader; #[doc = "Field `WKUINT` writer - Resume/remote wakeup detected interrupt"] -pub type WKUINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type WKUINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Current mode of operation"] #[inline(always)] @@ -248,116 +216,157 @@ impl R { WKUINT_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GINTSTS") + .field("cmod", &format_args!("{}", self.cmod().bit())) + .field("mmis", &format_args!("{}", self.mmis().bit())) + .field("otgint", &format_args!("{}", self.otgint().bit())) + .field("sof", &format_args!("{}", self.sof().bit())) + .field("rxflvl", &format_args!("{}", self.rxflvl().bit())) + .field("nptxfe", &format_args!("{}", self.nptxfe().bit())) + .field("ginakeff", &format_args!("{}", self.ginakeff().bit())) + .field("boutnakeff", &format_args!("{}", self.boutnakeff().bit())) + .field("esusp", &format_args!("{}", self.esusp().bit())) + .field("usbsusp", &format_args!("{}", self.usbsusp().bit())) + .field("usbrst", &format_args!("{}", self.usbrst().bit())) + .field("enumdne", &format_args!("{}", self.enumdne().bit())) + .field("isoodrp", &format_args!("{}", self.isoodrp().bit())) + .field("eopf", &format_args!("{}", self.eopf().bit())) + .field("iepint", &format_args!("{}", self.iepint().bit())) + .field("oepint", &format_args!("{}", self.oepint().bit())) + .field("iisoixfr", &format_args!("{}", self.iisoixfr().bit())) + .field( + "pxfr_incompisoout", + &format_args!("{}", self.pxfr_incompisoout().bit()), + ) + .field("datafsusp", &format_args!("{}", self.datafsusp().bit())) + .field("hprtint", &format_args!("{}", self.hprtint().bit())) + .field("hcint", &format_args!("{}", self.hcint().bit())) + .field("ptxfe", &format_args!("{}", self.ptxfe().bit())) + .field("cidschg", &format_args!("{}", self.cidschg().bit())) + .field("discint", &format_args!("{}", self.discint().bit())) + .field("srqint", &format_args!("{}", self.srqint().bit())) + .field("wkuint", &format_args!("{}", self.wkuint().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Mode mismatch interrupt"] #[inline(always)] #[must_use] - pub fn mmis(&mut self) -> MMIS_W<1> { + pub fn mmis(&mut self) -> MMIS_W { MMIS_W::new(self) } #[doc = "Bit 3 - Start of frame"] #[inline(always)] #[must_use] - pub fn sof(&mut self) -> SOF_W<3> { + pub fn sof(&mut self) -> SOF_W { SOF_W::new(self) } #[doc = "Bit 10 - Early suspend"] #[inline(always)] #[must_use] - pub fn esusp(&mut self) -> ESUSP_W<10> { + pub fn esusp(&mut self) -> ESUSP_W { ESUSP_W::new(self) } #[doc = "Bit 11 - USB suspend"] #[inline(always)] #[must_use] - pub fn usbsusp(&mut self) -> USBSUSP_W<11> { + pub fn usbsusp(&mut self) -> USBSUSP_W { USBSUSP_W::new(self) } #[doc = "Bit 12 - USB reset"] #[inline(always)] #[must_use] - pub fn usbrst(&mut self) -> USBRST_W<12> { + pub fn usbrst(&mut self) -> USBRST_W { USBRST_W::new(self) } #[doc = "Bit 13 - Enumeration done"] #[inline(always)] #[must_use] - pub fn enumdne(&mut self) -> ENUMDNE_W<13> { + pub fn enumdne(&mut self) -> ENUMDNE_W { ENUMDNE_W::new(self) } #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt"] #[inline(always)] #[must_use] - pub fn isoodrp(&mut self) -> ISOODRP_W<14> { + pub fn isoodrp(&mut self) -> ISOODRP_W { ISOODRP_W::new(self) } #[doc = "Bit 15 - End of periodic frame interrupt"] #[inline(always)] #[must_use] - pub fn eopf(&mut self) -> EOPF_W<15> { + pub fn eopf(&mut self) -> EOPF_W { EOPF_W::new(self) } #[doc = "Bit 20 - Incomplete isochronous IN transfer"] #[inline(always)] #[must_use] - pub fn iisoixfr(&mut self) -> IISOIXFR_W<20> { + pub fn iisoixfr(&mut self) -> IISOIXFR_W { IISOIXFR_W::new(self) } #[doc = "Bit 21 - Incomplete periodic transfer"] #[inline(always)] #[must_use] - pub fn pxfr_incompisoout(&mut self) -> PXFR_INCOMPISOOUT_W<21> { + pub fn pxfr_incompisoout(&mut self) -> PXFR_INCOMPISOOUT_W { PXFR_INCOMPISOOUT_W::new(self) } #[doc = "Bit 22 - Data fetch suspended"] #[inline(always)] #[must_use] - pub fn datafsusp(&mut self) -> DATAFSUSP_W<22> { + pub fn datafsusp(&mut self) -> DATAFSUSP_W { DATAFSUSP_W::new(self) } #[doc = "Bit 28 - Connector ID status change"] #[inline(always)] #[must_use] - pub fn cidschg(&mut self) -> CIDSCHG_W<28> { + pub fn cidschg(&mut self) -> CIDSCHG_W { CIDSCHG_W::new(self) } #[doc = "Bit 29 - Disconnect detected interrupt"] #[inline(always)] #[must_use] - pub fn discint(&mut self) -> DISCINT_W<29> { + pub fn discint(&mut self) -> DISCINT_W { DISCINT_W::new(self) } #[doc = "Bit 30 - Session request/new session detected interrupt"] #[inline(always)] #[must_use] - pub fn srqint(&mut self) -> SRQINT_W<30> { + pub fn srqint(&mut self) -> SRQINT_W { SRQINT_W::new(self) } #[doc = "Bit 31 - Resume/remote wakeup detected interrupt"] #[inline(always)] #[must_use] - pub fn wkuint(&mut self) -> WKUINT_W<31> { + pub fn wkuint(&mut self) -> WKUINT_W { WKUINT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS core interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintsts](index.html) module"] +#[doc = "OTG_HS core interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gintsts::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gintsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GINTSTS_SPEC; impl crate::RegisterSpec for GINTSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gintsts::R](R) reader structure"] -impl crate::Readable for GINTSTS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gintsts::W](W) writer structure"] +#[doc = "`read()` method returns [`gintsts::R`](R) reader structure"] +impl crate::Readable for GINTSTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gintsts::W`](W) writer structure"] impl crate::Writable for GINTSTS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gnptxfsiz_host.rs b/crates/bcm2835-lpa/src/usb_otg_global/gnptxfsiz_host.rs index 89a5540..b2b7b4e 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/gnptxfsiz_host.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/gnptxfsiz_host.rs @@ -1,49 +1,15 @@ #[doc = "Register `GNPTXFSIZ_Host` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GNPTXFSIZ_Host` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NPTXFSA` reader - Nonperiodic transmit RAM start address"] -pub type NPTXFSA_R = crate::FieldReader; +pub type NPTXFSA_R = crate::FieldReader; #[doc = "Field `NPTXFSA` writer - Nonperiodic transmit RAM start address"] -pub type NPTXFSA_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GNPTXFSIZ_HOST_SPEC, u16, u16, 16, O>; +pub type NPTXFSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `NPTXFD` reader - Nonperiodic TxFIFO depth"] -pub type NPTXFD_R = crate::FieldReader; +pub type NPTXFD_R = crate::FieldReader; #[doc = "Field `NPTXFD` writer - Nonperiodic TxFIFO depth"] -pub type NPTXFD_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GNPTXFSIZ_HOST_SPEC, u16, u16, 16, O>; +pub type NPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Nonperiodic transmit RAM start address"] #[inline(always)] @@ -56,38 +22,52 @@ impl R { NPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GNPTXFSIZ_Host") + .field("nptxfsa", &format_args!("{}", self.nptxfsa().bits())) + .field("nptxfd", &format_args!("{}", self.nptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Nonperiodic transmit RAM start address"] #[inline(always)] #[must_use] - pub fn nptxfsa(&mut self) -> NPTXFSA_W<0> { + pub fn nptxfsa(&mut self) -> NPTXFSA_W { NPTXFSA_W::new(self) } #[doc = "Bits 16:31 - Nonperiodic TxFIFO depth"] #[inline(always)] #[must_use] - pub fn nptxfd(&mut self) -> NPTXFD_W<16> { + pub fn nptxfd(&mut self) -> NPTXFD_W { NPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxfsiz_host](index.html) module"] +#[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxfsiz_host::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gnptxfsiz_host::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GNPTXFSIZ_HOST_SPEC; impl crate::RegisterSpec for GNPTXFSIZ_HOST_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gnptxfsiz_host::R](R) reader structure"] -impl crate::Readable for GNPTXFSIZ_HOST_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gnptxfsiz_host::W](W) writer structure"] +#[doc = "`read()` method returns [`gnptxfsiz_host::R`](R) reader structure"] +impl crate::Readable for GNPTXFSIZ_HOST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gnptxfsiz_host::W`](W) writer structure"] impl crate::Writable for GNPTXFSIZ_HOST_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gnptxsts.rs b/crates/bcm2835-lpa/src/usb_otg_global/gnptxsts.rs index 65ffd12..2b32a6f 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/gnptxsts.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/gnptxsts.rs @@ -1,24 +1,11 @@ #[doc = "Register `GNPTXSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NPTXFSAV` reader - Nonperiodic TxFIFO space available"] -pub type NPTXFSAV_R = crate::FieldReader; +pub type NPTXFSAV_R = crate::FieldReader; #[doc = "Field `NPTQXSAV` reader - Nonperiodic transmit request queue space available"] -pub type NPTQXSAV_R = crate::FieldReader; +pub type NPTQXSAV_R = crate::FieldReader; #[doc = "Field `NPTXQTOP` reader - Top of the nonperiodic transmit request queue"] -pub type NPTXQTOP_R = crate::FieldReader; +pub type NPTXQTOP_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - Nonperiodic TxFIFO space available"] #[inline(always)] @@ -36,15 +23,27 @@ impl R { NPTXQTOP_R::new(((self.bits >> 24) & 0x7f) as u8) } } -#[doc = "OTG_HS nonperiodic transmit FIFO/queue status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxsts](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GNPTXSTS") + .field("nptxfsav", &format_args!("{}", self.nptxfsav().bits())) + .field("nptqxsav", &format_args!("{}", self.nptqxsav().bits())) + .field("nptxqtop", &format_args!("{}", self.nptxqtop().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS nonperiodic transmit FIFO/queue status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxsts::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GNPTXSTS_SPEC; impl crate::RegisterSpec for GNPTXSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gnptxsts::R](R) reader structure"] -impl crate::Readable for GNPTXSTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gnptxsts::R`](R) reader structure"] +impl crate::Readable for GNPTXSTS_SPEC {} #[doc = "`reset()` method sets GNPTXSTS to value 0x0008_0200"] impl crate::Resettable for GNPTXSTS_SPEC { const RESET_VALUE: Self::Ux = 0x0008_0200; diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gotgctl.rs b/crates/bcm2835-lpa/src/usb_otg_global/gotgctl.rs index 6576636..36b3f21 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/gotgctl.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/gotgctl.rs @@ -1,67 +1,35 @@ #[doc = "Register `GOTGCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GOTGCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SRQSCS` reader - Session request success"] -pub type SRQSCS_R = crate::BitReader; +pub type SRQSCS_R = crate::BitReader; #[doc = "Field `SRQ` reader - Session request"] -pub type SRQ_R = crate::BitReader; +pub type SRQ_R = crate::BitReader; #[doc = "Field `SRQ` writer - Session request"] -pub type SRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +pub type SRQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HNGSCS` reader - Host negotiation success"] -pub type HNGSCS_R = crate::BitReader; +pub type HNGSCS_R = crate::BitReader; #[doc = "Field `HNPRQ` reader - HNP request"] -pub type HNPRQ_R = crate::BitReader; +pub type HNPRQ_R = crate::BitReader; #[doc = "Field `HNPRQ` writer - HNP request"] -pub type HNPRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +pub type HNPRQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HSHNPEN` reader - Host set HNP enable"] -pub type HSHNPEN_R = crate::BitReader; +pub type HSHNPEN_R = crate::BitReader; #[doc = "Field `HSHNPEN` writer - Host set HNP enable"] -pub type HSHNPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +pub type HSHNPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DHNPEN` reader - Device HNP enabled"] -pub type DHNPEN_R = crate::BitReader; +pub type DHNPEN_R = crate::BitReader; #[doc = "Field `DHNPEN` writer - Device HNP enabled"] -pub type DHNPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +pub type DHNPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CIDSTS` reader - Connector ID status"] -pub type CIDSTS_R = crate::BitReader; +pub type CIDSTS_R = crate::BitReader; #[doc = "Field `DBCT` reader - Long/short debounce time"] -pub type DBCT_R = crate::BitReader; +pub type DBCT_R = crate::BitReader; #[doc = "Field `ASVLD` reader - A-session valid"] -pub type ASVLD_R = crate::BitReader; +pub type ASVLD_R = crate::BitReader; #[doc = "Field `BSVLD` reader - B-session valid"] -pub type BSVLD_R = crate::BitReader; +pub type BSVLD_R = crate::BitReader; impl R { #[doc = "Bit 0 - Session request success"] #[inline(always)] @@ -114,50 +82,72 @@ impl R { BSVLD_R::new(((self.bits >> 19) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GOTGCTL") + .field("srqscs", &format_args!("{}", self.srqscs().bit())) + .field("srq", &format_args!("{}", self.srq().bit())) + .field("hngscs", &format_args!("{}", self.hngscs().bit())) + .field("hnprq", &format_args!("{}", self.hnprq().bit())) + .field("hshnpen", &format_args!("{}", self.hshnpen().bit())) + .field("dhnpen", &format_args!("{}", self.dhnpen().bit())) + .field("cidsts", &format_args!("{}", self.cidsts().bit())) + .field("dbct", &format_args!("{}", self.dbct().bit())) + .field("asvld", &format_args!("{}", self.asvld().bit())) + .field("bsvld", &format_args!("{}", self.bsvld().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Session request"] #[inline(always)] #[must_use] - pub fn srq(&mut self) -> SRQ_W<1> { + pub fn srq(&mut self) -> SRQ_W { SRQ_W::new(self) } #[doc = "Bit 9 - HNP request"] #[inline(always)] #[must_use] - pub fn hnprq(&mut self) -> HNPRQ_W<9> { + pub fn hnprq(&mut self) -> HNPRQ_W { HNPRQ_W::new(self) } #[doc = "Bit 10 - Host set HNP enable"] #[inline(always)] #[must_use] - pub fn hshnpen(&mut self) -> HSHNPEN_W<10> { + pub fn hshnpen(&mut self) -> HSHNPEN_W { HSHNPEN_W::new(self) } #[doc = "Bit 11 - Device HNP enabled"] #[inline(always)] #[must_use] - pub fn dhnpen(&mut self) -> DHNPEN_W<11> { + pub fn dhnpen(&mut self) -> DHNPEN_W { DHNPEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgctl](index.html) module"] +#[doc = "OTG_HS control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gotgctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gotgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GOTGCTL_SPEC; impl crate::RegisterSpec for GOTGCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gotgctl::R](R) reader structure"] -impl crate::Readable for GOTGCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gotgctl::W](W) writer structure"] +#[doc = "`read()` method returns [`gotgctl::R`](R) reader structure"] +impl crate::Readable for GOTGCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gotgctl::W`](W) writer structure"] impl crate::Writable for GOTGCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gotgint.rs b/crates/bcm2835-lpa/src/usb_otg_global/gotgint.rs index b2c3ab9..a44613f 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/gotgint.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/gotgint.rs @@ -1,63 +1,31 @@ #[doc = "Register `GOTGINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GOTGINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SEDET` reader - Session end detected"] -pub type SEDET_R = crate::BitReader; +pub type SEDET_R = crate::BitReader; #[doc = "Field `SEDET` writer - Session end detected"] -pub type SEDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type SEDET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRSSCHG` reader - Session request success status change"] -pub type SRSSCHG_R = crate::BitReader; +pub type SRSSCHG_R = crate::BitReader; #[doc = "Field `SRSSCHG` writer - Session request success status change"] -pub type SRSSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type SRSSCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HNSSCHG` reader - Host negotiation success status change"] -pub type HNSSCHG_R = crate::BitReader; +pub type HNSSCHG_R = crate::BitReader; #[doc = "Field `HNSSCHG` writer - Host negotiation success status change"] -pub type HNSSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type HNSSCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HNGDET` reader - Host negotiation detected"] -pub type HNGDET_R = crate::BitReader; +pub type HNGDET_R = crate::BitReader; #[doc = "Field `HNGDET` writer - Host negotiation detected"] -pub type HNGDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type HNGDET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ADTOCHG` reader - A-device timeout change"] -pub type ADTOCHG_R = crate::BitReader; +pub type ADTOCHG_R = crate::BitReader; #[doc = "Field `ADTOCHG` writer - A-device timeout change"] -pub type ADTOCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type ADTOCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DBCDNE` reader - Debounce done"] -pub type DBCDNE_R = crate::BitReader; +pub type DBCDNE_R = crate::BitReader; #[doc = "Field `DBCDNE` writer - Debounce done"] -pub type DBCDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type DBCDNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 2 - Session end detected"] #[inline(always)] @@ -90,62 +58,80 @@ impl R { DBCDNE_R::new(((self.bits >> 19) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GOTGINT") + .field("sedet", &format_args!("{}", self.sedet().bit())) + .field("srsschg", &format_args!("{}", self.srsschg().bit())) + .field("hnsschg", &format_args!("{}", self.hnsschg().bit())) + .field("hngdet", &format_args!("{}", self.hngdet().bit())) + .field("adtochg", &format_args!("{}", self.adtochg().bit())) + .field("dbcdne", &format_args!("{}", self.dbcdne().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 2 - Session end detected"] #[inline(always)] #[must_use] - pub fn sedet(&mut self) -> SEDET_W<2> { + pub fn sedet(&mut self) -> SEDET_W { SEDET_W::new(self) } #[doc = "Bit 8 - Session request success status change"] #[inline(always)] #[must_use] - pub fn srsschg(&mut self) -> SRSSCHG_W<8> { + pub fn srsschg(&mut self) -> SRSSCHG_W { SRSSCHG_W::new(self) } #[doc = "Bit 9 - Host negotiation success status change"] #[inline(always)] #[must_use] - pub fn hnsschg(&mut self) -> HNSSCHG_W<9> { + pub fn hnsschg(&mut self) -> HNSSCHG_W { HNSSCHG_W::new(self) } #[doc = "Bit 17 - Host negotiation detected"] #[inline(always)] #[must_use] - pub fn hngdet(&mut self) -> HNGDET_W<17> { + pub fn hngdet(&mut self) -> HNGDET_W { HNGDET_W::new(self) } #[doc = "Bit 18 - A-device timeout change"] #[inline(always)] #[must_use] - pub fn adtochg(&mut self) -> ADTOCHG_W<18> { + pub fn adtochg(&mut self) -> ADTOCHG_W { ADTOCHG_W::new(self) } #[doc = "Bit 19 - Debounce done"] #[inline(always)] #[must_use] - pub fn dbcdne(&mut self) -> DBCDNE_W<19> { + pub fn dbcdne(&mut self) -> DBCDNE_W { DBCDNE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgint](index.html) module"] +#[doc = "OTG_HS interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gotgint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gotgint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GOTGINT_SPEC; impl crate::RegisterSpec for GOTGINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gotgint::R](R) reader structure"] -impl crate::Readable for GOTGINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gotgint::W](W) writer structure"] +#[doc = "`read()` method returns [`gotgint::R`](R) reader structure"] +impl crate::Readable for GOTGINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gotgint::W`](W) writer structure"] impl crate::Writable for GOTGINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/grstctl.rs b/crates/bcm2835-lpa/src/usb_otg_global/grstctl.rs index c3f83dc..799d4ca 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/grstctl.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/grstctl.rs @@ -1,67 +1,35 @@ #[doc = "Register `GRSTCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GRSTCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CSRST` reader - Core soft reset"] -pub type CSRST_R = crate::BitReader; +pub type CSRST_R = crate::BitReader; #[doc = "Field `CSRST` writer - Core soft reset"] -pub type CSRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type CSRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HSRST` reader - HCLK soft reset"] -pub type HSRST_R = crate::BitReader; +pub type HSRST_R = crate::BitReader; #[doc = "Field `HSRST` writer - HCLK soft reset"] -pub type HSRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type HSRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FCRST` reader - Host frame counter reset"] -pub type FCRST_R = crate::BitReader; +pub type FCRST_R = crate::BitReader; #[doc = "Field `FCRST` writer - Host frame counter reset"] -pub type FCRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type FCRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFFLSH` reader - RxFIFO flush"] -pub type RXFFLSH_R = crate::BitReader; +pub type RXFFLSH_R = crate::BitReader; #[doc = "Field `RXFFLSH` writer - RxFIFO flush"] -pub type RXFFLSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type RXFFLSH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFFLSH` reader - TxFIFO flush"] -pub type TXFFLSH_R = crate::BitReader; +pub type TXFFLSH_R = crate::BitReader; #[doc = "Field `TXFFLSH` writer - TxFIFO flush"] -pub type TXFFLSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type TXFFLSH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFNUM` reader - TxFIFO number"] -pub type TXFNUM_R = crate::FieldReader; +pub type TXFNUM_R = crate::FieldReader; #[doc = "Field `TXFNUM` writer - TxFIFO number"] -pub type TXFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GRSTCTL_SPEC, u8, u8, 5, O>; +pub type TXFNUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `DMAREQ` reader - DMA request signal"] -pub type DMAREQ_R = crate::BitReader; +pub type DMAREQ_R = crate::BitReader; #[doc = "Field `AHBIDL` reader - AHB master idle"] -pub type AHBIDL_R = crate::BitReader; +pub type AHBIDL_R = crate::BitReader; impl R { #[doc = "Bit 0 - Core soft reset"] #[inline(always)] @@ -104,62 +72,82 @@ impl R { AHBIDL_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRSTCTL") + .field("csrst", &format_args!("{}", self.csrst().bit())) + .field("hsrst", &format_args!("{}", self.hsrst().bit())) + .field("fcrst", &format_args!("{}", self.fcrst().bit())) + .field("rxfflsh", &format_args!("{}", self.rxfflsh().bit())) + .field("txfflsh", &format_args!("{}", self.txfflsh().bit())) + .field("txfnum", &format_args!("{}", self.txfnum().bits())) + .field("dmareq", &format_args!("{}", self.dmareq().bit())) + .field("ahbidl", &format_args!("{}", self.ahbidl().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Core soft reset"] #[inline(always)] #[must_use] - pub fn csrst(&mut self) -> CSRST_W<0> { + pub fn csrst(&mut self) -> CSRST_W { CSRST_W::new(self) } #[doc = "Bit 1 - HCLK soft reset"] #[inline(always)] #[must_use] - pub fn hsrst(&mut self) -> HSRST_W<1> { + pub fn hsrst(&mut self) -> HSRST_W { HSRST_W::new(self) } #[doc = "Bit 2 - Host frame counter reset"] #[inline(always)] #[must_use] - pub fn fcrst(&mut self) -> FCRST_W<2> { + pub fn fcrst(&mut self) -> FCRST_W { FCRST_W::new(self) } #[doc = "Bit 4 - RxFIFO flush"] #[inline(always)] #[must_use] - pub fn rxfflsh(&mut self) -> RXFFLSH_W<4> { + pub fn rxfflsh(&mut self) -> RXFFLSH_W { RXFFLSH_W::new(self) } #[doc = "Bit 5 - TxFIFO flush"] #[inline(always)] #[must_use] - pub fn txfflsh(&mut self) -> TXFFLSH_W<5> { + pub fn txfflsh(&mut self) -> TXFFLSH_W { TXFFLSH_W::new(self) } #[doc = "Bits 6:10 - TxFIFO number"] #[inline(always)] #[must_use] - pub fn txfnum(&mut self) -> TXFNUM_W<6> { + pub fn txfnum(&mut self) -> TXFNUM_W { TXFNUM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS reset register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grstctl](index.html) module"] +#[doc = "OTG_HS reset register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grstctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grstctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRSTCTL_SPEC; impl crate::RegisterSpec for GRSTCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grstctl::R](R) reader structure"] -impl crate::Readable for GRSTCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [grstctl::W](W) writer structure"] +#[doc = "`read()` method returns [`grstctl::R`](R) reader structure"] +impl crate::Readable for GRSTCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`grstctl::W`](W) writer structure"] impl crate::Writable for GRSTCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/grxfsiz.rs b/crates/bcm2835-lpa/src/usb_otg_global/grxfsiz.rs index ec6ba8c..b243ab8 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/grxfsiz.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/grxfsiz.rs @@ -1,43 +1,11 @@ #[doc = "Register `GRXFSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GRXFSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXFD` reader - RxFIFO depth"] -pub type RXFD_R = crate::FieldReader; +pub type RXFD_R = crate::FieldReader; #[doc = "Field `RXFD` writer - RxFIFO depth"] -pub type RXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GRXFSIZ_SPEC, u16, u16, 16, O>; +pub type RXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - RxFIFO depth"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { RXFD_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXFSIZ") + .field("rxfd", &format_args!("{}", self.rxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - RxFIFO depth"] #[inline(always)] #[must_use] - pub fn rxfd(&mut self) -> RXFD_W<0> { + pub fn rxfd(&mut self) -> RXFD_W { RXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS Receive FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxfsiz](index.html) module"] +#[doc = "OTG_HS Receive FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxfsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grxfsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXFSIZ_SPEC; impl crate::RegisterSpec for GRXFSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxfsiz::R](R) reader structure"] -impl crate::Readable for GRXFSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [grxfsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`grxfsiz::R`](R) reader structure"] +impl crate::Readable for GRXFSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`grxfsiz::W`](W) writer structure"] impl crate::Writable for GRXFSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_host.rs b/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_host.rs index a0231ff..5e8d3bb 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_host.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_host.rs @@ -1,26 +1,13 @@ #[doc = "Register `GRXSTSP_Host` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CHNUM` reader - Channel number"] -pub type CHNUM_R = crate::FieldReader; +pub type CHNUM_R = crate::FieldReader; #[doc = "Field `BCNT` reader - Byte count"] -pub type BCNT_R = crate::FieldReader; +pub type BCNT_R = crate::FieldReader; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `PKTSTS` reader - Packet status"] -pub type PKTSTS_R = crate::FieldReader; +pub type PKTSTS_R = crate::FieldReader; impl R { #[doc = "Bits 0:3 - Channel number"] #[inline(always)] @@ -43,15 +30,28 @@ impl R { PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) } } -#[doc = "OTG_HS status read and pop register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsp_host](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXSTSP_Host") + .field("chnum", &format_args!("{}", self.chnum().bits())) + .field("bcnt", &format_args!("{}", self.bcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .field("pktsts", &format_args!("{}", self.pktsts().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS status read and pop register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp_host::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXSTSP_HOST_SPEC; impl crate::RegisterSpec for GRXSTSP_HOST_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxstsp_host::R](R) reader structure"] -impl crate::Readable for GRXSTSP_HOST_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`grxstsp_host::R`](R) reader structure"] +impl crate::Readable for GRXSTSP_HOST_SPEC {} #[doc = "`reset()` method sets GRXSTSP_Host to value 0"] impl crate::Resettable for GRXSTSP_HOST_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_peripheral.rs b/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_peripheral.rs index 5de1533..e28018e 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_peripheral.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/grxstsp_peripheral.rs @@ -1,28 +1,15 @@ #[doc = "Register `GRXSTSP_Peripheral` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EPNUM` reader - Endpoint number"] -pub type EPNUM_R = crate::FieldReader; +pub type EPNUM_R = crate::FieldReader; #[doc = "Field `BCNT` reader - Byte count"] -pub type BCNT_R = crate::FieldReader; +pub type BCNT_R = crate::FieldReader; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `PKTSTS` reader - Packet status"] -pub type PKTSTS_R = crate::FieldReader; +pub type PKTSTS_R = crate::FieldReader; #[doc = "Field `FRMNUM` reader - Frame number"] -pub type FRMNUM_R = crate::FieldReader; +pub type FRMNUM_R = crate::FieldReader; impl R { #[doc = "Bits 0:3 - Endpoint number"] #[inline(always)] @@ -50,15 +37,29 @@ impl R { FRMNUM_R::new(((self.bits >> 21) & 0x0f) as u8) } } -#[doc = "OTG_HS status read and pop register (peripheral mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsp_peripheral](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXSTSP_Peripheral") + .field("epnum", &format_args!("{}", self.epnum().bits())) + .field("bcnt", &format_args!("{}", self.bcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .field("pktsts", &format_args!("{}", self.pktsts().bits())) + .field("frmnum", &format_args!("{}", self.frmnum().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS status read and pop register (peripheral mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp_peripheral::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXSTSP_PERIPHERAL_SPEC; impl crate::RegisterSpec for GRXSTSP_PERIPHERAL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxstsp_peripheral::R](R) reader structure"] -impl crate::Readable for GRXSTSP_PERIPHERAL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`grxstsp_peripheral::R`](R) reader structure"] +impl crate::Readable for GRXSTSP_PERIPHERAL_SPEC {} #[doc = "`reset()` method sets GRXSTSP_Peripheral to value 0"] impl crate::Resettable for GRXSTSP_PERIPHERAL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_host.rs b/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_host.rs index 399a9f8..e9e1ba6 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_host.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_host.rs @@ -1,26 +1,13 @@ #[doc = "Register `GRXSTSR_Host` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CHNUM` reader - Channel number"] -pub type CHNUM_R = crate::FieldReader; +pub type CHNUM_R = crate::FieldReader; #[doc = "Field `BCNT` reader - Byte count"] -pub type BCNT_R = crate::FieldReader; +pub type BCNT_R = crate::FieldReader; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `PKTSTS` reader - Packet status"] -pub type PKTSTS_R = crate::FieldReader; +pub type PKTSTS_R = crate::FieldReader; impl R { #[doc = "Bits 0:3 - Channel number"] #[inline(always)] @@ -43,15 +30,28 @@ impl R { PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) } } -#[doc = "OTG_HS Receive status debug read register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsr_host](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXSTSR_Host") + .field("chnum", &format_args!("{}", self.chnum().bits())) + .field("bcnt", &format_args!("{}", self.bcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .field("pktsts", &format_args!("{}", self.pktsts().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS Receive status debug read register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr_host::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXSTSR_HOST_SPEC; impl crate::RegisterSpec for GRXSTSR_HOST_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxstsr_host::R](R) reader structure"] -impl crate::Readable for GRXSTSR_HOST_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`grxstsr_host::R`](R) reader structure"] +impl crate::Readable for GRXSTSR_HOST_SPEC {} #[doc = "`reset()` method sets GRXSTSR_Host to value 0"] impl crate::Resettable for GRXSTSR_HOST_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_peripheral.rs b/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_peripheral.rs index 89558d9..d6f8ca3 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_peripheral.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/grxstsr_peripheral.rs @@ -1,28 +1,15 @@ #[doc = "Register `GRXSTSR_Peripheral` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EPNUM` reader - Endpoint number"] -pub type EPNUM_R = crate::FieldReader; +pub type EPNUM_R = crate::FieldReader; #[doc = "Field `BCNT` reader - Byte count"] -pub type BCNT_R = crate::FieldReader; +pub type BCNT_R = crate::FieldReader; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `PKTSTS` reader - Packet status"] -pub type PKTSTS_R = crate::FieldReader; +pub type PKTSTS_R = crate::FieldReader; #[doc = "Field `FRMNUM` reader - Frame number"] -pub type FRMNUM_R = crate::FieldReader; +pub type FRMNUM_R = crate::FieldReader; impl R { #[doc = "Bits 0:3 - Endpoint number"] #[inline(always)] @@ -50,15 +37,29 @@ impl R { FRMNUM_R::new(((self.bits >> 21) & 0x0f) as u8) } } -#[doc = "OTG_HS Receive status debug read register (peripheral mode mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsr_peripheral](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXSTSR_Peripheral") + .field("epnum", &format_args!("{}", self.epnum().bits())) + .field("bcnt", &format_args!("{}", self.bcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .field("pktsts", &format_args!("{}", self.pktsts().bits())) + .field("frmnum", &format_args!("{}", self.frmnum().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS Receive status debug read register (peripheral mode mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr_peripheral::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXSTSR_PERIPHERAL_SPEC; impl crate::RegisterSpec for GRXSTSR_PERIPHERAL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxstsr_peripheral::R](R) reader structure"] -impl crate::Readable for GRXSTSR_PERIPHERAL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`grxstsr_peripheral::R`](R) reader structure"] +impl crate::Readable for GRXSTSR_PERIPHERAL_SPEC {} #[doc = "`reset()` method sets GRXSTSR_Peripheral to value 0"] impl crate::Resettable for GRXSTSR_PERIPHERAL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/usb_otg_global/gusbcfg.rs b/crates/bcm2835-lpa/src/usb_otg_global/gusbcfg.rs index a958441..b5f882e 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/gusbcfg.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/gusbcfg.rs @@ -1,43 +1,11 @@ #[doc = "Register `GUSBCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GUSBCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TOCAL` reader - FS timeout calibration"] -pub type TOCAL_R = crate::FieldReader; +pub type TOCAL_R = crate::FieldReader; #[doc = "Field `TOCAL` writer - FS timeout calibration"] -pub type TOCAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GUSBCFG_SPEC, u8, u8, 3, O>; +pub type TOCAL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `PHYIF` reader - PHY Interface width"] pub type PHYIF_R = crate::BitReader; #[doc = "PHY Interface width\n\nValue on reset: 0"] @@ -57,34 +25,37 @@ impl From for bool { impl PHYIF_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PHYIF_A { + pub const fn variant(&self) -> PHYIF_A { match self.bits { false => PHYIF_A::_8BIT, true => PHYIF_A::_16BIT, } } - #[doc = "Checks if the value of the field is `_8BIT`"] + #[doc = "`0`"] #[inline(always)] pub fn is_8bit(&self) -> bool { *self == PHYIF_A::_8BIT } - #[doc = "Checks if the value of the field is `_16BIT`"] + #[doc = "`1`"] #[inline(always)] pub fn is_16bit(&self) -> bool { *self == PHYIF_A::_16BIT } } #[doc = "Field `PHYIF` writer - PHY Interface width"] -pub type PHYIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYIF_A, O>; -impl<'a, const O: u8> PHYIF_W<'a, O> { +pub type PHYIF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PHYIF_A>; +impl<'a, REG, const O: u8> PHYIF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn _8bit(self) -> &'a mut W { + pub fn _8bit(self) -> &'a mut crate::W { self.variant(PHYIF_A::_8BIT) } #[doc = "`1`"] #[inline(always)] - pub fn _16bit(self) -> &'a mut W { + pub fn _16bit(self) -> &'a mut crate::W { self.variant(PHYIF_A::_16BIT) } } @@ -107,34 +78,37 @@ impl From for bool { impl PHYTYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PHYTYPE_A { + pub const fn variant(&self) -> PHYTYPE_A { match self.bits { false => PHYTYPE_A::UTMI, true => PHYTYPE_A::ULPI, } } - #[doc = "Checks if the value of the field is `UTMI`"] + #[doc = "`0`"] #[inline(always)] pub fn is_utmi(&self) -> bool { *self == PHYTYPE_A::UTMI } - #[doc = "Checks if the value of the field is `ULPI`"] + #[doc = "`1`"] #[inline(always)] pub fn is_ulpi(&self) -> bool { *self == PHYTYPE_A::ULPI } } #[doc = "Field `PHYTYPE` writer - PHY Type"] -pub type PHYTYPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYTYPE_A, O>; -impl<'a, const O: u8> PHYTYPE_W<'a, O> { +pub type PHYTYPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PHYTYPE_A>; +impl<'a, REG, const O: u8> PHYTYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn utmi(self) -> &'a mut W { + pub fn utmi(self) -> &'a mut crate::W { self.variant(PHYTYPE_A::UTMI) } #[doc = "`1`"] #[inline(always)] - pub fn ulpi(self) -> &'a mut W { + pub fn ulpi(self) -> &'a mut crate::W { self.variant(PHYTYPE_A::ULPI) } } @@ -157,34 +131,37 @@ impl From for bool { impl FSIF_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSIF_A { + pub const fn variant(&self) -> FSIF_A { match self.bits { false => FSIF_A::_6PIN, true => FSIF_A::_3PIN, } } - #[doc = "Checks if the value of the field is `_6PIN`"] + #[doc = "`0`"] #[inline(always)] pub fn is_6pin(&self) -> bool { *self == FSIF_A::_6PIN } - #[doc = "Checks if the value of the field is `_3PIN`"] + #[doc = "`1`"] #[inline(always)] pub fn is_3pin(&self) -> bool { *self == FSIF_A::_3PIN } } #[doc = "Field `FSIF` writer - Full speed interface"] -pub type FSIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, FSIF_A, O>; -impl<'a, const O: u8> FSIF_W<'a, O> { +pub type FSIF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, FSIF_A>; +impl<'a, REG, const O: u8> FSIF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn _6pin(self) -> &'a mut W { + pub fn _6pin(self) -> &'a mut crate::W { self.variant(FSIF_A::_6PIN) } #[doc = "`1`"] #[inline(always)] - pub fn _3pin(self) -> &'a mut W { + pub fn _3pin(self) -> &'a mut crate::W { self.variant(FSIF_A::_3PIN) } } @@ -207,34 +184,37 @@ impl From for bool { impl PHYSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PHYSEL_A { + pub const fn variant(&self) -> PHYSEL_A { match self.bits { false => PHYSEL_A::USB20, true => PHYSEL_A::USB11, } } - #[doc = "Checks if the value of the field is `USB20`"] + #[doc = "`0`"] #[inline(always)] pub fn is_usb20(&self) -> bool { *self == PHYSEL_A::USB20 } - #[doc = "Checks if the value of the field is `USB11`"] + #[doc = "`1`"] #[inline(always)] pub fn is_usb11(&self) -> bool { *self == PHYSEL_A::USB11 } } #[doc = "Field `PHYSEL` writer - Transceiver select"] -pub type PHYSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYSEL_A, O>; -impl<'a, const O: u8> PHYSEL_W<'a, O> { +pub type PHYSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PHYSEL_A>; +impl<'a, REG, const O: u8> PHYSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn usb20(self) -> &'a mut W { + pub fn usb20(self) -> &'a mut crate::W { self.variant(PHYSEL_A::USB20) } #[doc = "`1`"] #[inline(always)] - pub fn usb11(self) -> &'a mut W { + pub fn usb11(self) -> &'a mut crate::W { self.variant(PHYSEL_A::USB11) } } @@ -257,101 +237,104 @@ impl From for bool { impl DDRSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DDRSEL_A { + pub const fn variant(&self) -> DDRSEL_A { match self.bits { false => DDRSEL_A::SINGLE, true => DDRSEL_A::DOUBLE, } } - #[doc = "Checks if the value of the field is `SINGLE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_single(&self) -> bool { *self == DDRSEL_A::SINGLE } - #[doc = "Checks if the value of the field is `DOUBLE`"] + #[doc = "`1`"] #[inline(always)] pub fn is_double(&self) -> bool { *self == DDRSEL_A::DOUBLE } } #[doc = "Field `DDRSEL` writer - ULPI data rate"] -pub type DDRSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, DDRSEL_A, O>; -impl<'a, const O: u8> DDRSEL_W<'a, O> { +pub type DDRSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DDRSEL_A>; +impl<'a, REG, const O: u8> DDRSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn single(self) -> &'a mut W { + pub fn single(self) -> &'a mut crate::W { self.variant(DDRSEL_A::SINGLE) } #[doc = "`1`"] #[inline(always)] - pub fn double(self) -> &'a mut W { + pub fn double(self) -> &'a mut crate::W { self.variant(DDRSEL_A::DOUBLE) } } #[doc = "Field `SRPCAP` reader - SRP-capable"] -pub type SRPCAP_R = crate::BitReader; +pub type SRPCAP_R = crate::BitReader; #[doc = "Field `SRPCAP` writer - SRP-capable"] -pub type SRPCAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type SRPCAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HNPCAP` reader - HNP-capable"] -pub type HNPCAP_R = crate::BitReader; +pub type HNPCAP_R = crate::BitReader; #[doc = "Field `HNPCAP` writer - HNP-capable"] -pub type HNPCAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type HNPCAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TRDT` reader - USB turnaround time"] -pub type TRDT_R = crate::FieldReader; +pub type TRDT_R = crate::FieldReader; #[doc = "Field `TRDT` writer - USB turnaround time"] -pub type TRDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GUSBCFG_SPEC, u8, u8, 4, O>; +pub type TRDT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `PHYLPCS` reader - PHY Low-power clock select"] -pub type PHYLPCS_R = crate::BitReader; +pub type PHYLPCS_R = crate::BitReader; #[doc = "Field `PHYLPCS` writer - PHY Low-power clock select"] -pub type PHYLPCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type PHYLPCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIFSLS` reader - ULPI FS/LS select"] -pub type ULPIFSLS_R = crate::BitReader; +pub type ULPIFSLS_R = crate::BitReader; #[doc = "Field `ULPIFSLS` writer - ULPI FS/LS select"] -pub type ULPIFSLS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIFSLS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIAR` reader - ULPI Auto-resume"] -pub type ULPIAR_R = crate::BitReader; +pub type ULPIAR_R = crate::BitReader; #[doc = "Field `ULPIAR` writer - ULPI Auto-resume"] -pub type ULPIAR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPICSM` reader - ULPI Clock SuspendM"] -pub type ULPICSM_R = crate::BitReader; +pub type ULPICSM_R = crate::BitReader; #[doc = "Field `ULPICSM` writer - ULPI Clock SuspendM"] -pub type ULPICSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPICSM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIEVBUSD` reader - ULPI External VBUS Drive"] -pub type ULPIEVBUSD_R = crate::BitReader; +pub type ULPIEVBUSD_R = crate::BitReader; #[doc = "Field `ULPIEVBUSD` writer - ULPI External VBUS Drive"] -pub type ULPIEVBUSD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIEVBUSD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIEVBUSI` reader - ULPI external VBUS indicator"] -pub type ULPIEVBUSI_R = crate::BitReader; +pub type ULPIEVBUSI_R = crate::BitReader; #[doc = "Field `ULPIEVBUSI` writer - ULPI external VBUS indicator"] -pub type ULPIEVBUSI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIEVBUSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSDPS` reader - TermSel DLine pulsing selection"] -pub type TSDPS_R = crate::BitReader; +pub type TSDPS_R = crate::BitReader; #[doc = "Field `TSDPS` writer - TermSel DLine pulsing selection"] -pub type TSDPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type TSDPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCCI` reader - Indicator complement"] -pub type PCCI_R = crate::BitReader; +pub type PCCI_R = crate::BitReader; #[doc = "Field `PCCI` writer - Indicator complement"] -pub type PCCI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type PCCI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTCI` reader - Indicator pass through"] -pub type PTCI_R = crate::BitReader; +pub type PTCI_R = crate::BitReader; #[doc = "Field `PTCI` writer - Indicator pass through"] -pub type PTCI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type PTCI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIIPD` reader - ULPI interface protect disable"] -pub type ULPIIPD_R = crate::BitReader; +pub type ULPIIPD_R = crate::BitReader; #[doc = "Field `ULPIIPD` writer - ULPI interface protect disable"] -pub type ULPIIPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIIPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FHMOD` reader - Forced host mode"] -pub type FHMOD_R = crate::BitReader; +pub type FHMOD_R = crate::BitReader; #[doc = "Field `FHMOD` writer - Forced host mode"] -pub type FHMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type FHMOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FDMOD` reader - Forced peripheral mode"] -pub type FDMOD_R = crate::BitReader; +pub type FDMOD_R = crate::BitReader; #[doc = "Field `FDMOD` writer - Forced peripheral mode"] -pub type FDMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type FDMOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTXPKT` reader - Corrupt Tx packet"] -pub type CTXPKT_R = crate::BitReader; +pub type CTXPKT_R = crate::BitReader; #[doc = "Field `CTXPKT` writer - Corrupt Tx packet"] -pub type CTXPKT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type CTXPKT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:2 - FS timeout calibration"] #[inline(always)] @@ -464,158 +447,192 @@ impl R { CTXPKT_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GUSBCFG") + .field("tocal", &format_args!("{}", self.tocal().bits())) + .field("phyif", &format_args!("{}", self.phyif().bit())) + .field("phytype", &format_args!("{}", self.phytype().bit())) + .field("fsif", &format_args!("{}", self.fsif().bit())) + .field("physel", &format_args!("{}", self.physel().bit())) + .field("ddrsel", &format_args!("{}", self.ddrsel().bit())) + .field("srpcap", &format_args!("{}", self.srpcap().bit())) + .field("hnpcap", &format_args!("{}", self.hnpcap().bit())) + .field("trdt", &format_args!("{}", self.trdt().bits())) + .field("phylpcs", &format_args!("{}", self.phylpcs().bit())) + .field("ulpifsls", &format_args!("{}", self.ulpifsls().bit())) + .field("ulpiar", &format_args!("{}", self.ulpiar().bit())) + .field("ulpicsm", &format_args!("{}", self.ulpicsm().bit())) + .field("ulpievbusd", &format_args!("{}", self.ulpievbusd().bit())) + .field("ulpievbusi", &format_args!("{}", self.ulpievbusi().bit())) + .field("tsdps", &format_args!("{}", self.tsdps().bit())) + .field("pcci", &format_args!("{}", self.pcci().bit())) + .field("ptci", &format_args!("{}", self.ptci().bit())) + .field("ulpiipd", &format_args!("{}", self.ulpiipd().bit())) + .field("fhmod", &format_args!("{}", self.fhmod().bit())) + .field("fdmod", &format_args!("{}", self.fdmod().bit())) + .field("ctxpkt", &format_args!("{}", self.ctxpkt().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - FS timeout calibration"] #[inline(always)] #[must_use] - pub fn tocal(&mut self) -> TOCAL_W<0> { + pub fn tocal(&mut self) -> TOCAL_W { TOCAL_W::new(self) } #[doc = "Bit 3 - PHY Interface width"] #[inline(always)] #[must_use] - pub fn phyif(&mut self) -> PHYIF_W<3> { + pub fn phyif(&mut self) -> PHYIF_W { PHYIF_W::new(self) } #[doc = "Bit 4 - PHY Type"] #[inline(always)] #[must_use] - pub fn phytype(&mut self) -> PHYTYPE_W<4> { + pub fn phytype(&mut self) -> PHYTYPE_W { PHYTYPE_W::new(self) } #[doc = "Bit 5 - Full speed interface"] #[inline(always)] #[must_use] - pub fn fsif(&mut self) -> FSIF_W<5> { + pub fn fsif(&mut self) -> FSIF_W { FSIF_W::new(self) } #[doc = "Bit 6 - Transceiver select"] #[inline(always)] #[must_use] - pub fn physel(&mut self) -> PHYSEL_W<6> { + pub fn physel(&mut self) -> PHYSEL_W { PHYSEL_W::new(self) } #[doc = "Bit 7 - ULPI data rate"] #[inline(always)] #[must_use] - pub fn ddrsel(&mut self) -> DDRSEL_W<7> { + pub fn ddrsel(&mut self) -> DDRSEL_W { DDRSEL_W::new(self) } #[doc = "Bit 8 - SRP-capable"] #[inline(always)] #[must_use] - pub fn srpcap(&mut self) -> SRPCAP_W<8> { + pub fn srpcap(&mut self) -> SRPCAP_W { SRPCAP_W::new(self) } #[doc = "Bit 9 - HNP-capable"] #[inline(always)] #[must_use] - pub fn hnpcap(&mut self) -> HNPCAP_W<9> { + pub fn hnpcap(&mut self) -> HNPCAP_W { HNPCAP_W::new(self) } #[doc = "Bits 10:13 - USB turnaround time"] #[inline(always)] #[must_use] - pub fn trdt(&mut self) -> TRDT_W<10> { + pub fn trdt(&mut self) -> TRDT_W { TRDT_W::new(self) } #[doc = "Bit 15 - PHY Low-power clock select"] #[inline(always)] #[must_use] - pub fn phylpcs(&mut self) -> PHYLPCS_W<15> { + pub fn phylpcs(&mut self) -> PHYLPCS_W { PHYLPCS_W::new(self) } #[doc = "Bit 17 - ULPI FS/LS select"] #[inline(always)] #[must_use] - pub fn ulpifsls(&mut self) -> ULPIFSLS_W<17> { + pub fn ulpifsls(&mut self) -> ULPIFSLS_W { ULPIFSLS_W::new(self) } #[doc = "Bit 18 - ULPI Auto-resume"] #[inline(always)] #[must_use] - pub fn ulpiar(&mut self) -> ULPIAR_W<18> { + pub fn ulpiar(&mut self) -> ULPIAR_W { ULPIAR_W::new(self) } #[doc = "Bit 19 - ULPI Clock SuspendM"] #[inline(always)] #[must_use] - pub fn ulpicsm(&mut self) -> ULPICSM_W<19> { + pub fn ulpicsm(&mut self) -> ULPICSM_W { ULPICSM_W::new(self) } #[doc = "Bit 20 - ULPI External VBUS Drive"] #[inline(always)] #[must_use] - pub fn ulpievbusd(&mut self) -> ULPIEVBUSD_W<20> { + pub fn ulpievbusd(&mut self) -> ULPIEVBUSD_W { ULPIEVBUSD_W::new(self) } #[doc = "Bit 21 - ULPI external VBUS indicator"] #[inline(always)] #[must_use] - pub fn ulpievbusi(&mut self) -> ULPIEVBUSI_W<21> { + pub fn ulpievbusi(&mut self) -> ULPIEVBUSI_W { ULPIEVBUSI_W::new(self) } #[doc = "Bit 22 - TermSel DLine pulsing selection"] #[inline(always)] #[must_use] - pub fn tsdps(&mut self) -> TSDPS_W<22> { + pub fn tsdps(&mut self) -> TSDPS_W { TSDPS_W::new(self) } #[doc = "Bit 23 - Indicator complement"] #[inline(always)] #[must_use] - pub fn pcci(&mut self) -> PCCI_W<23> { + pub fn pcci(&mut self) -> PCCI_W { PCCI_W::new(self) } #[doc = "Bit 24 - Indicator pass through"] #[inline(always)] #[must_use] - pub fn ptci(&mut self) -> PTCI_W<24> { + pub fn ptci(&mut self) -> PTCI_W { PTCI_W::new(self) } #[doc = "Bit 25 - ULPI interface protect disable"] #[inline(always)] #[must_use] - pub fn ulpiipd(&mut self) -> ULPIIPD_W<25> { + pub fn ulpiipd(&mut self) -> ULPIIPD_W { ULPIIPD_W::new(self) } #[doc = "Bit 29 - Forced host mode"] #[inline(always)] #[must_use] - pub fn fhmod(&mut self) -> FHMOD_W<29> { + pub fn fhmod(&mut self) -> FHMOD_W { FHMOD_W::new(self) } #[doc = "Bit 30 - Forced peripheral mode"] #[inline(always)] #[must_use] - pub fn fdmod(&mut self) -> FDMOD_W<30> { + pub fn fdmod(&mut self) -> FDMOD_W { FDMOD_W::new(self) } #[doc = "Bit 31 - Corrupt Tx packet"] #[inline(always)] #[must_use] - pub fn ctxpkt(&mut self) -> CTXPKT_W<31> { + pub fn ctxpkt(&mut self) -> CTXPKT_W { CTXPKT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS USB configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gusbcfg](index.html) module"] +#[doc = "OTG_HS USB configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gusbcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gusbcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GUSBCFG_SPEC; impl crate::RegisterSpec for GUSBCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gusbcfg::R](R) reader structure"] -impl crate::Readable for GUSBCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gusbcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`gusbcfg::R`](R) reader structure"] +impl crate::Readable for GUSBCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gusbcfg::W`](W) writer structure"] impl crate::Writable for GUSBCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/hptxfsiz.rs b/crates/bcm2835-lpa/src/usb_otg_global/hptxfsiz.rs index c50a180..cd99421 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/hptxfsiz.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/hptxfsiz.rs @@ -1,47 +1,15 @@ #[doc = "Register `HPTXFSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HPTXFSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PTXSA` reader - Host periodic TxFIFO start address"] -pub type PTXSA_R = crate::FieldReader; +pub type PTXSA_R = crate::FieldReader; #[doc = "Field `PTXSA` writer - Host periodic TxFIFO start address"] -pub type PTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXFSIZ_SPEC, u16, u16, 16, O>; +pub type PTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `PTXFD` reader - Host periodic TxFIFO depth"] -pub type PTXFD_R = crate::FieldReader; +pub type PTXFD_R = crate::FieldReader; #[doc = "Field `PTXFD` writer - Host periodic TxFIFO depth"] -pub type PTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXFSIZ_SPEC, u16, u16, 16, O>; +pub type PTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Host periodic TxFIFO start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { PTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HPTXFSIZ") + .field("ptxsa", &format_args!("{}", self.ptxsa().bits())) + .field("ptxfd", &format_args!("{}", self.ptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Host periodic TxFIFO start address"] #[inline(always)] #[must_use] - pub fn ptxsa(&mut self) -> PTXSA_W<0> { + pub fn ptxsa(&mut self) -> PTXSA_W { PTXSA_W::new(self) } #[doc = "Bits 16:31 - Host periodic TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ptxfd(&mut self) -> PTXFD_W<16> { + pub fn ptxfd(&mut self) -> PTXFD_W { PTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS Host periodic transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxfsiz](index.html) module"] +#[doc = "OTG_HS Host periodic transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxfsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hptxfsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HPTXFSIZ_SPEC; impl crate::RegisterSpec for HPTXFSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hptxfsiz::R](R) reader structure"] -impl crate::Readable for HPTXFSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hptxfsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`hptxfsiz::R`](R) reader structure"] +impl crate::Readable for HPTXFSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hptxfsiz::W`](W) writer structure"] impl crate::Writable for HPTXFSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/hw_config0.rs b/crates/bcm2835-lpa/src/usb_otg_global/hw_config0.rs index 13715b7..93348b4 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/hw_config0.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/hw_config0.rs @@ -1,20 +1,7 @@ #[doc = "Register `HW_CONFIG0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `OPERATING_MODE` reader - Operating Mode"] -pub type OPERATING_MODE_R = crate::FieldReader; +pub type OPERATING_MODE_R = crate::FieldReader; #[doc = "Operating Mode"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -40,10 +27,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for OPERATING_MODE_A { + type Ux = u8; +} impl OPERATING_MODE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(OPERATING_MODE_A::HNP_SRP_CAPABLE), 1 => Some(OPERATING_MODE_A::SRP_ONLY_CAPABLE), @@ -55,44 +45,44 @@ impl OPERATING_MODE_R { _ => None, } } - #[doc = "Checks if the value of the field is `HNP_SRP_CAPABLE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_hnp_srp_capable(&self) -> bool { *self == OPERATING_MODE_A::HNP_SRP_CAPABLE } - #[doc = "Checks if the value of the field is `SRP_ONLY_CAPABLE`"] + #[doc = "`1`"] #[inline(always)] pub fn is_srp_only_capable(&self) -> bool { *self == OPERATING_MODE_A::SRP_ONLY_CAPABLE } - #[doc = "Checks if the value of the field is `NO_HNP_SRP_CAPABLE`"] + #[doc = "`10`"] #[inline(always)] pub fn is_no_hnp_srp_capable(&self) -> bool { *self == OPERATING_MODE_A::NO_HNP_SRP_CAPABLE } - #[doc = "Checks if the value of the field is `SRP_CAPABLE_DEVICE`"] + #[doc = "`11`"] #[inline(always)] pub fn is_srp_capable_device(&self) -> bool { *self == OPERATING_MODE_A::SRP_CAPABLE_DEVICE } - #[doc = "Checks if the value of the field is `NO_SRP_CAPABLE_DEVICE`"] + #[doc = "`100`"] #[inline(always)] pub fn is_no_srp_capable_device(&self) -> bool { *self == OPERATING_MODE_A::NO_SRP_CAPABLE_DEVICE } - #[doc = "Checks if the value of the field is `SRP_CAPABLE_HOST`"] + #[doc = "`101`"] #[inline(always)] pub fn is_srp_capable_host(&self) -> bool { *self == OPERATING_MODE_A::SRP_CAPABLE_HOST } - #[doc = "Checks if the value of the field is `NO_SRP_CAPABLE_HOST`"] + #[doc = "`110`"] #[inline(always)] pub fn is_no_srp_capable_host(&self) -> bool { *self == OPERATING_MODE_A::NO_SRP_CAPABLE_HOST } } #[doc = "Field `ARCHITECTURE` reader - Architecture"] -pub type ARCHITECTURE_R = crate::FieldReader; +pub type ARCHITECTURE_R = crate::FieldReader; #[doc = "Architecture"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -110,10 +100,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for ARCHITECTURE_A { + type Ux = u8; +} impl ARCHITECTURE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(ARCHITECTURE_A::SLAVE_ONLY), 1 => Some(ARCHITECTURE_A::EXTERNAL_DMA), @@ -121,26 +114,26 @@ impl ARCHITECTURE_R { _ => None, } } - #[doc = "Checks if the value of the field is `SLAVE_ONLY`"] + #[doc = "`0`"] #[inline(always)] pub fn is_slave_only(&self) -> bool { *self == ARCHITECTURE_A::SLAVE_ONLY } - #[doc = "Checks if the value of the field is `EXTERNAL_DMA`"] + #[doc = "`1`"] #[inline(always)] pub fn is_external_dma(&self) -> bool { *self == ARCHITECTURE_A::EXTERNAL_DMA } - #[doc = "Checks if the value of the field is `INTERNAL_DMA`"] + #[doc = "`10`"] #[inline(always)] pub fn is_internal_dma(&self) -> bool { *self == ARCHITECTURE_A::INTERNAL_DMA } } #[doc = "Field `POINT_TO_POINT` reader - Point to Point"] -pub type POINT_TO_POINT_R = crate::BitReader; +pub type POINT_TO_POINT_R = crate::BitReader; #[doc = "Field `HIGH_SPEED_PHY` reader - High Speed Physical"] -pub type HIGH_SPEED_PHY_R = crate::FieldReader; +pub type HIGH_SPEED_PHY_R = crate::FieldReader; #[doc = "High Speed Physical"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -160,10 +153,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for HIGH_SPEED_PHY_A { + type Ux = u8; +} impl HIGH_SPEED_PHY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> HIGH_SPEED_PHY_A { + pub const fn variant(&self) -> HIGH_SPEED_PHY_A { match self.bits { 0 => HIGH_SPEED_PHY_A::NOT_SUPPORTED, 1 => HIGH_SPEED_PHY_A::UTMI, @@ -172,29 +168,29 @@ impl HIGH_SPEED_PHY_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NOT_SUPPORTED`"] + #[doc = "`0`"] #[inline(always)] pub fn is_not_supported(&self) -> bool { *self == HIGH_SPEED_PHY_A::NOT_SUPPORTED } - #[doc = "Checks if the value of the field is `UTMI`"] + #[doc = "`1`"] #[inline(always)] pub fn is_utmi(&self) -> bool { *self == HIGH_SPEED_PHY_A::UTMI } - #[doc = "Checks if the value of the field is `ULPI`"] + #[doc = "`10`"] #[inline(always)] pub fn is_ulpi(&self) -> bool { *self == HIGH_SPEED_PHY_A::ULPI } - #[doc = "Checks if the value of the field is `UTMI_ULPI`"] + #[doc = "`11`"] #[inline(always)] pub fn is_utmi_ulpi(&self) -> bool { *self == HIGH_SPEED_PHY_A::UTMI_ULPI } } #[doc = "Field `FULL_SPEED_PHY` reader - Full Speed Physical"] -pub type FULL_SPEED_PHY_R = crate::FieldReader; +pub type FULL_SPEED_PHY_R = crate::FieldReader; #[doc = "Full Speed Physical"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -214,10 +210,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FULL_SPEED_PHY_A { + type Ux = u8; +} impl FULL_SPEED_PHY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FULL_SPEED_PHY_A { + pub const fn variant(&self) -> FULL_SPEED_PHY_A { match self.bits { 0 => FULL_SPEED_PHY_A::PHY0, 1 => FULL_SPEED_PHY_A::DEDICATED, @@ -226,45 +225,45 @@ impl FULL_SPEED_PHY_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `PHY0`"] + #[doc = "`0`"] #[inline(always)] pub fn is_phy0(&self) -> bool { *self == FULL_SPEED_PHY_A::PHY0 } - #[doc = "Checks if the value of the field is `DEDICATED`"] + #[doc = "`1`"] #[inline(always)] pub fn is_dedicated(&self) -> bool { *self == FULL_SPEED_PHY_A::DEDICATED } - #[doc = "Checks if the value of the field is `PHY2`"] + #[doc = "`10`"] #[inline(always)] pub fn is_phy2(&self) -> bool { *self == FULL_SPEED_PHY_A::PHY2 } - #[doc = "Checks if the value of the field is `PHY3`"] + #[doc = "`11`"] #[inline(always)] pub fn is_phy3(&self) -> bool { *self == FULL_SPEED_PHY_A::PHY3 } } #[doc = "Field `DEVICE_END_POINT_COUNT` reader - Device end point count"] -pub type DEVICE_END_POINT_COUNT_R = crate::FieldReader; +pub type DEVICE_END_POINT_COUNT_R = crate::FieldReader; #[doc = "Field `HOST_CHANNEL_COUNT` reader - Host channel count"] -pub type HOST_CHANNEL_COUNT_R = crate::FieldReader; +pub type HOST_CHANNEL_COUNT_R = crate::FieldReader; #[doc = "Field `SUPPORTS_PERIODIC_ENDPOINTS` reader - Supports periodic endpoints"] -pub type SUPPORTS_PERIODIC_ENDPOINTS_R = crate::BitReader; +pub type SUPPORTS_PERIODIC_ENDPOINTS_R = crate::BitReader; #[doc = "Field `DYNAMIC_FIFO` reader - Dynamic FIFO"] -pub type DYNAMIC_FIFO_R = crate::BitReader; +pub type DYNAMIC_FIFO_R = crate::BitReader; #[doc = "Field `MULTI_PROC_INT` reader - Multi proc int"] -pub type MULTI_PROC_INT_R = crate::BitReader; +pub type MULTI_PROC_INT_R = crate::BitReader; #[doc = "Field `NON_PERIODIC_QUEUE_DEPTH` reader - Non periodic queue depth"] -pub type NON_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; +pub type NON_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; #[doc = "Field `HOST_PERIODIC_QUEUE_DEPTH` reader - Host periodic queue depth"] -pub type HOST_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; +pub type HOST_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; #[doc = "Field `DEVICE_TOKEN_QUEUE_DEPTH` reader - Device token queue depth"] -pub type DEVICE_TOKEN_QUEUE_DEPTH_R = crate::FieldReader; +pub type DEVICE_TOKEN_QUEUE_DEPTH_R = crate::FieldReader; #[doc = "Field `ENABLE_IC_USB` reader - Enable IC USB"] -pub type ENABLE_IC_USB_R = crate::BitReader; +pub type ENABLE_IC_USB_R = crate::BitReader; impl R { #[doc = "Bits 0:2 - Operating Mode"] #[inline(always)] @@ -337,12 +336,77 @@ impl R { ENABLE_IC_USB_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Hardware Config 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hw_config0](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HW_CONFIG0") + .field( + "operating_mode", + &format_args!("{}", self.operating_mode().bits()), + ) + .field( + "architecture", + &format_args!("{}", self.architecture().bits()), + ) + .field( + "point_to_point", + &format_args!("{}", self.point_to_point().bit()), + ) + .field( + "high_speed_phy", + &format_args!("{}", self.high_speed_phy().bits()), + ) + .field( + "full_speed_phy", + &format_args!("{}", self.full_speed_phy().bits()), + ) + .field( + "device_end_point_count", + &format_args!("{}", self.device_end_point_count().bits()), + ) + .field( + "host_channel_count", + &format_args!("{}", self.host_channel_count().bits()), + ) + .field( + "supports_periodic_endpoints", + &format_args!("{}", self.supports_periodic_endpoints().bit()), + ) + .field( + "dynamic_fifo", + &format_args!("{}", self.dynamic_fifo().bit()), + ) + .field( + "multi_proc_int", + &format_args!("{}", self.multi_proc_int().bit()), + ) + .field( + "non_periodic_queue_depth", + &format_args!("{}", self.non_periodic_queue_depth().bits()), + ) + .field( + "host_periodic_queue_depth", + &format_args!("{}", self.host_periodic_queue_depth().bits()), + ) + .field( + "device_token_queue_depth", + &format_args!("{}", self.device_token_queue_depth().bits()), + ) + .field( + "enable_ic_usb", + &format_args!("{}", self.enable_ic_usb().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Hardware Config 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_config0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HW_CONFIG0_SPEC; impl crate::RegisterSpec for HW_CONFIG0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hw_config0::R](R) reader structure"] -impl crate::Readable for HW_CONFIG0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hw_config0::R`](R) reader structure"] +impl crate::Readable for HW_CONFIG0_SPEC {} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/hw_direction.rs b/crates/bcm2835-lpa/src/usb_otg_global/hw_direction.rs index 1ca29d0..3545475 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/hw_direction.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/hw_direction.rs @@ -1,20 +1,7 @@ #[doc = "Register `HW_DIRECTION` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DIRECTION[0-15]` reader - Direction %s"] -pub type DIRECTION_R = crate::FieldReader; +pub type DIRECTION_R = crate::FieldReader; #[doc = "Direction %s"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -32,10 +19,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for DIRECTION_A { + type Ux = u8; +} impl DIRECTION_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(DIRECTION_A::BIDIR), 1 => Some(DIRECTION_A::IN), @@ -43,17 +33,17 @@ impl DIRECTION_R { _ => None, } } - #[doc = "Checks if the value of the field is `BIDIR`"] + #[doc = "`0`"] #[inline(always)] pub fn is_bidir(&self) -> bool { *self == DIRECTION_A::BIDIR } - #[doc = "Checks if the value of the field is `IN`"] + #[doc = "`1`"] #[inline(always)] pub fn is_in(&self) -> bool { *self == DIRECTION_A::IN } - #[doc = "Checks if the value of the field is `OUT`"] + #[doc = "`10`"] #[inline(always)] pub fn is_out(&self) -> bool { *self == DIRECTION_A::OUT @@ -146,12 +136,55 @@ impl R { DIRECTION_R::new(((self.bits >> 30) & 3) as u8) } } -#[doc = "Direction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hw_direction](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HW_DIRECTION") + .field("direction0", &format_args!("{}", self.direction0().bits())) + .field("direction1", &format_args!("{}", self.direction1().bits())) + .field("direction2", &format_args!("{}", self.direction2().bits())) + .field("direction3", &format_args!("{}", self.direction3().bits())) + .field("direction4", &format_args!("{}", self.direction4().bits())) + .field("direction5", &format_args!("{}", self.direction5().bits())) + .field("direction6", &format_args!("{}", self.direction6().bits())) + .field("direction7", &format_args!("{}", self.direction7().bits())) + .field("direction8", &format_args!("{}", self.direction8().bits())) + .field("direction9", &format_args!("{}", self.direction9().bits())) + .field( + "direction10", + &format_args!("{}", self.direction10().bits()), + ) + .field( + "direction11", + &format_args!("{}", self.direction11().bits()), + ) + .field( + "direction12", + &format_args!("{}", self.direction12().bits()), + ) + .field( + "direction13", + &format_args!("{}", self.direction13().bits()), + ) + .field( + "direction14", + &format_args!("{}", self.direction14().bits()), + ) + .field( + "direction15", + &format_args!("{}", self.direction15().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_direction::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HW_DIRECTION_SPEC; impl crate::RegisterSpec for HW_DIRECTION_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hw_direction::R](R) reader structure"] -impl crate::Readable for HW_DIRECTION_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hw_direction::R`](R) reader structure"] +impl crate::Readable for HW_DIRECTION_SPEC {} diff --git a/crates/bcm2835-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs b/crates/bcm2835-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs index 8734146..73658ab 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs @@ -1,49 +1,15 @@ #[doc = "Register `TX0FSIZ_Peripheral` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TX0FSIZ_Peripheral` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TX0FSA` reader - Endpoint 0 transmit RAM start address"] -pub type TX0FSA_R = crate::FieldReader; +pub type TX0FSA_R = crate::FieldReader; #[doc = "Field `TX0FSA` writer - Endpoint 0 transmit RAM start address"] -pub type TX0FSA_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, TX0FSIZ_PERIPHERAL_SPEC, u16, u16, 16, O>; +pub type TX0FSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `TX0FD` reader - Endpoint 0 TxFIFO depth"] -pub type TX0FD_R = crate::FieldReader; +pub type TX0FD_R = crate::FieldReader; #[doc = "Field `TX0FD` writer - Endpoint 0 TxFIFO depth"] -pub type TX0FD_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, TX0FSIZ_PERIPHERAL_SPEC, u16, u16, 16, O>; +pub type TX0FD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Endpoint 0 transmit RAM start address"] #[inline(always)] @@ -56,38 +22,52 @@ impl R { TX0FD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX0FSIZ_Peripheral") + .field("tx0fsa", &format_args!("{}", self.tx0fsa().bits())) + .field("tx0fd", &format_args!("{}", self.tx0fd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Endpoint 0 transmit RAM start address"] #[inline(always)] #[must_use] - pub fn tx0fsa(&mut self) -> TX0FSA_W<0> { + pub fn tx0fsa(&mut self) -> TX0FSA_W { TX0FSA_W::new(self) } #[doc = "Bits 16:31 - Endpoint 0 TxFIFO depth"] #[inline(always)] #[must_use] - pub fn tx0fd(&mut self) -> TX0FD_W<16> { + pub fn tx0fd(&mut self) -> TX0FD_W { TX0FD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Endpoint 0 transmit FIFO size (peripheral mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx0fsiz_peripheral](index.html) module"] +#[doc = "Endpoint 0 transmit FIFO size (peripheral mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx0fsiz_peripheral::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx0fsiz_peripheral::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TX0FSIZ_PERIPHERAL_SPEC; impl crate::RegisterSpec for TX0FSIZ_PERIPHERAL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tx0fsiz_peripheral::R](R) reader structure"] -impl crate::Readable for TX0FSIZ_PERIPHERAL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tx0fsiz_peripheral::W](W) writer structure"] +#[doc = "`read()` method returns [`tx0fsiz_peripheral::R`](R) reader structure"] +impl crate::Readable for TX0FSIZ_PERIPHERAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx0fsiz_peripheral::W`](W) writer structure"] impl crate::Writable for TX0FSIZ_PERIPHERAL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_global/vid.rs b/crates/bcm2835-lpa/src/usb_otg_global/vid.rs index ae468f7..732dd16 100644 --- a/crates/bcm2835-lpa/src/usb_otg_global/vid.rs +++ b/crates/bcm2835-lpa/src/usb_otg_global/vid.rs @@ -1,24 +1,19 @@ #[doc = "Register `VID` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } -#[doc = "OTG_HS vendor ID register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vid](index.html) module"] +#[doc = "OTG_HS vendor ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct VID_SPEC; impl crate::RegisterSpec for VID_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [vid::R](R) reader structure"] -impl crate::Readable for VID_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`vid::R`](R) reader structure"] +impl crate::Readable for VID_SPEC {} diff --git a/crates/bcm2835-lpa/src/usb_otg_host.rs b/crates/bcm2835-lpa/src/usb_otg_host.rs index c2b6fb8..f40a06f 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - OTG_HS host configuration register"] pub hcfg: HCFG, @@ -54,31 +55,38 @@ pub struct RegisterBlock { #[doc = "0x260..0x278 - Host channel %s"] pub host_channel11: HOST_CHANNEL, } -#[doc = "HCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "HCFG (rw) register accessor: OTG_HS host configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcfg`] +module"] pub type HCFG = crate::Reg; #[doc = "OTG_HS host configuration register"] pub mod hcfg; -#[doc = "HFIR (rw) register accessor: an alias for `Reg`"] +#[doc = "HFIR (rw) register accessor: OTG_HS Host frame interval register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hfir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hfir`] +module"] pub type HFIR = crate::Reg; #[doc = "OTG_HS Host frame interval register"] pub mod hfir; -#[doc = "HFNUM (r) register accessor: an alias for `Reg`"] +#[doc = "HFNUM (r) register accessor: OTG_HS host frame number/frame time remaining register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfnum::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hfnum`] +module"] pub type HFNUM = crate::Reg; #[doc = "OTG_HS host frame number/frame time remaining register"] pub mod hfnum; -#[doc = "HPTXSTS (rw) register accessor: an alias for `Reg`"] +#[doc = "HPTXSTS (rw) register accessor: Host periodic transmit FIFO/queue status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxsts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hptxsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hptxsts`] +module"] pub type HPTXSTS = crate::Reg; #[doc = "Host periodic transmit FIFO/queue status register"] pub mod hptxsts; -#[doc = "HAINT (r) register accessor: an alias for `Reg`"] +#[doc = "HAINT (r) register accessor: OTG_HS Host all channels interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haint::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@haint`] +module"] pub type HAINT = crate::Reg; #[doc = "OTG_HS Host all channels interrupt register"] pub mod haint; -#[doc = "HAINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "HAINTMSK (rw) register accessor: OTG_HS host all channels interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`haintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@haintmsk`] +module"] pub type HAINTMSK = crate::Reg; #[doc = "OTG_HS host all channels interrupt mask register"] pub mod haintmsk; -#[doc = "HPRT (rw) register accessor: an alias for `Reg`"] +#[doc = "HPRT (rw) register accessor: OTG_HS host port control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hprt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hprt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hprt`] +module"] pub type HPRT = crate::Reg; #[doc = "OTG_HS host port control and status register"] pub mod hprt; diff --git a/crates/bcm2835-lpa/src/usb_otg_host/haint.rs b/crates/bcm2835-lpa/src/usb_otg_host/haint.rs index 16455f3..fd11584 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/haint.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/haint.rs @@ -1,20 +1,7 @@ #[doc = "Register `HAINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `HAINT` reader - Channel interrupts"] -pub type HAINT_R = crate::FieldReader; +pub type HAINT_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - Channel interrupts"] #[inline(always)] @@ -22,15 +9,25 @@ impl R { HAINT_R::new((self.bits & 0xffff) as u16) } } -#[doc = "OTG_HS Host all channels interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haint](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HAINT") + .field("haint", &format_args!("{}", self.haint().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS Host all channels interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haint::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HAINT_SPEC; impl crate::RegisterSpec for HAINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [haint::R](R) reader structure"] -impl crate::Readable for HAINT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`haint::R`](R) reader structure"] +impl crate::Readable for HAINT_SPEC {} #[doc = "`reset()` method sets HAINT to value 0"] impl crate::Resettable for HAINT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2835-lpa/src/usb_otg_host/haintmsk.rs b/crates/bcm2835-lpa/src/usb_otg_host/haintmsk.rs index 69df5e9..f820459 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/haintmsk.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/haintmsk.rs @@ -1,43 +1,11 @@ #[doc = "Register `HAINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HAINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HAINTM` reader - Channel interrupt mask"] -pub type HAINTM_R = crate::FieldReader; +pub type HAINTM_R = crate::FieldReader; #[doc = "Field `HAINTM` writer - Channel interrupt mask"] -pub type HAINTM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HAINTMSK_SPEC, u16, u16, 16, O>; +pub type HAINTM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Channel interrupt mask"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { HAINTM_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HAINTMSK") + .field("haintm", &format_args!("{}", self.haintm().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Channel interrupt mask"] #[inline(always)] #[must_use] - pub fn haintm(&mut self) -> HAINTM_W<0> { + pub fn haintm(&mut self) -> HAINTM_W { HAINTM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS host all channels interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haintmsk](index.html) module"] +#[doc = "OTG_HS host all channels interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`haintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HAINTMSK_SPEC; impl crate::RegisterSpec for HAINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [haintmsk::R](R) reader structure"] -impl crate::Readable for HAINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [haintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`haintmsk::R`](R) reader structure"] +impl crate::Readable for HAINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`haintmsk::W`](W) writer structure"] impl crate::Writable for HAINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_host/hcfg.rs b/crates/bcm2835-lpa/src/usb_otg_host/hcfg.rs index 17f4b01..af6795d 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/hcfg.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/hcfg.rs @@ -1,45 +1,13 @@ #[doc = "Register `HCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSLSPCS` reader - FS/LS PHY clock select"] -pub type FSLSPCS_R = crate::FieldReader; +pub type FSLSPCS_R = crate::FieldReader; #[doc = "Field `FSLSPCS` writer - FS/LS PHY clock select"] -pub type FSLSPCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCFG_SPEC, u8, u8, 2, O>; +pub type FSLSPCS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `FSLSS` reader - FS- and LS-only support"] -pub type FSLSS_R = crate::BitReader; +pub type FSLSS_R = crate::BitReader; impl R { #[doc = "Bits 0:1 - FS/LS PHY clock select"] #[inline(always)] @@ -52,32 +20,46 @@ impl R { FSLSS_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCFG") + .field("fslspcs", &format_args!("{}", self.fslspcs().bits())) + .field("fslss", &format_args!("{}", self.fslss().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - FS/LS PHY clock select"] #[inline(always)] #[must_use] - pub fn fslspcs(&mut self) -> FSLSPCS_W<0> { + pub fn fslspcs(&mut self) -> FSLSPCS_W { FSLSPCS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS host configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcfg](index.html) module"] +#[doc = "OTG_HS host configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCFG_SPEC; impl crate::RegisterSpec for HCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcfg::R](R) reader structure"] -impl crate::Readable for HCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`hcfg::R`](R) reader structure"] +impl crate::Readable for HCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcfg::W`](W) writer structure"] impl crate::Writable for HCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_host/hfir.rs b/crates/bcm2835-lpa/src/usb_otg_host/hfir.rs index 9182ff2..d373916 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/hfir.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/hfir.rs @@ -1,43 +1,11 @@ #[doc = "Register `HFIR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HFIR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FRIVL` reader - Frame interval"] -pub type FRIVL_R = crate::FieldReader; +pub type FRIVL_R = crate::FieldReader; #[doc = "Field `FRIVL` writer - Frame interval"] -pub type FRIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HFIR_SPEC, u16, u16, 16, O>; +pub type FRIVL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Frame interval"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { FRIVL_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HFIR") + .field("frivl", &format_args!("{}", self.frivl().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Frame interval"] #[inline(always)] #[must_use] - pub fn frivl(&mut self) -> FRIVL_W<0> { + pub fn frivl(&mut self) -> FRIVL_W { FRIVL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS Host frame interval register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfir](index.html) module"] +#[doc = "OTG_HS Host frame interval register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hfir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HFIR_SPEC; impl crate::RegisterSpec for HFIR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hfir::R](R) reader structure"] -impl crate::Readable for HFIR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hfir::W](W) writer structure"] +#[doc = "`read()` method returns [`hfir::R`](R) reader structure"] +impl crate::Readable for HFIR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hfir::W`](W) writer structure"] impl crate::Writable for HFIR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_host/hfnum.rs b/crates/bcm2835-lpa/src/usb_otg_host/hfnum.rs index 0df982a..5bb48e9 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/hfnum.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/hfnum.rs @@ -1,22 +1,9 @@ #[doc = "Register `HFNUM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FRNUM` reader - Frame number"] -pub type FRNUM_R = crate::FieldReader; +pub type FRNUM_R = crate::FieldReader; #[doc = "Field `FTREM` reader - Frame time remaining"] -pub type FTREM_R = crate::FieldReader; +pub type FTREM_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - Frame number"] #[inline(always)] @@ -29,15 +16,26 @@ impl R { FTREM_R::new(((self.bits >> 16) & 0xffff) as u16) } } -#[doc = "OTG_HS host frame number/frame time remaining register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfnum](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HFNUM") + .field("frnum", &format_args!("{}", self.frnum().bits())) + .field("ftrem", &format_args!("{}", self.ftrem().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS host frame number/frame time remaining register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfnum::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HFNUM_SPEC; impl crate::RegisterSpec for HFNUM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hfnum::R](R) reader structure"] -impl crate::Readable for HFNUM_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hfnum::R`](R) reader structure"] +impl crate::Readable for HFNUM_SPEC {} #[doc = "`reset()` method sets HFNUM to value 0x3fff"] impl crate::Resettable for HFNUM_SPEC { const RESET_VALUE: Self::Ux = 0x3fff; diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel.rs index ee4a815..54d36d3 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/host_channel.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct HOST_CHANNEL { #[doc = "0x00 - Characteristics register"] pub hcchar: HCCHAR, @@ -14,27 +15,33 @@ pub struct HOST_CHANNEL { #[doc = "0x14 - DMA address"] pub hcdma: HCDMA, } -#[doc = "HCCHAR (rw) register accessor: an alias for `Reg`"] +#[doc = "HCCHAR (rw) register accessor: Characteristics register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcchar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcchar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcchar`] +module"] pub type HCCHAR = crate::Reg; #[doc = "Characteristics register"] pub mod hcchar; -#[doc = "HCSPLT (rw) register accessor: an alias for `Reg`"] +#[doc = "HCSPLT (rw) register accessor: Split control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcsplt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcsplt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcsplt`] +module"] pub type HCSPLT = crate::Reg; #[doc = "Split control register"] pub mod hcsplt; -#[doc = "HCINT (rw) register accessor: an alias for `Reg`"] +#[doc = "HCINT (rw) register accessor: Interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcint`] +module"] pub type HCINT = crate::Reg; #[doc = "Interrupt register"] pub mod hcint; -#[doc = "HCINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "HCINTMSK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcintmsk`] +module"] pub type HCINTMSK = crate::Reg; #[doc = "Interrupt mask"] pub mod hcintmsk; -#[doc = "HCTSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "HCTSIZ (rw) register accessor: Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hctsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hctsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hctsiz`] +module"] pub type HCTSIZ = crate::Reg; #[doc = "Transfer size"] pub mod hctsiz; -#[doc = "HCDMA (rw) register accessor: an alias for `Reg`"] +#[doc = "HCDMA (rw) register accessor: DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcdma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcdma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcdma`] +module"] pub type HCDMA = crate::Reg; #[doc = "DMA address"] pub mod hcdma; diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcchar.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcchar.rs index d73f560..4bc5c53 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcchar.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcchar.rs @@ -1,79 +1,47 @@ #[doc = "Register `HCCHAR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCCHAR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MPSIZ` reader - Maximum packet size"] -pub type MPSIZ_R = crate::FieldReader; +pub type MPSIZ_R = crate::FieldReader; #[doc = "Field `MPSIZ` writer - Maximum packet size"] -pub type MPSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u16, u16, 11, O>; +pub type MPSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 11, O, u16>; #[doc = "Field `EPNUM` reader - Endpoint number"] -pub type EPNUM_R = crate::FieldReader; +pub type EPNUM_R = crate::FieldReader; #[doc = "Field `EPNUM` writer - Endpoint number"] -pub type EPNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 4, O>; +pub type EPNUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `EPDIR` reader - Endpoint direction"] -pub type EPDIR_R = crate::BitReader; +pub type EPDIR_R = crate::BitReader; #[doc = "Field `EPDIR` writer - Endpoint direction"] -pub type EPDIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type EPDIR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LSDEV` reader - Low-speed device"] -pub type LSDEV_R = crate::BitReader; +pub type LSDEV_R = crate::BitReader; #[doc = "Field `LSDEV` writer - Low-speed device"] -pub type LSDEV_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type LSDEV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPTYP` reader - Endpoint type"] -pub type EPTYP_R = crate::FieldReader; +pub type EPTYP_R = crate::FieldReader; #[doc = "Field `EPTYP` writer - Endpoint type"] -pub type EPTYP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 2, O>; +pub type EPTYP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `MC` reader - Multi Count (MC) / Error Count (EC)"] -pub type MC_R = crate::FieldReader; +pub type MC_R = crate::FieldReader; #[doc = "Field `MC` writer - Multi Count (MC) / Error Count (EC)"] -pub type MC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 2, O>; +pub type MC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `DAD` reader - Device address"] -pub type DAD_R = crate::FieldReader; +pub type DAD_R = crate::FieldReader; #[doc = "Field `DAD` writer - Device address"] -pub type DAD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 7, O>; +pub type DAD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `ODDFRM` reader - Odd frame"] -pub type ODDFRM_R = crate::BitReader; +pub type ODDFRM_R = crate::BitReader; #[doc = "Field `ODDFRM` writer - Odd frame"] -pub type ODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type ODDFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHDIS` reader - Channel disable"] -pub type CHDIS_R = crate::BitReader; +pub type CHDIS_R = crate::BitReader; #[doc = "Field `CHDIS` writer - Channel disable"] -pub type CHDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type CHDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHENA` reader - Channel enable"] -pub type CHENA_R = crate::BitReader; +pub type CHENA_R = crate::BitReader; #[doc = "Field `CHENA` writer - Channel enable"] -pub type CHENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type CHENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] @@ -126,86 +94,108 @@ impl R { CHENA_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCCHAR") + .field("mpsiz", &format_args!("{}", self.mpsiz().bits())) + .field("epnum", &format_args!("{}", self.epnum().bits())) + .field("epdir", &format_args!("{}", self.epdir().bit())) + .field("lsdev", &format_args!("{}", self.lsdev().bit())) + .field("eptyp", &format_args!("{}", self.eptyp().bits())) + .field("mc", &format_args!("{}", self.mc().bits())) + .field("dad", &format_args!("{}", self.dad().bits())) + .field("oddfrm", &format_args!("{}", self.oddfrm().bit())) + .field("chdis", &format_args!("{}", self.chdis().bit())) + .field("chena", &format_args!("{}", self.chena().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] #[must_use] - pub fn mpsiz(&mut self) -> MPSIZ_W<0> { + pub fn mpsiz(&mut self) -> MPSIZ_W { MPSIZ_W::new(self) } #[doc = "Bits 11:14 - Endpoint number"] #[inline(always)] #[must_use] - pub fn epnum(&mut self) -> EPNUM_W<11> { + pub fn epnum(&mut self) -> EPNUM_W { EPNUM_W::new(self) } #[doc = "Bit 15 - Endpoint direction"] #[inline(always)] #[must_use] - pub fn epdir(&mut self) -> EPDIR_W<15> { + pub fn epdir(&mut self) -> EPDIR_W { EPDIR_W::new(self) } #[doc = "Bit 17 - Low-speed device"] #[inline(always)] #[must_use] - pub fn lsdev(&mut self) -> LSDEV_W<17> { + pub fn lsdev(&mut self) -> LSDEV_W { LSDEV_W::new(self) } #[doc = "Bits 18:19 - Endpoint type"] #[inline(always)] #[must_use] - pub fn eptyp(&mut self) -> EPTYP_W<18> { + pub fn eptyp(&mut self) -> EPTYP_W { EPTYP_W::new(self) } #[doc = "Bits 20:21 - Multi Count (MC) / Error Count (EC)"] #[inline(always)] #[must_use] - pub fn mc(&mut self) -> MC_W<20> { + pub fn mc(&mut self) -> MC_W { MC_W::new(self) } #[doc = "Bits 22:28 - Device address"] #[inline(always)] #[must_use] - pub fn dad(&mut self) -> DAD_W<22> { + pub fn dad(&mut self) -> DAD_W { DAD_W::new(self) } #[doc = "Bit 29 - Odd frame"] #[inline(always)] #[must_use] - pub fn oddfrm(&mut self) -> ODDFRM_W<29> { + pub fn oddfrm(&mut self) -> ODDFRM_W { ODDFRM_W::new(self) } #[doc = "Bit 30 - Channel disable"] #[inline(always)] #[must_use] - pub fn chdis(&mut self) -> CHDIS_W<30> { + pub fn chdis(&mut self) -> CHDIS_W { CHDIS_W::new(self) } #[doc = "Bit 31 - Channel enable"] #[inline(always)] #[must_use] - pub fn chena(&mut self) -> CHENA_W<31> { + pub fn chena(&mut self) -> CHENA_W { CHENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Characteristics register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcchar](index.html) module"] +#[doc = "Characteristics register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcchar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcchar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCCHAR_SPEC; impl crate::RegisterSpec for HCCHAR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcchar::R](R) reader structure"] -impl crate::Readable for HCCHAR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcchar::W](W) writer structure"] +#[doc = "`read()` method returns [`hcchar::R`](R) reader structure"] +impl crate::Readable for HCCHAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcchar::W`](W) writer structure"] impl crate::Writable for HCCHAR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcdma.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcdma.rs index bfcef2a..49ce1a2 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcdma.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcdma.rs @@ -1,43 +1,11 @@ #[doc = "Register `HCDMA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCDMA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMAADDR` reader - DMA address"] -pub type DMAADDR_R = crate::FieldReader; +pub type DMAADDR_R = crate::FieldReader; #[doc = "Field `DMAADDR` writer - DMA address"] -pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCDMA_SPEC, u32, u32, 32, O>; +pub type DMAADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DMAADDR_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCDMA") + .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] #[must_use] - pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + pub fn dmaaddr(&mut self) -> DMAADDR_W { DMAADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcdma](index.html) module"] +#[doc = "DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcdma::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcdma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCDMA_SPEC; impl crate::RegisterSpec for HCDMA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcdma::R](R) reader structure"] -impl crate::Readable for HCDMA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcdma::W](W) writer structure"] +#[doc = "`read()` method returns [`hcdma::R`](R) reader structure"] +impl crate::Readable for HCDMA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcdma::W`](W) writer structure"] impl crate::Writable for HCDMA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcint.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcint.rs index a8ef9ea..0fd949e 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcint.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcint.rs @@ -1,83 +1,51 @@ #[doc = "Register `HCINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRC` reader - Transfer completed"] -pub type XFRC_R = crate::BitReader; +pub type XFRC_R = crate::BitReader; #[doc = "Field `XFRC` writer - Transfer completed"] -pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type XFRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHH` reader - Channel halted"] -pub type CHH_R = crate::BitReader; +pub type CHH_R = crate::BitReader; #[doc = "Field `CHH` writer - Channel halted"] -pub type CHH_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type CHH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AHBERR` reader - AHB error"] -pub type AHBERR_R = crate::BitReader; +pub type AHBERR_R = crate::BitReader; #[doc = "Field `AHBERR` writer - AHB error"] -pub type AHBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type AHBERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALL` reader - STALL response received interrupt"] -pub type STALL_R = crate::BitReader; +pub type STALL_R = crate::BitReader; #[doc = "Field `STALL` writer - STALL response received interrupt"] -pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAK` reader - NAK response received interrupt"] -pub type NAK_R = crate::BitReader; +pub type NAK_R = crate::BitReader; #[doc = "Field `NAK` writer - NAK response received interrupt"] -pub type NAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type NAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACK` reader - ACK response received/transmitted interrupt"] -pub type ACK_R = crate::BitReader; +pub type ACK_R = crate::BitReader; #[doc = "Field `ACK` writer - ACK response received/transmitted interrupt"] -pub type ACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type ACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYET` reader - Response received interrupt"] -pub type NYET_R = crate::BitReader; +pub type NYET_R = crate::BitReader; #[doc = "Field `NYET` writer - Response received interrupt"] -pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type NYET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXERR` reader - Transaction error"] -pub type TXERR_R = crate::BitReader; +pub type TXERR_R = crate::BitReader; #[doc = "Field `TXERR` writer - Transaction error"] -pub type TXERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type TXERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BBERR` reader - Babble error"] -pub type BBERR_R = crate::BitReader; +pub type BBERR_R = crate::BitReader; #[doc = "Field `BBERR` writer - Babble error"] -pub type BBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type BBERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRMOR` reader - Frame overrun"] -pub type FRMOR_R = crate::BitReader; +pub type FRMOR_R = crate::BitReader; #[doc = "Field `FRMOR` writer - Frame overrun"] -pub type FRMOR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type FRMOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTERR` reader - Data toggle error"] -pub type DTERR_R = crate::BitReader; +pub type DTERR_R = crate::BitReader; #[doc = "Field `DTERR` writer - Data toggle error"] -pub type DTERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type DTERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed"] #[inline(always)] @@ -135,92 +103,115 @@ impl R { DTERR_R::new(((self.bits >> 10) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCINT") + .field("xfrc", &format_args!("{}", self.xfrc().bit())) + .field("chh", &format_args!("{}", self.chh().bit())) + .field("ahberr", &format_args!("{}", self.ahberr().bit())) + .field("stall", &format_args!("{}", self.stall().bit())) + .field("nak", &format_args!("{}", self.nak().bit())) + .field("ack", &format_args!("{}", self.ack().bit())) + .field("nyet", &format_args!("{}", self.nyet().bit())) + .field("txerr", &format_args!("{}", self.txerr().bit())) + .field("bberr", &format_args!("{}", self.bberr().bit())) + .field("frmor", &format_args!("{}", self.frmor().bit())) + .field("dterr", &format_args!("{}", self.dterr().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed"] #[inline(always)] #[must_use] - pub fn xfrc(&mut self) -> XFRC_W<0> { + pub fn xfrc(&mut self) -> XFRC_W { XFRC_W::new(self) } #[doc = "Bit 1 - Channel halted"] #[inline(always)] #[must_use] - pub fn chh(&mut self) -> CHH_W<1> { + pub fn chh(&mut self) -> CHH_W { CHH_W::new(self) } #[doc = "Bit 2 - AHB error"] #[inline(always)] #[must_use] - pub fn ahberr(&mut self) -> AHBERR_W<2> { + pub fn ahberr(&mut self) -> AHBERR_W { AHBERR_W::new(self) } #[doc = "Bit 3 - STALL response received interrupt"] #[inline(always)] #[must_use] - pub fn stall(&mut self) -> STALL_W<3> { + pub fn stall(&mut self) -> STALL_W { STALL_W::new(self) } #[doc = "Bit 4 - NAK response received interrupt"] #[inline(always)] #[must_use] - pub fn nak(&mut self) -> NAK_W<4> { + pub fn nak(&mut self) -> NAK_W { NAK_W::new(self) } #[doc = "Bit 5 - ACK response received/transmitted interrupt"] #[inline(always)] #[must_use] - pub fn ack(&mut self) -> ACK_W<5> { + pub fn ack(&mut self) -> ACK_W { ACK_W::new(self) } #[doc = "Bit 6 - Response received interrupt"] #[inline(always)] #[must_use] - pub fn nyet(&mut self) -> NYET_W<6> { + pub fn nyet(&mut self) -> NYET_W { NYET_W::new(self) } #[doc = "Bit 7 - Transaction error"] #[inline(always)] #[must_use] - pub fn txerr(&mut self) -> TXERR_W<7> { + pub fn txerr(&mut self) -> TXERR_W { TXERR_W::new(self) } #[doc = "Bit 8 - Babble error"] #[inline(always)] #[must_use] - pub fn bberr(&mut self) -> BBERR_W<8> { + pub fn bberr(&mut self) -> BBERR_W { BBERR_W::new(self) } #[doc = "Bit 9 - Frame overrun"] #[inline(always)] #[must_use] - pub fn frmor(&mut self) -> FRMOR_W<9> { + pub fn frmor(&mut self) -> FRMOR_W { FRMOR_W::new(self) } #[doc = "Bit 10 - Data toggle error"] #[inline(always)] #[must_use] - pub fn dterr(&mut self) -> DTERR_W<10> { + pub fn dterr(&mut self) -> DTERR_W { DTERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcint](index.html) module"] +#[doc = "Interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCINT_SPEC; impl crate::RegisterSpec for HCINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcint::R](R) reader structure"] -impl crate::Readable for HCINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcint::W](W) writer structure"] +#[doc = "`read()` method returns [`hcint::R`](R) reader structure"] +impl crate::Readable for HCINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcint::W`](W) writer structure"] impl crate::Writable for HCINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcintmsk.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcintmsk.rs index e158cb4..03aa41c 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcintmsk.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcintmsk.rs @@ -1,83 +1,51 @@ #[doc = "Register `HCINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHHM` reader - Channel halted mask"] -pub type CHHM_R = crate::BitReader; +pub type CHHM_R = crate::BitReader; #[doc = "Field `CHHM` writer - Channel halted mask"] -pub type CHHM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type CHHM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AHBERR` reader - AHB error"] -pub type AHBERR_R = crate::BitReader; +pub type AHBERR_R = crate::BitReader; #[doc = "Field `AHBERR` writer - AHB error"] -pub type AHBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type AHBERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLM` reader - STALL response received interrupt mask"] -pub type STALLM_R = crate::BitReader; +pub type STALLM_R = crate::BitReader; #[doc = "Field `STALLM` writer - STALL response received interrupt mask"] -pub type STALLM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type STALLM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKM` reader - NAK response received interrupt mask"] -pub type NAKM_R = crate::BitReader; +pub type NAKM_R = crate::BitReader; #[doc = "Field `NAKM` writer - NAK response received interrupt mask"] -pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type NAKM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACKM` reader - ACK response received/transmitted interrupt mask"] -pub type ACKM_R = crate::BitReader; +pub type ACKM_R = crate::BitReader; #[doc = "Field `ACKM` writer - ACK response received/transmitted interrupt mask"] -pub type ACKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type ACKM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYET` reader - response received interrupt mask"] -pub type NYET_R = crate::BitReader; +pub type NYET_R = crate::BitReader; #[doc = "Field `NYET` writer - response received interrupt mask"] -pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type NYET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXERRM` reader - Transaction error mask"] -pub type TXERRM_R = crate::BitReader; +pub type TXERRM_R = crate::BitReader; #[doc = "Field `TXERRM` writer - Transaction error mask"] -pub type TXERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type TXERRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BBERRM` reader - Babble error mask"] -pub type BBERRM_R = crate::BitReader; +pub type BBERRM_R = crate::BitReader; #[doc = "Field `BBERRM` writer - Babble error mask"] -pub type BBERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type BBERRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRMORM` reader - Frame overrun mask"] -pub type FRMORM_R = crate::BitReader; +pub type FRMORM_R = crate::BitReader; #[doc = "Field `FRMORM` writer - Frame overrun mask"] -pub type FRMORM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type FRMORM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTERRM` reader - Data toggle error mask"] -pub type DTERRM_R = crate::BitReader; +pub type DTERRM_R = crate::BitReader; #[doc = "Field `DTERRM` writer - Data toggle error mask"] -pub type DTERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type DTERRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed mask"] #[inline(always)] @@ -135,92 +103,115 @@ impl R { DTERRM_R::new(((self.bits >> 10) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCINTMSK") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("chhm", &format_args!("{}", self.chhm().bit())) + .field("ahberr", &format_args!("{}", self.ahberr().bit())) + .field("stallm", &format_args!("{}", self.stallm().bit())) + .field("nakm", &format_args!("{}", self.nakm().bit())) + .field("ackm", &format_args!("{}", self.ackm().bit())) + .field("nyet", &format_args!("{}", self.nyet().bit())) + .field("txerrm", &format_args!("{}", self.txerrm().bit())) + .field("bberrm", &format_args!("{}", self.bberrm().bit())) + .field("frmorm", &format_args!("{}", self.frmorm().bit())) + .field("dterrm", &format_args!("{}", self.dterrm().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Channel halted mask"] #[inline(always)] #[must_use] - pub fn chhm(&mut self) -> CHHM_W<1> { + pub fn chhm(&mut self) -> CHHM_W { CHHM_W::new(self) } #[doc = "Bit 2 - AHB error"] #[inline(always)] #[must_use] - pub fn ahberr(&mut self) -> AHBERR_W<2> { + pub fn ahberr(&mut self) -> AHBERR_W { AHBERR_W::new(self) } #[doc = "Bit 3 - STALL response received interrupt mask"] #[inline(always)] #[must_use] - pub fn stallm(&mut self) -> STALLM_W<3> { + pub fn stallm(&mut self) -> STALLM_W { STALLM_W::new(self) } #[doc = "Bit 4 - NAK response received interrupt mask"] #[inline(always)] #[must_use] - pub fn nakm(&mut self) -> NAKM_W<4> { + pub fn nakm(&mut self) -> NAKM_W { NAKM_W::new(self) } #[doc = "Bit 5 - ACK response received/transmitted interrupt mask"] #[inline(always)] #[must_use] - pub fn ackm(&mut self) -> ACKM_W<5> { + pub fn ackm(&mut self) -> ACKM_W { ACKM_W::new(self) } #[doc = "Bit 6 - response received interrupt mask"] #[inline(always)] #[must_use] - pub fn nyet(&mut self) -> NYET_W<6> { + pub fn nyet(&mut self) -> NYET_W { NYET_W::new(self) } #[doc = "Bit 7 - Transaction error mask"] #[inline(always)] #[must_use] - pub fn txerrm(&mut self) -> TXERRM_W<7> { + pub fn txerrm(&mut self) -> TXERRM_W { TXERRM_W::new(self) } #[doc = "Bit 8 - Babble error mask"] #[inline(always)] #[must_use] - pub fn bberrm(&mut self) -> BBERRM_W<8> { + pub fn bberrm(&mut self) -> BBERRM_W { BBERRM_W::new(self) } #[doc = "Bit 9 - Frame overrun mask"] #[inline(always)] #[must_use] - pub fn frmorm(&mut self) -> FRMORM_W<9> { + pub fn frmorm(&mut self) -> FRMORM_W { FRMORM_W::new(self) } #[doc = "Bit 10 - Data toggle error mask"] #[inline(always)] #[must_use] - pub fn dterrm(&mut self) -> DTERRM_W<10> { + pub fn dterrm(&mut self) -> DTERRM_W { DTERRM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcintmsk](index.html) module"] +#[doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCINTMSK_SPEC; impl crate::RegisterSpec for HCINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcintmsk::R](R) reader structure"] -impl crate::Readable for HCINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`hcintmsk::R`](R) reader structure"] +impl crate::Readable for HCINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcintmsk::W`](W) writer structure"] impl crate::Writable for HCINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcsplt.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcsplt.rs index b20ca79..dfc4fa0 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcsplt.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hcsplt.rs @@ -1,59 +1,27 @@ #[doc = "Register `HCSPLT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCSPLT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PRTADDR` reader - Port address"] -pub type PRTADDR_R = crate::FieldReader; +pub type PRTADDR_R = crate::FieldReader; #[doc = "Field `PRTADDR` writer - Port address"] -pub type PRTADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 7, O>; +pub type PRTADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `HUBADDR` reader - Hub address"] -pub type HUBADDR_R = crate::FieldReader; +pub type HUBADDR_R = crate::FieldReader; #[doc = "Field `HUBADDR` writer - Hub address"] -pub type HUBADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 7, O>; +pub type HUBADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `XACTPOS` reader - XACTPOS"] -pub type XACTPOS_R = crate::FieldReader; +pub type XACTPOS_R = crate::FieldReader; #[doc = "Field `XACTPOS` writer - XACTPOS"] -pub type XACTPOS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 2, O>; +pub type XACTPOS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `COMPLSPLT` reader - Do complete split"] -pub type COMPLSPLT_R = crate::BitReader; +pub type COMPLSPLT_R = crate::BitReader; #[doc = "Field `COMPLSPLT` writer - Do complete split"] -pub type COMPLSPLT_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCSPLT_SPEC, bool, O>; +pub type COMPLSPLT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPLITEN` reader - Split enable"] -pub type SPLITEN_R = crate::BitReader; +pub type SPLITEN_R = crate::BitReader; #[doc = "Field `SPLITEN` writer - Split enable"] -pub type SPLITEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCSPLT_SPEC, bool, O>; +pub type SPLITEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - Port address"] #[inline(always)] @@ -81,56 +49,73 @@ impl R { SPLITEN_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCSPLT") + .field("prtaddr", &format_args!("{}", self.prtaddr().bits())) + .field("hubaddr", &format_args!("{}", self.hubaddr().bits())) + .field("xactpos", &format_args!("{}", self.xactpos().bits())) + .field("complsplt", &format_args!("{}", self.complsplt().bit())) + .field("spliten", &format_args!("{}", self.spliten().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - Port address"] #[inline(always)] #[must_use] - pub fn prtaddr(&mut self) -> PRTADDR_W<0> { + pub fn prtaddr(&mut self) -> PRTADDR_W { PRTADDR_W::new(self) } #[doc = "Bits 7:13 - Hub address"] #[inline(always)] #[must_use] - pub fn hubaddr(&mut self) -> HUBADDR_W<7> { + pub fn hubaddr(&mut self) -> HUBADDR_W { HUBADDR_W::new(self) } #[doc = "Bits 14:15 - XACTPOS"] #[inline(always)] #[must_use] - pub fn xactpos(&mut self) -> XACTPOS_W<14> { + pub fn xactpos(&mut self) -> XACTPOS_W { XACTPOS_W::new(self) } #[doc = "Bit 16 - Do complete split"] #[inline(always)] #[must_use] - pub fn complsplt(&mut self) -> COMPLSPLT_W<16> { + pub fn complsplt(&mut self) -> COMPLSPLT_W { COMPLSPLT_W::new(self) } #[doc = "Bit 31 - Split enable"] #[inline(always)] #[must_use] - pub fn spliten(&mut self) -> SPLITEN_W<31> { + pub fn spliten(&mut self) -> SPLITEN_W { SPLITEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Split control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcsplt](index.html) module"] +#[doc = "Split control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcsplt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcsplt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCSPLT_SPEC; impl crate::RegisterSpec for HCSPLT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcsplt::R](R) reader structure"] -impl crate::Readable for HCSPLT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcsplt::W](W) writer structure"] +#[doc = "`read()` method returns [`hcsplt::R`](R) reader structure"] +impl crate::Readable for HCSPLT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcsplt::W`](W) writer structure"] impl crate::Writable for HCSPLT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hctsiz.rs b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hctsiz.rs index a7361fd..ebfe51b 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hctsiz.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/host_channel/hctsiz.rs @@ -1,51 +1,19 @@ #[doc = "Register `HCTSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCTSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRSIZ` reader - Transfer size"] -pub type XFRSIZ_R = crate::FieldReader; +pub type XFRSIZ_R = crate::FieldReader; #[doc = "Field `XFRSIZ` writer - Transfer size"] -pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u32, u32, 19, O>; +pub type XFRSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 19, O, u32>; #[doc = "Field `PKTCNT` reader - Packet count"] -pub type PKTCNT_R = crate::FieldReader; +pub type PKTCNT_R = crate::FieldReader; #[doc = "Field `PKTCNT` writer - Packet count"] -pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u16, u16, 10, O>; +pub type PKTCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `DPID` writer - Data PID"] -pub type DPID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u8, u8, 2, O>; +pub type DPID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:18 - Transfer size"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { DPID_R::new(((self.bits >> 29) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCTSIZ") + .field("xfrsiz", &format_args!("{}", self.xfrsiz().bits())) + .field("pktcnt", &format_args!("{}", self.pktcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:18 - Transfer size"] #[inline(always)] #[must_use] - pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + pub fn xfrsiz(&mut self) -> XFRSIZ_W { XFRSIZ_W::new(self) } #[doc = "Bits 19:28 - Packet count"] #[inline(always)] #[must_use] - pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + pub fn pktcnt(&mut self) -> PKTCNT_W { PKTCNT_W::new(self) } #[doc = "Bits 29:30 - Data PID"] #[inline(always)] #[must_use] - pub fn dpid(&mut self) -> DPID_W<29> { + pub fn dpid(&mut self) -> DPID_W { DPID_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hctsiz](index.html) module"] +#[doc = "Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hctsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hctsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCTSIZ_SPEC; impl crate::RegisterSpec for HCTSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hctsiz::R](R) reader structure"] -impl crate::Readable for HCTSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hctsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`hctsiz::R`](R) reader structure"] +impl crate::Readable for HCTSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hctsiz::W`](W) writer structure"] impl crate::Writable for HCTSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_host/hprt.rs b/crates/bcm2835-lpa/src/usb_otg_host/hprt.rs index cb893f3..ca27b6f 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/hprt.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/hprt.rs @@ -1,83 +1,51 @@ #[doc = "Register `HPRT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HPRT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PCSTS` reader - Port connect status"] -pub type PCSTS_R = crate::BitReader; +pub type PCSTS_R = crate::BitReader; #[doc = "Field `PCDET` reader - Port connect detected"] -pub type PCDET_R = crate::BitReader; +pub type PCDET_R = crate::BitReader; #[doc = "Field `PCDET` writer - Port connect detected"] -pub type PCDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PCDET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PENA` reader - Port enable"] -pub type PENA_R = crate::BitReader; +pub type PENA_R = crate::BitReader; #[doc = "Field `PENA` writer - Port enable"] -pub type PENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PENCHNG` reader - Port enable/disable change"] -pub type PENCHNG_R = crate::BitReader; +pub type PENCHNG_R = crate::BitReader; #[doc = "Field `PENCHNG` writer - Port enable/disable change"] -pub type PENCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PENCHNG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POCA` reader - Port overcurrent active"] -pub type POCA_R = crate::BitReader; +pub type POCA_R = crate::BitReader; #[doc = "Field `POCCHNG` reader - Port overcurrent change"] -pub type POCCHNG_R = crate::BitReader; +pub type POCCHNG_R = crate::BitReader; #[doc = "Field `POCCHNG` writer - Port overcurrent change"] -pub type POCCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type POCCHNG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRES` reader - Port resume"] -pub type PRES_R = crate::BitReader; +pub type PRES_R = crate::BitReader; #[doc = "Field `PRES` writer - Port resume"] -pub type PRES_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PSUSP` reader - Port suspend"] -pub type PSUSP_R = crate::BitReader; +pub type PSUSP_R = crate::BitReader; #[doc = "Field `PSUSP` writer - Port suspend"] -pub type PSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRST` reader - Port reset"] -pub type PRST_R = crate::BitReader; +pub type PRST_R = crate::BitReader; #[doc = "Field `PRST` writer - Port reset"] -pub type PRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PLSTS` reader - Port line status"] -pub type PLSTS_R = crate::FieldReader; +pub type PLSTS_R = crate::FieldReader; #[doc = "Field `PPWR` reader - Port power"] -pub type PPWR_R = crate::BitReader; +pub type PPWR_R = crate::BitReader; #[doc = "Field `PPWR` writer - Port power"] -pub type PPWR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PPWR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTCTL` reader - Port test control"] -pub type PTCTL_R = crate::FieldReader; +pub type PTCTL_R = crate::FieldReader; #[doc = "Field `PTCTL` writer - Port test control"] -pub type PTCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPRT_SPEC, u8, u8, 4, O>; +pub type PTCTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `PSPD` reader - Port speed"] -pub type PSPD_R = crate::FieldReader; +pub type PSPD_R = crate::FieldReader; impl R { #[doc = "Bit 0 - Port connect status"] #[inline(always)] @@ -145,80 +113,105 @@ impl R { PSPD_R::new(((self.bits >> 17) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HPRT") + .field("pcsts", &format_args!("{}", self.pcsts().bit())) + .field("pcdet", &format_args!("{}", self.pcdet().bit())) + .field("pena", &format_args!("{}", self.pena().bit())) + .field("penchng", &format_args!("{}", self.penchng().bit())) + .field("poca", &format_args!("{}", self.poca().bit())) + .field("pocchng", &format_args!("{}", self.pocchng().bit())) + .field("pres", &format_args!("{}", self.pres().bit())) + .field("psusp", &format_args!("{}", self.psusp().bit())) + .field("prst", &format_args!("{}", self.prst().bit())) + .field("plsts", &format_args!("{}", self.plsts().bits())) + .field("ppwr", &format_args!("{}", self.ppwr().bit())) + .field("ptctl", &format_args!("{}", self.ptctl().bits())) + .field("pspd", &format_args!("{}", self.pspd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Port connect detected"] #[inline(always)] #[must_use] - pub fn pcdet(&mut self) -> PCDET_W<1> { + pub fn pcdet(&mut self) -> PCDET_W { PCDET_W::new(self) } #[doc = "Bit 2 - Port enable"] #[inline(always)] #[must_use] - pub fn pena(&mut self) -> PENA_W<2> { + pub fn pena(&mut self) -> PENA_W { PENA_W::new(self) } #[doc = "Bit 3 - Port enable/disable change"] #[inline(always)] #[must_use] - pub fn penchng(&mut self) -> PENCHNG_W<3> { + pub fn penchng(&mut self) -> PENCHNG_W { PENCHNG_W::new(self) } #[doc = "Bit 5 - Port overcurrent change"] #[inline(always)] #[must_use] - pub fn pocchng(&mut self) -> POCCHNG_W<5> { + pub fn pocchng(&mut self) -> POCCHNG_W { POCCHNG_W::new(self) } #[doc = "Bit 6 - Port resume"] #[inline(always)] #[must_use] - pub fn pres(&mut self) -> PRES_W<6> { + pub fn pres(&mut self) -> PRES_W { PRES_W::new(self) } #[doc = "Bit 7 - Port suspend"] #[inline(always)] #[must_use] - pub fn psusp(&mut self) -> PSUSP_W<7> { + pub fn psusp(&mut self) -> PSUSP_W { PSUSP_W::new(self) } #[doc = "Bit 8 - Port reset"] #[inline(always)] #[must_use] - pub fn prst(&mut self) -> PRST_W<8> { + pub fn prst(&mut self) -> PRST_W { PRST_W::new(self) } #[doc = "Bit 12 - Port power"] #[inline(always)] #[must_use] - pub fn ppwr(&mut self) -> PPWR_W<12> { + pub fn ppwr(&mut self) -> PPWR_W { PPWR_W::new(self) } #[doc = "Bits 13:16 - Port test control"] #[inline(always)] #[must_use] - pub fn ptctl(&mut self) -> PTCTL_W<13> { + pub fn ptctl(&mut self) -> PTCTL_W { PTCTL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS host port control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hprt](index.html) module"] +#[doc = "OTG_HS host port control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hprt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hprt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HPRT_SPEC; impl crate::RegisterSpec for HPRT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hprt::R](R) reader structure"] -impl crate::Readable for HPRT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hprt::W](W) writer structure"] +#[doc = "`read()` method returns [`hprt::R`](R) reader structure"] +impl crate::Readable for HPRT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hprt::W`](W) writer structure"] impl crate::Writable for HPRT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_host/hptxsts.rs b/crates/bcm2835-lpa/src/usb_otg_host/hptxsts.rs index 3cb5895..ffb1b12 100644 --- a/crates/bcm2835-lpa/src/usb_otg_host/hptxsts.rs +++ b/crates/bcm2835-lpa/src/usb_otg_host/hptxsts.rs @@ -1,47 +1,15 @@ #[doc = "Register `HPTXSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HPTXSTS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PTXFSAVL` reader - Periodic transmit data FIFO space available"] -pub type PTXFSAVL_R = crate::FieldReader; +pub type PTXFSAVL_R = crate::FieldReader; #[doc = "Field `PTXFSAVL` writer - Periodic transmit data FIFO space available"] -pub type PTXFSAVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXSTS_SPEC, u16, u16, 16, O>; +pub type PTXFSAVL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `PTXQSAV` reader - Periodic transmit request queue space available"] -pub type PTXQSAV_R = crate::FieldReader; +pub type PTXQSAV_R = crate::FieldReader; #[doc = "Field `PTXQTOP` reader - Top of the periodic transmit request queue"] -pub type PTXQTOP_R = crate::FieldReader; +pub type PTXQTOP_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - Periodic transmit data FIFO space available"] #[inline(always)] @@ -59,32 +27,47 @@ impl R { PTXQTOP_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HPTXSTS") + .field("ptxfsavl", &format_args!("{}", self.ptxfsavl().bits())) + .field("ptxqsav", &format_args!("{}", self.ptxqsav().bits())) + .field("ptxqtop", &format_args!("{}", self.ptxqtop().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Periodic transmit data FIFO space available"] #[inline(always)] #[must_use] - pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<0> { + pub fn ptxfsavl(&mut self) -> PTXFSAVL_W { PTXFSAVL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host periodic transmit FIFO/queue status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxsts](index.html) module"] +#[doc = "Host periodic transmit FIFO/queue status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxsts::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hptxsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HPTXSTS_SPEC; impl crate::RegisterSpec for HPTXSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hptxsts::R](R) reader structure"] -impl crate::Readable for HPTXSTS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hptxsts::W](W) writer structure"] +#[doc = "`read()` method returns [`hptxsts::R`](R) reader structure"] +impl crate::Readable for HPTXSTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hptxsts::W`](W) writer structure"] impl crate::Writable for HPTXSTS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/usb_otg_pwrclk.rs b/crates/bcm2835-lpa/src/usb_otg_pwrclk.rs index 67a9eb5..242f3b2 100644 --- a/crates/bcm2835-lpa/src/usb_otg_pwrclk.rs +++ b/crates/bcm2835-lpa/src/usb_otg_pwrclk.rs @@ -1,10 +1,12 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - power and clock gating control"] pub pcgcctl: PCGCCTL, } -#[doc = "PCGCCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "PCGCCTL (rw) register accessor: power and clock gating control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcgcctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcgcctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcgcctl`] +module"] pub type PCGCCTL = crate::Reg; #[doc = "power and clock gating control"] pub mod pcgcctl; diff --git a/crates/bcm2835-lpa/src/usb_otg_pwrclk/pcgcctl.rs b/crates/bcm2835-lpa/src/usb_otg_pwrclk/pcgcctl.rs index 061312d..97a2598 100644 --- a/crates/bcm2835-lpa/src/usb_otg_pwrclk/pcgcctl.rs +++ b/crates/bcm2835-lpa/src/usb_otg_pwrclk/pcgcctl.rs @@ -1,102 +1,67 @@ #[doc = "Register `PCGCCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PCGCCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `STPPCLK` reader - Stop PHY clock"] -pub type STPPCLK_R = crate::BitReader; +pub type STPPCLK_R = crate::BitReader; #[doc = "Field `STPPCLK` writer - Stop PHY clock"] -pub type STPPCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type STPPCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GATEHCLK` reader - Gate HCLK"] -pub type GATEHCLK_R = crate::BitReader; +pub type GATEHCLK_R = crate::BitReader; #[doc = "Field `GATEHCLK` writer - Gate HCLK"] -pub type GATEHCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type GATEHCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWRCLMP` reader - Power clamp"] -pub type PWRCLMP_R = crate::BitReader; +pub type PWRCLMP_R = crate::BitReader; #[doc = "Field `PWRCLMP` writer - Power clamp"] -pub type PWRCLMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type PWRCLMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTPDWNMODULE` reader - Power down modules"] -pub type RSTPDWNMODULE_R = crate::BitReader; +pub type RSTPDWNMODULE_R = crate::BitReader; #[doc = "Field `RSTPDWNMODULE` writer - Power down modules"] -pub type RSTPDWNMODULE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type RSTPDWNMODULE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PHYSUSP` reader - PHY Suspended"] -pub type PHYSUSP_R = crate::BitReader; +pub type PHYSUSP_R = crate::BitReader; #[doc = "Field `PHYSUSP` writer - PHY Suspended"] -pub type PHYSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type PHYSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE_L1GATING` reader - Enable sleep clock gating"] -pub type ENABLE_L1GATING_R = crate::BitReader; +pub type ENABLE_L1GATING_R = crate::BitReader; #[doc = "Field `ENABLE_L1GATING` writer - Enable sleep clock gating"] -pub type ENABLE_L1GATING_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type ENABLE_L1GATING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PHYSLEEP` reader - PHY is in sleep mode"] -pub type PHYSLEEP_R = crate::BitReader; +pub type PHYSLEEP_R = crate::BitReader; #[doc = "Field `PHYSLEEP` writer - PHY is in sleep mode"] -pub type PHYSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type PHYSLEEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEEPSLEEP` reader - PHY is in deep sleep"] -pub type DEEPSLEEP_R = crate::BitReader; +pub type DEEPSLEEP_R = crate::BitReader; #[doc = "Field `DEEPSLEEP` writer - PHY is in deep sleep"] -pub type DEEPSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type DEEPSLEEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESETAFTERSUSP` reader - Reset after suspend"] -pub type RESETAFTERSUSP_R = crate::BitReader; +pub type RESETAFTERSUSP_R = crate::BitReader; #[doc = "Field `RESETAFTERSUSP` writer - Reset after suspend"] -pub type RESETAFTERSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type RESETAFTERSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESTOREMODE` reader - Restore mode"] -pub type RESTOREMODE_R = crate::BitReader; +pub type RESTOREMODE_R = crate::BitReader; #[doc = "Field `RESTOREMODE` writer - Restore mode"] -pub type RESTOREMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type RESTOREMODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENEXTNDEDHIBER` reader - Enable extended hibernation"] -pub type ENEXTNDEDHIBER_R = crate::BitReader; +pub type ENEXTNDEDHIBER_R = crate::BitReader; #[doc = "Field `ENEXTNDEDHIBER` writer - Enable extended hibernation"] -pub type ENEXTNDEDHIBER_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type ENEXTNDEDHIBER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EXTNDEDHIBERNATIONCLAMP` reader - Extended hibernation clamp"] -pub type EXTNDEDHIBERNATIONCLAMP_R = crate::BitReader; +pub type EXTNDEDHIBERNATIONCLAMP_R = crate::BitReader; #[doc = "Field `EXTNDEDHIBERNATIONCLAMP` writer - Extended hibernation clamp"] -pub type EXTNDEDHIBERNATIONCLAMP_W<'a, const O: u8> = - crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type EXTNDEDHIBERNATIONCLAMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EXTNDEDHIBERNATIONSWITCH` reader - Extended hibernation switch"] -pub type EXTNDEDHIBERNATIONSWITCH_R = crate::BitReader; +pub type EXTNDEDHIBERNATIONSWITCH_R = crate::BitReader; #[doc = "Field `EXTNDEDHIBERNATIONSWITCH` writer - Extended hibernation switch"] -pub type EXTNDEDHIBERNATIONSWITCH_W<'a, const O: u8> = - crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type EXTNDEDHIBERNATIONSWITCH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ESSREGRESTORED` reader - Essential register values restored"] -pub type ESSREGRESTORED_R = crate::BitReader; +pub type ESSREGRESTORED_R = crate::BitReader; #[doc = "Field `ESSREGRESTORED` writer - Essential register values restored"] -pub type ESSREGRESTORED_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type ESSREGRESTORED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESTORE_VALUE` reader - Restore value"] -pub type RESTORE_VALUE_R = crate::FieldReader; +pub type RESTORE_VALUE_R = crate::FieldReader; #[doc = "Field `RESTORE_VALUE` writer - Restore value"] -pub type RESTORE_VALUE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, PCGCCTL_SPEC, u32, u32, 18, O>; +pub type RESTORE_VALUE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 18, O, u32>; impl R { #[doc = "Bit 0 - Stop PHY clock"] #[inline(always)] @@ -174,116 +139,167 @@ impl R { RESTORE_VALUE_R::new((self.bits >> 14) & 0x0003_ffff) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PCGCCTL") + .field("stppclk", &format_args!("{}", self.stppclk().bit())) + .field("gatehclk", &format_args!("{}", self.gatehclk().bit())) + .field("pwrclmp", &format_args!("{}", self.pwrclmp().bit())) + .field( + "rstpdwnmodule", + &format_args!("{}", self.rstpdwnmodule().bit()), + ) + .field("physusp", &format_args!("{}", self.physusp().bit())) + .field( + "enable_l1gating", + &format_args!("{}", self.enable_l1gating().bit()), + ) + .field("physleep", &format_args!("{}", self.physleep().bit())) + .field("deepsleep", &format_args!("{}", self.deepsleep().bit())) + .field( + "resetaftersusp", + &format_args!("{}", self.resetaftersusp().bit()), + ) + .field("restoremode", &format_args!("{}", self.restoremode().bit())) + .field( + "enextndedhiber", + &format_args!("{}", self.enextndedhiber().bit()), + ) + .field( + "extndedhibernationclamp", + &format_args!("{}", self.extndedhibernationclamp().bit()), + ) + .field( + "extndedhibernationswitch", + &format_args!("{}", self.extndedhibernationswitch().bit()), + ) + .field( + "essregrestored", + &format_args!("{}", self.essregrestored().bit()), + ) + .field( + "restore_value", + &format_args!("{}", self.restore_value().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Stop PHY clock"] #[inline(always)] #[must_use] - pub fn stppclk(&mut self) -> STPPCLK_W<0> { + pub fn stppclk(&mut self) -> STPPCLK_W { STPPCLK_W::new(self) } #[doc = "Bit 1 - Gate HCLK"] #[inline(always)] #[must_use] - pub fn gatehclk(&mut self) -> GATEHCLK_W<1> { + pub fn gatehclk(&mut self) -> GATEHCLK_W { GATEHCLK_W::new(self) } #[doc = "Bit 2 - Power clamp"] #[inline(always)] #[must_use] - pub fn pwrclmp(&mut self) -> PWRCLMP_W<2> { + pub fn pwrclmp(&mut self) -> PWRCLMP_W { PWRCLMP_W::new(self) } #[doc = "Bit 3 - Power down modules"] #[inline(always)] #[must_use] - pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W<3> { + pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W { RSTPDWNMODULE_W::new(self) } #[doc = "Bit 4 - PHY Suspended"] #[inline(always)] #[must_use] - pub fn physusp(&mut self) -> PHYSUSP_W<4> { + pub fn physusp(&mut self) -> PHYSUSP_W { PHYSUSP_W::new(self) } #[doc = "Bit 5 - Enable sleep clock gating"] #[inline(always)] #[must_use] - pub fn enable_l1gating(&mut self) -> ENABLE_L1GATING_W<5> { + pub fn enable_l1gating(&mut self) -> ENABLE_L1GATING_W { ENABLE_L1GATING_W::new(self) } #[doc = "Bit 6 - PHY is in sleep mode"] #[inline(always)] #[must_use] - pub fn physleep(&mut self) -> PHYSLEEP_W<6> { + pub fn physleep(&mut self) -> PHYSLEEP_W { PHYSLEEP_W::new(self) } #[doc = "Bit 7 - PHY is in deep sleep"] #[inline(always)] #[must_use] - pub fn deepsleep(&mut self) -> DEEPSLEEP_W<7> { + pub fn deepsleep(&mut self) -> DEEPSLEEP_W { DEEPSLEEP_W::new(self) } #[doc = "Bit 8 - Reset after suspend"] #[inline(always)] #[must_use] - pub fn resetaftersusp(&mut self) -> RESETAFTERSUSP_W<8> { + pub fn resetaftersusp(&mut self) -> RESETAFTERSUSP_W { RESETAFTERSUSP_W::new(self) } #[doc = "Bit 9 - Restore mode"] #[inline(always)] #[must_use] - pub fn restoremode(&mut self) -> RESTOREMODE_W<9> { + pub fn restoremode(&mut self) -> RESTOREMODE_W { RESTOREMODE_W::new(self) } #[doc = "Bit 10 - Enable extended hibernation"] #[inline(always)] #[must_use] - pub fn enextndedhiber(&mut self) -> ENEXTNDEDHIBER_W<10> { + pub fn enextndedhiber(&mut self) -> ENEXTNDEDHIBER_W { ENEXTNDEDHIBER_W::new(self) } #[doc = "Bit 11 - Extended hibernation clamp"] #[inline(always)] #[must_use] - pub fn extndedhibernationclamp(&mut self) -> EXTNDEDHIBERNATIONCLAMP_W<11> { + pub fn extndedhibernationclamp(&mut self) -> EXTNDEDHIBERNATIONCLAMP_W { EXTNDEDHIBERNATIONCLAMP_W::new(self) } #[doc = "Bit 12 - Extended hibernation switch"] #[inline(always)] #[must_use] - pub fn extndedhibernationswitch(&mut self) -> EXTNDEDHIBERNATIONSWITCH_W<12> { + pub fn extndedhibernationswitch(&mut self) -> EXTNDEDHIBERNATIONSWITCH_W { EXTNDEDHIBERNATIONSWITCH_W::new(self) } #[doc = "Bit 13 - Essential register values restored"] #[inline(always)] #[must_use] - pub fn essregrestored(&mut self) -> ESSREGRESTORED_W<13> { + pub fn essregrestored(&mut self) -> ESSREGRESTORED_W { ESSREGRESTORED_W::new(self) } #[doc = "Bits 14:31 - Restore value"] #[inline(always)] #[must_use] - pub fn restore_value(&mut self) -> RESTORE_VALUE_W<14> { + pub fn restore_value(&mut self) -> RESTORE_VALUE_W { RESTORE_VALUE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "power and clock gating control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcgcctl](index.html) module"] +#[doc = "power and clock gating control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcgcctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcgcctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCGCCTL_SPEC; impl crate::RegisterSpec for PCGCCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pcgcctl::R](R) reader structure"] -impl crate::Readable for PCGCCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [pcgcctl::W](W) writer structure"] +#[doc = "`read()` method returns [`pcgcctl::R`](R) reader structure"] +impl crate::Readable for PCGCCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pcgcctl::W`](W) writer structure"] impl crate::Writable for PCGCCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/vcmailbox.rs b/crates/bcm2835-lpa/src/vcmailbox.rs index 7490467..f3d9184 100644 --- a/crates/bcm2835-lpa/src/vcmailbox.rs +++ b/crates/bcm2835-lpa/src/vcmailbox.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Read messages from the VideoCore"] pub read: READ, @@ -24,43 +25,53 @@ pub struct RegisterBlock { #[doc = "0x3c - "] pub config1: CONFIG1, } -#[doc = "READ (r) register accessor: an alias for `Reg`"] +#[doc = "READ (r) register accessor: Read messages from the VideoCore\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`read::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@read`] +module"] pub type READ = crate::Reg; #[doc = "Read messages from the VideoCore"] pub mod read; -#[doc = "PEEK0 (rw) register accessor: an alias for `Reg`"] +#[doc = "PEEK0 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peek0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peek0`] +module"] pub type PEEK0 = crate::Reg; #[doc = ""] pub mod peek0; -#[doc = "SENDER0 (rw) register accessor: an alias for `Reg`"] +#[doc = "SENDER0 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sender0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sender0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sender0`] +module"] pub type SENDER0 = crate::Reg; #[doc = ""] pub mod sender0; -#[doc = "STATUS0 (r) register accessor: an alias for `Reg`"] +#[doc = "STATUS0 (r) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status0`] +module"] pub type STATUS0 = crate::Reg; #[doc = ""] pub mod status0; -#[doc = "CONFIG0 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONFIG0 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config0`] +module"] pub type CONFIG0 = crate::Reg; #[doc = ""] pub mod config0; -#[doc = "WRITE (w) register accessor: an alias for `Reg`"] +#[doc = "WRITE (w) register accessor: Write messages to the VideoCore\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`write::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@write`] +module"] pub type WRITE = crate::Reg; #[doc = "Write messages to the VideoCore"] pub mod write; -#[doc = "PEEK1 (rw) register accessor: an alias for `Reg`"] +#[doc = "PEEK1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peek1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peek1`] +module"] pub type PEEK1 = crate::Reg; #[doc = ""] pub mod peek1; -#[doc = "SENDER1 (rw) register accessor: an alias for `Reg`"] +#[doc = "SENDER1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sender1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sender1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sender1`] +module"] pub type SENDER1 = crate::Reg; #[doc = ""] pub mod sender1; -#[doc = "STATUS1 (rw) register accessor: an alias for `Reg`"] +#[doc = "STATUS1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status1`] +module"] pub type STATUS1 = crate::Reg; #[doc = ""] pub mod status1; -#[doc = "CONFIG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONFIG1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config1`] +module"] pub type CONFIG1 = crate::Reg; #[doc = ""] pub mod config1; diff --git a/crates/bcm2835-lpa/src/vcmailbox/config0.rs b/crates/bcm2835-lpa/src/vcmailbox/config0.rs index dce060f..b90c56d 100644 --- a/crates/bcm2835-lpa/src/vcmailbox/config0.rs +++ b/crates/bcm2835-lpa/src/vcmailbox/config0.rs @@ -1,43 +1,11 @@ #[doc = "Register `CONFIG0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONFIG0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IRQEN` reader - Enable the interrupt when data is available"] -pub type IRQEN_R = crate::BitReader; +pub type IRQEN_R = crate::BitReader; #[doc = "Field `IRQEN` writer - Enable the interrupt when data is available"] -pub type IRQEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG0_SPEC, bool, O>; +pub type IRQEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable the interrupt when data is available"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { IRQEN_R::new((self.bits & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONFIG0") + .field("irqen", &format_args!("{}", self.irqen().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable the interrupt when data is available"] #[inline(always)] #[must_use] - pub fn irqen(&mut self) -> IRQEN_W<0> { + pub fn irqen(&mut self) -> IRQEN_W { IRQEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config0](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONFIG0_SPEC; impl crate::RegisterSpec for CONFIG0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [config0::R](R) reader structure"] -impl crate::Readable for CONFIG0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [config0::W](W) writer structure"] +#[doc = "`read()` method returns [`config0::R`](R) reader structure"] +impl crate::Readable for CONFIG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config0::W`](W) writer structure"] impl crate::Writable for CONFIG0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/vcmailbox/config1.rs b/crates/bcm2835-lpa/src/vcmailbox/config1.rs index 3c238a6..8a50eee 100644 --- a/crates/bcm2835-lpa/src/vcmailbox/config1.rs +++ b/crates/bcm2835-lpa/src/vcmailbox/config1.rs @@ -1,59 +1,38 @@ #[doc = "Register `CONFIG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONFIG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config1](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONFIG1_SPEC; impl crate::RegisterSpec for CONFIG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [config1::R](R) reader structure"] -impl crate::Readable for CONFIG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [config1::W](W) writer structure"] +#[doc = "`read()` method returns [`config1::R`](R) reader structure"] +impl crate::Readable for CONFIG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config1::W`](W) writer structure"] impl crate::Writable for CONFIG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/vcmailbox/peek0.rs b/crates/bcm2835-lpa/src/vcmailbox/peek0.rs index 3b63843..9119a22 100644 --- a/crates/bcm2835-lpa/src/vcmailbox/peek0.rs +++ b/crates/bcm2835-lpa/src/vcmailbox/peek0.rs @@ -1,59 +1,38 @@ #[doc = "Register `PEEK0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PEEK0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek0](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peek0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEEK0_SPEC; impl crate::RegisterSpec for PEEK0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [peek0::R](R) reader structure"] -impl crate::Readable for PEEK0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [peek0::W](W) writer structure"] +#[doc = "`read()` method returns [`peek0::R`](R) reader structure"] +impl crate::Readable for PEEK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peek0::W`](W) writer structure"] impl crate::Writable for PEEK0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/vcmailbox/peek1.rs b/crates/bcm2835-lpa/src/vcmailbox/peek1.rs index 2431cc4..221331c 100644 --- a/crates/bcm2835-lpa/src/vcmailbox/peek1.rs +++ b/crates/bcm2835-lpa/src/vcmailbox/peek1.rs @@ -1,59 +1,38 @@ #[doc = "Register `PEEK1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PEEK1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek1](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peek1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEEK1_SPEC; impl crate::RegisterSpec for PEEK1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [peek1::R](R) reader structure"] -impl crate::Readable for PEEK1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [peek1::W](W) writer structure"] +#[doc = "`read()` method returns [`peek1::R`](R) reader structure"] +impl crate::Readable for PEEK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peek1::W`](W) writer structure"] impl crate::Writable for PEEK1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/vcmailbox/read.rs b/crates/bcm2835-lpa/src/vcmailbox/read.rs index 60b2d04..7328372 100644 --- a/crates/bcm2835-lpa/src/vcmailbox/read.rs +++ b/crates/bcm2835-lpa/src/vcmailbox/read.rs @@ -1,24 +1,19 @@ #[doc = "Register `READ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } -#[doc = "Read messages from the VideoCore\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [read](index.html) module"] +#[doc = "Read messages from the VideoCore\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`read::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct READ_SPEC; impl crate::RegisterSpec for READ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [read::R](R) reader structure"] -impl crate::Readable for READ_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`read::R`](R) reader structure"] +impl crate::Readable for READ_SPEC {} diff --git a/crates/bcm2835-lpa/src/vcmailbox/sender0.rs b/crates/bcm2835-lpa/src/vcmailbox/sender0.rs index cbeb2f1..4b8ec27 100644 --- a/crates/bcm2835-lpa/src/vcmailbox/sender0.rs +++ b/crates/bcm2835-lpa/src/vcmailbox/sender0.rs @@ -1,59 +1,38 @@ #[doc = "Register `SENDER0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SENDER0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sender0](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sender0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sender0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SENDER0_SPEC; impl crate::RegisterSpec for SENDER0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sender0::R](R) reader structure"] -impl crate::Readable for SENDER0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sender0::W](W) writer structure"] +#[doc = "`read()` method returns [`sender0::R`](R) reader structure"] +impl crate::Readable for SENDER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sender0::W`](W) writer structure"] impl crate::Writable for SENDER0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/vcmailbox/sender1.rs b/crates/bcm2835-lpa/src/vcmailbox/sender1.rs index 1537c2d..f787ecb 100644 --- a/crates/bcm2835-lpa/src/vcmailbox/sender1.rs +++ b/crates/bcm2835-lpa/src/vcmailbox/sender1.rs @@ -1,59 +1,38 @@ #[doc = "Register `SENDER1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SENDER1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sender1](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sender1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sender1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SENDER1_SPEC; impl crate::RegisterSpec for SENDER1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sender1::R](R) reader structure"] -impl crate::Readable for SENDER1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sender1::W](W) writer structure"] +#[doc = "`read()` method returns [`sender1::R`](R) reader structure"] +impl crate::Readable for SENDER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sender1::W`](W) writer structure"] impl crate::Writable for SENDER1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/vcmailbox/status0.rs b/crates/bcm2835-lpa/src/vcmailbox/status0.rs index 035e2a4..92a12f6 100644 --- a/crates/bcm2835-lpa/src/vcmailbox/status0.rs +++ b/crates/bcm2835-lpa/src/vcmailbox/status0.rs @@ -1,22 +1,9 @@ #[doc = "Register `STATUS0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EMPTY` reader - "] -pub type EMPTY_R = crate::BitReader; +pub type EMPTY_R = crate::BitReader; #[doc = "Field `FULL` reader - "] -pub type FULL_R = crate::BitReader; +pub type FULL_R = crate::BitReader; impl R { #[doc = "Bit 30"] #[inline(always)] @@ -29,12 +16,23 @@ impl R { FULL_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status0](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS0") + .field("full", &format_args!("{}", self.full().bit())) + .field("empty", &format_args!("{}", self.empty().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STATUS0_SPEC; impl crate::RegisterSpec for STATUS0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [status0::R](R) reader structure"] -impl crate::Readable for STATUS0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`status0::R`](R) reader structure"] +impl crate::Readable for STATUS0_SPEC {} diff --git a/crates/bcm2835-lpa/src/vcmailbox/status1.rs b/crates/bcm2835-lpa/src/vcmailbox/status1.rs index 1a7b501..64ad85f 100644 --- a/crates/bcm2835-lpa/src/vcmailbox/status1.rs +++ b/crates/bcm2835-lpa/src/vcmailbox/status1.rs @@ -1,59 +1,38 @@ #[doc = "Register `STATUS1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STATUS1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status1](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STATUS1_SPEC; impl crate::RegisterSpec for STATUS1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [status1::R](R) reader structure"] -impl crate::Readable for STATUS1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [status1::W](W) writer structure"] +#[doc = "`read()` method returns [`status1::R`](R) reader structure"] +impl crate::Readable for STATUS1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status1::W`](W) writer structure"] impl crate::Writable for STATUS1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2835-lpa/src/vcmailbox/write.rs b/crates/bcm2835-lpa/src/vcmailbox/write.rs index 4e09735..f34b6af 100644 --- a/crates/bcm2835-lpa/src/vcmailbox/write.rs +++ b/crates/bcm2835-lpa/src/vcmailbox/write.rs @@ -1,40 +1,29 @@ #[doc = "Register `WRITE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +pub type W = crate::W; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write messages to the VideoCore\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [write](index.html) module"] +#[doc = "Write messages to the VideoCore\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`write::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WRITE_SPEC; impl crate::RegisterSpec for WRITE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [write::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`write::W`](W) writer structure"] impl crate::Writable for WRITE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/Cargo.toml b/crates/bcm2837-lpa/Cargo.toml index ba2bbb0..50f622a 100644 --- a/crates/bcm2837-lpa/Cargo.toml +++ b/crates/bcm2837-lpa/Cargo.toml @@ -1,9 +1,9 @@ [package] name = "bcm2837-lpa" -version = "0.1.0" +version = "0.2.0" authors = ["Po-Yi Tsai "] edition = "2021" -rust-version = "1.61.0" +rust-version = "1.65.0" description = "Peripheral access crate for BCM2837 found in the Raspberry Pi 3 and Zero 2W." repository = "https://github.com/abt8601/raspi-pacs" license = "Unlicense" diff --git a/crates/bcm2837-lpa/src/aux.rs b/crates/bcm2837-lpa/src/aux.rs index 5380cb2..e9cf956 100644 --- a/crates/bcm2837-lpa/src/aux.rs +++ b/crates/bcm2837-lpa/src/aux.rs @@ -1,16 +1,19 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Interrupt status"] pub irq: IRQ, #[doc = "0x04 - Enable sub-peripherals"] pub enables: ENABLES, } -#[doc = "IRQ (rw) register accessor: an alias for `Reg`"] +#[doc = "IRQ (rw) register accessor: Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq`] +module"] pub type IRQ = crate::Reg; #[doc = "Interrupt status"] pub mod irq; -#[doc = "ENABLES (rw) register accessor: an alias for `Reg`"] +#[doc = "ENABLES (rw) register accessor: Enable sub-peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enables::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enables::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enables`] +module"] pub type ENABLES = crate::Reg; #[doc = "Enable sub-peripherals"] pub mod enables; diff --git a/crates/bcm2837-lpa/src/aux/enables.rs b/crates/bcm2837-lpa/src/aux/enables.rs index eb9fc6d..c84adb4 100644 --- a/crates/bcm2837-lpa/src/aux/enables.rs +++ b/crates/bcm2837-lpa/src/aux/enables.rs @@ -1,51 +1,19 @@ #[doc = "Register `ENABLES` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ENABLES` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UART_1` reader - UART1 enabled"] -pub type UART_1_R = crate::BitReader; +pub type UART_1_R = crate::BitReader; #[doc = "Field `UART_1` writer - UART1 enabled"] -pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +pub type UART_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_1` reader - SPI1 enabled"] -pub type SPI_1_R = crate::BitReader; +pub type SPI_1_R = crate::BitReader; #[doc = "Field `SPI_1` writer - SPI1 enabled"] -pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +pub type SPI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_2` reader - SPI2 enabled"] -pub type SPI_2_R = crate::BitReader; +pub type SPI_2_R = crate::BitReader; #[doc = "Field `SPI_2` writer - SPI2 enabled"] -pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>; +pub type SPI_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - UART1 enabled"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { SPI_2_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLES") + .field("spi_2", &format_args!("{}", self.spi_2().bit())) + .field("spi_1", &format_args!("{}", self.spi_1().bit())) + .field("uart_1", &format_args!("{}", self.uart_1().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - UART1 enabled"] #[inline(always)] #[must_use] - pub fn uart_1(&mut self) -> UART_1_W<0> { + pub fn uart_1(&mut self) -> UART_1_W { UART_1_W::new(self) } #[doc = "Bit 1 - SPI1 enabled"] #[inline(always)] #[must_use] - pub fn spi_1(&mut self) -> SPI_1_W<1> { + pub fn spi_1(&mut self) -> SPI_1_W { SPI_1_W::new(self) } #[doc = "Bit 2 - SPI2 enabled"] #[inline(always)] #[must_use] - pub fn spi_2(&mut self) -> SPI_2_W<2> { + pub fn spi_2(&mut self) -> SPI_2_W { SPI_2_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable sub-peripherals\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enables](index.html) module"] +#[doc = "Enable sub-peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enables::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enables::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLES_SPEC; impl crate::RegisterSpec for ENABLES_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enables::R](R) reader structure"] -impl crate::Readable for ENABLES_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [enables::W](W) writer structure"] +#[doc = "`read()` method returns [`enables::R`](R) reader structure"] +impl crate::Readable for ENABLES_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enables::W`](W) writer structure"] impl crate::Writable for ENABLES_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/aux/irq.rs b/crates/bcm2837-lpa/src/aux/irq.rs index a59c319..785d02a 100644 --- a/crates/bcm2837-lpa/src/aux/irq.rs +++ b/crates/bcm2837-lpa/src/aux/irq.rs @@ -1,51 +1,19 @@ #[doc = "Register `IRQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UART_1` reader - UART1 interrupt active"] -pub type UART_1_R = crate::BitReader; +pub type UART_1_R = crate::BitReader; #[doc = "Field `UART_1` writer - UART1 interrupt active"] -pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +pub type UART_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_1` reader - SPI1 interrupt active"] -pub type SPI_1_R = crate::BitReader; +pub type SPI_1_R = crate::BitReader; #[doc = "Field `SPI_1` writer - SPI1 interrupt active"] -pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +pub type SPI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_2` reader - SPI2 interrupt active"] -pub type SPI_2_R = crate::BitReader; +pub type SPI_2_R = crate::BitReader; #[doc = "Field `SPI_2` writer - SPI2 interrupt active"] -pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>; +pub type SPI_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - UART1 interrupt active"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { SPI_2_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IRQ") + .field("spi_2", &format_args!("{}", self.spi_2().bit())) + .field("spi_1", &format_args!("{}", self.spi_1().bit())) + .field("uart_1", &format_args!("{}", self.uart_1().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - UART1 interrupt active"] #[inline(always)] #[must_use] - pub fn uart_1(&mut self) -> UART_1_W<0> { + pub fn uart_1(&mut self) -> UART_1_W { UART_1_W::new(self) } #[doc = "Bit 1 - SPI1 interrupt active"] #[inline(always)] #[must_use] - pub fn spi_1(&mut self) -> SPI_1_W<1> { + pub fn spi_1(&mut self) -> SPI_1_W { SPI_1_W::new(self) } #[doc = "Bit 2 - SPI2 interrupt active"] #[inline(always)] #[must_use] - pub fn spi_2(&mut self) -> SPI_2_W<2> { + pub fn spi_2(&mut self) -> SPI_2_W { SPI_2_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq](index.html) module"] +#[doc = "Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRQ_SPEC; impl crate::RegisterSpec for IRQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irq::R](R) reader structure"] -impl crate::Readable for IRQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irq::W](W) writer structure"] +#[doc = "`read()` method returns [`irq::R`](R) reader structure"] +impl crate::Readable for IRQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq::W`](W) writer structure"] impl crate::Writable for IRQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/bsc0.rs b/crates/bcm2837-lpa/src/bsc0.rs index 8ccfb52..0d1c120 100644 --- a/crates/bcm2837-lpa/src/bsc0.rs +++ b/crates/bcm2837-lpa/src/bsc0.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control"] pub c: C, @@ -18,35 +19,43 @@ pub struct RegisterBlock { #[doc = "0x1c - Clock stretch timeout (broken on 283x)"] pub clkt: CLKT, } -#[doc = "C (rw) register accessor: an alias for `Reg`"] +#[doc = "C (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c`] +module"] pub type C = crate::Reg; #[doc = "Control"] pub mod c; -#[doc = "S (rw) register accessor: an alias for `Reg`"] +#[doc = "S (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s`] +module"] pub type S = crate::Reg; #[doc = "Status"] pub mod s; -#[doc = "DLEN (rw) register accessor: an alias for `Reg`"] +#[doc = "DLEN (rw) register accessor: Data length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlen`] +module"] pub type DLEN = crate::Reg; #[doc = "Data length"] pub mod dlen; -#[doc = "A (rw) register accessor: an alias for `Reg`"] +#[doc = "A (rw) register accessor: Slave address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a`] +module"] pub type A = crate::Reg; #[doc = "Slave address"] pub mod a; -#[doc = "FIFO (rw) register accessor: an alias for `Reg`"] +#[doc = "FIFO (rw) register accessor: Data FIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`] +module"] pub type FIFO = crate::Reg; #[doc = "Data FIFO"] pub mod fifo; -#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV (rw) register accessor: Clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div`] +module"] pub type DIV = crate::Reg; #[doc = "Clock divider"] pub mod div; -#[doc = "DEL (rw) register accessor: an alias for `Reg`"] +#[doc = "DEL (rw) register accessor: Data delay (Values must be under CDIV / 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`del::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`del::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@del`] +module"] pub type DEL = crate::Reg; #[doc = "Data delay (Values must be under CDIV / 2)"] pub mod del; -#[doc = "CLKT (rw) register accessor: an alias for `Reg`"] +#[doc = "CLKT (rw) register accessor: Clock stretch timeout (broken on 283x)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkt`] +module"] pub type CLKT = crate::Reg; #[doc = "Clock stretch timeout (broken on 283x)"] pub mod clkt; diff --git a/crates/bcm2837-lpa/src/bsc0/a.rs b/crates/bcm2837-lpa/src/bsc0/a.rs index d98d147..e9669f3 100644 --- a/crates/bcm2837-lpa/src/bsc0/a.rs +++ b/crates/bcm2837-lpa/src/bsc0/a.rs @@ -1,43 +1,11 @@ #[doc = "Register `A` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `A` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDR` reader - Slave address"] -pub type ADDR_R = crate::FieldReader; +pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - Slave address"] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, A_SPEC, u8, u8, 7, O>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; impl R { #[doc = "Bits 0:6 - Slave address"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { ADDR_R::new((self.bits & 0x7f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A") + .field("addr", &format_args!("{}", self.addr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - Slave address"] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<0> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Slave address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [a](index.html) module"] +#[doc = "Slave address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct A_SPEC; impl crate::RegisterSpec for A_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [a::R](R) reader structure"] -impl crate::Readable for A_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [a::W](W) writer structure"] +#[doc = "`read()` method returns [`a::R`](R) reader structure"] +impl crate::Readable for A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a::W`](W) writer structure"] impl crate::Writable for A_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/bsc0/c.rs b/crates/bcm2837-lpa/src/bsc0/c.rs index f62d48d..85f86f7 100644 --- a/crates/bcm2837-lpa/src/bsc0/c.rs +++ b/crates/bcm2837-lpa/src/bsc0/c.rs @@ -1,67 +1,35 @@ #[doc = "Register `C` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `READ` reader - Transfer is read"] -pub type READ_R = crate::BitReader; +pub type READ_R = crate::BitReader; #[doc = "Field `READ` writer - Transfer is read"] -pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type READ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLEAR` reader - Clear the FIFO"] -pub type CLEAR_R = crate::FieldReader; +pub type CLEAR_R = crate::FieldReader; #[doc = "Field `CLEAR` writer - Clear the FIFO"] -pub type CLEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, C_SPEC, u8, u8, 2, O>; +pub type CLEAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `ST` reader - Start transfer"] -pub type ST_R = crate::BitReader; +pub type ST_R = crate::BitReader; #[doc = "Field `ST` writer - Start transfer"] -pub type ST_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTD` reader - Interrupt on done"] -pub type INTD_R = crate::BitReader; +pub type INTD_R = crate::BitReader; #[doc = "Field `INTD` writer - Interrupt on done"] -pub type INTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type INTD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTT` reader - Interrupt on TX"] -pub type INTT_R = crate::BitReader; +pub type INTT_R = crate::BitReader; #[doc = "Field `INTT` writer - Interrupt on TX"] -pub type INTT_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type INTT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTR` reader - Interrupt on RX"] -pub type INTR_R = crate::BitReader; +pub type INTR_R = crate::BitReader; #[doc = "Field `INTR` writer - Interrupt on RX"] -pub type INTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type INTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2CEN` reader - I2C Enable"] -pub type I2CEN_R = crate::BitReader; +pub type I2CEN_R = crate::BitReader; #[doc = "Field `I2CEN` writer - I2C Enable"] -pub type I2CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, C_SPEC, bool, O>; +pub type I2CEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer is read"] #[inline(always)] @@ -99,68 +67,87 @@ impl R { I2CEN_R::new(((self.bits >> 15) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("C") + .field("i2cen", &format_args!("{}", self.i2cen().bit())) + .field("intr", &format_args!("{}", self.intr().bit())) + .field("intt", &format_args!("{}", self.intt().bit())) + .field("intd", &format_args!("{}", self.intd().bit())) + .field("st", &format_args!("{}", self.st().bit())) + .field("clear", &format_args!("{}", self.clear().bits())) + .field("read", &format_args!("{}", self.read().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer is read"] #[inline(always)] #[must_use] - pub fn read(&mut self) -> READ_W<0> { + pub fn read(&mut self) -> READ_W { READ_W::new(self) } #[doc = "Bits 4:5 - Clear the FIFO"] #[inline(always)] #[must_use] - pub fn clear(&mut self) -> CLEAR_W<4> { + pub fn clear(&mut self) -> CLEAR_W { CLEAR_W::new(self) } #[doc = "Bit 7 - Start transfer"] #[inline(always)] #[must_use] - pub fn st(&mut self) -> ST_W<7> { + pub fn st(&mut self) -> ST_W { ST_W::new(self) } #[doc = "Bit 8 - Interrupt on done"] #[inline(always)] #[must_use] - pub fn intd(&mut self) -> INTD_W<8> { + pub fn intd(&mut self) -> INTD_W { INTD_W::new(self) } #[doc = "Bit 9 - Interrupt on TX"] #[inline(always)] #[must_use] - pub fn intt(&mut self) -> INTT_W<9> { + pub fn intt(&mut self) -> INTT_W { INTT_W::new(self) } #[doc = "Bit 10 - Interrupt on RX"] #[inline(always)] #[must_use] - pub fn intr(&mut self) -> INTR_W<10> { + pub fn intr(&mut self) -> INTR_W { INTR_W::new(self) } #[doc = "Bit 15 - I2C Enable"] #[inline(always)] #[must_use] - pub fn i2cen(&mut self) -> I2CEN_W<15> { + pub fn i2cen(&mut self) -> I2CEN_W { I2CEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C_SPEC; impl crate::RegisterSpec for C_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c::R](R) reader structure"] -impl crate::Readable for C_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c::W](W) writer structure"] +#[doc = "`read()` method returns [`c::R`](R) reader structure"] +impl crate::Readable for C_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c::W`](W) writer structure"] impl crate::Writable for C_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/bsc0/clkt.rs b/crates/bcm2837-lpa/src/bsc0/clkt.rs index 15bc5c4..103f923 100644 --- a/crates/bcm2837-lpa/src/bsc0/clkt.rs +++ b/crates/bcm2837-lpa/src/bsc0/clkt.rs @@ -1,43 +1,11 @@ #[doc = "Register `CLKT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLKT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TOUT` reader - Number of SCL clock cycles to wait"] -pub type TOUT_R = crate::FieldReader; +pub type TOUT_R = crate::FieldReader; #[doc = "Field `TOUT` writer - Number of SCL clock cycles to wait"] -pub type TOUT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKT_SPEC, u16, u16, 16, O>; +pub type TOUT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { TOUT_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLKT") + .field("tout", &format_args!("{}", self.tout().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Number of SCL clock cycles to wait"] #[inline(always)] #[must_use] - pub fn tout(&mut self) -> TOUT_W<0> { + pub fn tout(&mut self) -> TOUT_W { TOUT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock stretch timeout (broken on 283x)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkt](index.html) module"] +#[doc = "Clock stretch timeout (broken on 283x)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKT_SPEC; impl crate::RegisterSpec for CLKT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clkt::R](R) reader structure"] -impl crate::Readable for CLKT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clkt::W](W) writer structure"] +#[doc = "`read()` method returns [`clkt::R`](R) reader structure"] +impl crate::Readable for CLKT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clkt::W`](W) writer structure"] impl crate::Writable for CLKT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/bsc0/del.rs b/crates/bcm2837-lpa/src/bsc0/del.rs index c39336b..4c0e876 100644 --- a/crates/bcm2837-lpa/src/bsc0/del.rs +++ b/crates/bcm2837-lpa/src/bsc0/del.rs @@ -1,47 +1,15 @@ #[doc = "Register `DEL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `REDL` reader - Delay before reading after a rising edge"] -pub type REDL_R = crate::FieldReader; +pub type REDL_R = crate::FieldReader; #[doc = "Field `REDL` writer - Delay before reading after a rising edge"] -pub type REDL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEL_SPEC, u16, u16, 16, O>; +pub type REDL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `FEDL` reader - Delay before reading after a falling edge"] -pub type FEDL_R = crate::FieldReader; +pub type FEDL_R = crate::FieldReader; #[doc = "Field `FEDL` writer - Delay before reading after a falling edge"] -pub type FEDL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DEL_SPEC, u16, u16, 16, O>; +pub type FEDL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Delay before reading after a rising edge"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { FEDL_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEL") + .field("fedl", &format_args!("{}", self.fedl().bits())) + .field("redl", &format_args!("{}", self.redl().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Delay before reading after a rising edge"] #[inline(always)] #[must_use] - pub fn redl(&mut self) -> REDL_W<0> { + pub fn redl(&mut self) -> REDL_W { REDL_W::new(self) } #[doc = "Bits 16:31 - Delay before reading after a falling edge"] #[inline(always)] #[must_use] - pub fn fedl(&mut self) -> FEDL_W<16> { + pub fn fedl(&mut self) -> FEDL_W { FEDL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data delay (Values must be under CDIV / 2)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [del](index.html) module"] +#[doc = "Data delay (Values must be under CDIV / 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`del::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`del::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEL_SPEC; impl crate::RegisterSpec for DEL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [del::R](R) reader structure"] -impl crate::Readable for DEL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [del::W](W) writer structure"] +#[doc = "`read()` method returns [`del::R`](R) reader structure"] +impl crate::Readable for DEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`del::W`](W) writer structure"] impl crate::Writable for DEL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/bsc0/div.rs b/crates/bcm2837-lpa/src/bsc0/div.rs index ce0aa5a..9ffd801 100644 --- a/crates/bcm2837-lpa/src/bsc0/div.rs +++ b/crates/bcm2837-lpa/src/bsc0/div.rs @@ -1,43 +1,11 @@ #[doc = "Register `DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CDIV` reader - Divide the source clock"] -pub type CDIV_R = crate::FieldReader; +pub type CDIV_R = crate::FieldReader; #[doc = "Field `CDIV` writer - Divide the source clock"] -pub type CDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 16, O>; +pub type CDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Divide the source clock"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { CDIV_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIV") + .field("cdiv", &format_args!("{}", self.cdiv().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Divide the source clock"] #[inline(always)] #[must_use] - pub fn cdiv(&mut self) -> CDIV_W<0> { + pub fn cdiv(&mut self) -> CDIV_W { CDIV_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](index.html) module"] +#[doc = "Clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SPEC; impl crate::RegisterSpec for DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div::R](R) reader structure"] -impl crate::Readable for DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +#[doc = "`read()` method returns [`div::R`](R) reader structure"] +impl crate::Readable for DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] impl crate::Writable for DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/bsc0/dlen.rs b/crates/bcm2837-lpa/src/bsc0/dlen.rs index 25e2771..5c7bb83 100644 --- a/crates/bcm2837-lpa/src/bsc0/dlen.rs +++ b/crates/bcm2837-lpa/src/bsc0/dlen.rs @@ -1,43 +1,11 @@ #[doc = "Register `DLEN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DLEN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DLEN` reader - Data length"] -pub type DLEN_R = crate::FieldReader; +pub type DLEN_R = crate::FieldReader; #[doc = "Field `DLEN` writer - Data length"] -pub type DLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLEN_SPEC, u16, u16, 16, O>; +pub type DLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Data length"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DLEN_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DLEN") + .field("dlen", &format_args!("{}", self.dlen().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Data length"] #[inline(always)] #[must_use] - pub fn dlen(&mut self) -> DLEN_W<0> { + pub fn dlen(&mut self) -> DLEN_W { DLEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlen](index.html) module"] +#[doc = "Data length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DLEN_SPEC; impl crate::RegisterSpec for DLEN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dlen::R](R) reader structure"] -impl crate::Readable for DLEN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dlen::W](W) writer structure"] +#[doc = "`read()` method returns [`dlen::R`](R) reader structure"] +impl crate::Readable for DLEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dlen::W`](W) writer structure"] impl crate::Writable for DLEN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/bsc0/fifo.rs b/crates/bcm2837-lpa/src/bsc0/fifo.rs index f85912b..0536908 100644 --- a/crates/bcm2837-lpa/src/bsc0/fifo.rs +++ b/crates/bcm2837-lpa/src/bsc0/fifo.rs @@ -1,43 +1,11 @@ #[doc = "Register `FIFO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FIFO` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - Access the FIFO"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - Access the FIFO"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u8, u8, 8, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Access the FIFO"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new((self.bits & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - Access the FIFO"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data FIFO\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"] +#[doc = "Data FIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_SPEC; impl crate::RegisterSpec for FIFO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fifo::R](R) reader structure"] -impl crate::Readable for FIFO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"] +#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] +impl crate::Readable for FIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"] impl crate::Writable for FIFO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/bsc0/s.rs b/crates/bcm2837-lpa/src/bsc0/s.rs index 45f365b..56cb006 100644 --- a/crates/bcm2837-lpa/src/bsc0/s.rs +++ b/crates/bcm2837-lpa/src/bsc0/s.rs @@ -1,65 +1,33 @@ #[doc = "Register `S` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `S` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TA` reader - Transfer active"] -pub type TA_R = crate::BitReader; +pub type TA_R = crate::BitReader; #[doc = "Field `DONE` reader - Transfer done"] -pub type DONE_R = crate::BitReader; +pub type DONE_R = crate::BitReader; #[doc = "Field `DONE` writer - Transfer done"] -pub type DONE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +pub type DONE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TXW` reader - FIFO needs to be written"] -pub type TXW_R = crate::BitReader; +pub type TXW_R = crate::BitReader; #[doc = "Field `RXR` reader - FIFO needs to be read"] -pub type RXR_R = crate::BitReader; +pub type RXR_R = crate::BitReader; #[doc = "Field `TXD` reader - FIFO has space for at least one byte"] -pub type TXD_R = crate::BitReader; +pub type TXD_R = crate::BitReader; #[doc = "Field `RXD` reader - FIFO contains at least one byte"] -pub type RXD_R = crate::BitReader; +pub type RXD_R = crate::BitReader; #[doc = "Field `TXE` reader - FIFO is empty. Nothing to transmit"] -pub type TXE_R = crate::BitReader; +pub type TXE_R = crate::BitReader; #[doc = "Field `RXF` reader - FIFO is full. Can't receive anything else"] -pub type RXF_R = crate::BitReader; +pub type RXF_R = crate::BitReader; #[doc = "Field `ERR` reader - Error: No ack"] -pub type ERR_R = crate::BitReader; +pub type ERR_R = crate::BitReader; #[doc = "Field `ERR` writer - Error: No ack"] -pub type ERR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +pub type ERR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLKT` reader - Clock stretch timeout"] -pub type CLKT_R = crate::BitReader; +pub type CLKT_R = crate::BitReader; #[doc = "Field `CLKT` writer - Clock stretch timeout"] -pub type CLKT_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, S_SPEC, bool, O>; +pub type CLKT_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer active"] #[inline(always)] @@ -112,44 +80,66 @@ impl R { CLKT_R::new(((self.bits >> 9) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("S") + .field("clkt", &format_args!("{}", self.clkt().bit())) + .field("err", &format_args!("{}", self.err().bit())) + .field("rxf", &format_args!("{}", self.rxf().bit())) + .field("txe", &format_args!("{}", self.txe().bit())) + .field("rxd", &format_args!("{}", self.rxd().bit())) + .field("txd", &format_args!("{}", self.txd().bit())) + .field("rxr", &format_args!("{}", self.rxr().bit())) + .field("txw", &format_args!("{}", self.txw().bit())) + .field("done", &format_args!("{}", self.done().bit())) + .field("ta", &format_args!("{}", self.ta().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Transfer done"] #[inline(always)] #[must_use] - pub fn done(&mut self) -> DONE_W<1> { + pub fn done(&mut self) -> DONE_W { DONE_W::new(self) } #[doc = "Bit 8 - Error: No ack"] #[inline(always)] #[must_use] - pub fn err(&mut self) -> ERR_W<8> { + pub fn err(&mut self) -> ERR_W { ERR_W::new(self) } #[doc = "Bit 9 - Clock stretch timeout"] #[inline(always)] #[must_use] - pub fn clkt(&mut self) -> CLKT_W<9> { + pub fn clkt(&mut self) -> CLKT_W { CLKT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s](index.html) module"] +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct S_SPEC; impl crate::RegisterSpec for S_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [s::R](R) reader structure"] -impl crate::Readable for S_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [s::W](W) writer structure"] +#[doc = "`read()` method returns [`s::R`](R) reader structure"] +impl crate::Readable for S_SPEC {} +#[doc = "`write(|w| ..)` method takes [`s::W`](W) writer structure"] impl crate::Writable for S_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0302; } diff --git a/crates/bcm2837-lpa/src/cm_pcm.rs b/crates/bcm2837-lpa/src/cm_pcm.rs index 0c60fcd..855e1b0 100644 --- a/crates/bcm2837-lpa/src/cm_pcm.rs +++ b/crates/bcm2837-lpa/src/cm_pcm.rs @@ -1,16 +1,19 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control / Status"] pub cs: CS, #[doc = "0x04 - Clock divisor"] pub div: DIV, } -#[doc = "CS (rw) register accessor: an alias for `Reg`"] +#[doc = "CS (rw) register accessor: Control / Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cs`] +module"] pub type CS = crate::Reg; #[doc = "Control / Status"] pub mod cs; -#[doc = "DIV (rw) register accessor: an alias for `Reg`"] +#[doc = "DIV (rw) register accessor: Clock divisor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div`] +module"] pub type DIV = crate::Reg; #[doc = "Clock divisor"] pub mod div; diff --git a/crates/bcm2837-lpa/src/cm_pcm/cs.rs b/crates/bcm2837-lpa/src/cm_pcm/cs.rs index 67ddd60..036729f 100644 --- a/crates/bcm2837-lpa/src/cm_pcm/cs.rs +++ b/crates/bcm2837-lpa/src/cm_pcm/cs.rs @@ -1,41 +1,9 @@ #[doc = "Register `CS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SRC` reader - Clock source"] -pub type SRC_R = crate::FieldReader; +pub type SRC_R = crate::FieldReader; #[doc = "Clock source\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -61,10 +29,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for SRC_A { + type Ux = u8; +} impl SRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 1 => Some(SRC_A::XOSC), 2 => Some(SRC_A::TEST0), @@ -76,99 +47,103 @@ impl SRC_R { _ => None, } } - #[doc = "Checks if the value of the field is `XOSC`"] + #[doc = "`1`"] #[inline(always)] pub fn is_xosc(&self) -> bool { *self == SRC_A::XOSC } - #[doc = "Checks if the value of the field is `TEST0`"] + #[doc = "`10`"] #[inline(always)] pub fn is_test0(&self) -> bool { *self == SRC_A::TEST0 } - #[doc = "Checks if the value of the field is `TEST1`"] + #[doc = "`11`"] #[inline(always)] pub fn is_test1(&self) -> bool { *self == SRC_A::TEST1 } - #[doc = "Checks if the value of the field is `PLLA`"] + #[doc = "`100`"] #[inline(always)] pub fn is_plla(&self) -> bool { *self == SRC_A::PLLA } - #[doc = "Checks if the value of the field is `PLLB`"] + #[doc = "`101`"] #[inline(always)] pub fn is_pllb(&self) -> bool { *self == SRC_A::PLLB } - #[doc = "Checks if the value of the field is `PLLC`"] + #[doc = "`110`"] #[inline(always)] pub fn is_pllc(&self) -> bool { *self == SRC_A::PLLC } - #[doc = "Checks if the value of the field is `HDMI`"] + #[doc = "`111`"] #[inline(always)] pub fn is_hdmi(&self) -> bool { *self == SRC_A::HDMI } } #[doc = "Field `SRC` writer - Clock source"] -pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, SRC_A, 4, O>; -impl<'a, const O: u8> SRC_W<'a, O> { +pub type SRC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, SRC_A>; +impl<'a, REG, const O: u8> SRC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1`"] #[inline(always)] - pub fn xosc(self) -> &'a mut W { + pub fn xosc(self) -> &'a mut crate::W { self.variant(SRC_A::XOSC) } #[doc = "`10`"] #[inline(always)] - pub fn test0(self) -> &'a mut W { + pub fn test0(self) -> &'a mut crate::W { self.variant(SRC_A::TEST0) } #[doc = "`11`"] #[inline(always)] - pub fn test1(self) -> &'a mut W { + pub fn test1(self) -> &'a mut crate::W { self.variant(SRC_A::TEST1) } #[doc = "`100`"] #[inline(always)] - pub fn plla(self) -> &'a mut W { + pub fn plla(self) -> &'a mut crate::W { self.variant(SRC_A::PLLA) } #[doc = "`101`"] #[inline(always)] - pub fn pllb(self) -> &'a mut W { + pub fn pllb(self) -> &'a mut crate::W { self.variant(SRC_A::PLLB) } #[doc = "`110`"] #[inline(always)] - pub fn pllc(self) -> &'a mut W { + pub fn pllc(self) -> &'a mut crate::W { self.variant(SRC_A::PLLC) } #[doc = "`111`"] #[inline(always)] - pub fn hdmi(self) -> &'a mut W { + pub fn hdmi(self) -> &'a mut crate::W { self.variant(SRC_A::HDMI) } } #[doc = "Field `ENAB` reader - Enable the clock generator. (Switch SRC first.)"] -pub type ENAB_R = crate::BitReader; +pub type ENAB_R = crate::BitReader; #[doc = "Field `ENAB` writer - Enable the clock generator. (Switch SRC first.)"] -pub type ENAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type ENAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `KILL` reader - Stop and reset the generator"] -pub type KILL_R = crate::BitReader; +pub type KILL_R = crate::BitReader; #[doc = "Field `KILL` writer - Stop and reset the generator"] -pub type KILL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type KILL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUSY` reader - Indicates the clock generator is running"] -pub type BUSY_R = crate::BitReader; +pub type BUSY_R = crate::BitReader; #[doc = "Field `FLIP` reader - Generate an edge on output. (For testing)"] -pub type FLIP_R = crate::BitReader; +pub type FLIP_R = crate::BitReader; #[doc = "Field `FLIP` writer - Generate an edge on output. (For testing)"] -pub type FLIP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type FLIP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MASH` reader - MASH control, stage count"] -pub type MASH_R = crate::FieldReader; +pub type MASH_R = crate::FieldReader; #[doc = "Field `MASH` writer - MASH control, stage count"] -pub type MASH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, u8, 2, O>; +pub type MASH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Password. Always 0x5a\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -182,12 +157,19 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for PASSWD_AW { + type Ux = u8; +} #[doc = "Field `PASSWD` writer - Password. Always 0x5a"] -pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, PASSWD_AW, 8, O>; -impl<'a, const O: u8> PASSWD_W<'a, O> { +pub type PASSWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, PASSWD_AW>; +impl<'a, REG, const O: u8> PASSWD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1011010`"] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(PASSWD_AW::PASSWD) } } @@ -223,62 +205,80 @@ impl R { MASH_R::new(((self.bits >> 9) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CS") + .field("mash", &format_args!("{}", self.mash().bits())) + .field("flip", &format_args!("{}", self.flip().bit())) + .field("busy", &format_args!("{}", self.busy().bit())) + .field("kill", &format_args!("{}", self.kill().bit())) + .field("enab", &format_args!("{}", self.enab().bit())) + .field("src", &format_args!("{}", self.src().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:3 - Clock source"] #[inline(always)] #[must_use] - pub fn src(&mut self) -> SRC_W<0> { + pub fn src(&mut self) -> SRC_W { SRC_W::new(self) } #[doc = "Bit 4 - Enable the clock generator. (Switch SRC first.)"] #[inline(always)] #[must_use] - pub fn enab(&mut self) -> ENAB_W<4> { + pub fn enab(&mut self) -> ENAB_W { ENAB_W::new(self) } #[doc = "Bit 5 - Stop and reset the generator"] #[inline(always)] #[must_use] - pub fn kill(&mut self) -> KILL_W<5> { + pub fn kill(&mut self) -> KILL_W { KILL_W::new(self) } #[doc = "Bit 8 - Generate an edge on output. (For testing)"] #[inline(always)] #[must_use] - pub fn flip(&mut self) -> FLIP_W<8> { + pub fn flip(&mut self) -> FLIP_W { FLIP_W::new(self) } #[doc = "Bits 9:10 - MASH control, stage count"] #[inline(always)] #[must_use] - pub fn mash(&mut self) -> MASH_W<9> { + pub fn mash(&mut self) -> MASH_W { MASH_W::new(self) } #[doc = "Bits 24:31 - Password. Always 0x5a"] #[inline(always)] #[must_use] - pub fn passwd(&mut self) -> PASSWD_W<24> { + pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control / Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +#[doc = "Control / Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CS_SPEC; impl crate::RegisterSpec for CS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cs::R](R) reader structure"] -impl crate::Readable for CS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/cm_pcm/div.rs b/crates/bcm2837-lpa/src/cm_pcm/div.rs index a0c99f8..825974e 100644 --- a/crates/bcm2837-lpa/src/cm_pcm/div.rs +++ b/crates/bcm2837-lpa/src/cm_pcm/div.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DIVF` reader - Fractional part of divisor"] -pub type DIVF_R = crate::FieldReader; +pub type DIVF_R = crate::FieldReader; #[doc = "Field `DIVF` writer - Fractional part of divisor"] -pub type DIVF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 12, O>; +pub type DIVF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; #[doc = "Field `DIVI` reader - Integer part of divisor"] -pub type DIVI_R = crate::FieldReader; +pub type DIVI_R = crate::FieldReader; #[doc = "Field `DIVI` writer - Integer part of divisor"] -pub type DIVI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u16, u16, 12, O>; +pub type DIVI_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; #[doc = "Password. Always 0x5a\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -55,12 +23,19 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for PASSWD_AW { + type Ux = u8; +} #[doc = "Field `PASSWD` writer - Password. Always 0x5a"] -pub type PASSWD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIV_SPEC, u8, PASSWD_AW, 8, O>; -impl<'a, const O: u8> PASSWD_W<'a, O> { +pub type PASSWD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, PASSWD_AW>; +impl<'a, REG, const O: u8> PASSWD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1011010`"] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(PASSWD_AW::PASSWD) } } @@ -76,44 +51,58 @@ impl R { DIVI_R::new(((self.bits >> 12) & 0x0fff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIV") + .field("divi", &format_args!("{}", self.divi().bits())) + .field("divf", &format_args!("{}", self.divf().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:11 - Fractional part of divisor"] #[inline(always)] #[must_use] - pub fn divf(&mut self) -> DIVF_W<0> { + pub fn divf(&mut self) -> DIVF_W { DIVF_W::new(self) } #[doc = "Bits 12:23 - Integer part of divisor"] #[inline(always)] #[must_use] - pub fn divi(&mut self) -> DIVI_W<12> { + pub fn divi(&mut self) -> DIVI_W { DIVI_W::new(self) } #[doc = "Bits 24:31 - Password. Always 0x5a"] #[inline(always)] #[must_use] - pub fn passwd(&mut self) -> PASSWD_W<24> { + pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [div](index.html) module"] +#[doc = "Clock divisor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SPEC; impl crate::RegisterSpec for DIV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [div::R](R) reader structure"] -impl crate::Readable for DIV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"] +#[doc = "`read()` method returns [`div::R`](R) reader structure"] +impl crate::Readable for DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] impl crate::Writable for DIV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc.rs b/crates/bcm2837-lpa/src/emmc.rs index e4be2cf..597a27a 100644 --- a/crates/bcm2837-lpa/src/emmc.rs +++ b/crates/bcm2837-lpa/src/emmc.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Argument for ACMD23 command"] pub arg2: ARG2, @@ -59,107 +60,133 @@ pub struct RegisterBlock { #[doc = "0xfc - Version information and slot interrupt status"] pub slotisr_ver: SLOTISR_VER, } -#[doc = "ARG2 (rw) register accessor: an alias for `Reg`"] +#[doc = "ARG2 (rw) register accessor: Argument for ACMD23 command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arg2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arg2`] +module"] pub type ARG2 = crate::Reg; #[doc = "Argument for ACMD23 command"] pub mod arg2; -#[doc = "BLKSIZECNT (rw) register accessor: an alias for `Reg`"] +#[doc = "BLKSIZECNT (rw) register accessor: Numer and size in bytes for data block to be transferred\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blksizecnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blksizecnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blksizecnt`] +module"] pub type BLKSIZECNT = crate::Reg; #[doc = "Numer and size in bytes for data block to be transferred"] pub mod blksizecnt; -#[doc = "ARG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "ARG1 (rw) register accessor: Argument for everything but ACMD23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arg1`] +module"] pub type ARG1 = crate::Reg; #[doc = "Argument for everything but ACMD23"] pub mod arg1; -#[doc = "CMDTM (rw) register accessor: an alias for `Reg`"] +#[doc = "CMDTM (rw) register accessor: Issue commands to the card\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdtm::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdtm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdtm`] +module"] pub type CMDTM = crate::Reg; #[doc = "Issue commands to the card"] pub mod cmdtm; -#[doc = "RESP0 (rw) register accessor: an alias for `Reg`"] +#[doc = "RESP0 (rw) register accessor: Status bits of the response\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp0`] +module"] pub type RESP0 = crate::Reg; #[doc = "Status bits of the response"] pub mod resp0; -#[doc = "RESP1 (rw) register accessor: an alias for `Reg`"] +#[doc = "RESP1 (rw) register accessor: Bits 63:32 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp1`] +module"] pub type RESP1 = crate::Reg; #[doc = "Bits 63:32 of CMD2 and CMD10 responses"] pub mod resp1; -#[doc = "RESP2 (rw) register accessor: an alias for `Reg`"] +#[doc = "RESP2 (rw) register accessor: Bits 95:64 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp2`] +module"] pub type RESP2 = crate::Reg; #[doc = "Bits 95:64 of CMD2 and CMD10 responses"] pub mod resp2; -#[doc = "RESP3 (rw) register accessor: an alias for `Reg`"] +#[doc = "RESP3 (rw) register accessor: Bits 127:96 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp3`] +module"] pub type RESP3 = crate::Reg; #[doc = "Bits 127:96 of CMD2 and CMD10 responses"] pub mod resp3; -#[doc = "DATA (rw) register accessor: an alias for `Reg`"] +#[doc = "DATA (rw) register accessor: Data to/from the card\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] +module"] pub type DATA = crate::Reg; #[doc = "Data to/from the card"] pub mod data; -#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +#[doc = "STATUS (rw) register accessor: Status info for debugging\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] +module"] pub type STATUS = crate::Reg; #[doc = "Status info for debugging"] pub mod status; -#[doc = "CONTROL0 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONTROL0 (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control0`] +module"] pub type CONTROL0 = crate::Reg; #[doc = "Control"] pub mod control0; -#[doc = "CONTROL1 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONTROL1 (rw) register accessor: Configure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control1`] +module"] pub type CONTROL1 = crate::Reg; #[doc = "Configure"] pub mod control1; -#[doc = "INTERRUPT (rw) register accessor: an alias for `Reg`"] +#[doc = "INTERRUPT (rw) register accessor: Interrupt flags\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrupt`] +module"] pub type INTERRUPT = crate::Reg; #[doc = "Interrupt flags"] pub mod interrupt; -#[doc = "IRPT_MASK (rw) register accessor: an alias for `Reg`"] +#[doc = "IRPT_MASK (rw) register accessor: Mask interrupts that change in INTERRUPT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irpt_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irpt_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irpt_mask`] +module"] pub type IRPT_MASK = crate::Reg; #[doc = "Mask interrupts that change in INTERRUPT"] pub mod irpt_mask; -#[doc = "IRPT_EN (rw) register accessor: an alias for `Reg`"] +#[doc = "IRPT_EN (rw) register accessor: Enable interrupt to core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irpt_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irpt_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irpt_en`] +module"] pub type IRPT_EN = crate::Reg; #[doc = "Enable interrupt to core"] pub mod irpt_en; -#[doc = "CONTROL2 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONTROL2 (rw) register accessor: Control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control2`] +module"] pub type CONTROL2 = crate::Reg; #[doc = "Control 2"] pub mod control2; -#[doc = "FORCE_IRPT (rw) register accessor: an alias for `Reg`"] +#[doc = "FORCE_IRPT (rw) register accessor: Force an interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`force_irpt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`force_irpt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@force_irpt`] +module"] pub type FORCE_IRPT = crate::Reg; #[doc = "Force an interrupt"] pub mod force_irpt; -#[doc = "BOOT_TIMEOUT (rw) register accessor: an alias for `Reg`"] +#[doc = "BOOT_TIMEOUT (rw) register accessor: Number of SD clock cycles to wait for boot\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`boot_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`boot_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@boot_timeout`] +module"] pub type BOOT_TIMEOUT = crate::Reg; #[doc = "Number of SD clock cycles to wait for boot"] pub mod boot_timeout; -#[doc = "DBG_SEL (rw) register accessor: an alias for `Reg`"] +#[doc = "DBG_SEL (rw) register accessor: What submodules are accessed by the debug bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbg_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbg_sel`] +module"] pub type DBG_SEL = crate::Reg; #[doc = "What submodules are accessed by the debug bus"] pub mod dbg_sel; -#[doc = "EXRDFIFO_CFG (rw) register accessor: an alias for `Reg`"] +#[doc = "EXRDFIFO_CFG (rw) register accessor: Fine tune DMA request generation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exrdfifo_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrdfifo_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exrdfifo_cfg`] +module"] pub type EXRDFIFO_CFG = crate::Reg; #[doc = "Fine tune DMA request generation"] pub mod exrdfifo_cfg; -#[doc = "EXRDFIFO_EN (rw) register accessor: an alias for `Reg`"] +#[doc = "EXRDFIFO_EN (rw) register accessor: Enable the extension data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exrdfifo_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrdfifo_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exrdfifo_en`] +module"] pub type EXRDFIFO_EN = crate::Reg; #[doc = "Enable the extension data register"] pub mod exrdfifo_en; -#[doc = "TUNE_STEP (rw) register accessor: an alias for `Reg`"] +#[doc = "TUNE_STEP (rw) register accessor: Sample clock delay step duration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_step::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_step::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tune_step`] +module"] pub type TUNE_STEP = crate::Reg; #[doc = "Sample clock delay step duration"] pub mod tune_step; -#[doc = "TUNE_STEPS_STD (rw) register accessor: an alias for `Reg`"] +#[doc = "TUNE_STEPS_STD (rw) register accessor: Sample clock delay step count for SDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_steps_std::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_steps_std::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tune_steps_std`] +module"] pub type TUNE_STEPS_STD = crate::Reg; #[doc = "Sample clock delay step count for SDR"] pub mod tune_steps_std; -#[doc = "TUNE_STEPS_DDR (rw) register accessor: an alias for `Reg`"] +#[doc = "TUNE_STEPS_DDR (rw) register accessor: Sample clock delay step count for DDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_steps_ddr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_steps_ddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tune_steps_ddr`] +module"] pub type TUNE_STEPS_DDR = crate::Reg; #[doc = "Sample clock delay step count for DDR"] pub mod tune_steps_ddr; -#[doc = "SPI_INT_SPT (rw) register accessor: an alias for `Reg`"] +#[doc = "SPI_INT_SPT (rw) register accessor: Interrupts in SPI mode depend on CS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_int_spt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_int_spt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_int_spt`] +module"] pub type SPI_INT_SPT = crate::Reg; #[doc = "Interrupts in SPI mode depend on CS"] pub mod spi_int_spt; -#[doc = "SLOTISR_VER (rw) register accessor: an alias for `Reg`"] +#[doc = "SLOTISR_VER (rw) register accessor: Version information and slot interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slotisr_ver::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slotisr_ver::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slotisr_ver`] +module"] pub type SLOTISR_VER = crate::Reg; #[doc = "Version information and slot interrupt status"] pub mod slotisr_ver; diff --git a/crates/bcm2837-lpa/src/emmc/arg1.rs b/crates/bcm2837-lpa/src/emmc/arg1.rs index 4a25300..491f890 100644 --- a/crates/bcm2837-lpa/src/emmc/arg1.rs +++ b/crates/bcm2837-lpa/src/emmc/arg1.rs @@ -1,59 +1,38 @@ #[doc = "Register `ARG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ARG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Argument for everything but ACMD23\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arg1](index.html) module"] +#[doc = "Argument for everything but ACMD23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ARG1_SPEC; impl crate::RegisterSpec for ARG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [arg1::R](R) reader structure"] -impl crate::Readable for ARG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [arg1::W](W) writer structure"] +#[doc = "`read()` method returns [`arg1::R`](R) reader structure"] +impl crate::Readable for ARG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`arg1::W`](W) writer structure"] impl crate::Writable for ARG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/arg2.rs b/crates/bcm2837-lpa/src/emmc/arg2.rs index b295b35..90678c2 100644 --- a/crates/bcm2837-lpa/src/emmc/arg2.rs +++ b/crates/bcm2837-lpa/src/emmc/arg2.rs @@ -1,59 +1,38 @@ #[doc = "Register `ARG2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ARG2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Argument for ACMD23 command\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arg2](index.html) module"] +#[doc = "Argument for ACMD23 command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arg2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ARG2_SPEC; impl crate::RegisterSpec for ARG2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [arg2::R](R) reader structure"] -impl crate::Readable for ARG2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [arg2::W](W) writer structure"] +#[doc = "`read()` method returns [`arg2::R`](R) reader structure"] +impl crate::Readable for ARG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`arg2::W`](W) writer structure"] impl crate::Writable for ARG2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/blksizecnt.rs b/crates/bcm2837-lpa/src/emmc/blksizecnt.rs index f3dabd8..c6eec15 100644 --- a/crates/bcm2837-lpa/src/emmc/blksizecnt.rs +++ b/crates/bcm2837-lpa/src/emmc/blksizecnt.rs @@ -1,47 +1,15 @@ #[doc = "Register `BLKSIZECNT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BLKSIZECNT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BLKSIZE` reader - Block size in bytes"] -pub type BLKSIZE_R = crate::FieldReader; +pub type BLKSIZE_R = crate::FieldReader; #[doc = "Field `BLKSIZE` writer - Block size in bytes"] -pub type BLKSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BLKSIZECNT_SPEC, u16, u16, 10, O>; +pub type BLKSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `BLKCNT` reader - Number of blocks to be transferred"] -pub type BLKCNT_R = crate::FieldReader; +pub type BLKCNT_R = crate::FieldReader; #[doc = "Field `BLKCNT` writer - Number of blocks to be transferred"] -pub type BLKCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BLKSIZECNT_SPEC, u16, u16, 16, O>; +pub type BLKCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:9 - Block size in bytes"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { BLKCNT_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLKSIZECNT") + .field("blkcnt", &format_args!("{}", self.blkcnt().bits())) + .field("blksize", &format_args!("{}", self.blksize().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:9 - Block size in bytes"] #[inline(always)] #[must_use] - pub fn blksize(&mut self) -> BLKSIZE_W<0> { + pub fn blksize(&mut self) -> BLKSIZE_W { BLKSIZE_W::new(self) } #[doc = "Bits 16:31 - Number of blocks to be transferred"] #[inline(always)] #[must_use] - pub fn blkcnt(&mut self) -> BLKCNT_W<16> { + pub fn blkcnt(&mut self) -> BLKCNT_W { BLKCNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Numer and size in bytes for data block to be transferred\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [blksizecnt](index.html) module"] +#[doc = "Numer and size in bytes for data block to be transferred\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blksizecnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blksizecnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BLKSIZECNT_SPEC; impl crate::RegisterSpec for BLKSIZECNT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [blksizecnt::R](R) reader structure"] -impl crate::Readable for BLKSIZECNT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [blksizecnt::W](W) writer structure"] +#[doc = "`read()` method returns [`blksizecnt::R`](R) reader structure"] +impl crate::Readable for BLKSIZECNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blksizecnt::W`](W) writer structure"] impl crate::Writable for BLKSIZECNT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/boot_timeout.rs b/crates/bcm2837-lpa/src/emmc/boot_timeout.rs index 5a9943a..41d8ff1 100644 --- a/crates/bcm2837-lpa/src/emmc/boot_timeout.rs +++ b/crates/bcm2837-lpa/src/emmc/boot_timeout.rs @@ -1,59 +1,38 @@ #[doc = "Register `BOOT_TIMEOUT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BOOT_TIMEOUT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Number of SD clock cycles to wait for boot\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [boot_timeout](index.html) module"] +#[doc = "Number of SD clock cycles to wait for boot\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`boot_timeout::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`boot_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BOOT_TIMEOUT_SPEC; impl crate::RegisterSpec for BOOT_TIMEOUT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [boot_timeout::R](R) reader structure"] -impl crate::Readable for BOOT_TIMEOUT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [boot_timeout::W](W) writer structure"] +#[doc = "`read()` method returns [`boot_timeout::R`](R) reader structure"] +impl crate::Readable for BOOT_TIMEOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot_timeout::W`](W) writer structure"] impl crate::Writable for BOOT_TIMEOUT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/cmdtm.rs b/crates/bcm2837-lpa/src/emmc/cmdtm.rs index e30a873..6ff28c8 100644 --- a/crates/bcm2837-lpa/src/emmc/cmdtm.rs +++ b/crates/bcm2837-lpa/src/emmc/cmdtm.rs @@ -1,45 +1,13 @@ #[doc = "Register `CMDTM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CMDTM` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TM_BLKCNT_EN` reader - Enable block counter"] -pub type TM_BLKCNT_EN_R = crate::BitReader; +pub type TM_BLKCNT_EN_R = crate::BitReader; #[doc = "Field `TM_BLKCNT_EN` writer - Enable block counter"] -pub type TM_BLKCNT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +pub type TM_BLKCNT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TM_AUTO_CMD_EN` reader - Command after completion"] -pub type TM_AUTO_CMD_EN_R = crate::FieldReader; +pub type TM_AUTO_CMD_EN_R = crate::FieldReader; #[doc = "Command after completion\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -57,10 +25,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for TM_AUTO_CMD_EN_A { + type Ux = u8; +} impl TM_AUTO_CMD_EN_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(TM_AUTO_CMD_EN_A::NONE), 1 => Some(TM_AUTO_CMD_EN_A::CMD12), @@ -68,39 +39,43 @@ impl TM_AUTO_CMD_EN_R { _ => None, } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_none(&self) -> bool { *self == TM_AUTO_CMD_EN_A::NONE } - #[doc = "Checks if the value of the field is `CMD12`"] + #[doc = "`1`"] #[inline(always)] pub fn is_cmd12(&self) -> bool { *self == TM_AUTO_CMD_EN_A::CMD12 } - #[doc = "Checks if the value of the field is `CMD23`"] + #[doc = "`10`"] #[inline(always)] pub fn is_cmd23(&self) -> bool { *self == TM_AUTO_CMD_EN_A::CMD23 } } #[doc = "Field `TM_AUTO_CMD_EN` writer - Command after completion"] -pub type TM_AUTO_CMD_EN_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, CMDTM_SPEC, u8, TM_AUTO_CMD_EN_A, 2, O>; -impl<'a, const O: u8> TM_AUTO_CMD_EN_W<'a, O> { +pub type TM_AUTO_CMD_EN_W<'a, REG, const O: u8> = + crate::FieldWriter<'a, REG, 2, O, TM_AUTO_CMD_EN_A>; +impl<'a, REG, const O: u8> TM_AUTO_CMD_EN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(TM_AUTO_CMD_EN_A::NONE) } #[doc = "`1`"] #[inline(always)] - pub fn cmd12(self) -> &'a mut W { + pub fn cmd12(self) -> &'a mut crate::W { self.variant(TM_AUTO_CMD_EN_A::CMD12) } #[doc = "`10`"] #[inline(always)] - pub fn cmd23(self) -> &'a mut W { + pub fn cmd23(self) -> &'a mut crate::W { self.variant(TM_AUTO_CMD_EN_A::CMD23) } } @@ -123,34 +98,37 @@ impl From for bool { impl TM_DAT_DIR_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TM_DAT_DIR_A { + pub const fn variant(&self) -> TM_DAT_DIR_A { match self.bits { false => TM_DAT_DIR_A::HOST_TO_CARD, true => TM_DAT_DIR_A::CARD_TO_HOST, } } - #[doc = "Checks if the value of the field is `HOST_TO_CARD`"] + #[doc = "`0`"] #[inline(always)] pub fn is_host_to_card(&self) -> bool { *self == TM_DAT_DIR_A::HOST_TO_CARD } - #[doc = "Checks if the value of the field is `CARD_TO_HOST`"] + #[doc = "`1`"] #[inline(always)] pub fn is_card_to_host(&self) -> bool { *self == TM_DAT_DIR_A::CARD_TO_HOST } } #[doc = "Field `TM_DAT_DIR` writer - Direction of data transfer"] -pub type TM_DAT_DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, TM_DAT_DIR_A, O>; -impl<'a, const O: u8> TM_DAT_DIR_W<'a, O> { +pub type TM_DAT_DIR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TM_DAT_DIR_A>; +impl<'a, REG, const O: u8> TM_DAT_DIR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn host_to_card(self) -> &'a mut W { + pub fn host_to_card(self) -> &'a mut crate::W { self.variant(TM_DAT_DIR_A::HOST_TO_CARD) } #[doc = "`1`"] #[inline(always)] - pub fn card_to_host(self) -> &'a mut W { + pub fn card_to_host(self) -> &'a mut crate::W { self.variant(TM_DAT_DIR_A::CARD_TO_HOST) } } @@ -173,40 +151,42 @@ impl From for bool { impl TM_MULTI_BLOCK_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> TM_MULTI_BLOCK_A { + pub const fn variant(&self) -> TM_MULTI_BLOCK_A { match self.bits { false => TM_MULTI_BLOCK_A::SINGLE, true => TM_MULTI_BLOCK_A::MULTIPLE, } } - #[doc = "Checks if the value of the field is `SINGLE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_single(&self) -> bool { *self == TM_MULTI_BLOCK_A::SINGLE } - #[doc = "Checks if the value of the field is `MULTIPLE`"] + #[doc = "`1`"] #[inline(always)] pub fn is_multiple(&self) -> bool { *self == TM_MULTI_BLOCK_A::MULTIPLE } } #[doc = "Field `TM_MULTI_BLOCK` writer - Type of data transfer"] -pub type TM_MULTI_BLOCK_W<'a, const O: u8> = - crate::BitWriter<'a, u32, CMDTM_SPEC, TM_MULTI_BLOCK_A, O>; -impl<'a, const O: u8> TM_MULTI_BLOCK_W<'a, O> { +pub type TM_MULTI_BLOCK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TM_MULTI_BLOCK_A>; +impl<'a, REG, const O: u8> TM_MULTI_BLOCK_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn single(self) -> &'a mut W { + pub fn single(self) -> &'a mut crate::W { self.variant(TM_MULTI_BLOCK_A::SINGLE) } #[doc = "`1`"] #[inline(always)] - pub fn multiple(self) -> &'a mut W { + pub fn multiple(self) -> &'a mut crate::W { self.variant(TM_MULTI_BLOCK_A::MULTIPLE) } } #[doc = "Field `CMD_RSPNS_TYPE` reader - Type of expected response"] -pub type CMD_RSPNS_TYPE_R = crate::FieldReader; +pub type CMD_RSPNS_TYPE_R = crate::FieldReader; #[doc = "Type of expected response\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -226,10 +206,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for RESPONSE_A { + type Ux = u8; +} impl CMD_RSPNS_TYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> RESPONSE_A { + pub const fn variant(&self) -> RESPONSE_A { match self.bits { 0 => RESPONSE_A::NONE, 1 => RESPONSE_A::_136BITS, @@ -238,66 +221,69 @@ impl CMD_RSPNS_TYPE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_none(&self) -> bool { *self == RESPONSE_A::NONE } - #[doc = "Checks if the value of the field is `_136BITS`"] + #[doc = "`1`"] #[inline(always)] pub fn is_136bits(&self) -> bool { *self == RESPONSE_A::_136BITS } - #[doc = "Checks if the value of the field is `_48BITS`"] + #[doc = "`10`"] #[inline(always)] pub fn is_48bits(&self) -> bool { *self == RESPONSE_A::_48BITS } - #[doc = "Checks if the value of the field is `_48BITS_USING_BUSY`"] + #[doc = "`11`"] #[inline(always)] pub fn is_48bits_using_busy(&self) -> bool { *self == RESPONSE_A::_48BITS_USING_BUSY } } #[doc = "Field `CMD_RSPNS_TYPE` writer - Type of expected response"] -pub type CMD_RSPNS_TYPE_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, CMDTM_SPEC, u8, RESPONSE_A, 2, O>; -impl<'a, const O: u8> CMD_RSPNS_TYPE_W<'a, O> { +pub type CMD_RSPNS_TYPE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, RESPONSE_A>; +impl<'a, REG, const O: u8> CMD_RSPNS_TYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(RESPONSE_A::NONE) } #[doc = "`1`"] #[inline(always)] - pub fn _136bits(self) -> &'a mut W { + pub fn _136bits(self) -> &'a mut crate::W { self.variant(RESPONSE_A::_136BITS) } #[doc = "`10`"] #[inline(always)] - pub fn _48bits(self) -> &'a mut W { + pub fn _48bits(self) -> &'a mut crate::W { self.variant(RESPONSE_A::_48BITS) } #[doc = "`11`"] #[inline(always)] - pub fn _48bits_using_busy(self) -> &'a mut W { + pub fn _48bits_using_busy(self) -> &'a mut crate::W { self.variant(RESPONSE_A::_48BITS_USING_BUSY) } } #[doc = "Field `CMD_CRCCHK_EN` reader - Check the responses CRC"] -pub type CMD_CRCCHK_EN_R = crate::BitReader; +pub type CMD_CRCCHK_EN_R = crate::BitReader; #[doc = "Field `CMD_CRCCHK_EN` writer - Check the responses CRC"] -pub type CMD_CRCCHK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +pub type CMD_CRCCHK_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMD_IXCHK_EN` reader - Check that the response has the same command index"] -pub type CMD_IXCHK_EN_R = crate::BitReader; +pub type CMD_IXCHK_EN_R = crate::BitReader; #[doc = "Field `CMD_IXCHK_EN` writer - Check that the response has the same command index"] -pub type CMD_IXCHK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +pub type CMD_IXCHK_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMD_ISDATA` reader - Command involves data"] -pub type CMD_ISDATA_R = crate::BitReader; +pub type CMD_ISDATA_R = crate::BitReader; #[doc = "Field `CMD_ISDATA` writer - Command involves data"] -pub type CMD_ISDATA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMDTM_SPEC, bool, O>; +pub type CMD_ISDATA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMD_TYPE` reader - Type of command to be issued"] -pub type CMD_TYPE_R = crate::FieldReader; +pub type CMD_TYPE_R = crate::FieldReader; #[doc = "Type of command to be issued\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -317,10 +303,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for CMD_TYPE_A { + type Ux = u8; +} impl CMD_TYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> CMD_TYPE_A { + pub const fn variant(&self) -> CMD_TYPE_A { match self.bits { 0 => CMD_TYPE_A::NORMAL, 1 => CMD_TYPE_A::SUSPEND, @@ -329,56 +318,59 @@ impl CMD_TYPE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "`0`"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == CMD_TYPE_A::NORMAL } - #[doc = "Checks if the value of the field is `SUSPEND`"] + #[doc = "`1`"] #[inline(always)] pub fn is_suspend(&self) -> bool { *self == CMD_TYPE_A::SUSPEND } - #[doc = "Checks if the value of the field is `RESUME`"] + #[doc = "`10`"] #[inline(always)] pub fn is_resume(&self) -> bool { *self == CMD_TYPE_A::RESUME } - #[doc = "Checks if the value of the field is `ABORT`"] + #[doc = "`11`"] #[inline(always)] pub fn is_abort(&self) -> bool { *self == CMD_TYPE_A::ABORT } } #[doc = "Field `CMD_TYPE` writer - Type of command to be issued"] -pub type CMD_TYPE_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, CMDTM_SPEC, u8, CMD_TYPE_A, 2, O>; -impl<'a, const O: u8> CMD_TYPE_W<'a, O> { +pub type CMD_TYPE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, CMD_TYPE_A>; +impl<'a, REG, const O: u8> CMD_TYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(CMD_TYPE_A::NORMAL) } #[doc = "`1`"] #[inline(always)] - pub fn suspend(self) -> &'a mut W { + pub fn suspend(self) -> &'a mut crate::W { self.variant(CMD_TYPE_A::SUSPEND) } #[doc = "`10`"] #[inline(always)] - pub fn resume(self) -> &'a mut W { + pub fn resume(self) -> &'a mut crate::W { self.variant(CMD_TYPE_A::RESUME) } #[doc = "`11`"] #[inline(always)] - pub fn abort(self) -> &'a mut W { + pub fn abort(self) -> &'a mut crate::W { self.variant(CMD_TYPE_A::ABORT) } } #[doc = "Field `CMD_INDEX` reader - Command index to be issued"] -pub type CMD_INDEX_R = crate::FieldReader; +pub type CMD_INDEX_R = crate::FieldReader; #[doc = "Field `CMD_INDEX` writer - Command index to be issued"] -pub type CMD_INDEX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMDTM_SPEC, u8, u8, 6, O>; +pub type CMD_INDEX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bit 1 - Enable block counter"] #[inline(always)] @@ -431,86 +423,126 @@ impl R { CMD_INDEX_R::new(((self.bits >> 24) & 0x3f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CMDTM") + .field("cmd_index", &format_args!("{}", self.cmd_index().bits())) + .field("cmd_type", &format_args!("{}", self.cmd_type().bits())) + .field("cmd_isdata", &format_args!("{}", self.cmd_isdata().bit())) + .field( + "cmd_ixchk_en", + &format_args!("{}", self.cmd_ixchk_en().bit()), + ) + .field( + "cmd_crcchk_en", + &format_args!("{}", self.cmd_crcchk_en().bit()), + ) + .field( + "cmd_rspns_type", + &format_args!("{}", self.cmd_rspns_type().bits()), + ) + .field( + "tm_multi_block", + &format_args!("{}", self.tm_multi_block().bit()), + ) + .field("tm_dat_dir", &format_args!("{}", self.tm_dat_dir().bit())) + .field( + "tm_auto_cmd_en", + &format_args!("{}", self.tm_auto_cmd_en().bits()), + ) + .field( + "tm_blkcnt_en", + &format_args!("{}", self.tm_blkcnt_en().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Enable block counter"] #[inline(always)] #[must_use] - pub fn tm_blkcnt_en(&mut self) -> TM_BLKCNT_EN_W<1> { + pub fn tm_blkcnt_en(&mut self) -> TM_BLKCNT_EN_W { TM_BLKCNT_EN_W::new(self) } #[doc = "Bits 2:3 - Command after completion"] #[inline(always)] #[must_use] - pub fn tm_auto_cmd_en(&mut self) -> TM_AUTO_CMD_EN_W<2> { + pub fn tm_auto_cmd_en(&mut self) -> TM_AUTO_CMD_EN_W { TM_AUTO_CMD_EN_W::new(self) } #[doc = "Bit 4 - Direction of data transfer"] #[inline(always)] #[must_use] - pub fn tm_dat_dir(&mut self) -> TM_DAT_DIR_W<4> { + pub fn tm_dat_dir(&mut self) -> TM_DAT_DIR_W { TM_DAT_DIR_W::new(self) } #[doc = "Bit 5 - Type of data transfer"] #[inline(always)] #[must_use] - pub fn tm_multi_block(&mut self) -> TM_MULTI_BLOCK_W<5> { + pub fn tm_multi_block(&mut self) -> TM_MULTI_BLOCK_W { TM_MULTI_BLOCK_W::new(self) } #[doc = "Bits 16:17 - Type of expected response"] #[inline(always)] #[must_use] - pub fn cmd_rspns_type(&mut self) -> CMD_RSPNS_TYPE_W<16> { + pub fn cmd_rspns_type(&mut self) -> CMD_RSPNS_TYPE_W { CMD_RSPNS_TYPE_W::new(self) } #[doc = "Bit 19 - Check the responses CRC"] #[inline(always)] #[must_use] - pub fn cmd_crcchk_en(&mut self) -> CMD_CRCCHK_EN_W<19> { + pub fn cmd_crcchk_en(&mut self) -> CMD_CRCCHK_EN_W { CMD_CRCCHK_EN_W::new(self) } #[doc = "Bit 20 - Check that the response has the same command index"] #[inline(always)] #[must_use] - pub fn cmd_ixchk_en(&mut self) -> CMD_IXCHK_EN_W<20> { + pub fn cmd_ixchk_en(&mut self) -> CMD_IXCHK_EN_W { CMD_IXCHK_EN_W::new(self) } #[doc = "Bit 21 - Command involves data"] #[inline(always)] #[must_use] - pub fn cmd_isdata(&mut self) -> CMD_ISDATA_W<21> { + pub fn cmd_isdata(&mut self) -> CMD_ISDATA_W { CMD_ISDATA_W::new(self) } #[doc = "Bits 22:23 - Type of command to be issued"] #[inline(always)] #[must_use] - pub fn cmd_type(&mut self) -> CMD_TYPE_W<22> { + pub fn cmd_type(&mut self) -> CMD_TYPE_W { CMD_TYPE_W::new(self) } #[doc = "Bits 24:29 - Command index to be issued"] #[inline(always)] #[must_use] - pub fn cmd_index(&mut self) -> CMD_INDEX_W<24> { + pub fn cmd_index(&mut self) -> CMD_INDEX_W { CMD_INDEX_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Issue commands to the card\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmdtm](index.html) module"] +#[doc = "Issue commands to the card\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdtm::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdtm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMDTM_SPEC; impl crate::RegisterSpec for CMDTM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cmdtm::R](R) reader structure"] -impl crate::Readable for CMDTM_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cmdtm::W](W) writer structure"] +#[doc = "`read()` method returns [`cmdtm::R`](R) reader structure"] +impl crate::Readable for CMDTM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmdtm::W`](W) writer structure"] impl crate::Writable for CMDTM_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/control0.rs b/crates/bcm2837-lpa/src/emmc/control0.rs index 948b94b..47fb08f 100644 --- a/crates/bcm2837-lpa/src/emmc/control0.rs +++ b/crates/bcm2837-lpa/src/emmc/control0.rs @@ -1,79 +1,47 @@ #[doc = "Register `CONTROL0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONTROL0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HCTL_DWIDTH` reader - Use 4 data lines"] -pub type HCTL_DWIDTH_R = crate::BitReader; +pub type HCTL_DWIDTH_R = crate::BitReader; #[doc = "Field `HCTL_DWIDTH` writer - Use 4 data lines"] -pub type HCTL_DWIDTH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type HCTL_DWIDTH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HCTL_HS_EN` reader - Enable high speed mode"] -pub type HCTL_HS_EN_R = crate::BitReader; +pub type HCTL_HS_EN_R = crate::BitReader; #[doc = "Field `HCTL_HS_EN` writer - Enable high speed mode"] -pub type HCTL_HS_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type HCTL_HS_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HCTL_8BIT` reader - Use 8 data lines"] -pub type HCTL_8BIT_R = crate::BitReader; +pub type HCTL_8BIT_R = crate::BitReader; #[doc = "Field `HCTL_8BIT` writer - Use 8 data lines"] -pub type HCTL_8BIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type HCTL_8BIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAP_STOP` reader - Stop the current transaction at the next block gap"] -pub type GAP_STOP_R = crate::BitReader; +pub type GAP_STOP_R = crate::BitReader; #[doc = "Field `GAP_STOP` writer - Stop the current transaction at the next block gap"] -pub type GAP_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type GAP_STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAP_RESTART` reader - Restart a transaction stopped by GAP_STOP"] -pub type GAP_RESTART_R = crate::BitReader; +pub type GAP_RESTART_R = crate::BitReader; #[doc = "Field `GAP_RESTART` writer - Restart a transaction stopped by GAP_STOP"] -pub type GAP_RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type GAP_RESTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READWAIT_EN` reader - Use DAT2 read/wait protocol"] -pub type READWAIT_EN_R = crate::BitReader; +pub type READWAIT_EN_R = crate::BitReader; #[doc = "Field `READWAIT_EN` writer - Use DAT2 read/wait protocol"] -pub type READWAIT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type READWAIT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAP_IEN` reader - Enable interrupt on block gap"] -pub type GAP_IEN_R = crate::BitReader; +pub type GAP_IEN_R = crate::BitReader; #[doc = "Field `GAP_IEN` writer - Enable interrupt on block gap"] -pub type GAP_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type GAP_IEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPI_MODE` reader - Enable SPI mode"] -pub type SPI_MODE_R = crate::BitReader; +pub type SPI_MODE_R = crate::BitReader; #[doc = "Field `SPI_MODE` writer - Enable SPI mode"] -pub type SPI_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type SPI_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOT_EN` reader - Boot mode enabled"] -pub type BOOT_EN_R = crate::BitReader; +pub type BOOT_EN_R = crate::BitReader; #[doc = "Field `BOOT_EN` writer - Boot mode enabled"] -pub type BOOT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type BOOT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ALT_BOOT_EN` reader - Enable alternate boot mode"] -pub type ALT_BOOT_EN_R = crate::BitReader; +pub type ALT_BOOT_EN_R = crate::BitReader; #[doc = "Field `ALT_BOOT_EN` writer - Enable alternate boot mode"] -pub type ALT_BOOT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL0_SPEC, bool, O>; +pub type ALT_BOOT_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - Use 4 data lines"] #[inline(always)] @@ -126,86 +94,108 @@ impl R { ALT_BOOT_EN_R::new(((self.bits >> 22) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONTROL0") + .field("alt_boot_en", &format_args!("{}", self.alt_boot_en().bit())) + .field("boot_en", &format_args!("{}", self.boot_en().bit())) + .field("spi_mode", &format_args!("{}", self.spi_mode().bit())) + .field("gap_ien", &format_args!("{}", self.gap_ien().bit())) + .field("readwait_en", &format_args!("{}", self.readwait_en().bit())) + .field("gap_restart", &format_args!("{}", self.gap_restart().bit())) + .field("gap_stop", &format_args!("{}", self.gap_stop().bit())) + .field("hctl_8bit", &format_args!("{}", self.hctl_8bit().bit())) + .field("hctl_hs_en", &format_args!("{}", self.hctl_hs_en().bit())) + .field("hctl_dwidth", &format_args!("{}", self.hctl_dwidth().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Use 4 data lines"] #[inline(always)] #[must_use] - pub fn hctl_dwidth(&mut self) -> HCTL_DWIDTH_W<1> { + pub fn hctl_dwidth(&mut self) -> HCTL_DWIDTH_W { HCTL_DWIDTH_W::new(self) } #[doc = "Bit 2 - Enable high speed mode"] #[inline(always)] #[must_use] - pub fn hctl_hs_en(&mut self) -> HCTL_HS_EN_W<2> { + pub fn hctl_hs_en(&mut self) -> HCTL_HS_EN_W { HCTL_HS_EN_W::new(self) } #[doc = "Bit 5 - Use 8 data lines"] #[inline(always)] #[must_use] - pub fn hctl_8bit(&mut self) -> HCTL_8BIT_W<5> { + pub fn hctl_8bit(&mut self) -> HCTL_8BIT_W { HCTL_8BIT_W::new(self) } #[doc = "Bit 16 - Stop the current transaction at the next block gap"] #[inline(always)] #[must_use] - pub fn gap_stop(&mut self) -> GAP_STOP_W<16> { + pub fn gap_stop(&mut self) -> GAP_STOP_W { GAP_STOP_W::new(self) } #[doc = "Bit 17 - Restart a transaction stopped by GAP_STOP"] #[inline(always)] #[must_use] - pub fn gap_restart(&mut self) -> GAP_RESTART_W<17> { + pub fn gap_restart(&mut self) -> GAP_RESTART_W { GAP_RESTART_W::new(self) } #[doc = "Bit 18 - Use DAT2 read/wait protocol"] #[inline(always)] #[must_use] - pub fn readwait_en(&mut self) -> READWAIT_EN_W<18> { + pub fn readwait_en(&mut self) -> READWAIT_EN_W { READWAIT_EN_W::new(self) } #[doc = "Bit 19 - Enable interrupt on block gap"] #[inline(always)] #[must_use] - pub fn gap_ien(&mut self) -> GAP_IEN_W<19> { + pub fn gap_ien(&mut self) -> GAP_IEN_W { GAP_IEN_W::new(self) } #[doc = "Bit 20 - Enable SPI mode"] #[inline(always)] #[must_use] - pub fn spi_mode(&mut self) -> SPI_MODE_W<20> { + pub fn spi_mode(&mut self) -> SPI_MODE_W { SPI_MODE_W::new(self) } #[doc = "Bit 21 - Boot mode enabled"] #[inline(always)] #[must_use] - pub fn boot_en(&mut self) -> BOOT_EN_W<21> { + pub fn boot_en(&mut self) -> BOOT_EN_W { BOOT_EN_W::new(self) } #[doc = "Bit 22 - Enable alternate boot mode"] #[inline(always)] #[must_use] - pub fn alt_boot_en(&mut self) -> ALT_BOOT_EN_W<22> { + pub fn alt_boot_en(&mut self) -> ALT_BOOT_EN_W { ALT_BOOT_EN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control0](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONTROL0_SPEC; impl crate::RegisterSpec for CONTROL0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [control0::R](R) reader structure"] -impl crate::Readable for CONTROL0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [control0::W](W) writer structure"] +#[doc = "`read()` method returns [`control0::R`](R) reader structure"] +impl crate::Readable for CONTROL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`control0::W`](W) writer structure"] impl crate::Writable for CONTROL0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/control1.rs b/crates/bcm2837-lpa/src/emmc/control1.rs index 1dc7cb3..40a8765 100644 --- a/crates/bcm2837-lpa/src/emmc/control1.rs +++ b/crates/bcm2837-lpa/src/emmc/control1.rs @@ -1,49 +1,17 @@ #[doc = "Register `CONTROL1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONTROL1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLK_INTLEN` reader - Enable internal clock"] -pub type CLK_INTLEN_R = crate::BitReader; +pub type CLK_INTLEN_R = crate::BitReader; #[doc = "Field `CLK_INTLEN` writer - Enable internal clock"] -pub type CLK_INTLEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type CLK_INTLEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLK_STABLE` reader - SD Clock stable"] -pub type CLK_STABLE_R = crate::BitReader; +pub type CLK_STABLE_R = crate::BitReader; #[doc = "Field `CLK_EN` reader - SD Clock enable"] -pub type CLK_EN_R = crate::BitReader; +pub type CLK_EN_R = crate::BitReader; #[doc = "Field `CLK_EN` writer - SD Clock enable"] -pub type CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type CLK_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLK_GENSEL` reader - Mode of clock generation"] pub type CLK_GENSEL_R = crate::BitReader; #[doc = "Mode of clock generation\n\nValue on reset: 0"] @@ -63,61 +31,64 @@ impl From for bool { impl CLK_GENSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> CLK_GENSEL_A { + pub const fn variant(&self) -> CLK_GENSEL_A { match self.bits { false => CLK_GENSEL_A::DIVIDED, true => CLK_GENSEL_A::PROGRAMMABLE, } } - #[doc = "Checks if the value of the field is `DIVIDED`"] + #[doc = "`0`"] #[inline(always)] pub fn is_divided(&self) -> bool { *self == CLK_GENSEL_A::DIVIDED } - #[doc = "Checks if the value of the field is `PROGRAMMABLE`"] + #[doc = "`1`"] #[inline(always)] pub fn is_programmable(&self) -> bool { *self == CLK_GENSEL_A::PROGRAMMABLE } } #[doc = "Field `CLK_GENSEL` writer - Mode of clock generation"] -pub type CLK_GENSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, CLK_GENSEL_A, O>; -impl<'a, const O: u8> CLK_GENSEL_W<'a, O> { +pub type CLK_GENSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CLK_GENSEL_A>; +impl<'a, REG, const O: u8> CLK_GENSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn divided(self) -> &'a mut W { + pub fn divided(self) -> &'a mut crate::W { self.variant(CLK_GENSEL_A::DIVIDED) } #[doc = "`1`"] #[inline(always)] - pub fn programmable(self) -> &'a mut W { + pub fn programmable(self) -> &'a mut crate::W { self.variant(CLK_GENSEL_A::PROGRAMMABLE) } } #[doc = "Field `CLK_FREQ_MS2` reader - Clock base divider MSBs"] -pub type CLK_FREQ_MS2_R = crate::FieldReader; +pub type CLK_FREQ_MS2_R = crate::FieldReader; #[doc = "Field `CLK_FREQ_MS2` writer - Clock base divider MSBs"] -pub type CLK_FREQ_MS2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 2, O>; +pub type CLK_FREQ_MS2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `CLK_FREQ8` reader - Clock base divider LSB"] -pub type CLK_FREQ8_R = crate::FieldReader; +pub type CLK_FREQ8_R = crate::FieldReader; #[doc = "Field `CLK_FREQ8` writer - Clock base divider LSB"] -pub type CLK_FREQ8_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 8, O>; +pub type CLK_FREQ8_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DATA_TOUNIT` reader - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] -pub type DATA_TOUNIT_R = crate::FieldReader; +pub type DATA_TOUNIT_R = crate::FieldReader; #[doc = "Field `DATA_TOUNIT` writer - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] -pub type DATA_TOUNIT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONTROL1_SPEC, u8, u8, 4, O>; +pub type DATA_TOUNIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `SRST_HC` reader - Reset the complete host circuit"] -pub type SRST_HC_R = crate::BitReader; +pub type SRST_HC_R = crate::BitReader; #[doc = "Field `SRST_HC` writer - Reset the complete host circuit"] -pub type SRST_HC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type SRST_HC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRST_CMD` reader - Reset the command handling circuit"] -pub type SRST_CMD_R = crate::BitReader; +pub type SRST_CMD_R = crate::BitReader; #[doc = "Field `SRST_CMD` writer - Reset the command handling circuit"] -pub type SRST_CMD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type SRST_CMD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRST_DATA` reader - Reset the data handling circuit"] -pub type SRST_DATA_R = crate::BitReader; +pub type SRST_DATA_R = crate::BitReader; #[doc = "Field `SRST_DATA` writer - Reset the data handling circuit"] -pub type SRST_DATA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL1_SPEC, bool, O>; +pub type SRST_DATA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable internal clock"] #[inline(always)] @@ -170,80 +141,108 @@ impl R { SRST_DATA_R::new(((self.bits >> 26) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONTROL1") + .field("srst_data", &format_args!("{}", self.srst_data().bit())) + .field("srst_cmd", &format_args!("{}", self.srst_cmd().bit())) + .field("srst_hc", &format_args!("{}", self.srst_hc().bit())) + .field( + "data_tounit", + &format_args!("{}", self.data_tounit().bits()), + ) + .field("clk_freq8", &format_args!("{}", self.clk_freq8().bits())) + .field( + "clk_freq_ms2", + &format_args!("{}", self.clk_freq_ms2().bits()), + ) + .field("clk_gensel", &format_args!("{}", self.clk_gensel().bit())) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .field("clk_stable", &format_args!("{}", self.clk_stable().bit())) + .field("clk_intlen", &format_args!("{}", self.clk_intlen().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable internal clock"] #[inline(always)] #[must_use] - pub fn clk_intlen(&mut self) -> CLK_INTLEN_W<0> { + pub fn clk_intlen(&mut self) -> CLK_INTLEN_W { CLK_INTLEN_W::new(self) } #[doc = "Bit 2 - SD Clock enable"] #[inline(always)] #[must_use] - pub fn clk_en(&mut self) -> CLK_EN_W<2> { + pub fn clk_en(&mut self) -> CLK_EN_W { CLK_EN_W::new(self) } #[doc = "Bit 5 - Mode of clock generation"] #[inline(always)] #[must_use] - pub fn clk_gensel(&mut self) -> CLK_GENSEL_W<5> { + pub fn clk_gensel(&mut self) -> CLK_GENSEL_W { CLK_GENSEL_W::new(self) } #[doc = "Bits 6:7 - Clock base divider MSBs"] #[inline(always)] #[must_use] - pub fn clk_freq_ms2(&mut self) -> CLK_FREQ_MS2_W<6> { + pub fn clk_freq_ms2(&mut self) -> CLK_FREQ_MS2_W { CLK_FREQ_MS2_W::new(self) } #[doc = "Bits 8:15 - Clock base divider LSB"] #[inline(always)] #[must_use] - pub fn clk_freq8(&mut self) -> CLK_FREQ8_W<8> { + pub fn clk_freq8(&mut self) -> CLK_FREQ8_W { CLK_FREQ8_W::new(self) } #[doc = "Bits 16:19 - Data timeout exponent (TMCLK * 2 ** (x + 13)) 1111 disabled"] #[inline(always)] #[must_use] - pub fn data_tounit(&mut self) -> DATA_TOUNIT_W<16> { + pub fn data_tounit(&mut self) -> DATA_TOUNIT_W { DATA_TOUNIT_W::new(self) } #[doc = "Bit 24 - Reset the complete host circuit"] #[inline(always)] #[must_use] - pub fn srst_hc(&mut self) -> SRST_HC_W<24> { + pub fn srst_hc(&mut self) -> SRST_HC_W { SRST_HC_W::new(self) } #[doc = "Bit 25 - Reset the command handling circuit"] #[inline(always)] #[must_use] - pub fn srst_cmd(&mut self) -> SRST_CMD_W<25> { + pub fn srst_cmd(&mut self) -> SRST_CMD_W { SRST_CMD_W::new(self) } #[doc = "Bit 26 - Reset the data handling circuit"] #[inline(always)] #[must_use] - pub fn srst_data(&mut self) -> SRST_DATA_W<26> { + pub fn srst_data(&mut self) -> SRST_DATA_W { SRST_DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Configure\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control1](index.html) module"] +#[doc = "Configure\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONTROL1_SPEC; impl crate::RegisterSpec for CONTROL1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [control1::R](R) reader structure"] -impl crate::Readable for CONTROL1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [control1::W](W) writer structure"] +#[doc = "`read()` method returns [`control1::R`](R) reader structure"] +impl crate::Readable for CONTROL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`control1::W`](W) writer structure"] impl crate::Writable for CONTROL1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/control2.rs b/crates/bcm2837-lpa/src/emmc/control2.rs index 1bc9076..bb052fc 100644 --- a/crates/bcm2837-lpa/src/emmc/control2.rs +++ b/crates/bcm2837-lpa/src/emmc/control2.rs @@ -1,53 +1,21 @@ #[doc = "Register `CONTROL2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONTROL2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ACNOX_ERR` reader - Auto command not executed due to an error"] -pub type ACNOX_ERR_R = crate::BitReader; +pub type ACNOX_ERR_R = crate::BitReader; #[doc = "Field `ACTO_ERR` reader - Auto command timeout"] -pub type ACTO_ERR_R = crate::BitReader; +pub type ACTO_ERR_R = crate::BitReader; #[doc = "Field `ACCRC_ERR` reader - Command CRC error during auto command"] -pub type ACCRC_ERR_R = crate::BitReader; +pub type ACCRC_ERR_R = crate::BitReader; #[doc = "Field `ACEND_ERR` reader - End bit is not 1 during auto command"] -pub type ACEND_ERR_R = crate::BitReader; +pub type ACEND_ERR_R = crate::BitReader; #[doc = "Field `ACBAD_ERR` reader - Command index error during auto command"] -pub type ACBAD_ERR_R = crate::BitReader; +pub type ACBAD_ERR_R = crate::BitReader; #[doc = "Field `NOTC12_ERR` reader - Error during auto CMD12"] -pub type NOTC12_ERR_R = crate::BitReader; +pub type NOTC12_ERR_R = crate::BitReader; #[doc = "Field `UHSMODE` reader - Select the speed of the SD card"] -pub type UHSMODE_R = crate::FieldReader; +pub type UHSMODE_R = crate::FieldReader; #[doc = "Select the speed of the SD card\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -69,10 +37,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for UHSMODE_A { + type Ux = u8; +} impl UHSMODE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(UHSMODE_A::SDR12), 1 => Some(UHSMODE_A::SDR25), @@ -82,70 +53,73 @@ impl UHSMODE_R { _ => None, } } - #[doc = "Checks if the value of the field is `SDR12`"] + #[doc = "`0`"] #[inline(always)] pub fn is_sdr12(&self) -> bool { *self == UHSMODE_A::SDR12 } - #[doc = "Checks if the value of the field is `SDR25`"] + #[doc = "`1`"] #[inline(always)] pub fn is_sdr25(&self) -> bool { *self == UHSMODE_A::SDR25 } - #[doc = "Checks if the value of the field is `SDR50`"] + #[doc = "`10`"] #[inline(always)] pub fn is_sdr50(&self) -> bool { *self == UHSMODE_A::SDR50 } - #[doc = "Checks if the value of the field is `SDR104`"] + #[doc = "`11`"] #[inline(always)] pub fn is_sdr104(&self) -> bool { *self == UHSMODE_A::SDR104 } - #[doc = "Checks if the value of the field is `DDR50`"] + #[doc = "`100`"] #[inline(always)] pub fn is_ddr50(&self) -> bool { *self == UHSMODE_A::DDR50 } } #[doc = "Field `UHSMODE` writer - Select the speed of the SD card"] -pub type UHSMODE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, CONTROL2_SPEC, u8, UHSMODE_A, 3, O>; -impl<'a, const O: u8> UHSMODE_W<'a, O> { +pub type UHSMODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, UHSMODE_A>; +impl<'a, REG, const O: u8> UHSMODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn sdr12(self) -> &'a mut W { + pub fn sdr12(self) -> &'a mut crate::W { self.variant(UHSMODE_A::SDR12) } #[doc = "`1`"] #[inline(always)] - pub fn sdr25(self) -> &'a mut W { + pub fn sdr25(self) -> &'a mut crate::W { self.variant(UHSMODE_A::SDR25) } #[doc = "`10`"] #[inline(always)] - pub fn sdr50(self) -> &'a mut W { + pub fn sdr50(self) -> &'a mut crate::W { self.variant(UHSMODE_A::SDR50) } #[doc = "`11`"] #[inline(always)] - pub fn sdr104(self) -> &'a mut W { + pub fn sdr104(self) -> &'a mut crate::W { self.variant(UHSMODE_A::SDR104) } #[doc = "`100`"] #[inline(always)] - pub fn ddr50(self) -> &'a mut W { + pub fn ddr50(self) -> &'a mut crate::W { self.variant(UHSMODE_A::DDR50) } } #[doc = "Field `TUNEON` reader - SD Clock tune in progress"] -pub type TUNEON_R = crate::BitReader; +pub type TUNEON_R = crate::BitReader; #[doc = "Field `TUNEON` writer - SD Clock tune in progress"] -pub type TUNEON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL2_SPEC, bool, O>; +pub type TUNEON_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TUNED` reader - Tuned clock is used for sampling data"] -pub type TUNED_R = crate::BitReader; +pub type TUNED_R = crate::BitReader; #[doc = "Field `TUNED` writer - Tuned clock is used for sampling data"] -pub type TUNED_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL2_SPEC, bool, O>; +pub type TUNED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Auto command not executed due to an error"] #[inline(always)] @@ -193,44 +167,65 @@ impl R { TUNED_R::new(((self.bits >> 23) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONTROL2") + .field("tuned", &format_args!("{}", self.tuned().bit())) + .field("tuneon", &format_args!("{}", self.tuneon().bit())) + .field("uhsmode", &format_args!("{}", self.uhsmode().bits())) + .field("notc12_err", &format_args!("{}", self.notc12_err().bit())) + .field("acbad_err", &format_args!("{}", self.acbad_err().bit())) + .field("acend_err", &format_args!("{}", self.acend_err().bit())) + .field("accrc_err", &format_args!("{}", self.accrc_err().bit())) + .field("acto_err", &format_args!("{}", self.acto_err().bit())) + .field("acnox_err", &format_args!("{}", self.acnox_err().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 16:18 - Select the speed of the SD card"] #[inline(always)] #[must_use] - pub fn uhsmode(&mut self) -> UHSMODE_W<16> { + pub fn uhsmode(&mut self) -> UHSMODE_W { UHSMODE_W::new(self) } #[doc = "Bit 22 - SD Clock tune in progress"] #[inline(always)] #[must_use] - pub fn tuneon(&mut self) -> TUNEON_W<22> { + pub fn tuneon(&mut self) -> TUNEON_W { TUNEON_W::new(self) } #[doc = "Bit 23 - Tuned clock is used for sampling data"] #[inline(always)] #[must_use] - pub fn tuned(&mut self) -> TUNED_W<23> { + pub fn tuned(&mut self) -> TUNED_W { TUNED_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control2](index.html) module"] +#[doc = "Control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONTROL2_SPEC; impl crate::RegisterSpec for CONTROL2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [control2::R](R) reader structure"] -impl crate::Readable for CONTROL2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [control2::W](W) writer structure"] +#[doc = "`read()` method returns [`control2::R`](R) reader structure"] +impl crate::Readable for CONTROL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`control2::W`](W) writer structure"] impl crate::Writable for CONTROL2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/data.rs b/crates/bcm2837-lpa/src/emmc/data.rs index 8c082b8..ac2280f 100644 --- a/crates/bcm2837-lpa/src/emmc/data.rs +++ b/crates/bcm2837-lpa/src/emmc/data.rs @@ -1,59 +1,38 @@ #[doc = "Register `DATA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DATA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data to/from the card\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +#[doc = "Data to/from the card\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DATA_SPEC; impl crate::RegisterSpec for DATA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [data::R](R) reader structure"] -impl crate::Readable for DATA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] impl crate::Writable for DATA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/dbg_sel.rs b/crates/bcm2837-lpa/src/emmc/dbg_sel.rs index c489a27..343a4db 100644 --- a/crates/bcm2837-lpa/src/emmc/dbg_sel.rs +++ b/crates/bcm2837-lpa/src/emmc/dbg_sel.rs @@ -1,39 +1,7 @@ #[doc = "Register `DBG_SEL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DBG_SEL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SELECT` reader - "] pub type SELECT_R = crate::BitReader; #[doc = "\n\nValue on reset: 0"] @@ -53,34 +21,37 @@ impl From for bool { impl SELECT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SELECT_A { + pub const fn variant(&self) -> SELECT_A { match self.bits { false => SELECT_A::RECEIVER_FIFO, true => SELECT_A::OTHERS, } } - #[doc = "Checks if the value of the field is `RECEIVER_FIFO`"] + #[doc = "`0`"] #[inline(always)] pub fn is_receiver_fifo(&self) -> bool { *self == SELECT_A::RECEIVER_FIFO } - #[doc = "Checks if the value of the field is `OTHERS`"] + #[doc = "`1`"] #[inline(always)] pub fn is_others(&self) -> bool { *self == SELECT_A::OTHERS } } #[doc = "Field `SELECT` writer - "] -pub type SELECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DBG_SEL_SPEC, SELECT_A, O>; -impl<'a, const O: u8> SELECT_W<'a, O> { +pub type SELECT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SELECT_A>; +impl<'a, REG, const O: u8> SELECT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn receiver_fifo(self) -> &'a mut W { + pub fn receiver_fifo(self) -> &'a mut crate::W { self.variant(SELECT_A::RECEIVER_FIFO) } #[doc = "`1`"] #[inline(always)] - pub fn others(self) -> &'a mut W { + pub fn others(self) -> &'a mut crate::W { self.variant(SELECT_A::OTHERS) } } @@ -91,32 +62,45 @@ impl R { SELECT_R::new((self.bits & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBG_SEL") + .field("select", &format_args!("{}", self.select().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn select(&mut self) -> SELECT_W<0> { + pub fn select(&mut self) -> SELECT_W { SELECT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "What submodules are accessed by the debug bus\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbg_sel](index.html) module"] +#[doc = "What submodules are accessed by the debug bus\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbg_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DBG_SEL_SPEC; impl crate::RegisterSpec for DBG_SEL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dbg_sel::R](R) reader structure"] -impl crate::Readable for DBG_SEL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dbg_sel::W](W) writer structure"] +#[doc = "`read()` method returns [`dbg_sel::R`](R) reader structure"] +impl crate::Readable for DBG_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbg_sel::W`](W) writer structure"] impl crate::Writable for DBG_SEL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/exrdfifo_cfg.rs b/crates/bcm2837-lpa/src/emmc/exrdfifo_cfg.rs index 1c7e3be..13440a1 100644 --- a/crates/bcm2837-lpa/src/emmc/exrdfifo_cfg.rs +++ b/crates/bcm2837-lpa/src/emmc/exrdfifo_cfg.rs @@ -1,43 +1,11 @@ #[doc = "Register `EXRDFIFO_CFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EXRDFIFO_CFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RD_THRSH` reader - Read threshold in 32 bit words"] -pub type RD_THRSH_R = crate::FieldReader; +pub type RD_THRSH_R = crate::FieldReader; #[doc = "Field `RD_THRSH` writer - Read threshold in 32 bit words"] -pub type RD_THRSH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EXRDFIFO_CFG_SPEC, u8, u8, 3, O>; +pub type RD_THRSH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:2 - Read threshold in 32 bit words"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { RD_THRSH_R::new((self.bits & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXRDFIFO_CFG") + .field("rd_thrsh", &format_args!("{}", self.rd_thrsh().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Read threshold in 32 bit words"] #[inline(always)] #[must_use] - pub fn rd_thrsh(&mut self) -> RD_THRSH_W<0> { + pub fn rd_thrsh(&mut self) -> RD_THRSH_W { RD_THRSH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Fine tune DMA request generation\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exrdfifo_cfg](index.html) module"] +#[doc = "Fine tune DMA request generation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exrdfifo_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrdfifo_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EXRDFIFO_CFG_SPEC; impl crate::RegisterSpec for EXRDFIFO_CFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [exrdfifo_cfg::R](R) reader structure"] -impl crate::Readable for EXRDFIFO_CFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [exrdfifo_cfg::W](W) writer structure"] +#[doc = "`read()` method returns [`exrdfifo_cfg::R`](R) reader structure"] +impl crate::Readable for EXRDFIFO_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`exrdfifo_cfg::W`](W) writer structure"] impl crate::Writable for EXRDFIFO_CFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/exrdfifo_en.rs b/crates/bcm2837-lpa/src/emmc/exrdfifo_en.rs index 26c7adc..e6b6583 100644 --- a/crates/bcm2837-lpa/src/emmc/exrdfifo_en.rs +++ b/crates/bcm2837-lpa/src/emmc/exrdfifo_en.rs @@ -1,43 +1,11 @@ #[doc = "Register `EXRDFIFO_EN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EXRDFIFO_EN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ENABLE` reader - Enable the extension FIFO"] -pub type ENABLE_R = crate::BitReader; +pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Enable the extension FIFO"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXRDFIFO_EN_SPEC, bool, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable the extension FIFO"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { ENABLE_R::new((self.bits & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXRDFIFO_EN") + .field("enable", &format_args!("{}", self.enable().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable the extension FIFO"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<0> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable the extension data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exrdfifo_en](index.html) module"] +#[doc = "Enable the extension data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exrdfifo_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrdfifo_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EXRDFIFO_EN_SPEC; impl crate::RegisterSpec for EXRDFIFO_EN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [exrdfifo_en::R](R) reader structure"] -impl crate::Readable for EXRDFIFO_EN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [exrdfifo_en::W](W) writer structure"] +#[doc = "`read()` method returns [`exrdfifo_en::R`](R) reader structure"] +impl crate::Readable for EXRDFIFO_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`exrdfifo_en::W`](W) writer structure"] impl crate::Writable for EXRDFIFO_EN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/force_irpt.rs b/crates/bcm2837-lpa/src/emmc/force_irpt.rs index eca9ec6..682b8fe 100644 --- a/crates/bcm2837-lpa/src/emmc/force_irpt.rs +++ b/crates/bcm2837-lpa/src/emmc/force_irpt.rs @@ -1,107 +1,75 @@ #[doc = "Register `FORCE_IRPT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FORCE_IRPT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_DONE` reader - Command has finished"] -pub type CMD_DONE_R = crate::BitReader; +pub type CMD_DONE_R = crate::BitReader; #[doc = "Field `CMD_DONE` writer - Command has finished"] -pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CMD_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_DONE` reader - Data transfer has finished"] -pub type DATA_DONE_R = crate::BitReader; +pub type DATA_DONE_R = crate::BitReader; #[doc = "Field `DATA_DONE` writer - Data transfer has finished"] -pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type DATA_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_R = crate::BitReader; +pub type BLOCK_GAP_R = crate::BitReader; #[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type BLOCK_GAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_RDY` reader - DATA can be written to"] -pub type WRITE_RDY_R = crate::BitReader; +pub type WRITE_RDY_R = crate::BitReader; #[doc = "Field `WRITE_RDY` writer - DATA can be written to"] -pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type WRITE_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_RDY` reader - DATA contains data to be read"] -pub type READ_RDY_R = crate::BitReader; +pub type READ_RDY_R = crate::BitReader; #[doc = "Field `READ_RDY` writer - DATA contains data to be read"] -pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type READ_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CARD` reader - Card made interrupt request"] -pub type CARD_R = crate::BitReader; +pub type CARD_R = crate::BitReader; #[doc = "Field `CARD` writer - Card made interrupt request"] -pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CARD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RETUNE` reader - Clock retune request"] -pub type RETUNE_R = crate::BitReader; +pub type RETUNE_R = crate::BitReader; #[doc = "Field `RETUNE` writer - Clock retune request"] -pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type RETUNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] -pub type BOOTACK_R = crate::BitReader; +pub type BOOTACK_R = crate::BitReader; #[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] -pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type BOOTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] -pub type ENDBOOT_R = crate::BitReader; +pub type ENDBOOT_R = crate::BitReader; #[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] -pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type ENDBOOT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTO_ERR` reader - Command timeout"] -pub type CTO_ERR_R = crate::BitReader; +pub type CTO_ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` writer - Command timeout"] -pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CCRC_ERR` reader - Command CRC error"] -pub type CCRC_ERR_R = crate::BitReader; +pub type CCRC_ERR_R = crate::BitReader; #[doc = "Field `CCRC_ERR` writer - Command CRC error"] -pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] -pub type CEND_ERR_R = crate::BitReader; +pub type CEND_ERR_R = crate::BitReader; #[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] -pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] -pub type CBAD_ERR_R = crate::BitReader; +pub type CBAD_ERR_R = crate::BitReader; #[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] -pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type CBAD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTO_ERR` reader - Data timeout"] -pub type DTO_ERR_R = crate::BitReader; +pub type DTO_ERR_R = crate::BitReader; #[doc = "Field `DTO_ERR` writer - Data timeout"] -pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type DTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRC_ERR` reader - Data CRC error"] -pub type DCRC_ERR_R = crate::BitReader; +pub type DCRC_ERR_R = crate::BitReader; #[doc = "Field `DCRC_ERR` writer - Data CRC error"] -pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type DCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] -pub type DEND_ERR_R = crate::BitReader; +pub type DEND_ERR_R = crate::BitReader; #[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] -pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type DEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMD_ERR` reader - Auto command error"] -pub type ACMD_ERR_R = crate::BitReader; +pub type ACMD_ERR_R = crate::BitReader; #[doc = "Field `ACMD_ERR` writer - Auto command error"] -pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORCE_IRPT_SPEC, bool, O>; +pub type ACMD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Command has finished"] #[inline(always)] @@ -189,128 +157,157 @@ impl R { ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FORCE_IRPT") + .field("acmd_err", &format_args!("{}", self.acmd_err().bit())) + .field("dend_err", &format_args!("{}", self.dend_err().bit())) + .field("dcrc_err", &format_args!("{}", self.dcrc_err().bit())) + .field("dto_err", &format_args!("{}", self.dto_err().bit())) + .field("cbad_err", &format_args!("{}", self.cbad_err().bit())) + .field("cend_err", &format_args!("{}", self.cend_err().bit())) + .field("ccrc_err", &format_args!("{}", self.ccrc_err().bit())) + .field("cto_err", &format_args!("{}", self.cto_err().bit())) + .field("endboot", &format_args!("{}", self.endboot().bit())) + .field("bootack", &format_args!("{}", self.bootack().bit())) + .field("retune", &format_args!("{}", self.retune().bit())) + .field("card", &format_args!("{}", self.card().bit())) + .field("read_rdy", &format_args!("{}", self.read_rdy().bit())) + .field("write_rdy", &format_args!("{}", self.write_rdy().bit())) + .field("block_gap", &format_args!("{}", self.block_gap().bit())) + .field("data_done", &format_args!("{}", self.data_done().bit())) + .field("cmd_done", &format_args!("{}", self.cmd_done().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command has finished"] #[inline(always)] #[must_use] - pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + pub fn cmd_done(&mut self) -> CMD_DONE_W { CMD_DONE_W::new(self) } #[doc = "Bit 1 - Data transfer has finished"] #[inline(always)] #[must_use] - pub fn data_done(&mut self) -> DATA_DONE_W<1> { + pub fn data_done(&mut self) -> DATA_DONE_W { DATA_DONE_W::new(self) } #[doc = "Bit 2 - Data transfer has stopped at block gap"] #[inline(always)] #[must_use] - pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + pub fn block_gap(&mut self) -> BLOCK_GAP_W { BLOCK_GAP_W::new(self) } #[doc = "Bit 4 - DATA can be written to"] #[inline(always)] #[must_use] - pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + pub fn write_rdy(&mut self) -> WRITE_RDY_W { WRITE_RDY_W::new(self) } #[doc = "Bit 5 - DATA contains data to be read"] #[inline(always)] #[must_use] - pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + pub fn read_rdy(&mut self) -> READ_RDY_W { READ_RDY_W::new(self) } #[doc = "Bit 8 - Card made interrupt request"] #[inline(always)] #[must_use] - pub fn card(&mut self) -> CARD_W<8> { + pub fn card(&mut self) -> CARD_W { CARD_W::new(self) } #[doc = "Bit 12 - Clock retune request"] #[inline(always)] #[must_use] - pub fn retune(&mut self) -> RETUNE_W<12> { + pub fn retune(&mut self) -> RETUNE_W { RETUNE_W::new(self) } #[doc = "Bit 13 - Boot has been acknowledged"] #[inline(always)] #[must_use] - pub fn bootack(&mut self) -> BOOTACK_W<13> { + pub fn bootack(&mut self) -> BOOTACK_W { BOOTACK_W::new(self) } #[doc = "Bit 14 - Boot operation has terminated"] #[inline(always)] #[must_use] - pub fn endboot(&mut self) -> ENDBOOT_W<14> { + pub fn endboot(&mut self) -> ENDBOOT_W { ENDBOOT_W::new(self) } #[doc = "Bit 16 - Command timeout"] #[inline(always)] #[must_use] - pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + pub fn cto_err(&mut self) -> CTO_ERR_W { CTO_ERR_W::new(self) } #[doc = "Bit 17 - Command CRC error"] #[inline(always)] #[must_use] - pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + pub fn ccrc_err(&mut self) -> CCRC_ERR_W { CCRC_ERR_W::new(self) } #[doc = "Bit 18 - Command end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + pub fn cend_err(&mut self) -> CEND_ERR_W { CEND_ERR_W::new(self) } #[doc = "Bit 19 - Incorrect response command index"] #[inline(always)] #[must_use] - pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + pub fn cbad_err(&mut self) -> CBAD_ERR_W { CBAD_ERR_W::new(self) } #[doc = "Bit 20 - Data timeout"] #[inline(always)] #[must_use] - pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + pub fn dto_err(&mut self) -> DTO_ERR_W { DTO_ERR_W::new(self) } #[doc = "Bit 21 - Data CRC error"] #[inline(always)] #[must_use] - pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + pub fn dcrc_err(&mut self) -> DCRC_ERR_W { DCRC_ERR_W::new(self) } #[doc = "Bit 22 - Data end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + pub fn dend_err(&mut self) -> DEND_ERR_W { DEND_ERR_W::new(self) } #[doc = "Bit 24 - Auto command error"] #[inline(always)] #[must_use] - pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + pub fn acmd_err(&mut self) -> ACMD_ERR_W { ACMD_ERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Force an interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [force_irpt](index.html) module"] +#[doc = "Force an interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`force_irpt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`force_irpt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FORCE_IRPT_SPEC; impl crate::RegisterSpec for FORCE_IRPT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [force_irpt::R](R) reader structure"] -impl crate::Readable for FORCE_IRPT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [force_irpt::W](W) writer structure"] +#[doc = "`read()` method returns [`force_irpt::R`](R) reader structure"] +impl crate::Readable for FORCE_IRPT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`force_irpt::W`](W) writer structure"] impl crate::Writable for FORCE_IRPT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/interrupt.rs b/crates/bcm2837-lpa/src/emmc/interrupt.rs index c687814..c28598f 100644 --- a/crates/bcm2837-lpa/src/emmc/interrupt.rs +++ b/crates/bcm2837-lpa/src/emmc/interrupt.rs @@ -1,109 +1,77 @@ #[doc = "Register `INTERRUPT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `INTERRUPT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_DONE` reader - Command has finished"] -pub type CMD_DONE_R = crate::BitReader; +pub type CMD_DONE_R = crate::BitReader; #[doc = "Field `CMD_DONE` writer - Command has finished"] -pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CMD_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_DONE` reader - Data transfer has finished"] -pub type DATA_DONE_R = crate::BitReader; +pub type DATA_DONE_R = crate::BitReader; #[doc = "Field `DATA_DONE` writer - Data transfer has finished"] -pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type DATA_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_R = crate::BitReader; +pub type BLOCK_GAP_R = crate::BitReader; #[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type BLOCK_GAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_RDY` reader - DATA can be written to"] -pub type WRITE_RDY_R = crate::BitReader; +pub type WRITE_RDY_R = crate::BitReader; #[doc = "Field `WRITE_RDY` writer - DATA can be written to"] -pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type WRITE_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_RDY` reader - DATA contains data to be read"] -pub type READ_RDY_R = crate::BitReader; +pub type READ_RDY_R = crate::BitReader; #[doc = "Field `READ_RDY` writer - DATA contains data to be read"] -pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type READ_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CARD` reader - Card made interrupt request"] -pub type CARD_R = crate::BitReader; +pub type CARD_R = crate::BitReader; #[doc = "Field `CARD` writer - Card made interrupt request"] -pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CARD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RETUNE` reader - Clock retune request"] -pub type RETUNE_R = crate::BitReader; +pub type RETUNE_R = crate::BitReader; #[doc = "Field `RETUNE` writer - Clock retune request"] -pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type RETUNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] -pub type BOOTACK_R = crate::BitReader; +pub type BOOTACK_R = crate::BitReader; #[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] -pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type BOOTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] -pub type ENDBOOT_R = crate::BitReader; +pub type ENDBOOT_R = crate::BitReader; #[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] -pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type ENDBOOT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERR` reader - An error has occured"] -pub type ERR_R = crate::BitReader; +pub type ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` reader - Command timeout"] -pub type CTO_ERR_R = crate::BitReader; +pub type CTO_ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` writer - Command timeout"] -pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CCRC_ERR` reader - Command CRC error"] -pub type CCRC_ERR_R = crate::BitReader; +pub type CCRC_ERR_R = crate::BitReader; #[doc = "Field `CCRC_ERR` writer - Command CRC error"] -pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] -pub type CEND_ERR_R = crate::BitReader; +pub type CEND_ERR_R = crate::BitReader; #[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] -pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] -pub type CBAD_ERR_R = crate::BitReader; +pub type CBAD_ERR_R = crate::BitReader; #[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] -pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type CBAD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTO_ERR` reader - Data timeout"] -pub type DTO_ERR_R = crate::BitReader; +pub type DTO_ERR_R = crate::BitReader; #[doc = "Field `DTO_ERR` writer - Data timeout"] -pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type DTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRC_ERR` reader - Data CRC error"] -pub type DCRC_ERR_R = crate::BitReader; +pub type DCRC_ERR_R = crate::BitReader; #[doc = "Field `DCRC_ERR` writer - Data CRC error"] -pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type DCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] -pub type DEND_ERR_R = crate::BitReader; +pub type DEND_ERR_R = crate::BitReader; #[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] -pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type DEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMD_ERR` reader - Auto command error"] -pub type ACMD_ERR_R = crate::BitReader; +pub type ACMD_ERR_R = crate::BitReader; #[doc = "Field `ACMD_ERR` writer - Auto command error"] -pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTERRUPT_SPEC, bool, O>; +pub type ACMD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Command has finished"] #[inline(always)] @@ -196,128 +164,158 @@ impl R { ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTERRUPT") + .field("acmd_err", &format_args!("{}", self.acmd_err().bit())) + .field("dend_err", &format_args!("{}", self.dend_err().bit())) + .field("dcrc_err", &format_args!("{}", self.dcrc_err().bit())) + .field("dto_err", &format_args!("{}", self.dto_err().bit())) + .field("cbad_err", &format_args!("{}", self.cbad_err().bit())) + .field("cend_err", &format_args!("{}", self.cend_err().bit())) + .field("ccrc_err", &format_args!("{}", self.ccrc_err().bit())) + .field("cto_err", &format_args!("{}", self.cto_err().bit())) + .field("err", &format_args!("{}", self.err().bit())) + .field("endboot", &format_args!("{}", self.endboot().bit())) + .field("bootack", &format_args!("{}", self.bootack().bit())) + .field("retune", &format_args!("{}", self.retune().bit())) + .field("card", &format_args!("{}", self.card().bit())) + .field("read_rdy", &format_args!("{}", self.read_rdy().bit())) + .field("write_rdy", &format_args!("{}", self.write_rdy().bit())) + .field("block_gap", &format_args!("{}", self.block_gap().bit())) + .field("data_done", &format_args!("{}", self.data_done().bit())) + .field("cmd_done", &format_args!("{}", self.cmd_done().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command has finished"] #[inline(always)] #[must_use] - pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + pub fn cmd_done(&mut self) -> CMD_DONE_W { CMD_DONE_W::new(self) } #[doc = "Bit 1 - Data transfer has finished"] #[inline(always)] #[must_use] - pub fn data_done(&mut self) -> DATA_DONE_W<1> { + pub fn data_done(&mut self) -> DATA_DONE_W { DATA_DONE_W::new(self) } #[doc = "Bit 2 - Data transfer has stopped at block gap"] #[inline(always)] #[must_use] - pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + pub fn block_gap(&mut self) -> BLOCK_GAP_W { BLOCK_GAP_W::new(self) } #[doc = "Bit 4 - DATA can be written to"] #[inline(always)] #[must_use] - pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + pub fn write_rdy(&mut self) -> WRITE_RDY_W { WRITE_RDY_W::new(self) } #[doc = "Bit 5 - DATA contains data to be read"] #[inline(always)] #[must_use] - pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + pub fn read_rdy(&mut self) -> READ_RDY_W { READ_RDY_W::new(self) } #[doc = "Bit 8 - Card made interrupt request"] #[inline(always)] #[must_use] - pub fn card(&mut self) -> CARD_W<8> { + pub fn card(&mut self) -> CARD_W { CARD_W::new(self) } #[doc = "Bit 12 - Clock retune request"] #[inline(always)] #[must_use] - pub fn retune(&mut self) -> RETUNE_W<12> { + pub fn retune(&mut self) -> RETUNE_W { RETUNE_W::new(self) } #[doc = "Bit 13 - Boot has been acknowledged"] #[inline(always)] #[must_use] - pub fn bootack(&mut self) -> BOOTACK_W<13> { + pub fn bootack(&mut self) -> BOOTACK_W { BOOTACK_W::new(self) } #[doc = "Bit 14 - Boot operation has terminated"] #[inline(always)] #[must_use] - pub fn endboot(&mut self) -> ENDBOOT_W<14> { + pub fn endboot(&mut self) -> ENDBOOT_W { ENDBOOT_W::new(self) } #[doc = "Bit 16 - Command timeout"] #[inline(always)] #[must_use] - pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + pub fn cto_err(&mut self) -> CTO_ERR_W { CTO_ERR_W::new(self) } #[doc = "Bit 17 - Command CRC error"] #[inline(always)] #[must_use] - pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + pub fn ccrc_err(&mut self) -> CCRC_ERR_W { CCRC_ERR_W::new(self) } #[doc = "Bit 18 - Command end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + pub fn cend_err(&mut self) -> CEND_ERR_W { CEND_ERR_W::new(self) } #[doc = "Bit 19 - Incorrect response command index"] #[inline(always)] #[must_use] - pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + pub fn cbad_err(&mut self) -> CBAD_ERR_W { CBAD_ERR_W::new(self) } #[doc = "Bit 20 - Data timeout"] #[inline(always)] #[must_use] - pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + pub fn dto_err(&mut self) -> DTO_ERR_W { DTO_ERR_W::new(self) } #[doc = "Bit 21 - Data CRC error"] #[inline(always)] #[must_use] - pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + pub fn dcrc_err(&mut self) -> DCRC_ERR_W { DCRC_ERR_W::new(self) } #[doc = "Bit 22 - Data end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + pub fn dend_err(&mut self) -> DEND_ERR_W { DEND_ERR_W::new(self) } #[doc = "Bit 24 - Auto command error"] #[inline(always)] #[must_use] - pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + pub fn acmd_err(&mut self) -> ACMD_ERR_W { ACMD_ERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt flags\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt](index.html) module"] +#[doc = "Interrupt flags\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERRUPT_SPEC; impl crate::RegisterSpec for INTERRUPT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [interrupt::R](R) reader structure"] -impl crate::Readable for INTERRUPT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [interrupt::W](W) writer structure"] +#[doc = "`read()` method returns [`interrupt::R`](R) reader structure"] +impl crate::Readable for INTERRUPT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interrupt::W`](W) writer structure"] impl crate::Writable for INTERRUPT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/irpt_en.rs b/crates/bcm2837-lpa/src/emmc/irpt_en.rs index 0e71317..af7bc80 100644 --- a/crates/bcm2837-lpa/src/emmc/irpt_en.rs +++ b/crates/bcm2837-lpa/src/emmc/irpt_en.rs @@ -1,107 +1,75 @@ #[doc = "Register `IRPT_EN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRPT_EN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_DONE` reader - Command has finished"] -pub type CMD_DONE_R = crate::BitReader; +pub type CMD_DONE_R = crate::BitReader; #[doc = "Field `CMD_DONE` writer - Command has finished"] -pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CMD_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_DONE` reader - Data transfer has finished"] -pub type DATA_DONE_R = crate::BitReader; +pub type DATA_DONE_R = crate::BitReader; #[doc = "Field `DATA_DONE` writer - Data transfer has finished"] -pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type DATA_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_R = crate::BitReader; +pub type BLOCK_GAP_R = crate::BitReader; #[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type BLOCK_GAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_RDY` reader - DATA can be written to"] -pub type WRITE_RDY_R = crate::BitReader; +pub type WRITE_RDY_R = crate::BitReader; #[doc = "Field `WRITE_RDY` writer - DATA can be written to"] -pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type WRITE_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_RDY` reader - DATA contains data to be read"] -pub type READ_RDY_R = crate::BitReader; +pub type READ_RDY_R = crate::BitReader; #[doc = "Field `READ_RDY` writer - DATA contains data to be read"] -pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type READ_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CARD` reader - Card made interrupt request"] -pub type CARD_R = crate::BitReader; +pub type CARD_R = crate::BitReader; #[doc = "Field `CARD` writer - Card made interrupt request"] -pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CARD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RETUNE` reader - Clock retune request"] -pub type RETUNE_R = crate::BitReader; +pub type RETUNE_R = crate::BitReader; #[doc = "Field `RETUNE` writer - Clock retune request"] -pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type RETUNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] -pub type BOOTACK_R = crate::BitReader; +pub type BOOTACK_R = crate::BitReader; #[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] -pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type BOOTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] -pub type ENDBOOT_R = crate::BitReader; +pub type ENDBOOT_R = crate::BitReader; #[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] -pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type ENDBOOT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTO_ERR` reader - Command timeout"] -pub type CTO_ERR_R = crate::BitReader; +pub type CTO_ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` writer - Command timeout"] -pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CCRC_ERR` reader - Command CRC error"] -pub type CCRC_ERR_R = crate::BitReader; +pub type CCRC_ERR_R = crate::BitReader; #[doc = "Field `CCRC_ERR` writer - Command CRC error"] -pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] -pub type CEND_ERR_R = crate::BitReader; +pub type CEND_ERR_R = crate::BitReader; #[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] -pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] -pub type CBAD_ERR_R = crate::BitReader; +pub type CBAD_ERR_R = crate::BitReader; #[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] -pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type CBAD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTO_ERR` reader - Data timeout"] -pub type DTO_ERR_R = crate::BitReader; +pub type DTO_ERR_R = crate::BitReader; #[doc = "Field `DTO_ERR` writer - Data timeout"] -pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type DTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRC_ERR` reader - Data CRC error"] -pub type DCRC_ERR_R = crate::BitReader; +pub type DCRC_ERR_R = crate::BitReader; #[doc = "Field `DCRC_ERR` writer - Data CRC error"] -pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type DCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] -pub type DEND_ERR_R = crate::BitReader; +pub type DEND_ERR_R = crate::BitReader; #[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] -pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type DEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMD_ERR` reader - Auto command error"] -pub type ACMD_ERR_R = crate::BitReader; +pub type ACMD_ERR_R = crate::BitReader; #[doc = "Field `ACMD_ERR` writer - Auto command error"] -pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_EN_SPEC, bool, O>; +pub type ACMD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Command has finished"] #[inline(always)] @@ -189,128 +157,157 @@ impl R { ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IRPT_EN") + .field("acmd_err", &format_args!("{}", self.acmd_err().bit())) + .field("dend_err", &format_args!("{}", self.dend_err().bit())) + .field("dcrc_err", &format_args!("{}", self.dcrc_err().bit())) + .field("dto_err", &format_args!("{}", self.dto_err().bit())) + .field("cbad_err", &format_args!("{}", self.cbad_err().bit())) + .field("cend_err", &format_args!("{}", self.cend_err().bit())) + .field("ccrc_err", &format_args!("{}", self.ccrc_err().bit())) + .field("cto_err", &format_args!("{}", self.cto_err().bit())) + .field("endboot", &format_args!("{}", self.endboot().bit())) + .field("bootack", &format_args!("{}", self.bootack().bit())) + .field("retune", &format_args!("{}", self.retune().bit())) + .field("card", &format_args!("{}", self.card().bit())) + .field("read_rdy", &format_args!("{}", self.read_rdy().bit())) + .field("write_rdy", &format_args!("{}", self.write_rdy().bit())) + .field("block_gap", &format_args!("{}", self.block_gap().bit())) + .field("data_done", &format_args!("{}", self.data_done().bit())) + .field("cmd_done", &format_args!("{}", self.cmd_done().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command has finished"] #[inline(always)] #[must_use] - pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + pub fn cmd_done(&mut self) -> CMD_DONE_W { CMD_DONE_W::new(self) } #[doc = "Bit 1 - Data transfer has finished"] #[inline(always)] #[must_use] - pub fn data_done(&mut self) -> DATA_DONE_W<1> { + pub fn data_done(&mut self) -> DATA_DONE_W { DATA_DONE_W::new(self) } #[doc = "Bit 2 - Data transfer has stopped at block gap"] #[inline(always)] #[must_use] - pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + pub fn block_gap(&mut self) -> BLOCK_GAP_W { BLOCK_GAP_W::new(self) } #[doc = "Bit 4 - DATA can be written to"] #[inline(always)] #[must_use] - pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + pub fn write_rdy(&mut self) -> WRITE_RDY_W { WRITE_RDY_W::new(self) } #[doc = "Bit 5 - DATA contains data to be read"] #[inline(always)] #[must_use] - pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + pub fn read_rdy(&mut self) -> READ_RDY_W { READ_RDY_W::new(self) } #[doc = "Bit 8 - Card made interrupt request"] #[inline(always)] #[must_use] - pub fn card(&mut self) -> CARD_W<8> { + pub fn card(&mut self) -> CARD_W { CARD_W::new(self) } #[doc = "Bit 12 - Clock retune request"] #[inline(always)] #[must_use] - pub fn retune(&mut self) -> RETUNE_W<12> { + pub fn retune(&mut self) -> RETUNE_W { RETUNE_W::new(self) } #[doc = "Bit 13 - Boot has been acknowledged"] #[inline(always)] #[must_use] - pub fn bootack(&mut self) -> BOOTACK_W<13> { + pub fn bootack(&mut self) -> BOOTACK_W { BOOTACK_W::new(self) } #[doc = "Bit 14 - Boot operation has terminated"] #[inline(always)] #[must_use] - pub fn endboot(&mut self) -> ENDBOOT_W<14> { + pub fn endboot(&mut self) -> ENDBOOT_W { ENDBOOT_W::new(self) } #[doc = "Bit 16 - Command timeout"] #[inline(always)] #[must_use] - pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + pub fn cto_err(&mut self) -> CTO_ERR_W { CTO_ERR_W::new(self) } #[doc = "Bit 17 - Command CRC error"] #[inline(always)] #[must_use] - pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + pub fn ccrc_err(&mut self) -> CCRC_ERR_W { CCRC_ERR_W::new(self) } #[doc = "Bit 18 - Command end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + pub fn cend_err(&mut self) -> CEND_ERR_W { CEND_ERR_W::new(self) } #[doc = "Bit 19 - Incorrect response command index"] #[inline(always)] #[must_use] - pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + pub fn cbad_err(&mut self) -> CBAD_ERR_W { CBAD_ERR_W::new(self) } #[doc = "Bit 20 - Data timeout"] #[inline(always)] #[must_use] - pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + pub fn dto_err(&mut self) -> DTO_ERR_W { DTO_ERR_W::new(self) } #[doc = "Bit 21 - Data CRC error"] #[inline(always)] #[must_use] - pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + pub fn dcrc_err(&mut self) -> DCRC_ERR_W { DCRC_ERR_W::new(self) } #[doc = "Bit 22 - Data end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + pub fn dend_err(&mut self) -> DEND_ERR_W { DEND_ERR_W::new(self) } #[doc = "Bit 24 - Auto command error"] #[inline(always)] #[must_use] - pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + pub fn acmd_err(&mut self) -> ACMD_ERR_W { ACMD_ERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable interrupt to core\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irpt_en](index.html) module"] +#[doc = "Enable interrupt to core\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irpt_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irpt_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRPT_EN_SPEC; impl crate::RegisterSpec for IRPT_EN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irpt_en::R](R) reader structure"] -impl crate::Readable for IRPT_EN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irpt_en::W](W) writer structure"] +#[doc = "`read()` method returns [`irpt_en::R`](R) reader structure"] +impl crate::Readable for IRPT_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irpt_en::W`](W) writer structure"] impl crate::Writable for IRPT_EN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/irpt_mask.rs b/crates/bcm2837-lpa/src/emmc/irpt_mask.rs index 87a9fdd..e8dc746 100644 --- a/crates/bcm2837-lpa/src/emmc/irpt_mask.rs +++ b/crates/bcm2837-lpa/src/emmc/irpt_mask.rs @@ -1,107 +1,75 @@ #[doc = "Register `IRPT_MASK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IRPT_MASK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_DONE` reader - Command has finished"] -pub type CMD_DONE_R = crate::BitReader; +pub type CMD_DONE_R = crate::BitReader; #[doc = "Field `CMD_DONE` writer - Command has finished"] -pub type CMD_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CMD_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_DONE` reader - Data transfer has finished"] -pub type DATA_DONE_R = crate::BitReader; +pub type DATA_DONE_R = crate::BitReader; #[doc = "Field `DATA_DONE` writer - Data transfer has finished"] -pub type DATA_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type DATA_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLOCK_GAP` reader - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_R = crate::BitReader; +pub type BLOCK_GAP_R = crate::BitReader; #[doc = "Field `BLOCK_GAP` writer - Data transfer has stopped at block gap"] -pub type BLOCK_GAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type BLOCK_GAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_RDY` reader - DATA can be written to"] -pub type WRITE_RDY_R = crate::BitReader; +pub type WRITE_RDY_R = crate::BitReader; #[doc = "Field `WRITE_RDY` writer - DATA can be written to"] -pub type WRITE_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type WRITE_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_RDY` reader - DATA contains data to be read"] -pub type READ_RDY_R = crate::BitReader; +pub type READ_RDY_R = crate::BitReader; #[doc = "Field `READ_RDY` writer - DATA contains data to be read"] -pub type READ_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type READ_RDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CARD` reader - Card made interrupt request"] -pub type CARD_R = crate::BitReader; +pub type CARD_R = crate::BitReader; #[doc = "Field `CARD` writer - Card made interrupt request"] -pub type CARD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CARD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RETUNE` reader - Clock retune request"] -pub type RETUNE_R = crate::BitReader; +pub type RETUNE_R = crate::BitReader; #[doc = "Field `RETUNE` writer - Clock retune request"] -pub type RETUNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type RETUNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOOTACK` reader - Boot has been acknowledged"] -pub type BOOTACK_R = crate::BitReader; +pub type BOOTACK_R = crate::BitReader; #[doc = "Field `BOOTACK` writer - Boot has been acknowledged"] -pub type BOOTACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type BOOTACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDBOOT` reader - Boot operation has terminated"] -pub type ENDBOOT_R = crate::BitReader; +pub type ENDBOOT_R = crate::BitReader; #[doc = "Field `ENDBOOT` writer - Boot operation has terminated"] -pub type ENDBOOT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type ENDBOOT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTO_ERR` reader - Command timeout"] -pub type CTO_ERR_R = crate::BitReader; +pub type CTO_ERR_R = crate::BitReader; #[doc = "Field `CTO_ERR` writer - Command timeout"] -pub type CTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CCRC_ERR` reader - Command CRC error"] -pub type CCRC_ERR_R = crate::BitReader; +pub type CCRC_ERR_R = crate::BitReader; #[doc = "Field `CCRC_ERR` writer - Command CRC error"] -pub type CCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CEND_ERR` reader - Command end bit error (not 1)"] -pub type CEND_ERR_R = crate::BitReader; +pub type CEND_ERR_R = crate::BitReader; #[doc = "Field `CEND_ERR` writer - Command end bit error (not 1)"] -pub type CEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CBAD_ERR` reader - Incorrect response command index"] -pub type CBAD_ERR_R = crate::BitReader; +pub type CBAD_ERR_R = crate::BitReader; #[doc = "Field `CBAD_ERR` writer - Incorrect response command index"] -pub type CBAD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type CBAD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTO_ERR` reader - Data timeout"] -pub type DTO_ERR_R = crate::BitReader; +pub type DTO_ERR_R = crate::BitReader; #[doc = "Field `DTO_ERR` writer - Data timeout"] -pub type DTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type DTO_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRC_ERR` reader - Data CRC error"] -pub type DCRC_ERR_R = crate::BitReader; +pub type DCRC_ERR_R = crate::BitReader; #[doc = "Field `DCRC_ERR` writer - Data CRC error"] -pub type DCRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type DCRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEND_ERR` reader - Data end bit error (not 1)"] -pub type DEND_ERR_R = crate::BitReader; +pub type DEND_ERR_R = crate::BitReader; #[doc = "Field `DEND_ERR` writer - Data end bit error (not 1)"] -pub type DEND_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type DEND_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMD_ERR` reader - Auto command error"] -pub type ACMD_ERR_R = crate::BitReader; +pub type ACMD_ERR_R = crate::BitReader; #[doc = "Field `ACMD_ERR` writer - Auto command error"] -pub type ACMD_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRPT_MASK_SPEC, bool, O>; +pub type ACMD_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Command has finished"] #[inline(always)] @@ -189,128 +157,157 @@ impl R { ACMD_ERR_R::new(((self.bits >> 24) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IRPT_MASK") + .field("acmd_err", &format_args!("{}", self.acmd_err().bit())) + .field("dend_err", &format_args!("{}", self.dend_err().bit())) + .field("dcrc_err", &format_args!("{}", self.dcrc_err().bit())) + .field("dto_err", &format_args!("{}", self.dto_err().bit())) + .field("cbad_err", &format_args!("{}", self.cbad_err().bit())) + .field("cend_err", &format_args!("{}", self.cend_err().bit())) + .field("ccrc_err", &format_args!("{}", self.ccrc_err().bit())) + .field("cto_err", &format_args!("{}", self.cto_err().bit())) + .field("endboot", &format_args!("{}", self.endboot().bit())) + .field("bootack", &format_args!("{}", self.bootack().bit())) + .field("retune", &format_args!("{}", self.retune().bit())) + .field("card", &format_args!("{}", self.card().bit())) + .field("read_rdy", &format_args!("{}", self.read_rdy().bit())) + .field("write_rdy", &format_args!("{}", self.write_rdy().bit())) + .field("block_gap", &format_args!("{}", self.block_gap().bit())) + .field("data_done", &format_args!("{}", self.data_done().bit())) + .field("cmd_done", &format_args!("{}", self.cmd_done().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command has finished"] #[inline(always)] #[must_use] - pub fn cmd_done(&mut self) -> CMD_DONE_W<0> { + pub fn cmd_done(&mut self) -> CMD_DONE_W { CMD_DONE_W::new(self) } #[doc = "Bit 1 - Data transfer has finished"] #[inline(always)] #[must_use] - pub fn data_done(&mut self) -> DATA_DONE_W<1> { + pub fn data_done(&mut self) -> DATA_DONE_W { DATA_DONE_W::new(self) } #[doc = "Bit 2 - Data transfer has stopped at block gap"] #[inline(always)] #[must_use] - pub fn block_gap(&mut self) -> BLOCK_GAP_W<2> { + pub fn block_gap(&mut self) -> BLOCK_GAP_W { BLOCK_GAP_W::new(self) } #[doc = "Bit 4 - DATA can be written to"] #[inline(always)] #[must_use] - pub fn write_rdy(&mut self) -> WRITE_RDY_W<4> { + pub fn write_rdy(&mut self) -> WRITE_RDY_W { WRITE_RDY_W::new(self) } #[doc = "Bit 5 - DATA contains data to be read"] #[inline(always)] #[must_use] - pub fn read_rdy(&mut self) -> READ_RDY_W<5> { + pub fn read_rdy(&mut self) -> READ_RDY_W { READ_RDY_W::new(self) } #[doc = "Bit 8 - Card made interrupt request"] #[inline(always)] #[must_use] - pub fn card(&mut self) -> CARD_W<8> { + pub fn card(&mut self) -> CARD_W { CARD_W::new(self) } #[doc = "Bit 12 - Clock retune request"] #[inline(always)] #[must_use] - pub fn retune(&mut self) -> RETUNE_W<12> { + pub fn retune(&mut self) -> RETUNE_W { RETUNE_W::new(self) } #[doc = "Bit 13 - Boot has been acknowledged"] #[inline(always)] #[must_use] - pub fn bootack(&mut self) -> BOOTACK_W<13> { + pub fn bootack(&mut self) -> BOOTACK_W { BOOTACK_W::new(self) } #[doc = "Bit 14 - Boot operation has terminated"] #[inline(always)] #[must_use] - pub fn endboot(&mut self) -> ENDBOOT_W<14> { + pub fn endboot(&mut self) -> ENDBOOT_W { ENDBOOT_W::new(self) } #[doc = "Bit 16 - Command timeout"] #[inline(always)] #[must_use] - pub fn cto_err(&mut self) -> CTO_ERR_W<16> { + pub fn cto_err(&mut self) -> CTO_ERR_W { CTO_ERR_W::new(self) } #[doc = "Bit 17 - Command CRC error"] #[inline(always)] #[must_use] - pub fn ccrc_err(&mut self) -> CCRC_ERR_W<17> { + pub fn ccrc_err(&mut self) -> CCRC_ERR_W { CCRC_ERR_W::new(self) } #[doc = "Bit 18 - Command end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn cend_err(&mut self) -> CEND_ERR_W<18> { + pub fn cend_err(&mut self) -> CEND_ERR_W { CEND_ERR_W::new(self) } #[doc = "Bit 19 - Incorrect response command index"] #[inline(always)] #[must_use] - pub fn cbad_err(&mut self) -> CBAD_ERR_W<19> { + pub fn cbad_err(&mut self) -> CBAD_ERR_W { CBAD_ERR_W::new(self) } #[doc = "Bit 20 - Data timeout"] #[inline(always)] #[must_use] - pub fn dto_err(&mut self) -> DTO_ERR_W<20> { + pub fn dto_err(&mut self) -> DTO_ERR_W { DTO_ERR_W::new(self) } #[doc = "Bit 21 - Data CRC error"] #[inline(always)] #[must_use] - pub fn dcrc_err(&mut self) -> DCRC_ERR_W<21> { + pub fn dcrc_err(&mut self) -> DCRC_ERR_W { DCRC_ERR_W::new(self) } #[doc = "Bit 22 - Data end bit error (not 1)"] #[inline(always)] #[must_use] - pub fn dend_err(&mut self) -> DEND_ERR_W<22> { + pub fn dend_err(&mut self) -> DEND_ERR_W { DEND_ERR_W::new(self) } #[doc = "Bit 24 - Auto command error"] #[inline(always)] #[must_use] - pub fn acmd_err(&mut self) -> ACMD_ERR_W<24> { + pub fn acmd_err(&mut self) -> ACMD_ERR_W { ACMD_ERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mask interrupts that change in INTERRUPT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irpt_mask](index.html) module"] +#[doc = "Mask interrupts that change in INTERRUPT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irpt_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irpt_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRPT_MASK_SPEC; impl crate::RegisterSpec for IRPT_MASK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [irpt_mask::R](R) reader structure"] -impl crate::Readable for IRPT_MASK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [irpt_mask::W](W) writer structure"] +#[doc = "`read()` method returns [`irpt_mask::R`](R) reader structure"] +impl crate::Readable for IRPT_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irpt_mask::W`](W) writer structure"] impl crate::Writable for IRPT_MASK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/resp0.rs b/crates/bcm2837-lpa/src/emmc/resp0.rs index 1022d1a..79ea5ca 100644 --- a/crates/bcm2837-lpa/src/emmc/resp0.rs +++ b/crates/bcm2837-lpa/src/emmc/resp0.rs @@ -1,59 +1,38 @@ #[doc = "Register `RESP0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RESP0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status bits of the response\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp0](index.html) module"] +#[doc = "Status bits of the response\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESP0_SPEC; impl crate::RegisterSpec for RESP0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [resp0::R](R) reader structure"] -impl crate::Readable for RESP0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [resp0::W](W) writer structure"] +#[doc = "`read()` method returns [`resp0::R`](R) reader structure"] +impl crate::Readable for RESP0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resp0::W`](W) writer structure"] impl crate::Writable for RESP0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/resp1.rs b/crates/bcm2837-lpa/src/emmc/resp1.rs index d1e9b42..12a2f9a 100644 --- a/crates/bcm2837-lpa/src/emmc/resp1.rs +++ b/crates/bcm2837-lpa/src/emmc/resp1.rs @@ -1,59 +1,38 @@ #[doc = "Register `RESP1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RESP1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Bits 63:32 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp1](index.html) module"] +#[doc = "Bits 63:32 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESP1_SPEC; impl crate::RegisterSpec for RESP1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [resp1::R](R) reader structure"] -impl crate::Readable for RESP1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [resp1::W](W) writer structure"] +#[doc = "`read()` method returns [`resp1::R`](R) reader structure"] +impl crate::Readable for RESP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resp1::W`](W) writer structure"] impl crate::Writable for RESP1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/resp2.rs b/crates/bcm2837-lpa/src/emmc/resp2.rs index 418942a..5a51d34 100644 --- a/crates/bcm2837-lpa/src/emmc/resp2.rs +++ b/crates/bcm2837-lpa/src/emmc/resp2.rs @@ -1,59 +1,38 @@ #[doc = "Register `RESP2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RESP2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Bits 95:64 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp2](index.html) module"] +#[doc = "Bits 95:64 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESP2_SPEC; impl crate::RegisterSpec for RESP2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [resp2::R](R) reader structure"] -impl crate::Readable for RESP2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [resp2::W](W) writer structure"] +#[doc = "`read()` method returns [`resp2::R`](R) reader structure"] +impl crate::Readable for RESP2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resp2::W`](W) writer structure"] impl crate::Writable for RESP2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/resp3.rs b/crates/bcm2837-lpa/src/emmc/resp3.rs index 36b2c80..65ef18f 100644 --- a/crates/bcm2837-lpa/src/emmc/resp3.rs +++ b/crates/bcm2837-lpa/src/emmc/resp3.rs @@ -1,59 +1,38 @@ #[doc = "Register `RESP3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RESP3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Bits 127:96 of CMD2 and CMD10 responses\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [resp3](index.html) module"] +#[doc = "Bits 127:96 of CMD2 and CMD10 responses\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resp3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESP3_SPEC; impl crate::RegisterSpec for RESP3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [resp3::R](R) reader structure"] -impl crate::Readable for RESP3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [resp3::W](W) writer structure"] +#[doc = "`read()` method returns [`resp3::R`](R) reader structure"] +impl crate::Readable for RESP3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resp3::W`](W) writer structure"] impl crate::Writable for RESP3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/slotisr_ver.rs b/crates/bcm2837-lpa/src/emmc/slotisr_ver.rs index 6016436..0db90df 100644 --- a/crates/bcm2837-lpa/src/emmc/slotisr_ver.rs +++ b/crates/bcm2837-lpa/src/emmc/slotisr_ver.rs @@ -1,52 +1,19 @@ #[doc = "Register `SLOTISR_VER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SLOTISR_VER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLOT_STATUS` reader - OR of interrupt and wakeup signals for each slot"] -pub type SLOT_STATUS_R = crate::FieldReader; +pub type SLOT_STATUS_R = crate::FieldReader; #[doc = "Field `SLOT_STATUS` writer - OR of interrupt and wakeup signals for each slot"] -pub type SLOT_STATUS_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +pub type SLOT_STATUS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SDVERSION` reader - Host controller specification version"] -pub type SDVERSION_R = crate::FieldReader; +pub type SDVERSION_R = crate::FieldReader; #[doc = "Field `SDVERSION` writer - Host controller specification version"] -pub type SDVERSION_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +pub type SDVERSION_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `VENDOR` reader - Vendor version number"] -pub type VENDOR_R = crate::FieldReader; +pub type VENDOR_R = crate::FieldReader; #[doc = "Field `VENDOR` writer - Vendor version number"] -pub type VENDOR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SLOTISR_VER_SPEC, u8, u8, 8, O>; +pub type VENDOR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - OR of interrupt and wakeup signals for each slot"] #[inline(always)] @@ -64,44 +31,62 @@ impl R { VENDOR_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLOTISR_VER") + .field("vendor", &format_args!("{}", self.vendor().bits())) + .field("sdversion", &format_args!("{}", self.sdversion().bits())) + .field( + "slot_status", + &format_args!("{}", self.slot_status().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - OR of interrupt and wakeup signals for each slot"] #[inline(always)] #[must_use] - pub fn slot_status(&mut self) -> SLOT_STATUS_W<0> { + pub fn slot_status(&mut self) -> SLOT_STATUS_W { SLOT_STATUS_W::new(self) } #[doc = "Bits 16:23 - Host controller specification version"] #[inline(always)] #[must_use] - pub fn sdversion(&mut self) -> SDVERSION_W<16> { + pub fn sdversion(&mut self) -> SDVERSION_W { SDVERSION_W::new(self) } #[doc = "Bits 24:31 - Vendor version number"] #[inline(always)] #[must_use] - pub fn vendor(&mut self) -> VENDOR_W<24> { + pub fn vendor(&mut self) -> VENDOR_W { VENDOR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Version information and slot interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slotisr_ver](index.html) module"] +#[doc = "Version information and slot interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slotisr_ver::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slotisr_ver::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLOTISR_VER_SPEC; impl crate::RegisterSpec for SLOTISR_VER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [slotisr_ver::R](R) reader structure"] -impl crate::Readable for SLOTISR_VER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [slotisr_ver::W](W) writer structure"] +#[doc = "`read()` method returns [`slotisr_ver::R`](R) reader structure"] +impl crate::Readable for SLOTISR_VER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slotisr_ver::W`](W) writer structure"] impl crate::Writable for SLOTISR_VER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/spi_int_spt.rs b/crates/bcm2837-lpa/src/emmc/spi_int_spt.rs index bce7edc..ba304fe 100644 --- a/crates/bcm2837-lpa/src/emmc/spi_int_spt.rs +++ b/crates/bcm2837-lpa/src/emmc/spi_int_spt.rs @@ -1,43 +1,11 @@ #[doc = "Register `SPI_INT_SPT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SPI_INT_SPT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SELECT` reader - "] -pub type SELECT_R = crate::FieldReader; +pub type SELECT_R = crate::FieldReader; #[doc = "Field `SELECT` writer - "] -pub type SELECT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SPI_INT_SPT_SPEC, u8, u8, 8, O>; +pub type SELECT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { SELECT_R::new((self.bits & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_INT_SPT") + .field("select", &format_args!("{}", self.select().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7"] #[inline(always)] #[must_use] - pub fn select(&mut self) -> SELECT_W<0> { + pub fn select(&mut self) -> SELECT_W { SELECT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupts in SPI mode depend on CS\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_int_spt](index.html) module"] +#[doc = "Interrupts in SPI mode depend on CS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_int_spt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_int_spt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SPI_INT_SPT_SPEC; impl crate::RegisterSpec for SPI_INT_SPT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [spi_int_spt::R](R) reader structure"] -impl crate::Readable for SPI_INT_SPT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [spi_int_spt::W](W) writer structure"] +#[doc = "`read()` method returns [`spi_int_spt::R`](R) reader structure"] +impl crate::Readable for SPI_INT_SPT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_int_spt::W`](W) writer structure"] impl crate::Writable for SPI_INT_SPT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/status.rs b/crates/bcm2837-lpa/src/emmc/status.rs index 0b86ab0..2b07e21 100644 --- a/crates/bcm2837-lpa/src/emmc/status.rs +++ b/crates/bcm2837-lpa/src/emmc/status.rs @@ -1,79 +1,47 @@ #[doc = "Register `STATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STATUS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMD_INHIBIT` reader - Command line still in use"] -pub type CMD_INHIBIT_R = crate::BitReader; +pub type CMD_INHIBIT_R = crate::BitReader; #[doc = "Field `CMD_INHIBIT` writer - Command line still in use"] -pub type CMD_INHIBIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type CMD_INHIBIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAT_INHIBIT` reader - Data lines still in use"] -pub type DAT_INHIBIT_R = crate::BitReader; +pub type DAT_INHIBIT_R = crate::BitReader; #[doc = "Field `DAT_INHIBIT` writer - Data lines still in use"] -pub type DAT_INHIBIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type DAT_INHIBIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAT_ACTIVE` reader - At least one data line is active"] -pub type DAT_ACTIVE_R = crate::BitReader; +pub type DAT_ACTIVE_R = crate::BitReader; #[doc = "Field `DAT_ACTIVE` writer - At least one data line is active"] -pub type DAT_ACTIVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type DAT_ACTIVE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_TRANSFER` reader - Write transfer is active"] -pub type WRITE_TRANSFER_R = crate::BitReader; +pub type WRITE_TRANSFER_R = crate::BitReader; #[doc = "Field `WRITE_TRANSFER` writer - Write transfer is active"] -pub type WRITE_TRANSFER_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type WRITE_TRANSFER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `READ_TRANSFER` reader - Read transfer is active"] -pub type READ_TRANSFER_R = crate::BitReader; +pub type READ_TRANSFER_R = crate::BitReader; #[doc = "Field `READ_TRANSFER` writer - Read transfer is active"] -pub type READ_TRANSFER_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type READ_TRANSFER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUFFER_WRITE_ENABLE` reader - The buffer has space for new data"] -pub type BUFFER_WRITE_ENABLE_R = crate::BitReader; +pub type BUFFER_WRITE_ENABLE_R = crate::BitReader; #[doc = "Field `BUFFER_WRITE_ENABLE` writer - The buffer has space for new data"] -pub type BUFFER_WRITE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type BUFFER_WRITE_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUFFER_READ_ENABLE` reader - New data is available to read"] -pub type BUFFER_READ_ENABLE_R = crate::BitReader; +pub type BUFFER_READ_ENABLE_R = crate::BitReader; #[doc = "Field `BUFFER_READ_ENABLE` writer - New data is available to read"] -pub type BUFFER_READ_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type BUFFER_READ_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAT_LEVEL0` reader - Value of DAT\\[3:0\\]"] -pub type DAT_LEVEL0_R = crate::FieldReader; +pub type DAT_LEVEL0_R = crate::FieldReader; #[doc = "Field `DAT_LEVEL0` writer - Value of DAT\\[3:0\\]"] -pub type DAT_LEVEL0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STATUS_SPEC, u8, u8, 4, O>; +pub type DAT_LEVEL0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CMD_LEVEL` reader - Value of CMD"] -pub type CMD_LEVEL_R = crate::BitReader; +pub type CMD_LEVEL_R = crate::BitReader; #[doc = "Field `CMD_LEVEL` writer - Value of CMD"] -pub type CMD_LEVEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +pub type CMD_LEVEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAT_LEVEL1` reader - Value of DAT\\[7:4\\]"] -pub type DAT_LEVEL1_R = crate::FieldReader; +pub type DAT_LEVEL1_R = crate::FieldReader; #[doc = "Field `DAT_LEVEL1` writer - Value of DAT\\[7:4\\]"] -pub type DAT_LEVEL1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STATUS_SPEC, u8, u8, 4, O>; +pub type DAT_LEVEL1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bit 0 - Command line still in use"] #[inline(always)] @@ -126,86 +94,120 @@ impl R { DAT_LEVEL1_R::new(((self.bits >> 25) & 0x0f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS") + .field("dat_level1", &format_args!("{}", self.dat_level1().bits())) + .field("cmd_level", &format_args!("{}", self.cmd_level().bit())) + .field("dat_level0", &format_args!("{}", self.dat_level0().bits())) + .field( + "buffer_read_enable", + &format_args!("{}", self.buffer_read_enable().bit()), + ) + .field( + "buffer_write_enable", + &format_args!("{}", self.buffer_write_enable().bit()), + ) + .field( + "read_transfer", + &format_args!("{}", self.read_transfer().bit()), + ) + .field( + "write_transfer", + &format_args!("{}", self.write_transfer().bit()), + ) + .field("dat_active", &format_args!("{}", self.dat_active().bit())) + .field("dat_inhibit", &format_args!("{}", self.dat_inhibit().bit())) + .field("cmd_inhibit", &format_args!("{}", self.cmd_inhibit().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Command line still in use"] #[inline(always)] #[must_use] - pub fn cmd_inhibit(&mut self) -> CMD_INHIBIT_W<0> { + pub fn cmd_inhibit(&mut self) -> CMD_INHIBIT_W { CMD_INHIBIT_W::new(self) } #[doc = "Bit 1 - Data lines still in use"] #[inline(always)] #[must_use] - pub fn dat_inhibit(&mut self) -> DAT_INHIBIT_W<1> { + pub fn dat_inhibit(&mut self) -> DAT_INHIBIT_W { DAT_INHIBIT_W::new(self) } #[doc = "Bit 2 - At least one data line is active"] #[inline(always)] #[must_use] - pub fn dat_active(&mut self) -> DAT_ACTIVE_W<2> { + pub fn dat_active(&mut self) -> DAT_ACTIVE_W { DAT_ACTIVE_W::new(self) } #[doc = "Bit 8 - Write transfer is active"] #[inline(always)] #[must_use] - pub fn write_transfer(&mut self) -> WRITE_TRANSFER_W<8> { + pub fn write_transfer(&mut self) -> WRITE_TRANSFER_W { WRITE_TRANSFER_W::new(self) } #[doc = "Bit 9 - Read transfer is active"] #[inline(always)] #[must_use] - pub fn read_transfer(&mut self) -> READ_TRANSFER_W<9> { + pub fn read_transfer(&mut self) -> READ_TRANSFER_W { READ_TRANSFER_W::new(self) } #[doc = "Bit 10 - The buffer has space for new data"] #[inline(always)] #[must_use] - pub fn buffer_write_enable(&mut self) -> BUFFER_WRITE_ENABLE_W<10> { + pub fn buffer_write_enable(&mut self) -> BUFFER_WRITE_ENABLE_W { BUFFER_WRITE_ENABLE_W::new(self) } #[doc = "Bit 11 - New data is available to read"] #[inline(always)] #[must_use] - pub fn buffer_read_enable(&mut self) -> BUFFER_READ_ENABLE_W<11> { + pub fn buffer_read_enable(&mut self) -> BUFFER_READ_ENABLE_W { BUFFER_READ_ENABLE_W::new(self) } #[doc = "Bits 20:23 - Value of DAT\\[3:0\\]"] #[inline(always)] #[must_use] - pub fn dat_level0(&mut self) -> DAT_LEVEL0_W<20> { + pub fn dat_level0(&mut self) -> DAT_LEVEL0_W { DAT_LEVEL0_W::new(self) } #[doc = "Bit 24 - Value of CMD"] #[inline(always)] #[must_use] - pub fn cmd_level(&mut self) -> CMD_LEVEL_W<24> { + pub fn cmd_level(&mut self) -> CMD_LEVEL_W { CMD_LEVEL_W::new(self) } #[doc = "Bits 25:28 - Value of DAT\\[7:4\\]"] #[inline(always)] #[must_use] - pub fn dat_level1(&mut self) -> DAT_LEVEL1_W<25> { + pub fn dat_level1(&mut self) -> DAT_LEVEL1_W { DAT_LEVEL1_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status info for debugging\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +#[doc = "Status info for debugging\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STATUS_SPEC; impl crate::RegisterSpec for STATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [status::R](R) reader structure"] -impl crate::Readable for STATUS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"] impl crate::Writable for STATUS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/tune_step.rs b/crates/bcm2837-lpa/src/emmc/tune_step.rs index 2f0169b..aa0dd84 100644 --- a/crates/bcm2837-lpa/src/emmc/tune_step.rs +++ b/crates/bcm2837-lpa/src/emmc/tune_step.rs @@ -1,43 +1,11 @@ #[doc = "Register `TUNE_STEP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TUNE_STEP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DELAY` reader - "] -pub type DELAY_R = crate::FieldReader; +pub type DELAY_R = crate::FieldReader; #[doc = "Field `DELAY` writer - "] -pub type DELAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEP_SPEC, u8, u8, 3, O>; +pub type DELAY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:2"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DELAY_R::new((self.bits & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TUNE_STEP") + .field("delay", &format_args!("{}", self.delay().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2"] #[inline(always)] #[must_use] - pub fn delay(&mut self) -> DELAY_W<0> { + pub fn delay(&mut self) -> DELAY_W { DELAY_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Sample clock delay step duration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_step](index.html) module"] +#[doc = "Sample clock delay step duration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_step::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_step::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TUNE_STEP_SPEC; impl crate::RegisterSpec for TUNE_STEP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tune_step::R](R) reader structure"] -impl crate::Readable for TUNE_STEP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tune_step::W](W) writer structure"] +#[doc = "`read()` method returns [`tune_step::R`](R) reader structure"] +impl crate::Readable for TUNE_STEP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tune_step::W`](W) writer structure"] impl crate::Writable for TUNE_STEP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/tune_steps_ddr.rs b/crates/bcm2837-lpa/src/emmc/tune_steps_ddr.rs index a8fea76..c4f1dd8 100644 --- a/crates/bcm2837-lpa/src/emmc/tune_steps_ddr.rs +++ b/crates/bcm2837-lpa/src/emmc/tune_steps_ddr.rs @@ -1,43 +1,11 @@ #[doc = "Register `TUNE_STEPS_DDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TUNE_STEPS_DDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `STEPS` reader - "] -pub type STEPS_R = crate::FieldReader; +pub type STEPS_R = crate::FieldReader; #[doc = "Field `STEPS` writer - "] -pub type STEPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEPS_DDR_SPEC, u8, u8, 6, O>; +pub type STEPS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { STEPS_R::new((self.bits & 0x3f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TUNE_STEPS_DDR") + .field("steps", &format_args!("{}", self.steps().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn steps(&mut self) -> STEPS_W<0> { + pub fn steps(&mut self) -> STEPS_W { STEPS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Sample clock delay step count for DDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_steps_ddr](index.html) module"] +#[doc = "Sample clock delay step count for DDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_steps_ddr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_steps_ddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TUNE_STEPS_DDR_SPEC; impl crate::RegisterSpec for TUNE_STEPS_DDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tune_steps_ddr::R](R) reader structure"] -impl crate::Readable for TUNE_STEPS_DDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tune_steps_ddr::W](W) writer structure"] +#[doc = "`read()` method returns [`tune_steps_ddr::R`](R) reader structure"] +impl crate::Readable for TUNE_STEPS_DDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tune_steps_ddr::W`](W) writer structure"] impl crate::Writable for TUNE_STEPS_DDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/emmc/tune_steps_std.rs b/crates/bcm2837-lpa/src/emmc/tune_steps_std.rs index c04740c..cf65897 100644 --- a/crates/bcm2837-lpa/src/emmc/tune_steps_std.rs +++ b/crates/bcm2837-lpa/src/emmc/tune_steps_std.rs @@ -1,43 +1,11 @@ #[doc = "Register `TUNE_STEPS_STD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TUNE_STEPS_STD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `STEPS` reader - "] -pub type STEPS_R = crate::FieldReader; +pub type STEPS_R = crate::FieldReader; #[doc = "Field `STEPS` writer - "] -pub type STEPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TUNE_STEPS_STD_SPEC, u8, u8, 6, O>; +pub type STEPS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { STEPS_R::new((self.bits & 0x3f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TUNE_STEPS_STD") + .field("steps", &format_args!("{}", self.steps().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5"] #[inline(always)] #[must_use] - pub fn steps(&mut self) -> STEPS_W<0> { + pub fn steps(&mut self) -> STEPS_W { STEPS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Sample clock delay step count for SDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tune_steps_std](index.html) module"] +#[doc = "Sample clock delay step count for SDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tune_steps_std::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tune_steps_std::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TUNE_STEPS_STD_SPEC; impl crate::RegisterSpec for TUNE_STEPS_STD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tune_steps_std::R](R) reader structure"] -impl crate::Readable for TUNE_STEPS_STD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tune_steps_std::W](W) writer structure"] +#[doc = "`read()` method returns [`tune_steps_std::R`](R) reader structure"] +impl crate::Readable for TUNE_STEPS_STD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tune_steps_std::W`](W) writer structure"] impl crate::Writable for TUNE_STEPS_STD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/generic.rs b/crates/bcm2837-lpa/src/generic.rs index f10ca73..a34573a 100644 --- a/crates/bcm2837-lpa/src/generic.rs +++ b/crates/bcm2837-lpa/src/generic.rs @@ -31,6 +31,9 @@ macro_rules! raw_reg { const fn $mask() -> $U { <$U>::MAX >> ($size - WI) } + impl FieldSpec for $U { + type Ux = $U; + } }; } raw_reg!(u8, 8, mask_u8); @@ -42,21 +45,21 @@ pub trait RegisterSpec { #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] type Ux: RawReg; } +#[doc = " Raw field type"] +pub trait FieldSpec: Sized { + #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy + PartialEq + From; +} #[doc = " Trait implemented by readable registers to enable the `read` method."] #[doc = ""] #[doc = " Registers marked with `Writable` can be also be `modify`'ed."] -pub trait Readable: RegisterSpec { - #[doc = " Result from a call to `read` and argument to `modify`."] - type Reader: From> + core::ops::Deref>; -} +pub trait Readable: RegisterSpec {} #[doc = " Trait implemented by writeable registers."] #[doc = ""] #[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] #[doc = ""] #[doc = " Registers marked with `Readable` can be also be `modify`'ed."] pub trait Writable: RegisterSpec { - #[doc = " Writer type argument to `write`, et al."] - type Writer: From> + core::ops::DerefMut>; #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] @@ -107,11 +110,11 @@ impl Reg { #[doc = " let flag = reader.field2().bit_is_set();"] #[doc = " ```"] #[inline(always)] - pub fn read(&self) -> REG::Reader { - REG::Reader::from(R { + pub fn read(&self) -> R { + R { bits: self.register.get(), _reg: marker::PhantomData, - }) + } } } impl Reg { @@ -148,14 +151,14 @@ impl Reg { #[inline(always)] pub fn write(&self, f: F) where - F: FnOnce(&mut REG::Writer) -> &mut W, + F: FnOnce(&mut W) -> &mut W, { self.register.set( - f(&mut REG::Writer::from(W { + f(&mut W { bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, _reg: marker::PhantomData, - })) + }) .bits, ); } @@ -171,13 +174,13 @@ impl Reg { #[inline(always)] pub unsafe fn write_with_zero(&self, f: F) where - F: FnOnce(&mut REG::Writer) -> &mut W, + F: FnOnce(&mut W) -> &mut W, { self.register.set( - f(&mut REG::Writer::from(W { + f(&mut W { bits: REG::Ux::default(), _reg: marker::PhantomData, - })) + }) .bits, ); } @@ -211,37 +214,36 @@ impl Reg { #[inline(always)] pub fn modify(&self, f: F) where - for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); self.register.set( f( - ®::Reader::from(R { + &R { bits, _reg: marker::PhantomData, - }), - &mut REG::Writer::from(W { + }, + &mut W { bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, _reg: marker::PhantomData, - }), + }, ) .bits, ); } } +#[doc(hidden)] +pub mod raw; #[doc = " Register reader."] #[doc = ""] #[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] #[doc = " method."] -pub struct R { - pub(crate) bits: REG::Ux, - _reg: marker::PhantomData, -} +pub type R = raw::R; impl R { #[doc = " Reads raw bits from register."] #[inline(always)] - pub fn bits(&self) -> REG::Ux { + pub const fn bits(&self) -> REG::Ux { self.bits } } @@ -259,83 +261,27 @@ where #[doc = " Register writer."] #[doc = ""] #[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] -pub struct W { - #[doc = "Writable bits"] - pub(crate) bits: REG::Ux, - _reg: marker::PhantomData, -} -impl W { - #[doc = " Writes raw bits to the register."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Read datasheet or reference manual to find what values are allowed to pass."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { - self.bits = bits; - self - } -} -#[doc(hidden)] -pub struct FieldReaderRaw { - pub(crate) bits: U, - _reg: marker::PhantomData, -} -impl FieldReaderRaw -where - U: Copy, -{ - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(bits: U) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} -#[doc(hidden)] -pub struct BitReaderRaw { - pub(crate) bits: bool, - _reg: marker::PhantomData, -} -impl BitReaderRaw { - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(bits: bool) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} +pub type W = raw::W; #[doc = " Field reader."] #[doc = ""] #[doc = " Result of the `read` methods of fields."] -pub type FieldReader = FieldReaderRaw; +pub type FieldReader = raw::FieldReader; #[doc = " Bit-wise field reader"] -pub type BitReader = BitReaderRaw; -impl FieldReader -where - U: Copy, -{ +pub type BitReader = raw::BitReader; +impl FieldReader { #[doc = " Reads raw bits from field."] #[inline(always)] - pub fn bits(&self) -> U { + pub const fn bits(&self) -> FI::Ux { self.bits } } -impl PartialEq for FieldReader +impl PartialEq for FieldReader where - U: PartialEq, - FI: Copy, - U: From, + FI: FieldSpec + Copy, { #[inline(always)] fn eq(&self, other: &FI) -> bool { - self.bits.eq(&U::from(*other)) + self.bits.eq(&FI::Ux::from(*other)) } } impl PartialEq for BitReader @@ -351,17 +297,17 @@ where impl BitReader { #[doc = " Value of the field as raw bits."] #[inline(always)] - pub fn bit(&self) -> bool { + pub const fn bit(&self) -> bool { self.bits } #[doc = " Returns `true` if the bit is clear (0)."] #[inline(always)] - pub fn bit_is_clear(&self) -> bool { + pub const fn bit_is_clear(&self) -> bool { !self.bit() } #[doc = " Returns `true` if the bit is set (1)."] #[inline(always)] - pub fn bit_is_set(&self) -> bool { + pub const fn bit_is_set(&self) -> bool { self.bit() } } @@ -369,111 +315,81 @@ impl BitReader { pub struct Safe; #[doc(hidden)] pub struct Unsafe; -#[doc(hidden)] -pub struct FieldWriterRaw<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> -where - REG: Writable + RegisterSpec, - N: From, -{ - pub(crate) w: &'a mut REG::Writer, - _field: marker::PhantomData<(N, FI, Safety)>, -} -impl<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> - FieldWriterRaw<'a, U, REG, N, FI, Safety, WI, O> -where - REG: Writable + RegisterSpec, - N: From, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut REG::Writer) -> Self { - Self { - w, - _field: marker::PhantomData, - } - } -} -#[doc(hidden)] -pub struct BitWriterRaw<'a, U, REG, FI, M, const O: u8> -where - REG: Writable + RegisterSpec, - bool: From, -{ - pub(crate) w: &'a mut REG::Writer, - _field: marker::PhantomData<(FI, M)>, -} -impl<'a, U, REG, FI, M, const O: u8> BitWriterRaw<'a, U, REG, FI, M, O> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut REG::Writer) -> Self { - Self { - w, - _field: marker::PhantomData, - } - } -} #[doc = " Write field Proxy with unsafe `bits`"] -pub type FieldWriter<'a, U, REG, N, FI, const WI: u8, const O: u8> = - FieldWriterRaw<'a, U, REG, N, FI, Unsafe, WI, O>; +pub type FieldWriter<'a, REG, const WI: u8, const O: u8, FI = u8> = + raw::FieldWriter<'a, REG, WI, O, FI, Unsafe>; #[doc = " Write field Proxy with safe `bits`"] -pub type FieldWriterSafe<'a, U, REG, N, FI, const WI: u8, const O: u8> = - FieldWriterRaw<'a, U, REG, N, FI, Safe, WI, O>; -impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> +pub type FieldWriterSafe<'a, REG, const WI: u8, const O: u8, FI = u8> = + raw::FieldWriter<'a, REG, WI, O, FI, Safe>; +impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI> where - REG: Writable + RegisterSpec, - N: From, + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, { #[doc = " Field width"] pub const WIDTH: u8 = WI; + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << OF); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } } -impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> +impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI> where - REG: Writable + RegisterSpec, - N: From, + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, { #[doc = " Field width"] pub const WIDTH: u8 = WI; + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << OF); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bits(FI::Ux::from(variant)) + } } macro_rules! bit_proxy { ($ writer : ident , $ mwv : ident) => { #[doc(hidden)] pub struct $mwv; #[doc = " Bit-wise write field proxy"] - pub type $writer<'a, U, REG, FI, const O: u8> = BitWriterRaw<'a, U, REG, FI, $mwv, O>; - impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> + pub type $writer<'a, REG, const O: u8, FI = bool> = raw::BitWriter<'a, REG, O, FI, $mwv>; + impl<'a, REG, const OF: u8, FI> $writer<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, + REG: Writable + RegisterSpec, bool: From, { #[doc = " Field width"] pub const WIDTH: u8 = 1; - } - }; -} -macro_rules! impl_bit_proxy { - ($ writer : ident) => { - impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> - where - REG: Writable + RegisterSpec, - U: RawReg, - bool: From, - { #[doc = " Writes bit to the field"] #[inline(always)] - pub fn bit(self, value: bool) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); - self.w.bits |= (U::from(value) & U::one()) << OF; + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << OF; self.w } #[doc = " Writes `variant` to the field"] #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + pub fn variant(self, variant: FI) -> &'a mut W { self.bit(bool::from(variant)) } } @@ -486,210 +402,94 @@ bit_proxy!(BitWriter1C, Bit1C); bit_proxy!(BitWriter0S, Bit0S); bit_proxy!(BitWriter1T, Bit1T); bit_proxy!(BitWriter0T, Bit0T); -impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> -where - REG: Writable + RegisterSpec, - U: RawReg + From, - N: From, -{ - #[doc = " Writes raw bits to the field"] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(self, value: N) -> &'a mut REG::Writer { - self.w.bits &= !(U::mask::() << OF); - self.w.bits |= (U::from(value) & U::mask::()) << OF; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { - unsafe { self.bits(N::from(variant)) } - } -} -impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> -where - REG: Writable + RegisterSpec, - U: RawReg + From, - N: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn bits(self, value: N) -> &'a mut REG::Writer { - self.w.bits &= !(U::mask::() << OF); - self.w.bits |= (U::from(value) & U::mask::()) << OF; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { - self.bits(N::from(variant)) - } -} -impl_bit_proxy!(BitWriter); -impl_bit_proxy!(BitWriter1S); -impl_bit_proxy!(BitWriter0C); -impl_bit_proxy!(BitWriter1C); -impl_bit_proxy!(BitWriter0S); -impl_bit_proxy!(BitWriter1T); -impl_bit_proxy!(BitWriter0T); -impl<'a, U, REG, FI, const OF: u8> BitWriter<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = " Sets the field bit"] #[inline(always)] - pub fn set_bit(self) -> &'a mut REG::Writer { - self.w.bits |= U::one() << OF; + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << OF; self.w } #[doc = " Clears the field bit"] #[inline(always)] - pub fn clear_bit(self) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter1S<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter1S<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = " Sets the field bit"] #[inline(always)] - pub fn set_bit(self) -> &'a mut REG::Writer { - self.w.bits |= U::one() << OF; + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << OF; self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter0C<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter0C<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = " Clears the field bit"] #[inline(always)] - pub fn clear_bit(self) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter1C<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter1C<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = "Clears the field bit by passing one"] #[inline(always)] - pub fn clear_bit_by_one(self) -> &'a mut REG::Writer { - self.w.bits |= U::one() << OF; + pub fn clear_bit_by_one(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << OF; self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter0S<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter0S<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = "Sets the field bit by passing zero"] #[inline(always)] - pub fn set_bit_by_zero(self) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); + pub fn set_bit_by_zero(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter1T<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter1T<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = "Toggle the field bit by passing one"] #[inline(always)] - pub fn toggle_bit(self) -> &'a mut REG::Writer { - self.w.bits |= U::one() << OF; + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << OF; self.w } } -impl<'a, U, REG, FI, const OF: u8> BitWriter0T<'a, U, REG, FI, OF> +impl<'a, REG, const OF: u8, FI> BitWriter0T<'a, REG, OF, FI> where - REG: Writable + RegisterSpec, - U: RawReg, + REG: Writable + RegisterSpec, bool: From, { #[doc = "Toggle the field bit by passing zero"] #[inline(always)] - pub fn toggle_bit(self) -> &'a mut REG::Writer { - self.w.bits &= !(U::one() << OF); + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << OF); self.w } } mod atomic; -use atomic::AtomicOperations; -impl Reg -where - REG::Ux: AtomicOperations + Default + core::ops::Not, -{ - #[doc = " Set high every bit in the register that was set in the write proxy. Leave other bits"] - #[doc = " untouched. The write is done in a single atomic instruction."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " The resultant bit pattern may not be valid for the register."] - #[inline(always)] - pub unsafe fn set_bits(&self, f: F) - where - F: FnOnce(&mut REG::Writer) -> &mut W, - { - let bits = f(&mut REG::Writer::from(W { - bits: Default::default(), - _reg: marker::PhantomData, - })) - .bits; - REG::Ux::atomic_or(self.register.as_ptr(), bits); - } - #[doc = " Clear every bit in the register that was cleared in the write proxy. Leave other bits"] - #[doc = " untouched. The write is done in a single atomic instruction."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " The resultant bit pattern may not be valid for the register."] - #[inline(always)] - pub unsafe fn clear_bits(&self, f: F) - where - F: FnOnce(&mut REG::Writer) -> &mut W, - { - let bits = f(&mut REG::Writer::from(W { - bits: !REG::Ux::default(), - _reg: marker::PhantomData, - })) - .bits; - REG::Ux::atomic_and(self.register.as_ptr(), bits); - } - #[doc = " Toggle every bit in the register that was set in the write proxy. Leave other bits"] - #[doc = " untouched. The write is done in a single atomic instruction."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " The resultant bit pattern may not be valid for the register."] - #[inline(always)] - pub unsafe fn toggle_bits(&self, f: F) - where - F: FnOnce(&mut REG::Writer) -> &mut W, - { - let bits = f(&mut REG::Writer::from(W { - bits: Default::default(), - _reg: marker::PhantomData, - })) - .bits; - REG::Ux::atomic_xor(self.register.as_ptr(), bits); - } -} diff --git a/crates/bcm2837-lpa/src/generic/atomic.rs b/crates/bcm2837-lpa/src/generic/atomic.rs index acee997..89d6c54 100644 --- a/crates/bcm2837-lpa/src/generic/atomic.rs +++ b/crates/bcm2837-lpa/src/generic/atomic.rs @@ -1,3 +1,4 @@ +use super::*; use portable_atomic::Ordering; pub trait AtomicOperations { unsafe fn atomic_or(ptr: *mut Self, val: Self); @@ -25,3 +26,62 @@ impl_atomics!(u16, portable_atomic::AtomicU16); impl_atomics!(u32, portable_atomic::AtomicU32); #[cfg(any(target_pointer_width = "64", target_has_atomic = "64"))] impl_atomics!(u64, portable_atomic::AtomicU64); +impl Reg +where + REG::Ux: AtomicOperations + Default + core::ops::Not, +{ + #[doc = " Set high every bit in the register that was set in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn set_bits(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + let bits = f(&mut W { + bits: Default::default(), + _reg: marker::PhantomData, + }) + .bits; + REG::Ux::atomic_or(self.register.as_ptr(), bits); + } + #[doc = " Clear every bit in the register that was cleared in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn clear_bits(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + let bits = f(&mut W { + bits: !REG::Ux::default(), + _reg: marker::PhantomData, + }) + .bits; + REG::Ux::atomic_and(self.register.as_ptr(), bits); + } + #[doc = " Toggle every bit in the register that was set in the write proxy. Leave other bits"] + #[doc = " untouched. The write is done in a single atomic instruction."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " The resultant bit pattern may not be valid for the register."] + #[inline(always)] + pub unsafe fn toggle_bits(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + let bits = f(&mut W { + bits: Default::default(), + _reg: marker::PhantomData, + }) + .bits; + REG::Ux::atomic_xor(self.register.as_ptr(), bits); + } +} diff --git a/crates/bcm2837-lpa/src/generic/raw.rs b/crates/bcm2837-lpa/src/generic/raw.rs new file mode 100644 index 0000000..4ab1635 --- /dev/null +++ b/crates/bcm2837-lpa/src/generic/raw.rs @@ -0,0 +1,89 @@ +use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; +pub struct R { + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct FieldReader +where + FI: FieldSpec, +{ + pub(crate) bits: FI::Ux, + _reg: marker::PhantomData, +} +impl FieldReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: FI::Ux) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct BitReader { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct FieldWriter<'a, REG, const WI: u8, const O: u8, FI = u8, Safety = Unsafe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + pub(crate) w: &'a mut W, + _field: marker::PhantomData<(FI, Safety)>, +} +impl<'a, REG, const WI: u8, const O: u8, FI, Safety> FieldWriter<'a, REG, WI, O, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +pub struct BitWriter<'a, REG, const O: u8, FI = bool, M = BitM> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut W, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, REG, const O: u8, FI, M> BitWriter<'a, REG, O, FI, M> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} diff --git a/crates/bcm2837-lpa/src/gpio.rs b/crates/bcm2837-lpa/src/gpio.rs index e643036..270dc41 100644 --- a/crates/bcm2837-lpa/src/gpio.rs +++ b/crates/bcm2837-lpa/src/gpio.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - GPIO Function Select 0"] pub gpfsel0: GPFSEL0, @@ -76,130 +77,161 @@ pub struct RegisterBlock { #[doc = "0xf0 - GPIO Pull-up / Pull-down Register 3"] pub gpio_pup_pdn_cntrl_reg3: GPIO_PUP_PDN_CNTRL_REG3, } -#[doc = "GPFSEL0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL0 (rw) register accessor: GPIO Function Select 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel0`] +module"] pub type GPFSEL0 = crate::Reg; #[doc = "GPIO Function Select 0"] pub mod gpfsel0; -#[doc = "GPFSEL1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL1 (rw) register accessor: GPIO Function Select 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel1`] +module"] pub type GPFSEL1 = crate::Reg; #[doc = "GPIO Function Select 1"] pub mod gpfsel1; -#[doc = "GPFSEL2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL2 (rw) register accessor: GPIO Function Select 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel2`] +module"] pub type GPFSEL2 = crate::Reg; #[doc = "GPIO Function Select 2"] pub mod gpfsel2; -#[doc = "GPFSEL3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL3 (rw) register accessor: GPIO Function Select 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel3`] +module"] pub type GPFSEL3 = crate::Reg; #[doc = "GPIO Function Select 3"] pub mod gpfsel3; -#[doc = "GPFSEL4 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL4 (rw) register accessor: GPIO Function Select 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel4::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel4`] +module"] pub type GPFSEL4 = crate::Reg; #[doc = "GPIO Function Select 4"] pub mod gpfsel4; -#[doc = "GPFSEL5 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFSEL5 (rw) register accessor: GPIO Function Select 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel5::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfsel5`] +module"] pub type GPFSEL5 = crate::Reg; #[doc = "GPIO Function Select 5"] pub mod gpfsel5; -#[doc = "GPSET0 (w) register accessor: an alias for `Reg`"] +#[doc = "GPSET0 (w) register accessor: GPIO Pin Output Set 0\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpset0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpset0`] +module"] pub type GPSET0 = crate::Reg; #[doc = "GPIO Pin Output Set 0"] pub mod gpset0; -#[doc = "GPSET1 (w) register accessor: an alias for `Reg`"] +#[doc = "GPSET1 (w) register accessor: GPIO Pin Output Set 1\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpset1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpset1`] +module"] pub type GPSET1 = crate::Reg; #[doc = "GPIO Pin Output Set 1"] pub mod gpset1; -#[doc = "GPCLR0 (w) register accessor: an alias for `Reg`"] +#[doc = "GPCLR0 (w) register accessor: GPIO Pin Output Clear 0\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpclr0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr0`] +module"] pub type GPCLR0 = crate::Reg; #[doc = "GPIO Pin Output Clear 0"] pub mod gpclr0; -#[doc = "GPCLR1 (w) register accessor: an alias for `Reg`"] +#[doc = "GPCLR1 (w) register accessor: GPIO Pin Output Clear 1\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpclr1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpclr1`] +module"] pub type GPCLR1 = crate::Reg; #[doc = "GPIO Pin Output Clear 1"] pub mod gpclr1; -#[doc = "GPLEV0 (r) register accessor: an alias for `Reg`"] +#[doc = "GPLEV0 (r) register accessor: GPIO Pin Level 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplev0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gplev0`] +module"] pub type GPLEV0 = crate::Reg; #[doc = "GPIO Pin Level 0"] pub mod gplev0; -#[doc = "GPLEV1 (r) register accessor: an alias for `Reg`"] +#[doc = "GPLEV1 (r) register accessor: GPIO Pin Level 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplev1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gplev1`] +module"] pub type GPLEV1 = crate::Reg; #[doc = "GPIO Pin Level 1"] pub mod gplev1; -#[doc = "GPEDS0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPEDS0 (rw) register accessor: GPIO Pin Event Detect Status 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpeds0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpeds0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpeds0`] +module"] pub type GPEDS0 = crate::Reg; #[doc = "GPIO Pin Event Detect Status 0"] pub mod gpeds0; -#[doc = "GPEDS1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPEDS1 (rw) register accessor: GPIO Pin Event Detect Status 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpeds1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpeds1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpeds1`] +module"] pub type GPEDS1 = crate::Reg; #[doc = "GPIO Pin Event Detect Status 1"] pub mod gpeds1; -#[doc = "GPREN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPREN0 (rw) register accessor: GPIO Pin Rising Edge Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpren0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpren0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpren0`] +module"] pub type GPREN0 = crate::Reg; #[doc = "GPIO Pin Rising Edge Detect Enable 0"] pub mod gpren0; -#[doc = "GPREN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPREN1 (rw) register accessor: GPIO Pin Rising Edge Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpren1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpren1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpren1`] +module"] pub type GPREN1 = crate::Reg; #[doc = "GPIO Pin Rising Edge Detect Enable 1"] pub mod gpren1; -#[doc = "GPFEN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFEN0 (rw) register accessor: GPIO Pin Falling Edge Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfen0`] +module"] pub type GPFEN0 = crate::Reg; #[doc = "GPIO Pin Falling Edge Detect Enable 0"] pub mod gpfen0; -#[doc = "GPFEN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPFEN1 (rw) register accessor: GPIO Pin Falling Edge Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpfen1`] +module"] pub type GPFEN1 = crate::Reg; #[doc = "GPIO Pin Falling Edge Detect Enable 1"] pub mod gpfen1; -#[doc = "GPHEN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPHEN0 (rw) register accessor: GPIO Pin High Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gphen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gphen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gphen0`] +module"] pub type GPHEN0 = crate::Reg; #[doc = "GPIO Pin High Detect Enable 0"] pub mod gphen0; -#[doc = "GPHEN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPHEN1 (rw) register accessor: GPIO Pin High Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gphen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gphen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gphen1`] +module"] pub type GPHEN1 = crate::Reg; #[doc = "GPIO Pin High Detect Enable 1"] pub mod gphen1; -#[doc = "GPLEN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPLEN0 (rw) register accessor: GPIO Pin Low Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gplen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gplen0`] +module"] pub type GPLEN0 = crate::Reg; #[doc = "GPIO Pin Low Detect Enable 0"] pub mod gplen0; -#[doc = "GPLEN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPLEN1 (rw) register accessor: GPIO Pin Low Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gplen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gplen1`] +module"] pub type GPLEN1 = crate::Reg; #[doc = "GPIO Pin Low Detect Enable 1"] pub mod gplen1; -#[doc = "GPAREN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPAREN0 (rw) register accessor: GPIO Pin Async. Rising Edge Detect 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gparen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gparen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gparen0`] +module"] pub type GPAREN0 = crate::Reg; #[doc = "GPIO Pin Async. Rising Edge Detect 0"] pub mod gparen0; -#[doc = "GPAREN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPAREN1 (rw) register accessor: GPIO Pin Async. Rising Edge Detect 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gparen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gparen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gparen1`] +module"] pub type GPAREN1 = crate::Reg; #[doc = "GPIO Pin Async. Rising Edge Detect 1"] pub mod gparen1; -#[doc = "GPAFEN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPAFEN0 (rw) register accessor: GPIO Pin Async. Falling Edge Detect 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpafen0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpafen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpafen0`] +module"] pub type GPAFEN0 = crate::Reg; #[doc = "GPIO Pin Async. Falling Edge Detect 0"] pub mod gpafen0; -#[doc = "GPAFEN1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPAFEN1 (rw) register accessor: GPIO Pin Async. Falling Edge Detect 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpafen1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpafen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpafen1`] +module"] pub type GPAFEN1 = crate::Reg; #[doc = "GPIO Pin Async. Falling Edge Detect 1"] pub mod gpafen1; -#[doc = "EXTRA_MUX (rw) register accessor: an alias for `Reg`"] +#[doc = "EXTRA_MUX (rw) register accessor: Undocumented multiplexing bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extra_mux::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`extra_mux::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@extra_mux`] +module"] pub type EXTRA_MUX = crate::Reg; #[doc = "Undocumented multiplexing bits"] pub mod extra_mux; -#[doc = "GPIO_PUP_PDN_CNTRL_REG0 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_PUP_PDN_CNTRL_REG0 (rw) register accessor: GPIO Pull-up / Pull-down Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pup_pdn_cntrl_reg0`] +module"] pub type GPIO_PUP_PDN_CNTRL_REG0 = crate::Reg; #[doc = "GPIO Pull-up / Pull-down Register 0"] pub mod gpio_pup_pdn_cntrl_reg0; -#[doc = "GPIO_PUP_PDN_CNTRL_REG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_PUP_PDN_CNTRL_REG1 (rw) register accessor: GPIO Pull-up / Pull-down Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pup_pdn_cntrl_reg1`] +module"] pub type GPIO_PUP_PDN_CNTRL_REG1 = crate::Reg; #[doc = "GPIO Pull-up / Pull-down Register 1"] pub mod gpio_pup_pdn_cntrl_reg1; -#[doc = "GPIO_PUP_PDN_CNTRL_REG2 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_PUP_PDN_CNTRL_REG2 (rw) register accessor: GPIO Pull-up / Pull-down Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg2::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pup_pdn_cntrl_reg2`] +module"] pub type GPIO_PUP_PDN_CNTRL_REG2 = crate::Reg; #[doc = "GPIO Pull-up / Pull-down Register 2"] pub mod gpio_pup_pdn_cntrl_reg2; -#[doc = "GPIO_PUP_PDN_CNTRL_REG3 (rw) register accessor: an alias for `Reg`"] +#[doc = "GPIO_PUP_PDN_CNTRL_REG3 (rw) register accessor: GPIO Pull-up / Pull-down Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg3::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pup_pdn_cntrl_reg3`] +module"] pub type GPIO_PUP_PDN_CNTRL_REG3 = crate::Reg; #[doc = "GPIO Pull-up / Pull-down Register 3"] diff --git a/crates/bcm2837-lpa/src/gpio/extra_mux.rs b/crates/bcm2837-lpa/src/gpio/extra_mux.rs index a35ba4f..bac06d5 100644 --- a/crates/bcm2837-lpa/src/gpio/extra_mux.rs +++ b/crates/bcm2837-lpa/src/gpio/extra_mux.rs @@ -1,39 +1,7 @@ #[doc = "Register `EXTRA_MUX` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EXTRA_MUX` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SDIO` reader - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] pub type SDIO_R = crate::BitReader; #[doc = "Switch peripheral connection to undocumented SDIO pins used on Pi 4"] @@ -53,34 +21,37 @@ impl From for bool { impl SDIO_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> SDIO_A { + pub const fn variant(&self) -> SDIO_A { match self.bits { false => SDIO_A::SDHOST, true => SDIO_A::ARASAN, } } - #[doc = "Checks if the value of the field is `SDHOST`"] + #[doc = "Connect the newer SD host"] #[inline(always)] pub fn is_sdhost(&self) -> bool { *self == SDIO_A::SDHOST } - #[doc = "Checks if the value of the field is `ARASAN`"] + #[doc = "Connect Arasan SD/EMMC host"] #[inline(always)] pub fn is_arasan(&self) -> bool { *self == SDIO_A::ARASAN } } #[doc = "Field `SDIO` writer - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] -pub type SDIO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EXTRA_MUX_SPEC, SDIO_A, O>; -impl<'a, const O: u8> SDIO_W<'a, O> { +pub type SDIO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SDIO_A>; +impl<'a, REG, const O: u8> SDIO_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Connect the newer SD host"] #[inline(always)] - pub fn sdhost(self) -> &'a mut W { + pub fn sdhost(self) -> &'a mut crate::W { self.variant(SDIO_A::SDHOST) } #[doc = "Connect Arasan SD/EMMC host"] #[inline(always)] - pub fn arasan(self) -> &'a mut W { + pub fn arasan(self) -> &'a mut crate::W { self.variant(SDIO_A::ARASAN) } } @@ -91,32 +62,45 @@ impl R { SDIO_R::new(((self.bits >> 1) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXTRA_MUX") + .field("sdio", &format_args!("{}", self.sdio().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Switch peripheral connection to undocumented SDIO pins used on Pi 4"] #[inline(always)] #[must_use] - pub fn sdio(&mut self) -> SDIO_W<1> { + pub fn sdio(&mut self) -> SDIO_W { SDIO_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Undocumented multiplexing bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [extra_mux](index.html) module"] +#[doc = "Undocumented multiplexing bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extra_mux::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`extra_mux::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EXTRA_MUX_SPEC; impl crate::RegisterSpec for EXTRA_MUX_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [extra_mux::R](R) reader structure"] -impl crate::Readable for EXTRA_MUX_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [extra_mux::W](W) writer structure"] +#[doc = "`read()` method returns [`extra_mux::R`](R) reader structure"] +impl crate::Readable for EXTRA_MUX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`extra_mux::W`](W) writer structure"] impl crate::Writable for EXTRA_MUX_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpafen0.rs b/crates/bcm2837-lpa/src/gpio/gpafen0.rs index 5c84fd8..44bf785 100644 --- a/crates/bcm2837-lpa/src/gpio/gpafen0.rs +++ b/crates/bcm2837-lpa/src/gpio/gpafen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPAFEN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPAFEN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AFEN0` reader - Async falling enabled 0"] -pub type AFEN0_R = crate::BitReader; +pub type AFEN0_R = crate::BitReader; #[doc = "Field `AFEN0` writer - Async falling enabled 0"] -pub type AFEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN1` reader - Async falling enabled 1"] -pub type AFEN1_R = crate::BitReader; +pub type AFEN1_R = crate::BitReader; #[doc = "Field `AFEN1` writer - Async falling enabled 1"] -pub type AFEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN2` reader - Async falling enabled 2"] -pub type AFEN2_R = crate::BitReader; +pub type AFEN2_R = crate::BitReader; #[doc = "Field `AFEN2` writer - Async falling enabled 2"] -pub type AFEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN3` reader - Async falling enabled 3"] -pub type AFEN3_R = crate::BitReader; +pub type AFEN3_R = crate::BitReader; #[doc = "Field `AFEN3` writer - Async falling enabled 3"] -pub type AFEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN4` reader - Async falling enabled 4"] -pub type AFEN4_R = crate::BitReader; +pub type AFEN4_R = crate::BitReader; #[doc = "Field `AFEN4` writer - Async falling enabled 4"] -pub type AFEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN5` reader - Async falling enabled 5"] -pub type AFEN5_R = crate::BitReader; +pub type AFEN5_R = crate::BitReader; #[doc = "Field `AFEN5` writer - Async falling enabled 5"] -pub type AFEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN6` reader - Async falling enabled 6"] -pub type AFEN6_R = crate::BitReader; +pub type AFEN6_R = crate::BitReader; #[doc = "Field `AFEN6` writer - Async falling enabled 6"] -pub type AFEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN7` reader - Async falling enabled 7"] -pub type AFEN7_R = crate::BitReader; +pub type AFEN7_R = crate::BitReader; #[doc = "Field `AFEN7` writer - Async falling enabled 7"] -pub type AFEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN8` reader - Async falling enabled 8"] -pub type AFEN8_R = crate::BitReader; +pub type AFEN8_R = crate::BitReader; #[doc = "Field `AFEN8` writer - Async falling enabled 8"] -pub type AFEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN9` reader - Async falling enabled 9"] -pub type AFEN9_R = crate::BitReader; +pub type AFEN9_R = crate::BitReader; #[doc = "Field `AFEN9` writer - Async falling enabled 9"] -pub type AFEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN10` reader - Async falling enabled 10"] -pub type AFEN10_R = crate::BitReader; +pub type AFEN10_R = crate::BitReader; #[doc = "Field `AFEN10` writer - Async falling enabled 10"] -pub type AFEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN11` reader - Async falling enabled 11"] -pub type AFEN11_R = crate::BitReader; +pub type AFEN11_R = crate::BitReader; #[doc = "Field `AFEN11` writer - Async falling enabled 11"] -pub type AFEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN12` reader - Async falling enabled 12"] -pub type AFEN12_R = crate::BitReader; +pub type AFEN12_R = crate::BitReader; #[doc = "Field `AFEN12` writer - Async falling enabled 12"] -pub type AFEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN13` reader - Async falling enabled 13"] -pub type AFEN13_R = crate::BitReader; +pub type AFEN13_R = crate::BitReader; #[doc = "Field `AFEN13` writer - Async falling enabled 13"] -pub type AFEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN14` reader - Async falling enabled 14"] -pub type AFEN14_R = crate::BitReader; +pub type AFEN14_R = crate::BitReader; #[doc = "Field `AFEN14` writer - Async falling enabled 14"] -pub type AFEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN15` reader - Async falling enabled 15"] -pub type AFEN15_R = crate::BitReader; +pub type AFEN15_R = crate::BitReader; #[doc = "Field `AFEN15` writer - Async falling enabled 15"] -pub type AFEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN16` reader - Async falling enabled 16"] -pub type AFEN16_R = crate::BitReader; +pub type AFEN16_R = crate::BitReader; #[doc = "Field `AFEN16` writer - Async falling enabled 16"] -pub type AFEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN17` reader - Async falling enabled 17"] -pub type AFEN17_R = crate::BitReader; +pub type AFEN17_R = crate::BitReader; #[doc = "Field `AFEN17` writer - Async falling enabled 17"] -pub type AFEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN18` reader - Async falling enabled 18"] -pub type AFEN18_R = crate::BitReader; +pub type AFEN18_R = crate::BitReader; #[doc = "Field `AFEN18` writer - Async falling enabled 18"] -pub type AFEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN19` reader - Async falling enabled 19"] -pub type AFEN19_R = crate::BitReader; +pub type AFEN19_R = crate::BitReader; #[doc = "Field `AFEN19` writer - Async falling enabled 19"] -pub type AFEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN20` reader - Async falling enabled 20"] -pub type AFEN20_R = crate::BitReader; +pub type AFEN20_R = crate::BitReader; #[doc = "Field `AFEN20` writer - Async falling enabled 20"] -pub type AFEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN21` reader - Async falling enabled 21"] -pub type AFEN21_R = crate::BitReader; +pub type AFEN21_R = crate::BitReader; #[doc = "Field `AFEN21` writer - Async falling enabled 21"] -pub type AFEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN22` reader - Async falling enabled 22"] -pub type AFEN22_R = crate::BitReader; +pub type AFEN22_R = crate::BitReader; #[doc = "Field `AFEN22` writer - Async falling enabled 22"] -pub type AFEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN23` reader - Async falling enabled 23"] -pub type AFEN23_R = crate::BitReader; +pub type AFEN23_R = crate::BitReader; #[doc = "Field `AFEN23` writer - Async falling enabled 23"] -pub type AFEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN24` reader - Async falling enabled 24"] -pub type AFEN24_R = crate::BitReader; +pub type AFEN24_R = crate::BitReader; #[doc = "Field `AFEN24` writer - Async falling enabled 24"] -pub type AFEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN25` reader - Async falling enabled 25"] -pub type AFEN25_R = crate::BitReader; +pub type AFEN25_R = crate::BitReader; #[doc = "Field `AFEN25` writer - Async falling enabled 25"] -pub type AFEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN26` reader - Async falling enabled 26"] -pub type AFEN26_R = crate::BitReader; +pub type AFEN26_R = crate::BitReader; #[doc = "Field `AFEN26` writer - Async falling enabled 26"] -pub type AFEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN27` reader - Async falling enabled 27"] -pub type AFEN27_R = crate::BitReader; +pub type AFEN27_R = crate::BitReader; #[doc = "Field `AFEN27` writer - Async falling enabled 27"] -pub type AFEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN28` reader - Async falling enabled 28"] -pub type AFEN28_R = crate::BitReader; +pub type AFEN28_R = crate::BitReader; #[doc = "Field `AFEN28` writer - Async falling enabled 28"] -pub type AFEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN29` reader - Async falling enabled 29"] -pub type AFEN29_R = crate::BitReader; +pub type AFEN29_R = crate::BitReader; #[doc = "Field `AFEN29` writer - Async falling enabled 29"] -pub type AFEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN30` reader - Async falling enabled 30"] -pub type AFEN30_R = crate::BitReader; +pub type AFEN30_R = crate::BitReader; #[doc = "Field `AFEN30` writer - Async falling enabled 30"] -pub type AFEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN31` reader - Async falling enabled 31"] -pub type AFEN31_R = crate::BitReader; +pub type AFEN31_R = crate::BitReader; #[doc = "Field `AFEN31` writer - Async falling enabled 31"] -pub type AFEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN0_SPEC, bool, O>; +pub type AFEN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Async falling enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { AFEN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPAFEN0") + .field("afen0", &format_args!("{}", self.afen0().bit())) + .field("afen1", &format_args!("{}", self.afen1().bit())) + .field("afen2", &format_args!("{}", self.afen2().bit())) + .field("afen3", &format_args!("{}", self.afen3().bit())) + .field("afen4", &format_args!("{}", self.afen4().bit())) + .field("afen5", &format_args!("{}", self.afen5().bit())) + .field("afen6", &format_args!("{}", self.afen6().bit())) + .field("afen7", &format_args!("{}", self.afen7().bit())) + .field("afen8", &format_args!("{}", self.afen8().bit())) + .field("afen9", &format_args!("{}", self.afen9().bit())) + .field("afen10", &format_args!("{}", self.afen10().bit())) + .field("afen11", &format_args!("{}", self.afen11().bit())) + .field("afen12", &format_args!("{}", self.afen12().bit())) + .field("afen13", &format_args!("{}", self.afen13().bit())) + .field("afen14", &format_args!("{}", self.afen14().bit())) + .field("afen15", &format_args!("{}", self.afen15().bit())) + .field("afen16", &format_args!("{}", self.afen16().bit())) + .field("afen17", &format_args!("{}", self.afen17().bit())) + .field("afen18", &format_args!("{}", self.afen18().bit())) + .field("afen19", &format_args!("{}", self.afen19().bit())) + .field("afen20", &format_args!("{}", self.afen20().bit())) + .field("afen21", &format_args!("{}", self.afen21().bit())) + .field("afen22", &format_args!("{}", self.afen22().bit())) + .field("afen23", &format_args!("{}", self.afen23().bit())) + .field("afen24", &format_args!("{}", self.afen24().bit())) + .field("afen25", &format_args!("{}", self.afen25().bit())) + .field("afen26", &format_args!("{}", self.afen26().bit())) + .field("afen27", &format_args!("{}", self.afen27().bit())) + .field("afen28", &format_args!("{}", self.afen28().bit())) + .field("afen29", &format_args!("{}", self.afen29().bit())) + .field("afen30", &format_args!("{}", self.afen30().bit())) + .field("afen31", &format_args!("{}", self.afen31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Async falling enabled 0"] #[inline(always)] #[must_use] - pub fn afen0(&mut self) -> AFEN0_W<0> { + pub fn afen0(&mut self) -> AFEN0_W { AFEN0_W::new(self) } #[doc = "Bit 1 - Async falling enabled 1"] #[inline(always)] #[must_use] - pub fn afen1(&mut self) -> AFEN1_W<1> { + pub fn afen1(&mut self) -> AFEN1_W { AFEN1_W::new(self) } #[doc = "Bit 2 - Async falling enabled 2"] #[inline(always)] #[must_use] - pub fn afen2(&mut self) -> AFEN2_W<2> { + pub fn afen2(&mut self) -> AFEN2_W { AFEN2_W::new(self) } #[doc = "Bit 3 - Async falling enabled 3"] #[inline(always)] #[must_use] - pub fn afen3(&mut self) -> AFEN3_W<3> { + pub fn afen3(&mut self) -> AFEN3_W { AFEN3_W::new(self) } #[doc = "Bit 4 - Async falling enabled 4"] #[inline(always)] #[must_use] - pub fn afen4(&mut self) -> AFEN4_W<4> { + pub fn afen4(&mut self) -> AFEN4_W { AFEN4_W::new(self) } #[doc = "Bit 5 - Async falling enabled 5"] #[inline(always)] #[must_use] - pub fn afen5(&mut self) -> AFEN5_W<5> { + pub fn afen5(&mut self) -> AFEN5_W { AFEN5_W::new(self) } #[doc = "Bit 6 - Async falling enabled 6"] #[inline(always)] #[must_use] - pub fn afen6(&mut self) -> AFEN6_W<6> { + pub fn afen6(&mut self) -> AFEN6_W { AFEN6_W::new(self) } #[doc = "Bit 7 - Async falling enabled 7"] #[inline(always)] #[must_use] - pub fn afen7(&mut self) -> AFEN7_W<7> { + pub fn afen7(&mut self) -> AFEN7_W { AFEN7_W::new(self) } #[doc = "Bit 8 - Async falling enabled 8"] #[inline(always)] #[must_use] - pub fn afen8(&mut self) -> AFEN8_W<8> { + pub fn afen8(&mut self) -> AFEN8_W { AFEN8_W::new(self) } #[doc = "Bit 9 - Async falling enabled 9"] #[inline(always)] #[must_use] - pub fn afen9(&mut self) -> AFEN9_W<9> { + pub fn afen9(&mut self) -> AFEN9_W { AFEN9_W::new(self) } #[doc = "Bit 10 - Async falling enabled 10"] #[inline(always)] #[must_use] - pub fn afen10(&mut self) -> AFEN10_W<10> { + pub fn afen10(&mut self) -> AFEN10_W { AFEN10_W::new(self) } #[doc = "Bit 11 - Async falling enabled 11"] #[inline(always)] #[must_use] - pub fn afen11(&mut self) -> AFEN11_W<11> { + pub fn afen11(&mut self) -> AFEN11_W { AFEN11_W::new(self) } #[doc = "Bit 12 - Async falling enabled 12"] #[inline(always)] #[must_use] - pub fn afen12(&mut self) -> AFEN12_W<12> { + pub fn afen12(&mut self) -> AFEN12_W { AFEN12_W::new(self) } #[doc = "Bit 13 - Async falling enabled 13"] #[inline(always)] #[must_use] - pub fn afen13(&mut self) -> AFEN13_W<13> { + pub fn afen13(&mut self) -> AFEN13_W { AFEN13_W::new(self) } #[doc = "Bit 14 - Async falling enabled 14"] #[inline(always)] #[must_use] - pub fn afen14(&mut self) -> AFEN14_W<14> { + pub fn afen14(&mut self) -> AFEN14_W { AFEN14_W::new(self) } #[doc = "Bit 15 - Async falling enabled 15"] #[inline(always)] #[must_use] - pub fn afen15(&mut self) -> AFEN15_W<15> { + pub fn afen15(&mut self) -> AFEN15_W { AFEN15_W::new(self) } #[doc = "Bit 16 - Async falling enabled 16"] #[inline(always)] #[must_use] - pub fn afen16(&mut self) -> AFEN16_W<16> { + pub fn afen16(&mut self) -> AFEN16_W { AFEN16_W::new(self) } #[doc = "Bit 17 - Async falling enabled 17"] #[inline(always)] #[must_use] - pub fn afen17(&mut self) -> AFEN17_W<17> { + pub fn afen17(&mut self) -> AFEN17_W { AFEN17_W::new(self) } #[doc = "Bit 18 - Async falling enabled 18"] #[inline(always)] #[must_use] - pub fn afen18(&mut self) -> AFEN18_W<18> { + pub fn afen18(&mut self) -> AFEN18_W { AFEN18_W::new(self) } #[doc = "Bit 19 - Async falling enabled 19"] #[inline(always)] #[must_use] - pub fn afen19(&mut self) -> AFEN19_W<19> { + pub fn afen19(&mut self) -> AFEN19_W { AFEN19_W::new(self) } #[doc = "Bit 20 - Async falling enabled 20"] #[inline(always)] #[must_use] - pub fn afen20(&mut self) -> AFEN20_W<20> { + pub fn afen20(&mut self) -> AFEN20_W { AFEN20_W::new(self) } #[doc = "Bit 21 - Async falling enabled 21"] #[inline(always)] #[must_use] - pub fn afen21(&mut self) -> AFEN21_W<21> { + pub fn afen21(&mut self) -> AFEN21_W { AFEN21_W::new(self) } #[doc = "Bit 22 - Async falling enabled 22"] #[inline(always)] #[must_use] - pub fn afen22(&mut self) -> AFEN22_W<22> { + pub fn afen22(&mut self) -> AFEN22_W { AFEN22_W::new(self) } #[doc = "Bit 23 - Async falling enabled 23"] #[inline(always)] #[must_use] - pub fn afen23(&mut self) -> AFEN23_W<23> { + pub fn afen23(&mut self) -> AFEN23_W { AFEN23_W::new(self) } #[doc = "Bit 24 - Async falling enabled 24"] #[inline(always)] #[must_use] - pub fn afen24(&mut self) -> AFEN24_W<24> { + pub fn afen24(&mut self) -> AFEN24_W { AFEN24_W::new(self) } #[doc = "Bit 25 - Async falling enabled 25"] #[inline(always)] #[must_use] - pub fn afen25(&mut self) -> AFEN25_W<25> { + pub fn afen25(&mut self) -> AFEN25_W { AFEN25_W::new(self) } #[doc = "Bit 26 - Async falling enabled 26"] #[inline(always)] #[must_use] - pub fn afen26(&mut self) -> AFEN26_W<26> { + pub fn afen26(&mut self) -> AFEN26_W { AFEN26_W::new(self) } #[doc = "Bit 27 - Async falling enabled 27"] #[inline(always)] #[must_use] - pub fn afen27(&mut self) -> AFEN27_W<27> { + pub fn afen27(&mut self) -> AFEN27_W { AFEN27_W::new(self) } #[doc = "Bit 28 - Async falling enabled 28"] #[inline(always)] #[must_use] - pub fn afen28(&mut self) -> AFEN28_W<28> { + pub fn afen28(&mut self) -> AFEN28_W { AFEN28_W::new(self) } #[doc = "Bit 29 - Async falling enabled 29"] #[inline(always)] #[must_use] - pub fn afen29(&mut self) -> AFEN29_W<29> { + pub fn afen29(&mut self) -> AFEN29_W { AFEN29_W::new(self) } #[doc = "Bit 30 - Async falling enabled 30"] #[inline(always)] #[must_use] - pub fn afen30(&mut self) -> AFEN30_W<30> { + pub fn afen30(&mut self) -> AFEN30_W { AFEN30_W::new(self) } #[doc = "Bit 31 - Async falling enabled 31"] #[inline(always)] #[must_use] - pub fn afen31(&mut self) -> AFEN31_W<31> { + pub fn afen31(&mut self) -> AFEN31_W { AFEN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Async. Falling Edge Detect 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpafen0](index.html) module"] +#[doc = "GPIO Pin Async. Falling Edge Detect 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpafen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpafen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPAFEN0_SPEC; impl crate::RegisterSpec for GPAFEN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpafen0::R](R) reader structure"] -impl crate::Readable for GPAFEN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpafen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpafen0::R`](R) reader structure"] +impl crate::Readable for GPAFEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpafen0::W`](W) writer structure"] impl crate::Writable for GPAFEN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpafen1.rs b/crates/bcm2837-lpa/src/gpio/gpafen1.rs index a87edeb..83ed52d 100644 --- a/crates/bcm2837-lpa/src/gpio/gpafen1.rs +++ b/crates/bcm2837-lpa/src/gpio/gpafen1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPAFEN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPAFEN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AFEN32` reader - Async falling enabled 32"] -pub type AFEN32_R = crate::BitReader; +pub type AFEN32_R = crate::BitReader; #[doc = "Field `AFEN32` writer - Async falling enabled 32"] -pub type AFEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN33` reader - Async falling enabled 33"] -pub type AFEN33_R = crate::BitReader; +pub type AFEN33_R = crate::BitReader; #[doc = "Field `AFEN33` writer - Async falling enabled 33"] -pub type AFEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN34` reader - Async falling enabled 34"] -pub type AFEN34_R = crate::BitReader; +pub type AFEN34_R = crate::BitReader; #[doc = "Field `AFEN34` writer - Async falling enabled 34"] -pub type AFEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN35` reader - Async falling enabled 35"] -pub type AFEN35_R = crate::BitReader; +pub type AFEN35_R = crate::BitReader; #[doc = "Field `AFEN35` writer - Async falling enabled 35"] -pub type AFEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN36` reader - Async falling enabled 36"] -pub type AFEN36_R = crate::BitReader; +pub type AFEN36_R = crate::BitReader; #[doc = "Field `AFEN36` writer - Async falling enabled 36"] -pub type AFEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN37` reader - Async falling enabled 37"] -pub type AFEN37_R = crate::BitReader; +pub type AFEN37_R = crate::BitReader; #[doc = "Field `AFEN37` writer - Async falling enabled 37"] -pub type AFEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN38` reader - Async falling enabled 38"] -pub type AFEN38_R = crate::BitReader; +pub type AFEN38_R = crate::BitReader; #[doc = "Field `AFEN38` writer - Async falling enabled 38"] -pub type AFEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN39` reader - Async falling enabled 39"] -pub type AFEN39_R = crate::BitReader; +pub type AFEN39_R = crate::BitReader; #[doc = "Field `AFEN39` writer - Async falling enabled 39"] -pub type AFEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN40` reader - Async falling enabled 40"] -pub type AFEN40_R = crate::BitReader; +pub type AFEN40_R = crate::BitReader; #[doc = "Field `AFEN40` writer - Async falling enabled 40"] -pub type AFEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN41` reader - Async falling enabled 41"] -pub type AFEN41_R = crate::BitReader; +pub type AFEN41_R = crate::BitReader; #[doc = "Field `AFEN41` writer - Async falling enabled 41"] -pub type AFEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN42` reader - Async falling enabled 42"] -pub type AFEN42_R = crate::BitReader; +pub type AFEN42_R = crate::BitReader; #[doc = "Field `AFEN42` writer - Async falling enabled 42"] -pub type AFEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN43` reader - Async falling enabled 43"] -pub type AFEN43_R = crate::BitReader; +pub type AFEN43_R = crate::BitReader; #[doc = "Field `AFEN43` writer - Async falling enabled 43"] -pub type AFEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN44` reader - Async falling enabled 44"] -pub type AFEN44_R = crate::BitReader; +pub type AFEN44_R = crate::BitReader; #[doc = "Field `AFEN44` writer - Async falling enabled 44"] -pub type AFEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN45` reader - Async falling enabled 45"] -pub type AFEN45_R = crate::BitReader; +pub type AFEN45_R = crate::BitReader; #[doc = "Field `AFEN45` writer - Async falling enabled 45"] -pub type AFEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN46` reader - Async falling enabled 46"] -pub type AFEN46_R = crate::BitReader; +pub type AFEN46_R = crate::BitReader; #[doc = "Field `AFEN46` writer - Async falling enabled 46"] -pub type AFEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN47` reader - Async falling enabled 47"] -pub type AFEN47_R = crate::BitReader; +pub type AFEN47_R = crate::BitReader; #[doc = "Field `AFEN47` writer - Async falling enabled 47"] -pub type AFEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN48` reader - Async falling enabled 48"] -pub type AFEN48_R = crate::BitReader; +pub type AFEN48_R = crate::BitReader; #[doc = "Field `AFEN48` writer - Async falling enabled 48"] -pub type AFEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN49` reader - Async falling enabled 49"] -pub type AFEN49_R = crate::BitReader; +pub type AFEN49_R = crate::BitReader; #[doc = "Field `AFEN49` writer - Async falling enabled 49"] -pub type AFEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN50` reader - Async falling enabled 50"] -pub type AFEN50_R = crate::BitReader; +pub type AFEN50_R = crate::BitReader; #[doc = "Field `AFEN50` writer - Async falling enabled 50"] -pub type AFEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN51` reader - Async falling enabled 51"] -pub type AFEN51_R = crate::BitReader; +pub type AFEN51_R = crate::BitReader; #[doc = "Field `AFEN51` writer - Async falling enabled 51"] -pub type AFEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN52` reader - Async falling enabled 52"] -pub type AFEN52_R = crate::BitReader; +pub type AFEN52_R = crate::BitReader; #[doc = "Field `AFEN52` writer - Async falling enabled 52"] -pub type AFEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AFEN53` reader - Async falling enabled 53"] -pub type AFEN53_R = crate::BitReader; +pub type AFEN53_R = crate::BitReader; #[doc = "Field `AFEN53` writer - Async falling enabled 53"] -pub type AFEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAFEN1_SPEC, bool, O>; +pub type AFEN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Async falling enabled 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { AFEN53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPAFEN1") + .field("afen32", &format_args!("{}", self.afen32().bit())) + .field("afen33", &format_args!("{}", self.afen33().bit())) + .field("afen34", &format_args!("{}", self.afen34().bit())) + .field("afen35", &format_args!("{}", self.afen35().bit())) + .field("afen36", &format_args!("{}", self.afen36().bit())) + .field("afen37", &format_args!("{}", self.afen37().bit())) + .field("afen38", &format_args!("{}", self.afen38().bit())) + .field("afen39", &format_args!("{}", self.afen39().bit())) + .field("afen40", &format_args!("{}", self.afen40().bit())) + .field("afen41", &format_args!("{}", self.afen41().bit())) + .field("afen42", &format_args!("{}", self.afen42().bit())) + .field("afen43", &format_args!("{}", self.afen43().bit())) + .field("afen44", &format_args!("{}", self.afen44().bit())) + .field("afen45", &format_args!("{}", self.afen45().bit())) + .field("afen46", &format_args!("{}", self.afen46().bit())) + .field("afen47", &format_args!("{}", self.afen47().bit())) + .field("afen48", &format_args!("{}", self.afen48().bit())) + .field("afen49", &format_args!("{}", self.afen49().bit())) + .field("afen50", &format_args!("{}", self.afen50().bit())) + .field("afen51", &format_args!("{}", self.afen51().bit())) + .field("afen52", &format_args!("{}", self.afen52().bit())) + .field("afen53", &format_args!("{}", self.afen53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Async falling enabled 32"] #[inline(always)] #[must_use] - pub fn afen32(&mut self) -> AFEN32_W<0> { + pub fn afen32(&mut self) -> AFEN32_W { AFEN32_W::new(self) } #[doc = "Bit 1 - Async falling enabled 33"] #[inline(always)] #[must_use] - pub fn afen33(&mut self) -> AFEN33_W<1> { + pub fn afen33(&mut self) -> AFEN33_W { AFEN33_W::new(self) } #[doc = "Bit 2 - Async falling enabled 34"] #[inline(always)] #[must_use] - pub fn afen34(&mut self) -> AFEN34_W<2> { + pub fn afen34(&mut self) -> AFEN34_W { AFEN34_W::new(self) } #[doc = "Bit 3 - Async falling enabled 35"] #[inline(always)] #[must_use] - pub fn afen35(&mut self) -> AFEN35_W<3> { + pub fn afen35(&mut self) -> AFEN35_W { AFEN35_W::new(self) } #[doc = "Bit 4 - Async falling enabled 36"] #[inline(always)] #[must_use] - pub fn afen36(&mut self) -> AFEN36_W<4> { + pub fn afen36(&mut self) -> AFEN36_W { AFEN36_W::new(self) } #[doc = "Bit 5 - Async falling enabled 37"] #[inline(always)] #[must_use] - pub fn afen37(&mut self) -> AFEN37_W<5> { + pub fn afen37(&mut self) -> AFEN37_W { AFEN37_W::new(self) } #[doc = "Bit 6 - Async falling enabled 38"] #[inline(always)] #[must_use] - pub fn afen38(&mut self) -> AFEN38_W<6> { + pub fn afen38(&mut self) -> AFEN38_W { AFEN38_W::new(self) } #[doc = "Bit 7 - Async falling enabled 39"] #[inline(always)] #[must_use] - pub fn afen39(&mut self) -> AFEN39_W<7> { + pub fn afen39(&mut self) -> AFEN39_W { AFEN39_W::new(self) } #[doc = "Bit 8 - Async falling enabled 40"] #[inline(always)] #[must_use] - pub fn afen40(&mut self) -> AFEN40_W<8> { + pub fn afen40(&mut self) -> AFEN40_W { AFEN40_W::new(self) } #[doc = "Bit 9 - Async falling enabled 41"] #[inline(always)] #[must_use] - pub fn afen41(&mut self) -> AFEN41_W<9> { + pub fn afen41(&mut self) -> AFEN41_W { AFEN41_W::new(self) } #[doc = "Bit 10 - Async falling enabled 42"] #[inline(always)] #[must_use] - pub fn afen42(&mut self) -> AFEN42_W<10> { + pub fn afen42(&mut self) -> AFEN42_W { AFEN42_W::new(self) } #[doc = "Bit 11 - Async falling enabled 43"] #[inline(always)] #[must_use] - pub fn afen43(&mut self) -> AFEN43_W<11> { + pub fn afen43(&mut self) -> AFEN43_W { AFEN43_W::new(self) } #[doc = "Bit 12 - Async falling enabled 44"] #[inline(always)] #[must_use] - pub fn afen44(&mut self) -> AFEN44_W<12> { + pub fn afen44(&mut self) -> AFEN44_W { AFEN44_W::new(self) } #[doc = "Bit 13 - Async falling enabled 45"] #[inline(always)] #[must_use] - pub fn afen45(&mut self) -> AFEN45_W<13> { + pub fn afen45(&mut self) -> AFEN45_W { AFEN45_W::new(self) } #[doc = "Bit 14 - Async falling enabled 46"] #[inline(always)] #[must_use] - pub fn afen46(&mut self) -> AFEN46_W<14> { + pub fn afen46(&mut self) -> AFEN46_W { AFEN46_W::new(self) } #[doc = "Bit 15 - Async falling enabled 47"] #[inline(always)] #[must_use] - pub fn afen47(&mut self) -> AFEN47_W<15> { + pub fn afen47(&mut self) -> AFEN47_W { AFEN47_W::new(self) } #[doc = "Bit 16 - Async falling enabled 48"] #[inline(always)] #[must_use] - pub fn afen48(&mut self) -> AFEN48_W<16> { + pub fn afen48(&mut self) -> AFEN48_W { AFEN48_W::new(self) } #[doc = "Bit 17 - Async falling enabled 49"] #[inline(always)] #[must_use] - pub fn afen49(&mut self) -> AFEN49_W<17> { + pub fn afen49(&mut self) -> AFEN49_W { AFEN49_W::new(self) } #[doc = "Bit 18 - Async falling enabled 50"] #[inline(always)] #[must_use] - pub fn afen50(&mut self) -> AFEN50_W<18> { + pub fn afen50(&mut self) -> AFEN50_W { AFEN50_W::new(self) } #[doc = "Bit 19 - Async falling enabled 51"] #[inline(always)] #[must_use] - pub fn afen51(&mut self) -> AFEN51_W<19> { + pub fn afen51(&mut self) -> AFEN51_W { AFEN51_W::new(self) } #[doc = "Bit 20 - Async falling enabled 52"] #[inline(always)] #[must_use] - pub fn afen52(&mut self) -> AFEN52_W<20> { + pub fn afen52(&mut self) -> AFEN52_W { AFEN52_W::new(self) } #[doc = "Bit 21 - Async falling enabled 53"] #[inline(always)] #[must_use] - pub fn afen53(&mut self) -> AFEN53_W<21> { + pub fn afen53(&mut self) -> AFEN53_W { AFEN53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Async. Falling Edge Detect 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpafen1](index.html) module"] +#[doc = "GPIO Pin Async. Falling Edge Detect 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpafen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpafen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPAFEN1_SPEC; impl crate::RegisterSpec for GPAFEN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpafen1::R](R) reader structure"] -impl crate::Readable for GPAFEN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpafen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpafen1::R`](R) reader structure"] +impl crate::Readable for GPAFEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpafen1::W`](W) writer structure"] impl crate::Writable for GPAFEN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gparen0.rs b/crates/bcm2837-lpa/src/gpio/gparen0.rs index f4ef746..ac719d0 100644 --- a/crates/bcm2837-lpa/src/gpio/gparen0.rs +++ b/crates/bcm2837-lpa/src/gpio/gparen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPAREN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPAREN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AREN0` reader - Async rising enabled 0"] -pub type AREN0_R = crate::BitReader; +pub type AREN0_R = crate::BitReader; #[doc = "Field `AREN0` writer - Async rising enabled 0"] -pub type AREN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN1` reader - Async rising enabled 1"] -pub type AREN1_R = crate::BitReader; +pub type AREN1_R = crate::BitReader; #[doc = "Field `AREN1` writer - Async rising enabled 1"] -pub type AREN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN2` reader - Async rising enabled 2"] -pub type AREN2_R = crate::BitReader; +pub type AREN2_R = crate::BitReader; #[doc = "Field `AREN2` writer - Async rising enabled 2"] -pub type AREN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN3` reader - Async rising enabled 3"] -pub type AREN3_R = crate::BitReader; +pub type AREN3_R = crate::BitReader; #[doc = "Field `AREN3` writer - Async rising enabled 3"] -pub type AREN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN4` reader - Async rising enabled 4"] -pub type AREN4_R = crate::BitReader; +pub type AREN4_R = crate::BitReader; #[doc = "Field `AREN4` writer - Async rising enabled 4"] -pub type AREN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN5` reader - Async rising enabled 5"] -pub type AREN5_R = crate::BitReader; +pub type AREN5_R = crate::BitReader; #[doc = "Field `AREN5` writer - Async rising enabled 5"] -pub type AREN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN6` reader - Async rising enabled 6"] -pub type AREN6_R = crate::BitReader; +pub type AREN6_R = crate::BitReader; #[doc = "Field `AREN6` writer - Async rising enabled 6"] -pub type AREN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN7` reader - Async rising enabled 7"] -pub type AREN7_R = crate::BitReader; +pub type AREN7_R = crate::BitReader; #[doc = "Field `AREN7` writer - Async rising enabled 7"] -pub type AREN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN8` reader - Async rising enabled 8"] -pub type AREN8_R = crate::BitReader; +pub type AREN8_R = crate::BitReader; #[doc = "Field `AREN8` writer - Async rising enabled 8"] -pub type AREN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN9` reader - Async rising enabled 9"] -pub type AREN9_R = crate::BitReader; +pub type AREN9_R = crate::BitReader; #[doc = "Field `AREN9` writer - Async rising enabled 9"] -pub type AREN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN10` reader - Async rising enabled 10"] -pub type AREN10_R = crate::BitReader; +pub type AREN10_R = crate::BitReader; #[doc = "Field `AREN10` writer - Async rising enabled 10"] -pub type AREN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN11` reader - Async rising enabled 11"] -pub type AREN11_R = crate::BitReader; +pub type AREN11_R = crate::BitReader; #[doc = "Field `AREN11` writer - Async rising enabled 11"] -pub type AREN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN12` reader - Async rising enabled 12"] -pub type AREN12_R = crate::BitReader; +pub type AREN12_R = crate::BitReader; #[doc = "Field `AREN12` writer - Async rising enabled 12"] -pub type AREN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN13` reader - Async rising enabled 13"] -pub type AREN13_R = crate::BitReader; +pub type AREN13_R = crate::BitReader; #[doc = "Field `AREN13` writer - Async rising enabled 13"] -pub type AREN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN14` reader - Async rising enabled 14"] -pub type AREN14_R = crate::BitReader; +pub type AREN14_R = crate::BitReader; #[doc = "Field `AREN14` writer - Async rising enabled 14"] -pub type AREN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN15` reader - Async rising enabled 15"] -pub type AREN15_R = crate::BitReader; +pub type AREN15_R = crate::BitReader; #[doc = "Field `AREN15` writer - Async rising enabled 15"] -pub type AREN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN16` reader - Async rising enabled 16"] -pub type AREN16_R = crate::BitReader; +pub type AREN16_R = crate::BitReader; #[doc = "Field `AREN16` writer - Async rising enabled 16"] -pub type AREN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN17` reader - Async rising enabled 17"] -pub type AREN17_R = crate::BitReader; +pub type AREN17_R = crate::BitReader; #[doc = "Field `AREN17` writer - Async rising enabled 17"] -pub type AREN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN18` reader - Async rising enabled 18"] -pub type AREN18_R = crate::BitReader; +pub type AREN18_R = crate::BitReader; #[doc = "Field `AREN18` writer - Async rising enabled 18"] -pub type AREN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN19` reader - Async rising enabled 19"] -pub type AREN19_R = crate::BitReader; +pub type AREN19_R = crate::BitReader; #[doc = "Field `AREN19` writer - Async rising enabled 19"] -pub type AREN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN20` reader - Async rising enabled 20"] -pub type AREN20_R = crate::BitReader; +pub type AREN20_R = crate::BitReader; #[doc = "Field `AREN20` writer - Async rising enabled 20"] -pub type AREN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN21` reader - Async rising enabled 21"] -pub type AREN21_R = crate::BitReader; +pub type AREN21_R = crate::BitReader; #[doc = "Field `AREN21` writer - Async rising enabled 21"] -pub type AREN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN22` reader - Async rising enabled 22"] -pub type AREN22_R = crate::BitReader; +pub type AREN22_R = crate::BitReader; #[doc = "Field `AREN22` writer - Async rising enabled 22"] -pub type AREN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN23` reader - Async rising enabled 23"] -pub type AREN23_R = crate::BitReader; +pub type AREN23_R = crate::BitReader; #[doc = "Field `AREN23` writer - Async rising enabled 23"] -pub type AREN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN24` reader - Async rising enabled 24"] -pub type AREN24_R = crate::BitReader; +pub type AREN24_R = crate::BitReader; #[doc = "Field `AREN24` writer - Async rising enabled 24"] -pub type AREN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN25` reader - Async rising enabled 25"] -pub type AREN25_R = crate::BitReader; +pub type AREN25_R = crate::BitReader; #[doc = "Field `AREN25` writer - Async rising enabled 25"] -pub type AREN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN26` reader - Async rising enabled 26"] -pub type AREN26_R = crate::BitReader; +pub type AREN26_R = crate::BitReader; #[doc = "Field `AREN26` writer - Async rising enabled 26"] -pub type AREN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN27` reader - Async rising enabled 27"] -pub type AREN27_R = crate::BitReader; +pub type AREN27_R = crate::BitReader; #[doc = "Field `AREN27` writer - Async rising enabled 27"] -pub type AREN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN28` reader - Async rising enabled 28"] -pub type AREN28_R = crate::BitReader; +pub type AREN28_R = crate::BitReader; #[doc = "Field `AREN28` writer - Async rising enabled 28"] -pub type AREN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN29` reader - Async rising enabled 29"] -pub type AREN29_R = crate::BitReader; +pub type AREN29_R = crate::BitReader; #[doc = "Field `AREN29` writer - Async rising enabled 29"] -pub type AREN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN30` reader - Async rising enabled 30"] -pub type AREN30_R = crate::BitReader; +pub type AREN30_R = crate::BitReader; #[doc = "Field `AREN30` writer - Async rising enabled 30"] -pub type AREN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN31` reader - Async rising enabled 31"] -pub type AREN31_R = crate::BitReader; +pub type AREN31_R = crate::BitReader; #[doc = "Field `AREN31` writer - Async rising enabled 31"] -pub type AREN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN0_SPEC, bool, O>; +pub type AREN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Async rising enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { AREN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPAREN0") + .field("aren0", &format_args!("{}", self.aren0().bit())) + .field("aren1", &format_args!("{}", self.aren1().bit())) + .field("aren2", &format_args!("{}", self.aren2().bit())) + .field("aren3", &format_args!("{}", self.aren3().bit())) + .field("aren4", &format_args!("{}", self.aren4().bit())) + .field("aren5", &format_args!("{}", self.aren5().bit())) + .field("aren6", &format_args!("{}", self.aren6().bit())) + .field("aren7", &format_args!("{}", self.aren7().bit())) + .field("aren8", &format_args!("{}", self.aren8().bit())) + .field("aren9", &format_args!("{}", self.aren9().bit())) + .field("aren10", &format_args!("{}", self.aren10().bit())) + .field("aren11", &format_args!("{}", self.aren11().bit())) + .field("aren12", &format_args!("{}", self.aren12().bit())) + .field("aren13", &format_args!("{}", self.aren13().bit())) + .field("aren14", &format_args!("{}", self.aren14().bit())) + .field("aren15", &format_args!("{}", self.aren15().bit())) + .field("aren16", &format_args!("{}", self.aren16().bit())) + .field("aren17", &format_args!("{}", self.aren17().bit())) + .field("aren18", &format_args!("{}", self.aren18().bit())) + .field("aren19", &format_args!("{}", self.aren19().bit())) + .field("aren20", &format_args!("{}", self.aren20().bit())) + .field("aren21", &format_args!("{}", self.aren21().bit())) + .field("aren22", &format_args!("{}", self.aren22().bit())) + .field("aren23", &format_args!("{}", self.aren23().bit())) + .field("aren24", &format_args!("{}", self.aren24().bit())) + .field("aren25", &format_args!("{}", self.aren25().bit())) + .field("aren26", &format_args!("{}", self.aren26().bit())) + .field("aren27", &format_args!("{}", self.aren27().bit())) + .field("aren28", &format_args!("{}", self.aren28().bit())) + .field("aren29", &format_args!("{}", self.aren29().bit())) + .field("aren30", &format_args!("{}", self.aren30().bit())) + .field("aren31", &format_args!("{}", self.aren31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Async rising enabled 0"] #[inline(always)] #[must_use] - pub fn aren0(&mut self) -> AREN0_W<0> { + pub fn aren0(&mut self) -> AREN0_W { AREN0_W::new(self) } #[doc = "Bit 1 - Async rising enabled 1"] #[inline(always)] #[must_use] - pub fn aren1(&mut self) -> AREN1_W<1> { + pub fn aren1(&mut self) -> AREN1_W { AREN1_W::new(self) } #[doc = "Bit 2 - Async rising enabled 2"] #[inline(always)] #[must_use] - pub fn aren2(&mut self) -> AREN2_W<2> { + pub fn aren2(&mut self) -> AREN2_W { AREN2_W::new(self) } #[doc = "Bit 3 - Async rising enabled 3"] #[inline(always)] #[must_use] - pub fn aren3(&mut self) -> AREN3_W<3> { + pub fn aren3(&mut self) -> AREN3_W { AREN3_W::new(self) } #[doc = "Bit 4 - Async rising enabled 4"] #[inline(always)] #[must_use] - pub fn aren4(&mut self) -> AREN4_W<4> { + pub fn aren4(&mut self) -> AREN4_W { AREN4_W::new(self) } #[doc = "Bit 5 - Async rising enabled 5"] #[inline(always)] #[must_use] - pub fn aren5(&mut self) -> AREN5_W<5> { + pub fn aren5(&mut self) -> AREN5_W { AREN5_W::new(self) } #[doc = "Bit 6 - Async rising enabled 6"] #[inline(always)] #[must_use] - pub fn aren6(&mut self) -> AREN6_W<6> { + pub fn aren6(&mut self) -> AREN6_W { AREN6_W::new(self) } #[doc = "Bit 7 - Async rising enabled 7"] #[inline(always)] #[must_use] - pub fn aren7(&mut self) -> AREN7_W<7> { + pub fn aren7(&mut self) -> AREN7_W { AREN7_W::new(self) } #[doc = "Bit 8 - Async rising enabled 8"] #[inline(always)] #[must_use] - pub fn aren8(&mut self) -> AREN8_W<8> { + pub fn aren8(&mut self) -> AREN8_W { AREN8_W::new(self) } #[doc = "Bit 9 - Async rising enabled 9"] #[inline(always)] #[must_use] - pub fn aren9(&mut self) -> AREN9_W<9> { + pub fn aren9(&mut self) -> AREN9_W { AREN9_W::new(self) } #[doc = "Bit 10 - Async rising enabled 10"] #[inline(always)] #[must_use] - pub fn aren10(&mut self) -> AREN10_W<10> { + pub fn aren10(&mut self) -> AREN10_W { AREN10_W::new(self) } #[doc = "Bit 11 - Async rising enabled 11"] #[inline(always)] #[must_use] - pub fn aren11(&mut self) -> AREN11_W<11> { + pub fn aren11(&mut self) -> AREN11_W { AREN11_W::new(self) } #[doc = "Bit 12 - Async rising enabled 12"] #[inline(always)] #[must_use] - pub fn aren12(&mut self) -> AREN12_W<12> { + pub fn aren12(&mut self) -> AREN12_W { AREN12_W::new(self) } #[doc = "Bit 13 - Async rising enabled 13"] #[inline(always)] #[must_use] - pub fn aren13(&mut self) -> AREN13_W<13> { + pub fn aren13(&mut self) -> AREN13_W { AREN13_W::new(self) } #[doc = "Bit 14 - Async rising enabled 14"] #[inline(always)] #[must_use] - pub fn aren14(&mut self) -> AREN14_W<14> { + pub fn aren14(&mut self) -> AREN14_W { AREN14_W::new(self) } #[doc = "Bit 15 - Async rising enabled 15"] #[inline(always)] #[must_use] - pub fn aren15(&mut self) -> AREN15_W<15> { + pub fn aren15(&mut self) -> AREN15_W { AREN15_W::new(self) } #[doc = "Bit 16 - Async rising enabled 16"] #[inline(always)] #[must_use] - pub fn aren16(&mut self) -> AREN16_W<16> { + pub fn aren16(&mut self) -> AREN16_W { AREN16_W::new(self) } #[doc = "Bit 17 - Async rising enabled 17"] #[inline(always)] #[must_use] - pub fn aren17(&mut self) -> AREN17_W<17> { + pub fn aren17(&mut self) -> AREN17_W { AREN17_W::new(self) } #[doc = "Bit 18 - Async rising enabled 18"] #[inline(always)] #[must_use] - pub fn aren18(&mut self) -> AREN18_W<18> { + pub fn aren18(&mut self) -> AREN18_W { AREN18_W::new(self) } #[doc = "Bit 19 - Async rising enabled 19"] #[inline(always)] #[must_use] - pub fn aren19(&mut self) -> AREN19_W<19> { + pub fn aren19(&mut self) -> AREN19_W { AREN19_W::new(self) } #[doc = "Bit 20 - Async rising enabled 20"] #[inline(always)] #[must_use] - pub fn aren20(&mut self) -> AREN20_W<20> { + pub fn aren20(&mut self) -> AREN20_W { AREN20_W::new(self) } #[doc = "Bit 21 - Async rising enabled 21"] #[inline(always)] #[must_use] - pub fn aren21(&mut self) -> AREN21_W<21> { + pub fn aren21(&mut self) -> AREN21_W { AREN21_W::new(self) } #[doc = "Bit 22 - Async rising enabled 22"] #[inline(always)] #[must_use] - pub fn aren22(&mut self) -> AREN22_W<22> { + pub fn aren22(&mut self) -> AREN22_W { AREN22_W::new(self) } #[doc = "Bit 23 - Async rising enabled 23"] #[inline(always)] #[must_use] - pub fn aren23(&mut self) -> AREN23_W<23> { + pub fn aren23(&mut self) -> AREN23_W { AREN23_W::new(self) } #[doc = "Bit 24 - Async rising enabled 24"] #[inline(always)] #[must_use] - pub fn aren24(&mut self) -> AREN24_W<24> { + pub fn aren24(&mut self) -> AREN24_W { AREN24_W::new(self) } #[doc = "Bit 25 - Async rising enabled 25"] #[inline(always)] #[must_use] - pub fn aren25(&mut self) -> AREN25_W<25> { + pub fn aren25(&mut self) -> AREN25_W { AREN25_W::new(self) } #[doc = "Bit 26 - Async rising enabled 26"] #[inline(always)] #[must_use] - pub fn aren26(&mut self) -> AREN26_W<26> { + pub fn aren26(&mut self) -> AREN26_W { AREN26_W::new(self) } #[doc = "Bit 27 - Async rising enabled 27"] #[inline(always)] #[must_use] - pub fn aren27(&mut self) -> AREN27_W<27> { + pub fn aren27(&mut self) -> AREN27_W { AREN27_W::new(self) } #[doc = "Bit 28 - Async rising enabled 28"] #[inline(always)] #[must_use] - pub fn aren28(&mut self) -> AREN28_W<28> { + pub fn aren28(&mut self) -> AREN28_W { AREN28_W::new(self) } #[doc = "Bit 29 - Async rising enabled 29"] #[inline(always)] #[must_use] - pub fn aren29(&mut self) -> AREN29_W<29> { + pub fn aren29(&mut self) -> AREN29_W { AREN29_W::new(self) } #[doc = "Bit 30 - Async rising enabled 30"] #[inline(always)] #[must_use] - pub fn aren30(&mut self) -> AREN30_W<30> { + pub fn aren30(&mut self) -> AREN30_W { AREN30_W::new(self) } #[doc = "Bit 31 - Async rising enabled 31"] #[inline(always)] #[must_use] - pub fn aren31(&mut self) -> AREN31_W<31> { + pub fn aren31(&mut self) -> AREN31_W { AREN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Async. Rising Edge Detect 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gparen0](index.html) module"] +#[doc = "GPIO Pin Async. Rising Edge Detect 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gparen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gparen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPAREN0_SPEC; impl crate::RegisterSpec for GPAREN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gparen0::R](R) reader structure"] -impl crate::Readable for GPAREN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gparen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gparen0::R`](R) reader structure"] +impl crate::Readable for GPAREN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gparen0::W`](W) writer structure"] impl crate::Writable for GPAREN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gparen1.rs b/crates/bcm2837-lpa/src/gpio/gparen1.rs index 158f1ef..f4a64ad 100644 --- a/crates/bcm2837-lpa/src/gpio/gparen1.rs +++ b/crates/bcm2837-lpa/src/gpio/gparen1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPAREN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPAREN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AREN32` reader - Async rising enabled 32"] -pub type AREN32_R = crate::BitReader; +pub type AREN32_R = crate::BitReader; #[doc = "Field `AREN32` writer - Async rising enabled 32"] -pub type AREN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN33` reader - Async rising enabled 33"] -pub type AREN33_R = crate::BitReader; +pub type AREN33_R = crate::BitReader; #[doc = "Field `AREN33` writer - Async rising enabled 33"] -pub type AREN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN34` reader - Async rising enabled 34"] -pub type AREN34_R = crate::BitReader; +pub type AREN34_R = crate::BitReader; #[doc = "Field `AREN34` writer - Async rising enabled 34"] -pub type AREN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN35` reader - Async rising enabled 35"] -pub type AREN35_R = crate::BitReader; +pub type AREN35_R = crate::BitReader; #[doc = "Field `AREN35` writer - Async rising enabled 35"] -pub type AREN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN36` reader - Async rising enabled 36"] -pub type AREN36_R = crate::BitReader; +pub type AREN36_R = crate::BitReader; #[doc = "Field `AREN36` writer - Async rising enabled 36"] -pub type AREN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN37` reader - Async rising enabled 37"] -pub type AREN37_R = crate::BitReader; +pub type AREN37_R = crate::BitReader; #[doc = "Field `AREN37` writer - Async rising enabled 37"] -pub type AREN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN38` reader - Async rising enabled 38"] -pub type AREN38_R = crate::BitReader; +pub type AREN38_R = crate::BitReader; #[doc = "Field `AREN38` writer - Async rising enabled 38"] -pub type AREN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN39` reader - Async rising enabled 39"] -pub type AREN39_R = crate::BitReader; +pub type AREN39_R = crate::BitReader; #[doc = "Field `AREN39` writer - Async rising enabled 39"] -pub type AREN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN40` reader - Async rising enabled 40"] -pub type AREN40_R = crate::BitReader; +pub type AREN40_R = crate::BitReader; #[doc = "Field `AREN40` writer - Async rising enabled 40"] -pub type AREN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN41` reader - Async rising enabled 41"] -pub type AREN41_R = crate::BitReader; +pub type AREN41_R = crate::BitReader; #[doc = "Field `AREN41` writer - Async rising enabled 41"] -pub type AREN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN42` reader - Async rising enabled 42"] -pub type AREN42_R = crate::BitReader; +pub type AREN42_R = crate::BitReader; #[doc = "Field `AREN42` writer - Async rising enabled 42"] -pub type AREN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN43` reader - Async rising enabled 43"] -pub type AREN43_R = crate::BitReader; +pub type AREN43_R = crate::BitReader; #[doc = "Field `AREN43` writer - Async rising enabled 43"] -pub type AREN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN44` reader - Async rising enabled 44"] -pub type AREN44_R = crate::BitReader; +pub type AREN44_R = crate::BitReader; #[doc = "Field `AREN44` writer - Async rising enabled 44"] -pub type AREN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN45` reader - Async rising enabled 45"] -pub type AREN45_R = crate::BitReader; +pub type AREN45_R = crate::BitReader; #[doc = "Field `AREN45` writer - Async rising enabled 45"] -pub type AREN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN46` reader - Async rising enabled 46"] -pub type AREN46_R = crate::BitReader; +pub type AREN46_R = crate::BitReader; #[doc = "Field `AREN46` writer - Async rising enabled 46"] -pub type AREN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN47` reader - Async rising enabled 47"] -pub type AREN47_R = crate::BitReader; +pub type AREN47_R = crate::BitReader; #[doc = "Field `AREN47` writer - Async rising enabled 47"] -pub type AREN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN48` reader - Async rising enabled 48"] -pub type AREN48_R = crate::BitReader; +pub type AREN48_R = crate::BitReader; #[doc = "Field `AREN48` writer - Async rising enabled 48"] -pub type AREN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN49` reader - Async rising enabled 49"] -pub type AREN49_R = crate::BitReader; +pub type AREN49_R = crate::BitReader; #[doc = "Field `AREN49` writer - Async rising enabled 49"] -pub type AREN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN50` reader - Async rising enabled 50"] -pub type AREN50_R = crate::BitReader; +pub type AREN50_R = crate::BitReader; #[doc = "Field `AREN50` writer - Async rising enabled 50"] -pub type AREN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN51` reader - Async rising enabled 51"] -pub type AREN51_R = crate::BitReader; +pub type AREN51_R = crate::BitReader; #[doc = "Field `AREN51` writer - Async rising enabled 51"] -pub type AREN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN52` reader - Async rising enabled 52"] -pub type AREN52_R = crate::BitReader; +pub type AREN52_R = crate::BitReader; #[doc = "Field `AREN52` writer - Async rising enabled 52"] -pub type AREN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AREN53` reader - Async rising enabled 53"] -pub type AREN53_R = crate::BitReader; +pub type AREN53_R = crate::BitReader; #[doc = "Field `AREN53` writer - Async rising enabled 53"] -pub type AREN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPAREN1_SPEC, bool, O>; +pub type AREN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Async rising enabled 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { AREN53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPAREN1") + .field("aren32", &format_args!("{}", self.aren32().bit())) + .field("aren33", &format_args!("{}", self.aren33().bit())) + .field("aren34", &format_args!("{}", self.aren34().bit())) + .field("aren35", &format_args!("{}", self.aren35().bit())) + .field("aren36", &format_args!("{}", self.aren36().bit())) + .field("aren37", &format_args!("{}", self.aren37().bit())) + .field("aren38", &format_args!("{}", self.aren38().bit())) + .field("aren39", &format_args!("{}", self.aren39().bit())) + .field("aren40", &format_args!("{}", self.aren40().bit())) + .field("aren41", &format_args!("{}", self.aren41().bit())) + .field("aren42", &format_args!("{}", self.aren42().bit())) + .field("aren43", &format_args!("{}", self.aren43().bit())) + .field("aren44", &format_args!("{}", self.aren44().bit())) + .field("aren45", &format_args!("{}", self.aren45().bit())) + .field("aren46", &format_args!("{}", self.aren46().bit())) + .field("aren47", &format_args!("{}", self.aren47().bit())) + .field("aren48", &format_args!("{}", self.aren48().bit())) + .field("aren49", &format_args!("{}", self.aren49().bit())) + .field("aren50", &format_args!("{}", self.aren50().bit())) + .field("aren51", &format_args!("{}", self.aren51().bit())) + .field("aren52", &format_args!("{}", self.aren52().bit())) + .field("aren53", &format_args!("{}", self.aren53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Async rising enabled 32"] #[inline(always)] #[must_use] - pub fn aren32(&mut self) -> AREN32_W<0> { + pub fn aren32(&mut self) -> AREN32_W { AREN32_W::new(self) } #[doc = "Bit 1 - Async rising enabled 33"] #[inline(always)] #[must_use] - pub fn aren33(&mut self) -> AREN33_W<1> { + pub fn aren33(&mut self) -> AREN33_W { AREN33_W::new(self) } #[doc = "Bit 2 - Async rising enabled 34"] #[inline(always)] #[must_use] - pub fn aren34(&mut self) -> AREN34_W<2> { + pub fn aren34(&mut self) -> AREN34_W { AREN34_W::new(self) } #[doc = "Bit 3 - Async rising enabled 35"] #[inline(always)] #[must_use] - pub fn aren35(&mut self) -> AREN35_W<3> { + pub fn aren35(&mut self) -> AREN35_W { AREN35_W::new(self) } #[doc = "Bit 4 - Async rising enabled 36"] #[inline(always)] #[must_use] - pub fn aren36(&mut self) -> AREN36_W<4> { + pub fn aren36(&mut self) -> AREN36_W { AREN36_W::new(self) } #[doc = "Bit 5 - Async rising enabled 37"] #[inline(always)] #[must_use] - pub fn aren37(&mut self) -> AREN37_W<5> { + pub fn aren37(&mut self) -> AREN37_W { AREN37_W::new(self) } #[doc = "Bit 6 - Async rising enabled 38"] #[inline(always)] #[must_use] - pub fn aren38(&mut self) -> AREN38_W<6> { + pub fn aren38(&mut self) -> AREN38_W { AREN38_W::new(self) } #[doc = "Bit 7 - Async rising enabled 39"] #[inline(always)] #[must_use] - pub fn aren39(&mut self) -> AREN39_W<7> { + pub fn aren39(&mut self) -> AREN39_W { AREN39_W::new(self) } #[doc = "Bit 8 - Async rising enabled 40"] #[inline(always)] #[must_use] - pub fn aren40(&mut self) -> AREN40_W<8> { + pub fn aren40(&mut self) -> AREN40_W { AREN40_W::new(self) } #[doc = "Bit 9 - Async rising enabled 41"] #[inline(always)] #[must_use] - pub fn aren41(&mut self) -> AREN41_W<9> { + pub fn aren41(&mut self) -> AREN41_W { AREN41_W::new(self) } #[doc = "Bit 10 - Async rising enabled 42"] #[inline(always)] #[must_use] - pub fn aren42(&mut self) -> AREN42_W<10> { + pub fn aren42(&mut self) -> AREN42_W { AREN42_W::new(self) } #[doc = "Bit 11 - Async rising enabled 43"] #[inline(always)] #[must_use] - pub fn aren43(&mut self) -> AREN43_W<11> { + pub fn aren43(&mut self) -> AREN43_W { AREN43_W::new(self) } #[doc = "Bit 12 - Async rising enabled 44"] #[inline(always)] #[must_use] - pub fn aren44(&mut self) -> AREN44_W<12> { + pub fn aren44(&mut self) -> AREN44_W { AREN44_W::new(self) } #[doc = "Bit 13 - Async rising enabled 45"] #[inline(always)] #[must_use] - pub fn aren45(&mut self) -> AREN45_W<13> { + pub fn aren45(&mut self) -> AREN45_W { AREN45_W::new(self) } #[doc = "Bit 14 - Async rising enabled 46"] #[inline(always)] #[must_use] - pub fn aren46(&mut self) -> AREN46_W<14> { + pub fn aren46(&mut self) -> AREN46_W { AREN46_W::new(self) } #[doc = "Bit 15 - Async rising enabled 47"] #[inline(always)] #[must_use] - pub fn aren47(&mut self) -> AREN47_W<15> { + pub fn aren47(&mut self) -> AREN47_W { AREN47_W::new(self) } #[doc = "Bit 16 - Async rising enabled 48"] #[inline(always)] #[must_use] - pub fn aren48(&mut self) -> AREN48_W<16> { + pub fn aren48(&mut self) -> AREN48_W { AREN48_W::new(self) } #[doc = "Bit 17 - Async rising enabled 49"] #[inline(always)] #[must_use] - pub fn aren49(&mut self) -> AREN49_W<17> { + pub fn aren49(&mut self) -> AREN49_W { AREN49_W::new(self) } #[doc = "Bit 18 - Async rising enabled 50"] #[inline(always)] #[must_use] - pub fn aren50(&mut self) -> AREN50_W<18> { + pub fn aren50(&mut self) -> AREN50_W { AREN50_W::new(self) } #[doc = "Bit 19 - Async rising enabled 51"] #[inline(always)] #[must_use] - pub fn aren51(&mut self) -> AREN51_W<19> { + pub fn aren51(&mut self) -> AREN51_W { AREN51_W::new(self) } #[doc = "Bit 20 - Async rising enabled 52"] #[inline(always)] #[must_use] - pub fn aren52(&mut self) -> AREN52_W<20> { + pub fn aren52(&mut self) -> AREN52_W { AREN52_W::new(self) } #[doc = "Bit 21 - Async rising enabled 53"] #[inline(always)] #[must_use] - pub fn aren53(&mut self) -> AREN53_W<21> { + pub fn aren53(&mut self) -> AREN53_W { AREN53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Async. Rising Edge Detect 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gparen1](index.html) module"] +#[doc = "GPIO Pin Async. Rising Edge Detect 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gparen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gparen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPAREN1_SPEC; impl crate::RegisterSpec for GPAREN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gparen1::R](R) reader structure"] -impl crate::Readable for GPAREN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gparen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gparen1::R`](R) reader structure"] +impl crate::Readable for GPAREN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gparen1::W`](W) writer structure"] impl crate::Writable for GPAREN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpclr0.rs b/crates/bcm2837-lpa/src/gpio/gpclr0.rs index 1a6b2cd..210af7f 100644 --- a/crates/bcm2837-lpa/src/gpio/gpclr0.rs +++ b/crates/bcm2837-lpa/src/gpio/gpclr0.rs @@ -1,296 +1,285 @@ #[doc = "Register `GPCLR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLR0` writer - Clear 0"] -pub type CLR0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR1` writer - Clear 1"] -pub type CLR1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR2` writer - Clear 2"] -pub type CLR2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR3` writer - Clear 3"] -pub type CLR3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR4` writer - Clear 4"] -pub type CLR4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR5` writer - Clear 5"] -pub type CLR5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR6` writer - Clear 6"] -pub type CLR6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR7` writer - Clear 7"] -pub type CLR7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR8` writer - Clear 8"] -pub type CLR8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR9` writer - Clear 9"] -pub type CLR9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR9_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR10` writer - Clear 10"] -pub type CLR10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR11` writer - Clear 11"] -pub type CLR11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR12` writer - Clear 12"] -pub type CLR12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR13` writer - Clear 13"] -pub type CLR13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR14` writer - Clear 14"] -pub type CLR14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR15` writer - Clear 15"] -pub type CLR15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR16` writer - Clear 16"] -pub type CLR16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR16_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR17` writer - Clear 17"] -pub type CLR17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR17_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR18` writer - Clear 18"] -pub type CLR18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR18_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR19` writer - Clear 19"] -pub type CLR19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR19_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR20` writer - Clear 20"] -pub type CLR20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR20_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR21` writer - Clear 21"] -pub type CLR21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR21_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR22` writer - Clear 22"] -pub type CLR22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR22_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR23` writer - Clear 23"] -pub type CLR23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR23_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR24` writer - Clear 24"] -pub type CLR24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR24_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR25` writer - Clear 25"] -pub type CLR25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR25_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR26` writer - Clear 26"] -pub type CLR26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR26_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR27` writer - Clear 27"] -pub type CLR27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR27_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR28` writer - Clear 28"] -pub type CLR28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR28_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR29` writer - Clear 29"] -pub type CLR29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR29_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR30` writer - Clear 30"] -pub type CLR30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR30_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR31` writer - Clear 31"] -pub type CLR31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR0_SPEC, bool, O>; +pub type CLR31_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - Clear 0"] #[inline(always)] #[must_use] - pub fn clr0(&mut self) -> CLR0_W<0> { + pub fn clr0(&mut self) -> CLR0_W { CLR0_W::new(self) } #[doc = "Bit 1 - Clear 1"] #[inline(always)] #[must_use] - pub fn clr1(&mut self) -> CLR1_W<1> { + pub fn clr1(&mut self) -> CLR1_W { CLR1_W::new(self) } #[doc = "Bit 2 - Clear 2"] #[inline(always)] #[must_use] - pub fn clr2(&mut self) -> CLR2_W<2> { + pub fn clr2(&mut self) -> CLR2_W { CLR2_W::new(self) } #[doc = "Bit 3 - Clear 3"] #[inline(always)] #[must_use] - pub fn clr3(&mut self) -> CLR3_W<3> { + pub fn clr3(&mut self) -> CLR3_W { CLR3_W::new(self) } #[doc = "Bit 4 - Clear 4"] #[inline(always)] #[must_use] - pub fn clr4(&mut self) -> CLR4_W<4> { + pub fn clr4(&mut self) -> CLR4_W { CLR4_W::new(self) } #[doc = "Bit 5 - Clear 5"] #[inline(always)] #[must_use] - pub fn clr5(&mut self) -> CLR5_W<5> { + pub fn clr5(&mut self) -> CLR5_W { CLR5_W::new(self) } #[doc = "Bit 6 - Clear 6"] #[inline(always)] #[must_use] - pub fn clr6(&mut self) -> CLR6_W<6> { + pub fn clr6(&mut self) -> CLR6_W { CLR6_W::new(self) } #[doc = "Bit 7 - Clear 7"] #[inline(always)] #[must_use] - pub fn clr7(&mut self) -> CLR7_W<7> { + pub fn clr7(&mut self) -> CLR7_W { CLR7_W::new(self) } #[doc = "Bit 8 - Clear 8"] #[inline(always)] #[must_use] - pub fn clr8(&mut self) -> CLR8_W<8> { + pub fn clr8(&mut self) -> CLR8_W { CLR8_W::new(self) } #[doc = "Bit 9 - Clear 9"] #[inline(always)] #[must_use] - pub fn clr9(&mut self) -> CLR9_W<9> { + pub fn clr9(&mut self) -> CLR9_W { CLR9_W::new(self) } #[doc = "Bit 10 - Clear 10"] #[inline(always)] #[must_use] - pub fn clr10(&mut self) -> CLR10_W<10> { + pub fn clr10(&mut self) -> CLR10_W { CLR10_W::new(self) } #[doc = "Bit 11 - Clear 11"] #[inline(always)] #[must_use] - pub fn clr11(&mut self) -> CLR11_W<11> { + pub fn clr11(&mut self) -> CLR11_W { CLR11_W::new(self) } #[doc = "Bit 12 - Clear 12"] #[inline(always)] #[must_use] - pub fn clr12(&mut self) -> CLR12_W<12> { + pub fn clr12(&mut self) -> CLR12_W { CLR12_W::new(self) } #[doc = "Bit 13 - Clear 13"] #[inline(always)] #[must_use] - pub fn clr13(&mut self) -> CLR13_W<13> { + pub fn clr13(&mut self) -> CLR13_W { CLR13_W::new(self) } #[doc = "Bit 14 - Clear 14"] #[inline(always)] #[must_use] - pub fn clr14(&mut self) -> CLR14_W<14> { + pub fn clr14(&mut self) -> CLR14_W { CLR14_W::new(self) } #[doc = "Bit 15 - Clear 15"] #[inline(always)] #[must_use] - pub fn clr15(&mut self) -> CLR15_W<15> { + pub fn clr15(&mut self) -> CLR15_W { CLR15_W::new(self) } #[doc = "Bit 16 - Clear 16"] #[inline(always)] #[must_use] - pub fn clr16(&mut self) -> CLR16_W<16> { + pub fn clr16(&mut self) -> CLR16_W { CLR16_W::new(self) } #[doc = "Bit 17 - Clear 17"] #[inline(always)] #[must_use] - pub fn clr17(&mut self) -> CLR17_W<17> { + pub fn clr17(&mut self) -> CLR17_W { CLR17_W::new(self) } #[doc = "Bit 18 - Clear 18"] #[inline(always)] #[must_use] - pub fn clr18(&mut self) -> CLR18_W<18> { + pub fn clr18(&mut self) -> CLR18_W { CLR18_W::new(self) } #[doc = "Bit 19 - Clear 19"] #[inline(always)] #[must_use] - pub fn clr19(&mut self) -> CLR19_W<19> { + pub fn clr19(&mut self) -> CLR19_W { CLR19_W::new(self) } #[doc = "Bit 20 - Clear 20"] #[inline(always)] #[must_use] - pub fn clr20(&mut self) -> CLR20_W<20> { + pub fn clr20(&mut self) -> CLR20_W { CLR20_W::new(self) } #[doc = "Bit 21 - Clear 21"] #[inline(always)] #[must_use] - pub fn clr21(&mut self) -> CLR21_W<21> { + pub fn clr21(&mut self) -> CLR21_W { CLR21_W::new(self) } #[doc = "Bit 22 - Clear 22"] #[inline(always)] #[must_use] - pub fn clr22(&mut self) -> CLR22_W<22> { + pub fn clr22(&mut self) -> CLR22_W { CLR22_W::new(self) } #[doc = "Bit 23 - Clear 23"] #[inline(always)] #[must_use] - pub fn clr23(&mut self) -> CLR23_W<23> { + pub fn clr23(&mut self) -> CLR23_W { CLR23_W::new(self) } #[doc = "Bit 24 - Clear 24"] #[inline(always)] #[must_use] - pub fn clr24(&mut self) -> CLR24_W<24> { + pub fn clr24(&mut self) -> CLR24_W { CLR24_W::new(self) } #[doc = "Bit 25 - Clear 25"] #[inline(always)] #[must_use] - pub fn clr25(&mut self) -> CLR25_W<25> { + pub fn clr25(&mut self) -> CLR25_W { CLR25_W::new(self) } #[doc = "Bit 26 - Clear 26"] #[inline(always)] #[must_use] - pub fn clr26(&mut self) -> CLR26_W<26> { + pub fn clr26(&mut self) -> CLR26_W { CLR26_W::new(self) } #[doc = "Bit 27 - Clear 27"] #[inline(always)] #[must_use] - pub fn clr27(&mut self) -> CLR27_W<27> { + pub fn clr27(&mut self) -> CLR27_W { CLR27_W::new(self) } #[doc = "Bit 28 - Clear 28"] #[inline(always)] #[must_use] - pub fn clr28(&mut self) -> CLR28_W<28> { + pub fn clr28(&mut self) -> CLR28_W { CLR28_W::new(self) } #[doc = "Bit 29 - Clear 29"] #[inline(always)] #[must_use] - pub fn clr29(&mut self) -> CLR29_W<29> { + pub fn clr29(&mut self) -> CLR29_W { CLR29_W::new(self) } #[doc = "Bit 30 - Clear 30"] #[inline(always)] #[must_use] - pub fn clr30(&mut self) -> CLR30_W<30> { + pub fn clr30(&mut self) -> CLR30_W { CLR30_W::new(self) } #[doc = "Bit 31 - Clear 31"] #[inline(always)] #[must_use] - pub fn clr31(&mut self) -> CLR31_W<31> { + pub fn clr31(&mut self) -> CLR31_W { CLR31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Output Clear 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpclr0](index.html) module"] +#[doc = "GPIO Pin Output Clear 0\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpclr0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPCLR0_SPEC; impl crate::RegisterSpec for GPCLR0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpclr0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpclr0::W`](W) writer structure"] impl crate::Writable for GPCLR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2837-lpa/src/gpio/gpclr1.rs b/crates/bcm2837-lpa/src/gpio/gpclr1.rs index 84ce196..21e8c12 100644 --- a/crates/bcm2837-lpa/src/gpio/gpclr1.rs +++ b/crates/bcm2837-lpa/src/gpio/gpclr1.rs @@ -1,216 +1,205 @@ #[doc = "Register `GPCLR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLR32` writer - Clear 32"] -pub type CLR32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR32_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR33` writer - Clear 33"] -pub type CLR33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR33_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR34` writer - Clear 34"] -pub type CLR34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR34_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR35` writer - Clear 35"] -pub type CLR35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR35_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR36` writer - Clear 36"] -pub type CLR36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR36_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR37` writer - Clear 37"] -pub type CLR37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR37_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR38` writer - Clear 38"] -pub type CLR38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR38_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR39` writer - Clear 39"] -pub type CLR39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR39_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR40` writer - Clear 40"] -pub type CLR40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR40_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR41` writer - Clear 41"] -pub type CLR41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR41_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR42` writer - Clear 42"] -pub type CLR42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR42_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR43` writer - Clear 43"] -pub type CLR43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR43_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR44` writer - Clear 44"] -pub type CLR44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR44_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR45` writer - Clear 45"] -pub type CLR45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR45_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR46` writer - Clear 46"] -pub type CLR46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR46_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR47` writer - Clear 47"] -pub type CLR47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR47_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR48` writer - Clear 48"] -pub type CLR48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR48_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR49` writer - Clear 49"] -pub type CLR49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR49_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR50` writer - Clear 50"] -pub type CLR50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR50_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR51` writer - Clear 51"] -pub type CLR51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR51_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR52` writer - Clear 52"] -pub type CLR52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR52_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CLR53` writer - Clear 53"] -pub type CLR53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPCLR1_SPEC, bool, O>; +pub type CLR53_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - Clear 32"] #[inline(always)] #[must_use] - pub fn clr32(&mut self) -> CLR32_W<0> { + pub fn clr32(&mut self) -> CLR32_W { CLR32_W::new(self) } #[doc = "Bit 1 - Clear 33"] #[inline(always)] #[must_use] - pub fn clr33(&mut self) -> CLR33_W<1> { + pub fn clr33(&mut self) -> CLR33_W { CLR33_W::new(self) } #[doc = "Bit 2 - Clear 34"] #[inline(always)] #[must_use] - pub fn clr34(&mut self) -> CLR34_W<2> { + pub fn clr34(&mut self) -> CLR34_W { CLR34_W::new(self) } #[doc = "Bit 3 - Clear 35"] #[inline(always)] #[must_use] - pub fn clr35(&mut self) -> CLR35_W<3> { + pub fn clr35(&mut self) -> CLR35_W { CLR35_W::new(self) } #[doc = "Bit 4 - Clear 36"] #[inline(always)] #[must_use] - pub fn clr36(&mut self) -> CLR36_W<4> { + pub fn clr36(&mut self) -> CLR36_W { CLR36_W::new(self) } #[doc = "Bit 5 - Clear 37"] #[inline(always)] #[must_use] - pub fn clr37(&mut self) -> CLR37_W<5> { + pub fn clr37(&mut self) -> CLR37_W { CLR37_W::new(self) } #[doc = "Bit 6 - Clear 38"] #[inline(always)] #[must_use] - pub fn clr38(&mut self) -> CLR38_W<6> { + pub fn clr38(&mut self) -> CLR38_W { CLR38_W::new(self) } #[doc = "Bit 7 - Clear 39"] #[inline(always)] #[must_use] - pub fn clr39(&mut self) -> CLR39_W<7> { + pub fn clr39(&mut self) -> CLR39_W { CLR39_W::new(self) } #[doc = "Bit 8 - Clear 40"] #[inline(always)] #[must_use] - pub fn clr40(&mut self) -> CLR40_W<8> { + pub fn clr40(&mut self) -> CLR40_W { CLR40_W::new(self) } #[doc = "Bit 9 - Clear 41"] #[inline(always)] #[must_use] - pub fn clr41(&mut self) -> CLR41_W<9> { + pub fn clr41(&mut self) -> CLR41_W { CLR41_W::new(self) } #[doc = "Bit 10 - Clear 42"] #[inline(always)] #[must_use] - pub fn clr42(&mut self) -> CLR42_W<10> { + pub fn clr42(&mut self) -> CLR42_W { CLR42_W::new(self) } #[doc = "Bit 11 - Clear 43"] #[inline(always)] #[must_use] - pub fn clr43(&mut self) -> CLR43_W<11> { + pub fn clr43(&mut self) -> CLR43_W { CLR43_W::new(self) } #[doc = "Bit 12 - Clear 44"] #[inline(always)] #[must_use] - pub fn clr44(&mut self) -> CLR44_W<12> { + pub fn clr44(&mut self) -> CLR44_W { CLR44_W::new(self) } #[doc = "Bit 13 - Clear 45"] #[inline(always)] #[must_use] - pub fn clr45(&mut self) -> CLR45_W<13> { + pub fn clr45(&mut self) -> CLR45_W { CLR45_W::new(self) } #[doc = "Bit 14 - Clear 46"] #[inline(always)] #[must_use] - pub fn clr46(&mut self) -> CLR46_W<14> { + pub fn clr46(&mut self) -> CLR46_W { CLR46_W::new(self) } #[doc = "Bit 15 - Clear 47"] #[inline(always)] #[must_use] - pub fn clr47(&mut self) -> CLR47_W<15> { + pub fn clr47(&mut self) -> CLR47_W { CLR47_W::new(self) } #[doc = "Bit 16 - Clear 48"] #[inline(always)] #[must_use] - pub fn clr48(&mut self) -> CLR48_W<16> { + pub fn clr48(&mut self) -> CLR48_W { CLR48_W::new(self) } #[doc = "Bit 17 - Clear 49"] #[inline(always)] #[must_use] - pub fn clr49(&mut self) -> CLR49_W<17> { + pub fn clr49(&mut self) -> CLR49_W { CLR49_W::new(self) } #[doc = "Bit 18 - Clear 50"] #[inline(always)] #[must_use] - pub fn clr50(&mut self) -> CLR50_W<18> { + pub fn clr50(&mut self) -> CLR50_W { CLR50_W::new(self) } #[doc = "Bit 19 - Clear 51"] #[inline(always)] #[must_use] - pub fn clr51(&mut self) -> CLR51_W<19> { + pub fn clr51(&mut self) -> CLR51_W { CLR51_W::new(self) } #[doc = "Bit 20 - Clear 52"] #[inline(always)] #[must_use] - pub fn clr52(&mut self) -> CLR52_W<20> { + pub fn clr52(&mut self) -> CLR52_W { CLR52_W::new(self) } #[doc = "Bit 21 - Clear 53"] #[inline(always)] #[must_use] - pub fn clr53(&mut self) -> CLR53_W<21> { + pub fn clr53(&mut self) -> CLR53_W { CLR53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Output Clear 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpclr1](index.html) module"] +#[doc = "GPIO Pin Output Clear 1\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpclr1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPCLR1_SPEC; impl crate::RegisterSpec for GPCLR1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpclr1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpclr1::W`](W) writer structure"] impl crate::Writable for GPCLR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x003f_ffff; } diff --git a/crates/bcm2837-lpa/src/gpio/gpeds0.rs b/crates/bcm2837-lpa/src/gpio/gpeds0.rs index 7aadf5b..caa11e1 100644 --- a/crates/bcm2837-lpa/src/gpio/gpeds0.rs +++ b/crates/bcm2837-lpa/src/gpio/gpeds0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPEDS0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPEDS0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EDS0` reader - Event detected 0"] -pub type EDS0_R = crate::BitReader; +pub type EDS0_R = crate::BitReader; #[doc = "Field `EDS0` writer - Event detected 0"] -pub type EDS0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS1` reader - Event detected 1"] -pub type EDS1_R = crate::BitReader; +pub type EDS1_R = crate::BitReader; #[doc = "Field `EDS1` writer - Event detected 1"] -pub type EDS1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS2` reader - Event detected 2"] -pub type EDS2_R = crate::BitReader; +pub type EDS2_R = crate::BitReader; #[doc = "Field `EDS2` writer - Event detected 2"] -pub type EDS2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS3` reader - Event detected 3"] -pub type EDS3_R = crate::BitReader; +pub type EDS3_R = crate::BitReader; #[doc = "Field `EDS3` writer - Event detected 3"] -pub type EDS3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS4` reader - Event detected 4"] -pub type EDS4_R = crate::BitReader; +pub type EDS4_R = crate::BitReader; #[doc = "Field `EDS4` writer - Event detected 4"] -pub type EDS4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS5` reader - Event detected 5"] -pub type EDS5_R = crate::BitReader; +pub type EDS5_R = crate::BitReader; #[doc = "Field `EDS5` writer - Event detected 5"] -pub type EDS5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS6` reader - Event detected 6"] -pub type EDS6_R = crate::BitReader; +pub type EDS6_R = crate::BitReader; #[doc = "Field `EDS6` writer - Event detected 6"] -pub type EDS6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS7` reader - Event detected 7"] -pub type EDS7_R = crate::BitReader; +pub type EDS7_R = crate::BitReader; #[doc = "Field `EDS7` writer - Event detected 7"] -pub type EDS7_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS7_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS8` reader - Event detected 8"] -pub type EDS8_R = crate::BitReader; +pub type EDS8_R = crate::BitReader; #[doc = "Field `EDS8` writer - Event detected 8"] -pub type EDS8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS9` reader - Event detected 9"] -pub type EDS9_R = crate::BitReader; +pub type EDS9_R = crate::BitReader; #[doc = "Field `EDS9` writer - Event detected 9"] -pub type EDS9_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS9_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS10` reader - Event detected 10"] -pub type EDS10_R = crate::BitReader; +pub type EDS10_R = crate::BitReader; #[doc = "Field `EDS10` writer - Event detected 10"] -pub type EDS10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS11` reader - Event detected 11"] -pub type EDS11_R = crate::BitReader; +pub type EDS11_R = crate::BitReader; #[doc = "Field `EDS11` writer - Event detected 11"] -pub type EDS11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS12` reader - Event detected 12"] -pub type EDS12_R = crate::BitReader; +pub type EDS12_R = crate::BitReader; #[doc = "Field `EDS12` writer - Event detected 12"] -pub type EDS12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS13` reader - Event detected 13"] -pub type EDS13_R = crate::BitReader; +pub type EDS13_R = crate::BitReader; #[doc = "Field `EDS13` writer - Event detected 13"] -pub type EDS13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS14` reader - Event detected 14"] -pub type EDS14_R = crate::BitReader; +pub type EDS14_R = crate::BitReader; #[doc = "Field `EDS14` writer - Event detected 14"] -pub type EDS14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS15` reader - Event detected 15"] -pub type EDS15_R = crate::BitReader; +pub type EDS15_R = crate::BitReader; #[doc = "Field `EDS15` writer - Event detected 15"] -pub type EDS15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS16` reader - Event detected 16"] -pub type EDS16_R = crate::BitReader; +pub type EDS16_R = crate::BitReader; #[doc = "Field `EDS16` writer - Event detected 16"] -pub type EDS16_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS16_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS17` reader - Event detected 17"] -pub type EDS17_R = crate::BitReader; +pub type EDS17_R = crate::BitReader; #[doc = "Field `EDS17` writer - Event detected 17"] -pub type EDS17_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS17_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS18` reader - Event detected 18"] -pub type EDS18_R = crate::BitReader; +pub type EDS18_R = crate::BitReader; #[doc = "Field `EDS18` writer - Event detected 18"] -pub type EDS18_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS18_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS19` reader - Event detected 19"] -pub type EDS19_R = crate::BitReader; +pub type EDS19_R = crate::BitReader; #[doc = "Field `EDS19` writer - Event detected 19"] -pub type EDS19_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS19_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS20` reader - Event detected 20"] -pub type EDS20_R = crate::BitReader; +pub type EDS20_R = crate::BitReader; #[doc = "Field `EDS20` writer - Event detected 20"] -pub type EDS20_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS20_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS21` reader - Event detected 21"] -pub type EDS21_R = crate::BitReader; +pub type EDS21_R = crate::BitReader; #[doc = "Field `EDS21` writer - Event detected 21"] -pub type EDS21_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS21_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS22` reader - Event detected 22"] -pub type EDS22_R = crate::BitReader; +pub type EDS22_R = crate::BitReader; #[doc = "Field `EDS22` writer - Event detected 22"] -pub type EDS22_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS22_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS23` reader - Event detected 23"] -pub type EDS23_R = crate::BitReader; +pub type EDS23_R = crate::BitReader; #[doc = "Field `EDS23` writer - Event detected 23"] -pub type EDS23_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS23_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS24` reader - Event detected 24"] -pub type EDS24_R = crate::BitReader; +pub type EDS24_R = crate::BitReader; #[doc = "Field `EDS24` writer - Event detected 24"] -pub type EDS24_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS24_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS25` reader - Event detected 25"] -pub type EDS25_R = crate::BitReader; +pub type EDS25_R = crate::BitReader; #[doc = "Field `EDS25` writer - Event detected 25"] -pub type EDS25_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS25_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS26` reader - Event detected 26"] -pub type EDS26_R = crate::BitReader; +pub type EDS26_R = crate::BitReader; #[doc = "Field `EDS26` writer - Event detected 26"] -pub type EDS26_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS26_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS27` reader - Event detected 27"] -pub type EDS27_R = crate::BitReader; +pub type EDS27_R = crate::BitReader; #[doc = "Field `EDS27` writer - Event detected 27"] -pub type EDS27_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS27_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS28` reader - Event detected 28"] -pub type EDS28_R = crate::BitReader; +pub type EDS28_R = crate::BitReader; #[doc = "Field `EDS28` writer - Event detected 28"] -pub type EDS28_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS28_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS29` reader - Event detected 29"] -pub type EDS29_R = crate::BitReader; +pub type EDS29_R = crate::BitReader; #[doc = "Field `EDS29` writer - Event detected 29"] -pub type EDS29_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS29_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS30` reader - Event detected 30"] -pub type EDS30_R = crate::BitReader; +pub type EDS30_R = crate::BitReader; #[doc = "Field `EDS30` writer - Event detected 30"] -pub type EDS30_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS30_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS31` reader - Event detected 31"] -pub type EDS31_R = crate::BitReader; +pub type EDS31_R = crate::BitReader; #[doc = "Field `EDS31` writer - Event detected 31"] -pub type EDS31_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS0_SPEC, bool, O>; +pub type EDS31_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Event detected 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { EDS31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPEDS0") + .field("eds0", &format_args!("{}", self.eds0().bit())) + .field("eds1", &format_args!("{}", self.eds1().bit())) + .field("eds2", &format_args!("{}", self.eds2().bit())) + .field("eds3", &format_args!("{}", self.eds3().bit())) + .field("eds4", &format_args!("{}", self.eds4().bit())) + .field("eds5", &format_args!("{}", self.eds5().bit())) + .field("eds6", &format_args!("{}", self.eds6().bit())) + .field("eds7", &format_args!("{}", self.eds7().bit())) + .field("eds8", &format_args!("{}", self.eds8().bit())) + .field("eds9", &format_args!("{}", self.eds9().bit())) + .field("eds10", &format_args!("{}", self.eds10().bit())) + .field("eds11", &format_args!("{}", self.eds11().bit())) + .field("eds12", &format_args!("{}", self.eds12().bit())) + .field("eds13", &format_args!("{}", self.eds13().bit())) + .field("eds14", &format_args!("{}", self.eds14().bit())) + .field("eds15", &format_args!("{}", self.eds15().bit())) + .field("eds16", &format_args!("{}", self.eds16().bit())) + .field("eds17", &format_args!("{}", self.eds17().bit())) + .field("eds18", &format_args!("{}", self.eds18().bit())) + .field("eds19", &format_args!("{}", self.eds19().bit())) + .field("eds20", &format_args!("{}", self.eds20().bit())) + .field("eds21", &format_args!("{}", self.eds21().bit())) + .field("eds22", &format_args!("{}", self.eds22().bit())) + .field("eds23", &format_args!("{}", self.eds23().bit())) + .field("eds24", &format_args!("{}", self.eds24().bit())) + .field("eds25", &format_args!("{}", self.eds25().bit())) + .field("eds26", &format_args!("{}", self.eds26().bit())) + .field("eds27", &format_args!("{}", self.eds27().bit())) + .field("eds28", &format_args!("{}", self.eds28().bit())) + .field("eds29", &format_args!("{}", self.eds29().bit())) + .field("eds30", &format_args!("{}", self.eds30().bit())) + .field("eds31", &format_args!("{}", self.eds31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Event detected 0"] #[inline(always)] #[must_use] - pub fn eds0(&mut self) -> EDS0_W<0> { + pub fn eds0(&mut self) -> EDS0_W { EDS0_W::new(self) } #[doc = "Bit 1 - Event detected 1"] #[inline(always)] #[must_use] - pub fn eds1(&mut self) -> EDS1_W<1> { + pub fn eds1(&mut self) -> EDS1_W { EDS1_W::new(self) } #[doc = "Bit 2 - Event detected 2"] #[inline(always)] #[must_use] - pub fn eds2(&mut self) -> EDS2_W<2> { + pub fn eds2(&mut self) -> EDS2_W { EDS2_W::new(self) } #[doc = "Bit 3 - Event detected 3"] #[inline(always)] #[must_use] - pub fn eds3(&mut self) -> EDS3_W<3> { + pub fn eds3(&mut self) -> EDS3_W { EDS3_W::new(self) } #[doc = "Bit 4 - Event detected 4"] #[inline(always)] #[must_use] - pub fn eds4(&mut self) -> EDS4_W<4> { + pub fn eds4(&mut self) -> EDS4_W { EDS4_W::new(self) } #[doc = "Bit 5 - Event detected 5"] #[inline(always)] #[must_use] - pub fn eds5(&mut self) -> EDS5_W<5> { + pub fn eds5(&mut self) -> EDS5_W { EDS5_W::new(self) } #[doc = "Bit 6 - Event detected 6"] #[inline(always)] #[must_use] - pub fn eds6(&mut self) -> EDS6_W<6> { + pub fn eds6(&mut self) -> EDS6_W { EDS6_W::new(self) } #[doc = "Bit 7 - Event detected 7"] #[inline(always)] #[must_use] - pub fn eds7(&mut self) -> EDS7_W<7> { + pub fn eds7(&mut self) -> EDS7_W { EDS7_W::new(self) } #[doc = "Bit 8 - Event detected 8"] #[inline(always)] #[must_use] - pub fn eds8(&mut self) -> EDS8_W<8> { + pub fn eds8(&mut self) -> EDS8_W { EDS8_W::new(self) } #[doc = "Bit 9 - Event detected 9"] #[inline(always)] #[must_use] - pub fn eds9(&mut self) -> EDS9_W<9> { + pub fn eds9(&mut self) -> EDS9_W { EDS9_W::new(self) } #[doc = "Bit 10 - Event detected 10"] #[inline(always)] #[must_use] - pub fn eds10(&mut self) -> EDS10_W<10> { + pub fn eds10(&mut self) -> EDS10_W { EDS10_W::new(self) } #[doc = "Bit 11 - Event detected 11"] #[inline(always)] #[must_use] - pub fn eds11(&mut self) -> EDS11_W<11> { + pub fn eds11(&mut self) -> EDS11_W { EDS11_W::new(self) } #[doc = "Bit 12 - Event detected 12"] #[inline(always)] #[must_use] - pub fn eds12(&mut self) -> EDS12_W<12> { + pub fn eds12(&mut self) -> EDS12_W { EDS12_W::new(self) } #[doc = "Bit 13 - Event detected 13"] #[inline(always)] #[must_use] - pub fn eds13(&mut self) -> EDS13_W<13> { + pub fn eds13(&mut self) -> EDS13_W { EDS13_W::new(self) } #[doc = "Bit 14 - Event detected 14"] #[inline(always)] #[must_use] - pub fn eds14(&mut self) -> EDS14_W<14> { + pub fn eds14(&mut self) -> EDS14_W { EDS14_W::new(self) } #[doc = "Bit 15 - Event detected 15"] #[inline(always)] #[must_use] - pub fn eds15(&mut self) -> EDS15_W<15> { + pub fn eds15(&mut self) -> EDS15_W { EDS15_W::new(self) } #[doc = "Bit 16 - Event detected 16"] #[inline(always)] #[must_use] - pub fn eds16(&mut self) -> EDS16_W<16> { + pub fn eds16(&mut self) -> EDS16_W { EDS16_W::new(self) } #[doc = "Bit 17 - Event detected 17"] #[inline(always)] #[must_use] - pub fn eds17(&mut self) -> EDS17_W<17> { + pub fn eds17(&mut self) -> EDS17_W { EDS17_W::new(self) } #[doc = "Bit 18 - Event detected 18"] #[inline(always)] #[must_use] - pub fn eds18(&mut self) -> EDS18_W<18> { + pub fn eds18(&mut self) -> EDS18_W { EDS18_W::new(self) } #[doc = "Bit 19 - Event detected 19"] #[inline(always)] #[must_use] - pub fn eds19(&mut self) -> EDS19_W<19> { + pub fn eds19(&mut self) -> EDS19_W { EDS19_W::new(self) } #[doc = "Bit 20 - Event detected 20"] #[inline(always)] #[must_use] - pub fn eds20(&mut self) -> EDS20_W<20> { + pub fn eds20(&mut self) -> EDS20_W { EDS20_W::new(self) } #[doc = "Bit 21 - Event detected 21"] #[inline(always)] #[must_use] - pub fn eds21(&mut self) -> EDS21_W<21> { + pub fn eds21(&mut self) -> EDS21_W { EDS21_W::new(self) } #[doc = "Bit 22 - Event detected 22"] #[inline(always)] #[must_use] - pub fn eds22(&mut self) -> EDS22_W<22> { + pub fn eds22(&mut self) -> EDS22_W { EDS22_W::new(self) } #[doc = "Bit 23 - Event detected 23"] #[inline(always)] #[must_use] - pub fn eds23(&mut self) -> EDS23_W<23> { + pub fn eds23(&mut self) -> EDS23_W { EDS23_W::new(self) } #[doc = "Bit 24 - Event detected 24"] #[inline(always)] #[must_use] - pub fn eds24(&mut self) -> EDS24_W<24> { + pub fn eds24(&mut self) -> EDS24_W { EDS24_W::new(self) } #[doc = "Bit 25 - Event detected 25"] #[inline(always)] #[must_use] - pub fn eds25(&mut self) -> EDS25_W<25> { + pub fn eds25(&mut self) -> EDS25_W { EDS25_W::new(self) } #[doc = "Bit 26 - Event detected 26"] #[inline(always)] #[must_use] - pub fn eds26(&mut self) -> EDS26_W<26> { + pub fn eds26(&mut self) -> EDS26_W { EDS26_W::new(self) } #[doc = "Bit 27 - Event detected 27"] #[inline(always)] #[must_use] - pub fn eds27(&mut self) -> EDS27_W<27> { + pub fn eds27(&mut self) -> EDS27_W { EDS27_W::new(self) } #[doc = "Bit 28 - Event detected 28"] #[inline(always)] #[must_use] - pub fn eds28(&mut self) -> EDS28_W<28> { + pub fn eds28(&mut self) -> EDS28_W { EDS28_W::new(self) } #[doc = "Bit 29 - Event detected 29"] #[inline(always)] #[must_use] - pub fn eds29(&mut self) -> EDS29_W<29> { + pub fn eds29(&mut self) -> EDS29_W { EDS29_W::new(self) } #[doc = "Bit 30 - Event detected 30"] #[inline(always)] #[must_use] - pub fn eds30(&mut self) -> EDS30_W<30> { + pub fn eds30(&mut self) -> EDS30_W { EDS30_W::new(self) } #[doc = "Bit 31 - Event detected 31"] #[inline(always)] #[must_use] - pub fn eds31(&mut self) -> EDS31_W<31> { + pub fn eds31(&mut self) -> EDS31_W { EDS31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Event Detect Status 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpeds0](index.html) module"] +#[doc = "GPIO Pin Event Detect Status 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpeds0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpeds0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPEDS0_SPEC; impl crate::RegisterSpec for GPEDS0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpeds0::R](R) reader structure"] -impl crate::Readable for GPEDS0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpeds0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpeds0::R`](R) reader structure"] +impl crate::Readable for GPEDS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpeds0::W`](W) writer structure"] impl crate::Writable for GPEDS0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2837-lpa/src/gpio/gpeds1.rs b/crates/bcm2837-lpa/src/gpio/gpeds1.rs index bcef23a..ac728c0 100644 --- a/crates/bcm2837-lpa/src/gpio/gpeds1.rs +++ b/crates/bcm2837-lpa/src/gpio/gpeds1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPEDS1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPEDS1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EDS32` reader - Event detected 32"] -pub type EDS32_R = crate::BitReader; +pub type EDS32_R = crate::BitReader; #[doc = "Field `EDS32` writer - Event detected 32"] -pub type EDS32_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS32_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS33` reader - Event detected 33"] -pub type EDS33_R = crate::BitReader; +pub type EDS33_R = crate::BitReader; #[doc = "Field `EDS33` writer - Event detected 33"] -pub type EDS33_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS33_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS34` reader - Event detected 34"] -pub type EDS34_R = crate::BitReader; +pub type EDS34_R = crate::BitReader; #[doc = "Field `EDS34` writer - Event detected 34"] -pub type EDS34_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS34_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS35` reader - Event detected 35"] -pub type EDS35_R = crate::BitReader; +pub type EDS35_R = crate::BitReader; #[doc = "Field `EDS35` writer - Event detected 35"] -pub type EDS35_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS35_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS36` reader - Event detected 36"] -pub type EDS36_R = crate::BitReader; +pub type EDS36_R = crate::BitReader; #[doc = "Field `EDS36` writer - Event detected 36"] -pub type EDS36_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS36_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS37` reader - Event detected 37"] -pub type EDS37_R = crate::BitReader; +pub type EDS37_R = crate::BitReader; #[doc = "Field `EDS37` writer - Event detected 37"] -pub type EDS37_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS37_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS38` reader - Event detected 38"] -pub type EDS38_R = crate::BitReader; +pub type EDS38_R = crate::BitReader; #[doc = "Field `EDS38` writer - Event detected 38"] -pub type EDS38_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS38_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS39` reader - Event detected 39"] -pub type EDS39_R = crate::BitReader; +pub type EDS39_R = crate::BitReader; #[doc = "Field `EDS39` writer - Event detected 39"] -pub type EDS39_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS39_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS40` reader - Event detected 40"] -pub type EDS40_R = crate::BitReader; +pub type EDS40_R = crate::BitReader; #[doc = "Field `EDS40` writer - Event detected 40"] -pub type EDS40_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS40_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS41` reader - Event detected 41"] -pub type EDS41_R = crate::BitReader; +pub type EDS41_R = crate::BitReader; #[doc = "Field `EDS41` writer - Event detected 41"] -pub type EDS41_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS41_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS42` reader - Event detected 42"] -pub type EDS42_R = crate::BitReader; +pub type EDS42_R = crate::BitReader; #[doc = "Field `EDS42` writer - Event detected 42"] -pub type EDS42_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS42_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS43` reader - Event detected 43"] -pub type EDS43_R = crate::BitReader; +pub type EDS43_R = crate::BitReader; #[doc = "Field `EDS43` writer - Event detected 43"] -pub type EDS43_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS43_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS44` reader - Event detected 44"] -pub type EDS44_R = crate::BitReader; +pub type EDS44_R = crate::BitReader; #[doc = "Field `EDS44` writer - Event detected 44"] -pub type EDS44_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS44_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS45` reader - Event detected 45"] -pub type EDS45_R = crate::BitReader; +pub type EDS45_R = crate::BitReader; #[doc = "Field `EDS45` writer - Event detected 45"] -pub type EDS45_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS45_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS46` reader - Event detected 46"] -pub type EDS46_R = crate::BitReader; +pub type EDS46_R = crate::BitReader; #[doc = "Field `EDS46` writer - Event detected 46"] -pub type EDS46_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS46_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS47` reader - Event detected 47"] -pub type EDS47_R = crate::BitReader; +pub type EDS47_R = crate::BitReader; #[doc = "Field `EDS47` writer - Event detected 47"] -pub type EDS47_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS47_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS48` reader - Event detected 48"] -pub type EDS48_R = crate::BitReader; +pub type EDS48_R = crate::BitReader; #[doc = "Field `EDS48` writer - Event detected 48"] -pub type EDS48_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS48_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS49` reader - Event detected 49"] -pub type EDS49_R = crate::BitReader; +pub type EDS49_R = crate::BitReader; #[doc = "Field `EDS49` writer - Event detected 49"] -pub type EDS49_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS49_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS50` reader - Event detected 50"] -pub type EDS50_R = crate::BitReader; +pub type EDS50_R = crate::BitReader; #[doc = "Field `EDS50` writer - Event detected 50"] -pub type EDS50_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS50_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS51` reader - Event detected 51"] -pub type EDS51_R = crate::BitReader; +pub type EDS51_R = crate::BitReader; #[doc = "Field `EDS51` writer - Event detected 51"] -pub type EDS51_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS51_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS52` reader - Event detected 52"] -pub type EDS52_R = crate::BitReader; +pub type EDS52_R = crate::BitReader; #[doc = "Field `EDS52` writer - Event detected 52"] -pub type EDS52_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS52_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EDS53` reader - Event detected 53"] -pub type EDS53_R = crate::BitReader; +pub type EDS53_R = crate::BitReader; #[doc = "Field `EDS53` writer - Event detected 53"] -pub type EDS53_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, GPEDS1_SPEC, bool, O>; +pub type EDS53_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Event detected 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { EDS53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPEDS1") + .field("eds32", &format_args!("{}", self.eds32().bit())) + .field("eds33", &format_args!("{}", self.eds33().bit())) + .field("eds34", &format_args!("{}", self.eds34().bit())) + .field("eds35", &format_args!("{}", self.eds35().bit())) + .field("eds36", &format_args!("{}", self.eds36().bit())) + .field("eds37", &format_args!("{}", self.eds37().bit())) + .field("eds38", &format_args!("{}", self.eds38().bit())) + .field("eds39", &format_args!("{}", self.eds39().bit())) + .field("eds40", &format_args!("{}", self.eds40().bit())) + .field("eds41", &format_args!("{}", self.eds41().bit())) + .field("eds42", &format_args!("{}", self.eds42().bit())) + .field("eds43", &format_args!("{}", self.eds43().bit())) + .field("eds44", &format_args!("{}", self.eds44().bit())) + .field("eds45", &format_args!("{}", self.eds45().bit())) + .field("eds46", &format_args!("{}", self.eds46().bit())) + .field("eds47", &format_args!("{}", self.eds47().bit())) + .field("eds48", &format_args!("{}", self.eds48().bit())) + .field("eds49", &format_args!("{}", self.eds49().bit())) + .field("eds50", &format_args!("{}", self.eds50().bit())) + .field("eds51", &format_args!("{}", self.eds51().bit())) + .field("eds52", &format_args!("{}", self.eds52().bit())) + .field("eds53", &format_args!("{}", self.eds53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Event detected 32"] #[inline(always)] #[must_use] - pub fn eds32(&mut self) -> EDS32_W<0> { + pub fn eds32(&mut self) -> EDS32_W { EDS32_W::new(self) } #[doc = "Bit 1 - Event detected 33"] #[inline(always)] #[must_use] - pub fn eds33(&mut self) -> EDS33_W<1> { + pub fn eds33(&mut self) -> EDS33_W { EDS33_W::new(self) } #[doc = "Bit 2 - Event detected 34"] #[inline(always)] #[must_use] - pub fn eds34(&mut self) -> EDS34_W<2> { + pub fn eds34(&mut self) -> EDS34_W { EDS34_W::new(self) } #[doc = "Bit 3 - Event detected 35"] #[inline(always)] #[must_use] - pub fn eds35(&mut self) -> EDS35_W<3> { + pub fn eds35(&mut self) -> EDS35_W { EDS35_W::new(self) } #[doc = "Bit 4 - Event detected 36"] #[inline(always)] #[must_use] - pub fn eds36(&mut self) -> EDS36_W<4> { + pub fn eds36(&mut self) -> EDS36_W { EDS36_W::new(self) } #[doc = "Bit 5 - Event detected 37"] #[inline(always)] #[must_use] - pub fn eds37(&mut self) -> EDS37_W<5> { + pub fn eds37(&mut self) -> EDS37_W { EDS37_W::new(self) } #[doc = "Bit 6 - Event detected 38"] #[inline(always)] #[must_use] - pub fn eds38(&mut self) -> EDS38_W<6> { + pub fn eds38(&mut self) -> EDS38_W { EDS38_W::new(self) } #[doc = "Bit 7 - Event detected 39"] #[inline(always)] #[must_use] - pub fn eds39(&mut self) -> EDS39_W<7> { + pub fn eds39(&mut self) -> EDS39_W { EDS39_W::new(self) } #[doc = "Bit 8 - Event detected 40"] #[inline(always)] #[must_use] - pub fn eds40(&mut self) -> EDS40_W<8> { + pub fn eds40(&mut self) -> EDS40_W { EDS40_W::new(self) } #[doc = "Bit 9 - Event detected 41"] #[inline(always)] #[must_use] - pub fn eds41(&mut self) -> EDS41_W<9> { + pub fn eds41(&mut self) -> EDS41_W { EDS41_W::new(self) } #[doc = "Bit 10 - Event detected 42"] #[inline(always)] #[must_use] - pub fn eds42(&mut self) -> EDS42_W<10> { + pub fn eds42(&mut self) -> EDS42_W { EDS42_W::new(self) } #[doc = "Bit 11 - Event detected 43"] #[inline(always)] #[must_use] - pub fn eds43(&mut self) -> EDS43_W<11> { + pub fn eds43(&mut self) -> EDS43_W { EDS43_W::new(self) } #[doc = "Bit 12 - Event detected 44"] #[inline(always)] #[must_use] - pub fn eds44(&mut self) -> EDS44_W<12> { + pub fn eds44(&mut self) -> EDS44_W { EDS44_W::new(self) } #[doc = "Bit 13 - Event detected 45"] #[inline(always)] #[must_use] - pub fn eds45(&mut self) -> EDS45_W<13> { + pub fn eds45(&mut self) -> EDS45_W { EDS45_W::new(self) } #[doc = "Bit 14 - Event detected 46"] #[inline(always)] #[must_use] - pub fn eds46(&mut self) -> EDS46_W<14> { + pub fn eds46(&mut self) -> EDS46_W { EDS46_W::new(self) } #[doc = "Bit 15 - Event detected 47"] #[inline(always)] #[must_use] - pub fn eds47(&mut self) -> EDS47_W<15> { + pub fn eds47(&mut self) -> EDS47_W { EDS47_W::new(self) } #[doc = "Bit 16 - Event detected 48"] #[inline(always)] #[must_use] - pub fn eds48(&mut self) -> EDS48_W<16> { + pub fn eds48(&mut self) -> EDS48_W { EDS48_W::new(self) } #[doc = "Bit 17 - Event detected 49"] #[inline(always)] #[must_use] - pub fn eds49(&mut self) -> EDS49_W<17> { + pub fn eds49(&mut self) -> EDS49_W { EDS49_W::new(self) } #[doc = "Bit 18 - Event detected 50"] #[inline(always)] #[must_use] - pub fn eds50(&mut self) -> EDS50_W<18> { + pub fn eds50(&mut self) -> EDS50_W { EDS50_W::new(self) } #[doc = "Bit 19 - Event detected 51"] #[inline(always)] #[must_use] - pub fn eds51(&mut self) -> EDS51_W<19> { + pub fn eds51(&mut self) -> EDS51_W { EDS51_W::new(self) } #[doc = "Bit 20 - Event detected 52"] #[inline(always)] #[must_use] - pub fn eds52(&mut self) -> EDS52_W<20> { + pub fn eds52(&mut self) -> EDS52_W { EDS52_W::new(self) } #[doc = "Bit 21 - Event detected 53"] #[inline(always)] #[must_use] - pub fn eds53(&mut self) -> EDS53_W<21> { + pub fn eds53(&mut self) -> EDS53_W { EDS53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Event Detect Status 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpeds1](index.html) module"] +#[doc = "GPIO Pin Event Detect Status 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpeds1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpeds1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPEDS1_SPEC; impl crate::RegisterSpec for GPEDS1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpeds1::R](R) reader structure"] -impl crate::Readable for GPEDS1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpeds1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpeds1::R`](R) reader structure"] +impl crate::Readable for GPEDS1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpeds1::W`](W) writer structure"] impl crate::Writable for GPEDS1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x003f_ffff; } diff --git a/crates/bcm2837-lpa/src/gpio/gpfen0.rs b/crates/bcm2837-lpa/src/gpio/gpfen0.rs index 58ded22..abcf609 100644 --- a/crates/bcm2837-lpa/src/gpio/gpfen0.rs +++ b/crates/bcm2837-lpa/src/gpio/gpfen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPFEN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFEN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FEN0` reader - Falling edge enabled 0"] -pub type FEN0_R = crate::BitReader; +pub type FEN0_R = crate::BitReader; #[doc = "Field `FEN0` writer - Falling edge enabled 0"] -pub type FEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN1` reader - Falling edge enabled 1"] -pub type FEN1_R = crate::BitReader; +pub type FEN1_R = crate::BitReader; #[doc = "Field `FEN1` writer - Falling edge enabled 1"] -pub type FEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN2` reader - Falling edge enabled 2"] -pub type FEN2_R = crate::BitReader; +pub type FEN2_R = crate::BitReader; #[doc = "Field `FEN2` writer - Falling edge enabled 2"] -pub type FEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN3` reader - Falling edge enabled 3"] -pub type FEN3_R = crate::BitReader; +pub type FEN3_R = crate::BitReader; #[doc = "Field `FEN3` writer - Falling edge enabled 3"] -pub type FEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN4` reader - Falling edge enabled 4"] -pub type FEN4_R = crate::BitReader; +pub type FEN4_R = crate::BitReader; #[doc = "Field `FEN4` writer - Falling edge enabled 4"] -pub type FEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN5` reader - Falling edge enabled 5"] -pub type FEN5_R = crate::BitReader; +pub type FEN5_R = crate::BitReader; #[doc = "Field `FEN5` writer - Falling edge enabled 5"] -pub type FEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN6` reader - Falling edge enabled 6"] -pub type FEN6_R = crate::BitReader; +pub type FEN6_R = crate::BitReader; #[doc = "Field `FEN6` writer - Falling edge enabled 6"] -pub type FEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN7` reader - Falling edge enabled 7"] -pub type FEN7_R = crate::BitReader; +pub type FEN7_R = crate::BitReader; #[doc = "Field `FEN7` writer - Falling edge enabled 7"] -pub type FEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN8` reader - Falling edge enabled 8"] -pub type FEN8_R = crate::BitReader; +pub type FEN8_R = crate::BitReader; #[doc = "Field `FEN8` writer - Falling edge enabled 8"] -pub type FEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN9` reader - Falling edge enabled 9"] -pub type FEN9_R = crate::BitReader; +pub type FEN9_R = crate::BitReader; #[doc = "Field `FEN9` writer - Falling edge enabled 9"] -pub type FEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN10` reader - Falling edge enabled 10"] -pub type FEN10_R = crate::BitReader; +pub type FEN10_R = crate::BitReader; #[doc = "Field `FEN10` writer - Falling edge enabled 10"] -pub type FEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN11` reader - Falling edge enabled 11"] -pub type FEN11_R = crate::BitReader; +pub type FEN11_R = crate::BitReader; #[doc = "Field `FEN11` writer - Falling edge enabled 11"] -pub type FEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN12` reader - Falling edge enabled 12"] -pub type FEN12_R = crate::BitReader; +pub type FEN12_R = crate::BitReader; #[doc = "Field `FEN12` writer - Falling edge enabled 12"] -pub type FEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN13` reader - Falling edge enabled 13"] -pub type FEN13_R = crate::BitReader; +pub type FEN13_R = crate::BitReader; #[doc = "Field `FEN13` writer - Falling edge enabled 13"] -pub type FEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN14` reader - Falling edge enabled 14"] -pub type FEN14_R = crate::BitReader; +pub type FEN14_R = crate::BitReader; #[doc = "Field `FEN14` writer - Falling edge enabled 14"] -pub type FEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN15` reader - Falling edge enabled 15"] -pub type FEN15_R = crate::BitReader; +pub type FEN15_R = crate::BitReader; #[doc = "Field `FEN15` writer - Falling edge enabled 15"] -pub type FEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN16` reader - Falling edge enabled 16"] -pub type FEN16_R = crate::BitReader; +pub type FEN16_R = crate::BitReader; #[doc = "Field `FEN16` writer - Falling edge enabled 16"] -pub type FEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN17` reader - Falling edge enabled 17"] -pub type FEN17_R = crate::BitReader; +pub type FEN17_R = crate::BitReader; #[doc = "Field `FEN17` writer - Falling edge enabled 17"] -pub type FEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN18` reader - Falling edge enabled 18"] -pub type FEN18_R = crate::BitReader; +pub type FEN18_R = crate::BitReader; #[doc = "Field `FEN18` writer - Falling edge enabled 18"] -pub type FEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN19` reader - Falling edge enabled 19"] -pub type FEN19_R = crate::BitReader; +pub type FEN19_R = crate::BitReader; #[doc = "Field `FEN19` writer - Falling edge enabled 19"] -pub type FEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN20` reader - Falling edge enabled 20"] -pub type FEN20_R = crate::BitReader; +pub type FEN20_R = crate::BitReader; #[doc = "Field `FEN20` writer - Falling edge enabled 20"] -pub type FEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN21` reader - Falling edge enabled 21"] -pub type FEN21_R = crate::BitReader; +pub type FEN21_R = crate::BitReader; #[doc = "Field `FEN21` writer - Falling edge enabled 21"] -pub type FEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN22` reader - Falling edge enabled 22"] -pub type FEN22_R = crate::BitReader; +pub type FEN22_R = crate::BitReader; #[doc = "Field `FEN22` writer - Falling edge enabled 22"] -pub type FEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN23` reader - Falling edge enabled 23"] -pub type FEN23_R = crate::BitReader; +pub type FEN23_R = crate::BitReader; #[doc = "Field `FEN23` writer - Falling edge enabled 23"] -pub type FEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN24` reader - Falling edge enabled 24"] -pub type FEN24_R = crate::BitReader; +pub type FEN24_R = crate::BitReader; #[doc = "Field `FEN24` writer - Falling edge enabled 24"] -pub type FEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN25` reader - Falling edge enabled 25"] -pub type FEN25_R = crate::BitReader; +pub type FEN25_R = crate::BitReader; #[doc = "Field `FEN25` writer - Falling edge enabled 25"] -pub type FEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN26` reader - Falling edge enabled 26"] -pub type FEN26_R = crate::BitReader; +pub type FEN26_R = crate::BitReader; #[doc = "Field `FEN26` writer - Falling edge enabled 26"] -pub type FEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN27` reader - Falling edge enabled 27"] -pub type FEN27_R = crate::BitReader; +pub type FEN27_R = crate::BitReader; #[doc = "Field `FEN27` writer - Falling edge enabled 27"] -pub type FEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN28` reader - Falling edge enabled 28"] -pub type FEN28_R = crate::BitReader; +pub type FEN28_R = crate::BitReader; #[doc = "Field `FEN28` writer - Falling edge enabled 28"] -pub type FEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN29` reader - Falling edge enabled 29"] -pub type FEN29_R = crate::BitReader; +pub type FEN29_R = crate::BitReader; #[doc = "Field `FEN29` writer - Falling edge enabled 29"] -pub type FEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN30` reader - Falling edge enabled 30"] -pub type FEN30_R = crate::BitReader; +pub type FEN30_R = crate::BitReader; #[doc = "Field `FEN30` writer - Falling edge enabled 30"] -pub type FEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN31` reader - Falling edge enabled 31"] -pub type FEN31_R = crate::BitReader; +pub type FEN31_R = crate::BitReader; #[doc = "Field `FEN31` writer - Falling edge enabled 31"] -pub type FEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN0_SPEC, bool, O>; +pub type FEN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Falling edge enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { FEN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFEN0") + .field("fen0", &format_args!("{}", self.fen0().bit())) + .field("fen1", &format_args!("{}", self.fen1().bit())) + .field("fen2", &format_args!("{}", self.fen2().bit())) + .field("fen3", &format_args!("{}", self.fen3().bit())) + .field("fen4", &format_args!("{}", self.fen4().bit())) + .field("fen5", &format_args!("{}", self.fen5().bit())) + .field("fen6", &format_args!("{}", self.fen6().bit())) + .field("fen7", &format_args!("{}", self.fen7().bit())) + .field("fen8", &format_args!("{}", self.fen8().bit())) + .field("fen9", &format_args!("{}", self.fen9().bit())) + .field("fen10", &format_args!("{}", self.fen10().bit())) + .field("fen11", &format_args!("{}", self.fen11().bit())) + .field("fen12", &format_args!("{}", self.fen12().bit())) + .field("fen13", &format_args!("{}", self.fen13().bit())) + .field("fen14", &format_args!("{}", self.fen14().bit())) + .field("fen15", &format_args!("{}", self.fen15().bit())) + .field("fen16", &format_args!("{}", self.fen16().bit())) + .field("fen17", &format_args!("{}", self.fen17().bit())) + .field("fen18", &format_args!("{}", self.fen18().bit())) + .field("fen19", &format_args!("{}", self.fen19().bit())) + .field("fen20", &format_args!("{}", self.fen20().bit())) + .field("fen21", &format_args!("{}", self.fen21().bit())) + .field("fen22", &format_args!("{}", self.fen22().bit())) + .field("fen23", &format_args!("{}", self.fen23().bit())) + .field("fen24", &format_args!("{}", self.fen24().bit())) + .field("fen25", &format_args!("{}", self.fen25().bit())) + .field("fen26", &format_args!("{}", self.fen26().bit())) + .field("fen27", &format_args!("{}", self.fen27().bit())) + .field("fen28", &format_args!("{}", self.fen28().bit())) + .field("fen29", &format_args!("{}", self.fen29().bit())) + .field("fen30", &format_args!("{}", self.fen30().bit())) + .field("fen31", &format_args!("{}", self.fen31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Falling edge enabled 0"] #[inline(always)] #[must_use] - pub fn fen0(&mut self) -> FEN0_W<0> { + pub fn fen0(&mut self) -> FEN0_W { FEN0_W::new(self) } #[doc = "Bit 1 - Falling edge enabled 1"] #[inline(always)] #[must_use] - pub fn fen1(&mut self) -> FEN1_W<1> { + pub fn fen1(&mut self) -> FEN1_W { FEN1_W::new(self) } #[doc = "Bit 2 - Falling edge enabled 2"] #[inline(always)] #[must_use] - pub fn fen2(&mut self) -> FEN2_W<2> { + pub fn fen2(&mut self) -> FEN2_W { FEN2_W::new(self) } #[doc = "Bit 3 - Falling edge enabled 3"] #[inline(always)] #[must_use] - pub fn fen3(&mut self) -> FEN3_W<3> { + pub fn fen3(&mut self) -> FEN3_W { FEN3_W::new(self) } #[doc = "Bit 4 - Falling edge enabled 4"] #[inline(always)] #[must_use] - pub fn fen4(&mut self) -> FEN4_W<4> { + pub fn fen4(&mut self) -> FEN4_W { FEN4_W::new(self) } #[doc = "Bit 5 - Falling edge enabled 5"] #[inline(always)] #[must_use] - pub fn fen5(&mut self) -> FEN5_W<5> { + pub fn fen5(&mut self) -> FEN5_W { FEN5_W::new(self) } #[doc = "Bit 6 - Falling edge enabled 6"] #[inline(always)] #[must_use] - pub fn fen6(&mut self) -> FEN6_W<6> { + pub fn fen6(&mut self) -> FEN6_W { FEN6_W::new(self) } #[doc = "Bit 7 - Falling edge enabled 7"] #[inline(always)] #[must_use] - pub fn fen7(&mut self) -> FEN7_W<7> { + pub fn fen7(&mut self) -> FEN7_W { FEN7_W::new(self) } #[doc = "Bit 8 - Falling edge enabled 8"] #[inline(always)] #[must_use] - pub fn fen8(&mut self) -> FEN8_W<8> { + pub fn fen8(&mut self) -> FEN8_W { FEN8_W::new(self) } #[doc = "Bit 9 - Falling edge enabled 9"] #[inline(always)] #[must_use] - pub fn fen9(&mut self) -> FEN9_W<9> { + pub fn fen9(&mut self) -> FEN9_W { FEN9_W::new(self) } #[doc = "Bit 10 - Falling edge enabled 10"] #[inline(always)] #[must_use] - pub fn fen10(&mut self) -> FEN10_W<10> { + pub fn fen10(&mut self) -> FEN10_W { FEN10_W::new(self) } #[doc = "Bit 11 - Falling edge enabled 11"] #[inline(always)] #[must_use] - pub fn fen11(&mut self) -> FEN11_W<11> { + pub fn fen11(&mut self) -> FEN11_W { FEN11_W::new(self) } #[doc = "Bit 12 - Falling edge enabled 12"] #[inline(always)] #[must_use] - pub fn fen12(&mut self) -> FEN12_W<12> { + pub fn fen12(&mut self) -> FEN12_W { FEN12_W::new(self) } #[doc = "Bit 13 - Falling edge enabled 13"] #[inline(always)] #[must_use] - pub fn fen13(&mut self) -> FEN13_W<13> { + pub fn fen13(&mut self) -> FEN13_W { FEN13_W::new(self) } #[doc = "Bit 14 - Falling edge enabled 14"] #[inline(always)] #[must_use] - pub fn fen14(&mut self) -> FEN14_W<14> { + pub fn fen14(&mut self) -> FEN14_W { FEN14_W::new(self) } #[doc = "Bit 15 - Falling edge enabled 15"] #[inline(always)] #[must_use] - pub fn fen15(&mut self) -> FEN15_W<15> { + pub fn fen15(&mut self) -> FEN15_W { FEN15_W::new(self) } #[doc = "Bit 16 - Falling edge enabled 16"] #[inline(always)] #[must_use] - pub fn fen16(&mut self) -> FEN16_W<16> { + pub fn fen16(&mut self) -> FEN16_W { FEN16_W::new(self) } #[doc = "Bit 17 - Falling edge enabled 17"] #[inline(always)] #[must_use] - pub fn fen17(&mut self) -> FEN17_W<17> { + pub fn fen17(&mut self) -> FEN17_W { FEN17_W::new(self) } #[doc = "Bit 18 - Falling edge enabled 18"] #[inline(always)] #[must_use] - pub fn fen18(&mut self) -> FEN18_W<18> { + pub fn fen18(&mut self) -> FEN18_W { FEN18_W::new(self) } #[doc = "Bit 19 - Falling edge enabled 19"] #[inline(always)] #[must_use] - pub fn fen19(&mut self) -> FEN19_W<19> { + pub fn fen19(&mut self) -> FEN19_W { FEN19_W::new(self) } #[doc = "Bit 20 - Falling edge enabled 20"] #[inline(always)] #[must_use] - pub fn fen20(&mut self) -> FEN20_W<20> { + pub fn fen20(&mut self) -> FEN20_W { FEN20_W::new(self) } #[doc = "Bit 21 - Falling edge enabled 21"] #[inline(always)] #[must_use] - pub fn fen21(&mut self) -> FEN21_W<21> { + pub fn fen21(&mut self) -> FEN21_W { FEN21_W::new(self) } #[doc = "Bit 22 - Falling edge enabled 22"] #[inline(always)] #[must_use] - pub fn fen22(&mut self) -> FEN22_W<22> { + pub fn fen22(&mut self) -> FEN22_W { FEN22_W::new(self) } #[doc = "Bit 23 - Falling edge enabled 23"] #[inline(always)] #[must_use] - pub fn fen23(&mut self) -> FEN23_W<23> { + pub fn fen23(&mut self) -> FEN23_W { FEN23_W::new(self) } #[doc = "Bit 24 - Falling edge enabled 24"] #[inline(always)] #[must_use] - pub fn fen24(&mut self) -> FEN24_W<24> { + pub fn fen24(&mut self) -> FEN24_W { FEN24_W::new(self) } #[doc = "Bit 25 - Falling edge enabled 25"] #[inline(always)] #[must_use] - pub fn fen25(&mut self) -> FEN25_W<25> { + pub fn fen25(&mut self) -> FEN25_W { FEN25_W::new(self) } #[doc = "Bit 26 - Falling edge enabled 26"] #[inline(always)] #[must_use] - pub fn fen26(&mut self) -> FEN26_W<26> { + pub fn fen26(&mut self) -> FEN26_W { FEN26_W::new(self) } #[doc = "Bit 27 - Falling edge enabled 27"] #[inline(always)] #[must_use] - pub fn fen27(&mut self) -> FEN27_W<27> { + pub fn fen27(&mut self) -> FEN27_W { FEN27_W::new(self) } #[doc = "Bit 28 - Falling edge enabled 28"] #[inline(always)] #[must_use] - pub fn fen28(&mut self) -> FEN28_W<28> { + pub fn fen28(&mut self) -> FEN28_W { FEN28_W::new(self) } #[doc = "Bit 29 - Falling edge enabled 29"] #[inline(always)] #[must_use] - pub fn fen29(&mut self) -> FEN29_W<29> { + pub fn fen29(&mut self) -> FEN29_W { FEN29_W::new(self) } #[doc = "Bit 30 - Falling edge enabled 30"] #[inline(always)] #[must_use] - pub fn fen30(&mut self) -> FEN30_W<30> { + pub fn fen30(&mut self) -> FEN30_W { FEN30_W::new(self) } #[doc = "Bit 31 - Falling edge enabled 31"] #[inline(always)] #[must_use] - pub fn fen31(&mut self) -> FEN31_W<31> { + pub fn fen31(&mut self) -> FEN31_W { FEN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Falling Edge Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfen0](index.html) module"] +#[doc = "GPIO Pin Falling Edge Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFEN0_SPEC; impl crate::RegisterSpec for GPFEN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfen0::R](R) reader structure"] -impl crate::Readable for GPFEN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfen0::R`](R) reader structure"] +impl crate::Readable for GPFEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfen0::W`](W) writer structure"] impl crate::Writable for GPFEN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpfen1.rs b/crates/bcm2837-lpa/src/gpio/gpfen1.rs index 4e4498a..d0e94e8 100644 --- a/crates/bcm2837-lpa/src/gpio/gpfen1.rs +++ b/crates/bcm2837-lpa/src/gpio/gpfen1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPFEN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFEN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FEN32` reader - Falling edge enabled 32"] -pub type FEN32_R = crate::BitReader; +pub type FEN32_R = crate::BitReader; #[doc = "Field `FEN32` writer - Falling edge enabled 32"] -pub type FEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN33` reader - Falling edge enabled 33"] -pub type FEN33_R = crate::BitReader; +pub type FEN33_R = crate::BitReader; #[doc = "Field `FEN33` writer - Falling edge enabled 33"] -pub type FEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN34` reader - Falling edge enabled 34"] -pub type FEN34_R = crate::BitReader; +pub type FEN34_R = crate::BitReader; #[doc = "Field `FEN34` writer - Falling edge enabled 34"] -pub type FEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN35` reader - Falling edge enabled 35"] -pub type FEN35_R = crate::BitReader; +pub type FEN35_R = crate::BitReader; #[doc = "Field `FEN35` writer - Falling edge enabled 35"] -pub type FEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN36` reader - Falling edge enabled 36"] -pub type FEN36_R = crate::BitReader; +pub type FEN36_R = crate::BitReader; #[doc = "Field `FEN36` writer - Falling edge enabled 36"] -pub type FEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN37` reader - Falling edge enabled 37"] -pub type FEN37_R = crate::BitReader; +pub type FEN37_R = crate::BitReader; #[doc = "Field `FEN37` writer - Falling edge enabled 37"] -pub type FEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN38` reader - Falling edge enabled 38"] -pub type FEN38_R = crate::BitReader; +pub type FEN38_R = crate::BitReader; #[doc = "Field `FEN38` writer - Falling edge enabled 38"] -pub type FEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN39` reader - Falling edge enabled 39"] -pub type FEN39_R = crate::BitReader; +pub type FEN39_R = crate::BitReader; #[doc = "Field `FEN39` writer - Falling edge enabled 39"] -pub type FEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN40` reader - Falling edge enabled 40"] -pub type FEN40_R = crate::BitReader; +pub type FEN40_R = crate::BitReader; #[doc = "Field `FEN40` writer - Falling edge enabled 40"] -pub type FEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN41` reader - Falling edge enabled 41"] -pub type FEN41_R = crate::BitReader; +pub type FEN41_R = crate::BitReader; #[doc = "Field `FEN41` writer - Falling edge enabled 41"] -pub type FEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN42` reader - Falling edge enabled 42"] -pub type FEN42_R = crate::BitReader; +pub type FEN42_R = crate::BitReader; #[doc = "Field `FEN42` writer - Falling edge enabled 42"] -pub type FEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN43` reader - Falling edge enabled 43"] -pub type FEN43_R = crate::BitReader; +pub type FEN43_R = crate::BitReader; #[doc = "Field `FEN43` writer - Falling edge enabled 43"] -pub type FEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN44` reader - Falling edge enabled 44"] -pub type FEN44_R = crate::BitReader; +pub type FEN44_R = crate::BitReader; #[doc = "Field `FEN44` writer - Falling edge enabled 44"] -pub type FEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN45` reader - Falling edge enabled 45"] -pub type FEN45_R = crate::BitReader; +pub type FEN45_R = crate::BitReader; #[doc = "Field `FEN45` writer - Falling edge enabled 45"] -pub type FEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN46` reader - Falling edge enabled 46"] -pub type FEN46_R = crate::BitReader; +pub type FEN46_R = crate::BitReader; #[doc = "Field `FEN46` writer - Falling edge enabled 46"] -pub type FEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN47` reader - Falling edge enabled 47"] -pub type FEN47_R = crate::BitReader; +pub type FEN47_R = crate::BitReader; #[doc = "Field `FEN47` writer - Falling edge enabled 47"] -pub type FEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN48` reader - Falling edge enabled 48"] -pub type FEN48_R = crate::BitReader; +pub type FEN48_R = crate::BitReader; #[doc = "Field `FEN48` writer - Falling edge enabled 48"] -pub type FEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN49` reader - Falling edge enabled 49"] -pub type FEN49_R = crate::BitReader; +pub type FEN49_R = crate::BitReader; #[doc = "Field `FEN49` writer - Falling edge enabled 49"] -pub type FEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN50` reader - Falling edge enabled 50"] -pub type FEN50_R = crate::BitReader; +pub type FEN50_R = crate::BitReader; #[doc = "Field `FEN50` writer - Falling edge enabled 50"] -pub type FEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN51` reader - Falling edge enabled 51"] -pub type FEN51_R = crate::BitReader; +pub type FEN51_R = crate::BitReader; #[doc = "Field `FEN51` writer - Falling edge enabled 51"] -pub type FEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN52` reader - Falling edge enabled 52"] -pub type FEN52_R = crate::BitReader; +pub type FEN52_R = crate::BitReader; #[doc = "Field `FEN52` writer - Falling edge enabled 52"] -pub type FEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN53` reader - Falling edge enabled 53"] -pub type FEN53_R = crate::BitReader; +pub type FEN53_R = crate::BitReader; #[doc = "Field `FEN53` writer - Falling edge enabled 53"] -pub type FEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPFEN1_SPEC, bool, O>; +pub type FEN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Falling edge enabled 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { FEN53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFEN1") + .field("fen32", &format_args!("{}", self.fen32().bit())) + .field("fen33", &format_args!("{}", self.fen33().bit())) + .field("fen34", &format_args!("{}", self.fen34().bit())) + .field("fen35", &format_args!("{}", self.fen35().bit())) + .field("fen36", &format_args!("{}", self.fen36().bit())) + .field("fen37", &format_args!("{}", self.fen37().bit())) + .field("fen38", &format_args!("{}", self.fen38().bit())) + .field("fen39", &format_args!("{}", self.fen39().bit())) + .field("fen40", &format_args!("{}", self.fen40().bit())) + .field("fen41", &format_args!("{}", self.fen41().bit())) + .field("fen42", &format_args!("{}", self.fen42().bit())) + .field("fen43", &format_args!("{}", self.fen43().bit())) + .field("fen44", &format_args!("{}", self.fen44().bit())) + .field("fen45", &format_args!("{}", self.fen45().bit())) + .field("fen46", &format_args!("{}", self.fen46().bit())) + .field("fen47", &format_args!("{}", self.fen47().bit())) + .field("fen48", &format_args!("{}", self.fen48().bit())) + .field("fen49", &format_args!("{}", self.fen49().bit())) + .field("fen50", &format_args!("{}", self.fen50().bit())) + .field("fen51", &format_args!("{}", self.fen51().bit())) + .field("fen52", &format_args!("{}", self.fen52().bit())) + .field("fen53", &format_args!("{}", self.fen53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Falling edge enabled 32"] #[inline(always)] #[must_use] - pub fn fen32(&mut self) -> FEN32_W<0> { + pub fn fen32(&mut self) -> FEN32_W { FEN32_W::new(self) } #[doc = "Bit 1 - Falling edge enabled 33"] #[inline(always)] #[must_use] - pub fn fen33(&mut self) -> FEN33_W<1> { + pub fn fen33(&mut self) -> FEN33_W { FEN33_W::new(self) } #[doc = "Bit 2 - Falling edge enabled 34"] #[inline(always)] #[must_use] - pub fn fen34(&mut self) -> FEN34_W<2> { + pub fn fen34(&mut self) -> FEN34_W { FEN34_W::new(self) } #[doc = "Bit 3 - Falling edge enabled 35"] #[inline(always)] #[must_use] - pub fn fen35(&mut self) -> FEN35_W<3> { + pub fn fen35(&mut self) -> FEN35_W { FEN35_W::new(self) } #[doc = "Bit 4 - Falling edge enabled 36"] #[inline(always)] #[must_use] - pub fn fen36(&mut self) -> FEN36_W<4> { + pub fn fen36(&mut self) -> FEN36_W { FEN36_W::new(self) } #[doc = "Bit 5 - Falling edge enabled 37"] #[inline(always)] #[must_use] - pub fn fen37(&mut self) -> FEN37_W<5> { + pub fn fen37(&mut self) -> FEN37_W { FEN37_W::new(self) } #[doc = "Bit 6 - Falling edge enabled 38"] #[inline(always)] #[must_use] - pub fn fen38(&mut self) -> FEN38_W<6> { + pub fn fen38(&mut self) -> FEN38_W { FEN38_W::new(self) } #[doc = "Bit 7 - Falling edge enabled 39"] #[inline(always)] #[must_use] - pub fn fen39(&mut self) -> FEN39_W<7> { + pub fn fen39(&mut self) -> FEN39_W { FEN39_W::new(self) } #[doc = "Bit 8 - Falling edge enabled 40"] #[inline(always)] #[must_use] - pub fn fen40(&mut self) -> FEN40_W<8> { + pub fn fen40(&mut self) -> FEN40_W { FEN40_W::new(self) } #[doc = "Bit 9 - Falling edge enabled 41"] #[inline(always)] #[must_use] - pub fn fen41(&mut self) -> FEN41_W<9> { + pub fn fen41(&mut self) -> FEN41_W { FEN41_W::new(self) } #[doc = "Bit 10 - Falling edge enabled 42"] #[inline(always)] #[must_use] - pub fn fen42(&mut self) -> FEN42_W<10> { + pub fn fen42(&mut self) -> FEN42_W { FEN42_W::new(self) } #[doc = "Bit 11 - Falling edge enabled 43"] #[inline(always)] #[must_use] - pub fn fen43(&mut self) -> FEN43_W<11> { + pub fn fen43(&mut self) -> FEN43_W { FEN43_W::new(self) } #[doc = "Bit 12 - Falling edge enabled 44"] #[inline(always)] #[must_use] - pub fn fen44(&mut self) -> FEN44_W<12> { + pub fn fen44(&mut self) -> FEN44_W { FEN44_W::new(self) } #[doc = "Bit 13 - Falling edge enabled 45"] #[inline(always)] #[must_use] - pub fn fen45(&mut self) -> FEN45_W<13> { + pub fn fen45(&mut self) -> FEN45_W { FEN45_W::new(self) } #[doc = "Bit 14 - Falling edge enabled 46"] #[inline(always)] #[must_use] - pub fn fen46(&mut self) -> FEN46_W<14> { + pub fn fen46(&mut self) -> FEN46_W { FEN46_W::new(self) } #[doc = "Bit 15 - Falling edge enabled 47"] #[inline(always)] #[must_use] - pub fn fen47(&mut self) -> FEN47_W<15> { + pub fn fen47(&mut self) -> FEN47_W { FEN47_W::new(self) } #[doc = "Bit 16 - Falling edge enabled 48"] #[inline(always)] #[must_use] - pub fn fen48(&mut self) -> FEN48_W<16> { + pub fn fen48(&mut self) -> FEN48_W { FEN48_W::new(self) } #[doc = "Bit 17 - Falling edge enabled 49"] #[inline(always)] #[must_use] - pub fn fen49(&mut self) -> FEN49_W<17> { + pub fn fen49(&mut self) -> FEN49_W { FEN49_W::new(self) } #[doc = "Bit 18 - Falling edge enabled 50"] #[inline(always)] #[must_use] - pub fn fen50(&mut self) -> FEN50_W<18> { + pub fn fen50(&mut self) -> FEN50_W { FEN50_W::new(self) } #[doc = "Bit 19 - Falling edge enabled 51"] #[inline(always)] #[must_use] - pub fn fen51(&mut self) -> FEN51_W<19> { + pub fn fen51(&mut self) -> FEN51_W { FEN51_W::new(self) } #[doc = "Bit 20 - Falling edge enabled 52"] #[inline(always)] #[must_use] - pub fn fen52(&mut self) -> FEN52_W<20> { + pub fn fen52(&mut self) -> FEN52_W { FEN52_W::new(self) } #[doc = "Bit 21 - Falling edge enabled 53"] #[inline(always)] #[must_use] - pub fn fen53(&mut self) -> FEN53_W<21> { + pub fn fen53(&mut self) -> FEN53_W { FEN53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Falling Edge Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfen1](index.html) module"] +#[doc = "GPIO Pin Falling Edge Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFEN1_SPEC; impl crate::RegisterSpec for GPFEN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfen1::R](R) reader structure"] -impl crate::Readable for GPFEN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfen1::R`](R) reader structure"] +impl crate::Readable for GPFEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfen1::W`](W) writer structure"] impl crate::Writable for GPFEN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpfsel0.rs b/crates/bcm2837-lpa/src/gpio/gpfsel0.rs index 4109144..dcdf15a 100644 --- a/crates/bcm2837-lpa/src/gpio/gpfsel0.rs +++ b/crates/bcm2837-lpa/src/gpio/gpfsel0.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL0` reader - Function Select 0"] -pub type FSEL0_R = crate::FieldReader; +pub type FSEL0_R = crate::FieldReader; #[doc = "Function Select 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL0_A { + type Ux = u8; +} impl FSEL0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL0_A { + pub const fn variant(&self) -> FSEL0_A { match self.bits { 0 => FSEL0_A::INPUT, 1 => FSEL0_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL0_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL0_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL0_A::OUTPUT } - #[doc = "Checks if the value of the field is `SDA0`"] + #[doc = "Pin is connected to SDA0"] #[inline(always)] pub fn is_sda0(&self) -> bool { *self == FSEL0_A::SDA0 } - #[doc = "Checks if the value of the field is `SA5`"] + #[doc = "Pin is connected to SA5"] #[inline(always)] pub fn is_sa5(&self) -> bool { *self == FSEL0_A::SA5 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL0_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL0_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL0_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL0_A::RESERVED5 } } #[doc = "Field `FSEL0` writer - Function Select 0"] -pub type FSEL0_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL0_A, 3, O>; -impl<'a, const O: u8> FSEL0_W<'a, O> { +pub type FSEL0_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL0_A>; +impl<'a, REG, const O: u8> FSEL0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL0_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL0_A::OUTPUT) } #[doc = "Pin is connected to SDA0"] #[inline(always)] - pub fn sda0(self) -> &'a mut W { + pub fn sda0(self) -> &'a mut crate::W { self.variant(FSEL0_A::SDA0) } #[doc = "Pin is connected to SA5"] #[inline(always)] - pub fn sa5(self) -> &'a mut W { + pub fn sa5(self) -> &'a mut crate::W { self.variant(FSEL0_A::SA5) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL0_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL0_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL0_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL0_A::RESERVED5) } } #[doc = "Field `FSEL1` reader - Function Select 1"] -pub type FSEL1_R = crate::FieldReader; +pub type FSEL1_R = crate::FieldReader; #[doc = "Function Select 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL1_A { + type Ux = u8; +} impl FSEL1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL1_A { + pub const fn variant(&self) -> FSEL1_A { match self.bits { 0 => FSEL1_A::INPUT, 1 => FSEL1_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL1_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL1_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL1_A::OUTPUT } - #[doc = "Checks if the value of the field is `SCL0`"] + #[doc = "Pin is connected to SCL0"] #[inline(always)] pub fn is_scl0(&self) -> bool { *self == FSEL1_A::SCL0 } - #[doc = "Checks if the value of the field is `SA4`"] + #[doc = "Pin is connected to SA4"] #[inline(always)] pub fn is_sa4(&self) -> bool { *self == FSEL1_A::SA4 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL1_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL1_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL1_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL1_A::RESERVED5 } } #[doc = "Field `FSEL1` writer - Function Select 1"] -pub type FSEL1_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL1_A, 3, O>; -impl<'a, const O: u8> FSEL1_W<'a, O> { +pub type FSEL1_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL1_A>; +impl<'a, REG, const O: u8> FSEL1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL1_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL1_A::OUTPUT) } #[doc = "Pin is connected to SCL0"] #[inline(always)] - pub fn scl0(self) -> &'a mut W { + pub fn scl0(self) -> &'a mut crate::W { self.variant(FSEL1_A::SCL0) } #[doc = "Pin is connected to SA4"] #[inline(always)] - pub fn sa4(self) -> &'a mut W { + pub fn sa4(self) -> &'a mut crate::W { self.variant(FSEL1_A::SA4) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL1_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL1_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL1_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL1_A::RESERVED5) } } #[doc = "Field `FSEL2` reader - Function Select 2"] -pub type FSEL2_R = crate::FieldReader; +pub type FSEL2_R = crate::FieldReader; #[doc = "Function Select 2"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL2_A { + type Ux = u8; +} impl FSEL2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL2_A { + pub const fn variant(&self) -> FSEL2_A { match self.bits { 0 => FSEL2_A::INPUT, 1 => FSEL2_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL2_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL2_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL2_A::OUTPUT } - #[doc = "Checks if the value of the field is `SDA1`"] + #[doc = "Pin is connected to SDA1"] #[inline(always)] pub fn is_sda1(&self) -> bool { *self == FSEL2_A::SDA1 } - #[doc = "Checks if the value of the field is `SA3`"] + #[doc = "Pin is connected to SA3"] #[inline(always)] pub fn is_sa3(&self) -> bool { *self == FSEL2_A::SA3 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL2_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL2_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL2_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL2_A::RESERVED5 } } #[doc = "Field `FSEL2` writer - Function Select 2"] -pub type FSEL2_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL2_A, 3, O>; -impl<'a, const O: u8> FSEL2_W<'a, O> { +pub type FSEL2_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL2_A>; +impl<'a, REG, const O: u8> FSEL2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL2_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL2_A::OUTPUT) } #[doc = "Pin is connected to SDA1"] #[inline(always)] - pub fn sda1(self) -> &'a mut W { + pub fn sda1(self) -> &'a mut crate::W { self.variant(FSEL2_A::SDA1) } #[doc = "Pin is connected to SA3"] #[inline(always)] - pub fn sa3(self) -> &'a mut W { + pub fn sa3(self) -> &'a mut crate::W { self.variant(FSEL2_A::SA3) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL2_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL2_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL2_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL2_A::RESERVED5) } } #[doc = "Field `FSEL3` reader - Function Select 3"] -pub type FSEL3_R = crate::FieldReader; +pub type FSEL3_R = crate::FieldReader; #[doc = "Function Select 3"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL3_A { + type Ux = u8; +} impl FSEL3_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL3_A { + pub const fn variant(&self) -> FSEL3_A { match self.bits { 0 => FSEL3_A::INPUT, 1 => FSEL3_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL3_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL3_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL3_A::OUTPUT } - #[doc = "Checks if the value of the field is `SCL1`"] + #[doc = "Pin is connected to SCL1"] #[inline(always)] pub fn is_scl1(&self) -> bool { *self == FSEL3_A::SCL1 } - #[doc = "Checks if the value of the field is `SA2`"] + #[doc = "Pin is connected to SA2"] #[inline(always)] pub fn is_sa2(&self) -> bool { *self == FSEL3_A::SA2 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL3_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL3_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL3_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL3_A::RESERVED5 } } #[doc = "Field `FSEL3` writer - Function Select 3"] -pub type FSEL3_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL3_A, 3, O>; -impl<'a, const O: u8> FSEL3_W<'a, O> { +pub type FSEL3_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL3_A>; +impl<'a, REG, const O: u8> FSEL3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL3_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL3_A::OUTPUT) } #[doc = "Pin is connected to SCL1"] #[inline(always)] - pub fn scl1(self) -> &'a mut W { + pub fn scl1(self) -> &'a mut crate::W { self.variant(FSEL3_A::SCL1) } #[doc = "Pin is connected to SA2"] #[inline(always)] - pub fn sa2(self) -> &'a mut W { + pub fn sa2(self) -> &'a mut crate::W { self.variant(FSEL3_A::SA2) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL3_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL3_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL3_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL3_A::RESERVED5) } } #[doc = "Field `FSEL4` reader - Function Select 4"] -pub type FSEL4_R = crate::FieldReader; +pub type FSEL4_R = crate::FieldReader; #[doc = "Function Select 4"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL4_A { + type Ux = u8; +} impl FSEL4_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL4_A { + pub const fn variant(&self) -> FSEL4_A { match self.bits { 0 => FSEL4_A::INPUT, 1 => FSEL4_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL4_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL4_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL4_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK0`"] + #[doc = "Pin is connected to GPCLK0"] #[inline(always)] pub fn is_gpclk0(&self) -> bool { *self == FSEL4_A::GPCLK0 } - #[doc = "Checks if the value of the field is `SA1`"] + #[doc = "Pin is connected to SA1"] #[inline(always)] pub fn is_sa1(&self) -> bool { *self == FSEL4_A::SA1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL4_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL4_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL4_A::RESERVED4 } - #[doc = "Checks if the value of the field is `ARM_TDI`"] + #[doc = "Pin is connected to ARM_TDI"] #[inline(always)] pub fn is_arm_tdi(&self) -> bool { *self == FSEL4_A::ARM_TDI } } #[doc = "Field `FSEL4` writer - Function Select 4"] -pub type FSEL4_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL4_A, 3, O>; -impl<'a, const O: u8> FSEL4_W<'a, O> { +pub type FSEL4_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL4_A>; +impl<'a, REG, const O: u8> FSEL4_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL4_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL4_A::OUTPUT) } #[doc = "Pin is connected to GPCLK0"] #[inline(always)] - pub fn gpclk0(self) -> &'a mut W { + pub fn gpclk0(self) -> &'a mut crate::W { self.variant(FSEL4_A::GPCLK0) } #[doc = "Pin is connected to SA1"] #[inline(always)] - pub fn sa1(self) -> &'a mut W { + pub fn sa1(self) -> &'a mut crate::W { self.variant(FSEL4_A::SA1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL4_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL4_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL4_A::RESERVED4) } #[doc = "Pin is connected to ARM_TDI"] #[inline(always)] - pub fn arm_tdi(self) -> &'a mut W { + pub fn arm_tdi(self) -> &'a mut crate::W { self.variant(FSEL4_A::ARM_TDI) } } #[doc = "Field `FSEL5` reader - Function Select 5"] -pub type FSEL5_R = crate::FieldReader; +pub type FSEL5_R = crate::FieldReader; #[doc = "Function Select 5"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL5_A { + type Ux = u8; +} impl FSEL5_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL5_A { + pub const fn variant(&self) -> FSEL5_A { match self.bits { 0 => FSEL5_A::INPUT, 1 => FSEL5_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL5_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL5_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL5_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK1`"] + #[doc = "Pin is connected to GPCLK1"] #[inline(always)] pub fn is_gpclk1(&self) -> bool { *self == FSEL5_A::GPCLK1 } - #[doc = "Checks if the value of the field is `SA0`"] + #[doc = "Pin is connected to SA0"] #[inline(always)] pub fn is_sa0(&self) -> bool { *self == FSEL5_A::SA0 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL5_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL5_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL5_A::RESERVED4 } - #[doc = "Checks if the value of the field is `ARM_TDO`"] + #[doc = "Pin is connected to ARM_TDO"] #[inline(always)] pub fn is_arm_tdo(&self) -> bool { *self == FSEL5_A::ARM_TDO } } #[doc = "Field `FSEL5` writer - Function Select 5"] -pub type FSEL5_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL5_A, 3, O>; -impl<'a, const O: u8> FSEL5_W<'a, O> { +pub type FSEL5_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL5_A>; +impl<'a, REG, const O: u8> FSEL5_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL5_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL5_A::OUTPUT) } #[doc = "Pin is connected to GPCLK1"] #[inline(always)] - pub fn gpclk1(self) -> &'a mut W { + pub fn gpclk1(self) -> &'a mut crate::W { self.variant(FSEL5_A::GPCLK1) } #[doc = "Pin is connected to SA0"] #[inline(always)] - pub fn sa0(self) -> &'a mut W { + pub fn sa0(self) -> &'a mut crate::W { self.variant(FSEL5_A::SA0) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL5_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL5_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL5_A::RESERVED4) } #[doc = "Pin is connected to ARM_TDO"] #[inline(always)] - pub fn arm_tdo(self) -> &'a mut W { + pub fn arm_tdo(self) -> &'a mut crate::W { self.variant(FSEL5_A::ARM_TDO) } } #[doc = "Field `FSEL6` reader - Function Select 6"] -pub type FSEL6_R = crate::FieldReader; +pub type FSEL6_R = crate::FieldReader; #[doc = "Function Select 6"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL6_A { + type Ux = u8; +} impl FSEL6_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL6_A { + pub const fn variant(&self) -> FSEL6_A { match self.bits { 0 => FSEL6_A::INPUT, 1 => FSEL6_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL6_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL6_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL6_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK2`"] + #[doc = "Pin is connected to GPCLK2"] #[inline(always)] pub fn is_gpclk2(&self) -> bool { *self == FSEL6_A::GPCLK2 } - #[doc = "Checks if the value of the field is `SOE_N`"] + #[doc = "Pin is connected to SOE_N"] #[inline(always)] pub fn is_soe_n(&self) -> bool { *self == FSEL6_A::SOE_N } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL6_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL6_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL6_A::RESERVED4 } - #[doc = "Checks if the value of the field is `ARM_RTCK`"] + #[doc = "Pin is connected to ARM_RTCK"] #[inline(always)] pub fn is_arm_rtck(&self) -> bool { *self == FSEL6_A::ARM_RTCK } } #[doc = "Field `FSEL6` writer - Function Select 6"] -pub type FSEL6_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL6_A, 3, O>; -impl<'a, const O: u8> FSEL6_W<'a, O> { +pub type FSEL6_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL6_A>; +impl<'a, REG, const O: u8> FSEL6_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL6_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL6_A::OUTPUT) } #[doc = "Pin is connected to GPCLK2"] #[inline(always)] - pub fn gpclk2(self) -> &'a mut W { + pub fn gpclk2(self) -> &'a mut crate::W { self.variant(FSEL6_A::GPCLK2) } #[doc = "Pin is connected to SOE_N"] #[inline(always)] - pub fn soe_n(self) -> &'a mut W { + pub fn soe_n(self) -> &'a mut crate::W { self.variant(FSEL6_A::SOE_N) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL6_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL6_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL6_A::RESERVED4) } #[doc = "Pin is connected to ARM_RTCK"] #[inline(always)] - pub fn arm_rtck(self) -> &'a mut W { + pub fn arm_rtck(self) -> &'a mut crate::W { self.variant(FSEL6_A::ARM_RTCK) } } #[doc = "Field `FSEL7` reader - Function Select 7"] -pub type FSEL7_R = crate::FieldReader; +pub type FSEL7_R = crate::FieldReader; #[doc = "Function Select 7"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL7_A { + type Ux = u8; +} impl FSEL7_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL7_A { + pub const fn variant(&self) -> FSEL7_A { match self.bits { 0 => FSEL7_A::INPUT, 1 => FSEL7_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL7_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL7_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL7_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_CE1_N`"] + #[doc = "Pin is connected to SPI0_CE1_N"] #[inline(always)] pub fn is_spi0_ce1_n(&self) -> bool { *self == FSEL7_A::SPI0_CE1_N } - #[doc = "Checks if the value of the field is `SWE_N`"] + #[doc = "Pin is connected to SWE_N"] #[inline(always)] pub fn is_swe_n(&self) -> bool { *self == FSEL7_A::SWE_N } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL7_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL7_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL7_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL7_A::RESERVED5 } } #[doc = "Field `FSEL7` writer - Function Select 7"] -pub type FSEL7_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL7_A, 3, O>; -impl<'a, const O: u8> FSEL7_W<'a, O> { +pub type FSEL7_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL7_A>; +impl<'a, REG, const O: u8> FSEL7_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL7_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL7_A::OUTPUT) } #[doc = "Pin is connected to SPI0_CE1_N"] #[inline(always)] - pub fn spi0_ce1_n(self) -> &'a mut W { + pub fn spi0_ce1_n(self) -> &'a mut crate::W { self.variant(FSEL7_A::SPI0_CE1_N) } #[doc = "Pin is connected to SWE_N"] #[inline(always)] - pub fn swe_n(self) -> &'a mut W { + pub fn swe_n(self) -> &'a mut crate::W { self.variant(FSEL7_A::SWE_N) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL7_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL7_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL7_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL7_A::RESERVED5) } } #[doc = "Field `FSEL8` reader - Function Select 8"] -pub type FSEL8_R = crate::FieldReader; +pub type FSEL8_R = crate::FieldReader; #[doc = "Function Select 8"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL8_A { + type Ux = u8; +} impl FSEL8_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL8_A { + pub const fn variant(&self) -> FSEL8_A { match self.bits { 0 => FSEL8_A::INPUT, 1 => FSEL8_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL8_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL8_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL8_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_CE0_N`"] + #[doc = "Pin is connected to SPI0_CE0_N"] #[inline(always)] pub fn is_spi0_ce0_n(&self) -> bool { *self == FSEL8_A::SPI0_CE0_N } - #[doc = "Checks if the value of the field is `SD0`"] + #[doc = "Pin is connected to SD0"] #[inline(always)] pub fn is_sd0(&self) -> bool { *self == FSEL8_A::SD0 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL8_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL8_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL8_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL8_A::RESERVED5 } } #[doc = "Field `FSEL8` writer - Function Select 8"] -pub type FSEL8_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL8_A, 3, O>; -impl<'a, const O: u8> FSEL8_W<'a, O> { +pub type FSEL8_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL8_A>; +impl<'a, REG, const O: u8> FSEL8_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL8_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL8_A::OUTPUT) } #[doc = "Pin is connected to SPI0_CE0_N"] #[inline(always)] - pub fn spi0_ce0_n(self) -> &'a mut W { + pub fn spi0_ce0_n(self) -> &'a mut crate::W { self.variant(FSEL8_A::SPI0_CE0_N) } #[doc = "Pin is connected to SD0"] #[inline(always)] - pub fn sd0(self) -> &'a mut W { + pub fn sd0(self) -> &'a mut crate::W { self.variant(FSEL8_A::SD0) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL8_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL8_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL8_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL8_A::RESERVED5) } } #[doc = "Field `FSEL9` reader - Function Select 9"] -pub type FSEL9_R = crate::FieldReader; +pub type FSEL9_R = crate::FieldReader; #[doc = "Function Select 9"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL9_A { + type Ux = u8; +} impl FSEL9_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL9_A { + pub const fn variant(&self) -> FSEL9_A { match self.bits { 0 => FSEL9_A::INPUT, 1 => FSEL9_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL9_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL9_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL9_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_MISO`"] + #[doc = "Pin is connected to SPI0_MISO"] #[inline(always)] pub fn is_spi0_miso(&self) -> bool { *self == FSEL9_A::SPI0_MISO } - #[doc = "Checks if the value of the field is `SD1`"] + #[doc = "Pin is connected to SD1"] #[inline(always)] pub fn is_sd1(&self) -> bool { *self == FSEL9_A::SD1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL9_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL9_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL9_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL9_A::RESERVED5 } } #[doc = "Field `FSEL9` writer - Function Select 9"] -pub type FSEL9_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL0_SPEC, u8, FSEL9_A, 3, O>; -impl<'a, const O: u8> FSEL9_W<'a, O> { +pub type FSEL9_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL9_A>; +impl<'a, REG, const O: u8> FSEL9_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL9_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL9_A::OUTPUT) } #[doc = "Pin is connected to SPI0_MISO"] #[inline(always)] - pub fn spi0_miso(self) -> &'a mut W { + pub fn spi0_miso(self) -> &'a mut crate::W { self.variant(FSEL9_A::SPI0_MISO) } #[doc = "Pin is connected to SD1"] #[inline(always)] - pub fn sd1(self) -> &'a mut W { + pub fn sd1(self) -> &'a mut crate::W { self.variant(FSEL9_A::SD1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL9_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL9_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL9_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL9_A::RESERVED5) } } @@ -1396,86 +1424,108 @@ impl R { FSEL9_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL0") + .field("fsel0", &format_args!("{}", self.fsel0().bits())) + .field("fsel1", &format_args!("{}", self.fsel1().bits())) + .field("fsel2", &format_args!("{}", self.fsel2().bits())) + .field("fsel3", &format_args!("{}", self.fsel3().bits())) + .field("fsel4", &format_args!("{}", self.fsel4().bits())) + .field("fsel5", &format_args!("{}", self.fsel5().bits())) + .field("fsel6", &format_args!("{}", self.fsel6().bits())) + .field("fsel7", &format_args!("{}", self.fsel7().bits())) + .field("fsel8", &format_args!("{}", self.fsel8().bits())) + .field("fsel9", &format_args!("{}", self.fsel9().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 0"] #[inline(always)] #[must_use] - pub fn fsel0(&mut self) -> FSEL0_W<0> { + pub fn fsel0(&mut self) -> FSEL0_W { FSEL0_W::new(self) } #[doc = "Bits 3:5 - Function Select 1"] #[inline(always)] #[must_use] - pub fn fsel1(&mut self) -> FSEL1_W<3> { + pub fn fsel1(&mut self) -> FSEL1_W { FSEL1_W::new(self) } #[doc = "Bits 6:8 - Function Select 2"] #[inline(always)] #[must_use] - pub fn fsel2(&mut self) -> FSEL2_W<6> { + pub fn fsel2(&mut self) -> FSEL2_W { FSEL2_W::new(self) } #[doc = "Bits 9:11 - Function Select 3"] #[inline(always)] #[must_use] - pub fn fsel3(&mut self) -> FSEL3_W<9> { + pub fn fsel3(&mut self) -> FSEL3_W { FSEL3_W::new(self) } #[doc = "Bits 12:14 - Function Select 4"] #[inline(always)] #[must_use] - pub fn fsel4(&mut self) -> FSEL4_W<12> { + pub fn fsel4(&mut self) -> FSEL4_W { FSEL4_W::new(self) } #[doc = "Bits 15:17 - Function Select 5"] #[inline(always)] #[must_use] - pub fn fsel5(&mut self) -> FSEL5_W<15> { + pub fn fsel5(&mut self) -> FSEL5_W { FSEL5_W::new(self) } #[doc = "Bits 18:20 - Function Select 6"] #[inline(always)] #[must_use] - pub fn fsel6(&mut self) -> FSEL6_W<18> { + pub fn fsel6(&mut self) -> FSEL6_W { FSEL6_W::new(self) } #[doc = "Bits 21:23 - Function Select 7"] #[inline(always)] #[must_use] - pub fn fsel7(&mut self) -> FSEL7_W<21> { + pub fn fsel7(&mut self) -> FSEL7_W { FSEL7_W::new(self) } #[doc = "Bits 24:26 - Function Select 8"] #[inline(always)] #[must_use] - pub fn fsel8(&mut self) -> FSEL8_W<24> { + pub fn fsel8(&mut self) -> FSEL8_W { FSEL8_W::new(self) } #[doc = "Bits 27:29 - Function Select 9"] #[inline(always)] #[must_use] - pub fn fsel9(&mut self) -> FSEL9_W<27> { + pub fn fsel9(&mut self) -> FSEL9_W { FSEL9_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel0](index.html) module"] +#[doc = "GPIO Function Select 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL0_SPEC; impl crate::RegisterSpec for GPFSEL0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel0::R](R) reader structure"] -impl crate::Readable for GPFSEL0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel0::R`](R) reader structure"] +impl crate::Readable for GPFSEL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel0::W`](W) writer structure"] impl crate::Writable for GPFSEL0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpfsel1.rs b/crates/bcm2837-lpa/src/gpio/gpfsel1.rs index 170dd75..acb33a1 100644 --- a/crates/bcm2837-lpa/src/gpio/gpfsel1.rs +++ b/crates/bcm2837-lpa/src/gpio/gpfsel1.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL10` reader - Function Select 10"] -pub type FSEL10_R = crate::FieldReader; +pub type FSEL10_R = crate::FieldReader; #[doc = "Function Select 10"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL10_A { + type Ux = u8; +} impl FSEL10_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL10_A { + pub const fn variant(&self) -> FSEL10_A { match self.bits { 0 => FSEL10_A::INPUT, 1 => FSEL10_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL10_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL10_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL10_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_MOSI`"] + #[doc = "Pin is connected to SPI0_MOSI"] #[inline(always)] pub fn is_spi0_mosi(&self) -> bool { *self == FSEL10_A::SPI0_MOSI } - #[doc = "Checks if the value of the field is `SD2`"] + #[doc = "Pin is connected to SD2"] #[inline(always)] pub fn is_sd2(&self) -> bool { *self == FSEL10_A::SD2 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL10_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL10_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL10_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL10_A::RESERVED5 } } #[doc = "Field `FSEL10` writer - Function Select 10"] -pub type FSEL10_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL10_A, 3, O>; -impl<'a, const O: u8> FSEL10_W<'a, O> { +pub type FSEL10_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL10_A>; +impl<'a, REG, const O: u8> FSEL10_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL10_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL10_A::OUTPUT) } #[doc = "Pin is connected to SPI0_MOSI"] #[inline(always)] - pub fn spi0_mosi(self) -> &'a mut W { + pub fn spi0_mosi(self) -> &'a mut crate::W { self.variant(FSEL10_A::SPI0_MOSI) } #[doc = "Pin is connected to SD2"] #[inline(always)] - pub fn sd2(self) -> &'a mut W { + pub fn sd2(self) -> &'a mut crate::W { self.variant(FSEL10_A::SD2) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL10_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL10_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL10_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL10_A::RESERVED5) } } #[doc = "Field `FSEL11` reader - Function Select 11"] -pub type FSEL11_R = crate::FieldReader; +pub type FSEL11_R = crate::FieldReader; #[doc = "Function Select 11"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL11_A { + type Ux = u8; +} impl FSEL11_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL11_A { + pub const fn variant(&self) -> FSEL11_A { match self.bits { 0 => FSEL11_A::INPUT, 1 => FSEL11_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL11_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL11_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL11_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_SCLK`"] + #[doc = "Pin is connected to SPI0_SCLK"] #[inline(always)] pub fn is_spi0_sclk(&self) -> bool { *self == FSEL11_A::SPI0_SCLK } - #[doc = "Checks if the value of the field is `SD3`"] + #[doc = "Pin is connected to SD3"] #[inline(always)] pub fn is_sd3(&self) -> bool { *self == FSEL11_A::SD3 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL11_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL11_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL11_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL11_A::RESERVED5 } } #[doc = "Field `FSEL11` writer - Function Select 11"] -pub type FSEL11_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL11_A, 3, O>; -impl<'a, const O: u8> FSEL11_W<'a, O> { +pub type FSEL11_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL11_A>; +impl<'a, REG, const O: u8> FSEL11_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL11_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL11_A::OUTPUT) } #[doc = "Pin is connected to SPI0_SCLK"] #[inline(always)] - pub fn spi0_sclk(self) -> &'a mut W { + pub fn spi0_sclk(self) -> &'a mut crate::W { self.variant(FSEL11_A::SPI0_SCLK) } #[doc = "Pin is connected to SD3"] #[inline(always)] - pub fn sd3(self) -> &'a mut W { + pub fn sd3(self) -> &'a mut crate::W { self.variant(FSEL11_A::SD3) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL11_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL11_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL11_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL11_A::RESERVED5) } } #[doc = "Field `FSEL12` reader - Function Select 12"] -pub type FSEL12_R = crate::FieldReader; +pub type FSEL12_R = crate::FieldReader; #[doc = "Function Select 12"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL12_A { + type Ux = u8; +} impl FSEL12_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL12_A { + pub const fn variant(&self) -> FSEL12_A { match self.bits { 0 => FSEL12_A::INPUT, 1 => FSEL12_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL12_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL12_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL12_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM0_0`"] + #[doc = "Pin is connected to PWM0_0"] #[inline(always)] pub fn is_pwm0_0(&self) -> bool { *self == FSEL12_A::PWM0_0 } - #[doc = "Checks if the value of the field is `SD4`"] + #[doc = "Pin is connected to SD4"] #[inline(always)] pub fn is_sd4(&self) -> bool { *self == FSEL12_A::SD4 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL12_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL12_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL12_A::RESERVED4 } - #[doc = "Checks if the value of the field is `ARM_TMS`"] + #[doc = "Pin is connected to ARM_TMS"] #[inline(always)] pub fn is_arm_tms(&self) -> bool { *self == FSEL12_A::ARM_TMS } } #[doc = "Field `FSEL12` writer - Function Select 12"] -pub type FSEL12_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL12_A, 3, O>; -impl<'a, const O: u8> FSEL12_W<'a, O> { +pub type FSEL12_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL12_A>; +impl<'a, REG, const O: u8> FSEL12_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL12_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL12_A::OUTPUT) } #[doc = "Pin is connected to PWM0_0"] #[inline(always)] - pub fn pwm0_0(self) -> &'a mut W { + pub fn pwm0_0(self) -> &'a mut crate::W { self.variant(FSEL12_A::PWM0_0) } #[doc = "Pin is connected to SD4"] #[inline(always)] - pub fn sd4(self) -> &'a mut W { + pub fn sd4(self) -> &'a mut crate::W { self.variant(FSEL12_A::SD4) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL12_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL12_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL12_A::RESERVED4) } #[doc = "Pin is connected to ARM_TMS"] #[inline(always)] - pub fn arm_tms(self) -> &'a mut W { + pub fn arm_tms(self) -> &'a mut crate::W { self.variant(FSEL12_A::ARM_TMS) } } #[doc = "Field `FSEL13` reader - Function Select 13"] -pub type FSEL13_R = crate::FieldReader; +pub type FSEL13_R = crate::FieldReader; #[doc = "Function Select 13"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL13_A { + type Ux = u8; +} impl FSEL13_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL13_A { + pub const fn variant(&self) -> FSEL13_A { match self.bits { 0 => FSEL13_A::INPUT, 1 => FSEL13_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL13_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL13_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL13_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM0_1`"] + #[doc = "Pin is connected to PWM0_1"] #[inline(always)] pub fn is_pwm0_1(&self) -> bool { *self == FSEL13_A::PWM0_1 } - #[doc = "Checks if the value of the field is `SD5`"] + #[doc = "Pin is connected to SD5"] #[inline(always)] pub fn is_sd5(&self) -> bool { *self == FSEL13_A::SD5 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL13_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL13_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL13_A::RESERVED4 } - #[doc = "Checks if the value of the field is `ARM_TCK`"] + #[doc = "Pin is connected to ARM_TCK"] #[inline(always)] pub fn is_arm_tck(&self) -> bool { *self == FSEL13_A::ARM_TCK } } #[doc = "Field `FSEL13` writer - Function Select 13"] -pub type FSEL13_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL13_A, 3, O>; -impl<'a, const O: u8> FSEL13_W<'a, O> { +pub type FSEL13_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL13_A>; +impl<'a, REG, const O: u8> FSEL13_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL13_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL13_A::OUTPUT) } #[doc = "Pin is connected to PWM0_1"] #[inline(always)] - pub fn pwm0_1(self) -> &'a mut W { + pub fn pwm0_1(self) -> &'a mut crate::W { self.variant(FSEL13_A::PWM0_1) } #[doc = "Pin is connected to SD5"] #[inline(always)] - pub fn sd5(self) -> &'a mut W { + pub fn sd5(self) -> &'a mut crate::W { self.variant(FSEL13_A::SD5) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL13_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL13_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL13_A::RESERVED4) } #[doc = "Pin is connected to ARM_TCK"] #[inline(always)] - pub fn arm_tck(self) -> &'a mut W { + pub fn arm_tck(self) -> &'a mut crate::W { self.variant(FSEL13_A::ARM_TCK) } } #[doc = "Field `FSEL14` reader - Function Select 14"] -pub type FSEL14_R = crate::FieldReader; +pub type FSEL14_R = crate::FieldReader; #[doc = "Function Select 14"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL14_A { + type Ux = u8; +} impl FSEL14_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL14_A { + pub const fn variant(&self) -> FSEL14_A { match self.bits { 0 => FSEL14_A::INPUT, 1 => FSEL14_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL14_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL14_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL14_A::OUTPUT } - #[doc = "Checks if the value of the field is `TXD0`"] + #[doc = "Pin is connected to TXD0"] #[inline(always)] pub fn is_txd0(&self) -> bool { *self == FSEL14_A::TXD0 } - #[doc = "Checks if the value of the field is `SD6`"] + #[doc = "Pin is connected to SD6"] #[inline(always)] pub fn is_sd6(&self) -> bool { *self == FSEL14_A::SD6 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL14_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL14_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL14_A::RESERVED4 } - #[doc = "Checks if the value of the field is `TXD1`"] + #[doc = "Pin is connected to TXD1"] #[inline(always)] pub fn is_txd1(&self) -> bool { *self == FSEL14_A::TXD1 } } #[doc = "Field `FSEL14` writer - Function Select 14"] -pub type FSEL14_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL14_A, 3, O>; -impl<'a, const O: u8> FSEL14_W<'a, O> { +pub type FSEL14_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL14_A>; +impl<'a, REG, const O: u8> FSEL14_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL14_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL14_A::OUTPUT) } #[doc = "Pin is connected to TXD0"] #[inline(always)] - pub fn txd0(self) -> &'a mut W { + pub fn txd0(self) -> &'a mut crate::W { self.variant(FSEL14_A::TXD0) } #[doc = "Pin is connected to SD6"] #[inline(always)] - pub fn sd6(self) -> &'a mut W { + pub fn sd6(self) -> &'a mut crate::W { self.variant(FSEL14_A::SD6) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL14_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL14_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL14_A::RESERVED4) } #[doc = "Pin is connected to TXD1"] #[inline(always)] - pub fn txd1(self) -> &'a mut W { + pub fn txd1(self) -> &'a mut crate::W { self.variant(FSEL14_A::TXD1) } } #[doc = "Field `FSEL15` reader - Function Select 15"] -pub type FSEL15_R = crate::FieldReader; +pub type FSEL15_R = crate::FieldReader; #[doc = "Function Select 15"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL15_A { + type Ux = u8; +} impl FSEL15_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL15_A { + pub const fn variant(&self) -> FSEL15_A { match self.bits { 0 => FSEL15_A::INPUT, 1 => FSEL15_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL15_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL15_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL15_A::OUTPUT } - #[doc = "Checks if the value of the field is `RXD0`"] + #[doc = "Pin is connected to RXD0"] #[inline(always)] pub fn is_rxd0(&self) -> bool { *self == FSEL15_A::RXD0 } - #[doc = "Checks if the value of the field is `SD7`"] + #[doc = "Pin is connected to SD7"] #[inline(always)] pub fn is_sd7(&self) -> bool { *self == FSEL15_A::SD7 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL15_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL15_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL15_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RXD1`"] + #[doc = "Pin is connected to RXD1"] #[inline(always)] pub fn is_rxd1(&self) -> bool { *self == FSEL15_A::RXD1 } } #[doc = "Field `FSEL15` writer - Function Select 15"] -pub type FSEL15_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL15_A, 3, O>; -impl<'a, const O: u8> FSEL15_W<'a, O> { +pub type FSEL15_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL15_A>; +impl<'a, REG, const O: u8> FSEL15_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL15_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL15_A::OUTPUT) } #[doc = "Pin is connected to RXD0"] #[inline(always)] - pub fn rxd0(self) -> &'a mut W { + pub fn rxd0(self) -> &'a mut crate::W { self.variant(FSEL15_A::RXD0) } #[doc = "Pin is connected to SD7"] #[inline(always)] - pub fn sd7(self) -> &'a mut W { + pub fn sd7(self) -> &'a mut crate::W { self.variant(FSEL15_A::SD7) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL15_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL15_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL15_A::RESERVED4) } #[doc = "Pin is connected to RXD1"] #[inline(always)] - pub fn rxd1(self) -> &'a mut W { + pub fn rxd1(self) -> &'a mut crate::W { self.variant(FSEL15_A::RXD1) } } #[doc = "Field `FSEL16` reader - Function Select 16"] -pub type FSEL16_R = crate::FieldReader; +pub type FSEL16_R = crate::FieldReader; #[doc = "Function Select 16"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL16_A { + type Ux = u8; +} impl FSEL16_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL16_A { + pub const fn variant(&self) -> FSEL16_A { match self.bits { 0 => FSEL16_A::INPUT, 1 => FSEL16_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL16_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL16_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL16_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL16_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD8`"] + #[doc = "Pin is connected to SD8"] #[inline(always)] pub fn is_sd8(&self) -> bool { *self == FSEL16_A::SD8 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL16_A::RESERVED2 } - #[doc = "Checks if the value of the field is `CTS0`"] + #[doc = "Pin is connected to CTS0"] #[inline(always)] pub fn is_cts0(&self) -> bool { *self == FSEL16_A::CTS0 } - #[doc = "Checks if the value of the field is `SPI1_CE2_N`"] + #[doc = "Pin is connected to SPI1_CE2_N"] #[inline(always)] pub fn is_spi1_ce2_n(&self) -> bool { *self == FSEL16_A::SPI1_CE2_N } - #[doc = "Checks if the value of the field is `CTS1`"] + #[doc = "Pin is connected to CTS1"] #[inline(always)] pub fn is_cts1(&self) -> bool { *self == FSEL16_A::CTS1 } } #[doc = "Field `FSEL16` writer - Function Select 16"] -pub type FSEL16_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL16_A, 3, O>; -impl<'a, const O: u8> FSEL16_W<'a, O> { +pub type FSEL16_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL16_A>; +impl<'a, REG, const O: u8> FSEL16_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL16_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL16_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL16_A::RESERVED0) } #[doc = "Pin is connected to SD8"] #[inline(always)] - pub fn sd8(self) -> &'a mut W { + pub fn sd8(self) -> &'a mut crate::W { self.variant(FSEL16_A::SD8) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL16_A::RESERVED2) } #[doc = "Pin is connected to CTS0"] #[inline(always)] - pub fn cts0(self) -> &'a mut W { + pub fn cts0(self) -> &'a mut crate::W { self.variant(FSEL16_A::CTS0) } #[doc = "Pin is connected to SPI1_CE2_N"] #[inline(always)] - pub fn spi1_ce2_n(self) -> &'a mut W { + pub fn spi1_ce2_n(self) -> &'a mut crate::W { self.variant(FSEL16_A::SPI1_CE2_N) } #[doc = "Pin is connected to CTS1"] #[inline(always)] - pub fn cts1(self) -> &'a mut W { + pub fn cts1(self) -> &'a mut crate::W { self.variant(FSEL16_A::CTS1) } } #[doc = "Field `FSEL17` reader - Function Select 17"] -pub type FSEL17_R = crate::FieldReader; +pub type FSEL17_R = crate::FieldReader; #[doc = "Function Select 17"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL17_A { + type Ux = u8; +} impl FSEL17_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL17_A { + pub const fn variant(&self) -> FSEL17_A { match self.bits { 0 => FSEL17_A::INPUT, 1 => FSEL17_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL17_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL17_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL17_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL17_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD9`"] + #[doc = "Pin is connected to SD9"] #[inline(always)] pub fn is_sd9(&self) -> bool { *self == FSEL17_A::SD9 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL17_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RTS0`"] + #[doc = "Pin is connected to RTS0"] #[inline(always)] pub fn is_rts0(&self) -> bool { *self == FSEL17_A::RTS0 } - #[doc = "Checks if the value of the field is `SPI1_CE1_N`"] + #[doc = "Pin is connected to SPI1_CE1_N"] #[inline(always)] pub fn is_spi1_ce1_n(&self) -> bool { *self == FSEL17_A::SPI1_CE1_N } - #[doc = "Checks if the value of the field is `RTS1`"] + #[doc = "Pin is connected to RTS1"] #[inline(always)] pub fn is_rts1(&self) -> bool { *self == FSEL17_A::RTS1 } } #[doc = "Field `FSEL17` writer - Function Select 17"] -pub type FSEL17_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL17_A, 3, O>; -impl<'a, const O: u8> FSEL17_W<'a, O> { +pub type FSEL17_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL17_A>; +impl<'a, REG, const O: u8> FSEL17_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL17_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL17_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL17_A::RESERVED0) } #[doc = "Pin is connected to SD9"] #[inline(always)] - pub fn sd9(self) -> &'a mut W { + pub fn sd9(self) -> &'a mut crate::W { self.variant(FSEL17_A::SD9) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL17_A::RESERVED2) } #[doc = "Pin is connected to RTS0"] #[inline(always)] - pub fn rts0(self) -> &'a mut W { + pub fn rts0(self) -> &'a mut crate::W { self.variant(FSEL17_A::RTS0) } #[doc = "Pin is connected to SPI1_CE1_N"] #[inline(always)] - pub fn spi1_ce1_n(self) -> &'a mut W { + pub fn spi1_ce1_n(self) -> &'a mut crate::W { self.variant(FSEL17_A::SPI1_CE1_N) } #[doc = "Pin is connected to RTS1"] #[inline(always)] - pub fn rts1(self) -> &'a mut W { + pub fn rts1(self) -> &'a mut crate::W { self.variant(FSEL17_A::RTS1) } } #[doc = "Field `FSEL18` reader - Function Select 18"] -pub type FSEL18_R = crate::FieldReader; +pub type FSEL18_R = crate::FieldReader; #[doc = "Function Select 18"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL18_A { + type Ux = u8; +} impl FSEL18_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL18_A { + pub const fn variant(&self) -> FSEL18_A { match self.bits { 0 => FSEL18_A::INPUT, 1 => FSEL18_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL18_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL18_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL18_A::OUTPUT } - #[doc = "Checks if the value of the field is `PCM_CLK`"] + #[doc = "Pin is connected to PCM_CLK"] #[inline(always)] pub fn is_pcm_clk(&self) -> bool { *self == FSEL18_A::PCM_CLK } - #[doc = "Checks if the value of the field is `SD10`"] + #[doc = "Pin is connected to SD10"] #[inline(always)] pub fn is_sd10(&self) -> bool { *self == FSEL18_A::SD10 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL18_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL18_A::RESERVED3 } - #[doc = "Checks if the value of the field is `SPI1_CE0_N`"] + #[doc = "Pin is connected to SPI1_CE0_N"] #[inline(always)] pub fn is_spi1_ce0_n(&self) -> bool { *self == FSEL18_A::SPI1_CE0_N } - #[doc = "Checks if the value of the field is `PWM0_0`"] + #[doc = "Pin is connected to PWM0_0"] #[inline(always)] pub fn is_pwm0_0(&self) -> bool { *self == FSEL18_A::PWM0_0 } } #[doc = "Field `FSEL18` writer - Function Select 18"] -pub type FSEL18_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL18_A, 3, O>; -impl<'a, const O: u8> FSEL18_W<'a, O> { +pub type FSEL18_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL18_A>; +impl<'a, REG, const O: u8> FSEL18_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL18_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL18_A::OUTPUT) } #[doc = "Pin is connected to PCM_CLK"] #[inline(always)] - pub fn pcm_clk(self) -> &'a mut W { + pub fn pcm_clk(self) -> &'a mut crate::W { self.variant(FSEL18_A::PCM_CLK) } #[doc = "Pin is connected to SD10"] #[inline(always)] - pub fn sd10(self) -> &'a mut W { + pub fn sd10(self) -> &'a mut crate::W { self.variant(FSEL18_A::SD10) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL18_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL18_A::RESERVED3) } #[doc = "Pin is connected to SPI1_CE0_N"] #[inline(always)] - pub fn spi1_ce0_n(self) -> &'a mut W { + pub fn spi1_ce0_n(self) -> &'a mut crate::W { self.variant(FSEL18_A::SPI1_CE0_N) } #[doc = "Pin is connected to PWM0_0"] #[inline(always)] - pub fn pwm0_0(self) -> &'a mut W { + pub fn pwm0_0(self) -> &'a mut crate::W { self.variant(FSEL18_A::PWM0_0) } } #[doc = "Field `FSEL19` reader - Function Select 19"] -pub type FSEL19_R = crate::FieldReader; +pub type FSEL19_R = crate::FieldReader; #[doc = "Function Select 19"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL19_A { + type Ux = u8; +} impl FSEL19_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL19_A { + pub const fn variant(&self) -> FSEL19_A { match self.bits { 0 => FSEL19_A::INPUT, 1 => FSEL19_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL19_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL19_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL19_A::OUTPUT } - #[doc = "Checks if the value of the field is `PCM_FS`"] + #[doc = "Pin is connected to PCM_FS"] #[inline(always)] pub fn is_pcm_fs(&self) -> bool { *self == FSEL19_A::PCM_FS } - #[doc = "Checks if the value of the field is `SD11`"] + #[doc = "Pin is connected to SD11"] #[inline(always)] pub fn is_sd11(&self) -> bool { *self == FSEL19_A::SD11 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL19_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL19_A::RESERVED3 } - #[doc = "Checks if the value of the field is `SPI1_MISO`"] + #[doc = "Pin is connected to SPI1_MISO"] #[inline(always)] pub fn is_spi1_miso(&self) -> bool { *self == FSEL19_A::SPI1_MISO } - #[doc = "Checks if the value of the field is `PWM0_1`"] + #[doc = "Pin is connected to PWM0_1"] #[inline(always)] pub fn is_pwm0_1(&self) -> bool { *self == FSEL19_A::PWM0_1 } } #[doc = "Field `FSEL19` writer - Function Select 19"] -pub type FSEL19_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL1_SPEC, u8, FSEL19_A, 3, O>; -impl<'a, const O: u8> FSEL19_W<'a, O> { +pub type FSEL19_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL19_A>; +impl<'a, REG, const O: u8> FSEL19_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL19_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL19_A::OUTPUT) } #[doc = "Pin is connected to PCM_FS"] #[inline(always)] - pub fn pcm_fs(self) -> &'a mut W { + pub fn pcm_fs(self) -> &'a mut crate::W { self.variant(FSEL19_A::PCM_FS) } #[doc = "Pin is connected to SD11"] #[inline(always)] - pub fn sd11(self) -> &'a mut W { + pub fn sd11(self) -> &'a mut crate::W { self.variant(FSEL19_A::SD11) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL19_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL19_A::RESERVED3) } #[doc = "Pin is connected to SPI1_MISO"] #[inline(always)] - pub fn spi1_miso(self) -> &'a mut W { + pub fn spi1_miso(self) -> &'a mut crate::W { self.variant(FSEL19_A::SPI1_MISO) } #[doc = "Pin is connected to PWM0_1"] #[inline(always)] - pub fn pwm0_1(self) -> &'a mut W { + pub fn pwm0_1(self) -> &'a mut crate::W { self.variant(FSEL19_A::PWM0_1) } } @@ -1396,86 +1424,108 @@ impl R { FSEL19_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL1") + .field("fsel10", &format_args!("{}", self.fsel10().bits())) + .field("fsel11", &format_args!("{}", self.fsel11().bits())) + .field("fsel12", &format_args!("{}", self.fsel12().bits())) + .field("fsel13", &format_args!("{}", self.fsel13().bits())) + .field("fsel14", &format_args!("{}", self.fsel14().bits())) + .field("fsel15", &format_args!("{}", self.fsel15().bits())) + .field("fsel16", &format_args!("{}", self.fsel16().bits())) + .field("fsel17", &format_args!("{}", self.fsel17().bits())) + .field("fsel18", &format_args!("{}", self.fsel18().bits())) + .field("fsel19", &format_args!("{}", self.fsel19().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 10"] #[inline(always)] #[must_use] - pub fn fsel10(&mut self) -> FSEL10_W<0> { + pub fn fsel10(&mut self) -> FSEL10_W { FSEL10_W::new(self) } #[doc = "Bits 3:5 - Function Select 11"] #[inline(always)] #[must_use] - pub fn fsel11(&mut self) -> FSEL11_W<3> { + pub fn fsel11(&mut self) -> FSEL11_W { FSEL11_W::new(self) } #[doc = "Bits 6:8 - Function Select 12"] #[inline(always)] #[must_use] - pub fn fsel12(&mut self) -> FSEL12_W<6> { + pub fn fsel12(&mut self) -> FSEL12_W { FSEL12_W::new(self) } #[doc = "Bits 9:11 - Function Select 13"] #[inline(always)] #[must_use] - pub fn fsel13(&mut self) -> FSEL13_W<9> { + pub fn fsel13(&mut self) -> FSEL13_W { FSEL13_W::new(self) } #[doc = "Bits 12:14 - Function Select 14"] #[inline(always)] #[must_use] - pub fn fsel14(&mut self) -> FSEL14_W<12> { + pub fn fsel14(&mut self) -> FSEL14_W { FSEL14_W::new(self) } #[doc = "Bits 15:17 - Function Select 15"] #[inline(always)] #[must_use] - pub fn fsel15(&mut self) -> FSEL15_W<15> { + pub fn fsel15(&mut self) -> FSEL15_W { FSEL15_W::new(self) } #[doc = "Bits 18:20 - Function Select 16"] #[inline(always)] #[must_use] - pub fn fsel16(&mut self) -> FSEL16_W<18> { + pub fn fsel16(&mut self) -> FSEL16_W { FSEL16_W::new(self) } #[doc = "Bits 21:23 - Function Select 17"] #[inline(always)] #[must_use] - pub fn fsel17(&mut self) -> FSEL17_W<21> { + pub fn fsel17(&mut self) -> FSEL17_W { FSEL17_W::new(self) } #[doc = "Bits 24:26 - Function Select 18"] #[inline(always)] #[must_use] - pub fn fsel18(&mut self) -> FSEL18_W<24> { + pub fn fsel18(&mut self) -> FSEL18_W { FSEL18_W::new(self) } #[doc = "Bits 27:29 - Function Select 19"] #[inline(always)] #[must_use] - pub fn fsel19(&mut self) -> FSEL19_W<27> { + pub fn fsel19(&mut self) -> FSEL19_W { FSEL19_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel1](index.html) module"] +#[doc = "GPIO Function Select 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL1_SPEC; impl crate::RegisterSpec for GPFSEL1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel1::R](R) reader structure"] -impl crate::Readable for GPFSEL1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel1::R`](R) reader structure"] +impl crate::Readable for GPFSEL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel1::W`](W) writer structure"] impl crate::Writable for GPFSEL1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpfsel2.rs b/crates/bcm2837-lpa/src/gpio/gpfsel2.rs index 8bc92dc..5704f8e 100644 --- a/crates/bcm2837-lpa/src/gpio/gpfsel2.rs +++ b/crates/bcm2837-lpa/src/gpio/gpfsel2.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL20` reader - Function Select 20"] -pub type FSEL20_R = crate::FieldReader; +pub type FSEL20_R = crate::FieldReader; #[doc = "Function Select 20"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL20_A { + type Ux = u8; +} impl FSEL20_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL20_A { + pub const fn variant(&self) -> FSEL20_A { match self.bits { 0 => FSEL20_A::INPUT, 1 => FSEL20_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL20_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL20_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL20_A::OUTPUT } - #[doc = "Checks if the value of the field is `PCM_DIN`"] + #[doc = "Pin is connected to PCM_DIN"] #[inline(always)] pub fn is_pcm_din(&self) -> bool { *self == FSEL20_A::PCM_DIN } - #[doc = "Checks if the value of the field is `SD12`"] + #[doc = "Pin is connected to SD12"] #[inline(always)] pub fn is_sd12(&self) -> bool { *self == FSEL20_A::SD12 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL20_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL20_A::RESERVED3 } - #[doc = "Checks if the value of the field is `SPI1_MOSI`"] + #[doc = "Pin is connected to SPI1_MOSI"] #[inline(always)] pub fn is_spi1_mosi(&self) -> bool { *self == FSEL20_A::SPI1_MOSI } - #[doc = "Checks if the value of the field is `GPCLK0`"] + #[doc = "Pin is connected to GPCLK0"] #[inline(always)] pub fn is_gpclk0(&self) -> bool { *self == FSEL20_A::GPCLK0 } } #[doc = "Field `FSEL20` writer - Function Select 20"] -pub type FSEL20_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL20_A, 3, O>; -impl<'a, const O: u8> FSEL20_W<'a, O> { +pub type FSEL20_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL20_A>; +impl<'a, REG, const O: u8> FSEL20_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL20_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL20_A::OUTPUT) } #[doc = "Pin is connected to PCM_DIN"] #[inline(always)] - pub fn pcm_din(self) -> &'a mut W { + pub fn pcm_din(self) -> &'a mut crate::W { self.variant(FSEL20_A::PCM_DIN) } #[doc = "Pin is connected to SD12"] #[inline(always)] - pub fn sd12(self) -> &'a mut W { + pub fn sd12(self) -> &'a mut crate::W { self.variant(FSEL20_A::SD12) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL20_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL20_A::RESERVED3) } #[doc = "Pin is connected to SPI1_MOSI"] #[inline(always)] - pub fn spi1_mosi(self) -> &'a mut W { + pub fn spi1_mosi(self) -> &'a mut crate::W { self.variant(FSEL20_A::SPI1_MOSI) } #[doc = "Pin is connected to GPCLK0"] #[inline(always)] - pub fn gpclk0(self) -> &'a mut W { + pub fn gpclk0(self) -> &'a mut crate::W { self.variant(FSEL20_A::GPCLK0) } } #[doc = "Field `FSEL21` reader - Function Select 21"] -pub type FSEL21_R = crate::FieldReader; +pub type FSEL21_R = crate::FieldReader; #[doc = "Function Select 21"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL21_A { + type Ux = u8; +} impl FSEL21_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL21_A { + pub const fn variant(&self) -> FSEL21_A { match self.bits { 0 => FSEL21_A::INPUT, 1 => FSEL21_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL21_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL21_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL21_A::OUTPUT } - #[doc = "Checks if the value of the field is `PCM_DOUT`"] + #[doc = "Pin is connected to PCM_DOUT"] #[inline(always)] pub fn is_pcm_dout(&self) -> bool { *self == FSEL21_A::PCM_DOUT } - #[doc = "Checks if the value of the field is `SD13`"] + #[doc = "Pin is connected to SD13"] #[inline(always)] pub fn is_sd13(&self) -> bool { *self == FSEL21_A::SD13 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL21_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL21_A::RESERVED3 } - #[doc = "Checks if the value of the field is `SPI1_SCLK`"] + #[doc = "Pin is connected to SPI1_SCLK"] #[inline(always)] pub fn is_spi1_sclk(&self) -> bool { *self == FSEL21_A::SPI1_SCLK } - #[doc = "Checks if the value of the field is `GPCLK1`"] + #[doc = "Pin is connected to GPCLK1"] #[inline(always)] pub fn is_gpclk1(&self) -> bool { *self == FSEL21_A::GPCLK1 } } #[doc = "Field `FSEL21` writer - Function Select 21"] -pub type FSEL21_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL21_A, 3, O>; -impl<'a, const O: u8> FSEL21_W<'a, O> { +pub type FSEL21_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL21_A>; +impl<'a, REG, const O: u8> FSEL21_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL21_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL21_A::OUTPUT) } #[doc = "Pin is connected to PCM_DOUT"] #[inline(always)] - pub fn pcm_dout(self) -> &'a mut W { + pub fn pcm_dout(self) -> &'a mut crate::W { self.variant(FSEL21_A::PCM_DOUT) } #[doc = "Pin is connected to SD13"] #[inline(always)] - pub fn sd13(self) -> &'a mut W { + pub fn sd13(self) -> &'a mut crate::W { self.variant(FSEL21_A::SD13) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL21_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL21_A::RESERVED3) } #[doc = "Pin is connected to SPI1_SCLK"] #[inline(always)] - pub fn spi1_sclk(self) -> &'a mut W { + pub fn spi1_sclk(self) -> &'a mut crate::W { self.variant(FSEL21_A::SPI1_SCLK) } #[doc = "Pin is connected to GPCLK1"] #[inline(always)] - pub fn gpclk1(self) -> &'a mut W { + pub fn gpclk1(self) -> &'a mut crate::W { self.variant(FSEL21_A::GPCLK1) } } #[doc = "Field `FSEL22` reader - Function Select 22"] -pub type FSEL22_R = crate::FieldReader; +pub type FSEL22_R = crate::FieldReader; #[doc = "Function Select 22"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL22_A { + type Ux = u8; +} impl FSEL22_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL22_A { + pub const fn variant(&self) -> FSEL22_A { match self.bits { 0 => FSEL22_A::INPUT, 1 => FSEL22_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL22_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL22_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL22_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL22_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD14`"] + #[doc = "Pin is connected to SD14"] #[inline(always)] pub fn is_sd14(&self) -> bool { *self == FSEL22_A::SD14 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL22_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] pub fn is_sd1_clk(&self) -> bool { *self == FSEL22_A::SD1_CLK } - #[doc = "Checks if the value of the field is `ARM_TRST`"] + #[doc = "Pin is connected to ARM_TRST"] #[inline(always)] pub fn is_arm_trst(&self) -> bool { *self == FSEL22_A::ARM_TRST } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL22_A::RESERVED5 } } #[doc = "Field `FSEL22` writer - Function Select 22"] -pub type FSEL22_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL22_A, 3, O>; -impl<'a, const O: u8> FSEL22_W<'a, O> { +pub type FSEL22_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL22_A>; +impl<'a, REG, const O: u8> FSEL22_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL22_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL22_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL22_A::RESERVED0) } #[doc = "Pin is connected to SD14"] #[inline(always)] - pub fn sd14(self) -> &'a mut W { + pub fn sd14(self) -> &'a mut crate::W { self.variant(FSEL22_A::SD14) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL22_A::RESERVED2) } #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] - pub fn sd1_clk(self) -> &'a mut W { + pub fn sd1_clk(self) -> &'a mut crate::W { self.variant(FSEL22_A::SD1_CLK) } #[doc = "Pin is connected to ARM_TRST"] #[inline(always)] - pub fn arm_trst(self) -> &'a mut W { + pub fn arm_trst(self) -> &'a mut crate::W { self.variant(FSEL22_A::ARM_TRST) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL22_A::RESERVED5) } } #[doc = "Field `FSEL23` reader - Function Select 23"] -pub type FSEL23_R = crate::FieldReader; +pub type FSEL23_R = crate::FieldReader; #[doc = "Function Select 23"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL23_A { + type Ux = u8; +} impl FSEL23_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL23_A { + pub const fn variant(&self) -> FSEL23_A { match self.bits { 0 => FSEL23_A::INPUT, 1 => FSEL23_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL23_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL23_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL23_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL23_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD15`"] + #[doc = "Pin is connected to SD15"] #[inline(always)] pub fn is_sd15(&self) -> bool { *self == FSEL23_A::SD15 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL23_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] pub fn is_sd1_cmd(&self) -> bool { *self == FSEL23_A::SD1_CMD } - #[doc = "Checks if the value of the field is `ARM_RTCK`"] + #[doc = "Pin is connected to ARM_RTCK"] #[inline(always)] pub fn is_arm_rtck(&self) -> bool { *self == FSEL23_A::ARM_RTCK } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL23_A::RESERVED5 } } #[doc = "Field `FSEL23` writer - Function Select 23"] -pub type FSEL23_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL23_A, 3, O>; -impl<'a, const O: u8> FSEL23_W<'a, O> { +pub type FSEL23_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL23_A>; +impl<'a, REG, const O: u8> FSEL23_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL23_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL23_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL23_A::RESERVED0) } #[doc = "Pin is connected to SD15"] #[inline(always)] - pub fn sd15(self) -> &'a mut W { + pub fn sd15(self) -> &'a mut crate::W { self.variant(FSEL23_A::SD15) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL23_A::RESERVED2) } #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] - pub fn sd1_cmd(self) -> &'a mut W { + pub fn sd1_cmd(self) -> &'a mut crate::W { self.variant(FSEL23_A::SD1_CMD) } #[doc = "Pin is connected to ARM_RTCK"] #[inline(always)] - pub fn arm_rtck(self) -> &'a mut W { + pub fn arm_rtck(self) -> &'a mut crate::W { self.variant(FSEL23_A::ARM_RTCK) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL23_A::RESERVED5) } } #[doc = "Field `FSEL24` reader - Function Select 24"] -pub type FSEL24_R = crate::FieldReader; +pub type FSEL24_R = crate::FieldReader; #[doc = "Function Select 24"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL24_A { + type Ux = u8; +} impl FSEL24_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL24_A { + pub const fn variant(&self) -> FSEL24_A { match self.bits { 0 => FSEL24_A::INPUT, 1 => FSEL24_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL24_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL24_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL24_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL24_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD16`"] + #[doc = "Pin is connected to SD16"] #[inline(always)] pub fn is_sd16(&self) -> bool { *self == FSEL24_A::SD16 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL24_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] pub fn is_sd1_dat0(&self) -> bool { *self == FSEL24_A::SD1_DAT0 } - #[doc = "Checks if the value of the field is `ARM_TDO`"] + #[doc = "Pin is connected to ARM_TDO"] #[inline(always)] pub fn is_arm_tdo(&self) -> bool { *self == FSEL24_A::ARM_TDO } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL24_A::RESERVED5 } } #[doc = "Field `FSEL24` writer - Function Select 24"] -pub type FSEL24_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL24_A, 3, O>; -impl<'a, const O: u8> FSEL24_W<'a, O> { +pub type FSEL24_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL24_A>; +impl<'a, REG, const O: u8> FSEL24_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL24_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL24_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL24_A::RESERVED0) } #[doc = "Pin is connected to SD16"] #[inline(always)] - pub fn sd16(self) -> &'a mut W { + pub fn sd16(self) -> &'a mut crate::W { self.variant(FSEL24_A::SD16) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL24_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] - pub fn sd1_dat0(self) -> &'a mut W { + pub fn sd1_dat0(self) -> &'a mut crate::W { self.variant(FSEL24_A::SD1_DAT0) } #[doc = "Pin is connected to ARM_TDO"] #[inline(always)] - pub fn arm_tdo(self) -> &'a mut W { + pub fn arm_tdo(self) -> &'a mut crate::W { self.variant(FSEL24_A::ARM_TDO) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL24_A::RESERVED5) } } #[doc = "Field `FSEL25` reader - Function Select 25"] -pub type FSEL25_R = crate::FieldReader; +pub type FSEL25_R = crate::FieldReader; #[doc = "Function Select 25"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL25_A { + type Ux = u8; +} impl FSEL25_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL25_A { + pub const fn variant(&self) -> FSEL25_A { match self.bits { 0 => FSEL25_A::INPUT, 1 => FSEL25_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL25_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL25_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL25_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL25_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SD17`"] + #[doc = "Pin is connected to SD17"] #[inline(always)] pub fn is_sd17(&self) -> bool { *self == FSEL25_A::SD17 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL25_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] pub fn is_sd1_dat1(&self) -> bool { *self == FSEL25_A::SD1_DAT1 } - #[doc = "Checks if the value of the field is `ARM_TCK`"] + #[doc = "Pin is connected to ARM_TCK"] #[inline(always)] pub fn is_arm_tck(&self) -> bool { *self == FSEL25_A::ARM_TCK } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL25_A::RESERVED5 } } #[doc = "Field `FSEL25` writer - Function Select 25"] -pub type FSEL25_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL25_A, 3, O>; -impl<'a, const O: u8> FSEL25_W<'a, O> { +pub type FSEL25_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL25_A>; +impl<'a, REG, const O: u8> FSEL25_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL25_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL25_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL25_A::RESERVED0) } #[doc = "Pin is connected to SD17"] #[inline(always)] - pub fn sd17(self) -> &'a mut W { + pub fn sd17(self) -> &'a mut crate::W { self.variant(FSEL25_A::SD17) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL25_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] - pub fn sd1_dat1(self) -> &'a mut W { + pub fn sd1_dat1(self) -> &'a mut crate::W { self.variant(FSEL25_A::SD1_DAT1) } #[doc = "Pin is connected to ARM_TCK"] #[inline(always)] - pub fn arm_tck(self) -> &'a mut W { + pub fn arm_tck(self) -> &'a mut crate::W { self.variant(FSEL25_A::ARM_TCK) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL25_A::RESERVED5) } } #[doc = "Field `FSEL26` reader - Function Select 26"] -pub type FSEL26_R = crate::FieldReader; +pub type FSEL26_R = crate::FieldReader; #[doc = "Function Select 26"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL26_A { + type Ux = u8; +} impl FSEL26_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL26_A { + pub const fn variant(&self) -> FSEL26_A { match self.bits { 0 => FSEL26_A::INPUT, 1 => FSEL26_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL26_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL26_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL26_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL26_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL26_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL26_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] pub fn is_sd1_dat2(&self) -> bool { *self == FSEL26_A::SD1_DAT2 } - #[doc = "Checks if the value of the field is `ARM_TDI`"] + #[doc = "Pin is connected to ARM_TDI"] #[inline(always)] pub fn is_arm_tdi(&self) -> bool { *self == FSEL26_A::ARM_TDI } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL26_A::RESERVED5 } } #[doc = "Field `FSEL26` writer - Function Select 26"] -pub type FSEL26_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL26_A, 3, O>; -impl<'a, const O: u8> FSEL26_W<'a, O> { +pub type FSEL26_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL26_A>; +impl<'a, REG, const O: u8> FSEL26_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL26_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL26_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL26_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL26_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL26_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] - pub fn sd1_dat2(self) -> &'a mut W { + pub fn sd1_dat2(self) -> &'a mut crate::W { self.variant(FSEL26_A::SD1_DAT2) } #[doc = "Pin is connected to ARM_TDI"] #[inline(always)] - pub fn arm_tdi(self) -> &'a mut W { + pub fn arm_tdi(self) -> &'a mut crate::W { self.variant(FSEL26_A::ARM_TDI) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL26_A::RESERVED5) } } #[doc = "Field `FSEL27` reader - Function Select 27"] -pub type FSEL27_R = crate::FieldReader; +pub type FSEL27_R = crate::FieldReader; #[doc = "Function Select 27"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL27_A { + type Ux = u8; +} impl FSEL27_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL27_A { + pub const fn variant(&self) -> FSEL27_A { match self.bits { 0 => FSEL27_A::INPUT, 1 => FSEL27_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL27_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL27_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL27_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL27_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL27_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL27_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] pub fn is_sd1_dat3(&self) -> bool { *self == FSEL27_A::SD1_DAT3 } - #[doc = "Checks if the value of the field is `ARM_TMS`"] + #[doc = "Pin is connected to ARM_TMS"] #[inline(always)] pub fn is_arm_tms(&self) -> bool { *self == FSEL27_A::ARM_TMS } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL27_A::RESERVED5 } } #[doc = "Field `FSEL27` writer - Function Select 27"] -pub type FSEL27_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL27_A, 3, O>; -impl<'a, const O: u8> FSEL27_W<'a, O> { +pub type FSEL27_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL27_A>; +impl<'a, REG, const O: u8> FSEL27_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL27_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL27_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL27_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL27_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL27_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] - pub fn sd1_dat3(self) -> &'a mut W { + pub fn sd1_dat3(self) -> &'a mut crate::W { self.variant(FSEL27_A::SD1_DAT3) } #[doc = "Pin is connected to ARM_TMS"] #[inline(always)] - pub fn arm_tms(self) -> &'a mut W { + pub fn arm_tms(self) -> &'a mut crate::W { self.variant(FSEL27_A::ARM_TMS) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL27_A::RESERVED5) } } #[doc = "Field `FSEL28` reader - Function Select 28"] -pub type FSEL28_R = crate::FieldReader; +pub type FSEL28_R = crate::FieldReader; #[doc = "Function Select 28"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL28_A { + type Ux = u8; +} impl FSEL28_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL28_A { + pub const fn variant(&self) -> FSEL28_A { match self.bits { 0 => FSEL28_A::INPUT, 1 => FSEL28_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL28_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL28_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL28_A::OUTPUT } - #[doc = "Checks if the value of the field is `SDA0`"] + #[doc = "Pin is connected to SDA0"] #[inline(always)] pub fn is_sda0(&self) -> bool { *self == FSEL28_A::SDA0 } - #[doc = "Checks if the value of the field is `SA5`"] + #[doc = "Pin is connected to SA5"] #[inline(always)] pub fn is_sa5(&self) -> bool { *self == FSEL28_A::SA5 } - #[doc = "Checks if the value of the field is `PCM_CLK`"] + #[doc = "Pin is connected to PCM_CLK"] #[inline(always)] pub fn is_pcm_clk(&self) -> bool { *self == FSEL28_A::PCM_CLK } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL28_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL28_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL28_A::RESERVED5 } } #[doc = "Field `FSEL28` writer - Function Select 28"] -pub type FSEL28_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL28_A, 3, O>; -impl<'a, const O: u8> FSEL28_W<'a, O> { +pub type FSEL28_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL28_A>; +impl<'a, REG, const O: u8> FSEL28_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL28_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL28_A::OUTPUT) } #[doc = "Pin is connected to SDA0"] #[inline(always)] - pub fn sda0(self) -> &'a mut W { + pub fn sda0(self) -> &'a mut crate::W { self.variant(FSEL28_A::SDA0) } #[doc = "Pin is connected to SA5"] #[inline(always)] - pub fn sa5(self) -> &'a mut W { + pub fn sa5(self) -> &'a mut crate::W { self.variant(FSEL28_A::SA5) } #[doc = "Pin is connected to PCM_CLK"] #[inline(always)] - pub fn pcm_clk(self) -> &'a mut W { + pub fn pcm_clk(self) -> &'a mut crate::W { self.variant(FSEL28_A::PCM_CLK) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL28_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL28_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL28_A::RESERVED5) } } #[doc = "Field `FSEL29` reader - Function Select 29"] -pub type FSEL29_R = crate::FieldReader; +pub type FSEL29_R = crate::FieldReader; #[doc = "Function Select 29"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL29_A { + type Ux = u8; +} impl FSEL29_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL29_A { + pub const fn variant(&self) -> FSEL29_A { match self.bits { 0 => FSEL29_A::INPUT, 1 => FSEL29_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL29_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL29_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL29_A::OUTPUT } - #[doc = "Checks if the value of the field is `SCL0`"] + #[doc = "Pin is connected to SCL0"] #[inline(always)] pub fn is_scl0(&self) -> bool { *self == FSEL29_A::SCL0 } - #[doc = "Checks if the value of the field is `SA4`"] + #[doc = "Pin is connected to SA4"] #[inline(always)] pub fn is_sa4(&self) -> bool { *self == FSEL29_A::SA4 } - #[doc = "Checks if the value of the field is `PCM_FS`"] + #[doc = "Pin is connected to PCM_FS"] #[inline(always)] pub fn is_pcm_fs(&self) -> bool { *self == FSEL29_A::PCM_FS } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL29_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL29_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL29_A::RESERVED5 } } #[doc = "Field `FSEL29` writer - Function Select 29"] -pub type FSEL29_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL2_SPEC, u8, FSEL29_A, 3, O>; -impl<'a, const O: u8> FSEL29_W<'a, O> { +pub type FSEL29_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL29_A>; +impl<'a, REG, const O: u8> FSEL29_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL29_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL29_A::OUTPUT) } #[doc = "Pin is connected to SCL0"] #[inline(always)] - pub fn scl0(self) -> &'a mut W { + pub fn scl0(self) -> &'a mut crate::W { self.variant(FSEL29_A::SCL0) } #[doc = "Pin is connected to SA4"] #[inline(always)] - pub fn sa4(self) -> &'a mut W { + pub fn sa4(self) -> &'a mut crate::W { self.variant(FSEL29_A::SA4) } #[doc = "Pin is connected to PCM_FS"] #[inline(always)] - pub fn pcm_fs(self) -> &'a mut W { + pub fn pcm_fs(self) -> &'a mut crate::W { self.variant(FSEL29_A::PCM_FS) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL29_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL29_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL29_A::RESERVED5) } } @@ -1396,86 +1424,108 @@ impl R { FSEL29_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL2") + .field("fsel20", &format_args!("{}", self.fsel20().bits())) + .field("fsel21", &format_args!("{}", self.fsel21().bits())) + .field("fsel22", &format_args!("{}", self.fsel22().bits())) + .field("fsel23", &format_args!("{}", self.fsel23().bits())) + .field("fsel24", &format_args!("{}", self.fsel24().bits())) + .field("fsel25", &format_args!("{}", self.fsel25().bits())) + .field("fsel26", &format_args!("{}", self.fsel26().bits())) + .field("fsel27", &format_args!("{}", self.fsel27().bits())) + .field("fsel28", &format_args!("{}", self.fsel28().bits())) + .field("fsel29", &format_args!("{}", self.fsel29().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 20"] #[inline(always)] #[must_use] - pub fn fsel20(&mut self) -> FSEL20_W<0> { + pub fn fsel20(&mut self) -> FSEL20_W { FSEL20_W::new(self) } #[doc = "Bits 3:5 - Function Select 21"] #[inline(always)] #[must_use] - pub fn fsel21(&mut self) -> FSEL21_W<3> { + pub fn fsel21(&mut self) -> FSEL21_W { FSEL21_W::new(self) } #[doc = "Bits 6:8 - Function Select 22"] #[inline(always)] #[must_use] - pub fn fsel22(&mut self) -> FSEL22_W<6> { + pub fn fsel22(&mut self) -> FSEL22_W { FSEL22_W::new(self) } #[doc = "Bits 9:11 - Function Select 23"] #[inline(always)] #[must_use] - pub fn fsel23(&mut self) -> FSEL23_W<9> { + pub fn fsel23(&mut self) -> FSEL23_W { FSEL23_W::new(self) } #[doc = "Bits 12:14 - Function Select 24"] #[inline(always)] #[must_use] - pub fn fsel24(&mut self) -> FSEL24_W<12> { + pub fn fsel24(&mut self) -> FSEL24_W { FSEL24_W::new(self) } #[doc = "Bits 15:17 - Function Select 25"] #[inline(always)] #[must_use] - pub fn fsel25(&mut self) -> FSEL25_W<15> { + pub fn fsel25(&mut self) -> FSEL25_W { FSEL25_W::new(self) } #[doc = "Bits 18:20 - Function Select 26"] #[inline(always)] #[must_use] - pub fn fsel26(&mut self) -> FSEL26_W<18> { + pub fn fsel26(&mut self) -> FSEL26_W { FSEL26_W::new(self) } #[doc = "Bits 21:23 - Function Select 27"] #[inline(always)] #[must_use] - pub fn fsel27(&mut self) -> FSEL27_W<21> { + pub fn fsel27(&mut self) -> FSEL27_W { FSEL27_W::new(self) } #[doc = "Bits 24:26 - Function Select 28"] #[inline(always)] #[must_use] - pub fn fsel28(&mut self) -> FSEL28_W<24> { + pub fn fsel28(&mut self) -> FSEL28_W { FSEL28_W::new(self) } #[doc = "Bits 27:29 - Function Select 29"] #[inline(always)] #[must_use] - pub fn fsel29(&mut self) -> FSEL29_W<27> { + pub fn fsel29(&mut self) -> FSEL29_W { FSEL29_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel2](index.html) module"] +#[doc = "GPIO Function Select 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL2_SPEC; impl crate::RegisterSpec for GPFSEL2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel2::R](R) reader structure"] -impl crate::Readable for GPFSEL2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel2::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel2::R`](R) reader structure"] +impl crate::Readable for GPFSEL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel2::W`](W) writer structure"] impl crate::Writable for GPFSEL2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpfsel3.rs b/crates/bcm2837-lpa/src/gpio/gpfsel3.rs index d3f9c4f..ce2ef3a 100644 --- a/crates/bcm2837-lpa/src/gpio/gpfsel3.rs +++ b/crates/bcm2837-lpa/src/gpio/gpfsel3.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL30` reader - Function Select 30"] -pub type FSEL30_R = crate::FieldReader; +pub type FSEL30_R = crate::FieldReader; #[doc = "Function Select 30"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL30_A { + type Ux = u8; +} impl FSEL30_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL30_A { + pub const fn variant(&self) -> FSEL30_A { match self.bits { 0 => FSEL30_A::INPUT, 1 => FSEL30_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL30_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL30_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL30_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL30_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SA3`"] + #[doc = "Pin is connected to SA3"] #[inline(always)] pub fn is_sa3(&self) -> bool { *self == FSEL30_A::SA3 } - #[doc = "Checks if the value of the field is `PCM_DIN`"] + #[doc = "Pin is connected to PCM_DIN"] #[inline(always)] pub fn is_pcm_din(&self) -> bool { *self == FSEL30_A::PCM_DIN } - #[doc = "Checks if the value of the field is `CTS0`"] + #[doc = "Pin is connected to CTS0"] #[inline(always)] pub fn is_cts0(&self) -> bool { *self == FSEL30_A::CTS0 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL30_A::RESERVED4 } - #[doc = "Checks if the value of the field is `CTS1`"] + #[doc = "Pin is connected to CTS1"] #[inline(always)] pub fn is_cts1(&self) -> bool { *self == FSEL30_A::CTS1 } } #[doc = "Field `FSEL30` writer - Function Select 30"] -pub type FSEL30_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL30_A, 3, O>; -impl<'a, const O: u8> FSEL30_W<'a, O> { +pub type FSEL30_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL30_A>; +impl<'a, REG, const O: u8> FSEL30_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL30_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL30_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL30_A::RESERVED0) } #[doc = "Pin is connected to SA3"] #[inline(always)] - pub fn sa3(self) -> &'a mut W { + pub fn sa3(self) -> &'a mut crate::W { self.variant(FSEL30_A::SA3) } #[doc = "Pin is connected to PCM_DIN"] #[inline(always)] - pub fn pcm_din(self) -> &'a mut W { + pub fn pcm_din(self) -> &'a mut crate::W { self.variant(FSEL30_A::PCM_DIN) } #[doc = "Pin is connected to CTS0"] #[inline(always)] - pub fn cts0(self) -> &'a mut W { + pub fn cts0(self) -> &'a mut crate::W { self.variant(FSEL30_A::CTS0) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL30_A::RESERVED4) } #[doc = "Pin is connected to CTS1"] #[inline(always)] - pub fn cts1(self) -> &'a mut W { + pub fn cts1(self) -> &'a mut crate::W { self.variant(FSEL30_A::CTS1) } } #[doc = "Field `FSEL31` reader - Function Select 31"] -pub type FSEL31_R = crate::FieldReader; +pub type FSEL31_R = crate::FieldReader; #[doc = "Function Select 31"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL31_A { + type Ux = u8; +} impl FSEL31_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL31_A { + pub const fn variant(&self) -> FSEL31_A { match self.bits { 0 => FSEL31_A::INPUT, 1 => FSEL31_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL31_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL31_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL31_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL31_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SA2`"] + #[doc = "Pin is connected to SA2"] #[inline(always)] pub fn is_sa2(&self) -> bool { *self == FSEL31_A::SA2 } - #[doc = "Checks if the value of the field is `PCM_DOUT`"] + #[doc = "Pin is connected to PCM_DOUT"] #[inline(always)] pub fn is_pcm_dout(&self) -> bool { *self == FSEL31_A::PCM_DOUT } - #[doc = "Checks if the value of the field is `RTS0`"] + #[doc = "Pin is connected to RTS0"] #[inline(always)] pub fn is_rts0(&self) -> bool { *self == FSEL31_A::RTS0 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL31_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RTS1`"] + #[doc = "Pin is connected to RTS1"] #[inline(always)] pub fn is_rts1(&self) -> bool { *self == FSEL31_A::RTS1 } } #[doc = "Field `FSEL31` writer - Function Select 31"] -pub type FSEL31_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL31_A, 3, O>; -impl<'a, const O: u8> FSEL31_W<'a, O> { +pub type FSEL31_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL31_A>; +impl<'a, REG, const O: u8> FSEL31_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL31_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL31_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL31_A::RESERVED0) } #[doc = "Pin is connected to SA2"] #[inline(always)] - pub fn sa2(self) -> &'a mut W { + pub fn sa2(self) -> &'a mut crate::W { self.variant(FSEL31_A::SA2) } #[doc = "Pin is connected to PCM_DOUT"] #[inline(always)] - pub fn pcm_dout(self) -> &'a mut W { + pub fn pcm_dout(self) -> &'a mut crate::W { self.variant(FSEL31_A::PCM_DOUT) } #[doc = "Pin is connected to RTS0"] #[inline(always)] - pub fn rts0(self) -> &'a mut W { + pub fn rts0(self) -> &'a mut crate::W { self.variant(FSEL31_A::RTS0) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL31_A::RESERVED4) } #[doc = "Pin is connected to RTS1"] #[inline(always)] - pub fn rts1(self) -> &'a mut W { + pub fn rts1(self) -> &'a mut crate::W { self.variant(FSEL31_A::RTS1) } } #[doc = "Field `FSEL32` reader - Function Select 32"] -pub type FSEL32_R = crate::FieldReader; +pub type FSEL32_R = crate::FieldReader; #[doc = "Function Select 32"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL32_A { + type Ux = u8; +} impl FSEL32_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL32_A { + pub const fn variant(&self) -> FSEL32_A { match self.bits { 0 => FSEL32_A::INPUT, 1 => FSEL32_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL32_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL32_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL32_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK0`"] + #[doc = "Pin is connected to GPCLK0"] #[inline(always)] pub fn is_gpclk0(&self) -> bool { *self == FSEL32_A::GPCLK0 } - #[doc = "Checks if the value of the field is `SA1`"] + #[doc = "Pin is connected to SA1"] #[inline(always)] pub fn is_sa1(&self) -> bool { *self == FSEL32_A::SA1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL32_A::RESERVED2 } - #[doc = "Checks if the value of the field is `TXD0`"] + #[doc = "Pin is connected to TXD0"] #[inline(always)] pub fn is_txd0(&self) -> bool { *self == FSEL32_A::TXD0 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL32_A::RESERVED4 } - #[doc = "Checks if the value of the field is `TXD1`"] + #[doc = "Pin is connected to TXD1"] #[inline(always)] pub fn is_txd1(&self) -> bool { *self == FSEL32_A::TXD1 } } #[doc = "Field `FSEL32` writer - Function Select 32"] -pub type FSEL32_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL32_A, 3, O>; -impl<'a, const O: u8> FSEL32_W<'a, O> { +pub type FSEL32_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL32_A>; +impl<'a, REG, const O: u8> FSEL32_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL32_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL32_A::OUTPUT) } #[doc = "Pin is connected to GPCLK0"] #[inline(always)] - pub fn gpclk0(self) -> &'a mut W { + pub fn gpclk0(self) -> &'a mut crate::W { self.variant(FSEL32_A::GPCLK0) } #[doc = "Pin is connected to SA1"] #[inline(always)] - pub fn sa1(self) -> &'a mut W { + pub fn sa1(self) -> &'a mut crate::W { self.variant(FSEL32_A::SA1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL32_A::RESERVED2) } #[doc = "Pin is connected to TXD0"] #[inline(always)] - pub fn txd0(self) -> &'a mut W { + pub fn txd0(self) -> &'a mut crate::W { self.variant(FSEL32_A::TXD0) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL32_A::RESERVED4) } #[doc = "Pin is connected to TXD1"] #[inline(always)] - pub fn txd1(self) -> &'a mut W { + pub fn txd1(self) -> &'a mut crate::W { self.variant(FSEL32_A::TXD1) } } #[doc = "Field `FSEL33` reader - Function Select 33"] -pub type FSEL33_R = crate::FieldReader; +pub type FSEL33_R = crate::FieldReader; #[doc = "Function Select 33"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL33_A { + type Ux = u8; +} impl FSEL33_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL33_A { + pub const fn variant(&self) -> FSEL33_A { match self.bits { 0 => FSEL33_A::INPUT, 1 => FSEL33_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL33_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL33_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL33_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL33_A::RESERVED0 } - #[doc = "Checks if the value of the field is `SA0`"] + #[doc = "Pin is connected to SA0"] #[inline(always)] pub fn is_sa0(&self) -> bool { *self == FSEL33_A::SA0 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL33_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RXD0`"] + #[doc = "Pin is connected to RXD0"] #[inline(always)] pub fn is_rxd0(&self) -> bool { *self == FSEL33_A::RXD0 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL33_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RXD1`"] + #[doc = "Pin is connected to RXD1"] #[inline(always)] pub fn is_rxd1(&self) -> bool { *self == FSEL33_A::RXD1 } } #[doc = "Field `FSEL33` writer - Function Select 33"] -pub type FSEL33_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL33_A, 3, O>; -impl<'a, const O: u8> FSEL33_W<'a, O> { +pub type FSEL33_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL33_A>; +impl<'a, REG, const O: u8> FSEL33_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL33_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL33_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL33_A::RESERVED0) } #[doc = "Pin is connected to SA0"] #[inline(always)] - pub fn sa0(self) -> &'a mut W { + pub fn sa0(self) -> &'a mut crate::W { self.variant(FSEL33_A::SA0) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL33_A::RESERVED2) } #[doc = "Pin is connected to RXD0"] #[inline(always)] - pub fn rxd0(self) -> &'a mut W { + pub fn rxd0(self) -> &'a mut crate::W { self.variant(FSEL33_A::RXD0) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL33_A::RESERVED4) } #[doc = "Pin is connected to RXD1"] #[inline(always)] - pub fn rxd1(self) -> &'a mut W { + pub fn rxd1(self) -> &'a mut crate::W { self.variant(FSEL33_A::RXD1) } } #[doc = "Field `FSEL34` reader - Function Select 34"] -pub type FSEL34_R = crate::FieldReader; +pub type FSEL34_R = crate::FieldReader; #[doc = "Function Select 34"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL34_A { + type Ux = u8; +} impl FSEL34_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL34_A { + pub const fn variant(&self) -> FSEL34_A { match self.bits { 0 => FSEL34_A::INPUT, 1 => FSEL34_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL34_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL34_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL34_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK0`"] + #[doc = "Pin is connected to GPCLK0"] #[inline(always)] pub fn is_gpclk0(&self) -> bool { *self == FSEL34_A::GPCLK0 } - #[doc = "Checks if the value of the field is `SOE_N`"] + #[doc = "Pin is connected to SOE_N"] #[inline(always)] pub fn is_soe_n(&self) -> bool { *self == FSEL34_A::SOE_N } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL34_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL34_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL34_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL34_A::RESERVED5 } } #[doc = "Field `FSEL34` writer - Function Select 34"] -pub type FSEL34_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL34_A, 3, O>; -impl<'a, const O: u8> FSEL34_W<'a, O> { +pub type FSEL34_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL34_A>; +impl<'a, REG, const O: u8> FSEL34_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL34_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL34_A::OUTPUT) } #[doc = "Pin is connected to GPCLK0"] #[inline(always)] - pub fn gpclk0(self) -> &'a mut W { + pub fn gpclk0(self) -> &'a mut crate::W { self.variant(FSEL34_A::GPCLK0) } #[doc = "Pin is connected to SOE_N"] #[inline(always)] - pub fn soe_n(self) -> &'a mut W { + pub fn soe_n(self) -> &'a mut crate::W { self.variant(FSEL34_A::SOE_N) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL34_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL34_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL34_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL34_A::RESERVED5) } } #[doc = "Field `FSEL35` reader - Function Select 35"] -pub type FSEL35_R = crate::FieldReader; +pub type FSEL35_R = crate::FieldReader; #[doc = "Function Select 35"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL35_A { + type Ux = u8; +} impl FSEL35_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL35_A { + pub const fn variant(&self) -> FSEL35_A { match self.bits { 0 => FSEL35_A::INPUT, 1 => FSEL35_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL35_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL35_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL35_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_CE1_N`"] + #[doc = "Pin is connected to SPI0_CE1_N"] #[inline(always)] pub fn is_spi0_ce1_n(&self) -> bool { *self == FSEL35_A::SPI0_CE1_N } - #[doc = "Checks if the value of the field is `SWE_N`"] + #[doc = "Pin is connected to SWE_N"] #[inline(always)] pub fn is_swe_n(&self) -> bool { *self == FSEL35_A::SWE_N } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL35_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL35_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL35_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL35_A::RESERVED5 } } #[doc = "Field `FSEL35` writer - Function Select 35"] -pub type FSEL35_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL35_A, 3, O>; -impl<'a, const O: u8> FSEL35_W<'a, O> { +pub type FSEL35_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL35_A>; +impl<'a, REG, const O: u8> FSEL35_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL35_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL35_A::OUTPUT) } #[doc = "Pin is connected to SPI0_CE1_N"] #[inline(always)] - pub fn spi0_ce1_n(self) -> &'a mut W { + pub fn spi0_ce1_n(self) -> &'a mut crate::W { self.variant(FSEL35_A::SPI0_CE1_N) } #[doc = "Pin is connected to SWE_N"] #[inline(always)] - pub fn swe_n(self) -> &'a mut W { + pub fn swe_n(self) -> &'a mut crate::W { self.variant(FSEL35_A::SWE_N) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL35_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL35_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL35_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL35_A::RESERVED5) } } #[doc = "Field `FSEL36` reader - Function Select 36"] -pub type FSEL36_R = crate::FieldReader; +pub type FSEL36_R = crate::FieldReader; #[doc = "Function Select 36"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL36_A { + type Ux = u8; +} impl FSEL36_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL36_A { + pub const fn variant(&self) -> FSEL36_A { match self.bits { 0 => FSEL36_A::INPUT, 1 => FSEL36_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL36_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL36_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL36_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_CE0_N`"] + #[doc = "Pin is connected to SPI0_CE0_N"] #[inline(always)] pub fn is_spi0_ce0_n(&self) -> bool { *self == FSEL36_A::SPI0_CE0_N } - #[doc = "Checks if the value of the field is `SD0`"] + #[doc = "Pin is connected to SD0"] #[inline(always)] pub fn is_sd0(&self) -> bool { *self == FSEL36_A::SD0 } - #[doc = "Checks if the value of the field is `TXD0`"] + #[doc = "Pin is connected to TXD0"] #[inline(always)] pub fn is_txd0(&self) -> bool { *self == FSEL36_A::TXD0 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL36_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL36_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL36_A::RESERVED5 } } #[doc = "Field `FSEL36` writer - Function Select 36"] -pub type FSEL36_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL36_A, 3, O>; -impl<'a, const O: u8> FSEL36_W<'a, O> { +pub type FSEL36_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL36_A>; +impl<'a, REG, const O: u8> FSEL36_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL36_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL36_A::OUTPUT) } #[doc = "Pin is connected to SPI0_CE0_N"] #[inline(always)] - pub fn spi0_ce0_n(self) -> &'a mut W { + pub fn spi0_ce0_n(self) -> &'a mut crate::W { self.variant(FSEL36_A::SPI0_CE0_N) } #[doc = "Pin is connected to SD0"] #[inline(always)] - pub fn sd0(self) -> &'a mut W { + pub fn sd0(self) -> &'a mut crate::W { self.variant(FSEL36_A::SD0) } #[doc = "Pin is connected to TXD0"] #[inline(always)] - pub fn txd0(self) -> &'a mut W { + pub fn txd0(self) -> &'a mut crate::W { self.variant(FSEL36_A::TXD0) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL36_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL36_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL36_A::RESERVED5) } } #[doc = "Field `FSEL37` reader - Function Select 37"] -pub type FSEL37_R = crate::FieldReader; +pub type FSEL37_R = crate::FieldReader; #[doc = "Function Select 37"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL37_A { + type Ux = u8; +} impl FSEL37_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL37_A { + pub const fn variant(&self) -> FSEL37_A { match self.bits { 0 => FSEL37_A::INPUT, 1 => FSEL37_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL37_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL37_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL37_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_MISO`"] + #[doc = "Pin is connected to SPI0_MISO"] #[inline(always)] pub fn is_spi0_miso(&self) -> bool { *self == FSEL37_A::SPI0_MISO } - #[doc = "Checks if the value of the field is `SD1`"] + #[doc = "Pin is connected to SD1"] #[inline(always)] pub fn is_sd1(&self) -> bool { *self == FSEL37_A::SD1 } - #[doc = "Checks if the value of the field is `RXD0`"] + #[doc = "Pin is connected to RXD0"] #[inline(always)] pub fn is_rxd0(&self) -> bool { *self == FSEL37_A::RXD0 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL37_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL37_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL37_A::RESERVED5 } } #[doc = "Field `FSEL37` writer - Function Select 37"] -pub type FSEL37_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL37_A, 3, O>; -impl<'a, const O: u8> FSEL37_W<'a, O> { +pub type FSEL37_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL37_A>; +impl<'a, REG, const O: u8> FSEL37_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL37_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL37_A::OUTPUT) } #[doc = "Pin is connected to SPI0_MISO"] #[inline(always)] - pub fn spi0_miso(self) -> &'a mut W { + pub fn spi0_miso(self) -> &'a mut crate::W { self.variant(FSEL37_A::SPI0_MISO) } #[doc = "Pin is connected to SD1"] #[inline(always)] - pub fn sd1(self) -> &'a mut W { + pub fn sd1(self) -> &'a mut crate::W { self.variant(FSEL37_A::SD1) } #[doc = "Pin is connected to RXD0"] #[inline(always)] - pub fn rxd0(self) -> &'a mut W { + pub fn rxd0(self) -> &'a mut crate::W { self.variant(FSEL37_A::RXD0) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL37_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL37_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL37_A::RESERVED5) } } #[doc = "Field `FSEL38` reader - Function Select 38"] -pub type FSEL38_R = crate::FieldReader; +pub type FSEL38_R = crate::FieldReader; #[doc = "Function Select 38"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL38_A { + type Ux = u8; +} impl FSEL38_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL38_A { + pub const fn variant(&self) -> FSEL38_A { match self.bits { 0 => FSEL38_A::INPUT, 1 => FSEL38_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL38_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL38_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL38_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_MOSI`"] + #[doc = "Pin is connected to SPI0_MOSI"] #[inline(always)] pub fn is_spi0_mosi(&self) -> bool { *self == FSEL38_A::SPI0_MOSI } - #[doc = "Checks if the value of the field is `SD2`"] + #[doc = "Pin is connected to SD2"] #[inline(always)] pub fn is_sd2(&self) -> bool { *self == FSEL38_A::SD2 } - #[doc = "Checks if the value of the field is `CTS0`"] + #[doc = "Pin is connected to CTS0"] #[inline(always)] pub fn is_cts0(&self) -> bool { *self == FSEL38_A::CTS0 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL38_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL38_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL38_A::RESERVED5 } } #[doc = "Field `FSEL38` writer - Function Select 38"] -pub type FSEL38_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL38_A, 3, O>; -impl<'a, const O: u8> FSEL38_W<'a, O> { +pub type FSEL38_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL38_A>; +impl<'a, REG, const O: u8> FSEL38_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL38_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL38_A::OUTPUT) } #[doc = "Pin is connected to SPI0_MOSI"] #[inline(always)] - pub fn spi0_mosi(self) -> &'a mut W { + pub fn spi0_mosi(self) -> &'a mut crate::W { self.variant(FSEL38_A::SPI0_MOSI) } #[doc = "Pin is connected to SD2"] #[inline(always)] - pub fn sd2(self) -> &'a mut W { + pub fn sd2(self) -> &'a mut crate::W { self.variant(FSEL38_A::SD2) } #[doc = "Pin is connected to CTS0"] #[inline(always)] - pub fn cts0(self) -> &'a mut W { + pub fn cts0(self) -> &'a mut crate::W { self.variant(FSEL38_A::CTS0) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL38_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL38_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL38_A::RESERVED5) } } #[doc = "Field `FSEL39` reader - Function Select 39"] -pub type FSEL39_R = crate::FieldReader; +pub type FSEL39_R = crate::FieldReader; #[doc = "Function Select 39"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL39_A { + type Ux = u8; +} impl FSEL39_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL39_A { + pub const fn variant(&self) -> FSEL39_A { match self.bits { 0 => FSEL39_A::INPUT, 1 => FSEL39_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL39_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL39_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL39_A::OUTPUT } - #[doc = "Checks if the value of the field is `SPI0_SCLK`"] + #[doc = "Pin is connected to SPI0_SCLK"] #[inline(always)] pub fn is_spi0_sclk(&self) -> bool { *self == FSEL39_A::SPI0_SCLK } - #[doc = "Checks if the value of the field is `SD3`"] + #[doc = "Pin is connected to SD3"] #[inline(always)] pub fn is_sd3(&self) -> bool { *self == FSEL39_A::SD3 } - #[doc = "Checks if the value of the field is `RTS0`"] + #[doc = "Pin is connected to RTS0"] #[inline(always)] pub fn is_rts0(&self) -> bool { *self == FSEL39_A::RTS0 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL39_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL39_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL39_A::RESERVED5 } } #[doc = "Field `FSEL39` writer - Function Select 39"] -pub type FSEL39_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL3_SPEC, u8, FSEL39_A, 3, O>; -impl<'a, const O: u8> FSEL39_W<'a, O> { +pub type FSEL39_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL39_A>; +impl<'a, REG, const O: u8> FSEL39_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL39_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL39_A::OUTPUT) } #[doc = "Pin is connected to SPI0_SCLK"] #[inline(always)] - pub fn spi0_sclk(self) -> &'a mut W { + pub fn spi0_sclk(self) -> &'a mut crate::W { self.variant(FSEL39_A::SPI0_SCLK) } #[doc = "Pin is connected to SD3"] #[inline(always)] - pub fn sd3(self) -> &'a mut W { + pub fn sd3(self) -> &'a mut crate::W { self.variant(FSEL39_A::SD3) } #[doc = "Pin is connected to RTS0"] #[inline(always)] - pub fn rts0(self) -> &'a mut W { + pub fn rts0(self) -> &'a mut crate::W { self.variant(FSEL39_A::RTS0) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL39_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL39_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL39_A::RESERVED5) } } @@ -1396,86 +1424,108 @@ impl R { FSEL39_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL3") + .field("fsel30", &format_args!("{}", self.fsel30().bits())) + .field("fsel31", &format_args!("{}", self.fsel31().bits())) + .field("fsel32", &format_args!("{}", self.fsel32().bits())) + .field("fsel33", &format_args!("{}", self.fsel33().bits())) + .field("fsel34", &format_args!("{}", self.fsel34().bits())) + .field("fsel35", &format_args!("{}", self.fsel35().bits())) + .field("fsel36", &format_args!("{}", self.fsel36().bits())) + .field("fsel37", &format_args!("{}", self.fsel37().bits())) + .field("fsel38", &format_args!("{}", self.fsel38().bits())) + .field("fsel39", &format_args!("{}", self.fsel39().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 30"] #[inline(always)] #[must_use] - pub fn fsel30(&mut self) -> FSEL30_W<0> { + pub fn fsel30(&mut self) -> FSEL30_W { FSEL30_W::new(self) } #[doc = "Bits 3:5 - Function Select 31"] #[inline(always)] #[must_use] - pub fn fsel31(&mut self) -> FSEL31_W<3> { + pub fn fsel31(&mut self) -> FSEL31_W { FSEL31_W::new(self) } #[doc = "Bits 6:8 - Function Select 32"] #[inline(always)] #[must_use] - pub fn fsel32(&mut self) -> FSEL32_W<6> { + pub fn fsel32(&mut self) -> FSEL32_W { FSEL32_W::new(self) } #[doc = "Bits 9:11 - Function Select 33"] #[inline(always)] #[must_use] - pub fn fsel33(&mut self) -> FSEL33_W<9> { + pub fn fsel33(&mut self) -> FSEL33_W { FSEL33_W::new(self) } #[doc = "Bits 12:14 - Function Select 34"] #[inline(always)] #[must_use] - pub fn fsel34(&mut self) -> FSEL34_W<12> { + pub fn fsel34(&mut self) -> FSEL34_W { FSEL34_W::new(self) } #[doc = "Bits 15:17 - Function Select 35"] #[inline(always)] #[must_use] - pub fn fsel35(&mut self) -> FSEL35_W<15> { + pub fn fsel35(&mut self) -> FSEL35_W { FSEL35_W::new(self) } #[doc = "Bits 18:20 - Function Select 36"] #[inline(always)] #[must_use] - pub fn fsel36(&mut self) -> FSEL36_W<18> { + pub fn fsel36(&mut self) -> FSEL36_W { FSEL36_W::new(self) } #[doc = "Bits 21:23 - Function Select 37"] #[inline(always)] #[must_use] - pub fn fsel37(&mut self) -> FSEL37_W<21> { + pub fn fsel37(&mut self) -> FSEL37_W { FSEL37_W::new(self) } #[doc = "Bits 24:26 - Function Select 38"] #[inline(always)] #[must_use] - pub fn fsel38(&mut self) -> FSEL38_W<24> { + pub fn fsel38(&mut self) -> FSEL38_W { FSEL38_W::new(self) } #[doc = "Bits 27:29 - Function Select 39"] #[inline(always)] #[must_use] - pub fn fsel39(&mut self) -> FSEL39_W<27> { + pub fn fsel39(&mut self) -> FSEL39_W { FSEL39_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel3](index.html) module"] +#[doc = "GPIO Function Select 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL3_SPEC; impl crate::RegisterSpec for GPFSEL3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel3::R](R) reader structure"] -impl crate::Readable for GPFSEL3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel3::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel3::R`](R) reader structure"] +impl crate::Readable for GPFSEL3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel3::W`](W) writer structure"] impl crate::Writable for GPFSEL3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpfsel4.rs b/crates/bcm2837-lpa/src/gpio/gpfsel4.rs index 16bf84a..50a568f 100644 --- a/crates/bcm2837-lpa/src/gpio/gpfsel4.rs +++ b/crates/bcm2837-lpa/src/gpio/gpfsel4.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL40` reader - Function Select 40"] -pub type FSEL40_R = crate::FieldReader; +pub type FSEL40_R = crate::FieldReader; #[doc = "Function Select 40"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL40_A { + type Ux = u8; +} impl FSEL40_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL40_A { + pub const fn variant(&self) -> FSEL40_A { match self.bits { 0 => FSEL40_A::INPUT, 1 => FSEL40_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL40_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL40_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL40_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM0_0`"] + #[doc = "Pin is connected to PWM0_0"] #[inline(always)] pub fn is_pwm0_0(&self) -> bool { *self == FSEL40_A::PWM0_0 } - #[doc = "Checks if the value of the field is `SD4`"] + #[doc = "Pin is connected to SD4"] #[inline(always)] pub fn is_sd4(&self) -> bool { *self == FSEL40_A::SD4 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL40_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL40_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL40_A::RESERVED4 } - #[doc = "Checks if the value of the field is `TXD1`"] + #[doc = "Pin is connected to TXD1"] #[inline(always)] pub fn is_txd1(&self) -> bool { *self == FSEL40_A::TXD1 } } #[doc = "Field `FSEL40` writer - Function Select 40"] -pub type FSEL40_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL40_A, 3, O>; -impl<'a, const O: u8> FSEL40_W<'a, O> { +pub type FSEL40_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL40_A>; +impl<'a, REG, const O: u8> FSEL40_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL40_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL40_A::OUTPUT) } #[doc = "Pin is connected to PWM0_0"] #[inline(always)] - pub fn pwm0_0(self) -> &'a mut W { + pub fn pwm0_0(self) -> &'a mut crate::W { self.variant(FSEL40_A::PWM0_0) } #[doc = "Pin is connected to SD4"] #[inline(always)] - pub fn sd4(self) -> &'a mut W { + pub fn sd4(self) -> &'a mut crate::W { self.variant(FSEL40_A::SD4) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL40_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL40_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL40_A::RESERVED4) } #[doc = "Pin is connected to TXD1"] #[inline(always)] - pub fn txd1(self) -> &'a mut W { + pub fn txd1(self) -> &'a mut crate::W { self.variant(FSEL40_A::TXD1) } } #[doc = "Field `FSEL41` reader - Function Select 41"] -pub type FSEL41_R = crate::FieldReader; +pub type FSEL41_R = crate::FieldReader; #[doc = "Function Select 41"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL41_A { + type Ux = u8; +} impl FSEL41_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL41_A { + pub const fn variant(&self) -> FSEL41_A { match self.bits { 0 => FSEL41_A::INPUT, 1 => FSEL41_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL41_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL41_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL41_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM0_1`"] + #[doc = "Pin is connected to PWM0_1"] #[inline(always)] pub fn is_pwm0_1(&self) -> bool { *self == FSEL41_A::PWM0_1 } - #[doc = "Checks if the value of the field is `SD5`"] + #[doc = "Pin is connected to SD5"] #[inline(always)] pub fn is_sd5(&self) -> bool { *self == FSEL41_A::SD5 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL41_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL41_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL41_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RXD1`"] + #[doc = "Pin is connected to RXD1"] #[inline(always)] pub fn is_rxd1(&self) -> bool { *self == FSEL41_A::RXD1 } } #[doc = "Field `FSEL41` writer - Function Select 41"] -pub type FSEL41_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL41_A, 3, O>; -impl<'a, const O: u8> FSEL41_W<'a, O> { +pub type FSEL41_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL41_A>; +impl<'a, REG, const O: u8> FSEL41_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL41_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL41_A::OUTPUT) } #[doc = "Pin is connected to PWM0_1"] #[inline(always)] - pub fn pwm0_1(self) -> &'a mut W { + pub fn pwm0_1(self) -> &'a mut crate::W { self.variant(FSEL41_A::PWM0_1) } #[doc = "Pin is connected to SD5"] #[inline(always)] - pub fn sd5(self) -> &'a mut W { + pub fn sd5(self) -> &'a mut crate::W { self.variant(FSEL41_A::SD5) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL41_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL41_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL41_A::RESERVED4) } #[doc = "Pin is connected to RXD1"] #[inline(always)] - pub fn rxd1(self) -> &'a mut W { + pub fn rxd1(self) -> &'a mut crate::W { self.variant(FSEL41_A::RXD1) } } #[doc = "Field `FSEL42` reader - Function Select 42"] -pub type FSEL42_R = crate::FieldReader; +pub type FSEL42_R = crate::FieldReader; #[doc = "Function Select 42"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL42_A { + type Ux = u8; +} impl FSEL42_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL42_A { + pub const fn variant(&self) -> FSEL42_A { match self.bits { 0 => FSEL42_A::INPUT, 1 => FSEL42_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL42_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL42_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL42_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK1`"] + #[doc = "Pin is connected to GPCLK1"] #[inline(always)] pub fn is_gpclk1(&self) -> bool { *self == FSEL42_A::GPCLK1 } - #[doc = "Checks if the value of the field is `SD6`"] + #[doc = "Pin is connected to SD6"] #[inline(always)] pub fn is_sd6(&self) -> bool { *self == FSEL42_A::SD6 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL42_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL42_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL42_A::RESERVED4 } - #[doc = "Checks if the value of the field is `CTS1`"] + #[doc = "Pin is connected to CTS1"] #[inline(always)] pub fn is_cts1(&self) -> bool { *self == FSEL42_A::CTS1 } } #[doc = "Field `FSEL42` writer - Function Select 42"] -pub type FSEL42_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL42_A, 3, O>; -impl<'a, const O: u8> FSEL42_W<'a, O> { +pub type FSEL42_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL42_A>; +impl<'a, REG, const O: u8> FSEL42_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL42_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL42_A::OUTPUT) } #[doc = "Pin is connected to GPCLK1"] #[inline(always)] - pub fn gpclk1(self) -> &'a mut W { + pub fn gpclk1(self) -> &'a mut crate::W { self.variant(FSEL42_A::GPCLK1) } #[doc = "Pin is connected to SD6"] #[inline(always)] - pub fn sd6(self) -> &'a mut W { + pub fn sd6(self) -> &'a mut crate::W { self.variant(FSEL42_A::SD6) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL42_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL42_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL42_A::RESERVED4) } #[doc = "Pin is connected to CTS1"] #[inline(always)] - pub fn cts1(self) -> &'a mut W { + pub fn cts1(self) -> &'a mut crate::W { self.variant(FSEL42_A::CTS1) } } #[doc = "Field `FSEL43` reader - Function Select 43"] -pub type FSEL43_R = crate::FieldReader; +pub type FSEL43_R = crate::FieldReader; #[doc = "Function Select 43"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL43_A { + type Ux = u8; +} impl FSEL43_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL43_A { + pub const fn variant(&self) -> FSEL43_A { match self.bits { 0 => FSEL43_A::INPUT, 1 => FSEL43_A::OUTPUT, @@ -472,94 +461,97 @@ impl FSEL43_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL43_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL43_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK2`"] + #[doc = "Pin is connected to GPCLK2"] #[inline(always)] pub fn is_gpclk2(&self) -> bool { *self == FSEL43_A::GPCLK2 } - #[doc = "Checks if the value of the field is `SD7`"] + #[doc = "Pin is connected to SD7"] #[inline(always)] pub fn is_sd7(&self) -> bool { *self == FSEL43_A::SD7 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL43_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL43_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL43_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RTS1`"] + #[doc = "Pin is connected to RTS1"] #[inline(always)] pub fn is_rts1(&self) -> bool { *self == FSEL43_A::RTS1 } } #[doc = "Field `FSEL43` writer - Function Select 43"] -pub type FSEL43_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL43_A, 3, O>; -impl<'a, const O: u8> FSEL43_W<'a, O> { +pub type FSEL43_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL43_A>; +impl<'a, REG, const O: u8> FSEL43_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL43_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL43_A::OUTPUT) } #[doc = "Pin is connected to GPCLK2"] #[inline(always)] - pub fn gpclk2(self) -> &'a mut W { + pub fn gpclk2(self) -> &'a mut crate::W { self.variant(FSEL43_A::GPCLK2) } #[doc = "Pin is connected to SD7"] #[inline(always)] - pub fn sd7(self) -> &'a mut W { + pub fn sd7(self) -> &'a mut crate::W { self.variant(FSEL43_A::SD7) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL43_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL43_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL43_A::RESERVED4) } #[doc = "Pin is connected to RTS1"] #[inline(always)] - pub fn rts1(self) -> &'a mut W { + pub fn rts1(self) -> &'a mut crate::W { self.variant(FSEL43_A::RTS1) } } #[doc = "Field `FSEL44` reader - Function Select 44"] -pub type FSEL44_R = crate::FieldReader; +pub type FSEL44_R = crate::FieldReader; #[doc = "Function Select 44"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -587,10 +579,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL44_A { + type Ux = u8; +} impl FSEL44_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL44_A { + pub const fn variant(&self) -> FSEL44_A { match self.bits { 0 => FSEL44_A::INPUT, 1 => FSEL44_A::OUTPUT, @@ -603,94 +598,97 @@ impl FSEL44_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL44_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL44_A::OUTPUT } - #[doc = "Checks if the value of the field is `GPCLK1`"] + #[doc = "Pin is connected to GPCLK1"] #[inline(always)] pub fn is_gpclk1(&self) -> bool { *self == FSEL44_A::GPCLK1 } - #[doc = "Checks if the value of the field is `SDA0`"] + #[doc = "Pin is connected to SDA0"] #[inline(always)] pub fn is_sda0(&self) -> bool { *self == FSEL44_A::SDA0 } - #[doc = "Checks if the value of the field is `SDA1`"] + #[doc = "Pin is connected to SDA1"] #[inline(always)] pub fn is_sda1(&self) -> bool { *self == FSEL44_A::SDA1 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL44_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL44_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL44_A::RESERVED5 } } #[doc = "Field `FSEL44` writer - Function Select 44"] -pub type FSEL44_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL44_A, 3, O>; -impl<'a, const O: u8> FSEL44_W<'a, O> { +pub type FSEL44_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL44_A>; +impl<'a, REG, const O: u8> FSEL44_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL44_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL44_A::OUTPUT) } #[doc = "Pin is connected to GPCLK1"] #[inline(always)] - pub fn gpclk1(self) -> &'a mut W { + pub fn gpclk1(self) -> &'a mut crate::W { self.variant(FSEL44_A::GPCLK1) } #[doc = "Pin is connected to SDA0"] #[inline(always)] - pub fn sda0(self) -> &'a mut W { + pub fn sda0(self) -> &'a mut crate::W { self.variant(FSEL44_A::SDA0) } #[doc = "Pin is connected to SDA1"] #[inline(always)] - pub fn sda1(self) -> &'a mut W { + pub fn sda1(self) -> &'a mut crate::W { self.variant(FSEL44_A::SDA1) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL44_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL44_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL44_A::RESERVED5) } } #[doc = "Field `FSEL45` reader - Function Select 45"] -pub type FSEL45_R = crate::FieldReader; +pub type FSEL45_R = crate::FieldReader; #[doc = "Function Select 45"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -718,10 +716,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL45_A { + type Ux = u8; +} impl FSEL45_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL45_A { + pub const fn variant(&self) -> FSEL45_A { match self.bits { 0 => FSEL45_A::INPUT, 1 => FSEL45_A::OUTPUT, @@ -734,94 +735,97 @@ impl FSEL45_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL45_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL45_A::OUTPUT } - #[doc = "Checks if the value of the field is `PWM0_1`"] + #[doc = "Pin is connected to PWM0_1"] #[inline(always)] pub fn is_pwm0_1(&self) -> bool { *self == FSEL45_A::PWM0_1 } - #[doc = "Checks if the value of the field is `SCL0`"] + #[doc = "Pin is connected to SCL0"] #[inline(always)] pub fn is_scl0(&self) -> bool { *self == FSEL45_A::SCL0 } - #[doc = "Checks if the value of the field is `SCL1`"] + #[doc = "Pin is connected to SCL1"] #[inline(always)] pub fn is_scl1(&self) -> bool { *self == FSEL45_A::SCL1 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL45_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL45_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL45_A::RESERVED5 } } #[doc = "Field `FSEL45` writer - Function Select 45"] -pub type FSEL45_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL45_A, 3, O>; -impl<'a, const O: u8> FSEL45_W<'a, O> { +pub type FSEL45_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL45_A>; +impl<'a, REG, const O: u8> FSEL45_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL45_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL45_A::OUTPUT) } #[doc = "Pin is connected to PWM0_1"] #[inline(always)] - pub fn pwm0_1(self) -> &'a mut W { + pub fn pwm0_1(self) -> &'a mut crate::W { self.variant(FSEL45_A::PWM0_1) } #[doc = "Pin is connected to SCL0"] #[inline(always)] - pub fn scl0(self) -> &'a mut W { + pub fn scl0(self) -> &'a mut crate::W { self.variant(FSEL45_A::SCL0) } #[doc = "Pin is connected to SCL1"] #[inline(always)] - pub fn scl1(self) -> &'a mut W { + pub fn scl1(self) -> &'a mut crate::W { self.variant(FSEL45_A::SCL1) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL45_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL45_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL45_A::RESERVED5) } } #[doc = "Field `FSEL46` reader - Function Select 46"] -pub type FSEL46_R = crate::FieldReader; +pub type FSEL46_R = crate::FieldReader; #[doc = "Function Select 46"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -849,10 +853,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL46_A { + type Ux = u8; +} impl FSEL46_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL46_A { + pub const fn variant(&self) -> FSEL46_A { match self.bits { 0 => FSEL46_A::INPUT, 1 => FSEL46_A::OUTPUT, @@ -865,94 +872,97 @@ impl FSEL46_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL46_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL46_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL46_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL46_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL46_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL46_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL46_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL46_A::RESERVED5 } } #[doc = "Field `FSEL46` writer - Function Select 46"] -pub type FSEL46_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL46_A, 3, O>; -impl<'a, const O: u8> FSEL46_W<'a, O> { +pub type FSEL46_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL46_A>; +impl<'a, REG, const O: u8> FSEL46_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL46_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL46_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL46_A::RESERVED5) } } #[doc = "Field `FSEL47` reader - Function Select 47"] -pub type FSEL47_R = crate::FieldReader; +pub type FSEL47_R = crate::FieldReader; #[doc = "Function Select 47"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -980,10 +990,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL47_A { + type Ux = u8; +} impl FSEL47_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL47_A { + pub const fn variant(&self) -> FSEL47_A { match self.bits { 0 => FSEL47_A::INPUT, 1 => FSEL47_A::OUTPUT, @@ -996,94 +1009,97 @@ impl FSEL47_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL47_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL47_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL47_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL47_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL47_A::RESERVED2 } - #[doc = "Checks if the value of the field is `RESERVED3`"] + #[doc = "Alt function 3 reserved"] #[inline(always)] pub fn is_reserved3(&self) -> bool { *self == FSEL47_A::RESERVED3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL47_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL47_A::RESERVED5 } } #[doc = "Field `FSEL47` writer - Function Select 47"] -pub type FSEL47_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL47_A, 3, O>; -impl<'a, const O: u8> FSEL47_W<'a, O> { +pub type FSEL47_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL47_A>; +impl<'a, REG, const O: u8> FSEL47_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL47_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL47_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED2) } #[doc = "Alt function 3 reserved"] #[inline(always)] - pub fn reserved3(self) -> &'a mut W { + pub fn reserved3(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL47_A::RESERVED5) } } #[doc = "Field `FSEL48` reader - Function Select 48"] -pub type FSEL48_R = crate::FieldReader; +pub type FSEL48_R = crate::FieldReader; #[doc = "Function Select 48"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1111,10 +1127,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL48_A { + type Ux = u8; +} impl FSEL48_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL48_A { + pub const fn variant(&self) -> FSEL48_A { match self.bits { 0 => FSEL48_A::INPUT, 1 => FSEL48_A::OUTPUT, @@ -1127,94 +1146,97 @@ impl FSEL48_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL48_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL48_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL48_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL48_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL48_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_CLK`"] + #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] pub fn is_sd1_clk(&self) -> bool { *self == FSEL48_A::SD1_CLK } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL48_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL48_A::RESERVED5 } } #[doc = "Field `FSEL48` writer - Function Select 48"] -pub type FSEL48_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL48_A, 3, O>; -impl<'a, const O: u8> FSEL48_W<'a, O> { +pub type FSEL48_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL48_A>; +impl<'a, REG, const O: u8> FSEL48_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL48_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL48_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED2) } #[doc = "Pin is connected to SD1_CLK"] #[inline(always)] - pub fn sd1_clk(self) -> &'a mut W { + pub fn sd1_clk(self) -> &'a mut crate::W { self.variant(FSEL48_A::SD1_CLK) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL48_A::RESERVED5) } } #[doc = "Field `FSEL49` reader - Function Select 49"] -pub type FSEL49_R = crate::FieldReader; +pub type FSEL49_R = crate::FieldReader; #[doc = "Function Select 49"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -1242,10 +1264,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL49_A { + type Ux = u8; +} impl FSEL49_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL49_A { + pub const fn variant(&self) -> FSEL49_A { match self.bits { 0 => FSEL49_A::INPUT, 1 => FSEL49_A::OUTPUT, @@ -1258,89 +1283,92 @@ impl FSEL49_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL49_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL49_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL49_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL49_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL49_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_CMD`"] + #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] pub fn is_sd1_cmd(&self) -> bool { *self == FSEL49_A::SD1_CMD } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL49_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL49_A::RESERVED5 } } #[doc = "Field `FSEL49` writer - Function Select 49"] -pub type FSEL49_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL4_SPEC, u8, FSEL49_A, 3, O>; -impl<'a, const O: u8> FSEL49_W<'a, O> { +pub type FSEL49_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL49_A>; +impl<'a, REG, const O: u8> FSEL49_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL49_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL49_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED2) } #[doc = "Pin is connected to SD1_CMD"] #[inline(always)] - pub fn sd1_cmd(self) -> &'a mut W { + pub fn sd1_cmd(self) -> &'a mut crate::W { self.variant(FSEL49_A::SD1_CMD) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL49_A::RESERVED5) } } @@ -1396,86 +1424,108 @@ impl R { FSEL49_R::new(((self.bits >> 27) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL4") + .field("fsel40", &format_args!("{}", self.fsel40().bits())) + .field("fsel41", &format_args!("{}", self.fsel41().bits())) + .field("fsel42", &format_args!("{}", self.fsel42().bits())) + .field("fsel43", &format_args!("{}", self.fsel43().bits())) + .field("fsel44", &format_args!("{}", self.fsel44().bits())) + .field("fsel45", &format_args!("{}", self.fsel45().bits())) + .field("fsel46", &format_args!("{}", self.fsel46().bits())) + .field("fsel47", &format_args!("{}", self.fsel47().bits())) + .field("fsel48", &format_args!("{}", self.fsel48().bits())) + .field("fsel49", &format_args!("{}", self.fsel49().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 40"] #[inline(always)] #[must_use] - pub fn fsel40(&mut self) -> FSEL40_W<0> { + pub fn fsel40(&mut self) -> FSEL40_W { FSEL40_W::new(self) } #[doc = "Bits 3:5 - Function Select 41"] #[inline(always)] #[must_use] - pub fn fsel41(&mut self) -> FSEL41_W<3> { + pub fn fsel41(&mut self) -> FSEL41_W { FSEL41_W::new(self) } #[doc = "Bits 6:8 - Function Select 42"] #[inline(always)] #[must_use] - pub fn fsel42(&mut self) -> FSEL42_W<6> { + pub fn fsel42(&mut self) -> FSEL42_W { FSEL42_W::new(self) } #[doc = "Bits 9:11 - Function Select 43"] #[inline(always)] #[must_use] - pub fn fsel43(&mut self) -> FSEL43_W<9> { + pub fn fsel43(&mut self) -> FSEL43_W { FSEL43_W::new(self) } #[doc = "Bits 12:14 - Function Select 44"] #[inline(always)] #[must_use] - pub fn fsel44(&mut self) -> FSEL44_W<12> { + pub fn fsel44(&mut self) -> FSEL44_W { FSEL44_W::new(self) } #[doc = "Bits 15:17 - Function Select 45"] #[inline(always)] #[must_use] - pub fn fsel45(&mut self) -> FSEL45_W<15> { + pub fn fsel45(&mut self) -> FSEL45_W { FSEL45_W::new(self) } #[doc = "Bits 18:20 - Function Select 46"] #[inline(always)] #[must_use] - pub fn fsel46(&mut self) -> FSEL46_W<18> { + pub fn fsel46(&mut self) -> FSEL46_W { FSEL46_W::new(self) } #[doc = "Bits 21:23 - Function Select 47"] #[inline(always)] #[must_use] - pub fn fsel47(&mut self) -> FSEL47_W<21> { + pub fn fsel47(&mut self) -> FSEL47_W { FSEL47_W::new(self) } #[doc = "Bits 24:26 - Function Select 48"] #[inline(always)] #[must_use] - pub fn fsel48(&mut self) -> FSEL48_W<24> { + pub fn fsel48(&mut self) -> FSEL48_W { FSEL48_W::new(self) } #[doc = "Bits 27:29 - Function Select 49"] #[inline(always)] #[must_use] - pub fn fsel49(&mut self) -> FSEL49_W<27> { + pub fn fsel49(&mut self) -> FSEL49_W { FSEL49_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel4](index.html) module"] +#[doc = "GPIO Function Select 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel4::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL4_SPEC; impl crate::RegisterSpec for GPFSEL4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel4::R](R) reader structure"] -impl crate::Readable for GPFSEL4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel4::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel4::R`](R) reader structure"] +impl crate::Readable for GPFSEL4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel4::W`](W) writer structure"] impl crate::Writable for GPFSEL4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpfsel5.rs b/crates/bcm2837-lpa/src/gpio/gpfsel5.rs index 7195017..bb2d446 100644 --- a/crates/bcm2837-lpa/src/gpio/gpfsel5.rs +++ b/crates/bcm2837-lpa/src/gpio/gpfsel5.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPFSEL5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPFSEL5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSEL50` reader - Function Select 50"] -pub type FSEL50_R = crate::FieldReader; +pub type FSEL50_R = crate::FieldReader; #[doc = "Function Select 50"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -63,10 +31,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL50_A { + type Ux = u8; +} impl FSEL50_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL50_A { + pub const fn variant(&self) -> FSEL50_A { match self.bits { 0 => FSEL50_A::INPUT, 1 => FSEL50_A::OUTPUT, @@ -79,94 +50,97 @@ impl FSEL50_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL50_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL50_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL50_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL50_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL50_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT0`"] + #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] pub fn is_sd1_dat0(&self) -> bool { *self == FSEL50_A::SD1_DAT0 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL50_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL50_A::RESERVED5 } } #[doc = "Field `FSEL50` writer - Function Select 50"] -pub type FSEL50_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL50_A, 3, O>; -impl<'a, const O: u8> FSEL50_W<'a, O> { +pub type FSEL50_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL50_A>; +impl<'a, REG, const O: u8> FSEL50_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL50_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL50_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT0"] #[inline(always)] - pub fn sd1_dat0(self) -> &'a mut W { + pub fn sd1_dat0(self) -> &'a mut crate::W { self.variant(FSEL50_A::SD1_DAT0) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL50_A::RESERVED5) } } #[doc = "Field `FSEL51` reader - Function Select 51"] -pub type FSEL51_R = crate::FieldReader; +pub type FSEL51_R = crate::FieldReader; #[doc = "Function Select 51"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -194,10 +168,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL51_A { + type Ux = u8; +} impl FSEL51_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL51_A { + pub const fn variant(&self) -> FSEL51_A { match self.bits { 0 => FSEL51_A::INPUT, 1 => FSEL51_A::OUTPUT, @@ -210,94 +187,97 @@ impl FSEL51_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL51_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL51_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL51_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL51_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL51_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT1`"] + #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] pub fn is_sd1_dat1(&self) -> bool { *self == FSEL51_A::SD1_DAT1 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL51_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL51_A::RESERVED5 } } #[doc = "Field `FSEL51` writer - Function Select 51"] -pub type FSEL51_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL51_A, 3, O>; -impl<'a, const O: u8> FSEL51_W<'a, O> { +pub type FSEL51_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL51_A>; +impl<'a, REG, const O: u8> FSEL51_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL51_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL51_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT1"] #[inline(always)] - pub fn sd1_dat1(self) -> &'a mut W { + pub fn sd1_dat1(self) -> &'a mut crate::W { self.variant(FSEL51_A::SD1_DAT1) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL51_A::RESERVED5) } } #[doc = "Field `FSEL52` reader - Function Select 52"] -pub type FSEL52_R = crate::FieldReader; +pub type FSEL52_R = crate::FieldReader; #[doc = "Function Select 52"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -325,10 +305,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL52_A { + type Ux = u8; +} impl FSEL52_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL52_A { + pub const fn variant(&self) -> FSEL52_A { match self.bits { 0 => FSEL52_A::INPUT, 1 => FSEL52_A::OUTPUT, @@ -341,94 +324,97 @@ impl FSEL52_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL52_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL52_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL52_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL52_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL52_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT2`"] + #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] pub fn is_sd1_dat2(&self) -> bool { *self == FSEL52_A::SD1_DAT2 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL52_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL52_A::RESERVED5 } } #[doc = "Field `FSEL52` writer - Function Select 52"] -pub type FSEL52_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL52_A, 3, O>; -impl<'a, const O: u8> FSEL52_W<'a, O> { +pub type FSEL52_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL52_A>; +impl<'a, REG, const O: u8> FSEL52_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL52_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL52_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT2"] #[inline(always)] - pub fn sd1_dat2(self) -> &'a mut W { + pub fn sd1_dat2(self) -> &'a mut crate::W { self.variant(FSEL52_A::SD1_DAT2) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL52_A::RESERVED5) } } #[doc = "Field `FSEL53` reader - Function Select 53"] -pub type FSEL53_R = crate::FieldReader; +pub type FSEL53_R = crate::FieldReader; #[doc = "Function Select 53"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -456,10 +442,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FSEL53_A { + type Ux = u8; +} impl FSEL53_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSEL53_A { + pub const fn variant(&self) -> FSEL53_A { match self.bits { 0 => FSEL53_A::INPUT, 1 => FSEL53_A::OUTPUT, @@ -472,89 +461,92 @@ impl FSEL53_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `INPUT`"] + #[doc = "Pin is an input"] #[inline(always)] pub fn is_input(&self) -> bool { *self == FSEL53_A::INPUT } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "Pin is an output"] #[inline(always)] pub fn is_output(&self) -> bool { *self == FSEL53_A::OUTPUT } - #[doc = "Checks if the value of the field is `RESERVED0`"] + #[doc = "Alt function 0 reserved"] #[inline(always)] pub fn is_reserved0(&self) -> bool { *self == FSEL53_A::RESERVED0 } - #[doc = "Checks if the value of the field is `RESERVED1`"] + #[doc = "Alt function 1 reserved"] #[inline(always)] pub fn is_reserved1(&self) -> bool { *self == FSEL53_A::RESERVED1 } - #[doc = "Checks if the value of the field is `RESERVED2`"] + #[doc = "Alt function 2 reserved"] #[inline(always)] pub fn is_reserved2(&self) -> bool { *self == FSEL53_A::RESERVED2 } - #[doc = "Checks if the value of the field is `SD1_DAT3`"] + #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] pub fn is_sd1_dat3(&self) -> bool { *self == FSEL53_A::SD1_DAT3 } - #[doc = "Checks if the value of the field is `RESERVED4`"] + #[doc = "Alt function 4 reserved"] #[inline(always)] pub fn is_reserved4(&self) -> bool { *self == FSEL53_A::RESERVED4 } - #[doc = "Checks if the value of the field is `RESERVED5`"] + #[doc = "Alt function 5 reserved"] #[inline(always)] pub fn is_reserved5(&self) -> bool { *self == FSEL53_A::RESERVED5 } } #[doc = "Field `FSEL53` writer - Function Select 53"] -pub type FSEL53_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GPFSEL5_SPEC, u8, FSEL53_A, 3, O>; -impl<'a, const O: u8> FSEL53_W<'a, O> { +pub type FSEL53_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, FSEL53_A>; +impl<'a, REG, const O: u8> FSEL53_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Pin is an input"] #[inline(always)] - pub fn input(self) -> &'a mut W { + pub fn input(self) -> &'a mut crate::W { self.variant(FSEL53_A::INPUT) } #[doc = "Pin is an output"] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(FSEL53_A::OUTPUT) } #[doc = "Alt function 0 reserved"] #[inline(always)] - pub fn reserved0(self) -> &'a mut W { + pub fn reserved0(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED0) } #[doc = "Alt function 1 reserved"] #[inline(always)] - pub fn reserved1(self) -> &'a mut W { + pub fn reserved1(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED1) } #[doc = "Alt function 2 reserved"] #[inline(always)] - pub fn reserved2(self) -> &'a mut W { + pub fn reserved2(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED2) } #[doc = "Pin is connected to SD1_DAT3"] #[inline(always)] - pub fn sd1_dat3(self) -> &'a mut W { + pub fn sd1_dat3(self) -> &'a mut crate::W { self.variant(FSEL53_A::SD1_DAT3) } #[doc = "Alt function 4 reserved"] #[inline(always)] - pub fn reserved4(self) -> &'a mut W { + pub fn reserved4(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED4) } #[doc = "Alt function 5 reserved"] #[inline(always)] - pub fn reserved5(self) -> &'a mut W { + pub fn reserved5(self) -> &'a mut crate::W { self.variant(FSEL53_A::RESERVED5) } } @@ -580,50 +572,66 @@ impl R { FSEL53_R::new(((self.bits >> 9) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPFSEL5") + .field("fsel50", &format_args!("{}", self.fsel50().bits())) + .field("fsel51", &format_args!("{}", self.fsel51().bits())) + .field("fsel52", &format_args!("{}", self.fsel52().bits())) + .field("fsel53", &format_args!("{}", self.fsel53().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - Function Select 50"] #[inline(always)] #[must_use] - pub fn fsel50(&mut self) -> FSEL50_W<0> { + pub fn fsel50(&mut self) -> FSEL50_W { FSEL50_W::new(self) } #[doc = "Bits 3:5 - Function Select 51"] #[inline(always)] #[must_use] - pub fn fsel51(&mut self) -> FSEL51_W<3> { + pub fn fsel51(&mut self) -> FSEL51_W { FSEL51_W::new(self) } #[doc = "Bits 6:8 - Function Select 52"] #[inline(always)] #[must_use] - pub fn fsel52(&mut self) -> FSEL52_W<6> { + pub fn fsel52(&mut self) -> FSEL52_W { FSEL52_W::new(self) } #[doc = "Bits 9:11 - Function Select 53"] #[inline(always)] #[must_use] - pub fn fsel53(&mut self) -> FSEL53_W<9> { + pub fn fsel53(&mut self) -> FSEL53_W { FSEL53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Function Select 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpfsel5](index.html) module"] +#[doc = "GPIO Function Select 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpfsel5::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpfsel5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPFSEL5_SPEC; impl crate::RegisterSpec for GPFSEL5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpfsel5::R](R) reader structure"] -impl crate::Readable for GPFSEL5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpfsel5::W](W) writer structure"] +#[doc = "`read()` method returns [`gpfsel5::R`](R) reader structure"] +impl crate::Readable for GPFSEL5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpfsel5::W`](W) writer structure"] impl crate::Writable for GPFSEL5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gphen0.rs b/crates/bcm2837-lpa/src/gpio/gphen0.rs index b45a414..d788bbf 100644 --- a/crates/bcm2837-lpa/src/gpio/gphen0.rs +++ b/crates/bcm2837-lpa/src/gpio/gphen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPHEN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPHEN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HEN0` reader - High detect enabled 0"] -pub type HEN0_R = crate::BitReader; +pub type HEN0_R = crate::BitReader; #[doc = "Field `HEN0` writer - High detect enabled 0"] -pub type HEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN1` reader - High detect enabled 1"] -pub type HEN1_R = crate::BitReader; +pub type HEN1_R = crate::BitReader; #[doc = "Field `HEN1` writer - High detect enabled 1"] -pub type HEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN2` reader - High detect enabled 2"] -pub type HEN2_R = crate::BitReader; +pub type HEN2_R = crate::BitReader; #[doc = "Field `HEN2` writer - High detect enabled 2"] -pub type HEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN3` reader - High detect enabled 3"] -pub type HEN3_R = crate::BitReader; +pub type HEN3_R = crate::BitReader; #[doc = "Field `HEN3` writer - High detect enabled 3"] -pub type HEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN4` reader - High detect enabled 4"] -pub type HEN4_R = crate::BitReader; +pub type HEN4_R = crate::BitReader; #[doc = "Field `HEN4` writer - High detect enabled 4"] -pub type HEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN5` reader - High detect enabled 5"] -pub type HEN5_R = crate::BitReader; +pub type HEN5_R = crate::BitReader; #[doc = "Field `HEN5` writer - High detect enabled 5"] -pub type HEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN6` reader - High detect enabled 6"] -pub type HEN6_R = crate::BitReader; +pub type HEN6_R = crate::BitReader; #[doc = "Field `HEN6` writer - High detect enabled 6"] -pub type HEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN7` reader - High detect enabled 7"] -pub type HEN7_R = crate::BitReader; +pub type HEN7_R = crate::BitReader; #[doc = "Field `HEN7` writer - High detect enabled 7"] -pub type HEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN8` reader - High detect enabled 8"] -pub type HEN8_R = crate::BitReader; +pub type HEN8_R = crate::BitReader; #[doc = "Field `HEN8` writer - High detect enabled 8"] -pub type HEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN9` reader - High detect enabled 9"] -pub type HEN9_R = crate::BitReader; +pub type HEN9_R = crate::BitReader; #[doc = "Field `HEN9` writer - High detect enabled 9"] -pub type HEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN10` reader - High detect enabled 10"] -pub type HEN10_R = crate::BitReader; +pub type HEN10_R = crate::BitReader; #[doc = "Field `HEN10` writer - High detect enabled 10"] -pub type HEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN11` reader - High detect enabled 11"] -pub type HEN11_R = crate::BitReader; +pub type HEN11_R = crate::BitReader; #[doc = "Field `HEN11` writer - High detect enabled 11"] -pub type HEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN12` reader - High detect enabled 12"] -pub type HEN12_R = crate::BitReader; +pub type HEN12_R = crate::BitReader; #[doc = "Field `HEN12` writer - High detect enabled 12"] -pub type HEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN13` reader - High detect enabled 13"] -pub type HEN13_R = crate::BitReader; +pub type HEN13_R = crate::BitReader; #[doc = "Field `HEN13` writer - High detect enabled 13"] -pub type HEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN14` reader - High detect enabled 14"] -pub type HEN14_R = crate::BitReader; +pub type HEN14_R = crate::BitReader; #[doc = "Field `HEN14` writer - High detect enabled 14"] -pub type HEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN15` reader - High detect enabled 15"] -pub type HEN15_R = crate::BitReader; +pub type HEN15_R = crate::BitReader; #[doc = "Field `HEN15` writer - High detect enabled 15"] -pub type HEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN16` reader - High detect enabled 16"] -pub type HEN16_R = crate::BitReader; +pub type HEN16_R = crate::BitReader; #[doc = "Field `HEN16` writer - High detect enabled 16"] -pub type HEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN17` reader - High detect enabled 17"] -pub type HEN17_R = crate::BitReader; +pub type HEN17_R = crate::BitReader; #[doc = "Field `HEN17` writer - High detect enabled 17"] -pub type HEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN18` reader - High detect enabled 18"] -pub type HEN18_R = crate::BitReader; +pub type HEN18_R = crate::BitReader; #[doc = "Field `HEN18` writer - High detect enabled 18"] -pub type HEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN19` reader - High detect enabled 19"] -pub type HEN19_R = crate::BitReader; +pub type HEN19_R = crate::BitReader; #[doc = "Field `HEN19` writer - High detect enabled 19"] -pub type HEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN20` reader - High detect enabled 20"] -pub type HEN20_R = crate::BitReader; +pub type HEN20_R = crate::BitReader; #[doc = "Field `HEN20` writer - High detect enabled 20"] -pub type HEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN21` reader - High detect enabled 21"] -pub type HEN21_R = crate::BitReader; +pub type HEN21_R = crate::BitReader; #[doc = "Field `HEN21` writer - High detect enabled 21"] -pub type HEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN22` reader - High detect enabled 22"] -pub type HEN22_R = crate::BitReader; +pub type HEN22_R = crate::BitReader; #[doc = "Field `HEN22` writer - High detect enabled 22"] -pub type HEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN23` reader - High detect enabled 23"] -pub type HEN23_R = crate::BitReader; +pub type HEN23_R = crate::BitReader; #[doc = "Field `HEN23` writer - High detect enabled 23"] -pub type HEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN24` reader - High detect enabled 24"] -pub type HEN24_R = crate::BitReader; +pub type HEN24_R = crate::BitReader; #[doc = "Field `HEN24` writer - High detect enabled 24"] -pub type HEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN25` reader - High detect enabled 25"] -pub type HEN25_R = crate::BitReader; +pub type HEN25_R = crate::BitReader; #[doc = "Field `HEN25` writer - High detect enabled 25"] -pub type HEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN26` reader - High detect enabled 26"] -pub type HEN26_R = crate::BitReader; +pub type HEN26_R = crate::BitReader; #[doc = "Field `HEN26` writer - High detect enabled 26"] -pub type HEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN27` reader - High detect enabled 27"] -pub type HEN27_R = crate::BitReader; +pub type HEN27_R = crate::BitReader; #[doc = "Field `HEN27` writer - High detect enabled 27"] -pub type HEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN28` reader - High detect enabled 28"] -pub type HEN28_R = crate::BitReader; +pub type HEN28_R = crate::BitReader; #[doc = "Field `HEN28` writer - High detect enabled 28"] -pub type HEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN29` reader - High detect enabled 29"] -pub type HEN29_R = crate::BitReader; +pub type HEN29_R = crate::BitReader; #[doc = "Field `HEN29` writer - High detect enabled 29"] -pub type HEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN30` reader - High detect enabled 30"] -pub type HEN30_R = crate::BitReader; +pub type HEN30_R = crate::BitReader; #[doc = "Field `HEN30` writer - High detect enabled 30"] -pub type HEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN31` reader - High detect enabled 31"] -pub type HEN31_R = crate::BitReader; +pub type HEN31_R = crate::BitReader; #[doc = "Field `HEN31` writer - High detect enabled 31"] -pub type HEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN0_SPEC, bool, O>; +pub type HEN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - High detect enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { HEN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPHEN0") + .field("hen0", &format_args!("{}", self.hen0().bit())) + .field("hen1", &format_args!("{}", self.hen1().bit())) + .field("hen2", &format_args!("{}", self.hen2().bit())) + .field("hen3", &format_args!("{}", self.hen3().bit())) + .field("hen4", &format_args!("{}", self.hen4().bit())) + .field("hen5", &format_args!("{}", self.hen5().bit())) + .field("hen6", &format_args!("{}", self.hen6().bit())) + .field("hen7", &format_args!("{}", self.hen7().bit())) + .field("hen8", &format_args!("{}", self.hen8().bit())) + .field("hen9", &format_args!("{}", self.hen9().bit())) + .field("hen10", &format_args!("{}", self.hen10().bit())) + .field("hen11", &format_args!("{}", self.hen11().bit())) + .field("hen12", &format_args!("{}", self.hen12().bit())) + .field("hen13", &format_args!("{}", self.hen13().bit())) + .field("hen14", &format_args!("{}", self.hen14().bit())) + .field("hen15", &format_args!("{}", self.hen15().bit())) + .field("hen16", &format_args!("{}", self.hen16().bit())) + .field("hen17", &format_args!("{}", self.hen17().bit())) + .field("hen18", &format_args!("{}", self.hen18().bit())) + .field("hen19", &format_args!("{}", self.hen19().bit())) + .field("hen20", &format_args!("{}", self.hen20().bit())) + .field("hen21", &format_args!("{}", self.hen21().bit())) + .field("hen22", &format_args!("{}", self.hen22().bit())) + .field("hen23", &format_args!("{}", self.hen23().bit())) + .field("hen24", &format_args!("{}", self.hen24().bit())) + .field("hen25", &format_args!("{}", self.hen25().bit())) + .field("hen26", &format_args!("{}", self.hen26().bit())) + .field("hen27", &format_args!("{}", self.hen27().bit())) + .field("hen28", &format_args!("{}", self.hen28().bit())) + .field("hen29", &format_args!("{}", self.hen29().bit())) + .field("hen30", &format_args!("{}", self.hen30().bit())) + .field("hen31", &format_args!("{}", self.hen31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - High detect enabled 0"] #[inline(always)] #[must_use] - pub fn hen0(&mut self) -> HEN0_W<0> { + pub fn hen0(&mut self) -> HEN0_W { HEN0_W::new(self) } #[doc = "Bit 1 - High detect enabled 1"] #[inline(always)] #[must_use] - pub fn hen1(&mut self) -> HEN1_W<1> { + pub fn hen1(&mut self) -> HEN1_W { HEN1_W::new(self) } #[doc = "Bit 2 - High detect enabled 2"] #[inline(always)] #[must_use] - pub fn hen2(&mut self) -> HEN2_W<2> { + pub fn hen2(&mut self) -> HEN2_W { HEN2_W::new(self) } #[doc = "Bit 3 - High detect enabled 3"] #[inline(always)] #[must_use] - pub fn hen3(&mut self) -> HEN3_W<3> { + pub fn hen3(&mut self) -> HEN3_W { HEN3_W::new(self) } #[doc = "Bit 4 - High detect enabled 4"] #[inline(always)] #[must_use] - pub fn hen4(&mut self) -> HEN4_W<4> { + pub fn hen4(&mut self) -> HEN4_W { HEN4_W::new(self) } #[doc = "Bit 5 - High detect enabled 5"] #[inline(always)] #[must_use] - pub fn hen5(&mut self) -> HEN5_W<5> { + pub fn hen5(&mut self) -> HEN5_W { HEN5_W::new(self) } #[doc = "Bit 6 - High detect enabled 6"] #[inline(always)] #[must_use] - pub fn hen6(&mut self) -> HEN6_W<6> { + pub fn hen6(&mut self) -> HEN6_W { HEN6_W::new(self) } #[doc = "Bit 7 - High detect enabled 7"] #[inline(always)] #[must_use] - pub fn hen7(&mut self) -> HEN7_W<7> { + pub fn hen7(&mut self) -> HEN7_W { HEN7_W::new(self) } #[doc = "Bit 8 - High detect enabled 8"] #[inline(always)] #[must_use] - pub fn hen8(&mut self) -> HEN8_W<8> { + pub fn hen8(&mut self) -> HEN8_W { HEN8_W::new(self) } #[doc = "Bit 9 - High detect enabled 9"] #[inline(always)] #[must_use] - pub fn hen9(&mut self) -> HEN9_W<9> { + pub fn hen9(&mut self) -> HEN9_W { HEN9_W::new(self) } #[doc = "Bit 10 - High detect enabled 10"] #[inline(always)] #[must_use] - pub fn hen10(&mut self) -> HEN10_W<10> { + pub fn hen10(&mut self) -> HEN10_W { HEN10_W::new(self) } #[doc = "Bit 11 - High detect enabled 11"] #[inline(always)] #[must_use] - pub fn hen11(&mut self) -> HEN11_W<11> { + pub fn hen11(&mut self) -> HEN11_W { HEN11_W::new(self) } #[doc = "Bit 12 - High detect enabled 12"] #[inline(always)] #[must_use] - pub fn hen12(&mut self) -> HEN12_W<12> { + pub fn hen12(&mut self) -> HEN12_W { HEN12_W::new(self) } #[doc = "Bit 13 - High detect enabled 13"] #[inline(always)] #[must_use] - pub fn hen13(&mut self) -> HEN13_W<13> { + pub fn hen13(&mut self) -> HEN13_W { HEN13_W::new(self) } #[doc = "Bit 14 - High detect enabled 14"] #[inline(always)] #[must_use] - pub fn hen14(&mut self) -> HEN14_W<14> { + pub fn hen14(&mut self) -> HEN14_W { HEN14_W::new(self) } #[doc = "Bit 15 - High detect enabled 15"] #[inline(always)] #[must_use] - pub fn hen15(&mut self) -> HEN15_W<15> { + pub fn hen15(&mut self) -> HEN15_W { HEN15_W::new(self) } #[doc = "Bit 16 - High detect enabled 16"] #[inline(always)] #[must_use] - pub fn hen16(&mut self) -> HEN16_W<16> { + pub fn hen16(&mut self) -> HEN16_W { HEN16_W::new(self) } #[doc = "Bit 17 - High detect enabled 17"] #[inline(always)] #[must_use] - pub fn hen17(&mut self) -> HEN17_W<17> { + pub fn hen17(&mut self) -> HEN17_W { HEN17_W::new(self) } #[doc = "Bit 18 - High detect enabled 18"] #[inline(always)] #[must_use] - pub fn hen18(&mut self) -> HEN18_W<18> { + pub fn hen18(&mut self) -> HEN18_W { HEN18_W::new(self) } #[doc = "Bit 19 - High detect enabled 19"] #[inline(always)] #[must_use] - pub fn hen19(&mut self) -> HEN19_W<19> { + pub fn hen19(&mut self) -> HEN19_W { HEN19_W::new(self) } #[doc = "Bit 20 - High detect enabled 20"] #[inline(always)] #[must_use] - pub fn hen20(&mut self) -> HEN20_W<20> { + pub fn hen20(&mut self) -> HEN20_W { HEN20_W::new(self) } #[doc = "Bit 21 - High detect enabled 21"] #[inline(always)] #[must_use] - pub fn hen21(&mut self) -> HEN21_W<21> { + pub fn hen21(&mut self) -> HEN21_W { HEN21_W::new(self) } #[doc = "Bit 22 - High detect enabled 22"] #[inline(always)] #[must_use] - pub fn hen22(&mut self) -> HEN22_W<22> { + pub fn hen22(&mut self) -> HEN22_W { HEN22_W::new(self) } #[doc = "Bit 23 - High detect enabled 23"] #[inline(always)] #[must_use] - pub fn hen23(&mut self) -> HEN23_W<23> { + pub fn hen23(&mut self) -> HEN23_W { HEN23_W::new(self) } #[doc = "Bit 24 - High detect enabled 24"] #[inline(always)] #[must_use] - pub fn hen24(&mut self) -> HEN24_W<24> { + pub fn hen24(&mut self) -> HEN24_W { HEN24_W::new(self) } #[doc = "Bit 25 - High detect enabled 25"] #[inline(always)] #[must_use] - pub fn hen25(&mut self) -> HEN25_W<25> { + pub fn hen25(&mut self) -> HEN25_W { HEN25_W::new(self) } #[doc = "Bit 26 - High detect enabled 26"] #[inline(always)] #[must_use] - pub fn hen26(&mut self) -> HEN26_W<26> { + pub fn hen26(&mut self) -> HEN26_W { HEN26_W::new(self) } #[doc = "Bit 27 - High detect enabled 27"] #[inline(always)] #[must_use] - pub fn hen27(&mut self) -> HEN27_W<27> { + pub fn hen27(&mut self) -> HEN27_W { HEN27_W::new(self) } #[doc = "Bit 28 - High detect enabled 28"] #[inline(always)] #[must_use] - pub fn hen28(&mut self) -> HEN28_W<28> { + pub fn hen28(&mut self) -> HEN28_W { HEN28_W::new(self) } #[doc = "Bit 29 - High detect enabled 29"] #[inline(always)] #[must_use] - pub fn hen29(&mut self) -> HEN29_W<29> { + pub fn hen29(&mut self) -> HEN29_W { HEN29_W::new(self) } #[doc = "Bit 30 - High detect enabled 30"] #[inline(always)] #[must_use] - pub fn hen30(&mut self) -> HEN30_W<30> { + pub fn hen30(&mut self) -> HEN30_W { HEN30_W::new(self) } #[doc = "Bit 31 - High detect enabled 31"] #[inline(always)] #[must_use] - pub fn hen31(&mut self) -> HEN31_W<31> { + pub fn hen31(&mut self) -> HEN31_W { HEN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin High Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gphen0](index.html) module"] +#[doc = "GPIO Pin High Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gphen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gphen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPHEN0_SPEC; impl crate::RegisterSpec for GPHEN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gphen0::R](R) reader structure"] -impl crate::Readable for GPHEN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gphen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gphen0::R`](R) reader structure"] +impl crate::Readable for GPHEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gphen0::W`](W) writer structure"] impl crate::Writable for GPHEN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gphen1.rs b/crates/bcm2837-lpa/src/gpio/gphen1.rs index 23c512c..3d0aa21 100644 --- a/crates/bcm2837-lpa/src/gpio/gphen1.rs +++ b/crates/bcm2837-lpa/src/gpio/gphen1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPHEN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPHEN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HEN32` reader - High detect enabled 32"] -pub type HEN32_R = crate::BitReader; +pub type HEN32_R = crate::BitReader; #[doc = "Field `HEN32` writer - High detect enabled 32"] -pub type HEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN33` reader - High detect enabled 33"] -pub type HEN33_R = crate::BitReader; +pub type HEN33_R = crate::BitReader; #[doc = "Field `HEN33` writer - High detect enabled 33"] -pub type HEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN34` reader - High detect enabled 34"] -pub type HEN34_R = crate::BitReader; +pub type HEN34_R = crate::BitReader; #[doc = "Field `HEN34` writer - High detect enabled 34"] -pub type HEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN35` reader - High detect enabled 35"] -pub type HEN35_R = crate::BitReader; +pub type HEN35_R = crate::BitReader; #[doc = "Field `HEN35` writer - High detect enabled 35"] -pub type HEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN36` reader - High detect enabled 36"] -pub type HEN36_R = crate::BitReader; +pub type HEN36_R = crate::BitReader; #[doc = "Field `HEN36` writer - High detect enabled 36"] -pub type HEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN37` reader - High detect enabled 37"] -pub type HEN37_R = crate::BitReader; +pub type HEN37_R = crate::BitReader; #[doc = "Field `HEN37` writer - High detect enabled 37"] -pub type HEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN38` reader - High detect enabled 38"] -pub type HEN38_R = crate::BitReader; +pub type HEN38_R = crate::BitReader; #[doc = "Field `HEN38` writer - High detect enabled 38"] -pub type HEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN39` reader - High detect enabled 39"] -pub type HEN39_R = crate::BitReader; +pub type HEN39_R = crate::BitReader; #[doc = "Field `HEN39` writer - High detect enabled 39"] -pub type HEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN40` reader - High detect enabled 40"] -pub type HEN40_R = crate::BitReader; +pub type HEN40_R = crate::BitReader; #[doc = "Field `HEN40` writer - High detect enabled 40"] -pub type HEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN41` reader - High detect enabled 41"] -pub type HEN41_R = crate::BitReader; +pub type HEN41_R = crate::BitReader; #[doc = "Field `HEN41` writer - High detect enabled 41"] -pub type HEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN42` reader - High detect enabled 42"] -pub type HEN42_R = crate::BitReader; +pub type HEN42_R = crate::BitReader; #[doc = "Field `HEN42` writer - High detect enabled 42"] -pub type HEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN43` reader - High detect enabled 43"] -pub type HEN43_R = crate::BitReader; +pub type HEN43_R = crate::BitReader; #[doc = "Field `HEN43` writer - High detect enabled 43"] -pub type HEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN44` reader - High detect enabled 44"] -pub type HEN44_R = crate::BitReader; +pub type HEN44_R = crate::BitReader; #[doc = "Field `HEN44` writer - High detect enabled 44"] -pub type HEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN45` reader - High detect enabled 45"] -pub type HEN45_R = crate::BitReader; +pub type HEN45_R = crate::BitReader; #[doc = "Field `HEN45` writer - High detect enabled 45"] -pub type HEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN46` reader - High detect enabled 46"] -pub type HEN46_R = crate::BitReader; +pub type HEN46_R = crate::BitReader; #[doc = "Field `HEN46` writer - High detect enabled 46"] -pub type HEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN47` reader - High detect enabled 47"] -pub type HEN47_R = crate::BitReader; +pub type HEN47_R = crate::BitReader; #[doc = "Field `HEN47` writer - High detect enabled 47"] -pub type HEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN48` reader - High detect enabled 48"] -pub type HEN48_R = crate::BitReader; +pub type HEN48_R = crate::BitReader; #[doc = "Field `HEN48` writer - High detect enabled 48"] -pub type HEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN49` reader - High detect enabled 49"] -pub type HEN49_R = crate::BitReader; +pub type HEN49_R = crate::BitReader; #[doc = "Field `HEN49` writer - High detect enabled 49"] -pub type HEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN50` reader - High detect enabled 50"] -pub type HEN50_R = crate::BitReader; +pub type HEN50_R = crate::BitReader; #[doc = "Field `HEN50` writer - High detect enabled 50"] -pub type HEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN51` reader - High detect enabled 51"] -pub type HEN51_R = crate::BitReader; +pub type HEN51_R = crate::BitReader; #[doc = "Field `HEN51` writer - High detect enabled 51"] -pub type HEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN52` reader - High detect enabled 52"] -pub type HEN52_R = crate::BitReader; +pub type HEN52_R = crate::BitReader; #[doc = "Field `HEN52` writer - High detect enabled 52"] -pub type HEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HEN53` reader - High detect enabled 53"] -pub type HEN53_R = crate::BitReader; +pub type HEN53_R = crate::BitReader; #[doc = "Field `HEN53` writer - High detect enabled 53"] -pub type HEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPHEN1_SPEC, bool, O>; +pub type HEN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - High detect enabled 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { HEN53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPHEN1") + .field("hen32", &format_args!("{}", self.hen32().bit())) + .field("hen33", &format_args!("{}", self.hen33().bit())) + .field("hen34", &format_args!("{}", self.hen34().bit())) + .field("hen35", &format_args!("{}", self.hen35().bit())) + .field("hen36", &format_args!("{}", self.hen36().bit())) + .field("hen37", &format_args!("{}", self.hen37().bit())) + .field("hen38", &format_args!("{}", self.hen38().bit())) + .field("hen39", &format_args!("{}", self.hen39().bit())) + .field("hen40", &format_args!("{}", self.hen40().bit())) + .field("hen41", &format_args!("{}", self.hen41().bit())) + .field("hen42", &format_args!("{}", self.hen42().bit())) + .field("hen43", &format_args!("{}", self.hen43().bit())) + .field("hen44", &format_args!("{}", self.hen44().bit())) + .field("hen45", &format_args!("{}", self.hen45().bit())) + .field("hen46", &format_args!("{}", self.hen46().bit())) + .field("hen47", &format_args!("{}", self.hen47().bit())) + .field("hen48", &format_args!("{}", self.hen48().bit())) + .field("hen49", &format_args!("{}", self.hen49().bit())) + .field("hen50", &format_args!("{}", self.hen50().bit())) + .field("hen51", &format_args!("{}", self.hen51().bit())) + .field("hen52", &format_args!("{}", self.hen52().bit())) + .field("hen53", &format_args!("{}", self.hen53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - High detect enabled 32"] #[inline(always)] #[must_use] - pub fn hen32(&mut self) -> HEN32_W<0> { + pub fn hen32(&mut self) -> HEN32_W { HEN32_W::new(self) } #[doc = "Bit 1 - High detect enabled 33"] #[inline(always)] #[must_use] - pub fn hen33(&mut self) -> HEN33_W<1> { + pub fn hen33(&mut self) -> HEN33_W { HEN33_W::new(self) } #[doc = "Bit 2 - High detect enabled 34"] #[inline(always)] #[must_use] - pub fn hen34(&mut self) -> HEN34_W<2> { + pub fn hen34(&mut self) -> HEN34_W { HEN34_W::new(self) } #[doc = "Bit 3 - High detect enabled 35"] #[inline(always)] #[must_use] - pub fn hen35(&mut self) -> HEN35_W<3> { + pub fn hen35(&mut self) -> HEN35_W { HEN35_W::new(self) } #[doc = "Bit 4 - High detect enabled 36"] #[inline(always)] #[must_use] - pub fn hen36(&mut self) -> HEN36_W<4> { + pub fn hen36(&mut self) -> HEN36_W { HEN36_W::new(self) } #[doc = "Bit 5 - High detect enabled 37"] #[inline(always)] #[must_use] - pub fn hen37(&mut self) -> HEN37_W<5> { + pub fn hen37(&mut self) -> HEN37_W { HEN37_W::new(self) } #[doc = "Bit 6 - High detect enabled 38"] #[inline(always)] #[must_use] - pub fn hen38(&mut self) -> HEN38_W<6> { + pub fn hen38(&mut self) -> HEN38_W { HEN38_W::new(self) } #[doc = "Bit 7 - High detect enabled 39"] #[inline(always)] #[must_use] - pub fn hen39(&mut self) -> HEN39_W<7> { + pub fn hen39(&mut self) -> HEN39_W { HEN39_W::new(self) } #[doc = "Bit 8 - High detect enabled 40"] #[inline(always)] #[must_use] - pub fn hen40(&mut self) -> HEN40_W<8> { + pub fn hen40(&mut self) -> HEN40_W { HEN40_W::new(self) } #[doc = "Bit 9 - High detect enabled 41"] #[inline(always)] #[must_use] - pub fn hen41(&mut self) -> HEN41_W<9> { + pub fn hen41(&mut self) -> HEN41_W { HEN41_W::new(self) } #[doc = "Bit 10 - High detect enabled 42"] #[inline(always)] #[must_use] - pub fn hen42(&mut self) -> HEN42_W<10> { + pub fn hen42(&mut self) -> HEN42_W { HEN42_W::new(self) } #[doc = "Bit 11 - High detect enabled 43"] #[inline(always)] #[must_use] - pub fn hen43(&mut self) -> HEN43_W<11> { + pub fn hen43(&mut self) -> HEN43_W { HEN43_W::new(self) } #[doc = "Bit 12 - High detect enabled 44"] #[inline(always)] #[must_use] - pub fn hen44(&mut self) -> HEN44_W<12> { + pub fn hen44(&mut self) -> HEN44_W { HEN44_W::new(self) } #[doc = "Bit 13 - High detect enabled 45"] #[inline(always)] #[must_use] - pub fn hen45(&mut self) -> HEN45_W<13> { + pub fn hen45(&mut self) -> HEN45_W { HEN45_W::new(self) } #[doc = "Bit 14 - High detect enabled 46"] #[inline(always)] #[must_use] - pub fn hen46(&mut self) -> HEN46_W<14> { + pub fn hen46(&mut self) -> HEN46_W { HEN46_W::new(self) } #[doc = "Bit 15 - High detect enabled 47"] #[inline(always)] #[must_use] - pub fn hen47(&mut self) -> HEN47_W<15> { + pub fn hen47(&mut self) -> HEN47_W { HEN47_W::new(self) } #[doc = "Bit 16 - High detect enabled 48"] #[inline(always)] #[must_use] - pub fn hen48(&mut self) -> HEN48_W<16> { + pub fn hen48(&mut self) -> HEN48_W { HEN48_W::new(self) } #[doc = "Bit 17 - High detect enabled 49"] #[inline(always)] #[must_use] - pub fn hen49(&mut self) -> HEN49_W<17> { + pub fn hen49(&mut self) -> HEN49_W { HEN49_W::new(self) } #[doc = "Bit 18 - High detect enabled 50"] #[inline(always)] #[must_use] - pub fn hen50(&mut self) -> HEN50_W<18> { + pub fn hen50(&mut self) -> HEN50_W { HEN50_W::new(self) } #[doc = "Bit 19 - High detect enabled 51"] #[inline(always)] #[must_use] - pub fn hen51(&mut self) -> HEN51_W<19> { + pub fn hen51(&mut self) -> HEN51_W { HEN51_W::new(self) } #[doc = "Bit 20 - High detect enabled 52"] #[inline(always)] #[must_use] - pub fn hen52(&mut self) -> HEN52_W<20> { + pub fn hen52(&mut self) -> HEN52_W { HEN52_W::new(self) } #[doc = "Bit 21 - High detect enabled 53"] #[inline(always)] #[must_use] - pub fn hen53(&mut self) -> HEN53_W<21> { + pub fn hen53(&mut self) -> HEN53_W { HEN53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin High Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gphen1](index.html) module"] +#[doc = "GPIO Pin High Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gphen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gphen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPHEN1_SPEC; impl crate::RegisterSpec for GPHEN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gphen1::R](R) reader structure"] -impl crate::Readable for GPHEN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gphen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gphen1::R`](R) reader structure"] +impl crate::Readable for GPHEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gphen1::W`](W) writer structure"] impl crate::Writable for GPHEN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs index 12b55c2..507543e 100644 --- a/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs +++ b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg0.rs @@ -1,41 +1,9 @@ #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPIO_PUP_PDN_CNTRL0` reader - Resistor select for 0"] -pub type GPIO_PUP_PDN_CNTRL0_R = crate::FieldReader; +pub type GPIO_PUP_PDN_CNTRL0_R = crate::FieldReader; #[doc = "Resistor select for 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -53,10 +21,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for BP_PULL_A { + type Ux = u8; +} impl GPIO_PUP_PDN_CNTRL0_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(BP_PULL_A::NONE), 1 => Some(BP_PULL_A::UP), @@ -64,39 +35,42 @@ impl GPIO_PUP_PDN_CNTRL0_R { _ => None, } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "No pull"] #[inline(always)] pub fn is_none(&self) -> bool { *self == BP_PULL_A::NONE } - #[doc = "Checks if the value of the field is `UP`"] + #[doc = "Pull up"] #[inline(always)] pub fn is_up(&self) -> bool { *self == BP_PULL_A::UP } - #[doc = "Checks if the value of the field is `DOWN`"] + #[doc = "Pull down"] #[inline(always)] pub fn is_down(&self) -> bool { *self == BP_PULL_A::DOWN } } #[doc = "Field `GPIO_PUP_PDN_CNTRL0` writer - Resistor select for 0"] -pub type GPIO_PUP_PDN_CNTRL0_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG0_SPEC, u8, BP_PULL_A, 2, O>; -impl<'a, const O: u8> GPIO_PUP_PDN_CNTRL0_W<'a, O> { +pub type GPIO_PUP_PDN_CNTRL0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, BP_PULL_A>; +impl<'a, REG, const O: u8> GPIO_PUP_PDN_CNTRL0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "No pull"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(BP_PULL_A::NONE) } #[doc = "Pull up"] #[inline(always)] - pub fn up(self) -> &'a mut W { + pub fn up(self) -> &'a mut crate::W { self.variant(BP_PULL_A::UP) } #[doc = "Pull down"] #[inline(always)] - pub fn down(self) -> &'a mut W { + pub fn down(self) -> &'a mut crate::W { self.variant(BP_PULL_A::DOWN) } } @@ -242,122 +216,230 @@ impl R { GPIO_PUP_PDN_CNTRL15_R::new(((self.bits >> 30) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PUP_PDN_CNTRL_REG0") + .field( + "gpio_pup_pdn_cntrl0", + &format_args!("{}", self.gpio_pup_pdn_cntrl0().bits()), + ) + .field( + "gpio_pup_pdn_cntrl1", + &format_args!("{}", self.gpio_pup_pdn_cntrl1().bits()), + ) + .field( + "gpio_pup_pdn_cntrl2", + &format_args!("{}", self.gpio_pup_pdn_cntrl2().bits()), + ) + .field( + "gpio_pup_pdn_cntrl3", + &format_args!("{}", self.gpio_pup_pdn_cntrl3().bits()), + ) + .field( + "gpio_pup_pdn_cntrl4", + &format_args!("{}", self.gpio_pup_pdn_cntrl4().bits()), + ) + .field( + "gpio_pup_pdn_cntrl5", + &format_args!("{}", self.gpio_pup_pdn_cntrl5().bits()), + ) + .field( + "gpio_pup_pdn_cntrl6", + &format_args!("{}", self.gpio_pup_pdn_cntrl6().bits()), + ) + .field( + "gpio_pup_pdn_cntrl7", + &format_args!("{}", self.gpio_pup_pdn_cntrl7().bits()), + ) + .field( + "gpio_pup_pdn_cntrl8", + &format_args!("{}", self.gpio_pup_pdn_cntrl8().bits()), + ) + .field( + "gpio_pup_pdn_cntrl9", + &format_args!("{}", self.gpio_pup_pdn_cntrl9().bits()), + ) + .field( + "gpio_pup_pdn_cntrl10", + &format_args!("{}", self.gpio_pup_pdn_cntrl10().bits()), + ) + .field( + "gpio_pup_pdn_cntrl11", + &format_args!("{}", self.gpio_pup_pdn_cntrl11().bits()), + ) + .field( + "gpio_pup_pdn_cntrl12", + &format_args!("{}", self.gpio_pup_pdn_cntrl12().bits()), + ) + .field( + "gpio_pup_pdn_cntrl13", + &format_args!("{}", self.gpio_pup_pdn_cntrl13().bits()), + ) + .field( + "gpio_pup_pdn_cntrl14", + &format_args!("{}", self.gpio_pup_pdn_cntrl14().bits()), + ) + .field( + "gpio_pup_pdn_cntrl15", + &format_args!("{}", self.gpio_pup_pdn_cntrl15().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Resistor select for 0"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl0(&mut self) -> GPIO_PUP_PDN_CNTRL0_W<0> { + pub fn gpio_pup_pdn_cntrl0( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL0_W { GPIO_PUP_PDN_CNTRL0_W::new(self) } #[doc = "Bits 2:3 - Resistor select for 1"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl1(&mut self) -> GPIO_PUP_PDN_CNTRL1_W<2> { + pub fn gpio_pup_pdn_cntrl1( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL1_W { GPIO_PUP_PDN_CNTRL1_W::new(self) } #[doc = "Bits 4:5 - Resistor select for 2"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl2(&mut self) -> GPIO_PUP_PDN_CNTRL2_W<4> { + pub fn gpio_pup_pdn_cntrl2( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL2_W { GPIO_PUP_PDN_CNTRL2_W::new(self) } #[doc = "Bits 6:7 - Resistor select for 3"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl3(&mut self) -> GPIO_PUP_PDN_CNTRL3_W<6> { + pub fn gpio_pup_pdn_cntrl3( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL3_W { GPIO_PUP_PDN_CNTRL3_W::new(self) } #[doc = "Bits 8:9 - Resistor select for 4"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl4(&mut self) -> GPIO_PUP_PDN_CNTRL4_W<8> { + pub fn gpio_pup_pdn_cntrl4( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL4_W { GPIO_PUP_PDN_CNTRL4_W::new(self) } #[doc = "Bits 10:11 - Resistor select for 5"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl5(&mut self) -> GPIO_PUP_PDN_CNTRL5_W<10> { + pub fn gpio_pup_pdn_cntrl5( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL5_W { GPIO_PUP_PDN_CNTRL5_W::new(self) } #[doc = "Bits 12:13 - Resistor select for 6"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl6(&mut self) -> GPIO_PUP_PDN_CNTRL6_W<12> { + pub fn gpio_pup_pdn_cntrl6( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL6_W { GPIO_PUP_PDN_CNTRL6_W::new(self) } #[doc = "Bits 14:15 - Resistor select for 7"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl7(&mut self) -> GPIO_PUP_PDN_CNTRL7_W<14> { + pub fn gpio_pup_pdn_cntrl7( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL7_W { GPIO_PUP_PDN_CNTRL7_W::new(self) } #[doc = "Bits 16:17 - Resistor select for 8"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl8(&mut self) -> GPIO_PUP_PDN_CNTRL8_W<16> { + pub fn gpio_pup_pdn_cntrl8( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL8_W { GPIO_PUP_PDN_CNTRL8_W::new(self) } #[doc = "Bits 18:19 - Resistor select for 9"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl9(&mut self) -> GPIO_PUP_PDN_CNTRL9_W<18> { + pub fn gpio_pup_pdn_cntrl9( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL9_W { GPIO_PUP_PDN_CNTRL9_W::new(self) } #[doc = "Bits 20:21 - Resistor select for 10"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl10(&mut self) -> GPIO_PUP_PDN_CNTRL10_W<20> { + pub fn gpio_pup_pdn_cntrl10( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL10_W { GPIO_PUP_PDN_CNTRL10_W::new(self) } #[doc = "Bits 22:23 - Resistor select for 11"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl11(&mut self) -> GPIO_PUP_PDN_CNTRL11_W<22> { + pub fn gpio_pup_pdn_cntrl11( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL11_W { GPIO_PUP_PDN_CNTRL11_W::new(self) } #[doc = "Bits 24:25 - Resistor select for 12"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl12(&mut self) -> GPIO_PUP_PDN_CNTRL12_W<24> { + pub fn gpio_pup_pdn_cntrl12( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL12_W { GPIO_PUP_PDN_CNTRL12_W::new(self) } #[doc = "Bits 26:27 - Resistor select for 13"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl13(&mut self) -> GPIO_PUP_PDN_CNTRL13_W<26> { + pub fn gpio_pup_pdn_cntrl13( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL13_W { GPIO_PUP_PDN_CNTRL13_W::new(self) } #[doc = "Bits 28:29 - Resistor select for 14"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl14(&mut self) -> GPIO_PUP_PDN_CNTRL14_W<28> { + pub fn gpio_pup_pdn_cntrl14( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL14_W { GPIO_PUP_PDN_CNTRL14_W::new(self) } #[doc = "Bits 30:31 - Resistor select for 15"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl15(&mut self) -> GPIO_PUP_PDN_CNTRL15_W<30> { + pub fn gpio_pup_pdn_cntrl15( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL15_W { GPIO_PUP_PDN_CNTRL15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pull-up / Pull-down Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg0](index.html) module"] +#[doc = "GPIO Pull-up / Pull-down Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_PUP_PDN_CNTRL_REG0_SPEC; impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg0::R](R) reader structure"] -impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_pup_pdn_cntrl_reg0::R`](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pup_pdn_cntrl_reg0::W`](W) writer structure"] impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs index 49faec3..877b1ae 100644 --- a/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs +++ b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg1.rs @@ -1,121 +1,73 @@ #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Resistor select for 16"] pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; #[doc = "Field `GPIO_PUP_PDN_CNTRL16` reader - Resistor select for 16"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL16_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL16` writer - Resistor select for 16"] -pub type GPIO_PUP_PDN_CNTRL16_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL17` reader - Resistor select for 17"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL17_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL17` writer - Resistor select for 17"] -pub type GPIO_PUP_PDN_CNTRL17_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL18` reader - Resistor select for 18"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL18_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL18` writer - Resistor select for 18"] -pub type GPIO_PUP_PDN_CNTRL18_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL19` reader - Resistor select for 19"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL19_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL19` writer - Resistor select for 19"] -pub type GPIO_PUP_PDN_CNTRL19_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL20` reader - Resistor select for 20"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL20_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL20` writer - Resistor select for 20"] -pub type GPIO_PUP_PDN_CNTRL20_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL21` reader - Resistor select for 21"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL21_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL21` writer - Resistor select for 21"] -pub type GPIO_PUP_PDN_CNTRL21_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL22` reader - Resistor select for 22"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL22_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL22` writer - Resistor select for 22"] -pub type GPIO_PUP_PDN_CNTRL22_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL23` reader - Resistor select for 23"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL23_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL23` writer - Resistor select for 23"] -pub type GPIO_PUP_PDN_CNTRL23_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL24` reader - Resistor select for 24"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL24_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL24` writer - Resistor select for 24"] -pub type GPIO_PUP_PDN_CNTRL24_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL25` reader - Resistor select for 25"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL25_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL25` writer - Resistor select for 25"] -pub type GPIO_PUP_PDN_CNTRL25_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL26` reader - Resistor select for 26"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL26_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL26` writer - Resistor select for 26"] -pub type GPIO_PUP_PDN_CNTRL26_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL27` reader - Resistor select for 27"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL27_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL27` writer - Resistor select for 27"] -pub type GPIO_PUP_PDN_CNTRL27_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL28` reader - Resistor select for 28"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL28_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL28` writer - Resistor select for 28"] -pub type GPIO_PUP_PDN_CNTRL28_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL29` reader - Resistor select for 29"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL29_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL29` writer - Resistor select for 29"] -pub type GPIO_PUP_PDN_CNTRL29_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL30` reader - Resistor select for 30"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL30_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL30` writer - Resistor select for 30"] -pub type GPIO_PUP_PDN_CNTRL30_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL31` reader - Resistor select for 31"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL31_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL16` writer - Resistor select for 16"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL16_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL17` writer - Resistor select for 17"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL17_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL18` writer - Resistor select for 18"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL18_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL19` writer - Resistor select for 19"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL19_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL20` writer - Resistor select for 20"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL20_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL21` writer - Resistor select for 21"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL21_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL22` writer - Resistor select for 22"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL22_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL23` writer - Resistor select for 23"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL23_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL24` writer - Resistor select for 24"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL24_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL25` writer - Resistor select for 25"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL25_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL26` writer - Resistor select for 26"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL26_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL27` writer - Resistor select for 27"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL27_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL28` writer - Resistor select for 28"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL28_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL29` writer - Resistor select for 29"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL29_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL30` writer - Resistor select for 30"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL30_W; #[doc = "Field `GPIO_PUP_PDN_CNTRL31` writer - Resistor select for 31"] -pub type GPIO_PUP_PDN_CNTRL31_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG1_SPEC, u8, BP_PULL_A, 2, O>; +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL31_W; impl R { #[doc = "Bits 0:1 - Resistor select for 16"] #[inline(always)] @@ -198,122 +150,230 @@ impl R { GPIO_PUP_PDN_CNTRL31_R::new(((self.bits >> 30) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PUP_PDN_CNTRL_REG1") + .field( + "gpio_pup_pdn_cntrl16", + &format_args!("{}", self.gpio_pup_pdn_cntrl16().bits()), + ) + .field( + "gpio_pup_pdn_cntrl17", + &format_args!("{}", self.gpio_pup_pdn_cntrl17().bits()), + ) + .field( + "gpio_pup_pdn_cntrl18", + &format_args!("{}", self.gpio_pup_pdn_cntrl18().bits()), + ) + .field( + "gpio_pup_pdn_cntrl19", + &format_args!("{}", self.gpio_pup_pdn_cntrl19().bits()), + ) + .field( + "gpio_pup_pdn_cntrl20", + &format_args!("{}", self.gpio_pup_pdn_cntrl20().bits()), + ) + .field( + "gpio_pup_pdn_cntrl21", + &format_args!("{}", self.gpio_pup_pdn_cntrl21().bits()), + ) + .field( + "gpio_pup_pdn_cntrl22", + &format_args!("{}", self.gpio_pup_pdn_cntrl22().bits()), + ) + .field( + "gpio_pup_pdn_cntrl23", + &format_args!("{}", self.gpio_pup_pdn_cntrl23().bits()), + ) + .field( + "gpio_pup_pdn_cntrl24", + &format_args!("{}", self.gpio_pup_pdn_cntrl24().bits()), + ) + .field( + "gpio_pup_pdn_cntrl25", + &format_args!("{}", self.gpio_pup_pdn_cntrl25().bits()), + ) + .field( + "gpio_pup_pdn_cntrl26", + &format_args!("{}", self.gpio_pup_pdn_cntrl26().bits()), + ) + .field( + "gpio_pup_pdn_cntrl27", + &format_args!("{}", self.gpio_pup_pdn_cntrl27().bits()), + ) + .field( + "gpio_pup_pdn_cntrl28", + &format_args!("{}", self.gpio_pup_pdn_cntrl28().bits()), + ) + .field( + "gpio_pup_pdn_cntrl29", + &format_args!("{}", self.gpio_pup_pdn_cntrl29().bits()), + ) + .field( + "gpio_pup_pdn_cntrl30", + &format_args!("{}", self.gpio_pup_pdn_cntrl30().bits()), + ) + .field( + "gpio_pup_pdn_cntrl31", + &format_args!("{}", self.gpio_pup_pdn_cntrl31().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Resistor select for 16"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl16(&mut self) -> GPIO_PUP_PDN_CNTRL16_W<0> { + pub fn gpio_pup_pdn_cntrl16( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL16_W { GPIO_PUP_PDN_CNTRL16_W::new(self) } #[doc = "Bits 2:3 - Resistor select for 17"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl17(&mut self) -> GPIO_PUP_PDN_CNTRL17_W<2> { + pub fn gpio_pup_pdn_cntrl17( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL17_W { GPIO_PUP_PDN_CNTRL17_W::new(self) } #[doc = "Bits 4:5 - Resistor select for 18"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl18(&mut self) -> GPIO_PUP_PDN_CNTRL18_W<4> { + pub fn gpio_pup_pdn_cntrl18( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL18_W { GPIO_PUP_PDN_CNTRL18_W::new(self) } #[doc = "Bits 6:7 - Resistor select for 19"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl19(&mut self) -> GPIO_PUP_PDN_CNTRL19_W<6> { + pub fn gpio_pup_pdn_cntrl19( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL19_W { GPIO_PUP_PDN_CNTRL19_W::new(self) } #[doc = "Bits 8:9 - Resistor select for 20"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl20(&mut self) -> GPIO_PUP_PDN_CNTRL20_W<8> { + pub fn gpio_pup_pdn_cntrl20( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL20_W { GPIO_PUP_PDN_CNTRL20_W::new(self) } #[doc = "Bits 10:11 - Resistor select for 21"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl21(&mut self) -> GPIO_PUP_PDN_CNTRL21_W<10> { + pub fn gpio_pup_pdn_cntrl21( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL21_W { GPIO_PUP_PDN_CNTRL21_W::new(self) } #[doc = "Bits 12:13 - Resistor select for 22"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl22(&mut self) -> GPIO_PUP_PDN_CNTRL22_W<12> { + pub fn gpio_pup_pdn_cntrl22( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL22_W { GPIO_PUP_PDN_CNTRL22_W::new(self) } #[doc = "Bits 14:15 - Resistor select for 23"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl23(&mut self) -> GPIO_PUP_PDN_CNTRL23_W<14> { + pub fn gpio_pup_pdn_cntrl23( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL23_W { GPIO_PUP_PDN_CNTRL23_W::new(self) } #[doc = "Bits 16:17 - Resistor select for 24"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl24(&mut self) -> GPIO_PUP_PDN_CNTRL24_W<16> { + pub fn gpio_pup_pdn_cntrl24( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL24_W { GPIO_PUP_PDN_CNTRL24_W::new(self) } #[doc = "Bits 18:19 - Resistor select for 25"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl25(&mut self) -> GPIO_PUP_PDN_CNTRL25_W<18> { + pub fn gpio_pup_pdn_cntrl25( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL25_W { GPIO_PUP_PDN_CNTRL25_W::new(self) } #[doc = "Bits 20:21 - Resistor select for 26"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl26(&mut self) -> GPIO_PUP_PDN_CNTRL26_W<20> { + pub fn gpio_pup_pdn_cntrl26( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL26_W { GPIO_PUP_PDN_CNTRL26_W::new(self) } #[doc = "Bits 22:23 - Resistor select for 27"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl27(&mut self) -> GPIO_PUP_PDN_CNTRL27_W<22> { + pub fn gpio_pup_pdn_cntrl27( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL27_W { GPIO_PUP_PDN_CNTRL27_W::new(self) } #[doc = "Bits 24:25 - Resistor select for 28"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl28(&mut self) -> GPIO_PUP_PDN_CNTRL28_W<24> { + pub fn gpio_pup_pdn_cntrl28( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL28_W { GPIO_PUP_PDN_CNTRL28_W::new(self) } #[doc = "Bits 26:27 - Resistor select for 29"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl29(&mut self) -> GPIO_PUP_PDN_CNTRL29_W<26> { + pub fn gpio_pup_pdn_cntrl29( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL29_W { GPIO_PUP_PDN_CNTRL29_W::new(self) } #[doc = "Bits 28:29 - Resistor select for 30"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl30(&mut self) -> GPIO_PUP_PDN_CNTRL30_W<28> { + pub fn gpio_pup_pdn_cntrl30( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL30_W { GPIO_PUP_PDN_CNTRL30_W::new(self) } #[doc = "Bits 30:31 - Resistor select for 31"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl31(&mut self) -> GPIO_PUP_PDN_CNTRL31_W<30> { + pub fn gpio_pup_pdn_cntrl31( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL31_W { GPIO_PUP_PDN_CNTRL31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pull-up / Pull-down Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg1](index.html) module"] +#[doc = "GPIO Pull-up / Pull-down Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_PUP_PDN_CNTRL_REG1_SPEC; impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg1::R](R) reader structure"] -impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_pup_pdn_cntrl_reg1::R`](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pup_pdn_cntrl_reg1::W`](W) writer structure"] impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs index 67047c9..dfd838d 100644 --- a/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs +++ b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg2.rs @@ -1,121 +1,73 @@ #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Resistor select for 32"] pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; #[doc = "Field `GPIO_PUP_PDN_CNTRL32` reader - Resistor select for 32"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL32_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL32` writer - Resistor select for 32"] -pub type GPIO_PUP_PDN_CNTRL32_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL33` reader - Resistor select for 33"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL33_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL33` writer - Resistor select for 33"] -pub type GPIO_PUP_PDN_CNTRL33_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL34` reader - Resistor select for 34"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL34_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL34` writer - Resistor select for 34"] -pub type GPIO_PUP_PDN_CNTRL34_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL35` reader - Resistor select for 35"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL35_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL35` writer - Resistor select for 35"] -pub type GPIO_PUP_PDN_CNTRL35_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL36` reader - Resistor select for 36"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL36_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL36` writer - Resistor select for 36"] -pub type GPIO_PUP_PDN_CNTRL36_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL37` reader - Resistor select for 37"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL37_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL37` writer - Resistor select for 37"] -pub type GPIO_PUP_PDN_CNTRL37_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL38` reader - Resistor select for 38"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL38_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL38` writer - Resistor select for 38"] -pub type GPIO_PUP_PDN_CNTRL38_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL39` reader - Resistor select for 39"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL39_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL39` writer - Resistor select for 39"] -pub type GPIO_PUP_PDN_CNTRL39_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL40` reader - Resistor select for 40"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL40_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL40` writer - Resistor select for 40"] -pub type GPIO_PUP_PDN_CNTRL40_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL41` reader - Resistor select for 41"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL41_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL41` writer - Resistor select for 41"] -pub type GPIO_PUP_PDN_CNTRL41_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL42` reader - Resistor select for 42"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL42_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL42` writer - Resistor select for 42"] -pub type GPIO_PUP_PDN_CNTRL42_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL43` reader - Resistor select for 43"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL43_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL43` writer - Resistor select for 43"] -pub type GPIO_PUP_PDN_CNTRL43_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL44` reader - Resistor select for 44"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL44_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL44` writer - Resistor select for 44"] -pub type GPIO_PUP_PDN_CNTRL44_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL45` reader - Resistor select for 45"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL45_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL45` writer - Resistor select for 45"] -pub type GPIO_PUP_PDN_CNTRL45_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL46` reader - Resistor select for 46"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL46_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL46` writer - Resistor select for 46"] -pub type GPIO_PUP_PDN_CNTRL46_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL47` reader - Resistor select for 47"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL47_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL32` writer - Resistor select for 32"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL32_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL33` writer - Resistor select for 33"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL33_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL34` writer - Resistor select for 34"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL34_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL35` writer - Resistor select for 35"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL35_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL36` writer - Resistor select for 36"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL36_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL37` writer - Resistor select for 37"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL37_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL38` writer - Resistor select for 38"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL38_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL39` writer - Resistor select for 39"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL39_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL40` writer - Resistor select for 40"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL40_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL41` writer - Resistor select for 41"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL41_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL42` writer - Resistor select for 42"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL42_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL43` writer - Resistor select for 43"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL43_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL44` writer - Resistor select for 44"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL44_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL45` writer - Resistor select for 45"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL45_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL46` writer - Resistor select for 46"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL46_W; #[doc = "Field `GPIO_PUP_PDN_CNTRL47` writer - Resistor select for 47"] -pub type GPIO_PUP_PDN_CNTRL47_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG2_SPEC, u8, BP_PULL_A, 2, O>; +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL47_W; impl R { #[doc = "Bits 0:1 - Resistor select for 32"] #[inline(always)] @@ -198,122 +150,230 @@ impl R { GPIO_PUP_PDN_CNTRL47_R::new(((self.bits >> 30) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PUP_PDN_CNTRL_REG2") + .field( + "gpio_pup_pdn_cntrl32", + &format_args!("{}", self.gpio_pup_pdn_cntrl32().bits()), + ) + .field( + "gpio_pup_pdn_cntrl33", + &format_args!("{}", self.gpio_pup_pdn_cntrl33().bits()), + ) + .field( + "gpio_pup_pdn_cntrl34", + &format_args!("{}", self.gpio_pup_pdn_cntrl34().bits()), + ) + .field( + "gpio_pup_pdn_cntrl35", + &format_args!("{}", self.gpio_pup_pdn_cntrl35().bits()), + ) + .field( + "gpio_pup_pdn_cntrl36", + &format_args!("{}", self.gpio_pup_pdn_cntrl36().bits()), + ) + .field( + "gpio_pup_pdn_cntrl37", + &format_args!("{}", self.gpio_pup_pdn_cntrl37().bits()), + ) + .field( + "gpio_pup_pdn_cntrl38", + &format_args!("{}", self.gpio_pup_pdn_cntrl38().bits()), + ) + .field( + "gpio_pup_pdn_cntrl39", + &format_args!("{}", self.gpio_pup_pdn_cntrl39().bits()), + ) + .field( + "gpio_pup_pdn_cntrl40", + &format_args!("{}", self.gpio_pup_pdn_cntrl40().bits()), + ) + .field( + "gpio_pup_pdn_cntrl41", + &format_args!("{}", self.gpio_pup_pdn_cntrl41().bits()), + ) + .field( + "gpio_pup_pdn_cntrl42", + &format_args!("{}", self.gpio_pup_pdn_cntrl42().bits()), + ) + .field( + "gpio_pup_pdn_cntrl43", + &format_args!("{}", self.gpio_pup_pdn_cntrl43().bits()), + ) + .field( + "gpio_pup_pdn_cntrl44", + &format_args!("{}", self.gpio_pup_pdn_cntrl44().bits()), + ) + .field( + "gpio_pup_pdn_cntrl45", + &format_args!("{}", self.gpio_pup_pdn_cntrl45().bits()), + ) + .field( + "gpio_pup_pdn_cntrl46", + &format_args!("{}", self.gpio_pup_pdn_cntrl46().bits()), + ) + .field( + "gpio_pup_pdn_cntrl47", + &format_args!("{}", self.gpio_pup_pdn_cntrl47().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Resistor select for 32"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl32(&mut self) -> GPIO_PUP_PDN_CNTRL32_W<0> { + pub fn gpio_pup_pdn_cntrl32( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL32_W { GPIO_PUP_PDN_CNTRL32_W::new(self) } #[doc = "Bits 2:3 - Resistor select for 33"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl33(&mut self) -> GPIO_PUP_PDN_CNTRL33_W<2> { + pub fn gpio_pup_pdn_cntrl33( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL33_W { GPIO_PUP_PDN_CNTRL33_W::new(self) } #[doc = "Bits 4:5 - Resistor select for 34"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl34(&mut self) -> GPIO_PUP_PDN_CNTRL34_W<4> { + pub fn gpio_pup_pdn_cntrl34( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL34_W { GPIO_PUP_PDN_CNTRL34_W::new(self) } #[doc = "Bits 6:7 - Resistor select for 35"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl35(&mut self) -> GPIO_PUP_PDN_CNTRL35_W<6> { + pub fn gpio_pup_pdn_cntrl35( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL35_W { GPIO_PUP_PDN_CNTRL35_W::new(self) } #[doc = "Bits 8:9 - Resistor select for 36"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl36(&mut self) -> GPIO_PUP_PDN_CNTRL36_W<8> { + pub fn gpio_pup_pdn_cntrl36( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL36_W { GPIO_PUP_PDN_CNTRL36_W::new(self) } #[doc = "Bits 10:11 - Resistor select for 37"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl37(&mut self) -> GPIO_PUP_PDN_CNTRL37_W<10> { + pub fn gpio_pup_pdn_cntrl37( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL37_W { GPIO_PUP_PDN_CNTRL37_W::new(self) } #[doc = "Bits 12:13 - Resistor select for 38"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl38(&mut self) -> GPIO_PUP_PDN_CNTRL38_W<12> { + pub fn gpio_pup_pdn_cntrl38( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL38_W { GPIO_PUP_PDN_CNTRL38_W::new(self) } #[doc = "Bits 14:15 - Resistor select for 39"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl39(&mut self) -> GPIO_PUP_PDN_CNTRL39_W<14> { + pub fn gpio_pup_pdn_cntrl39( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL39_W { GPIO_PUP_PDN_CNTRL39_W::new(self) } #[doc = "Bits 16:17 - Resistor select for 40"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl40(&mut self) -> GPIO_PUP_PDN_CNTRL40_W<16> { + pub fn gpio_pup_pdn_cntrl40( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL40_W { GPIO_PUP_PDN_CNTRL40_W::new(self) } #[doc = "Bits 18:19 - Resistor select for 41"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl41(&mut self) -> GPIO_PUP_PDN_CNTRL41_W<18> { + pub fn gpio_pup_pdn_cntrl41( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL41_W { GPIO_PUP_PDN_CNTRL41_W::new(self) } #[doc = "Bits 20:21 - Resistor select for 42"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl42(&mut self) -> GPIO_PUP_PDN_CNTRL42_W<20> { + pub fn gpio_pup_pdn_cntrl42( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL42_W { GPIO_PUP_PDN_CNTRL42_W::new(self) } #[doc = "Bits 22:23 - Resistor select for 43"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl43(&mut self) -> GPIO_PUP_PDN_CNTRL43_W<22> { + pub fn gpio_pup_pdn_cntrl43( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL43_W { GPIO_PUP_PDN_CNTRL43_W::new(self) } #[doc = "Bits 24:25 - Resistor select for 44"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl44(&mut self) -> GPIO_PUP_PDN_CNTRL44_W<24> { + pub fn gpio_pup_pdn_cntrl44( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL44_W { GPIO_PUP_PDN_CNTRL44_W::new(self) } #[doc = "Bits 26:27 - Resistor select for 45"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl45(&mut self) -> GPIO_PUP_PDN_CNTRL45_W<26> { + pub fn gpio_pup_pdn_cntrl45( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL45_W { GPIO_PUP_PDN_CNTRL45_W::new(self) } #[doc = "Bits 28:29 - Resistor select for 46"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl46(&mut self) -> GPIO_PUP_PDN_CNTRL46_W<28> { + pub fn gpio_pup_pdn_cntrl46( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL46_W { GPIO_PUP_PDN_CNTRL46_W::new(self) } #[doc = "Bits 30:31 - Resistor select for 47"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl47(&mut self) -> GPIO_PUP_PDN_CNTRL47_W<30> { + pub fn gpio_pup_pdn_cntrl47( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL47_W { GPIO_PUP_PDN_CNTRL47_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pull-up / Pull-down Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg2](index.html) module"] +#[doc = "GPIO Pull-up / Pull-down Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg2::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_PUP_PDN_CNTRL_REG2_SPEC; impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg2::R](R) reader structure"] -impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg2::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_pup_pdn_cntrl_reg2::R`](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pup_pdn_cntrl_reg2::W`](W) writer structure"] impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs index 61b9329..52b564a 100644 --- a/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs +++ b/crates/bcm2837-lpa/src/gpio/gpio_pup_pdn_cntrl_reg3.rs @@ -1,71 +1,33 @@ #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPIO_PUP_PDN_CNTRL_REG3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Resistor select for 48"] pub use super::gpio_pup_pdn_cntrl_reg0::BP_PULL_A; #[doc = "Field `GPIO_PUP_PDN_CNTRL48` reader - Resistor select for 48"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL48_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL48` writer - Resistor select for 48"] -pub type GPIO_PUP_PDN_CNTRL48_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL49` reader - Resistor select for 49"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL49_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL49` writer - Resistor select for 49"] -pub type GPIO_PUP_PDN_CNTRL49_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL50` reader - Resistor select for 50"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL50_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL50` writer - Resistor select for 50"] -pub type GPIO_PUP_PDN_CNTRL50_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL51` reader - Resistor select for 51"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL51_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL51` writer - Resistor select for 51"] -pub type GPIO_PUP_PDN_CNTRL51_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL52` reader - Resistor select for 52"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL52_R; -#[doc = "Field `GPIO_PUP_PDN_CNTRL52` writer - Resistor select for 52"] -pub type GPIO_PUP_PDN_CNTRL52_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; #[doc = "Field `GPIO_PUP_PDN_CNTRL53` reader - Resistor select for 53"] pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_R as GPIO_PUP_PDN_CNTRL53_R; +#[doc = "Field `GPIO_PUP_PDN_CNTRL48` writer - Resistor select for 48"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL48_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL49` writer - Resistor select for 49"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL49_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL50` writer - Resistor select for 50"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL50_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL51` writer - Resistor select for 51"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL51_W; +#[doc = "Field `GPIO_PUP_PDN_CNTRL52` writer - Resistor select for 52"] +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL52_W; #[doc = "Field `GPIO_PUP_PDN_CNTRL53` writer - Resistor select for 53"] -pub type GPIO_PUP_PDN_CNTRL53_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GPIO_PUP_PDN_CNTRL_REG3_SPEC, u8, BP_PULL_A, 2, O>; +pub use super::gpio_pup_pdn_cntrl_reg0::GPIO_PUP_PDN_CNTRL0_W as GPIO_PUP_PDN_CNTRL53_W; impl R { #[doc = "Bits 0:1 - Resistor select for 48"] #[inline(always)] @@ -98,62 +60,110 @@ impl R { GPIO_PUP_PDN_CNTRL53_R::new(((self.bits >> 10) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PUP_PDN_CNTRL_REG3") + .field( + "gpio_pup_pdn_cntrl48", + &format_args!("{}", self.gpio_pup_pdn_cntrl48().bits()), + ) + .field( + "gpio_pup_pdn_cntrl49", + &format_args!("{}", self.gpio_pup_pdn_cntrl49().bits()), + ) + .field( + "gpio_pup_pdn_cntrl50", + &format_args!("{}", self.gpio_pup_pdn_cntrl50().bits()), + ) + .field( + "gpio_pup_pdn_cntrl51", + &format_args!("{}", self.gpio_pup_pdn_cntrl51().bits()), + ) + .field( + "gpio_pup_pdn_cntrl52", + &format_args!("{}", self.gpio_pup_pdn_cntrl52().bits()), + ) + .field( + "gpio_pup_pdn_cntrl53", + &format_args!("{}", self.gpio_pup_pdn_cntrl53().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Resistor select for 48"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl48(&mut self) -> GPIO_PUP_PDN_CNTRL48_W<0> { + pub fn gpio_pup_pdn_cntrl48( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL48_W { GPIO_PUP_PDN_CNTRL48_W::new(self) } #[doc = "Bits 2:3 - Resistor select for 49"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl49(&mut self) -> GPIO_PUP_PDN_CNTRL49_W<2> { + pub fn gpio_pup_pdn_cntrl49( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL49_W { GPIO_PUP_PDN_CNTRL49_W::new(self) } #[doc = "Bits 4:5 - Resistor select for 50"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl50(&mut self) -> GPIO_PUP_PDN_CNTRL50_W<4> { + pub fn gpio_pup_pdn_cntrl50( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL50_W { GPIO_PUP_PDN_CNTRL50_W::new(self) } #[doc = "Bits 6:7 - Resistor select for 51"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl51(&mut self) -> GPIO_PUP_PDN_CNTRL51_W<6> { + pub fn gpio_pup_pdn_cntrl51( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL51_W { GPIO_PUP_PDN_CNTRL51_W::new(self) } #[doc = "Bits 8:9 - Resistor select for 52"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl52(&mut self) -> GPIO_PUP_PDN_CNTRL52_W<8> { + pub fn gpio_pup_pdn_cntrl52( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL52_W { GPIO_PUP_PDN_CNTRL52_W::new(self) } #[doc = "Bits 10:11 - Resistor select for 53"] #[inline(always)] #[must_use] - pub fn gpio_pup_pdn_cntrl53(&mut self) -> GPIO_PUP_PDN_CNTRL53_W<10> { + pub fn gpio_pup_pdn_cntrl53( + &mut self, + ) -> GPIO_PUP_PDN_CNTRL53_W { GPIO_PUP_PDN_CNTRL53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pull-up / Pull-down Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_pup_pdn_cntrl_reg3](index.html) module"] +#[doc = "GPIO Pull-up / Pull-down Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pup_pdn_cntrl_reg3::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pup_pdn_cntrl_reg3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_PUP_PDN_CNTRL_REG3_SPEC; impl crate::RegisterSpec for GPIO_PUP_PDN_CNTRL_REG3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpio_pup_pdn_cntrl_reg3::R](R) reader structure"] -impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpio_pup_pdn_cntrl_reg3::W](W) writer structure"] +#[doc = "`read()` method returns [`gpio_pup_pdn_cntrl_reg3::R`](R) reader structure"] +impl crate::Readable for GPIO_PUP_PDN_CNTRL_REG3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pup_pdn_cntrl_reg3::W`](W) writer structure"] impl crate::Writable for GPIO_PUP_PDN_CNTRL_REG3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gplen0.rs b/crates/bcm2837-lpa/src/gpio/gplen0.rs index 54f51bd..bfac268 100644 --- a/crates/bcm2837-lpa/src/gpio/gplen0.rs +++ b/crates/bcm2837-lpa/src/gpio/gplen0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPLEN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPLEN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LEN0` reader - Low detect enabled 0"] -pub type LEN0_R = crate::BitReader; +pub type LEN0_R = crate::BitReader; #[doc = "Field `LEN0` writer - Low detect enabled 0"] -pub type LEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN1` reader - Low detect enabled 1"] -pub type LEN1_R = crate::BitReader; +pub type LEN1_R = crate::BitReader; #[doc = "Field `LEN1` writer - Low detect enabled 1"] -pub type LEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN2` reader - Low detect enabled 2"] -pub type LEN2_R = crate::BitReader; +pub type LEN2_R = crate::BitReader; #[doc = "Field `LEN2` writer - Low detect enabled 2"] -pub type LEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN3` reader - Low detect enabled 3"] -pub type LEN3_R = crate::BitReader; +pub type LEN3_R = crate::BitReader; #[doc = "Field `LEN3` writer - Low detect enabled 3"] -pub type LEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN4` reader - Low detect enabled 4"] -pub type LEN4_R = crate::BitReader; +pub type LEN4_R = crate::BitReader; #[doc = "Field `LEN4` writer - Low detect enabled 4"] -pub type LEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN5` reader - Low detect enabled 5"] -pub type LEN5_R = crate::BitReader; +pub type LEN5_R = crate::BitReader; #[doc = "Field `LEN5` writer - Low detect enabled 5"] -pub type LEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN6` reader - Low detect enabled 6"] -pub type LEN6_R = crate::BitReader; +pub type LEN6_R = crate::BitReader; #[doc = "Field `LEN6` writer - Low detect enabled 6"] -pub type LEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN7` reader - Low detect enabled 7"] -pub type LEN7_R = crate::BitReader; +pub type LEN7_R = crate::BitReader; #[doc = "Field `LEN7` writer - Low detect enabled 7"] -pub type LEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN8` reader - Low detect enabled 8"] -pub type LEN8_R = crate::BitReader; +pub type LEN8_R = crate::BitReader; #[doc = "Field `LEN8` writer - Low detect enabled 8"] -pub type LEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN9` reader - Low detect enabled 9"] -pub type LEN9_R = crate::BitReader; +pub type LEN9_R = crate::BitReader; #[doc = "Field `LEN9` writer - Low detect enabled 9"] -pub type LEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN10` reader - Low detect enabled 10"] -pub type LEN10_R = crate::BitReader; +pub type LEN10_R = crate::BitReader; #[doc = "Field `LEN10` writer - Low detect enabled 10"] -pub type LEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN11` reader - Low detect enabled 11"] -pub type LEN11_R = crate::BitReader; +pub type LEN11_R = crate::BitReader; #[doc = "Field `LEN11` writer - Low detect enabled 11"] -pub type LEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN12` reader - Low detect enabled 12"] -pub type LEN12_R = crate::BitReader; +pub type LEN12_R = crate::BitReader; #[doc = "Field `LEN12` writer - Low detect enabled 12"] -pub type LEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN13` reader - Low detect enabled 13"] -pub type LEN13_R = crate::BitReader; +pub type LEN13_R = crate::BitReader; #[doc = "Field `LEN13` writer - Low detect enabled 13"] -pub type LEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN14` reader - Low detect enabled 14"] -pub type LEN14_R = crate::BitReader; +pub type LEN14_R = crate::BitReader; #[doc = "Field `LEN14` writer - Low detect enabled 14"] -pub type LEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN15` reader - Low detect enabled 15"] -pub type LEN15_R = crate::BitReader; +pub type LEN15_R = crate::BitReader; #[doc = "Field `LEN15` writer - Low detect enabled 15"] -pub type LEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN16` reader - Low detect enabled 16"] -pub type LEN16_R = crate::BitReader; +pub type LEN16_R = crate::BitReader; #[doc = "Field `LEN16` writer - Low detect enabled 16"] -pub type LEN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN17` reader - Low detect enabled 17"] -pub type LEN17_R = crate::BitReader; +pub type LEN17_R = crate::BitReader; #[doc = "Field `LEN17` writer - Low detect enabled 17"] -pub type LEN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN18` reader - Low detect enabled 18"] -pub type LEN18_R = crate::BitReader; +pub type LEN18_R = crate::BitReader; #[doc = "Field `LEN18` writer - Low detect enabled 18"] -pub type LEN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN19` reader - Low detect enabled 19"] -pub type LEN19_R = crate::BitReader; +pub type LEN19_R = crate::BitReader; #[doc = "Field `LEN19` writer - Low detect enabled 19"] -pub type LEN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN20` reader - Low detect enabled 20"] -pub type LEN20_R = crate::BitReader; +pub type LEN20_R = crate::BitReader; #[doc = "Field `LEN20` writer - Low detect enabled 20"] -pub type LEN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN21` reader - Low detect enabled 21"] -pub type LEN21_R = crate::BitReader; +pub type LEN21_R = crate::BitReader; #[doc = "Field `LEN21` writer - Low detect enabled 21"] -pub type LEN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN22` reader - Low detect enabled 22"] -pub type LEN22_R = crate::BitReader; +pub type LEN22_R = crate::BitReader; #[doc = "Field `LEN22` writer - Low detect enabled 22"] -pub type LEN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN23` reader - Low detect enabled 23"] -pub type LEN23_R = crate::BitReader; +pub type LEN23_R = crate::BitReader; #[doc = "Field `LEN23` writer - Low detect enabled 23"] -pub type LEN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN24` reader - Low detect enabled 24"] -pub type LEN24_R = crate::BitReader; +pub type LEN24_R = crate::BitReader; #[doc = "Field `LEN24` writer - Low detect enabled 24"] -pub type LEN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN25` reader - Low detect enabled 25"] -pub type LEN25_R = crate::BitReader; +pub type LEN25_R = crate::BitReader; #[doc = "Field `LEN25` writer - Low detect enabled 25"] -pub type LEN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN26` reader - Low detect enabled 26"] -pub type LEN26_R = crate::BitReader; +pub type LEN26_R = crate::BitReader; #[doc = "Field `LEN26` writer - Low detect enabled 26"] -pub type LEN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN27` reader - Low detect enabled 27"] -pub type LEN27_R = crate::BitReader; +pub type LEN27_R = crate::BitReader; #[doc = "Field `LEN27` writer - Low detect enabled 27"] -pub type LEN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN28` reader - Low detect enabled 28"] -pub type LEN28_R = crate::BitReader; +pub type LEN28_R = crate::BitReader; #[doc = "Field `LEN28` writer - Low detect enabled 28"] -pub type LEN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN29` reader - Low detect enabled 29"] -pub type LEN29_R = crate::BitReader; +pub type LEN29_R = crate::BitReader; #[doc = "Field `LEN29` writer - Low detect enabled 29"] -pub type LEN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN30` reader - Low detect enabled 30"] -pub type LEN30_R = crate::BitReader; +pub type LEN30_R = crate::BitReader; #[doc = "Field `LEN30` writer - Low detect enabled 30"] -pub type LEN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN31` reader - Low detect enabled 31"] -pub type LEN31_R = crate::BitReader; +pub type LEN31_R = crate::BitReader; #[doc = "Field `LEN31` writer - Low detect enabled 31"] -pub type LEN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN0_SPEC, bool, O>; +pub type LEN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Low detect enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { LEN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPLEN0") + .field("len0", &format_args!("{}", self.len0().bit())) + .field("len1", &format_args!("{}", self.len1().bit())) + .field("len2", &format_args!("{}", self.len2().bit())) + .field("len3", &format_args!("{}", self.len3().bit())) + .field("len4", &format_args!("{}", self.len4().bit())) + .field("len5", &format_args!("{}", self.len5().bit())) + .field("len6", &format_args!("{}", self.len6().bit())) + .field("len7", &format_args!("{}", self.len7().bit())) + .field("len8", &format_args!("{}", self.len8().bit())) + .field("len9", &format_args!("{}", self.len9().bit())) + .field("len10", &format_args!("{}", self.len10().bit())) + .field("len11", &format_args!("{}", self.len11().bit())) + .field("len12", &format_args!("{}", self.len12().bit())) + .field("len13", &format_args!("{}", self.len13().bit())) + .field("len14", &format_args!("{}", self.len14().bit())) + .field("len15", &format_args!("{}", self.len15().bit())) + .field("len16", &format_args!("{}", self.len16().bit())) + .field("len17", &format_args!("{}", self.len17().bit())) + .field("len18", &format_args!("{}", self.len18().bit())) + .field("len19", &format_args!("{}", self.len19().bit())) + .field("len20", &format_args!("{}", self.len20().bit())) + .field("len21", &format_args!("{}", self.len21().bit())) + .field("len22", &format_args!("{}", self.len22().bit())) + .field("len23", &format_args!("{}", self.len23().bit())) + .field("len24", &format_args!("{}", self.len24().bit())) + .field("len25", &format_args!("{}", self.len25().bit())) + .field("len26", &format_args!("{}", self.len26().bit())) + .field("len27", &format_args!("{}", self.len27().bit())) + .field("len28", &format_args!("{}", self.len28().bit())) + .field("len29", &format_args!("{}", self.len29().bit())) + .field("len30", &format_args!("{}", self.len30().bit())) + .field("len31", &format_args!("{}", self.len31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Low detect enabled 0"] #[inline(always)] #[must_use] - pub fn len0(&mut self) -> LEN0_W<0> { + pub fn len0(&mut self) -> LEN0_W { LEN0_W::new(self) } #[doc = "Bit 1 - Low detect enabled 1"] #[inline(always)] #[must_use] - pub fn len1(&mut self) -> LEN1_W<1> { + pub fn len1(&mut self) -> LEN1_W { LEN1_W::new(self) } #[doc = "Bit 2 - Low detect enabled 2"] #[inline(always)] #[must_use] - pub fn len2(&mut self) -> LEN2_W<2> { + pub fn len2(&mut self) -> LEN2_W { LEN2_W::new(self) } #[doc = "Bit 3 - Low detect enabled 3"] #[inline(always)] #[must_use] - pub fn len3(&mut self) -> LEN3_W<3> { + pub fn len3(&mut self) -> LEN3_W { LEN3_W::new(self) } #[doc = "Bit 4 - Low detect enabled 4"] #[inline(always)] #[must_use] - pub fn len4(&mut self) -> LEN4_W<4> { + pub fn len4(&mut self) -> LEN4_W { LEN4_W::new(self) } #[doc = "Bit 5 - Low detect enabled 5"] #[inline(always)] #[must_use] - pub fn len5(&mut self) -> LEN5_W<5> { + pub fn len5(&mut self) -> LEN5_W { LEN5_W::new(self) } #[doc = "Bit 6 - Low detect enabled 6"] #[inline(always)] #[must_use] - pub fn len6(&mut self) -> LEN6_W<6> { + pub fn len6(&mut self) -> LEN6_W { LEN6_W::new(self) } #[doc = "Bit 7 - Low detect enabled 7"] #[inline(always)] #[must_use] - pub fn len7(&mut self) -> LEN7_W<7> { + pub fn len7(&mut self) -> LEN7_W { LEN7_W::new(self) } #[doc = "Bit 8 - Low detect enabled 8"] #[inline(always)] #[must_use] - pub fn len8(&mut self) -> LEN8_W<8> { + pub fn len8(&mut self) -> LEN8_W { LEN8_W::new(self) } #[doc = "Bit 9 - Low detect enabled 9"] #[inline(always)] #[must_use] - pub fn len9(&mut self) -> LEN9_W<9> { + pub fn len9(&mut self) -> LEN9_W { LEN9_W::new(self) } #[doc = "Bit 10 - Low detect enabled 10"] #[inline(always)] #[must_use] - pub fn len10(&mut self) -> LEN10_W<10> { + pub fn len10(&mut self) -> LEN10_W { LEN10_W::new(self) } #[doc = "Bit 11 - Low detect enabled 11"] #[inline(always)] #[must_use] - pub fn len11(&mut self) -> LEN11_W<11> { + pub fn len11(&mut self) -> LEN11_W { LEN11_W::new(self) } #[doc = "Bit 12 - Low detect enabled 12"] #[inline(always)] #[must_use] - pub fn len12(&mut self) -> LEN12_W<12> { + pub fn len12(&mut self) -> LEN12_W { LEN12_W::new(self) } #[doc = "Bit 13 - Low detect enabled 13"] #[inline(always)] #[must_use] - pub fn len13(&mut self) -> LEN13_W<13> { + pub fn len13(&mut self) -> LEN13_W { LEN13_W::new(self) } #[doc = "Bit 14 - Low detect enabled 14"] #[inline(always)] #[must_use] - pub fn len14(&mut self) -> LEN14_W<14> { + pub fn len14(&mut self) -> LEN14_W { LEN14_W::new(self) } #[doc = "Bit 15 - Low detect enabled 15"] #[inline(always)] #[must_use] - pub fn len15(&mut self) -> LEN15_W<15> { + pub fn len15(&mut self) -> LEN15_W { LEN15_W::new(self) } #[doc = "Bit 16 - Low detect enabled 16"] #[inline(always)] #[must_use] - pub fn len16(&mut self) -> LEN16_W<16> { + pub fn len16(&mut self) -> LEN16_W { LEN16_W::new(self) } #[doc = "Bit 17 - Low detect enabled 17"] #[inline(always)] #[must_use] - pub fn len17(&mut self) -> LEN17_W<17> { + pub fn len17(&mut self) -> LEN17_W { LEN17_W::new(self) } #[doc = "Bit 18 - Low detect enabled 18"] #[inline(always)] #[must_use] - pub fn len18(&mut self) -> LEN18_W<18> { + pub fn len18(&mut self) -> LEN18_W { LEN18_W::new(self) } #[doc = "Bit 19 - Low detect enabled 19"] #[inline(always)] #[must_use] - pub fn len19(&mut self) -> LEN19_W<19> { + pub fn len19(&mut self) -> LEN19_W { LEN19_W::new(self) } #[doc = "Bit 20 - Low detect enabled 20"] #[inline(always)] #[must_use] - pub fn len20(&mut self) -> LEN20_W<20> { + pub fn len20(&mut self) -> LEN20_W { LEN20_W::new(self) } #[doc = "Bit 21 - Low detect enabled 21"] #[inline(always)] #[must_use] - pub fn len21(&mut self) -> LEN21_W<21> { + pub fn len21(&mut self) -> LEN21_W { LEN21_W::new(self) } #[doc = "Bit 22 - Low detect enabled 22"] #[inline(always)] #[must_use] - pub fn len22(&mut self) -> LEN22_W<22> { + pub fn len22(&mut self) -> LEN22_W { LEN22_W::new(self) } #[doc = "Bit 23 - Low detect enabled 23"] #[inline(always)] #[must_use] - pub fn len23(&mut self) -> LEN23_W<23> { + pub fn len23(&mut self) -> LEN23_W { LEN23_W::new(self) } #[doc = "Bit 24 - Low detect enabled 24"] #[inline(always)] #[must_use] - pub fn len24(&mut self) -> LEN24_W<24> { + pub fn len24(&mut self) -> LEN24_W { LEN24_W::new(self) } #[doc = "Bit 25 - Low detect enabled 25"] #[inline(always)] #[must_use] - pub fn len25(&mut self) -> LEN25_W<25> { + pub fn len25(&mut self) -> LEN25_W { LEN25_W::new(self) } #[doc = "Bit 26 - Low detect enabled 26"] #[inline(always)] #[must_use] - pub fn len26(&mut self) -> LEN26_W<26> { + pub fn len26(&mut self) -> LEN26_W { LEN26_W::new(self) } #[doc = "Bit 27 - Low detect enabled 27"] #[inline(always)] #[must_use] - pub fn len27(&mut self) -> LEN27_W<27> { + pub fn len27(&mut self) -> LEN27_W { LEN27_W::new(self) } #[doc = "Bit 28 - Low detect enabled 28"] #[inline(always)] #[must_use] - pub fn len28(&mut self) -> LEN28_W<28> { + pub fn len28(&mut self) -> LEN28_W { LEN28_W::new(self) } #[doc = "Bit 29 - Low detect enabled 29"] #[inline(always)] #[must_use] - pub fn len29(&mut self) -> LEN29_W<29> { + pub fn len29(&mut self) -> LEN29_W { LEN29_W::new(self) } #[doc = "Bit 30 - Low detect enabled 30"] #[inline(always)] #[must_use] - pub fn len30(&mut self) -> LEN30_W<30> { + pub fn len30(&mut self) -> LEN30_W { LEN30_W::new(self) } #[doc = "Bit 31 - Low detect enabled 31"] #[inline(always)] #[must_use] - pub fn len31(&mut self) -> LEN31_W<31> { + pub fn len31(&mut self) -> LEN31_W { LEN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Low Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplen0](index.html) module"] +#[doc = "GPIO Pin Low Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplen0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gplen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPLEN0_SPEC; impl crate::RegisterSpec for GPLEN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gplen0::R](R) reader structure"] -impl crate::Readable for GPLEN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gplen0::W](W) writer structure"] +#[doc = "`read()` method returns [`gplen0::R`](R) reader structure"] +impl crate::Readable for GPLEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gplen0::W`](W) writer structure"] impl crate::Writable for GPLEN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gplen1.rs b/crates/bcm2837-lpa/src/gpio/gplen1.rs index 070e4d4..bcf3f46 100644 --- a/crates/bcm2837-lpa/src/gpio/gplen1.rs +++ b/crates/bcm2837-lpa/src/gpio/gplen1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPLEN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPLEN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LEN32` reader - Low detect enabled 32"] -pub type LEN32_R = crate::BitReader; +pub type LEN32_R = crate::BitReader; #[doc = "Field `LEN32` writer - Low detect enabled 32"] -pub type LEN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN33` reader - Low detect enabled 33"] -pub type LEN33_R = crate::BitReader; +pub type LEN33_R = crate::BitReader; #[doc = "Field `LEN33` writer - Low detect enabled 33"] -pub type LEN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN34` reader - Low detect enabled 34"] -pub type LEN34_R = crate::BitReader; +pub type LEN34_R = crate::BitReader; #[doc = "Field `LEN34` writer - Low detect enabled 34"] -pub type LEN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN35` reader - Low detect enabled 35"] -pub type LEN35_R = crate::BitReader; +pub type LEN35_R = crate::BitReader; #[doc = "Field `LEN35` writer - Low detect enabled 35"] -pub type LEN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN36` reader - Low detect enabled 36"] -pub type LEN36_R = crate::BitReader; +pub type LEN36_R = crate::BitReader; #[doc = "Field `LEN36` writer - Low detect enabled 36"] -pub type LEN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN37` reader - Low detect enabled 37"] -pub type LEN37_R = crate::BitReader; +pub type LEN37_R = crate::BitReader; #[doc = "Field `LEN37` writer - Low detect enabled 37"] -pub type LEN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN38` reader - Low detect enabled 38"] -pub type LEN38_R = crate::BitReader; +pub type LEN38_R = crate::BitReader; #[doc = "Field `LEN38` writer - Low detect enabled 38"] -pub type LEN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN39` reader - Low detect enabled 39"] -pub type LEN39_R = crate::BitReader; +pub type LEN39_R = crate::BitReader; #[doc = "Field `LEN39` writer - Low detect enabled 39"] -pub type LEN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN40` reader - Low detect enabled 40"] -pub type LEN40_R = crate::BitReader; +pub type LEN40_R = crate::BitReader; #[doc = "Field `LEN40` writer - Low detect enabled 40"] -pub type LEN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN41` reader - Low detect enabled 41"] -pub type LEN41_R = crate::BitReader; +pub type LEN41_R = crate::BitReader; #[doc = "Field `LEN41` writer - Low detect enabled 41"] -pub type LEN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN42` reader - Low detect enabled 42"] -pub type LEN42_R = crate::BitReader; +pub type LEN42_R = crate::BitReader; #[doc = "Field `LEN42` writer - Low detect enabled 42"] -pub type LEN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN43` reader - Low detect enabled 43"] -pub type LEN43_R = crate::BitReader; +pub type LEN43_R = crate::BitReader; #[doc = "Field `LEN43` writer - Low detect enabled 43"] -pub type LEN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN44` reader - Low detect enabled 44"] -pub type LEN44_R = crate::BitReader; +pub type LEN44_R = crate::BitReader; #[doc = "Field `LEN44` writer - Low detect enabled 44"] -pub type LEN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN45` reader - Low detect enabled 45"] -pub type LEN45_R = crate::BitReader; +pub type LEN45_R = crate::BitReader; #[doc = "Field `LEN45` writer - Low detect enabled 45"] -pub type LEN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN46` reader - Low detect enabled 46"] -pub type LEN46_R = crate::BitReader; +pub type LEN46_R = crate::BitReader; #[doc = "Field `LEN46` writer - Low detect enabled 46"] -pub type LEN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN47` reader - Low detect enabled 47"] -pub type LEN47_R = crate::BitReader; +pub type LEN47_R = crate::BitReader; #[doc = "Field `LEN47` writer - Low detect enabled 47"] -pub type LEN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN48` reader - Low detect enabled 48"] -pub type LEN48_R = crate::BitReader; +pub type LEN48_R = crate::BitReader; #[doc = "Field `LEN48` writer - Low detect enabled 48"] -pub type LEN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN49` reader - Low detect enabled 49"] -pub type LEN49_R = crate::BitReader; +pub type LEN49_R = crate::BitReader; #[doc = "Field `LEN49` writer - Low detect enabled 49"] -pub type LEN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN50` reader - Low detect enabled 50"] -pub type LEN50_R = crate::BitReader; +pub type LEN50_R = crate::BitReader; #[doc = "Field `LEN50` writer - Low detect enabled 50"] -pub type LEN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN51` reader - Low detect enabled 51"] -pub type LEN51_R = crate::BitReader; +pub type LEN51_R = crate::BitReader; #[doc = "Field `LEN51` writer - Low detect enabled 51"] -pub type LEN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN52` reader - Low detect enabled 52"] -pub type LEN52_R = crate::BitReader; +pub type LEN52_R = crate::BitReader; #[doc = "Field `LEN52` writer - Low detect enabled 52"] -pub type LEN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN53` reader - Low detect enabled 53"] -pub type LEN53_R = crate::BitReader; +pub type LEN53_R = crate::BitReader; #[doc = "Field `LEN53` writer - Low detect enabled 53"] -pub type LEN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPLEN1_SPEC, bool, O>; +pub type LEN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Low detect enabled 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { LEN53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPLEN1") + .field("len32", &format_args!("{}", self.len32().bit())) + .field("len33", &format_args!("{}", self.len33().bit())) + .field("len34", &format_args!("{}", self.len34().bit())) + .field("len35", &format_args!("{}", self.len35().bit())) + .field("len36", &format_args!("{}", self.len36().bit())) + .field("len37", &format_args!("{}", self.len37().bit())) + .field("len38", &format_args!("{}", self.len38().bit())) + .field("len39", &format_args!("{}", self.len39().bit())) + .field("len40", &format_args!("{}", self.len40().bit())) + .field("len41", &format_args!("{}", self.len41().bit())) + .field("len42", &format_args!("{}", self.len42().bit())) + .field("len43", &format_args!("{}", self.len43().bit())) + .field("len44", &format_args!("{}", self.len44().bit())) + .field("len45", &format_args!("{}", self.len45().bit())) + .field("len46", &format_args!("{}", self.len46().bit())) + .field("len47", &format_args!("{}", self.len47().bit())) + .field("len48", &format_args!("{}", self.len48().bit())) + .field("len49", &format_args!("{}", self.len49().bit())) + .field("len50", &format_args!("{}", self.len50().bit())) + .field("len51", &format_args!("{}", self.len51().bit())) + .field("len52", &format_args!("{}", self.len52().bit())) + .field("len53", &format_args!("{}", self.len53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Low detect enabled 32"] #[inline(always)] #[must_use] - pub fn len32(&mut self) -> LEN32_W<0> { + pub fn len32(&mut self) -> LEN32_W { LEN32_W::new(self) } #[doc = "Bit 1 - Low detect enabled 33"] #[inline(always)] #[must_use] - pub fn len33(&mut self) -> LEN33_W<1> { + pub fn len33(&mut self) -> LEN33_W { LEN33_W::new(self) } #[doc = "Bit 2 - Low detect enabled 34"] #[inline(always)] #[must_use] - pub fn len34(&mut self) -> LEN34_W<2> { + pub fn len34(&mut self) -> LEN34_W { LEN34_W::new(self) } #[doc = "Bit 3 - Low detect enabled 35"] #[inline(always)] #[must_use] - pub fn len35(&mut self) -> LEN35_W<3> { + pub fn len35(&mut self) -> LEN35_W { LEN35_W::new(self) } #[doc = "Bit 4 - Low detect enabled 36"] #[inline(always)] #[must_use] - pub fn len36(&mut self) -> LEN36_W<4> { + pub fn len36(&mut self) -> LEN36_W { LEN36_W::new(self) } #[doc = "Bit 5 - Low detect enabled 37"] #[inline(always)] #[must_use] - pub fn len37(&mut self) -> LEN37_W<5> { + pub fn len37(&mut self) -> LEN37_W { LEN37_W::new(self) } #[doc = "Bit 6 - Low detect enabled 38"] #[inline(always)] #[must_use] - pub fn len38(&mut self) -> LEN38_W<6> { + pub fn len38(&mut self) -> LEN38_W { LEN38_W::new(self) } #[doc = "Bit 7 - Low detect enabled 39"] #[inline(always)] #[must_use] - pub fn len39(&mut self) -> LEN39_W<7> { + pub fn len39(&mut self) -> LEN39_W { LEN39_W::new(self) } #[doc = "Bit 8 - Low detect enabled 40"] #[inline(always)] #[must_use] - pub fn len40(&mut self) -> LEN40_W<8> { + pub fn len40(&mut self) -> LEN40_W { LEN40_W::new(self) } #[doc = "Bit 9 - Low detect enabled 41"] #[inline(always)] #[must_use] - pub fn len41(&mut self) -> LEN41_W<9> { + pub fn len41(&mut self) -> LEN41_W { LEN41_W::new(self) } #[doc = "Bit 10 - Low detect enabled 42"] #[inline(always)] #[must_use] - pub fn len42(&mut self) -> LEN42_W<10> { + pub fn len42(&mut self) -> LEN42_W { LEN42_W::new(self) } #[doc = "Bit 11 - Low detect enabled 43"] #[inline(always)] #[must_use] - pub fn len43(&mut self) -> LEN43_W<11> { + pub fn len43(&mut self) -> LEN43_W { LEN43_W::new(self) } #[doc = "Bit 12 - Low detect enabled 44"] #[inline(always)] #[must_use] - pub fn len44(&mut self) -> LEN44_W<12> { + pub fn len44(&mut self) -> LEN44_W { LEN44_W::new(self) } #[doc = "Bit 13 - Low detect enabled 45"] #[inline(always)] #[must_use] - pub fn len45(&mut self) -> LEN45_W<13> { + pub fn len45(&mut self) -> LEN45_W { LEN45_W::new(self) } #[doc = "Bit 14 - Low detect enabled 46"] #[inline(always)] #[must_use] - pub fn len46(&mut self) -> LEN46_W<14> { + pub fn len46(&mut self) -> LEN46_W { LEN46_W::new(self) } #[doc = "Bit 15 - Low detect enabled 47"] #[inline(always)] #[must_use] - pub fn len47(&mut self) -> LEN47_W<15> { + pub fn len47(&mut self) -> LEN47_W { LEN47_W::new(self) } #[doc = "Bit 16 - Low detect enabled 48"] #[inline(always)] #[must_use] - pub fn len48(&mut self) -> LEN48_W<16> { + pub fn len48(&mut self) -> LEN48_W { LEN48_W::new(self) } #[doc = "Bit 17 - Low detect enabled 49"] #[inline(always)] #[must_use] - pub fn len49(&mut self) -> LEN49_W<17> { + pub fn len49(&mut self) -> LEN49_W { LEN49_W::new(self) } #[doc = "Bit 18 - Low detect enabled 50"] #[inline(always)] #[must_use] - pub fn len50(&mut self) -> LEN50_W<18> { + pub fn len50(&mut self) -> LEN50_W { LEN50_W::new(self) } #[doc = "Bit 19 - Low detect enabled 51"] #[inline(always)] #[must_use] - pub fn len51(&mut self) -> LEN51_W<19> { + pub fn len51(&mut self) -> LEN51_W { LEN51_W::new(self) } #[doc = "Bit 20 - Low detect enabled 52"] #[inline(always)] #[must_use] - pub fn len52(&mut self) -> LEN52_W<20> { + pub fn len52(&mut self) -> LEN52_W { LEN52_W::new(self) } #[doc = "Bit 21 - Low detect enabled 53"] #[inline(always)] #[must_use] - pub fn len53(&mut self) -> LEN53_W<21> { + pub fn len53(&mut self) -> LEN53_W { LEN53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Low Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplen1](index.html) module"] +#[doc = "GPIO Pin Low Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplen1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gplen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPLEN1_SPEC; impl crate::RegisterSpec for GPLEN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gplen1::R](R) reader structure"] -impl crate::Readable for GPLEN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gplen1::W](W) writer structure"] +#[doc = "`read()` method returns [`gplen1::R`](R) reader structure"] +impl crate::Readable for GPLEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gplen1::W`](W) writer structure"] impl crate::Writable for GPLEN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gplev0.rs b/crates/bcm2837-lpa/src/gpio/gplev0.rs index e6f9b94..43e1e5c 100644 --- a/crates/bcm2837-lpa/src/gpio/gplev0.rs +++ b/crates/bcm2837-lpa/src/gpio/gplev0.rs @@ -1,82 +1,69 @@ #[doc = "Register `GPLEV0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LEV0` reader - Level 0"] -pub type LEV0_R = crate::BitReader; +pub type LEV0_R = crate::BitReader; #[doc = "Field `LEV1` reader - Level 1"] -pub type LEV1_R = crate::BitReader; +pub type LEV1_R = crate::BitReader; #[doc = "Field `LEV2` reader - Level 2"] -pub type LEV2_R = crate::BitReader; +pub type LEV2_R = crate::BitReader; #[doc = "Field `LEV3` reader - Level 3"] -pub type LEV3_R = crate::BitReader; +pub type LEV3_R = crate::BitReader; #[doc = "Field `LEV4` reader - Level 4"] -pub type LEV4_R = crate::BitReader; +pub type LEV4_R = crate::BitReader; #[doc = "Field `LEV5` reader - Level 5"] -pub type LEV5_R = crate::BitReader; +pub type LEV5_R = crate::BitReader; #[doc = "Field `LEV6` reader - Level 6"] -pub type LEV6_R = crate::BitReader; +pub type LEV6_R = crate::BitReader; #[doc = "Field `LEV7` reader - Level 7"] -pub type LEV7_R = crate::BitReader; +pub type LEV7_R = crate::BitReader; #[doc = "Field `LEV8` reader - Level 8"] -pub type LEV8_R = crate::BitReader; +pub type LEV8_R = crate::BitReader; #[doc = "Field `LEV9` reader - Level 9"] -pub type LEV9_R = crate::BitReader; +pub type LEV9_R = crate::BitReader; #[doc = "Field `LEV10` reader - Level 10"] -pub type LEV10_R = crate::BitReader; +pub type LEV10_R = crate::BitReader; #[doc = "Field `LEV11` reader - Level 11"] -pub type LEV11_R = crate::BitReader; +pub type LEV11_R = crate::BitReader; #[doc = "Field `LEV12` reader - Level 12"] -pub type LEV12_R = crate::BitReader; +pub type LEV12_R = crate::BitReader; #[doc = "Field `LEV13` reader - Level 13"] -pub type LEV13_R = crate::BitReader; +pub type LEV13_R = crate::BitReader; #[doc = "Field `LEV14` reader - Level 14"] -pub type LEV14_R = crate::BitReader; +pub type LEV14_R = crate::BitReader; #[doc = "Field `LEV15` reader - Level 15"] -pub type LEV15_R = crate::BitReader; +pub type LEV15_R = crate::BitReader; #[doc = "Field `LEV16` reader - Level 16"] -pub type LEV16_R = crate::BitReader; +pub type LEV16_R = crate::BitReader; #[doc = "Field `LEV17` reader - Level 17"] -pub type LEV17_R = crate::BitReader; +pub type LEV17_R = crate::BitReader; #[doc = "Field `LEV18` reader - Level 18"] -pub type LEV18_R = crate::BitReader; +pub type LEV18_R = crate::BitReader; #[doc = "Field `LEV19` reader - Level 19"] -pub type LEV19_R = crate::BitReader; +pub type LEV19_R = crate::BitReader; #[doc = "Field `LEV20` reader - Level 20"] -pub type LEV20_R = crate::BitReader; +pub type LEV20_R = crate::BitReader; #[doc = "Field `LEV21` reader - Level 21"] -pub type LEV21_R = crate::BitReader; +pub type LEV21_R = crate::BitReader; #[doc = "Field `LEV22` reader - Level 22"] -pub type LEV22_R = crate::BitReader; +pub type LEV22_R = crate::BitReader; #[doc = "Field `LEV23` reader - Level 23"] -pub type LEV23_R = crate::BitReader; +pub type LEV23_R = crate::BitReader; #[doc = "Field `LEV24` reader - Level 24"] -pub type LEV24_R = crate::BitReader; +pub type LEV24_R = crate::BitReader; #[doc = "Field `LEV25` reader - Level 25"] -pub type LEV25_R = crate::BitReader; +pub type LEV25_R = crate::BitReader; #[doc = "Field `LEV26` reader - Level 26"] -pub type LEV26_R = crate::BitReader; +pub type LEV26_R = crate::BitReader; #[doc = "Field `LEV27` reader - Level 27"] -pub type LEV27_R = crate::BitReader; +pub type LEV27_R = crate::BitReader; #[doc = "Field `LEV28` reader - Level 28"] -pub type LEV28_R = crate::BitReader; +pub type LEV28_R = crate::BitReader; #[doc = "Field `LEV29` reader - Level 29"] -pub type LEV29_R = crate::BitReader; +pub type LEV29_R = crate::BitReader; #[doc = "Field `LEV30` reader - Level 30"] -pub type LEV30_R = crate::BitReader; +pub type LEV30_R = crate::BitReader; #[doc = "Field `LEV31` reader - Level 31"] -pub type LEV31_R = crate::BitReader; +pub type LEV31_R = crate::BitReader; impl R { #[doc = "Bit 0 - Level 0"] #[inline(always)] @@ -239,12 +226,53 @@ impl R { LEV31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "GPIO Pin Level 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplev0](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPLEV0") + .field("lev0", &format_args!("{}", self.lev0().bit())) + .field("lev1", &format_args!("{}", self.lev1().bit())) + .field("lev2", &format_args!("{}", self.lev2().bit())) + .field("lev3", &format_args!("{}", self.lev3().bit())) + .field("lev4", &format_args!("{}", self.lev4().bit())) + .field("lev5", &format_args!("{}", self.lev5().bit())) + .field("lev6", &format_args!("{}", self.lev6().bit())) + .field("lev7", &format_args!("{}", self.lev7().bit())) + .field("lev8", &format_args!("{}", self.lev8().bit())) + .field("lev9", &format_args!("{}", self.lev9().bit())) + .field("lev10", &format_args!("{}", self.lev10().bit())) + .field("lev11", &format_args!("{}", self.lev11().bit())) + .field("lev12", &format_args!("{}", self.lev12().bit())) + .field("lev13", &format_args!("{}", self.lev13().bit())) + .field("lev14", &format_args!("{}", self.lev14().bit())) + .field("lev15", &format_args!("{}", self.lev15().bit())) + .field("lev16", &format_args!("{}", self.lev16().bit())) + .field("lev17", &format_args!("{}", self.lev17().bit())) + .field("lev18", &format_args!("{}", self.lev18().bit())) + .field("lev19", &format_args!("{}", self.lev19().bit())) + .field("lev20", &format_args!("{}", self.lev20().bit())) + .field("lev21", &format_args!("{}", self.lev21().bit())) + .field("lev22", &format_args!("{}", self.lev22().bit())) + .field("lev23", &format_args!("{}", self.lev23().bit())) + .field("lev24", &format_args!("{}", self.lev24().bit())) + .field("lev25", &format_args!("{}", self.lev25().bit())) + .field("lev26", &format_args!("{}", self.lev26().bit())) + .field("lev27", &format_args!("{}", self.lev27().bit())) + .field("lev28", &format_args!("{}", self.lev28().bit())) + .field("lev29", &format_args!("{}", self.lev29().bit())) + .field("lev30", &format_args!("{}", self.lev30().bit())) + .field("lev31", &format_args!("{}", self.lev31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "GPIO Pin Level 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplev0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPLEV0_SPEC; impl crate::RegisterSpec for GPLEV0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gplev0::R](R) reader structure"] -impl crate::Readable for GPLEV0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gplev0::R`](R) reader structure"] +impl crate::Readable for GPLEV0_SPEC {} diff --git a/crates/bcm2837-lpa/src/gpio/gplev1.rs b/crates/bcm2837-lpa/src/gpio/gplev1.rs index 5323ce3..e881649 100644 --- a/crates/bcm2837-lpa/src/gpio/gplev1.rs +++ b/crates/bcm2837-lpa/src/gpio/gplev1.rs @@ -1,62 +1,49 @@ #[doc = "Register `GPLEV1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LEV32` reader - Level 32"] -pub type LEV32_R = crate::BitReader; +pub type LEV32_R = crate::BitReader; #[doc = "Field `LEV33` reader - Level 33"] -pub type LEV33_R = crate::BitReader; +pub type LEV33_R = crate::BitReader; #[doc = "Field `LEV34` reader - Level 34"] -pub type LEV34_R = crate::BitReader; +pub type LEV34_R = crate::BitReader; #[doc = "Field `LEV35` reader - Level 35"] -pub type LEV35_R = crate::BitReader; +pub type LEV35_R = crate::BitReader; #[doc = "Field `LEV36` reader - Level 36"] -pub type LEV36_R = crate::BitReader; +pub type LEV36_R = crate::BitReader; #[doc = "Field `LEV37` reader - Level 37"] -pub type LEV37_R = crate::BitReader; +pub type LEV37_R = crate::BitReader; #[doc = "Field `LEV38` reader - Level 38"] -pub type LEV38_R = crate::BitReader; +pub type LEV38_R = crate::BitReader; #[doc = "Field `LEV39` reader - Level 39"] -pub type LEV39_R = crate::BitReader; +pub type LEV39_R = crate::BitReader; #[doc = "Field `LEV40` reader - Level 40"] -pub type LEV40_R = crate::BitReader; +pub type LEV40_R = crate::BitReader; #[doc = "Field `LEV41` reader - Level 41"] -pub type LEV41_R = crate::BitReader; +pub type LEV41_R = crate::BitReader; #[doc = "Field `LEV42` reader - Level 42"] -pub type LEV42_R = crate::BitReader; +pub type LEV42_R = crate::BitReader; #[doc = "Field `LEV43` reader - Level 43"] -pub type LEV43_R = crate::BitReader; +pub type LEV43_R = crate::BitReader; #[doc = "Field `LEV44` reader - Level 44"] -pub type LEV44_R = crate::BitReader; +pub type LEV44_R = crate::BitReader; #[doc = "Field `LEV45` reader - Level 45"] -pub type LEV45_R = crate::BitReader; +pub type LEV45_R = crate::BitReader; #[doc = "Field `LEV46` reader - Level 46"] -pub type LEV46_R = crate::BitReader; +pub type LEV46_R = crate::BitReader; #[doc = "Field `LEV47` reader - Level 47"] -pub type LEV47_R = crate::BitReader; +pub type LEV47_R = crate::BitReader; #[doc = "Field `LEV48` reader - Level 48"] -pub type LEV48_R = crate::BitReader; +pub type LEV48_R = crate::BitReader; #[doc = "Field `LEV49` reader - Level 49"] -pub type LEV49_R = crate::BitReader; +pub type LEV49_R = crate::BitReader; #[doc = "Field `LEV50` reader - Level 50"] -pub type LEV50_R = crate::BitReader; +pub type LEV50_R = crate::BitReader; #[doc = "Field `LEV51` reader - Level 51"] -pub type LEV51_R = crate::BitReader; +pub type LEV51_R = crate::BitReader; #[doc = "Field `LEV52` reader - Level 52"] -pub type LEV52_R = crate::BitReader; +pub type LEV52_R = crate::BitReader; #[doc = "Field `LEV53` reader - Level 53"] -pub type LEV53_R = crate::BitReader; +pub type LEV53_R = crate::BitReader; impl R { #[doc = "Bit 0 - Level 32"] #[inline(always)] @@ -169,12 +156,43 @@ impl R { LEV53_R::new(((self.bits >> 21) & 1) != 0) } } -#[doc = "GPIO Pin Level 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gplev1](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPLEV1") + .field("lev32", &format_args!("{}", self.lev32().bit())) + .field("lev33", &format_args!("{}", self.lev33().bit())) + .field("lev34", &format_args!("{}", self.lev34().bit())) + .field("lev35", &format_args!("{}", self.lev35().bit())) + .field("lev36", &format_args!("{}", self.lev36().bit())) + .field("lev37", &format_args!("{}", self.lev37().bit())) + .field("lev38", &format_args!("{}", self.lev38().bit())) + .field("lev39", &format_args!("{}", self.lev39().bit())) + .field("lev40", &format_args!("{}", self.lev40().bit())) + .field("lev41", &format_args!("{}", self.lev41().bit())) + .field("lev42", &format_args!("{}", self.lev42().bit())) + .field("lev43", &format_args!("{}", self.lev43().bit())) + .field("lev44", &format_args!("{}", self.lev44().bit())) + .field("lev45", &format_args!("{}", self.lev45().bit())) + .field("lev46", &format_args!("{}", self.lev46().bit())) + .field("lev47", &format_args!("{}", self.lev47().bit())) + .field("lev48", &format_args!("{}", self.lev48().bit())) + .field("lev49", &format_args!("{}", self.lev49().bit())) + .field("lev50", &format_args!("{}", self.lev50().bit())) + .field("lev51", &format_args!("{}", self.lev51().bit())) + .field("lev52", &format_args!("{}", self.lev52().bit())) + .field("lev53", &format_args!("{}", self.lev53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "GPIO Pin Level 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gplev1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPLEV1_SPEC; impl crate::RegisterSpec for GPLEV1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gplev1::R](R) reader structure"] -impl crate::Readable for GPLEV1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gplev1::R`](R) reader structure"] +impl crate::Readable for GPLEV1_SPEC {} diff --git a/crates/bcm2837-lpa/src/gpio/gpren0.rs b/crates/bcm2837-lpa/src/gpio/gpren0.rs index af4f16c..f4dfc2e 100644 --- a/crates/bcm2837-lpa/src/gpio/gpren0.rs +++ b/crates/bcm2837-lpa/src/gpio/gpren0.rs @@ -1,167 +1,135 @@ #[doc = "Register `GPREN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPREN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `REN0` reader - Rising edge enabled 0"] -pub type REN0_R = crate::BitReader; +pub type REN0_R = crate::BitReader; #[doc = "Field `REN0` writer - Rising edge enabled 0"] -pub type REN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN1` reader - Rising edge enabled 1"] -pub type REN1_R = crate::BitReader; +pub type REN1_R = crate::BitReader; #[doc = "Field `REN1` writer - Rising edge enabled 1"] -pub type REN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN2` reader - Rising edge enabled 2"] -pub type REN2_R = crate::BitReader; +pub type REN2_R = crate::BitReader; #[doc = "Field `REN2` writer - Rising edge enabled 2"] -pub type REN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN3` reader - Rising edge enabled 3"] -pub type REN3_R = crate::BitReader; +pub type REN3_R = crate::BitReader; #[doc = "Field `REN3` writer - Rising edge enabled 3"] -pub type REN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN4` reader - Rising edge enabled 4"] -pub type REN4_R = crate::BitReader; +pub type REN4_R = crate::BitReader; #[doc = "Field `REN4` writer - Rising edge enabled 4"] -pub type REN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN5` reader - Rising edge enabled 5"] -pub type REN5_R = crate::BitReader; +pub type REN5_R = crate::BitReader; #[doc = "Field `REN5` writer - Rising edge enabled 5"] -pub type REN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN6` reader - Rising edge enabled 6"] -pub type REN6_R = crate::BitReader; +pub type REN6_R = crate::BitReader; #[doc = "Field `REN6` writer - Rising edge enabled 6"] -pub type REN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN7` reader - Rising edge enabled 7"] -pub type REN7_R = crate::BitReader; +pub type REN7_R = crate::BitReader; #[doc = "Field `REN7` writer - Rising edge enabled 7"] -pub type REN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN8` reader - Rising edge enabled 8"] -pub type REN8_R = crate::BitReader; +pub type REN8_R = crate::BitReader; #[doc = "Field `REN8` writer - Rising edge enabled 8"] -pub type REN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN9` reader - Rising edge enabled 9"] -pub type REN9_R = crate::BitReader; +pub type REN9_R = crate::BitReader; #[doc = "Field `REN9` writer - Rising edge enabled 9"] -pub type REN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN10` reader - Rising edge enabled 10"] -pub type REN10_R = crate::BitReader; +pub type REN10_R = crate::BitReader; #[doc = "Field `REN10` writer - Rising edge enabled 10"] -pub type REN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN11` reader - Rising edge enabled 11"] -pub type REN11_R = crate::BitReader; +pub type REN11_R = crate::BitReader; #[doc = "Field `REN11` writer - Rising edge enabled 11"] -pub type REN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN12` reader - Rising edge enabled 12"] -pub type REN12_R = crate::BitReader; +pub type REN12_R = crate::BitReader; #[doc = "Field `REN12` writer - Rising edge enabled 12"] -pub type REN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN13` reader - Rising edge enabled 13"] -pub type REN13_R = crate::BitReader; +pub type REN13_R = crate::BitReader; #[doc = "Field `REN13` writer - Rising edge enabled 13"] -pub type REN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN14` reader - Rising edge enabled 14"] -pub type REN14_R = crate::BitReader; +pub type REN14_R = crate::BitReader; #[doc = "Field `REN14` writer - Rising edge enabled 14"] -pub type REN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN15` reader - Rising edge enabled 15"] -pub type REN15_R = crate::BitReader; +pub type REN15_R = crate::BitReader; #[doc = "Field `REN15` writer - Rising edge enabled 15"] -pub type REN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN16` reader - Rising edge enabled 16"] -pub type REN16_R = crate::BitReader; +pub type REN16_R = crate::BitReader; #[doc = "Field `REN16` writer - Rising edge enabled 16"] -pub type REN16_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN17` reader - Rising edge enabled 17"] -pub type REN17_R = crate::BitReader; +pub type REN17_R = crate::BitReader; #[doc = "Field `REN17` writer - Rising edge enabled 17"] -pub type REN17_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN18` reader - Rising edge enabled 18"] -pub type REN18_R = crate::BitReader; +pub type REN18_R = crate::BitReader; #[doc = "Field `REN18` writer - Rising edge enabled 18"] -pub type REN18_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN19` reader - Rising edge enabled 19"] -pub type REN19_R = crate::BitReader; +pub type REN19_R = crate::BitReader; #[doc = "Field `REN19` writer - Rising edge enabled 19"] -pub type REN19_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN20` reader - Rising edge enabled 20"] -pub type REN20_R = crate::BitReader; +pub type REN20_R = crate::BitReader; #[doc = "Field `REN20` writer - Rising edge enabled 20"] -pub type REN20_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN21` reader - Rising edge enabled 21"] -pub type REN21_R = crate::BitReader; +pub type REN21_R = crate::BitReader; #[doc = "Field `REN21` writer - Rising edge enabled 21"] -pub type REN21_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN22` reader - Rising edge enabled 22"] -pub type REN22_R = crate::BitReader; +pub type REN22_R = crate::BitReader; #[doc = "Field `REN22` writer - Rising edge enabled 22"] -pub type REN22_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN23` reader - Rising edge enabled 23"] -pub type REN23_R = crate::BitReader; +pub type REN23_R = crate::BitReader; #[doc = "Field `REN23` writer - Rising edge enabled 23"] -pub type REN23_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN24` reader - Rising edge enabled 24"] -pub type REN24_R = crate::BitReader; +pub type REN24_R = crate::BitReader; #[doc = "Field `REN24` writer - Rising edge enabled 24"] -pub type REN24_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN25` reader - Rising edge enabled 25"] -pub type REN25_R = crate::BitReader; +pub type REN25_R = crate::BitReader; #[doc = "Field `REN25` writer - Rising edge enabled 25"] -pub type REN25_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN26` reader - Rising edge enabled 26"] -pub type REN26_R = crate::BitReader; +pub type REN26_R = crate::BitReader; #[doc = "Field `REN26` writer - Rising edge enabled 26"] -pub type REN26_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN27` reader - Rising edge enabled 27"] -pub type REN27_R = crate::BitReader; +pub type REN27_R = crate::BitReader; #[doc = "Field `REN27` writer - Rising edge enabled 27"] -pub type REN27_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN28` reader - Rising edge enabled 28"] -pub type REN28_R = crate::BitReader; +pub type REN28_R = crate::BitReader; #[doc = "Field `REN28` writer - Rising edge enabled 28"] -pub type REN28_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN29` reader - Rising edge enabled 29"] -pub type REN29_R = crate::BitReader; +pub type REN29_R = crate::BitReader; #[doc = "Field `REN29` writer - Rising edge enabled 29"] -pub type REN29_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN30` reader - Rising edge enabled 30"] -pub type REN30_R = crate::BitReader; +pub type REN30_R = crate::BitReader; #[doc = "Field `REN30` writer - Rising edge enabled 30"] -pub type REN30_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN31` reader - Rising edge enabled 31"] -pub type REN31_R = crate::BitReader; +pub type REN31_R = crate::BitReader; #[doc = "Field `REN31` writer - Rising edge enabled 31"] -pub type REN31_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN0_SPEC, bool, O>; +pub type REN31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Rising edge enabled 0"] #[inline(always)] @@ -324,218 +292,262 @@ impl R { REN31_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPREN0") + .field("ren0", &format_args!("{}", self.ren0().bit())) + .field("ren1", &format_args!("{}", self.ren1().bit())) + .field("ren2", &format_args!("{}", self.ren2().bit())) + .field("ren3", &format_args!("{}", self.ren3().bit())) + .field("ren4", &format_args!("{}", self.ren4().bit())) + .field("ren5", &format_args!("{}", self.ren5().bit())) + .field("ren6", &format_args!("{}", self.ren6().bit())) + .field("ren7", &format_args!("{}", self.ren7().bit())) + .field("ren8", &format_args!("{}", self.ren8().bit())) + .field("ren9", &format_args!("{}", self.ren9().bit())) + .field("ren10", &format_args!("{}", self.ren10().bit())) + .field("ren11", &format_args!("{}", self.ren11().bit())) + .field("ren12", &format_args!("{}", self.ren12().bit())) + .field("ren13", &format_args!("{}", self.ren13().bit())) + .field("ren14", &format_args!("{}", self.ren14().bit())) + .field("ren15", &format_args!("{}", self.ren15().bit())) + .field("ren16", &format_args!("{}", self.ren16().bit())) + .field("ren17", &format_args!("{}", self.ren17().bit())) + .field("ren18", &format_args!("{}", self.ren18().bit())) + .field("ren19", &format_args!("{}", self.ren19().bit())) + .field("ren20", &format_args!("{}", self.ren20().bit())) + .field("ren21", &format_args!("{}", self.ren21().bit())) + .field("ren22", &format_args!("{}", self.ren22().bit())) + .field("ren23", &format_args!("{}", self.ren23().bit())) + .field("ren24", &format_args!("{}", self.ren24().bit())) + .field("ren25", &format_args!("{}", self.ren25().bit())) + .field("ren26", &format_args!("{}", self.ren26().bit())) + .field("ren27", &format_args!("{}", self.ren27().bit())) + .field("ren28", &format_args!("{}", self.ren28().bit())) + .field("ren29", &format_args!("{}", self.ren29().bit())) + .field("ren30", &format_args!("{}", self.ren30().bit())) + .field("ren31", &format_args!("{}", self.ren31().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Rising edge enabled 0"] #[inline(always)] #[must_use] - pub fn ren0(&mut self) -> REN0_W<0> { + pub fn ren0(&mut self) -> REN0_W { REN0_W::new(self) } #[doc = "Bit 1 - Rising edge enabled 1"] #[inline(always)] #[must_use] - pub fn ren1(&mut self) -> REN1_W<1> { + pub fn ren1(&mut self) -> REN1_W { REN1_W::new(self) } #[doc = "Bit 2 - Rising edge enabled 2"] #[inline(always)] #[must_use] - pub fn ren2(&mut self) -> REN2_W<2> { + pub fn ren2(&mut self) -> REN2_W { REN2_W::new(self) } #[doc = "Bit 3 - Rising edge enabled 3"] #[inline(always)] #[must_use] - pub fn ren3(&mut self) -> REN3_W<3> { + pub fn ren3(&mut self) -> REN3_W { REN3_W::new(self) } #[doc = "Bit 4 - Rising edge enabled 4"] #[inline(always)] #[must_use] - pub fn ren4(&mut self) -> REN4_W<4> { + pub fn ren4(&mut self) -> REN4_W { REN4_W::new(self) } #[doc = "Bit 5 - Rising edge enabled 5"] #[inline(always)] #[must_use] - pub fn ren5(&mut self) -> REN5_W<5> { + pub fn ren5(&mut self) -> REN5_W { REN5_W::new(self) } #[doc = "Bit 6 - Rising edge enabled 6"] #[inline(always)] #[must_use] - pub fn ren6(&mut self) -> REN6_W<6> { + pub fn ren6(&mut self) -> REN6_W { REN6_W::new(self) } #[doc = "Bit 7 - Rising edge enabled 7"] #[inline(always)] #[must_use] - pub fn ren7(&mut self) -> REN7_W<7> { + pub fn ren7(&mut self) -> REN7_W { REN7_W::new(self) } #[doc = "Bit 8 - Rising edge enabled 8"] #[inline(always)] #[must_use] - pub fn ren8(&mut self) -> REN8_W<8> { + pub fn ren8(&mut self) -> REN8_W { REN8_W::new(self) } #[doc = "Bit 9 - Rising edge enabled 9"] #[inline(always)] #[must_use] - pub fn ren9(&mut self) -> REN9_W<9> { + pub fn ren9(&mut self) -> REN9_W { REN9_W::new(self) } #[doc = "Bit 10 - Rising edge enabled 10"] #[inline(always)] #[must_use] - pub fn ren10(&mut self) -> REN10_W<10> { + pub fn ren10(&mut self) -> REN10_W { REN10_W::new(self) } #[doc = "Bit 11 - Rising edge enabled 11"] #[inline(always)] #[must_use] - pub fn ren11(&mut self) -> REN11_W<11> { + pub fn ren11(&mut self) -> REN11_W { REN11_W::new(self) } #[doc = "Bit 12 - Rising edge enabled 12"] #[inline(always)] #[must_use] - pub fn ren12(&mut self) -> REN12_W<12> { + pub fn ren12(&mut self) -> REN12_W { REN12_W::new(self) } #[doc = "Bit 13 - Rising edge enabled 13"] #[inline(always)] #[must_use] - pub fn ren13(&mut self) -> REN13_W<13> { + pub fn ren13(&mut self) -> REN13_W { REN13_W::new(self) } #[doc = "Bit 14 - Rising edge enabled 14"] #[inline(always)] #[must_use] - pub fn ren14(&mut self) -> REN14_W<14> { + pub fn ren14(&mut self) -> REN14_W { REN14_W::new(self) } #[doc = "Bit 15 - Rising edge enabled 15"] #[inline(always)] #[must_use] - pub fn ren15(&mut self) -> REN15_W<15> { + pub fn ren15(&mut self) -> REN15_W { REN15_W::new(self) } #[doc = "Bit 16 - Rising edge enabled 16"] #[inline(always)] #[must_use] - pub fn ren16(&mut self) -> REN16_W<16> { + pub fn ren16(&mut self) -> REN16_W { REN16_W::new(self) } #[doc = "Bit 17 - Rising edge enabled 17"] #[inline(always)] #[must_use] - pub fn ren17(&mut self) -> REN17_W<17> { + pub fn ren17(&mut self) -> REN17_W { REN17_W::new(self) } #[doc = "Bit 18 - Rising edge enabled 18"] #[inline(always)] #[must_use] - pub fn ren18(&mut self) -> REN18_W<18> { + pub fn ren18(&mut self) -> REN18_W { REN18_W::new(self) } #[doc = "Bit 19 - Rising edge enabled 19"] #[inline(always)] #[must_use] - pub fn ren19(&mut self) -> REN19_W<19> { + pub fn ren19(&mut self) -> REN19_W { REN19_W::new(self) } #[doc = "Bit 20 - Rising edge enabled 20"] #[inline(always)] #[must_use] - pub fn ren20(&mut self) -> REN20_W<20> { + pub fn ren20(&mut self) -> REN20_W { REN20_W::new(self) } #[doc = "Bit 21 - Rising edge enabled 21"] #[inline(always)] #[must_use] - pub fn ren21(&mut self) -> REN21_W<21> { + pub fn ren21(&mut self) -> REN21_W { REN21_W::new(self) } #[doc = "Bit 22 - Rising edge enabled 22"] #[inline(always)] #[must_use] - pub fn ren22(&mut self) -> REN22_W<22> { + pub fn ren22(&mut self) -> REN22_W { REN22_W::new(self) } #[doc = "Bit 23 - Rising edge enabled 23"] #[inline(always)] #[must_use] - pub fn ren23(&mut self) -> REN23_W<23> { + pub fn ren23(&mut self) -> REN23_W { REN23_W::new(self) } #[doc = "Bit 24 - Rising edge enabled 24"] #[inline(always)] #[must_use] - pub fn ren24(&mut self) -> REN24_W<24> { + pub fn ren24(&mut self) -> REN24_W { REN24_W::new(self) } #[doc = "Bit 25 - Rising edge enabled 25"] #[inline(always)] #[must_use] - pub fn ren25(&mut self) -> REN25_W<25> { + pub fn ren25(&mut self) -> REN25_W { REN25_W::new(self) } #[doc = "Bit 26 - Rising edge enabled 26"] #[inline(always)] #[must_use] - pub fn ren26(&mut self) -> REN26_W<26> { + pub fn ren26(&mut self) -> REN26_W { REN26_W::new(self) } #[doc = "Bit 27 - Rising edge enabled 27"] #[inline(always)] #[must_use] - pub fn ren27(&mut self) -> REN27_W<27> { + pub fn ren27(&mut self) -> REN27_W { REN27_W::new(self) } #[doc = "Bit 28 - Rising edge enabled 28"] #[inline(always)] #[must_use] - pub fn ren28(&mut self) -> REN28_W<28> { + pub fn ren28(&mut self) -> REN28_W { REN28_W::new(self) } #[doc = "Bit 29 - Rising edge enabled 29"] #[inline(always)] #[must_use] - pub fn ren29(&mut self) -> REN29_W<29> { + pub fn ren29(&mut self) -> REN29_W { REN29_W::new(self) } #[doc = "Bit 30 - Rising edge enabled 30"] #[inline(always)] #[must_use] - pub fn ren30(&mut self) -> REN30_W<30> { + pub fn ren30(&mut self) -> REN30_W { REN30_W::new(self) } #[doc = "Bit 31 - Rising edge enabled 31"] #[inline(always)] #[must_use] - pub fn ren31(&mut self) -> REN31_W<31> { + pub fn ren31(&mut self) -> REN31_W { REN31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Rising Edge Detect Enable 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpren0](index.html) module"] +#[doc = "GPIO Pin Rising Edge Detect Enable 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpren0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpren0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPREN0_SPEC; impl crate::RegisterSpec for GPREN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpren0::R](R) reader structure"] -impl crate::Readable for GPREN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpren0::W](W) writer structure"] +#[doc = "`read()` method returns [`gpren0::R`](R) reader structure"] +impl crate::Readable for GPREN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpren0::W`](W) writer structure"] impl crate::Writable for GPREN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpren1.rs b/crates/bcm2837-lpa/src/gpio/gpren1.rs index 3e70995..9f78a23 100644 --- a/crates/bcm2837-lpa/src/gpio/gpren1.rs +++ b/crates/bcm2837-lpa/src/gpio/gpren1.rs @@ -1,127 +1,95 @@ #[doc = "Register `GPREN1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GPREN1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `REN32` reader - Rising edge enabled 32"] -pub type REN32_R = crate::BitReader; +pub type REN32_R = crate::BitReader; #[doc = "Field `REN32` writer - Rising edge enabled 32"] -pub type REN32_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN33` reader - Rising edge enabled 33"] -pub type REN33_R = crate::BitReader; +pub type REN33_R = crate::BitReader; #[doc = "Field `REN33` writer - Rising edge enabled 33"] -pub type REN33_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN34` reader - Rising edge enabled 34"] -pub type REN34_R = crate::BitReader; +pub type REN34_R = crate::BitReader; #[doc = "Field `REN34` writer - Rising edge enabled 34"] -pub type REN34_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN35` reader - Rising edge enabled 35"] -pub type REN35_R = crate::BitReader; +pub type REN35_R = crate::BitReader; #[doc = "Field `REN35` writer - Rising edge enabled 35"] -pub type REN35_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN36` reader - Rising edge enabled 36"] -pub type REN36_R = crate::BitReader; +pub type REN36_R = crate::BitReader; #[doc = "Field `REN36` writer - Rising edge enabled 36"] -pub type REN36_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN37` reader - Rising edge enabled 37"] -pub type REN37_R = crate::BitReader; +pub type REN37_R = crate::BitReader; #[doc = "Field `REN37` writer - Rising edge enabled 37"] -pub type REN37_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN38` reader - Rising edge enabled 38"] -pub type REN38_R = crate::BitReader; +pub type REN38_R = crate::BitReader; #[doc = "Field `REN38` writer - Rising edge enabled 38"] -pub type REN38_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN39` reader - Rising edge enabled 39"] -pub type REN39_R = crate::BitReader; +pub type REN39_R = crate::BitReader; #[doc = "Field `REN39` writer - Rising edge enabled 39"] -pub type REN39_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN40` reader - Rising edge enabled 40"] -pub type REN40_R = crate::BitReader; +pub type REN40_R = crate::BitReader; #[doc = "Field `REN40` writer - Rising edge enabled 40"] -pub type REN40_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN41` reader - Rising edge enabled 41"] -pub type REN41_R = crate::BitReader; +pub type REN41_R = crate::BitReader; #[doc = "Field `REN41` writer - Rising edge enabled 41"] -pub type REN41_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN42` reader - Rising edge enabled 42"] -pub type REN42_R = crate::BitReader; +pub type REN42_R = crate::BitReader; #[doc = "Field `REN42` writer - Rising edge enabled 42"] -pub type REN42_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN43` reader - Rising edge enabled 43"] -pub type REN43_R = crate::BitReader; +pub type REN43_R = crate::BitReader; #[doc = "Field `REN43` writer - Rising edge enabled 43"] -pub type REN43_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN44` reader - Rising edge enabled 44"] -pub type REN44_R = crate::BitReader; +pub type REN44_R = crate::BitReader; #[doc = "Field `REN44` writer - Rising edge enabled 44"] -pub type REN44_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN45` reader - Rising edge enabled 45"] -pub type REN45_R = crate::BitReader; +pub type REN45_R = crate::BitReader; #[doc = "Field `REN45` writer - Rising edge enabled 45"] -pub type REN45_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN46` reader - Rising edge enabled 46"] -pub type REN46_R = crate::BitReader; +pub type REN46_R = crate::BitReader; #[doc = "Field `REN46` writer - Rising edge enabled 46"] -pub type REN46_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN47` reader - Rising edge enabled 47"] -pub type REN47_R = crate::BitReader; +pub type REN47_R = crate::BitReader; #[doc = "Field `REN47` writer - Rising edge enabled 47"] -pub type REN47_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN48` reader - Rising edge enabled 48"] -pub type REN48_R = crate::BitReader; +pub type REN48_R = crate::BitReader; #[doc = "Field `REN48` writer - Rising edge enabled 48"] -pub type REN48_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN49` reader - Rising edge enabled 49"] -pub type REN49_R = crate::BitReader; +pub type REN49_R = crate::BitReader; #[doc = "Field `REN49` writer - Rising edge enabled 49"] -pub type REN49_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN50` reader - Rising edge enabled 50"] -pub type REN50_R = crate::BitReader; +pub type REN50_R = crate::BitReader; #[doc = "Field `REN50` writer - Rising edge enabled 50"] -pub type REN50_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN51` reader - Rising edge enabled 51"] -pub type REN51_R = crate::BitReader; +pub type REN51_R = crate::BitReader; #[doc = "Field `REN51` writer - Rising edge enabled 51"] -pub type REN51_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN52` reader - Rising edge enabled 52"] -pub type REN52_R = crate::BitReader; +pub type REN52_R = crate::BitReader; #[doc = "Field `REN52` writer - Rising edge enabled 52"] -pub type REN52_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN53` reader - Rising edge enabled 53"] -pub type REN53_R = crate::BitReader; +pub type REN53_R = crate::BitReader; #[doc = "Field `REN53` writer - Rising edge enabled 53"] -pub type REN53_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPREN1_SPEC, bool, O>; +pub type REN53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Rising edge enabled 32"] #[inline(always)] @@ -234,158 +202,192 @@ impl R { REN53_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPREN1") + .field("ren32", &format_args!("{}", self.ren32().bit())) + .field("ren33", &format_args!("{}", self.ren33().bit())) + .field("ren34", &format_args!("{}", self.ren34().bit())) + .field("ren35", &format_args!("{}", self.ren35().bit())) + .field("ren36", &format_args!("{}", self.ren36().bit())) + .field("ren37", &format_args!("{}", self.ren37().bit())) + .field("ren38", &format_args!("{}", self.ren38().bit())) + .field("ren39", &format_args!("{}", self.ren39().bit())) + .field("ren40", &format_args!("{}", self.ren40().bit())) + .field("ren41", &format_args!("{}", self.ren41().bit())) + .field("ren42", &format_args!("{}", self.ren42().bit())) + .field("ren43", &format_args!("{}", self.ren43().bit())) + .field("ren44", &format_args!("{}", self.ren44().bit())) + .field("ren45", &format_args!("{}", self.ren45().bit())) + .field("ren46", &format_args!("{}", self.ren46().bit())) + .field("ren47", &format_args!("{}", self.ren47().bit())) + .field("ren48", &format_args!("{}", self.ren48().bit())) + .field("ren49", &format_args!("{}", self.ren49().bit())) + .field("ren50", &format_args!("{}", self.ren50().bit())) + .field("ren51", &format_args!("{}", self.ren51().bit())) + .field("ren52", &format_args!("{}", self.ren52().bit())) + .field("ren53", &format_args!("{}", self.ren53().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Rising edge enabled 32"] #[inline(always)] #[must_use] - pub fn ren32(&mut self) -> REN32_W<0> { + pub fn ren32(&mut self) -> REN32_W { REN32_W::new(self) } #[doc = "Bit 1 - Rising edge enabled 33"] #[inline(always)] #[must_use] - pub fn ren33(&mut self) -> REN33_W<1> { + pub fn ren33(&mut self) -> REN33_W { REN33_W::new(self) } #[doc = "Bit 2 - Rising edge enabled 34"] #[inline(always)] #[must_use] - pub fn ren34(&mut self) -> REN34_W<2> { + pub fn ren34(&mut self) -> REN34_W { REN34_W::new(self) } #[doc = "Bit 3 - Rising edge enabled 35"] #[inline(always)] #[must_use] - pub fn ren35(&mut self) -> REN35_W<3> { + pub fn ren35(&mut self) -> REN35_W { REN35_W::new(self) } #[doc = "Bit 4 - Rising edge enabled 36"] #[inline(always)] #[must_use] - pub fn ren36(&mut self) -> REN36_W<4> { + pub fn ren36(&mut self) -> REN36_W { REN36_W::new(self) } #[doc = "Bit 5 - Rising edge enabled 37"] #[inline(always)] #[must_use] - pub fn ren37(&mut self) -> REN37_W<5> { + pub fn ren37(&mut self) -> REN37_W { REN37_W::new(self) } #[doc = "Bit 6 - Rising edge enabled 38"] #[inline(always)] #[must_use] - pub fn ren38(&mut self) -> REN38_W<6> { + pub fn ren38(&mut self) -> REN38_W { REN38_W::new(self) } #[doc = "Bit 7 - Rising edge enabled 39"] #[inline(always)] #[must_use] - pub fn ren39(&mut self) -> REN39_W<7> { + pub fn ren39(&mut self) -> REN39_W { REN39_W::new(self) } #[doc = "Bit 8 - Rising edge enabled 40"] #[inline(always)] #[must_use] - pub fn ren40(&mut self) -> REN40_W<8> { + pub fn ren40(&mut self) -> REN40_W { REN40_W::new(self) } #[doc = "Bit 9 - Rising edge enabled 41"] #[inline(always)] #[must_use] - pub fn ren41(&mut self) -> REN41_W<9> { + pub fn ren41(&mut self) -> REN41_W { REN41_W::new(self) } #[doc = "Bit 10 - Rising edge enabled 42"] #[inline(always)] #[must_use] - pub fn ren42(&mut self) -> REN42_W<10> { + pub fn ren42(&mut self) -> REN42_W { REN42_W::new(self) } #[doc = "Bit 11 - Rising edge enabled 43"] #[inline(always)] #[must_use] - pub fn ren43(&mut self) -> REN43_W<11> { + pub fn ren43(&mut self) -> REN43_W { REN43_W::new(self) } #[doc = "Bit 12 - Rising edge enabled 44"] #[inline(always)] #[must_use] - pub fn ren44(&mut self) -> REN44_W<12> { + pub fn ren44(&mut self) -> REN44_W { REN44_W::new(self) } #[doc = "Bit 13 - Rising edge enabled 45"] #[inline(always)] #[must_use] - pub fn ren45(&mut self) -> REN45_W<13> { + pub fn ren45(&mut self) -> REN45_W { REN45_W::new(self) } #[doc = "Bit 14 - Rising edge enabled 46"] #[inline(always)] #[must_use] - pub fn ren46(&mut self) -> REN46_W<14> { + pub fn ren46(&mut self) -> REN46_W { REN46_W::new(self) } #[doc = "Bit 15 - Rising edge enabled 47"] #[inline(always)] #[must_use] - pub fn ren47(&mut self) -> REN47_W<15> { + pub fn ren47(&mut self) -> REN47_W { REN47_W::new(self) } #[doc = "Bit 16 - Rising edge enabled 48"] #[inline(always)] #[must_use] - pub fn ren48(&mut self) -> REN48_W<16> { + pub fn ren48(&mut self) -> REN48_W { REN48_W::new(self) } #[doc = "Bit 17 - Rising edge enabled 49"] #[inline(always)] #[must_use] - pub fn ren49(&mut self) -> REN49_W<17> { + pub fn ren49(&mut self) -> REN49_W { REN49_W::new(self) } #[doc = "Bit 18 - Rising edge enabled 50"] #[inline(always)] #[must_use] - pub fn ren50(&mut self) -> REN50_W<18> { + pub fn ren50(&mut self) -> REN50_W { REN50_W::new(self) } #[doc = "Bit 19 - Rising edge enabled 51"] #[inline(always)] #[must_use] - pub fn ren51(&mut self) -> REN51_W<19> { + pub fn ren51(&mut self) -> REN51_W { REN51_W::new(self) } #[doc = "Bit 20 - Rising edge enabled 52"] #[inline(always)] #[must_use] - pub fn ren52(&mut self) -> REN52_W<20> { + pub fn ren52(&mut self) -> REN52_W { REN52_W::new(self) } #[doc = "Bit 21 - Rising edge enabled 53"] #[inline(always)] #[must_use] - pub fn ren53(&mut self) -> REN53_W<21> { + pub fn ren53(&mut self) -> REN53_W { REN53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Rising Edge Detect Enable 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpren1](index.html) module"] +#[doc = "GPIO Pin Rising Edge Detect Enable 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpren1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpren1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPREN1_SPEC; impl crate::RegisterSpec for GPREN1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gpren1::R](R) reader structure"] -impl crate::Readable for GPREN1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gpren1::W](W) writer structure"] +#[doc = "`read()` method returns [`gpren1::R`](R) reader structure"] +impl crate::Readable for GPREN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpren1::W`](W) writer structure"] impl crate::Writable for GPREN1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/gpio/gpset0.rs b/crates/bcm2837-lpa/src/gpio/gpset0.rs index 49e2659..513781b 100644 --- a/crates/bcm2837-lpa/src/gpio/gpset0.rs +++ b/crates/bcm2837-lpa/src/gpio/gpset0.rs @@ -1,296 +1,285 @@ #[doc = "Register `GPSET0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SET0` writer - Set 0"] -pub type SET0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET1` writer - Set 1"] -pub type SET1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET2` writer - Set 2"] -pub type SET2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET3` writer - Set 3"] -pub type SET3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET4` writer - Set 4"] -pub type SET4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET5` writer - Set 5"] -pub type SET5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET6` writer - Set 6"] -pub type SET6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET7` writer - Set 7"] -pub type SET7_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET7_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET8` writer - Set 8"] -pub type SET8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET8_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET9` writer - Set 9"] -pub type SET9_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET9_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET10` writer - Set 10"] -pub type SET10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET10_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET11` writer - Set 11"] -pub type SET11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET11_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET12` writer - Set 12"] -pub type SET12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET12_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET13` writer - Set 13"] -pub type SET13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET13_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET14` writer - Set 14"] -pub type SET14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET14_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET15` writer - Set 15"] -pub type SET15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET15_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET16` writer - Set 16"] -pub type SET16_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET16_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET17` writer - Set 17"] -pub type SET17_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET17_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET18` writer - Set 18"] -pub type SET18_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET18_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET19` writer - Set 19"] -pub type SET19_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET19_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET20` writer - Set 20"] -pub type SET20_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET20_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET21` writer - Set 21"] -pub type SET21_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET21_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET22` writer - Set 22"] -pub type SET22_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET22_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET23` writer - Set 23"] -pub type SET23_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET23_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET24` writer - Set 24"] -pub type SET24_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET24_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET25` writer - Set 25"] -pub type SET25_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET25_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET26` writer - Set 26"] -pub type SET26_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET26_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET27` writer - Set 27"] -pub type SET27_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET27_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET28` writer - Set 28"] -pub type SET28_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET28_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET29` writer - Set 29"] -pub type SET29_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET29_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET30` writer - Set 30"] -pub type SET30_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET30_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET31` writer - Set 31"] -pub type SET31_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET0_SPEC, bool, O>; +pub type SET31_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - Set 0"] #[inline(always)] #[must_use] - pub fn set0(&mut self) -> SET0_W<0> { + pub fn set0(&mut self) -> SET0_W { SET0_W::new(self) } #[doc = "Bit 1 - Set 1"] #[inline(always)] #[must_use] - pub fn set1(&mut self) -> SET1_W<1> { + pub fn set1(&mut self) -> SET1_W { SET1_W::new(self) } #[doc = "Bit 2 - Set 2"] #[inline(always)] #[must_use] - pub fn set2(&mut self) -> SET2_W<2> { + pub fn set2(&mut self) -> SET2_W { SET2_W::new(self) } #[doc = "Bit 3 - Set 3"] #[inline(always)] #[must_use] - pub fn set3(&mut self) -> SET3_W<3> { + pub fn set3(&mut self) -> SET3_W { SET3_W::new(self) } #[doc = "Bit 4 - Set 4"] #[inline(always)] #[must_use] - pub fn set4(&mut self) -> SET4_W<4> { + pub fn set4(&mut self) -> SET4_W { SET4_W::new(self) } #[doc = "Bit 5 - Set 5"] #[inline(always)] #[must_use] - pub fn set5(&mut self) -> SET5_W<5> { + pub fn set5(&mut self) -> SET5_W { SET5_W::new(self) } #[doc = "Bit 6 - Set 6"] #[inline(always)] #[must_use] - pub fn set6(&mut self) -> SET6_W<6> { + pub fn set6(&mut self) -> SET6_W { SET6_W::new(self) } #[doc = "Bit 7 - Set 7"] #[inline(always)] #[must_use] - pub fn set7(&mut self) -> SET7_W<7> { + pub fn set7(&mut self) -> SET7_W { SET7_W::new(self) } #[doc = "Bit 8 - Set 8"] #[inline(always)] #[must_use] - pub fn set8(&mut self) -> SET8_W<8> { + pub fn set8(&mut self) -> SET8_W { SET8_W::new(self) } #[doc = "Bit 9 - Set 9"] #[inline(always)] #[must_use] - pub fn set9(&mut self) -> SET9_W<9> { + pub fn set9(&mut self) -> SET9_W { SET9_W::new(self) } #[doc = "Bit 10 - Set 10"] #[inline(always)] #[must_use] - pub fn set10(&mut self) -> SET10_W<10> { + pub fn set10(&mut self) -> SET10_W { SET10_W::new(self) } #[doc = "Bit 11 - Set 11"] #[inline(always)] #[must_use] - pub fn set11(&mut self) -> SET11_W<11> { + pub fn set11(&mut self) -> SET11_W { SET11_W::new(self) } #[doc = "Bit 12 - Set 12"] #[inline(always)] #[must_use] - pub fn set12(&mut self) -> SET12_W<12> { + pub fn set12(&mut self) -> SET12_W { SET12_W::new(self) } #[doc = "Bit 13 - Set 13"] #[inline(always)] #[must_use] - pub fn set13(&mut self) -> SET13_W<13> { + pub fn set13(&mut self) -> SET13_W { SET13_W::new(self) } #[doc = "Bit 14 - Set 14"] #[inline(always)] #[must_use] - pub fn set14(&mut self) -> SET14_W<14> { + pub fn set14(&mut self) -> SET14_W { SET14_W::new(self) } #[doc = "Bit 15 - Set 15"] #[inline(always)] #[must_use] - pub fn set15(&mut self) -> SET15_W<15> { + pub fn set15(&mut self) -> SET15_W { SET15_W::new(self) } #[doc = "Bit 16 - Set 16"] #[inline(always)] #[must_use] - pub fn set16(&mut self) -> SET16_W<16> { + pub fn set16(&mut self) -> SET16_W { SET16_W::new(self) } #[doc = "Bit 17 - Set 17"] #[inline(always)] #[must_use] - pub fn set17(&mut self) -> SET17_W<17> { + pub fn set17(&mut self) -> SET17_W { SET17_W::new(self) } #[doc = "Bit 18 - Set 18"] #[inline(always)] #[must_use] - pub fn set18(&mut self) -> SET18_W<18> { + pub fn set18(&mut self) -> SET18_W { SET18_W::new(self) } #[doc = "Bit 19 - Set 19"] #[inline(always)] #[must_use] - pub fn set19(&mut self) -> SET19_W<19> { + pub fn set19(&mut self) -> SET19_W { SET19_W::new(self) } #[doc = "Bit 20 - Set 20"] #[inline(always)] #[must_use] - pub fn set20(&mut self) -> SET20_W<20> { + pub fn set20(&mut self) -> SET20_W { SET20_W::new(self) } #[doc = "Bit 21 - Set 21"] #[inline(always)] #[must_use] - pub fn set21(&mut self) -> SET21_W<21> { + pub fn set21(&mut self) -> SET21_W { SET21_W::new(self) } #[doc = "Bit 22 - Set 22"] #[inline(always)] #[must_use] - pub fn set22(&mut self) -> SET22_W<22> { + pub fn set22(&mut self) -> SET22_W { SET22_W::new(self) } #[doc = "Bit 23 - Set 23"] #[inline(always)] #[must_use] - pub fn set23(&mut self) -> SET23_W<23> { + pub fn set23(&mut self) -> SET23_W { SET23_W::new(self) } #[doc = "Bit 24 - Set 24"] #[inline(always)] #[must_use] - pub fn set24(&mut self) -> SET24_W<24> { + pub fn set24(&mut self) -> SET24_W { SET24_W::new(self) } #[doc = "Bit 25 - Set 25"] #[inline(always)] #[must_use] - pub fn set25(&mut self) -> SET25_W<25> { + pub fn set25(&mut self) -> SET25_W { SET25_W::new(self) } #[doc = "Bit 26 - Set 26"] #[inline(always)] #[must_use] - pub fn set26(&mut self) -> SET26_W<26> { + pub fn set26(&mut self) -> SET26_W { SET26_W::new(self) } #[doc = "Bit 27 - Set 27"] #[inline(always)] #[must_use] - pub fn set27(&mut self) -> SET27_W<27> { + pub fn set27(&mut self) -> SET27_W { SET27_W::new(self) } #[doc = "Bit 28 - Set 28"] #[inline(always)] #[must_use] - pub fn set28(&mut self) -> SET28_W<28> { + pub fn set28(&mut self) -> SET28_W { SET28_W::new(self) } #[doc = "Bit 29 - Set 29"] #[inline(always)] #[must_use] - pub fn set29(&mut self) -> SET29_W<29> { + pub fn set29(&mut self) -> SET29_W { SET29_W::new(self) } #[doc = "Bit 30 - Set 30"] #[inline(always)] #[must_use] - pub fn set30(&mut self) -> SET30_W<30> { + pub fn set30(&mut self) -> SET30_W { SET30_W::new(self) } #[doc = "Bit 31 - Set 31"] #[inline(always)] #[must_use] - pub fn set31(&mut self) -> SET31_W<31> { + pub fn set31(&mut self) -> SET31_W { SET31_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Output Set 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpset0](index.html) module"] +#[doc = "GPIO Pin Output Set 0\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpset0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPSET0_SPEC; impl crate::RegisterSpec for GPSET0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpset0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpset0::W`](W) writer structure"] impl crate::Writable for GPSET0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2837-lpa/src/gpio/gpset1.rs b/crates/bcm2837-lpa/src/gpio/gpset1.rs index 84f73e5..b6b4b3f 100644 --- a/crates/bcm2837-lpa/src/gpio/gpset1.rs +++ b/crates/bcm2837-lpa/src/gpio/gpset1.rs @@ -1,216 +1,205 @@ #[doc = "Register `GPSET1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SET32` writer - Set 32"] -pub type SET32_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET32_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET33` writer - Set 33"] -pub type SET33_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET33_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET34` writer - Set 34"] -pub type SET34_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET34_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET35` writer - Set 35"] -pub type SET35_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET35_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET36` writer - Set 36"] -pub type SET36_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET36_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET37` writer - Set 37"] -pub type SET37_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET37_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET38` writer - Set 38"] -pub type SET38_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET38_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET39` writer - Set 39"] -pub type SET39_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET39_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET40` writer - Set 40"] -pub type SET40_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET40_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET41` writer - Set 41"] -pub type SET41_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET41_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET42` writer - Set 42"] -pub type SET42_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET42_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET43` writer - Set 43"] -pub type SET43_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET43_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET44` writer - Set 44"] -pub type SET44_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET44_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET45` writer - Set 45"] -pub type SET45_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET45_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET46` writer - Set 46"] -pub type SET46_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET46_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET47` writer - Set 47"] -pub type SET47_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET47_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET48` writer - Set 48"] -pub type SET48_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET48_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET49` writer - Set 49"] -pub type SET49_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET49_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET50` writer - Set 50"] -pub type SET50_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET50_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET51` writer - Set 51"] -pub type SET51_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET51_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET52` writer - Set 52"] -pub type SET52_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET52_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SET53` writer - Set 53"] -pub type SET53_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, GPSET1_SPEC, bool, O>; +pub type SET53_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - Set 32"] #[inline(always)] #[must_use] - pub fn set32(&mut self) -> SET32_W<0> { + pub fn set32(&mut self) -> SET32_W { SET32_W::new(self) } #[doc = "Bit 1 - Set 33"] #[inline(always)] #[must_use] - pub fn set33(&mut self) -> SET33_W<1> { + pub fn set33(&mut self) -> SET33_W { SET33_W::new(self) } #[doc = "Bit 2 - Set 34"] #[inline(always)] #[must_use] - pub fn set34(&mut self) -> SET34_W<2> { + pub fn set34(&mut self) -> SET34_W { SET34_W::new(self) } #[doc = "Bit 3 - Set 35"] #[inline(always)] #[must_use] - pub fn set35(&mut self) -> SET35_W<3> { + pub fn set35(&mut self) -> SET35_W { SET35_W::new(self) } #[doc = "Bit 4 - Set 36"] #[inline(always)] #[must_use] - pub fn set36(&mut self) -> SET36_W<4> { + pub fn set36(&mut self) -> SET36_W { SET36_W::new(self) } #[doc = "Bit 5 - Set 37"] #[inline(always)] #[must_use] - pub fn set37(&mut self) -> SET37_W<5> { + pub fn set37(&mut self) -> SET37_W { SET37_W::new(self) } #[doc = "Bit 6 - Set 38"] #[inline(always)] #[must_use] - pub fn set38(&mut self) -> SET38_W<6> { + pub fn set38(&mut self) -> SET38_W { SET38_W::new(self) } #[doc = "Bit 7 - Set 39"] #[inline(always)] #[must_use] - pub fn set39(&mut self) -> SET39_W<7> { + pub fn set39(&mut self) -> SET39_W { SET39_W::new(self) } #[doc = "Bit 8 - Set 40"] #[inline(always)] #[must_use] - pub fn set40(&mut self) -> SET40_W<8> { + pub fn set40(&mut self) -> SET40_W { SET40_W::new(self) } #[doc = "Bit 9 - Set 41"] #[inline(always)] #[must_use] - pub fn set41(&mut self) -> SET41_W<9> { + pub fn set41(&mut self) -> SET41_W { SET41_W::new(self) } #[doc = "Bit 10 - Set 42"] #[inline(always)] #[must_use] - pub fn set42(&mut self) -> SET42_W<10> { + pub fn set42(&mut self) -> SET42_W { SET42_W::new(self) } #[doc = "Bit 11 - Set 43"] #[inline(always)] #[must_use] - pub fn set43(&mut self) -> SET43_W<11> { + pub fn set43(&mut self) -> SET43_W { SET43_W::new(self) } #[doc = "Bit 12 - Set 44"] #[inline(always)] #[must_use] - pub fn set44(&mut self) -> SET44_W<12> { + pub fn set44(&mut self) -> SET44_W { SET44_W::new(self) } #[doc = "Bit 13 - Set 45"] #[inline(always)] #[must_use] - pub fn set45(&mut self) -> SET45_W<13> { + pub fn set45(&mut self) -> SET45_W { SET45_W::new(self) } #[doc = "Bit 14 - Set 46"] #[inline(always)] #[must_use] - pub fn set46(&mut self) -> SET46_W<14> { + pub fn set46(&mut self) -> SET46_W { SET46_W::new(self) } #[doc = "Bit 15 - Set 47"] #[inline(always)] #[must_use] - pub fn set47(&mut self) -> SET47_W<15> { + pub fn set47(&mut self) -> SET47_W { SET47_W::new(self) } #[doc = "Bit 16 - Set 48"] #[inline(always)] #[must_use] - pub fn set48(&mut self) -> SET48_W<16> { + pub fn set48(&mut self) -> SET48_W { SET48_W::new(self) } #[doc = "Bit 17 - Set 49"] #[inline(always)] #[must_use] - pub fn set49(&mut self) -> SET49_W<17> { + pub fn set49(&mut self) -> SET49_W { SET49_W::new(self) } #[doc = "Bit 18 - Set 50"] #[inline(always)] #[must_use] - pub fn set50(&mut self) -> SET50_W<18> { + pub fn set50(&mut self) -> SET50_W { SET50_W::new(self) } #[doc = "Bit 19 - Set 51"] #[inline(always)] #[must_use] - pub fn set51(&mut self) -> SET51_W<19> { + pub fn set51(&mut self) -> SET51_W { SET51_W::new(self) } #[doc = "Bit 20 - Set 52"] #[inline(always)] #[must_use] - pub fn set52(&mut self) -> SET52_W<20> { + pub fn set52(&mut self) -> SET52_W { SET52_W::new(self) } #[doc = "Bit 21 - Set 53"] #[inline(always)] #[must_use] - pub fn set53(&mut self) -> SET53_W<21> { + pub fn set53(&mut self) -> SET53_W { SET53_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GPIO Pin Output Set 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpset1](index.html) module"] +#[doc = "GPIO Pin Output Set 1\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpset1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPSET1_SPEC; impl crate::RegisterSpec for GPSET1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gpset1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gpset1::W`](W) writer structure"] impl crate::Writable for GPSET1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x003f_ffff; } diff --git a/crates/bcm2837-lpa/src/lib.rs b/crates/bcm2837-lpa/src/lib.rs index 2647c5a..d22d75f 100644 --- a/crates/bcm2837-lpa/src/lib.rs +++ b/crates/bcm2837-lpa/src/lib.rs @@ -1,5 +1,5 @@ -#![doc = "Peripheral access API for BCM2837_LPA microcontrollers (generated using svd2rust v0.28.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] -svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.28.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![doc = "Peripheral access API for BCM2837_LPA microcontrollers (generated using svd2rust v0.30.2 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.30.2/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -8,7 +8,8 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] +#![deny(private_bounds)] +#![deny(private_interfaces)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] @@ -41,6 +42,24 @@ impl VCMAILBOX { pub const fn ptr() -> *const vcmailbox::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for VCMAILBOX { type Target = vcmailbox::RegisterBlock; @@ -69,6 +88,24 @@ impl CM_PCM { pub const fn ptr() -> *const cm_pcm::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for CM_PCM { type Target = cm_pcm::RegisterBlock; @@ -97,6 +134,24 @@ impl CM_PWM { pub const fn ptr() -> *const cm_pcm::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for CM_PWM { type Target = cm_pcm::RegisterBlock; @@ -125,6 +180,24 @@ impl GPIO { pub const fn ptr() -> *const gpio::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for GPIO { type Target = gpio::RegisterBlock; @@ -153,6 +226,24 @@ impl SYSTMR { pub const fn ptr() -> *const systmr::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SYSTMR { type Target = systmr::RegisterBlock; @@ -181,6 +272,24 @@ impl UART0 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART0 { type Target = uart0::RegisterBlock; @@ -209,6 +318,24 @@ impl SPI0 { pub const fn ptr() -> *const spi0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI0 { type Target = spi0::RegisterBlock; @@ -237,6 +364,24 @@ impl BSC0 { pub const fn ptr() -> *const bsc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for BSC0 { type Target = bsc0::RegisterBlock; @@ -265,6 +410,24 @@ impl PWM0 { pub const fn ptr() -> *const pwm0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PWM0 { type Target = pwm0::RegisterBlock; @@ -293,6 +456,24 @@ impl BSC1 { pub const fn ptr() -> *const bsc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for BSC1 { type Target = bsc0::RegisterBlock; @@ -321,6 +502,24 @@ impl BSC2 { pub const fn ptr() -> *const bsc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for BSC2 { type Target = bsc0::RegisterBlock; @@ -349,6 +548,24 @@ impl AUX { pub const fn ptr() -> *const aux::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for AUX { type Target = aux::RegisterBlock; @@ -377,6 +594,24 @@ impl UART1 { pub const fn ptr() -> *const uart1::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART1 { type Target = uart1::RegisterBlock; @@ -405,6 +640,24 @@ impl SPI1 { pub const fn ptr() -> *const spi1::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI1 { type Target = spi1::RegisterBlock; @@ -433,6 +686,24 @@ impl SPI2 { pub const fn ptr() -> *const spi1::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI2 { type Target = spi1::RegisterBlock; @@ -461,6 +732,24 @@ impl LIC { pub const fn ptr() -> *const lic::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for LIC { type Target = lic::RegisterBlock; @@ -489,6 +778,24 @@ impl USB_OTG_GLOBAL { pub const fn ptr() -> *const usb_otg_global::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USB_OTG_GLOBAL { type Target = usb_otg_global::RegisterBlock; @@ -517,6 +824,24 @@ impl USB_OTG_HOST { pub const fn ptr() -> *const usb_otg_host::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USB_OTG_HOST { type Target = usb_otg_host::RegisterBlock; @@ -545,6 +870,24 @@ impl USB_OTG_DEVICE { pub const fn ptr() -> *const usb_otg_device::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USB_OTG_DEVICE { type Target = usb_otg_device::RegisterBlock; @@ -573,6 +916,24 @@ impl USB_OTG_PWRCLK { pub const fn ptr() -> *const usb_otg_pwrclk::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USB_OTG_PWRCLK { type Target = usb_otg_pwrclk::RegisterBlock; @@ -601,6 +962,24 @@ impl EMMC { pub const fn ptr() -> *const emmc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for EMMC { type Target = emmc::RegisterBlock; diff --git a/crates/bcm2837-lpa/src/lic.rs b/crates/bcm2837-lpa/src/lic.rs index bc15cd4..36d6423 100644 --- a/crates/bcm2837-lpa/src/lic.rs +++ b/crates/bcm2837-lpa/src/lic.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { _reserved0: [u8; 0x0200], #[doc = "0x200 - Basic pending info"] @@ -23,43 +24,53 @@ pub struct RegisterBlock { #[doc = "0x224 - Disable basic interrupts"] pub disable_basic: DISABLE_BASIC, } -#[doc = "BASIC_PENDING (r) register accessor: an alias for `Reg`"] +#[doc = "BASIC_PENDING (r) register accessor: Basic pending info\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`basic_pending::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@basic_pending`] +module"] pub type BASIC_PENDING = crate::Reg; #[doc = "Basic pending info"] pub mod basic_pending; -#[doc = "PENDING_1 (r) register accessor: an alias for `Reg`"] +#[doc = "PENDING_1 (r) register accessor: Pending state for interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_1`] +module"] pub type PENDING_1 = crate::Reg; #[doc = "Pending state for interrupts 1 - 31"] pub mod pending_1; -#[doc = "PENDING_2 (r) register accessor: an alias for `Reg`"] +#[doc = "PENDING_2 (r) register accessor: Pending state for interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_2`] +module"] pub type PENDING_2 = crate::Reg; #[doc = "Pending state for interrupts 32 - 63"] pub mod pending_2; -#[doc = "FIQ_CONTROL (rw) register accessor: an alias for `Reg`"] +#[doc = "FIQ_CONTROL (rw) register accessor: FIQ control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fiq_control::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fiq_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fiq_control`] +module"] pub type FIQ_CONTROL = crate::Reg; #[doc = "FIQ control"] pub mod fiq_control; -#[doc = "ENABLE_1 (rw) register accessor: an alias for `Reg`"] +#[doc = "ENABLE_1 (rw) register accessor: Enable interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_1`] +module"] pub type ENABLE_1 = crate::Reg; #[doc = "Enable interrupts 1 - 31"] pub mod enable_1; -#[doc = "ENABLE_2 (rw) register accessor: an alias for `Reg`"] +#[doc = "ENABLE_2 (rw) register accessor: Enable interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_2`] +module"] pub type ENABLE_2 = crate::Reg; #[doc = "Enable interrupts 32 - 63"] pub mod enable_2; -#[doc = "ENABLE_BASIC (rw) register accessor: an alias for `Reg`"] +#[doc = "ENABLE_BASIC (rw) register accessor: Enable basic interrupts\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_basic::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_basic::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_basic`] +module"] pub type ENABLE_BASIC = crate::Reg; #[doc = "Enable basic interrupts"] pub mod enable_basic; -#[doc = "DISABLE_1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DISABLE_1 (rw) register accessor: Disable interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@disable_1`] +module"] pub type DISABLE_1 = crate::Reg; #[doc = "Disable interrupts 1 - 31"] pub mod disable_1; -#[doc = "DISABLE_2 (rw) register accessor: an alias for `Reg`"] +#[doc = "DISABLE_2 (rw) register accessor: Disable interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@disable_2`] +module"] pub type DISABLE_2 = crate::Reg; #[doc = "Disable interrupts 32 - 63"] pub mod disable_2; -#[doc = "DISABLE_BASIC (rw) register accessor: an alias for `Reg`"] +#[doc = "DISABLE_BASIC (rw) register accessor: Disable basic interrupts\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_basic::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_basic::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@disable_basic`] +module"] pub type DISABLE_BASIC = crate::Reg; #[doc = "Disable basic interrupts"] pub mod disable_basic; diff --git a/crates/bcm2837-lpa/src/lic/basic_pending.rs b/crates/bcm2837-lpa/src/lic/basic_pending.rs index c7dcea2..a88fcb1 100644 --- a/crates/bcm2837-lpa/src/lic/basic_pending.rs +++ b/crates/bcm2837-lpa/src/lic/basic_pending.rs @@ -1,60 +1,47 @@ #[doc = "Register `BASIC_PENDING` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `PENDING_1` reader - One or more bits are set in PENDING_1 (ignores 7, 9, 10, 18, 19)"] -pub type PENDING_1_R = crate::BitReader; +pub type PENDING_1_R = crate::BitReader; #[doc = "Field `PENDING_2` reader - One or more bits are set in PENDING_2 (ignores 53 - 57, 62)"] -pub type PENDING_2_R = crate::BitReader; +pub type PENDING_2_R = crate::BitReader; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -162,15 +149,51 @@ impl R { EMMC_R::new(((self.bits >> 20) & 1) != 0) } } -#[doc = "Basic pending info\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [basic_pending](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BASIC_PENDING") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .field("pending_1", &format_args!("{}", self.pending_1().bit())) + .field("pending_2", &format_args!("{}", self.pending_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Basic pending info\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`basic_pending::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BASIC_PENDING_SPEC; impl crate::RegisterSpec for BASIC_PENDING_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [basic_pending::R](R) reader structure"] -impl crate::Readable for BASIC_PENDING_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`basic_pending::R`](R) reader structure"] +impl crate::Readable for BASIC_PENDING_SPEC {} #[doc = "`reset()` method sets BASIC_PENDING to value 0"] impl crate::Resettable for BASIC_PENDING_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/lic/disable_1.rs b/crates/bcm2837-lpa/src/lic/disable_1.rs index 5c8027d..efd5fcf 100644 --- a/crates/bcm2837-lpa/src/lic/disable_1.rs +++ b/crates/bcm2837-lpa/src/lic/disable_1.rs @@ -1,167 +1,135 @@ #[doc = "Register `DISABLE_1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DISABLE_1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_1_SPEC, bool, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -324,218 +292,274 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DISABLE_1") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bit 1 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<1> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bit 2 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<2> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bit 3 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<3> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } #[doc = "Bit 4 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<4> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bit 5 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<5> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bit 6 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<6> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bit 7 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<7> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } #[doc = "Bit 8 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<8> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bit 9 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<9> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 10 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<10> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bit 11 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } #[doc = "Bit 12 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bit 13 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bit 14 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bit 15 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } #[doc = "Bit 16 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<16> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bit 17 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<17> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 18 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<18> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 19 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<19> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 20 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<20> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 21 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<21> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 22 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<22> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 23 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } #[doc = "Bit 24 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bit 25 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<25> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bit 26 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<26> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bit 27 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<27> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } #[doc = "Bit 28 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<28> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<29> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bit 30 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<30> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bit 31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<31> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Disable interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_1](index.html) module"] +#[doc = "Disable interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DISABLE_1_SPEC; impl crate::RegisterSpec for DISABLE_1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [disable_1::R](R) reader structure"] -impl crate::Readable for DISABLE_1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [disable_1::W](W) writer structure"] +#[doc = "`read()` method returns [`disable_1::R`](R) reader structure"] +impl crate::Readable for DISABLE_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`disable_1::W`](W) writer structure"] impl crate::Writable for DISABLE_1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2837-lpa/src/lic/disable_2.rs b/crates/bcm2837-lpa/src/lic/disable_2.rs index 9334cf8..05263c3 100644 --- a/crates/bcm2837-lpa/src/lic/disable_2.rs +++ b/crates/bcm2837-lpa/src/lic/disable_2.rs @@ -1,167 +1,135 @@ #[doc = "Register `DISABLE_2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DISABLE_2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type UART_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_2_SPEC, bool, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -324,218 +292,280 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DISABLE_2") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bit 1 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<1> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bit 2 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<2> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bit 3 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<3> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } #[doc = "Bit 4 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<4> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bit 5 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bit 6 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bit 7 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } #[doc = "Bit 8 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bit 9 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bit 10 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bit 11 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } #[doc = "Bit 12 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<12> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bit 13 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bit 15 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<15> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } #[doc = "Bit 16 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<16> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bit 17 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bit 18 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bit 19 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } #[doc = "Bit 20 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bit 21 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<21> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bit 22 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<22> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bit 23 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } #[doc = "Bit 24 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<24> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bit 25 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<25> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bit 26 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bit 27 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<27> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } #[doc = "Bit 28 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<28> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bit 29 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<29> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bit 30 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<30> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bit 31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Disable interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_2](index.html) module"] +#[doc = "Disable interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DISABLE_2_SPEC; impl crate::RegisterSpec for DISABLE_2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [disable_2::R](R) reader structure"] -impl crate::Readable for DISABLE_2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [disable_2::W](W) writer structure"] +#[doc = "`read()` method returns [`disable_2::R`](R) reader structure"] +impl crate::Readable for DISABLE_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`disable_2::W`](W) writer structure"] impl crate::Writable for DISABLE_2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2837-lpa/src/lic/disable_basic.rs b/crates/bcm2837-lpa/src/lic/disable_basic.rs index df73f14..da28ed6 100644 --- a/crates/bcm2837-lpa/src/lic/disable_basic.rs +++ b/crates/bcm2837-lpa/src/lic/disable_basic.rs @@ -1,73 +1,39 @@ #[doc = "Register `DISABLE_BASIC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DISABLE_BASIC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = - crate::BitWriter1C<'a, u32, DISABLE_BASIC_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -110,74 +76,100 @@ impl R { ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DISABLE_BASIC") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Disable basic interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable_basic](index.html) module"] +#[doc = "Disable basic interrupts\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`disable_basic::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`disable_basic::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DISABLE_BASIC_SPEC; impl crate::RegisterSpec for DISABLE_BASIC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [disable_basic::R](R) reader structure"] -impl crate::Readable for DISABLE_BASIC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [disable_basic::W](W) writer structure"] +#[doc = "`read()` method returns [`disable_basic::R`](R) reader structure"] +impl crate::Readable for DISABLE_BASIC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`disable_basic::W`](W) writer structure"] impl crate::Writable for DISABLE_BASIC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; } diff --git a/crates/bcm2837-lpa/src/lic/enable_1.rs b/crates/bcm2837-lpa/src/lic/enable_1.rs index e9aa7ce..d55fb6e 100644 --- a/crates/bcm2837-lpa/src/lic/enable_1.rs +++ b/crates/bcm2837-lpa/src/lic/enable_1.rs @@ -1,167 +1,135 @@ #[doc = "Register `ENABLE_1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ENABLE_1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_0` writer - Timer 0"] -pub type TIMER_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type TIMER_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_1` writer - Timer 1"] -pub type TIMER_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type TIMER_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_2` writer - Timer 2"] -pub type TIMER_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type TIMER_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `TIMER_3` writer - Timer 3"] -pub type TIMER_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type TIMER_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_0` writer - H264 0"] -pub type H264_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type H264_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_1` writer - H264 1"] -pub type H264_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type H264_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `H264_2` writer - H264 2"] -pub type H264_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type H264_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `JPEG` writer - JPEG"] -pub type JPEG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type JPEG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `ISP` writer - ISP"] -pub type ISP_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type ISP_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `USB` writer - USB"] -pub type USB_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type USB_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `V3D` writer - V3D"] -pub type V3D_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type V3D_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `TRANSPOSER` writer - Transposer"] -pub type TRANSPOSER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type TRANSPOSER_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` writer - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` writer - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` writer - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` writer - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type MULTICORE_SYNC_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_0` writer - DMA 0"] -pub type DMA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_1` writer - DMA 1"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_2` writer - DMA 2"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_3` writer - DMA 3"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_4` writer - DMA 4"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_5` writer - DMA 5"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_6` writer - DMA 6"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_7_8` writer - OR of DMA 7 and 8"] -pub type DMA_7_8_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_7_8_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_9_10` writer - OR of DMA 9 and 10"] -pub type DMA_9_10_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_9_10_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_11` writer - DMA 11"] -pub type DMA_11_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_11_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_12` writer - DMA 12"] -pub type DMA_12_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_12_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_13` writer - DMA 13"] -pub type DMA_13_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_13_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `DMA_14` writer - DMA 14"] -pub type DMA_14_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_14_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `AUX` writer - OR of UART1, SPI1 and SPI2"] -pub type AUX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type AUX_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `ARM` writer - ARM"] -pub type ARM_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type ARM_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; #[doc = "Field `DMA_15` writer - DMA 15"] -pub type DMA_15_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_1_SPEC, bool, O>; +pub type DMA_15_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -324,218 +292,274 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLE_1") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Timer 0"] #[inline(always)] #[must_use] - pub fn timer_0(&mut self) -> TIMER_0_W<0> { + pub fn timer_0(&mut self) -> TIMER_0_W { TIMER_0_W::new(self) } #[doc = "Bit 1 - Timer 1"] #[inline(always)] #[must_use] - pub fn timer_1(&mut self) -> TIMER_1_W<1> { + pub fn timer_1(&mut self) -> TIMER_1_W { TIMER_1_W::new(self) } #[doc = "Bit 2 - Timer 2"] #[inline(always)] #[must_use] - pub fn timer_2(&mut self) -> TIMER_2_W<2> { + pub fn timer_2(&mut self) -> TIMER_2_W { TIMER_2_W::new(self) } #[doc = "Bit 3 - Timer 3"] #[inline(always)] #[must_use] - pub fn timer_3(&mut self) -> TIMER_3_W<3> { + pub fn timer_3(&mut self) -> TIMER_3_W { TIMER_3_W::new(self) } #[doc = "Bit 4 - H264 0"] #[inline(always)] #[must_use] - pub fn h264_0(&mut self) -> H264_0_W<4> { + pub fn h264_0(&mut self) -> H264_0_W { H264_0_W::new(self) } #[doc = "Bit 5 - H264 1"] #[inline(always)] #[must_use] - pub fn h264_1(&mut self) -> H264_1_W<5> { + pub fn h264_1(&mut self) -> H264_1_W { H264_1_W::new(self) } #[doc = "Bit 6 - H264 2"] #[inline(always)] #[must_use] - pub fn h264_2(&mut self) -> H264_2_W<6> { + pub fn h264_2(&mut self) -> H264_2_W { H264_2_W::new(self) } #[doc = "Bit 7 - JPEG"] #[inline(always)] #[must_use] - pub fn jpeg(&mut self) -> JPEG_W<7> { + pub fn jpeg(&mut self) -> JPEG_W { JPEG_W::new(self) } #[doc = "Bit 8 - ISP"] #[inline(always)] #[must_use] - pub fn isp(&mut self) -> ISP_W<8> { + pub fn isp(&mut self) -> ISP_W { ISP_W::new(self) } #[doc = "Bit 9 - USB"] #[inline(always)] #[must_use] - pub fn usb(&mut self) -> USB_W<9> { + pub fn usb(&mut self) -> USB_W { USB_W::new(self) } #[doc = "Bit 10 - V3D"] #[inline(always)] #[must_use] - pub fn v3d(&mut self) -> V3D_W<10> { + pub fn v3d(&mut self) -> V3D_W { V3D_W::new(self) } #[doc = "Bit 11 - Transposer"] #[inline(always)] #[must_use] - pub fn transposer(&mut self) -> TRANSPOSER_W<11> { + pub fn transposer(&mut self) -> TRANSPOSER_W { TRANSPOSER_W::new(self) } #[doc = "Bit 12 - Multicore Sync 0"] #[inline(always)] #[must_use] - pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W<12> { + pub fn multicore_sync_0(&mut self) -> MULTICORE_SYNC_0_W { MULTICORE_SYNC_0_W::new(self) } #[doc = "Bit 13 - Multicore Sync 1"] #[inline(always)] #[must_use] - pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W<13> { + pub fn multicore_sync_1(&mut self) -> MULTICORE_SYNC_1_W { MULTICORE_SYNC_1_W::new(self) } #[doc = "Bit 14 - Multicore Sync 2"] #[inline(always)] #[must_use] - pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W<14> { + pub fn multicore_sync_2(&mut self) -> MULTICORE_SYNC_2_W { MULTICORE_SYNC_2_W::new(self) } #[doc = "Bit 15 - Multicore Sync 3"] #[inline(always)] #[must_use] - pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W<15> { + pub fn multicore_sync_3(&mut self) -> MULTICORE_SYNC_3_W { MULTICORE_SYNC_3_W::new(self) } #[doc = "Bit 16 - DMA 0"] #[inline(always)] #[must_use] - pub fn dma_0(&mut self) -> DMA_0_W<16> { + pub fn dma_0(&mut self) -> DMA_0_W { DMA_0_W::new(self) } #[doc = "Bit 17 - DMA 1"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<17> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 18 - DMA 2"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<18> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 19 - DMA 3"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<19> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 20 - DMA 4"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<20> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 21 - DMA 5"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<21> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 22 - DMA 6"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<22> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 23 - OR of DMA 7 and 8"] #[inline(always)] #[must_use] - pub fn dma_7_8(&mut self) -> DMA_7_8_W<23> { + pub fn dma_7_8(&mut self) -> DMA_7_8_W { DMA_7_8_W::new(self) } #[doc = "Bit 24 - OR of DMA 9 and 10"] #[inline(always)] #[must_use] - pub fn dma_9_10(&mut self) -> DMA_9_10_W<24> { + pub fn dma_9_10(&mut self) -> DMA_9_10_W { DMA_9_10_W::new(self) } #[doc = "Bit 25 - DMA 11"] #[inline(always)] #[must_use] - pub fn dma_11(&mut self) -> DMA_11_W<25> { + pub fn dma_11(&mut self) -> DMA_11_W { DMA_11_W::new(self) } #[doc = "Bit 26 - DMA 12"] #[inline(always)] #[must_use] - pub fn dma_12(&mut self) -> DMA_12_W<26> { + pub fn dma_12(&mut self) -> DMA_12_W { DMA_12_W::new(self) } #[doc = "Bit 27 - DMA 13"] #[inline(always)] #[must_use] - pub fn dma_13(&mut self) -> DMA_13_W<27> { + pub fn dma_13(&mut self) -> DMA_13_W { DMA_13_W::new(self) } #[doc = "Bit 28 - DMA 14"] #[inline(always)] #[must_use] - pub fn dma_14(&mut self) -> DMA_14_W<28> { + pub fn dma_14(&mut self) -> DMA_14_W { DMA_14_W::new(self) } #[doc = "Bit 29 - OR of UART1, SPI1 and SPI2"] #[inline(always)] #[must_use] - pub fn aux(&mut self) -> AUX_W<29> { + pub fn aux(&mut self) -> AUX_W { AUX_W::new(self) } #[doc = "Bit 30 - ARM"] #[inline(always)] #[must_use] - pub fn arm(&mut self) -> ARM_W<30> { + pub fn arm(&mut self) -> ARM_W { ARM_W::new(self) } #[doc = "Bit 31 - DMA 15"] #[inline(always)] #[must_use] - pub fn dma_15(&mut self) -> DMA_15_W<31> { + pub fn dma_15(&mut self) -> DMA_15_W { DMA_15_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_1](index.html) module"] +#[doc = "Enable interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLE_1_SPEC; impl crate::RegisterSpec for ENABLE_1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enable_1::R](R) reader structure"] -impl crate::Readable for ENABLE_1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [enable_1::W](W) writer structure"] +#[doc = "`read()` method returns [`enable_1::R`](R) reader structure"] +impl crate::Readable for ENABLE_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enable_1::W`](W) writer structure"] impl crate::Writable for ENABLE_1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2837-lpa/src/lic/enable_2.rs b/crates/bcm2837-lpa/src/lic/enable_2.rs index 45e156d..43769aa 100644 --- a/crates/bcm2837-lpa/src/lic/enable_2.rs +++ b/crates/bcm2837-lpa/src/lic/enable_2.rs @@ -1,167 +1,135 @@ #[doc = "Register `ENABLE_2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ENABLE_2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HDMI_CEC` writer - HDMI CEC"] -pub type HDMI_CEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type HDMI_CEC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `HVS` writer - HVS"] -pub type HVS_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type HVS_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `RPIVID` writer - RPIVID"] -pub type RPIVID_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type RPIVID_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `SDC` writer - SDC"] -pub type SDC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type SDC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `DSI_0` writer - DSI 0"] -pub type DSI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type DSI_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` writer - Pixel Valve 2"] -pub type PIXEL_VALVE_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_0` writer - Camera 0"] -pub type CAMERA_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type CAMERA_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `CAMERA_1` writer - Camera 1"] -pub type CAMERA_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type CAMERA_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_0` writer - HDMI 0"] -pub type HDMI_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type HDMI_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `HDMI_1` writer - HDMI 1"] -pub type HDMI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type HDMI_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` writer - Pixel Valve 3"] -pub type PIXEL_VALVE_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` writer - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type SPI_BSC_SLAVE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `DSI_1` writer - DSI 1"] -pub type DSI_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type DSI_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` writer - Pixel Valve 0"] -pub type PIXEL_VALVE_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` writer - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type PIXEL_VALVE_1_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `CPR` writer - CPR"] -pub type CPR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `SMI` writer - SMI"] -pub type SMI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type SMI_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_0` writer - GPIO 0"] -pub type GPIO_0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type GPIO_0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_1` writer - GPIO 1"] -pub type GPIO_1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type GPIO_1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_2` writer - GPIO 2"] -pub type GPIO_2_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type GPIO_2_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `GPIO_3` writer - GPIO 3"] -pub type GPIO_3_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type GPIO_3_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `I2C` writer - OR of all I2C"] -pub type I2C_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type I2C_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `SPI` writer - OR of all SPI"] -pub type SPI_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type SPI_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `PCM_I2S` writer - PCM/I2S"] -pub type PCM_I2S_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type PCM_I2S_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `SDHOST` writer - SDHOST"] -pub type SDHOST_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type SDHOST_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `UART` writer - OR of all PL011 UARTs"] -pub type UART_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type UART_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `ETH_PCIE` writer - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type ETH_PCIE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `VEC` writer - VEC"] -pub type VEC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type VEC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `CPG` writer - CPG"] -pub type CPG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type CPG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `RNG` writer - RNG"] -pub type RNG_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type RNG_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `EMMC` writer - OR of EMMC and EMMC2"] -pub type EMMC_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type EMMC_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` writer - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_2_SPEC, bool, O>; +pub type ETH_PCIE_SECURE_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -324,218 +292,280 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLE_2") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] #[must_use] - pub fn hdmi_cec(&mut self) -> HDMI_CEC_W<0> { + pub fn hdmi_cec(&mut self) -> HDMI_CEC_W { HDMI_CEC_W::new(self) } #[doc = "Bit 1 - HVS"] #[inline(always)] #[must_use] - pub fn hvs(&mut self) -> HVS_W<1> { + pub fn hvs(&mut self) -> HVS_W { HVS_W::new(self) } #[doc = "Bit 2 - RPIVID"] #[inline(always)] #[must_use] - pub fn rpivid(&mut self) -> RPIVID_W<2> { + pub fn rpivid(&mut self) -> RPIVID_W { RPIVID_W::new(self) } #[doc = "Bit 3 - SDC"] #[inline(always)] #[must_use] - pub fn sdc(&mut self) -> SDC_W<3> { + pub fn sdc(&mut self) -> SDC_W { SDC_W::new(self) } #[doc = "Bit 4 - DSI 0"] #[inline(always)] #[must_use] - pub fn dsi_0(&mut self) -> DSI_0_W<4> { + pub fn dsi_0(&mut self) -> DSI_0_W { DSI_0_W::new(self) } #[doc = "Bit 5 - Pixel Valve 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W<5> { + pub fn pixel_valve_2(&mut self) -> PIXEL_VALVE_2_W { PIXEL_VALVE_2_W::new(self) } #[doc = "Bit 6 - Camera 0"] #[inline(always)] #[must_use] - pub fn camera_0(&mut self) -> CAMERA_0_W<6> { + pub fn camera_0(&mut self) -> CAMERA_0_W { CAMERA_0_W::new(self) } #[doc = "Bit 7 - Camera 1"] #[inline(always)] #[must_use] - pub fn camera_1(&mut self) -> CAMERA_1_W<7> { + pub fn camera_1(&mut self) -> CAMERA_1_W { CAMERA_1_W::new(self) } #[doc = "Bit 8 - HDMI 0"] #[inline(always)] #[must_use] - pub fn hdmi_0(&mut self) -> HDMI_0_W<8> { + pub fn hdmi_0(&mut self) -> HDMI_0_W { HDMI_0_W::new(self) } #[doc = "Bit 9 - HDMI 1"] #[inline(always)] #[must_use] - pub fn hdmi_1(&mut self) -> HDMI_1_W<9> { + pub fn hdmi_1(&mut self) -> HDMI_1_W { HDMI_1_W::new(self) } #[doc = "Bit 10 - Pixel Valve 3"] #[inline(always)] #[must_use] - pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W<10> { + pub fn pixel_valve_3(&mut self) -> PIXEL_VALVE_3_W { PIXEL_VALVE_3_W::new(self) } #[doc = "Bit 11 - SPI/BSC Slave"] #[inline(always)] #[must_use] - pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W<11> { + pub fn spi_bsc_slave(&mut self) -> SPI_BSC_SLAVE_W { SPI_BSC_SLAVE_W::new(self) } #[doc = "Bit 12 - DSI 1"] #[inline(always)] #[must_use] - pub fn dsi_1(&mut self) -> DSI_1_W<12> { + pub fn dsi_1(&mut self) -> DSI_1_W { DSI_1_W::new(self) } #[doc = "Bit 13 - Pixel Valve 0"] #[inline(always)] #[must_use] - pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W<13> { + pub fn pixel_valve_0(&mut self) -> PIXEL_VALVE_0_W { PIXEL_VALVE_0_W::new(self) } #[doc = "Bit 14 - OR of Pixel Valve 1 and 2"] #[inline(always)] #[must_use] - pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W<14> { + pub fn pixel_valve_1_2(&mut self) -> PIXEL_VALVE_1_2_W { PIXEL_VALVE_1_2_W::new(self) } #[doc = "Bit 15 - CPR"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<15> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } #[doc = "Bit 16 - SMI"] #[inline(always)] #[must_use] - pub fn smi(&mut self) -> SMI_W<16> { + pub fn smi(&mut self) -> SMI_W { SMI_W::new(self) } #[doc = "Bit 17 - GPIO 0"] #[inline(always)] #[must_use] - pub fn gpio_0(&mut self) -> GPIO_0_W<17> { + pub fn gpio_0(&mut self) -> GPIO_0_W { GPIO_0_W::new(self) } #[doc = "Bit 18 - GPIO 1"] #[inline(always)] #[must_use] - pub fn gpio_1(&mut self) -> GPIO_1_W<18> { + pub fn gpio_1(&mut self) -> GPIO_1_W { GPIO_1_W::new(self) } #[doc = "Bit 19 - GPIO 2"] #[inline(always)] #[must_use] - pub fn gpio_2(&mut self) -> GPIO_2_W<19> { + pub fn gpio_2(&mut self) -> GPIO_2_W { GPIO_2_W::new(self) } #[doc = "Bit 20 - GPIO 3"] #[inline(always)] #[must_use] - pub fn gpio_3(&mut self) -> GPIO_3_W<20> { + pub fn gpio_3(&mut self) -> GPIO_3_W { GPIO_3_W::new(self) } #[doc = "Bit 21 - OR of all I2C"] #[inline(always)] #[must_use] - pub fn i2c(&mut self) -> I2C_W<21> { + pub fn i2c(&mut self) -> I2C_W { I2C_W::new(self) } #[doc = "Bit 22 - OR of all SPI"] #[inline(always)] #[must_use] - pub fn spi(&mut self) -> SPI_W<22> { + pub fn spi(&mut self) -> SPI_W { SPI_W::new(self) } #[doc = "Bit 23 - PCM/I2S"] #[inline(always)] #[must_use] - pub fn pcm_i2s(&mut self) -> PCM_I2S_W<23> { + pub fn pcm_i2s(&mut self) -> PCM_I2S_W { PCM_I2S_W::new(self) } #[doc = "Bit 24 - SDHOST"] #[inline(always)] #[must_use] - pub fn sdhost(&mut self) -> SDHOST_W<24> { + pub fn sdhost(&mut self) -> SDHOST_W { SDHOST_W::new(self) } #[doc = "Bit 25 - OR of all PL011 UARTs"] #[inline(always)] #[must_use] - pub fn uart(&mut self) -> UART_W<25> { + pub fn uart(&mut self) -> UART_W { UART_W::new(self) } #[doc = "Bit 26 - OR of all ETH_PCIe L2"] #[inline(always)] #[must_use] - pub fn eth_pcie(&mut self) -> ETH_PCIE_W<26> { + pub fn eth_pcie(&mut self) -> ETH_PCIE_W { ETH_PCIE_W::new(self) } #[doc = "Bit 27 - VEC"] #[inline(always)] #[must_use] - pub fn vec(&mut self) -> VEC_W<27> { + pub fn vec(&mut self) -> VEC_W { VEC_W::new(self) } #[doc = "Bit 28 - CPG"] #[inline(always)] #[must_use] - pub fn cpg(&mut self) -> CPG_W<28> { + pub fn cpg(&mut self) -> CPG_W { CPG_W::new(self) } #[doc = "Bit 29 - RNG"] #[inline(always)] #[must_use] - pub fn rng(&mut self) -> RNG_W<29> { + pub fn rng(&mut self) -> RNG_W { RNG_W::new(self) } #[doc = "Bit 30 - OR of EMMC and EMMC2"] #[inline(always)] #[must_use] - pub fn emmc(&mut self) -> EMMC_W<30> { + pub fn emmc(&mut self) -> EMMC_W { EMMC_W::new(self) } #[doc = "Bit 31 - ETH_PCIe secure"] #[inline(always)] #[must_use] - pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W<31> { + pub fn eth_pcie_secure(&mut self) -> ETH_PCIE_SECURE_W { ETH_PCIE_SECURE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_2](index.html) module"] +#[doc = "Enable interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLE_2_SPEC; impl crate::RegisterSpec for ENABLE_2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enable_2::R](R) reader structure"] -impl crate::Readable for ENABLE_2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [enable_2::W](W) writer structure"] +#[doc = "`read()` method returns [`enable_2::R`](R) reader structure"] +impl crate::Readable for ENABLE_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enable_2::W`](W) writer structure"] impl crate::Writable for ENABLE_2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff; } diff --git a/crates/bcm2837-lpa/src/lic/enable_basic.rs b/crates/bcm2837-lpa/src/lic/enable_basic.rs index b401deb..3533529 100644 --- a/crates/bcm2837-lpa/src/lic/enable_basic.rs +++ b/crates/bcm2837-lpa/src/lic/enable_basic.rs @@ -1,72 +1,39 @@ #[doc = "Register `ENABLE_BASIC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ENABLE_BASIC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIMER` reader - ARMC Timer"] -pub type TIMER_R = crate::BitReader; +pub type TIMER_R = crate::BitReader; #[doc = "Field `TIMER` writer - ARMC Timer"] -pub type TIMER_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type TIMER_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `MAILBOX` reader - Mailbox"] -pub type MAILBOX_R = crate::BitReader; +pub type MAILBOX_R = crate::BitReader; #[doc = "Field `MAILBOX` writer - Mailbox"] -pub type MAILBOX_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type MAILBOX_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DOORBELL0` reader - Doorbell 0"] -pub type DOORBELL0_R = crate::BitReader; +pub type DOORBELL0_R = crate::BitReader; #[doc = "Field `DOORBELL0` writer - Doorbell 0"] -pub type DOORBELL0_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type DOORBELL0_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `DOORBELL1` reader - Doorbell 1"] -pub type DOORBELL1_R = crate::BitReader; +pub type DOORBELL1_R = crate::BitReader; #[doc = "Field `DOORBELL1` writer - Doorbell 1"] -pub type DOORBELL1_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type DOORBELL1_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VPU0_HALTED` reader - VPU0 halted"] -pub type VPU0_HALTED_R = crate::BitReader; +pub type VPU0_HALTED_R = crate::BitReader; #[doc = "Field `VPU0_HALTED` writer - VPU0 halted"] -pub type VPU0_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type VPU0_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `VPU1_HALTED` reader - VPU1 halted"] -pub type VPU1_HALTED_R = crate::BitReader; +pub type VPU1_HALTED_R = crate::BitReader; #[doc = "Field `VPU1_HALTED` writer - VPU1 halted"] -pub type VPU1_HALTED_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type VPU1_HALTED_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM_ADDRESS_ERROR` reader - ARM address error"] -pub type ARM_ADDRESS_ERROR_R = crate::BitReader; +pub type ARM_ADDRESS_ERROR_R = crate::BitReader; #[doc = "Field `ARM_ADDRESS_ERROR` writer - ARM address error"] -pub type ARM_ADDRESS_ERROR_W<'a, const O: u8> = - crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type ARM_ADDRESS_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; #[doc = "Field `ARM_AXI_ERROR` reader - ARM AXI error"] -pub type ARM_AXI_ERROR_R = crate::BitReader; +pub type ARM_AXI_ERROR_R = crate::BitReader; #[doc = "Field `ARM_AXI_ERROR` writer - ARM AXI error"] -pub type ARM_AXI_ERROR_W<'a, const O: u8> = crate::BitWriter1S<'a, u32, ENABLE_BASIC_SPEC, bool, O>; +pub type ARM_AXI_ERROR_W<'a, REG, const O: u8> = crate::BitWriter1S<'a, REG, O>; impl R { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] @@ -109,74 +76,100 @@ impl R { ARM_AXI_ERROR_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLE_BASIC") + .field("timer", &format_args!("{}", self.timer().bit())) + .field("mailbox", &format_args!("{}", self.mailbox().bit())) + .field("doorbell0", &format_args!("{}", self.doorbell0().bit())) + .field("doorbell1", &format_args!("{}", self.doorbell1().bit())) + .field("vpu0_halted", &format_args!("{}", self.vpu0_halted().bit())) + .field("vpu1_halted", &format_args!("{}", self.vpu1_halted().bit())) + .field( + "arm_address_error", + &format_args!("{}", self.arm_address_error().bit()), + ) + .field( + "arm_axi_error", + &format_args!("{}", self.arm_axi_error().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - ARMC Timer"] #[inline(always)] #[must_use] - pub fn timer(&mut self) -> TIMER_W<0> { + pub fn timer(&mut self) -> TIMER_W { TIMER_W::new(self) } #[doc = "Bit 1 - Mailbox"] #[inline(always)] #[must_use] - pub fn mailbox(&mut self) -> MAILBOX_W<1> { + pub fn mailbox(&mut self) -> MAILBOX_W { MAILBOX_W::new(self) } #[doc = "Bit 2 - Doorbell 0"] #[inline(always)] #[must_use] - pub fn doorbell0(&mut self) -> DOORBELL0_W<2> { + pub fn doorbell0(&mut self) -> DOORBELL0_W { DOORBELL0_W::new(self) } #[doc = "Bit 3 - Doorbell 1"] #[inline(always)] #[must_use] - pub fn doorbell1(&mut self) -> DOORBELL1_W<3> { + pub fn doorbell1(&mut self) -> DOORBELL1_W { DOORBELL1_W::new(self) } #[doc = "Bit 4 - VPU0 halted"] #[inline(always)] #[must_use] - pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W<4> { + pub fn vpu0_halted(&mut self) -> VPU0_HALTED_W { VPU0_HALTED_W::new(self) } #[doc = "Bit 5 - VPU1 halted"] #[inline(always)] #[must_use] - pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W<5> { + pub fn vpu1_halted(&mut self) -> VPU1_HALTED_W { VPU1_HALTED_W::new(self) } #[doc = "Bit 6 - ARM address error"] #[inline(always)] #[must_use] - pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W<6> { + pub fn arm_address_error(&mut self) -> ARM_ADDRESS_ERROR_W { ARM_ADDRESS_ERROR_W::new(self) } #[doc = "Bit 7 - ARM AXI error"] #[inline(always)] #[must_use] - pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W<7> { + pub fn arm_axi_error(&mut self) -> ARM_AXI_ERROR_W { ARM_AXI_ERROR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Enable basic interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable_basic](index.html) module"] +#[doc = "Enable basic interrupts\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable_basic::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_basic::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLE_BASIC_SPEC; impl crate::RegisterSpec for ENABLE_BASIC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [enable_basic::R](R) reader structure"] -impl crate::Readable for ENABLE_BASIC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [enable_basic::W](W) writer structure"] +#[doc = "`read()` method returns [`enable_basic::R`](R) reader structure"] +impl crate::Readable for ENABLE_BASIC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enable_basic::W`](W) writer structure"] impl crate::Writable for ENABLE_BASIC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xff; } diff --git a/crates/bcm2837-lpa/src/lic/fiq_control.rs b/crates/bcm2837-lpa/src/lic/fiq_control.rs index d1b5d51..e7bc947 100644 --- a/crates/bcm2837-lpa/src/lic/fiq_control.rs +++ b/crates/bcm2837-lpa/src/lic/fiq_control.rs @@ -1,41 +1,9 @@ #[doc = "Register `FIQ_CONTROL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FIQ_CONTROL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SOURCE` reader - FIQ Source"] -pub type SOURCE_R = crate::FieldReader; +pub type SOURCE_R = crate::FieldReader; #[doc = "FIQ Source\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -191,10 +159,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for SOURCE_A { + type Ux = u8; +} impl SOURCE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(SOURCE_A::TIMER_0), 1 => Some(SOURCE_A::TIMER_1), @@ -271,736 +242,739 @@ impl SOURCE_R { _ => None, } } - #[doc = "Checks if the value of the field is `TIMER_0`"] + #[doc = "Timer 0"] #[inline(always)] pub fn is_timer_0(&self) -> bool { *self == SOURCE_A::TIMER_0 } - #[doc = "Checks if the value of the field is `TIMER_1`"] + #[doc = "Timer 1"] #[inline(always)] pub fn is_timer_1(&self) -> bool { *self == SOURCE_A::TIMER_1 } - #[doc = "Checks if the value of the field is `TIMER_2`"] + #[doc = "Timer 2"] #[inline(always)] pub fn is_timer_2(&self) -> bool { *self == SOURCE_A::TIMER_2 } - #[doc = "Checks if the value of the field is `TIMER_3`"] + #[doc = "Timer 3"] #[inline(always)] pub fn is_timer_3(&self) -> bool { *self == SOURCE_A::TIMER_3 } - #[doc = "Checks if the value of the field is `H264_0`"] + #[doc = "H264 0"] #[inline(always)] pub fn is_h264_0(&self) -> bool { *self == SOURCE_A::H264_0 } - #[doc = "Checks if the value of the field is `H264_1`"] + #[doc = "H264 1"] #[inline(always)] pub fn is_h264_1(&self) -> bool { *self == SOURCE_A::H264_1 } - #[doc = "Checks if the value of the field is `H264_2`"] + #[doc = "H264 2"] #[inline(always)] pub fn is_h264_2(&self) -> bool { *self == SOURCE_A::H264_2 } - #[doc = "Checks if the value of the field is `JPEG`"] + #[doc = "JPEG"] #[inline(always)] pub fn is_jpeg(&self) -> bool { *self == SOURCE_A::JPEG } - #[doc = "Checks if the value of the field is `ISP`"] + #[doc = "ISP"] #[inline(always)] pub fn is_isp(&self) -> bool { *self == SOURCE_A::ISP } - #[doc = "Checks if the value of the field is `USB`"] + #[doc = "USB"] #[inline(always)] pub fn is_usb(&self) -> bool { *self == SOURCE_A::USB } - #[doc = "Checks if the value of the field is `V3D`"] + #[doc = "V3D"] #[inline(always)] pub fn is_v3d(&self) -> bool { *self == SOURCE_A::V3D } - #[doc = "Checks if the value of the field is `TRANSPOSER`"] + #[doc = "Transposer"] #[inline(always)] pub fn is_transposer(&self) -> bool { *self == SOURCE_A::TRANSPOSER } - #[doc = "Checks if the value of the field is `MULTICORE_SYNC_0`"] + #[doc = "Multicore Sync 0"] #[inline(always)] pub fn is_multicore_sync_0(&self) -> bool { *self == SOURCE_A::MULTICORE_SYNC_0 } - #[doc = "Checks if the value of the field is `MULTICORE_SYNC_1`"] + #[doc = "Multicore Sync 1"] #[inline(always)] pub fn is_multicore_sync_1(&self) -> bool { *self == SOURCE_A::MULTICORE_SYNC_1 } - #[doc = "Checks if the value of the field is `MULTICORE_SYNC_2`"] + #[doc = "Multicore Sync 2"] #[inline(always)] pub fn is_multicore_sync_2(&self) -> bool { *self == SOURCE_A::MULTICORE_SYNC_2 } - #[doc = "Checks if the value of the field is `MULTICORE_SYNC_3`"] + #[doc = "Multicore Sync 3"] #[inline(always)] pub fn is_multicore_sync_3(&self) -> bool { *self == SOURCE_A::MULTICORE_SYNC_3 } - #[doc = "Checks if the value of the field is `DMA_0`"] + #[doc = "DMA 0"] #[inline(always)] pub fn is_dma_0(&self) -> bool { *self == SOURCE_A::DMA_0 } - #[doc = "Checks if the value of the field is `DMA_1`"] + #[doc = "DMA 1"] #[inline(always)] pub fn is_dma_1(&self) -> bool { *self == SOURCE_A::DMA_1 } - #[doc = "Checks if the value of the field is `DMA_2`"] + #[doc = "DMA 2"] #[inline(always)] pub fn is_dma_2(&self) -> bool { *self == SOURCE_A::DMA_2 } - #[doc = "Checks if the value of the field is `DMA_3`"] + #[doc = "DMA 3"] #[inline(always)] pub fn is_dma_3(&self) -> bool { *self == SOURCE_A::DMA_3 } - #[doc = "Checks if the value of the field is `DMA_4`"] + #[doc = "DMA 4"] #[inline(always)] pub fn is_dma_4(&self) -> bool { *self == SOURCE_A::DMA_4 } - #[doc = "Checks if the value of the field is `DMA_5`"] + #[doc = "DMA 5"] #[inline(always)] pub fn is_dma_5(&self) -> bool { *self == SOURCE_A::DMA_5 } - #[doc = "Checks if the value of the field is `DMA_6`"] + #[doc = "DMA 6"] #[inline(always)] pub fn is_dma_6(&self) -> bool { *self == SOURCE_A::DMA_6 } - #[doc = "Checks if the value of the field is `DMA_7_8`"] + #[doc = "OR of DMA 7 and 8"] #[inline(always)] pub fn is_dma_7_8(&self) -> bool { *self == SOURCE_A::DMA_7_8 } - #[doc = "Checks if the value of the field is `DMA_9_10`"] + #[doc = "OR of DMA 9 and 10"] #[inline(always)] pub fn is_dma_9_10(&self) -> bool { *self == SOURCE_A::DMA_9_10 } - #[doc = "Checks if the value of the field is `DMA_11`"] + #[doc = "DMA 11"] #[inline(always)] pub fn is_dma_11(&self) -> bool { *self == SOURCE_A::DMA_11 } - #[doc = "Checks if the value of the field is `DMA_12`"] + #[doc = "DMA 12"] #[inline(always)] pub fn is_dma_12(&self) -> bool { *self == SOURCE_A::DMA_12 } - #[doc = "Checks if the value of the field is `DMA_13`"] + #[doc = "DMA 13"] #[inline(always)] pub fn is_dma_13(&self) -> bool { *self == SOURCE_A::DMA_13 } - #[doc = "Checks if the value of the field is `DMA_14`"] + #[doc = "DMA 14"] #[inline(always)] pub fn is_dma_14(&self) -> bool { *self == SOURCE_A::DMA_14 } - #[doc = "Checks if the value of the field is `AUX`"] + #[doc = "OR of UART1, SPI1 and SPI2"] #[inline(always)] pub fn is_aux(&self) -> bool { *self == SOURCE_A::AUX } - #[doc = "Checks if the value of the field is `ARM`"] + #[doc = "ARM"] #[inline(always)] pub fn is_arm(&self) -> bool { *self == SOURCE_A::ARM } - #[doc = "Checks if the value of the field is `DMA_15`"] + #[doc = "DMA 15"] #[inline(always)] pub fn is_dma_15(&self) -> bool { *self == SOURCE_A::DMA_15 } - #[doc = "Checks if the value of the field is `HDMI_CEC`"] + #[doc = "HDMI CEC"] #[inline(always)] pub fn is_hdmi_cec(&self) -> bool { *self == SOURCE_A::HDMI_CEC } - #[doc = "Checks if the value of the field is `HVS`"] + #[doc = "HVS"] #[inline(always)] pub fn is_hvs(&self) -> bool { *self == SOURCE_A::HVS } - #[doc = "Checks if the value of the field is `RPIVID`"] + #[doc = "RPIVID"] #[inline(always)] pub fn is_rpivid(&self) -> bool { *self == SOURCE_A::RPIVID } - #[doc = "Checks if the value of the field is `SDC`"] + #[doc = "SDC"] #[inline(always)] pub fn is_sdc(&self) -> bool { *self == SOURCE_A::SDC } - #[doc = "Checks if the value of the field is `DSI_0`"] + #[doc = "DSI 0"] #[inline(always)] pub fn is_dsi_0(&self) -> bool { *self == SOURCE_A::DSI_0 } - #[doc = "Checks if the value of the field is `PIXEL_VALVE_2`"] + #[doc = "Pixel Valve 2"] #[inline(always)] pub fn is_pixel_valve_2(&self) -> bool { *self == SOURCE_A::PIXEL_VALVE_2 } - #[doc = "Checks if the value of the field is `CAMERA_0`"] + #[doc = "Camera 0"] #[inline(always)] pub fn is_camera_0(&self) -> bool { *self == SOURCE_A::CAMERA_0 } - #[doc = "Checks if the value of the field is `CAMERA_1`"] + #[doc = "Camera 1"] #[inline(always)] pub fn is_camera_1(&self) -> bool { *self == SOURCE_A::CAMERA_1 } - #[doc = "Checks if the value of the field is `HDMI_0`"] + #[doc = "HDMI 0"] #[inline(always)] pub fn is_hdmi_0(&self) -> bool { *self == SOURCE_A::HDMI_0 } - #[doc = "Checks if the value of the field is `HDMI_1`"] + #[doc = "HDMI 1"] #[inline(always)] pub fn is_hdmi_1(&self) -> bool { *self == SOURCE_A::HDMI_1 } - #[doc = "Checks if the value of the field is `PIXEL_VALVE_3`"] + #[doc = "Pixel Valve 3"] #[inline(always)] pub fn is_pixel_valve_3(&self) -> bool { *self == SOURCE_A::PIXEL_VALVE_3 } - #[doc = "Checks if the value of the field is `SPI_BSC_SLAVE`"] + #[doc = "SPI/BSC Slave"] #[inline(always)] pub fn is_spi_bsc_slave(&self) -> bool { *self == SOURCE_A::SPI_BSC_SLAVE } - #[doc = "Checks if the value of the field is `DSI_1`"] + #[doc = "DSI 1"] #[inline(always)] pub fn is_dsi_1(&self) -> bool { *self == SOURCE_A::DSI_1 } - #[doc = "Checks if the value of the field is `PIXEL_VALVE_0`"] + #[doc = "Pixel Valve 0"] #[inline(always)] pub fn is_pixel_valve_0(&self) -> bool { *self == SOURCE_A::PIXEL_VALVE_0 } - #[doc = "Checks if the value of the field is `PIXEL_VALVE_1_2`"] + #[doc = "OR of Pixel Valve 1 and 2"] #[inline(always)] pub fn is_pixel_valve_1_2(&self) -> bool { *self == SOURCE_A::PIXEL_VALVE_1_2 } - #[doc = "Checks if the value of the field is `CPR`"] + #[doc = "CPR"] #[inline(always)] pub fn is_cpr(&self) -> bool { *self == SOURCE_A::CPR } - #[doc = "Checks if the value of the field is `SMI`"] + #[doc = "SMI"] #[inline(always)] pub fn is_smi(&self) -> bool { *self == SOURCE_A::SMI } - #[doc = "Checks if the value of the field is `GPIO_0`"] + #[doc = "GPIO 0"] #[inline(always)] pub fn is_gpio_0(&self) -> bool { *self == SOURCE_A::GPIO_0 } - #[doc = "Checks if the value of the field is `GPIO_1`"] + #[doc = "GPIO 1"] #[inline(always)] pub fn is_gpio_1(&self) -> bool { *self == SOURCE_A::GPIO_1 } - #[doc = "Checks if the value of the field is `GPIO_2`"] + #[doc = "GPIO 2"] #[inline(always)] pub fn is_gpio_2(&self) -> bool { *self == SOURCE_A::GPIO_2 } - #[doc = "Checks if the value of the field is `GPIO_3`"] + #[doc = "GPIO 3"] #[inline(always)] pub fn is_gpio_3(&self) -> bool { *self == SOURCE_A::GPIO_3 } - #[doc = "Checks if the value of the field is `I2C`"] + #[doc = "OR of all I2C"] #[inline(always)] pub fn is_i2c(&self) -> bool { *self == SOURCE_A::I2C } - #[doc = "Checks if the value of the field is `SPI`"] + #[doc = "OR of all SPI"] #[inline(always)] pub fn is_spi(&self) -> bool { *self == SOURCE_A::SPI } - #[doc = "Checks if the value of the field is `PCM_I2S`"] + #[doc = "PCM/I2S"] #[inline(always)] pub fn is_pcm_i2s(&self) -> bool { *self == SOURCE_A::PCM_I2S } - #[doc = "Checks if the value of the field is `SDHOST`"] + #[doc = "SDHOST"] #[inline(always)] pub fn is_sdhost(&self) -> bool { *self == SOURCE_A::SDHOST } - #[doc = "Checks if the value of the field is `UART`"] + #[doc = "OR of all PL011 UARTs"] #[inline(always)] pub fn is_uart(&self) -> bool { *self == SOURCE_A::UART } - #[doc = "Checks if the value of the field is `ETH_PCIE`"] + #[doc = "OR of all ETH_PCIe L2"] #[inline(always)] pub fn is_eth_pcie(&self) -> bool { *self == SOURCE_A::ETH_PCIE } - #[doc = "Checks if the value of the field is `VEC`"] + #[doc = "VEC"] #[inline(always)] pub fn is_vec(&self) -> bool { *self == SOURCE_A::VEC } - #[doc = "Checks if the value of the field is `CPG`"] + #[doc = "CPG"] #[inline(always)] pub fn is_cpg(&self) -> bool { *self == SOURCE_A::CPG } - #[doc = "Checks if the value of the field is `RNG`"] + #[doc = "RNG"] #[inline(always)] pub fn is_rng(&self) -> bool { *self == SOURCE_A::RNG } - #[doc = "Checks if the value of the field is `EMMC`"] + #[doc = "OR of EMMC and EMMC2"] #[inline(always)] pub fn is_emmc(&self) -> bool { *self == SOURCE_A::EMMC } - #[doc = "Checks if the value of the field is `ETH_PCIE_SECURE`"] + #[doc = "ETH_PCIe secure"] #[inline(always)] pub fn is_eth_pcie_secure(&self) -> bool { *self == SOURCE_A::ETH_PCIE_SECURE } - #[doc = "Checks if the value of the field is `TIMER`"] + #[doc = "ARMC Timer"] #[inline(always)] pub fn is_timer(&self) -> bool { *self == SOURCE_A::TIMER } - #[doc = "Checks if the value of the field is `MAILBOX`"] + #[doc = "Mailbox"] #[inline(always)] pub fn is_mailbox(&self) -> bool { *self == SOURCE_A::MAILBOX } - #[doc = "Checks if the value of the field is `DOORBELL0`"] + #[doc = "Doorbell 0"] #[inline(always)] pub fn is_doorbell0(&self) -> bool { *self == SOURCE_A::DOORBELL0 } - #[doc = "Checks if the value of the field is `DOORBELL1`"] + #[doc = "Doorbell 1"] #[inline(always)] pub fn is_doorbell1(&self) -> bool { *self == SOURCE_A::DOORBELL1 } - #[doc = "Checks if the value of the field is `VPU0_HALTED`"] + #[doc = "VPU0 halted"] #[inline(always)] pub fn is_vpu0_halted(&self) -> bool { *self == SOURCE_A::VPU0_HALTED } - #[doc = "Checks if the value of the field is `VPU1_HALTED`"] + #[doc = "VPU1 halted"] #[inline(always)] pub fn is_vpu1_halted(&self) -> bool { *self == SOURCE_A::VPU1_HALTED } - #[doc = "Checks if the value of the field is `ARM_ADDRESS_ERROR`"] + #[doc = "ARM address error"] #[inline(always)] pub fn is_arm_address_error(&self) -> bool { *self == SOURCE_A::ARM_ADDRESS_ERROR } - #[doc = "Checks if the value of the field is `ARM_AXI_ERROR`"] + #[doc = "ARM AXI error"] #[inline(always)] pub fn is_arm_axi_error(&self) -> bool { *self == SOURCE_A::ARM_AXI_ERROR } } #[doc = "Field `SOURCE` writer - FIQ Source"] -pub type SOURCE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, FIQ_CONTROL_SPEC, u8, SOURCE_A, 7, O>; -impl<'a, const O: u8> SOURCE_W<'a, O> { +pub type SOURCE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O, SOURCE_A>; +impl<'a, REG, const O: u8> SOURCE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Timer 0"] #[inline(always)] - pub fn timer_0(self) -> &'a mut W { + pub fn timer_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::TIMER_0) } #[doc = "Timer 1"] #[inline(always)] - pub fn timer_1(self) -> &'a mut W { + pub fn timer_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::TIMER_1) } #[doc = "Timer 2"] #[inline(always)] - pub fn timer_2(self) -> &'a mut W { + pub fn timer_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::TIMER_2) } #[doc = "Timer 3"] #[inline(always)] - pub fn timer_3(self) -> &'a mut W { + pub fn timer_3(self) -> &'a mut crate::W { self.variant(SOURCE_A::TIMER_3) } #[doc = "H264 0"] #[inline(always)] - pub fn h264_0(self) -> &'a mut W { + pub fn h264_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::H264_0) } #[doc = "H264 1"] #[inline(always)] - pub fn h264_1(self) -> &'a mut W { + pub fn h264_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::H264_1) } #[doc = "H264 2"] #[inline(always)] - pub fn h264_2(self) -> &'a mut W { + pub fn h264_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::H264_2) } #[doc = "JPEG"] #[inline(always)] - pub fn jpeg(self) -> &'a mut W { + pub fn jpeg(self) -> &'a mut crate::W { self.variant(SOURCE_A::JPEG) } #[doc = "ISP"] #[inline(always)] - pub fn isp(self) -> &'a mut W { + pub fn isp(self) -> &'a mut crate::W { self.variant(SOURCE_A::ISP) } #[doc = "USB"] #[inline(always)] - pub fn usb(self) -> &'a mut W { + pub fn usb(self) -> &'a mut crate::W { self.variant(SOURCE_A::USB) } #[doc = "V3D"] #[inline(always)] - pub fn v3d(self) -> &'a mut W { + pub fn v3d(self) -> &'a mut crate::W { self.variant(SOURCE_A::V3D) } #[doc = "Transposer"] #[inline(always)] - pub fn transposer(self) -> &'a mut W { + pub fn transposer(self) -> &'a mut crate::W { self.variant(SOURCE_A::TRANSPOSER) } #[doc = "Multicore Sync 0"] #[inline(always)] - pub fn multicore_sync_0(self) -> &'a mut W { + pub fn multicore_sync_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::MULTICORE_SYNC_0) } #[doc = "Multicore Sync 1"] #[inline(always)] - pub fn multicore_sync_1(self) -> &'a mut W { + pub fn multicore_sync_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::MULTICORE_SYNC_1) } #[doc = "Multicore Sync 2"] #[inline(always)] - pub fn multicore_sync_2(self) -> &'a mut W { + pub fn multicore_sync_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::MULTICORE_SYNC_2) } #[doc = "Multicore Sync 3"] #[inline(always)] - pub fn multicore_sync_3(self) -> &'a mut W { + pub fn multicore_sync_3(self) -> &'a mut crate::W { self.variant(SOURCE_A::MULTICORE_SYNC_3) } #[doc = "DMA 0"] #[inline(always)] - pub fn dma_0(self) -> &'a mut W { + pub fn dma_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_0) } #[doc = "DMA 1"] #[inline(always)] - pub fn dma_1(self) -> &'a mut W { + pub fn dma_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_1) } #[doc = "DMA 2"] #[inline(always)] - pub fn dma_2(self) -> &'a mut W { + pub fn dma_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_2) } #[doc = "DMA 3"] #[inline(always)] - pub fn dma_3(self) -> &'a mut W { + pub fn dma_3(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_3) } #[doc = "DMA 4"] #[inline(always)] - pub fn dma_4(self) -> &'a mut W { + pub fn dma_4(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_4) } #[doc = "DMA 5"] #[inline(always)] - pub fn dma_5(self) -> &'a mut W { + pub fn dma_5(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_5) } #[doc = "DMA 6"] #[inline(always)] - pub fn dma_6(self) -> &'a mut W { + pub fn dma_6(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_6) } #[doc = "OR of DMA 7 and 8"] #[inline(always)] - pub fn dma_7_8(self) -> &'a mut W { + pub fn dma_7_8(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_7_8) } #[doc = "OR of DMA 9 and 10"] #[inline(always)] - pub fn dma_9_10(self) -> &'a mut W { + pub fn dma_9_10(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_9_10) } #[doc = "DMA 11"] #[inline(always)] - pub fn dma_11(self) -> &'a mut W { + pub fn dma_11(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_11) } #[doc = "DMA 12"] #[inline(always)] - pub fn dma_12(self) -> &'a mut W { + pub fn dma_12(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_12) } #[doc = "DMA 13"] #[inline(always)] - pub fn dma_13(self) -> &'a mut W { + pub fn dma_13(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_13) } #[doc = "DMA 14"] #[inline(always)] - pub fn dma_14(self) -> &'a mut W { + pub fn dma_14(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_14) } #[doc = "OR of UART1, SPI1 and SPI2"] #[inline(always)] - pub fn aux(self) -> &'a mut W { + pub fn aux(self) -> &'a mut crate::W { self.variant(SOURCE_A::AUX) } #[doc = "ARM"] #[inline(always)] - pub fn arm(self) -> &'a mut W { + pub fn arm(self) -> &'a mut crate::W { self.variant(SOURCE_A::ARM) } #[doc = "DMA 15"] #[inline(always)] - pub fn dma_15(self) -> &'a mut W { + pub fn dma_15(self) -> &'a mut crate::W { self.variant(SOURCE_A::DMA_15) } #[doc = "HDMI CEC"] #[inline(always)] - pub fn hdmi_cec(self) -> &'a mut W { + pub fn hdmi_cec(self) -> &'a mut crate::W { self.variant(SOURCE_A::HDMI_CEC) } #[doc = "HVS"] #[inline(always)] - pub fn hvs(self) -> &'a mut W { + pub fn hvs(self) -> &'a mut crate::W { self.variant(SOURCE_A::HVS) } #[doc = "RPIVID"] #[inline(always)] - pub fn rpivid(self) -> &'a mut W { + pub fn rpivid(self) -> &'a mut crate::W { self.variant(SOURCE_A::RPIVID) } #[doc = "SDC"] #[inline(always)] - pub fn sdc(self) -> &'a mut W { + pub fn sdc(self) -> &'a mut crate::W { self.variant(SOURCE_A::SDC) } #[doc = "DSI 0"] #[inline(always)] - pub fn dsi_0(self) -> &'a mut W { + pub fn dsi_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::DSI_0) } #[doc = "Pixel Valve 2"] #[inline(always)] - pub fn pixel_valve_2(self) -> &'a mut W { + pub fn pixel_valve_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::PIXEL_VALVE_2) } #[doc = "Camera 0"] #[inline(always)] - pub fn camera_0(self) -> &'a mut W { + pub fn camera_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::CAMERA_0) } #[doc = "Camera 1"] #[inline(always)] - pub fn camera_1(self) -> &'a mut W { + pub fn camera_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::CAMERA_1) } #[doc = "HDMI 0"] #[inline(always)] - pub fn hdmi_0(self) -> &'a mut W { + pub fn hdmi_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::HDMI_0) } #[doc = "HDMI 1"] #[inline(always)] - pub fn hdmi_1(self) -> &'a mut W { + pub fn hdmi_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::HDMI_1) } #[doc = "Pixel Valve 3"] #[inline(always)] - pub fn pixel_valve_3(self) -> &'a mut W { + pub fn pixel_valve_3(self) -> &'a mut crate::W { self.variant(SOURCE_A::PIXEL_VALVE_3) } #[doc = "SPI/BSC Slave"] #[inline(always)] - pub fn spi_bsc_slave(self) -> &'a mut W { + pub fn spi_bsc_slave(self) -> &'a mut crate::W { self.variant(SOURCE_A::SPI_BSC_SLAVE) } #[doc = "DSI 1"] #[inline(always)] - pub fn dsi_1(self) -> &'a mut W { + pub fn dsi_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::DSI_1) } #[doc = "Pixel Valve 0"] #[inline(always)] - pub fn pixel_valve_0(self) -> &'a mut W { + pub fn pixel_valve_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::PIXEL_VALVE_0) } #[doc = "OR of Pixel Valve 1 and 2"] #[inline(always)] - pub fn pixel_valve_1_2(self) -> &'a mut W { + pub fn pixel_valve_1_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::PIXEL_VALVE_1_2) } #[doc = "CPR"] #[inline(always)] - pub fn cpr(self) -> &'a mut W { + pub fn cpr(self) -> &'a mut crate::W { self.variant(SOURCE_A::CPR) } #[doc = "SMI"] #[inline(always)] - pub fn smi(self) -> &'a mut W { + pub fn smi(self) -> &'a mut crate::W { self.variant(SOURCE_A::SMI) } #[doc = "GPIO 0"] #[inline(always)] - pub fn gpio_0(self) -> &'a mut W { + pub fn gpio_0(self) -> &'a mut crate::W { self.variant(SOURCE_A::GPIO_0) } #[doc = "GPIO 1"] #[inline(always)] - pub fn gpio_1(self) -> &'a mut W { + pub fn gpio_1(self) -> &'a mut crate::W { self.variant(SOURCE_A::GPIO_1) } #[doc = "GPIO 2"] #[inline(always)] - pub fn gpio_2(self) -> &'a mut W { + pub fn gpio_2(self) -> &'a mut crate::W { self.variant(SOURCE_A::GPIO_2) } #[doc = "GPIO 3"] #[inline(always)] - pub fn gpio_3(self) -> &'a mut W { + pub fn gpio_3(self) -> &'a mut crate::W { self.variant(SOURCE_A::GPIO_3) } #[doc = "OR of all I2C"] #[inline(always)] - pub fn i2c(self) -> &'a mut W { + pub fn i2c(self) -> &'a mut crate::W { self.variant(SOURCE_A::I2C) } #[doc = "OR of all SPI"] #[inline(always)] - pub fn spi(self) -> &'a mut W { + pub fn spi(self) -> &'a mut crate::W { self.variant(SOURCE_A::SPI) } #[doc = "PCM/I2S"] #[inline(always)] - pub fn pcm_i2s(self) -> &'a mut W { + pub fn pcm_i2s(self) -> &'a mut crate::W { self.variant(SOURCE_A::PCM_I2S) } #[doc = "SDHOST"] #[inline(always)] - pub fn sdhost(self) -> &'a mut W { + pub fn sdhost(self) -> &'a mut crate::W { self.variant(SOURCE_A::SDHOST) } #[doc = "OR of all PL011 UARTs"] #[inline(always)] - pub fn uart(self) -> &'a mut W { + pub fn uart(self) -> &'a mut crate::W { self.variant(SOURCE_A::UART) } #[doc = "OR of all ETH_PCIe L2"] #[inline(always)] - pub fn eth_pcie(self) -> &'a mut W { + pub fn eth_pcie(self) -> &'a mut crate::W { self.variant(SOURCE_A::ETH_PCIE) } #[doc = "VEC"] #[inline(always)] - pub fn vec(self) -> &'a mut W { + pub fn vec(self) -> &'a mut crate::W { self.variant(SOURCE_A::VEC) } #[doc = "CPG"] #[inline(always)] - pub fn cpg(self) -> &'a mut W { + pub fn cpg(self) -> &'a mut crate::W { self.variant(SOURCE_A::CPG) } #[doc = "RNG"] #[inline(always)] - pub fn rng(self) -> &'a mut W { + pub fn rng(self) -> &'a mut crate::W { self.variant(SOURCE_A::RNG) } #[doc = "OR of EMMC and EMMC2"] #[inline(always)] - pub fn emmc(self) -> &'a mut W { + pub fn emmc(self) -> &'a mut crate::W { self.variant(SOURCE_A::EMMC) } #[doc = "ETH_PCIe secure"] #[inline(always)] - pub fn eth_pcie_secure(self) -> &'a mut W { + pub fn eth_pcie_secure(self) -> &'a mut crate::W { self.variant(SOURCE_A::ETH_PCIE_SECURE) } #[doc = "ARMC Timer"] #[inline(always)] - pub fn timer(self) -> &'a mut W { + pub fn timer(self) -> &'a mut crate::W { self.variant(SOURCE_A::TIMER) } #[doc = "Mailbox"] #[inline(always)] - pub fn mailbox(self) -> &'a mut W { + pub fn mailbox(self) -> &'a mut crate::W { self.variant(SOURCE_A::MAILBOX) } #[doc = "Doorbell 0"] #[inline(always)] - pub fn doorbell0(self) -> &'a mut W { + pub fn doorbell0(self) -> &'a mut crate::W { self.variant(SOURCE_A::DOORBELL0) } #[doc = "Doorbell 1"] #[inline(always)] - pub fn doorbell1(self) -> &'a mut W { + pub fn doorbell1(self) -> &'a mut crate::W { self.variant(SOURCE_A::DOORBELL1) } #[doc = "VPU0 halted"] #[inline(always)] - pub fn vpu0_halted(self) -> &'a mut W { + pub fn vpu0_halted(self) -> &'a mut crate::W { self.variant(SOURCE_A::VPU0_HALTED) } #[doc = "VPU1 halted"] #[inline(always)] - pub fn vpu1_halted(self) -> &'a mut W { + pub fn vpu1_halted(self) -> &'a mut crate::W { self.variant(SOURCE_A::VPU1_HALTED) } #[doc = "ARM address error"] #[inline(always)] - pub fn arm_address_error(self) -> &'a mut W { + pub fn arm_address_error(self) -> &'a mut crate::W { self.variant(SOURCE_A::ARM_ADDRESS_ERROR) } #[doc = "ARM AXI error"] #[inline(always)] - pub fn arm_axi_error(self) -> &'a mut W { + pub fn arm_axi_error(self) -> &'a mut crate::W { self.variant(SOURCE_A::ARM_AXI_ERROR) } } #[doc = "Field `ENABLE` reader - FIQ Enable"] -pub type ENABLE_R = crate::BitReader; +pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - FIQ Enable"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIQ_CONTROL_SPEC, bool, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - FIQ Source"] #[inline(always)] @@ -1013,38 +987,52 @@ impl R { ENABLE_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIQ_CONTROL") + .field("enable", &format_args!("{}", self.enable().bit())) + .field("source", &format_args!("{}", self.source().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - FIQ Source"] #[inline(always)] #[must_use] - pub fn source(&mut self) -> SOURCE_W<0> { + pub fn source(&mut self) -> SOURCE_W { SOURCE_W::new(self) } #[doc = "Bit 7 - FIQ Enable"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<7> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "FIQ control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fiq_control](index.html) module"] +#[doc = "FIQ control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fiq_control::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fiq_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIQ_CONTROL_SPEC; impl crate::RegisterSpec for FIQ_CONTROL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fiq_control::R](R) reader structure"] -impl crate::Readable for FIQ_CONTROL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fiq_control::W](W) writer structure"] +#[doc = "`read()` method returns [`fiq_control::R`](R) reader structure"] +impl crate::Readable for FIQ_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fiq_control::W`](W) writer structure"] impl crate::Writable for FIQ_CONTROL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/lic/pending_1.rs b/crates/bcm2837-lpa/src/lic/pending_1.rs index e4ae642..8c9286e 100644 --- a/crates/bcm2837-lpa/src/lic/pending_1.rs +++ b/crates/bcm2837-lpa/src/lic/pending_1.rs @@ -1,82 +1,69 @@ #[doc = "Register `PENDING_1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TIMER_0` reader - Timer 0"] -pub type TIMER_0_R = crate::BitReader; +pub type TIMER_0_R = crate::BitReader; #[doc = "Field `TIMER_1` reader - Timer 1"] -pub type TIMER_1_R = crate::BitReader; +pub type TIMER_1_R = crate::BitReader; #[doc = "Field `TIMER_2` reader - Timer 2"] -pub type TIMER_2_R = crate::BitReader; +pub type TIMER_2_R = crate::BitReader; #[doc = "Field `TIMER_3` reader - Timer 3"] -pub type TIMER_3_R = crate::BitReader; +pub type TIMER_3_R = crate::BitReader; #[doc = "Field `H264_0` reader - H264 0"] -pub type H264_0_R = crate::BitReader; +pub type H264_0_R = crate::BitReader; #[doc = "Field `H264_1` reader - H264 1"] -pub type H264_1_R = crate::BitReader; +pub type H264_1_R = crate::BitReader; #[doc = "Field `H264_2` reader - H264 2"] -pub type H264_2_R = crate::BitReader; +pub type H264_2_R = crate::BitReader; #[doc = "Field `JPEG` reader - JPEG"] -pub type JPEG_R = crate::BitReader; +pub type JPEG_R = crate::BitReader; #[doc = "Field `ISP` reader - ISP"] -pub type ISP_R = crate::BitReader; +pub type ISP_R = crate::BitReader; #[doc = "Field `USB` reader - USB"] -pub type USB_R = crate::BitReader; +pub type USB_R = crate::BitReader; #[doc = "Field `V3D` reader - V3D"] -pub type V3D_R = crate::BitReader; +pub type V3D_R = crate::BitReader; #[doc = "Field `TRANSPOSER` reader - Transposer"] -pub type TRANSPOSER_R = crate::BitReader; +pub type TRANSPOSER_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_0` reader - Multicore Sync 0"] -pub type MULTICORE_SYNC_0_R = crate::BitReader; +pub type MULTICORE_SYNC_0_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_1` reader - Multicore Sync 1"] -pub type MULTICORE_SYNC_1_R = crate::BitReader; +pub type MULTICORE_SYNC_1_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_2` reader - Multicore Sync 2"] -pub type MULTICORE_SYNC_2_R = crate::BitReader; +pub type MULTICORE_SYNC_2_R = crate::BitReader; #[doc = "Field `MULTICORE_SYNC_3` reader - Multicore Sync 3"] -pub type MULTICORE_SYNC_3_R = crate::BitReader; +pub type MULTICORE_SYNC_3_R = crate::BitReader; #[doc = "Field `DMA_0` reader - DMA 0"] -pub type DMA_0_R = crate::BitReader; +pub type DMA_0_R = crate::BitReader; #[doc = "Field `DMA_1` reader - DMA 1"] -pub type DMA_1_R = crate::BitReader; +pub type DMA_1_R = crate::BitReader; #[doc = "Field `DMA_2` reader - DMA 2"] -pub type DMA_2_R = crate::BitReader; +pub type DMA_2_R = crate::BitReader; #[doc = "Field `DMA_3` reader - DMA 3"] -pub type DMA_3_R = crate::BitReader; +pub type DMA_3_R = crate::BitReader; #[doc = "Field `DMA_4` reader - DMA 4"] -pub type DMA_4_R = crate::BitReader; +pub type DMA_4_R = crate::BitReader; #[doc = "Field `DMA_5` reader - DMA 5"] -pub type DMA_5_R = crate::BitReader; +pub type DMA_5_R = crate::BitReader; #[doc = "Field `DMA_6` reader - DMA 6"] -pub type DMA_6_R = crate::BitReader; +pub type DMA_6_R = crate::BitReader; #[doc = "Field `DMA_7_8` reader - OR of DMA 7 and 8"] -pub type DMA_7_8_R = crate::BitReader; +pub type DMA_7_8_R = crate::BitReader; #[doc = "Field `DMA_9_10` reader - OR of DMA 9 and 10"] -pub type DMA_9_10_R = crate::BitReader; +pub type DMA_9_10_R = crate::BitReader; #[doc = "Field `DMA_11` reader - DMA 11"] -pub type DMA_11_R = crate::BitReader; +pub type DMA_11_R = crate::BitReader; #[doc = "Field `DMA_12` reader - DMA 12"] -pub type DMA_12_R = crate::BitReader; +pub type DMA_12_R = crate::BitReader; #[doc = "Field `DMA_13` reader - DMA 13"] -pub type DMA_13_R = crate::BitReader; +pub type DMA_13_R = crate::BitReader; #[doc = "Field `DMA_14` reader - DMA 14"] -pub type DMA_14_R = crate::BitReader; +pub type DMA_14_R = crate::BitReader; #[doc = "Field `AUX` reader - OR of UART1, SPI1 and SPI2"] -pub type AUX_R = crate::BitReader; +pub type AUX_R = crate::BitReader; #[doc = "Field `ARM` reader - ARM"] -pub type ARM_R = crate::BitReader; +pub type ARM_R = crate::BitReader; #[doc = "Field `DMA_15` reader - DMA 15"] -pub type DMA_15_R = crate::BitReader; +pub type DMA_15_R = crate::BitReader; impl R { #[doc = "Bit 0 - Timer 0"] #[inline(always)] @@ -239,15 +226,68 @@ impl R { DMA_15_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Pending state for interrupts 1 - 31\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending_1](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PENDING_1") + .field("timer_0", &format_args!("{}", self.timer_0().bit())) + .field("timer_1", &format_args!("{}", self.timer_1().bit())) + .field("timer_2", &format_args!("{}", self.timer_2().bit())) + .field("timer_3", &format_args!("{}", self.timer_3().bit())) + .field("h264_0", &format_args!("{}", self.h264_0().bit())) + .field("h264_1", &format_args!("{}", self.h264_1().bit())) + .field("h264_2", &format_args!("{}", self.h264_2().bit())) + .field("jpeg", &format_args!("{}", self.jpeg().bit())) + .field("isp", &format_args!("{}", self.isp().bit())) + .field("usb", &format_args!("{}", self.usb().bit())) + .field("v3d", &format_args!("{}", self.v3d().bit())) + .field("transposer", &format_args!("{}", self.transposer().bit())) + .field( + "multicore_sync_0", + &format_args!("{}", self.multicore_sync_0().bit()), + ) + .field( + "multicore_sync_1", + &format_args!("{}", self.multicore_sync_1().bit()), + ) + .field( + "multicore_sync_2", + &format_args!("{}", self.multicore_sync_2().bit()), + ) + .field( + "multicore_sync_3", + &format_args!("{}", self.multicore_sync_3().bit()), + ) + .field("dma_0", &format_args!("{}", self.dma_0().bit())) + .field("dma_1", &format_args!("{}", self.dma_1().bit())) + .field("dma_2", &format_args!("{}", self.dma_2().bit())) + .field("dma_3", &format_args!("{}", self.dma_3().bit())) + .field("dma_4", &format_args!("{}", self.dma_4().bit())) + .field("dma_5", &format_args!("{}", self.dma_5().bit())) + .field("dma_6", &format_args!("{}", self.dma_6().bit())) + .field("dma_7_8", &format_args!("{}", self.dma_7_8().bit())) + .field("dma_9_10", &format_args!("{}", self.dma_9_10().bit())) + .field("dma_11", &format_args!("{}", self.dma_11().bit())) + .field("dma_12", &format_args!("{}", self.dma_12().bit())) + .field("dma_13", &format_args!("{}", self.dma_13().bit())) + .field("dma_14", &format_args!("{}", self.dma_14().bit())) + .field("aux", &format_args!("{}", self.aux().bit())) + .field("arm", &format_args!("{}", self.arm().bit())) + .field("dma_15", &format_args!("{}", self.dma_15().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Pending state for interrupts 1 - 31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PENDING_1_SPEC; impl crate::RegisterSpec for PENDING_1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pending_1::R](R) reader structure"] -impl crate::Readable for PENDING_1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pending_1::R`](R) reader structure"] +impl crate::Readable for PENDING_1_SPEC {} #[doc = "`reset()` method sets PENDING_1 to value 0"] impl crate::Resettable for PENDING_1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/lic/pending_2.rs b/crates/bcm2837-lpa/src/lic/pending_2.rs index f9a32c7..fcd18af 100644 --- a/crates/bcm2837-lpa/src/lic/pending_2.rs +++ b/crates/bcm2837-lpa/src/lic/pending_2.rs @@ -1,82 +1,69 @@ #[doc = "Register `PENDING_2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `HDMI_CEC` reader - HDMI CEC"] -pub type HDMI_CEC_R = crate::BitReader; +pub type HDMI_CEC_R = crate::BitReader; #[doc = "Field `HVS` reader - HVS"] -pub type HVS_R = crate::BitReader; +pub type HVS_R = crate::BitReader; #[doc = "Field `RPIVID` reader - RPIVID"] -pub type RPIVID_R = crate::BitReader; +pub type RPIVID_R = crate::BitReader; #[doc = "Field `SDC` reader - SDC"] -pub type SDC_R = crate::BitReader; +pub type SDC_R = crate::BitReader; #[doc = "Field `DSI_0` reader - DSI 0"] -pub type DSI_0_R = crate::BitReader; +pub type DSI_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_2` reader - Pixel Valve 2"] -pub type PIXEL_VALVE_2_R = crate::BitReader; +pub type PIXEL_VALVE_2_R = crate::BitReader; #[doc = "Field `CAMERA_0` reader - Camera 0"] -pub type CAMERA_0_R = crate::BitReader; +pub type CAMERA_0_R = crate::BitReader; #[doc = "Field `CAMERA_1` reader - Camera 1"] -pub type CAMERA_1_R = crate::BitReader; +pub type CAMERA_1_R = crate::BitReader; #[doc = "Field `HDMI_0` reader - HDMI 0"] -pub type HDMI_0_R = crate::BitReader; +pub type HDMI_0_R = crate::BitReader; #[doc = "Field `HDMI_1` reader - HDMI 1"] -pub type HDMI_1_R = crate::BitReader; +pub type HDMI_1_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_3` reader - Pixel Valve 3"] -pub type PIXEL_VALVE_3_R = crate::BitReader; +pub type PIXEL_VALVE_3_R = crate::BitReader; #[doc = "Field `SPI_BSC_SLAVE` reader - SPI/BSC Slave"] -pub type SPI_BSC_SLAVE_R = crate::BitReader; +pub type SPI_BSC_SLAVE_R = crate::BitReader; #[doc = "Field `DSI_1` reader - DSI 1"] -pub type DSI_1_R = crate::BitReader; +pub type DSI_1_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_0` reader - Pixel Valve 0"] -pub type PIXEL_VALVE_0_R = crate::BitReader; +pub type PIXEL_VALVE_0_R = crate::BitReader; #[doc = "Field `PIXEL_VALVE_1_2` reader - OR of Pixel Valve 1 and 2"] -pub type PIXEL_VALVE_1_2_R = crate::BitReader; +pub type PIXEL_VALVE_1_2_R = crate::BitReader; #[doc = "Field `CPR` reader - CPR"] -pub type CPR_R = crate::BitReader; +pub type CPR_R = crate::BitReader; #[doc = "Field `SMI` reader - SMI"] -pub type SMI_R = crate::BitReader; +pub type SMI_R = crate::BitReader; #[doc = "Field `GPIO_0` reader - GPIO 0"] -pub type GPIO_0_R = crate::BitReader; +pub type GPIO_0_R = crate::BitReader; #[doc = "Field `GPIO_1` reader - GPIO 1"] -pub type GPIO_1_R = crate::BitReader; +pub type GPIO_1_R = crate::BitReader; #[doc = "Field `GPIO_2` reader - GPIO 2"] -pub type GPIO_2_R = crate::BitReader; +pub type GPIO_2_R = crate::BitReader; #[doc = "Field `GPIO_3` reader - GPIO 3"] -pub type GPIO_3_R = crate::BitReader; +pub type GPIO_3_R = crate::BitReader; #[doc = "Field `I2C` reader - OR of all I2C"] -pub type I2C_R = crate::BitReader; +pub type I2C_R = crate::BitReader; #[doc = "Field `SPI` reader - OR of all SPI"] -pub type SPI_R = crate::BitReader; +pub type SPI_R = crate::BitReader; #[doc = "Field `PCM_I2S` reader - PCM/I2S"] -pub type PCM_I2S_R = crate::BitReader; +pub type PCM_I2S_R = crate::BitReader; #[doc = "Field `SDHOST` reader - SDHOST"] -pub type SDHOST_R = crate::BitReader; +pub type SDHOST_R = crate::BitReader; #[doc = "Field `UART` reader - OR of all PL011 UARTs"] -pub type UART_R = crate::BitReader; +pub type UART_R = crate::BitReader; #[doc = "Field `ETH_PCIE` reader - OR of all ETH_PCIe L2"] -pub type ETH_PCIE_R = crate::BitReader; +pub type ETH_PCIE_R = crate::BitReader; #[doc = "Field `VEC` reader - VEC"] -pub type VEC_R = crate::BitReader; +pub type VEC_R = crate::BitReader; #[doc = "Field `CPG` reader - CPG"] -pub type CPG_R = crate::BitReader; +pub type CPG_R = crate::BitReader; #[doc = "Field `RNG` reader - RNG"] -pub type RNG_R = crate::BitReader; +pub type RNG_R = crate::BitReader; #[doc = "Field `EMMC` reader - OR of EMMC and EMMC2"] -pub type EMMC_R = crate::BitReader; +pub type EMMC_R = crate::BitReader; #[doc = "Field `ETH_PCIE_SECURE` reader - ETH_PCIe secure"] -pub type ETH_PCIE_SECURE_R = crate::BitReader; +pub type ETH_PCIE_SECURE_R = crate::BitReader; impl R { #[doc = "Bit 0 - HDMI CEC"] #[inline(always)] @@ -239,15 +226,74 @@ impl R { ETH_PCIE_SECURE_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Pending state for interrupts 32 - 63\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pending_2](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PENDING_2") + .field("hdmi_cec", &format_args!("{}", self.hdmi_cec().bit())) + .field("hvs", &format_args!("{}", self.hvs().bit())) + .field("rpivid", &format_args!("{}", self.rpivid().bit())) + .field("sdc", &format_args!("{}", self.sdc().bit())) + .field("dsi_0", &format_args!("{}", self.dsi_0().bit())) + .field( + "pixel_valve_2", + &format_args!("{}", self.pixel_valve_2().bit()), + ) + .field("camera_0", &format_args!("{}", self.camera_0().bit())) + .field("camera_1", &format_args!("{}", self.camera_1().bit())) + .field("hdmi_0", &format_args!("{}", self.hdmi_0().bit())) + .field("hdmi_1", &format_args!("{}", self.hdmi_1().bit())) + .field( + "pixel_valve_3", + &format_args!("{}", self.pixel_valve_3().bit()), + ) + .field( + "spi_bsc_slave", + &format_args!("{}", self.spi_bsc_slave().bit()), + ) + .field("dsi_1", &format_args!("{}", self.dsi_1().bit())) + .field( + "pixel_valve_0", + &format_args!("{}", self.pixel_valve_0().bit()), + ) + .field( + "pixel_valve_1_2", + &format_args!("{}", self.pixel_valve_1_2().bit()), + ) + .field("cpr", &format_args!("{}", self.cpr().bit())) + .field("smi", &format_args!("{}", self.smi().bit())) + .field("gpio_0", &format_args!("{}", self.gpio_0().bit())) + .field("gpio_1", &format_args!("{}", self.gpio_1().bit())) + .field("gpio_2", &format_args!("{}", self.gpio_2().bit())) + .field("gpio_3", &format_args!("{}", self.gpio_3().bit())) + .field("i2c", &format_args!("{}", self.i2c().bit())) + .field("spi", &format_args!("{}", self.spi().bit())) + .field("pcm_i2s", &format_args!("{}", self.pcm_i2s().bit())) + .field("sdhost", &format_args!("{}", self.sdhost().bit())) + .field("uart", &format_args!("{}", self.uart().bit())) + .field("eth_pcie", &format_args!("{}", self.eth_pcie().bit())) + .field("vec", &format_args!("{}", self.vec().bit())) + .field("cpg", &format_args!("{}", self.cpg().bit())) + .field("rng", &format_args!("{}", self.rng().bit())) + .field("emmc", &format_args!("{}", self.emmc().bit())) + .field( + "eth_pcie_secure", + &format_args!("{}", self.eth_pcie_secure().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Pending state for interrupts 32 - 63\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PENDING_2_SPEC; impl crate::RegisterSpec for PENDING_2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pending_2::R](R) reader structure"] -impl crate::Readable for PENDING_2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pending_2::R`](R) reader structure"] +impl crate::Readable for PENDING_2_SPEC {} #[doc = "`reset()` method sets PENDING_2 to value 0"] impl crate::Resettable for PENDING_2_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/pwm0.rs b/crates/bcm2837-lpa/src/pwm0.rs index 4270433..4306916 100644 --- a/crates/bcm2837-lpa/src/pwm0.rs +++ b/crates/bcm2837-lpa/src/pwm0.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control"] pub ctl: CTL, @@ -20,35 +21,43 @@ pub struct RegisterBlock { #[doc = "0x24 - Channel 2 data"] pub dat2: DAT2, } -#[doc = "CTL (rw) register accessor: an alias for `Reg`"] +#[doc = "CTL (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl`] +module"] pub type CTL = crate::Reg; #[doc = "Control"] pub mod ctl; -#[doc = "STA (rw) register accessor: an alias for `Reg`"] +#[doc = "STA (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sta`] +module"] pub type STA = crate::Reg; #[doc = "Status"] pub mod sta; -#[doc = "DMAC (rw) register accessor: an alias for `Reg`"] +#[doc = "DMAC (rw) register accessor: DMA control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmac::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmac::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac`] +module"] pub type DMAC = crate::Reg; #[doc = "DMA control"] pub mod dmac; -#[doc = "RNG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "RNG1 (rw) register accessor: Range for channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rng1`] +module"] pub type RNG1 = crate::Reg; #[doc = "Range for channel 1"] pub mod rng1; -#[doc = "DAT1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DAT1 (rw) register accessor: Channel 1 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dat1`] +module"] pub type DAT1 = crate::Reg; #[doc = "Channel 1 data"] pub mod dat1; -#[doc = "FIF1 (w) register accessor: an alias for `Reg`"] +#[doc = "FIF1 (w) register accessor: FIFO input\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fif1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fif1`] +module"] pub type FIF1 = crate::Reg; #[doc = "FIFO input"] pub mod fif1; -#[doc = "RNG2 (rw) register accessor: an alias for `Reg`"] +#[doc = "RNG2 (rw) register accessor: Range for channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rng2`] +module"] pub type RNG2 = crate::Reg; #[doc = "Range for channel 2"] pub mod rng2; -#[doc = "DAT2 (rw) register accessor: an alias for `Reg`"] +#[doc = "DAT2 (rw) register accessor: Channel 2 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dat2`] +module"] pub type DAT2 = crate::Reg; #[doc = "Channel 2 data"] pub mod dat2; diff --git a/crates/bcm2837-lpa/src/pwm0/ctl.rs b/crates/bcm2837-lpa/src/pwm0/ctl.rs index b41b326..d1b9d57 100644 --- a/crates/bcm2837-lpa/src/pwm0/ctl.rs +++ b/crates/bcm2837-lpa/src/pwm0/ctl.rs @@ -1,43 +1,11 @@ #[doc = "Register `CTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PWEN1` reader - Enable channel 1"] -pub type PWEN1_R = crate::BitReader; +pub type PWEN1_R = crate::BitReader; #[doc = "Field `PWEN1` writer - Enable channel 1"] -pub type PWEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type PWEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MODE1` reader - Channel 1 mode"] pub type MODE1_R = crate::BitReader; #[doc = "Channel 1 mode\n\nValue on reset: 0"] @@ -57,65 +25,68 @@ impl From for bool { impl MODE1_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> MODE1_A { + pub const fn variant(&self) -> MODE1_A { match self.bits { false => MODE1_A::PWM, true => MODE1_A::SERIAL, } } - #[doc = "Checks if the value of the field is `PWM`"] + #[doc = "`0`"] #[inline(always)] pub fn is_pwm(&self) -> bool { *self == MODE1_A::PWM } - #[doc = "Checks if the value of the field is `SERIAL`"] + #[doc = "`1`"] #[inline(always)] pub fn is_serial(&self) -> bool { *self == MODE1_A::SERIAL } } #[doc = "Field `MODE1` writer - Channel 1 mode"] -pub type MODE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, MODE1_A, O>; -impl<'a, const O: u8> MODE1_W<'a, O> { +pub type MODE1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MODE1_A>; +impl<'a, REG, const O: u8> MODE1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn pwm(self) -> &'a mut W { + pub fn pwm(self) -> &'a mut crate::W { self.variant(MODE1_A::PWM) } #[doc = "`1`"] #[inline(always)] - pub fn serial(self) -> &'a mut W { + pub fn serial(self) -> &'a mut crate::W { self.variant(MODE1_A::SERIAL) } } #[doc = "Field `RPTL1` reader - Repeat last value from FIFO for channel 1"] -pub type RPTL1_R = crate::BitReader; +pub type RPTL1_R = crate::BitReader; #[doc = "Field `RPTL1` writer - Repeat last value from FIFO for channel 1"] -pub type RPTL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type RPTL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SBIT1` reader - State when not transmitting on channel 1"] -pub type SBIT1_R = crate::BitReader; +pub type SBIT1_R = crate::BitReader; #[doc = "Field `SBIT1` writer - State when not transmitting on channel 1"] -pub type SBIT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type SBIT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POLA1` reader - Channel 1 polarity inverted"] -pub type POLA1_R = crate::BitReader; +pub type POLA1_R = crate::BitReader; #[doc = "Field `POLA1` writer - Channel 1 polarity inverted"] -pub type POLA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type POLA1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USEF1` reader - Use FIFO for channel 1"] -pub type USEF1_R = crate::BitReader; +pub type USEF1_R = crate::BitReader; #[doc = "Field `USEF1` writer - Use FIFO for channel 1"] -pub type USEF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type USEF1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLRF1` reader - Clear FIFO"] -pub type CLRF1_R = crate::BitReader; +pub type CLRF1_R = crate::BitReader; #[doc = "Field `CLRF1` writer - Clear FIFO"] -pub type CLRF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type CLRF1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSEN1` reader - M/S mode for channel 1"] -pub type MSEN1_R = crate::BitReader; +pub type MSEN1_R = crate::BitReader; #[doc = "Field `MSEN1` writer - M/S mode for channel 1"] -pub type MSEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type MSEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWEN2` reader - Enable channel 2"] -pub type PWEN2_R = crate::BitReader; +pub type PWEN2_R = crate::BitReader; #[doc = "Field `PWEN2` writer - Enable channel 2"] -pub type PWEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type PWEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MODE2` reader - Channel 2 mode"] pub type MODE2_R = crate::BitReader; #[doc = "Channel 2 mode\n\nValue on reset: 0"] @@ -135,57 +106,60 @@ impl From for bool { impl MODE2_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> MODE2_A { + pub const fn variant(&self) -> MODE2_A { match self.bits { false => MODE2_A::PWM, true => MODE2_A::SERIAL, } } - #[doc = "Checks if the value of the field is `PWM`"] + #[doc = "`0`"] #[inline(always)] pub fn is_pwm(&self) -> bool { *self == MODE2_A::PWM } - #[doc = "Checks if the value of the field is `SERIAL`"] + #[doc = "`1`"] #[inline(always)] pub fn is_serial(&self) -> bool { *self == MODE2_A::SERIAL } } #[doc = "Field `MODE2` writer - Channel 2 mode"] -pub type MODE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, MODE2_A, O>; -impl<'a, const O: u8> MODE2_W<'a, O> { +pub type MODE2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MODE2_A>; +impl<'a, REG, const O: u8> MODE2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn pwm(self) -> &'a mut W { + pub fn pwm(self) -> &'a mut crate::W { self.variant(MODE2_A::PWM) } #[doc = "`1`"] #[inline(always)] - pub fn serial(self) -> &'a mut W { + pub fn serial(self) -> &'a mut crate::W { self.variant(MODE2_A::SERIAL) } } #[doc = "Field `RPTL2` reader - Repeat last value from FIFO for channel 2"] -pub type RPTL2_R = crate::BitReader; +pub type RPTL2_R = crate::BitReader; #[doc = "Field `RPTL2` writer - Repeat last value from FIFO for channel 2"] -pub type RPTL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type RPTL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SBIT2` reader - State when not transmitting on channel 2"] -pub type SBIT2_R = crate::BitReader; +pub type SBIT2_R = crate::BitReader; #[doc = "Field `SBIT2` writer - State when not transmitting on channel 2"] -pub type SBIT2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type SBIT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POLA2` reader - Channel 2 polarity inverted"] -pub type POLA2_R = crate::BitReader; +pub type POLA2_R = crate::BitReader; #[doc = "Field `POLA2` writer - Channel 2 polarity inverted"] -pub type POLA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type POLA2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USEF2` reader - Use FIFO for channel 2"] -pub type USEF2_R = crate::BitReader; +pub type USEF2_R = crate::BitReader; #[doc = "Field `USEF2` writer - Use FIFO for channel 2"] -pub type USEF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type USEF2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSEN2` reader - M/S mode for channel 2"] -pub type MSEN2_R = crate::BitReader; +pub type MSEN2_R = crate::BitReader; #[doc = "Field `MSEN2` writer - M/S mode for channel 2"] -pub type MSEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, bool, O>; +pub type MSEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable channel 1"] #[inline(always)] @@ -263,116 +237,143 @@ impl R { MSEN2_R::new(((self.bits >> 15) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTL") + .field("msen2", &format_args!("{}", self.msen2().bit())) + .field("usef2", &format_args!("{}", self.usef2().bit())) + .field("pola2", &format_args!("{}", self.pola2().bit())) + .field("sbit2", &format_args!("{}", self.sbit2().bit())) + .field("rptl2", &format_args!("{}", self.rptl2().bit())) + .field("mode2", &format_args!("{}", self.mode2().bit())) + .field("pwen2", &format_args!("{}", self.pwen2().bit())) + .field("msen1", &format_args!("{}", self.msen1().bit())) + .field("clrf1", &format_args!("{}", self.clrf1().bit())) + .field("usef1", &format_args!("{}", self.usef1().bit())) + .field("pola1", &format_args!("{}", self.pola1().bit())) + .field("sbit1", &format_args!("{}", self.sbit1().bit())) + .field("rptl1", &format_args!("{}", self.rptl1().bit())) + .field("mode1", &format_args!("{}", self.mode1().bit())) + .field("pwen1", &format_args!("{}", self.pwen1().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable channel 1"] #[inline(always)] #[must_use] - pub fn pwen1(&mut self) -> PWEN1_W<0> { + pub fn pwen1(&mut self) -> PWEN1_W { PWEN1_W::new(self) } #[doc = "Bit 1 - Channel 1 mode"] #[inline(always)] #[must_use] - pub fn mode1(&mut self) -> MODE1_W<1> { + pub fn mode1(&mut self) -> MODE1_W { MODE1_W::new(self) } #[doc = "Bit 2 - Repeat last value from FIFO for channel 1"] #[inline(always)] #[must_use] - pub fn rptl1(&mut self) -> RPTL1_W<2> { + pub fn rptl1(&mut self) -> RPTL1_W { RPTL1_W::new(self) } #[doc = "Bit 3 - State when not transmitting on channel 1"] #[inline(always)] #[must_use] - pub fn sbit1(&mut self) -> SBIT1_W<3> { + pub fn sbit1(&mut self) -> SBIT1_W { SBIT1_W::new(self) } #[doc = "Bit 4 - Channel 1 polarity inverted"] #[inline(always)] #[must_use] - pub fn pola1(&mut self) -> POLA1_W<4> { + pub fn pola1(&mut self) -> POLA1_W { POLA1_W::new(self) } #[doc = "Bit 5 - Use FIFO for channel 1"] #[inline(always)] #[must_use] - pub fn usef1(&mut self) -> USEF1_W<5> { + pub fn usef1(&mut self) -> USEF1_W { USEF1_W::new(self) } #[doc = "Bit 6 - Clear FIFO"] #[inline(always)] #[must_use] - pub fn clrf1(&mut self) -> CLRF1_W<6> { + pub fn clrf1(&mut self) -> CLRF1_W { CLRF1_W::new(self) } #[doc = "Bit 7 - M/S mode for channel 1"] #[inline(always)] #[must_use] - pub fn msen1(&mut self) -> MSEN1_W<7> { + pub fn msen1(&mut self) -> MSEN1_W { MSEN1_W::new(self) } #[doc = "Bit 8 - Enable channel 2"] #[inline(always)] #[must_use] - pub fn pwen2(&mut self) -> PWEN2_W<8> { + pub fn pwen2(&mut self) -> PWEN2_W { PWEN2_W::new(self) } #[doc = "Bit 9 - Channel 2 mode"] #[inline(always)] #[must_use] - pub fn mode2(&mut self) -> MODE2_W<9> { + pub fn mode2(&mut self) -> MODE2_W { MODE2_W::new(self) } #[doc = "Bit 10 - Repeat last value from FIFO for channel 2"] #[inline(always)] #[must_use] - pub fn rptl2(&mut self) -> RPTL2_W<10> { + pub fn rptl2(&mut self) -> RPTL2_W { RPTL2_W::new(self) } #[doc = "Bit 11 - State when not transmitting on channel 2"] #[inline(always)] #[must_use] - pub fn sbit2(&mut self) -> SBIT2_W<11> { + pub fn sbit2(&mut self) -> SBIT2_W { SBIT2_W::new(self) } #[doc = "Bit 12 - Channel 2 polarity inverted"] #[inline(always)] #[must_use] - pub fn pola2(&mut self) -> POLA2_W<12> { + pub fn pola2(&mut self) -> POLA2_W { POLA2_W::new(self) } #[doc = "Bit 13 - Use FIFO for channel 2"] #[inline(always)] #[must_use] - pub fn usef2(&mut self) -> USEF2_W<13> { + pub fn usef2(&mut self) -> USEF2_W { USEF2_W::new(self) } #[doc = "Bit 15 - M/S mode for channel 2"] #[inline(always)] #[must_use] - pub fn msen2(&mut self) -> MSEN2_W<15> { + pub fn msen2(&mut self) -> MSEN2_W { MSEN2_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTL_SPEC; impl crate::RegisterSpec for CTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctl::R](R) reader structure"] -impl crate::Readable for CTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctl::W](W) writer structure"] +#[doc = "`read()` method returns [`ctl::R`](R) reader structure"] +impl crate::Readable for CTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"] impl crate::Writable for CTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/pwm0/dat1.rs b/crates/bcm2837-lpa/src/pwm0/dat1.rs index c197492..b70672a 100644 --- a/crates/bcm2837-lpa/src/pwm0/dat1.rs +++ b/crates/bcm2837-lpa/src/pwm0/dat1.rs @@ -1,59 +1,38 @@ #[doc = "Register `DAT1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DAT1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel 1 data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dat1](index.html) module"] +#[doc = "Channel 1 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DAT1_SPEC; impl crate::RegisterSpec for DAT1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dat1::R](R) reader structure"] -impl crate::Readable for DAT1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dat1::W](W) writer structure"] +#[doc = "`read()` method returns [`dat1::R`](R) reader structure"] +impl crate::Readable for DAT1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dat1::W`](W) writer structure"] impl crate::Writable for DAT1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/pwm0/dat2.rs b/crates/bcm2837-lpa/src/pwm0/dat2.rs index b9e07a3..00bb85f 100644 --- a/crates/bcm2837-lpa/src/pwm0/dat2.rs +++ b/crates/bcm2837-lpa/src/pwm0/dat2.rs @@ -1,59 +1,38 @@ #[doc = "Register `DAT2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DAT2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel 2 data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dat2](index.html) module"] +#[doc = "Channel 2 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DAT2_SPEC; impl crate::RegisterSpec for DAT2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dat2::R](R) reader structure"] -impl crate::Readable for DAT2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dat2::W](W) writer structure"] +#[doc = "`read()` method returns [`dat2::R`](R) reader structure"] +impl crate::Readable for DAT2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dat2::W`](W) writer structure"] impl crate::Writable for DAT2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/pwm0/dmac.rs b/crates/bcm2837-lpa/src/pwm0/dmac.rs index b201822..d73ccfd 100644 --- a/crates/bcm2837-lpa/src/pwm0/dmac.rs +++ b/crates/bcm2837-lpa/src/pwm0/dmac.rs @@ -1,51 +1,19 @@ #[doc = "Register `DMAC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMAC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DREQ` reader - DMA threshold for DREQ signal"] -pub type DREQ_R = crate::FieldReader; +pub type DREQ_R = crate::FieldReader; #[doc = "Field `DREQ` writer - DMA threshold for DREQ signal"] -pub type DREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAC_SPEC, u8, u8, 8, O>; +pub type DREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PANIC` reader - DMA threshold for panic signal"] -pub type PANIC_R = crate::FieldReader; +pub type PANIC_R = crate::FieldReader; #[doc = "Field `PANIC` writer - DMA threshold for panic signal"] -pub type PANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAC_SPEC, u8, u8, 8, O>; +pub type PANIC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ENAB` reader - DMA enabled"] -pub type ENAB_R = crate::BitReader; +pub type ENAB_R = crate::BitReader; #[doc = "Field `ENAB` writer - DMA enabled"] -pub type ENAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAC_SPEC, bool, O>; +pub type ENAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:7 - DMA threshold for DREQ signal"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { ENAB_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC") + .field("enab", &format_args!("{}", self.enab().bit())) + .field("panic", &format_args!("{}", self.panic().bits())) + .field("dreq", &format_args!("{}", self.dreq().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DMA threshold for DREQ signal"] #[inline(always)] #[must_use] - pub fn dreq(&mut self) -> DREQ_W<0> { + pub fn dreq(&mut self) -> DREQ_W { DREQ_W::new(self) } #[doc = "Bits 8:15 - DMA threshold for panic signal"] #[inline(always)] #[must_use] - pub fn panic(&mut self) -> PANIC_W<8> { + pub fn panic(&mut self) -> PANIC_W { PANIC_W::new(self) } #[doc = "Bit 31 - DMA enabled"] #[inline(always)] #[must_use] - pub fn enab(&mut self) -> ENAB_W<31> { + pub fn enab(&mut self) -> ENAB_W { ENAB_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmac](index.html) module"] +#[doc = "DMA control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmac::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmac::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMAC_SPEC; impl crate::RegisterSpec for DMAC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dmac::R](R) reader structure"] -impl crate::Readable for DMAC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dmac::W](W) writer structure"] +#[doc = "`read()` method returns [`dmac::R`](R) reader structure"] +impl crate::Readable for DMAC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dmac::W`](W) writer structure"] impl crate::Writable for DMAC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/pwm0/fif1.rs b/crates/bcm2837-lpa/src/pwm0/fif1.rs index e786328..9cf85c2 100644 --- a/crates/bcm2837-lpa/src/pwm0/fif1.rs +++ b/crates/bcm2837-lpa/src/pwm0/fif1.rs @@ -1,40 +1,29 @@ #[doc = "Register `FIF1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +pub type W = crate::W; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "FIFO input\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fif1](index.html) module"] +#[doc = "FIFO input\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fif1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIF1_SPEC; impl crate::RegisterSpec for FIF1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [fif1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`fif1::W`](W) writer structure"] impl crate::Writable for FIF1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/pwm0/rng1.rs b/crates/bcm2837-lpa/src/pwm0/rng1.rs index b6f5446..2a01d68 100644 --- a/crates/bcm2837-lpa/src/pwm0/rng1.rs +++ b/crates/bcm2837-lpa/src/pwm0/rng1.rs @@ -1,59 +1,38 @@ #[doc = "Register `RNG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RNG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Range for channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rng1](index.html) module"] +#[doc = "Range for channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RNG1_SPEC; impl crate::RegisterSpec for RNG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rng1::R](R) reader structure"] -impl crate::Readable for RNG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rng1::W](W) writer structure"] +#[doc = "`read()` method returns [`rng1::R`](R) reader structure"] +impl crate::Readable for RNG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng1::W`](W) writer structure"] impl crate::Writable for RNG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/pwm0/rng2.rs b/crates/bcm2837-lpa/src/pwm0/rng2.rs index 0cc95d5..c7a9f74 100644 --- a/crates/bcm2837-lpa/src/pwm0/rng2.rs +++ b/crates/bcm2837-lpa/src/pwm0/rng2.rs @@ -1,59 +1,38 @@ #[doc = "Register `RNG2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RNG2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Range for channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rng2](index.html) module"] +#[doc = "Range for channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RNG2_SPEC; impl crate::RegisterSpec for RNG2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rng2::R](R) reader structure"] -impl crate::Readable for RNG2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rng2::W](W) writer structure"] +#[doc = "`read()` method returns [`rng2::R`](R) reader structure"] +impl crate::Readable for RNG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng2::W`](W) writer structure"] impl crate::Writable for RNG2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/pwm0/sta.rs b/crates/bcm2837-lpa/src/pwm0/sta.rs index f0b99b7..a0076a9 100644 --- a/crates/bcm2837-lpa/src/pwm0/sta.rs +++ b/crates/bcm2837-lpa/src/pwm0/sta.rs @@ -1,91 +1,59 @@ #[doc = "Register `STA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FULL1` reader - FIFO full"] -pub type FULL1_R = crate::BitReader; +pub type FULL1_R = crate::BitReader; #[doc = "Field `FULL1` writer - FIFO full"] -pub type FULL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type FULL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EMPT1` reader - FIFO empty"] -pub type EMPT1_R = crate::BitReader; +pub type EMPT1_R = crate::BitReader; #[doc = "Field `EMPT1` writer - FIFO empty"] -pub type EMPT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type EMPT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WERR1` reader - FIFO write error"] -pub type WERR1_R = crate::BitReader; +pub type WERR1_R = crate::BitReader; #[doc = "Field `WERR1` writer - FIFO write error"] -pub type WERR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type WERR1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RERR1` reader - FIFO read error"] -pub type RERR1_R = crate::BitReader; +pub type RERR1_R = crate::BitReader; #[doc = "Field `RERR1` writer - FIFO read error"] -pub type RERR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type RERR1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAPO1` reader - Channel 1 gap occurred"] -pub type GAPO1_R = crate::BitReader; +pub type GAPO1_R = crate::BitReader; #[doc = "Field `GAPO1` writer - Channel 1 gap occurred"] -pub type GAPO1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type GAPO1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAPO2` reader - Channel 2 gap occurred"] -pub type GAPO2_R = crate::BitReader; +pub type GAPO2_R = crate::BitReader; #[doc = "Field `GAPO2` writer - Channel 2 gap occurred"] -pub type GAPO2_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type GAPO2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAPO3` reader - Channel 3 gap occurred"] -pub type GAPO3_R = crate::BitReader; +pub type GAPO3_R = crate::BitReader; #[doc = "Field `GAPO3` writer - Channel 3 gap occurred"] -pub type GAPO3_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type GAPO3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GAPO4` reader - Channel 4 gap occurred"] -pub type GAPO4_R = crate::BitReader; +pub type GAPO4_R = crate::BitReader; #[doc = "Field `GAPO4` writer - Channel 4 gap occurred"] -pub type GAPO4_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type GAPO4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BERR` reader - Bus error"] -pub type BERR_R = crate::BitReader; +pub type BERR_R = crate::BitReader; #[doc = "Field `BERR` writer - Bus error"] -pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type BERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STA1` reader - Channel 1 state"] -pub type STA1_R = crate::BitReader; +pub type STA1_R = crate::BitReader; #[doc = "Field `STA1` writer - Channel 1 state"] -pub type STA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type STA1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STA2` reader - Channel 2 state"] -pub type STA2_R = crate::BitReader; +pub type STA2_R = crate::BitReader; #[doc = "Field `STA2` writer - Channel 2 state"] -pub type STA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type STA2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STA3` reader - Channel 3 state"] -pub type STA3_R = crate::BitReader; +pub type STA3_R = crate::BitReader; #[doc = "Field `STA3` writer - Channel 3 state"] -pub type STA3_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type STA3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STA4` reader - Channel 4 state"] -pub type STA4_R = crate::BitReader; +pub type STA4_R = crate::BitReader; #[doc = "Field `STA4` writer - Channel 4 state"] -pub type STA4_W<'a, const O: u8> = crate::BitWriter<'a, u32, STA_SPEC, bool, O>; +pub type STA4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - FIFO full"] #[inline(always)] @@ -153,104 +121,129 @@ impl R { STA4_R::new(((self.bits >> 12) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STA") + .field("sta4", &format_args!("{}", self.sta4().bit())) + .field("sta3", &format_args!("{}", self.sta3().bit())) + .field("sta2", &format_args!("{}", self.sta2().bit())) + .field("sta1", &format_args!("{}", self.sta1().bit())) + .field("berr", &format_args!("{}", self.berr().bit())) + .field("gapo4", &format_args!("{}", self.gapo4().bit())) + .field("gapo3", &format_args!("{}", self.gapo3().bit())) + .field("gapo2", &format_args!("{}", self.gapo2().bit())) + .field("gapo1", &format_args!("{}", self.gapo1().bit())) + .field("rerr1", &format_args!("{}", self.rerr1().bit())) + .field("werr1", &format_args!("{}", self.werr1().bit())) + .field("empt1", &format_args!("{}", self.empt1().bit())) + .field("full1", &format_args!("{}", self.full1().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - FIFO full"] #[inline(always)] #[must_use] - pub fn full1(&mut self) -> FULL1_W<0> { + pub fn full1(&mut self) -> FULL1_W { FULL1_W::new(self) } #[doc = "Bit 1 - FIFO empty"] #[inline(always)] #[must_use] - pub fn empt1(&mut self) -> EMPT1_W<1> { + pub fn empt1(&mut self) -> EMPT1_W { EMPT1_W::new(self) } #[doc = "Bit 2 - FIFO write error"] #[inline(always)] #[must_use] - pub fn werr1(&mut self) -> WERR1_W<2> { + pub fn werr1(&mut self) -> WERR1_W { WERR1_W::new(self) } #[doc = "Bit 3 - FIFO read error"] #[inline(always)] #[must_use] - pub fn rerr1(&mut self) -> RERR1_W<3> { + pub fn rerr1(&mut self) -> RERR1_W { RERR1_W::new(self) } #[doc = "Bit 4 - Channel 1 gap occurred"] #[inline(always)] #[must_use] - pub fn gapo1(&mut self) -> GAPO1_W<4> { + pub fn gapo1(&mut self) -> GAPO1_W { GAPO1_W::new(self) } #[doc = "Bit 5 - Channel 2 gap occurred"] #[inline(always)] #[must_use] - pub fn gapo2(&mut self) -> GAPO2_W<5> { + pub fn gapo2(&mut self) -> GAPO2_W { GAPO2_W::new(self) } #[doc = "Bit 6 - Channel 3 gap occurred"] #[inline(always)] #[must_use] - pub fn gapo3(&mut self) -> GAPO3_W<6> { + pub fn gapo3(&mut self) -> GAPO3_W { GAPO3_W::new(self) } #[doc = "Bit 7 - Channel 4 gap occurred"] #[inline(always)] #[must_use] - pub fn gapo4(&mut self) -> GAPO4_W<7> { + pub fn gapo4(&mut self) -> GAPO4_W { GAPO4_W::new(self) } #[doc = "Bit 8 - Bus error"] #[inline(always)] #[must_use] - pub fn berr(&mut self) -> BERR_W<8> { + pub fn berr(&mut self) -> BERR_W { BERR_W::new(self) } #[doc = "Bit 9 - Channel 1 state"] #[inline(always)] #[must_use] - pub fn sta1(&mut self) -> STA1_W<9> { + pub fn sta1(&mut self) -> STA1_W { STA1_W::new(self) } #[doc = "Bit 10 - Channel 2 state"] #[inline(always)] #[must_use] - pub fn sta2(&mut self) -> STA2_W<10> { + pub fn sta2(&mut self) -> STA2_W { STA2_W::new(self) } #[doc = "Bit 11 - Channel 3 state"] #[inline(always)] #[must_use] - pub fn sta3(&mut self) -> STA3_W<11> { + pub fn sta3(&mut self) -> STA3_W { STA3_W::new(self) } #[doc = "Bit 12 - Channel 4 state"] #[inline(always)] #[must_use] - pub fn sta4(&mut self) -> STA4_W<12> { + pub fn sta4(&mut self) -> STA4_W { STA4_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sta](index.html) module"] +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STA_SPEC; impl crate::RegisterSpec for STA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sta::R](R) reader structure"] -impl crate::Readable for STA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sta::W](W) writer structure"] +#[doc = "`read()` method returns [`sta::R`](R) reader structure"] +impl crate::Readable for STA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sta::W`](W) writer structure"] impl crate::Writable for STA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/spi0.rs b/crates/bcm2837-lpa/src/spi0.rs index 88737df..66be9b6 100644 --- a/crates/bcm2837-lpa/src/spi0.rs +++ b/crates/bcm2837-lpa/src/spi0.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control and Status"] pub cs: CS, @@ -14,27 +15,33 @@ pub struct RegisterBlock { #[doc = "0x14 - "] pub dc: DC, } -#[doc = "CS (rw) register accessor: an alias for `Reg`"] +#[doc = "CS (rw) register accessor: Control and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cs`] +module"] pub type CS = crate::Reg; #[doc = "Control and Status"] pub mod cs; -#[doc = "FIFO (rw) register accessor: an alias for `Reg`"] +#[doc = "FIFO (rw) register accessor: FIFO access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`] +module"] pub type FIFO = crate::Reg; #[doc = "FIFO access"] pub mod fifo; -#[doc = "CLK (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK (rw) register accessor: Clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk`] +module"] pub type CLK = crate::Reg; #[doc = "Clock divider"] pub mod clk; -#[doc = "DLEN (rw) register accessor: an alias for `Reg`"] +#[doc = "DLEN (rw) register accessor: Data length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlen`] +module"] pub type DLEN = crate::Reg; #[doc = "Data length"] pub mod dlen; -#[doc = "LTOH (rw) register accessor: an alias for `Reg`"] +#[doc = "LTOH (rw) register accessor: LoSSI output hold delay\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ltoh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ltoh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ltoh`] +module"] pub type LTOH = crate::Reg; #[doc = "LoSSI output hold delay"] pub mod ltoh; -#[doc = "DC (rw) register accessor: an alias for `Reg`"] +#[doc = "DC (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dc`] +module"] pub type DC = crate::Reg; #[doc = ""] pub mod dc; diff --git a/crates/bcm2837-lpa/src/spi0/clk.rs b/crates/bcm2837-lpa/src/spi0/clk.rs index ef3272e..54ce877 100644 --- a/crates/bcm2837-lpa/src/spi0/clk.rs +++ b/crates/bcm2837-lpa/src/spi0/clk.rs @@ -1,43 +1,11 @@ #[doc = "Register `CLK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CDIV` reader - Clock divider"] -pub type CDIV_R = crate::FieldReader; +pub type CDIV_R = crate::FieldReader; #[doc = "Field `CDIV` writer - Clock divider"] -pub type CDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_SPEC, u16, u16, 16, O>; +pub type CDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Clock divider"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { CDIV_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK") + .field("cdiv", &format_args!("{}", self.cdiv().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Clock divider"] #[inline(always)] #[must_use] - pub fn cdiv(&mut self) -> CDIV_W<0> { + pub fn cdiv(&mut self) -> CDIV_W { CDIV_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk](index.html) module"] +#[doc = "Clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_SPEC; impl crate::RegisterSpec for CLK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk::R](R) reader structure"] -impl crate::Readable for CLK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk::W](W) writer structure"] +#[doc = "`read()` method returns [`clk::R`](R) reader structure"] +impl crate::Readable for CLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk::W`](W) writer structure"] impl crate::Writable for CLK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/spi0/cs.rs b/crates/bcm2837-lpa/src/spi0/cs.rs index 50227aa..06511e6 100644 --- a/crates/bcm2837-lpa/src/spi0/cs.rs +++ b/crates/bcm2837-lpa/src/spi0/cs.rs @@ -1,53 +1,21 @@ #[doc = "Register `CS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CS` reader - Chip select"] -pub type CS_R = crate::FieldReader; +pub type CS_R = crate::FieldReader; #[doc = "Field `CS` writer - Chip select"] -pub type CS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, u8, 2, O>; +pub type CS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `CPHA` reader - Clock phase"] -pub type CPHA_R = crate::BitReader; +pub type CPHA_R = crate::BitReader; #[doc = "Field `CPHA` writer - Clock phase"] -pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CPHA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPOL` reader - Clock polarity"] -pub type CPOL_R = crate::BitReader; +pub type CPOL_R = crate::BitReader; #[doc = "Field `CPOL` writer - Clock polarity"] -pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLEAR` reader - Clear the FIFO(s)"] -pub type CLEAR_R = crate::FieldReader; +pub type CLEAR_R = crate::FieldReader; #[doc = "Clear the FIFO(s)\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -65,10 +33,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for CLEAR_A { + type Ux = u8; +} impl CLEAR_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 1 => Some(CLEAR_A::TX), 2 => Some(CLEAR_A::RX), @@ -76,111 +47,115 @@ impl CLEAR_R { _ => None, } } - #[doc = "Checks if the value of the field is `TX`"] + #[doc = "`1`"] #[inline(always)] pub fn is_tx(&self) -> bool { *self == CLEAR_A::TX } - #[doc = "Checks if the value of the field is `RX`"] + #[doc = "`10`"] #[inline(always)] pub fn is_rx(&self) -> bool { *self == CLEAR_A::RX } - #[doc = "Checks if the value of the field is `BOTH`"] + #[doc = "`11`"] #[inline(always)] pub fn is_both(&self) -> bool { *self == CLEAR_A::BOTH } } #[doc = "Field `CLEAR` writer - Clear the FIFO(s)"] -pub type CLEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS_SPEC, u8, CLEAR_A, 2, O>; -impl<'a, const O: u8> CLEAR_W<'a, O> { +pub type CLEAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, CLEAR_A>; +impl<'a, REG, const O: u8> CLEAR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`1`"] #[inline(always)] - pub fn tx(self) -> &'a mut W { + pub fn tx(self) -> &'a mut crate::W { self.variant(CLEAR_A::TX) } #[doc = "`10`"] #[inline(always)] - pub fn rx(self) -> &'a mut W { + pub fn rx(self) -> &'a mut crate::W { self.variant(CLEAR_A::RX) } #[doc = "`11`"] #[inline(always)] - pub fn both(self) -> &'a mut W { + pub fn both(self) -> &'a mut crate::W { self.variant(CLEAR_A::BOTH) } } #[doc = "Field `CSPOL` reader - Chip select polarity"] -pub type CSPOL_R = crate::BitReader; +pub type CSPOL_R = crate::BitReader; #[doc = "Field `CSPOL` writer - Chip select polarity"] -pub type CSPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CSPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TA` reader - Transfer active"] -pub type TA_R = crate::BitReader; +pub type TA_R = crate::BitReader; #[doc = "Field `TA` writer - Transfer active"] -pub type TA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type TA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMAEN` reader - Enable DMA"] -pub type DMAEN_R = crate::BitReader; +pub type DMAEN_R = crate::BitReader; #[doc = "Field `DMAEN` writer - Enable DMA"] -pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type DMAEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTD` reader - Interrupt on done"] -pub type INTD_R = crate::BitReader; +pub type INTD_R = crate::BitReader; #[doc = "Field `INTD` writer - Interrupt on done"] -pub type INTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type INTD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INTR` reader - Interrupt on RX"] -pub type INTR_R = crate::BitReader; +pub type INTR_R = crate::BitReader; #[doc = "Field `INTR` writer - Interrupt on RX"] -pub type INTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type INTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ADCS` reader - Automatically deassert chip select"] -pub type ADCS_R = crate::BitReader; +pub type ADCS_R = crate::BitReader; #[doc = "Field `ADCS` writer - Automatically deassert chip select"] -pub type ADCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type ADCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REN` reader - Read enable"] -pub type REN_R = crate::BitReader; +pub type REN_R = crate::BitReader; #[doc = "Field `REN` writer - Read enable"] -pub type REN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type REN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN` reader - LoSSI enable"] -pub type LEN_R = crate::BitReader; +pub type LEN_R = crate::BitReader; #[doc = "Field `LEN` writer - LoSSI enable"] -pub type LEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type LEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LMONO` reader - "] -pub type LMONO_R = crate::BitReader; +pub type LMONO_R = crate::BitReader; #[doc = "Field `LMONO` writer - "] -pub type LMONO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type LMONO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TE_EN` reader - "] -pub type TE_EN_R = crate::BitReader; +pub type TE_EN_R = crate::BitReader; #[doc = "Field `TE_EN` writer - "] -pub type TE_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type TE_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DONE` reader - Transfer is done"] -pub type DONE_R = crate::BitReader; +pub type DONE_R = crate::BitReader; #[doc = "Field `RXD` reader - RX FIFO contains data"] -pub type RXD_R = crate::BitReader; +pub type RXD_R = crate::BitReader; #[doc = "Field `TXD` reader - TX FIFO can accept data"] -pub type TXD_R = crate::BitReader; +pub type TXD_R = crate::BitReader; #[doc = "Field `RXR` reader - RX FIFO has data to be read"] -pub type RXR_R = crate::BitReader; +pub type RXR_R = crate::BitReader; #[doc = "Field `RXF` reader - RX FIFO full"] -pub type RXF_R = crate::BitReader; +pub type RXF_R = crate::BitReader; #[doc = "Field `CSPOL0` reader - Chip select 0 polarity"] -pub type CSPOL0_R = crate::BitReader; +pub type CSPOL0_R = crate::BitReader; #[doc = "Field `CSPOL0` writer - Chip select 0 polarity"] -pub type CSPOL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CSPOL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSPOL1` reader - Chip select 1 polarity"] -pub type CSPOL1_R = crate::BitReader; +pub type CSPOL1_R = crate::BitReader; #[doc = "Field `CSPOL1` writer - Chip select 1 polarity"] -pub type CSPOL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CSPOL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSPOL2` reader - Chip select 2 polarity"] -pub type CSPOL2_R = crate::BitReader; +pub type CSPOL2_R = crate::BitReader; #[doc = "Field `CSPOL2` writer - Chip select 2 polarity"] -pub type CSPOL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type CSPOL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_LEN` reader - Enable DMA in LoSSI mode"] -pub type DMA_LEN_R = crate::BitReader; +pub type DMA_LEN_R = crate::BitReader; #[doc = "Field `DMA_LEN` writer - Enable DMA in LoSSI mode"] -pub type DMA_LEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type DMA_LEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LEN_LONG` reader - Enable long data word in LoSSI mode"] -pub type LEN_LONG_R = crate::BitReader; +pub type LEN_LONG_R = crate::BitReader; #[doc = "Field `LEN_LONG` writer - Enable long data word in LoSSI mode"] -pub type LEN_LONG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS_SPEC, bool, O>; +pub type LEN_LONG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:1 - Chip select"] #[inline(always)] @@ -303,140 +278,176 @@ impl R { LEN_LONG_R::new(((self.bits >> 25) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CS") + .field("len_long", &format_args!("{}", self.len_long().bit())) + .field("dma_len", &format_args!("{}", self.dma_len().bit())) + .field("cspol2", &format_args!("{}", self.cspol2().bit())) + .field("cspol1", &format_args!("{}", self.cspol1().bit())) + .field("cspol0", &format_args!("{}", self.cspol0().bit())) + .field("rxf", &format_args!("{}", self.rxf().bit())) + .field("rxr", &format_args!("{}", self.rxr().bit())) + .field("txd", &format_args!("{}", self.txd().bit())) + .field("rxd", &format_args!("{}", self.rxd().bit())) + .field("done", &format_args!("{}", self.done().bit())) + .field("te_en", &format_args!("{}", self.te_en().bit())) + .field("lmono", &format_args!("{}", self.lmono().bit())) + .field("len", &format_args!("{}", self.len().bit())) + .field("ren", &format_args!("{}", self.ren().bit())) + .field("adcs", &format_args!("{}", self.adcs().bit())) + .field("intr", &format_args!("{}", self.intr().bit())) + .field("intd", &format_args!("{}", self.intd().bit())) + .field("dmaen", &format_args!("{}", self.dmaen().bit())) + .field("ta", &format_args!("{}", self.ta().bit())) + .field("cspol", &format_args!("{}", self.cspol().bit())) + .field("clear", &format_args!("{}", self.clear().bits())) + .field("cpol", &format_args!("{}", self.cpol().bit())) + .field("cpha", &format_args!("{}", self.cpha().bit())) + .field("cs", &format_args!("{}", self.cs().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Chip select"] #[inline(always)] #[must_use] - pub fn cs(&mut self) -> CS_W<0> { + pub fn cs(&mut self) -> CS_W { CS_W::new(self) } #[doc = "Bit 2 - Clock phase"] #[inline(always)] #[must_use] - pub fn cpha(&mut self) -> CPHA_W<2> { + pub fn cpha(&mut self) -> CPHA_W { CPHA_W::new(self) } #[doc = "Bit 3 - Clock polarity"] #[inline(always)] #[must_use] - pub fn cpol(&mut self) -> CPOL_W<3> { + pub fn cpol(&mut self) -> CPOL_W { CPOL_W::new(self) } #[doc = "Bits 4:5 - Clear the FIFO(s)"] #[inline(always)] #[must_use] - pub fn clear(&mut self) -> CLEAR_W<4> { + pub fn clear(&mut self) -> CLEAR_W { CLEAR_W::new(self) } #[doc = "Bit 6 - Chip select polarity"] #[inline(always)] #[must_use] - pub fn cspol(&mut self) -> CSPOL_W<6> { + pub fn cspol(&mut self) -> CSPOL_W { CSPOL_W::new(self) } #[doc = "Bit 7 - Transfer active"] #[inline(always)] #[must_use] - pub fn ta(&mut self) -> TA_W<7> { + pub fn ta(&mut self) -> TA_W { TA_W::new(self) } #[doc = "Bit 8 - Enable DMA"] #[inline(always)] #[must_use] - pub fn dmaen(&mut self) -> DMAEN_W<8> { + pub fn dmaen(&mut self) -> DMAEN_W { DMAEN_W::new(self) } #[doc = "Bit 9 - Interrupt on done"] #[inline(always)] #[must_use] - pub fn intd(&mut self) -> INTD_W<9> { + pub fn intd(&mut self) -> INTD_W { INTD_W::new(self) } #[doc = "Bit 10 - Interrupt on RX"] #[inline(always)] #[must_use] - pub fn intr(&mut self) -> INTR_W<10> { + pub fn intr(&mut self) -> INTR_W { INTR_W::new(self) } #[doc = "Bit 11 - Automatically deassert chip select"] #[inline(always)] #[must_use] - pub fn adcs(&mut self) -> ADCS_W<11> { + pub fn adcs(&mut self) -> ADCS_W { ADCS_W::new(self) } #[doc = "Bit 12 - Read enable"] #[inline(always)] #[must_use] - pub fn ren(&mut self) -> REN_W<12> { + pub fn ren(&mut self) -> REN_W { REN_W::new(self) } #[doc = "Bit 13 - LoSSI enable"] #[inline(always)] #[must_use] - pub fn len(&mut self) -> LEN_W<13> { + pub fn len(&mut self) -> LEN_W { LEN_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn lmono(&mut self) -> LMONO_W<14> { + pub fn lmono(&mut self) -> LMONO_W { LMONO_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn te_en(&mut self) -> TE_EN_W<15> { + pub fn te_en(&mut self) -> TE_EN_W { TE_EN_W::new(self) } #[doc = "Bit 21 - Chip select 0 polarity"] #[inline(always)] #[must_use] - pub fn cspol0(&mut self) -> CSPOL0_W<21> { + pub fn cspol0(&mut self) -> CSPOL0_W { CSPOL0_W::new(self) } #[doc = "Bit 22 - Chip select 1 polarity"] #[inline(always)] #[must_use] - pub fn cspol1(&mut self) -> CSPOL1_W<22> { + pub fn cspol1(&mut self) -> CSPOL1_W { CSPOL1_W::new(self) } #[doc = "Bit 23 - Chip select 2 polarity"] #[inline(always)] #[must_use] - pub fn cspol2(&mut self) -> CSPOL2_W<23> { + pub fn cspol2(&mut self) -> CSPOL2_W { CSPOL2_W::new(self) } #[doc = "Bit 24 - Enable DMA in LoSSI mode"] #[inline(always)] #[must_use] - pub fn dma_len(&mut self) -> DMA_LEN_W<24> { + pub fn dma_len(&mut self) -> DMA_LEN_W { DMA_LEN_W::new(self) } #[doc = "Bit 25 - Enable long data word in LoSSI mode"] #[inline(always)] #[must_use] - pub fn len_long(&mut self) -> LEN_LONG_W<25> { + pub fn len_long(&mut self) -> LEN_LONG_W { LEN_LONG_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control and Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +#[doc = "Control and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CS_SPEC; impl crate::RegisterSpec for CS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cs::R](R) reader structure"] -impl crate::Readable for CS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/spi0/dc.rs b/crates/bcm2837-lpa/src/spi0/dc.rs index 281dd71..23813da 100644 --- a/crates/bcm2837-lpa/src/spi0/dc.rs +++ b/crates/bcm2837-lpa/src/spi0/dc.rs @@ -1,55 +1,23 @@ #[doc = "Register `DC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TDREQ` reader - DMA Write request threshold"] -pub type TDREQ_R = crate::FieldReader; +pub type TDREQ_R = crate::FieldReader; #[doc = "Field `TDREQ` writer - DMA Write request threshold"] -pub type TDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +pub type TDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `TPANIC` reader - DMA write panic threshold"] -pub type TPANIC_R = crate::FieldReader; +pub type TPANIC_R = crate::FieldReader; #[doc = "Field `TPANIC` writer - DMA write panic threshold"] -pub type TPANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +pub type TPANIC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `RDREQ` reader - DMA read request threshold"] -pub type RDREQ_R = crate::FieldReader; +pub type RDREQ_R = crate::FieldReader; #[doc = "Field `RDREQ` writer - DMA read request threshold"] -pub type RDREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +pub type RDREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `RPANIC` reader - DMA read panic threshold"] -pub type RPANIC_R = crate::FieldReader; +pub type RPANIC_R = crate::FieldReader; #[doc = "Field `RPANIC` writer - DMA read panic threshold"] -pub type RPANIC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DC_SPEC, u8, u8, 8, O>; +pub type RPANIC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - DMA Write request threshold"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { RPANIC_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DC") + .field("rpanic", &format_args!("{}", self.rpanic().bits())) + .field("rdreq", &format_args!("{}", self.rdreq().bits())) + .field("tpanic", &format_args!("{}", self.tpanic().bits())) + .field("tdreq", &format_args!("{}", self.tdreq().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DMA Write request threshold"] #[inline(always)] #[must_use] - pub fn tdreq(&mut self) -> TDREQ_W<0> { + pub fn tdreq(&mut self) -> TDREQ_W { TDREQ_W::new(self) } #[doc = "Bits 8:15 - DMA write panic threshold"] #[inline(always)] #[must_use] - pub fn tpanic(&mut self) -> TPANIC_W<8> { + pub fn tpanic(&mut self) -> TPANIC_W { TPANIC_W::new(self) } #[doc = "Bits 16:23 - DMA read request threshold"] #[inline(always)] #[must_use] - pub fn rdreq(&mut self) -> RDREQ_W<16> { + pub fn rdreq(&mut self) -> RDREQ_W { RDREQ_W::new(self) } #[doc = "Bits 24:31 - DMA read panic threshold"] #[inline(always)] #[must_use] - pub fn rpanic(&mut self) -> RPANIC_W<24> { + pub fn rpanic(&mut self) -> RPANIC_W { RPANIC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dc](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DC_SPEC; impl crate::RegisterSpec for DC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dc::R](R) reader structure"] -impl crate::Readable for DC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dc::W](W) writer structure"] +#[doc = "`read()` method returns [`dc::R`](R) reader structure"] +impl crate::Readable for DC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dc::W`](W) writer structure"] impl crate::Writable for DC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/spi0/dlen.rs b/crates/bcm2837-lpa/src/spi0/dlen.rs index 25e2771..5c7bb83 100644 --- a/crates/bcm2837-lpa/src/spi0/dlen.rs +++ b/crates/bcm2837-lpa/src/spi0/dlen.rs @@ -1,43 +1,11 @@ #[doc = "Register `DLEN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DLEN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DLEN` reader - Data length"] -pub type DLEN_R = crate::FieldReader; +pub type DLEN_R = crate::FieldReader; #[doc = "Field `DLEN` writer - Data length"] -pub type DLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DLEN_SPEC, u16, u16, 16, O>; +pub type DLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Data length"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DLEN_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DLEN") + .field("dlen", &format_args!("{}", self.dlen().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Data length"] #[inline(always)] #[must_use] - pub fn dlen(&mut self) -> DLEN_W<0> { + pub fn dlen(&mut self) -> DLEN_W { DLEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dlen](index.html) module"] +#[doc = "Data length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DLEN_SPEC; impl crate::RegisterSpec for DLEN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dlen::R](R) reader structure"] -impl crate::Readable for DLEN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dlen::W](W) writer structure"] +#[doc = "`read()` method returns [`dlen::R`](R) reader structure"] +impl crate::Readable for DLEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dlen::W`](W) writer structure"] impl crate::Writable for DLEN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/spi0/fifo.rs b/crates/bcm2837-lpa/src/spi0/fifo.rs index 46d2ece..937c27b 100644 --- a/crates/bcm2837-lpa/src/spi0/fifo.rs +++ b/crates/bcm2837-lpa/src/spi0/fifo.rs @@ -1,43 +1,11 @@ #[doc = "Register `FIFO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FIFO` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - Data"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - Data"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_SPEC, u32, u32, 32, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Data"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - Data"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "FIFO access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"] +#[doc = "FIFO access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_SPEC; impl crate::RegisterSpec for FIFO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fifo::R](R) reader structure"] -impl crate::Readable for FIFO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"] +#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] +impl crate::Readable for FIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"] impl crate::Writable for FIFO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/spi0/ltoh.rs b/crates/bcm2837-lpa/src/spi0/ltoh.rs index 5d0ab3f..15d66d8 100644 --- a/crates/bcm2837-lpa/src/spi0/ltoh.rs +++ b/crates/bcm2837-lpa/src/spi0/ltoh.rs @@ -1,43 +1,11 @@ #[doc = "Register `LTOH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LTOH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TOH` reader - Output hold delay"] -pub type TOH_R = crate::FieldReader; +pub type TOH_R = crate::FieldReader; #[doc = "Field `TOH` writer - Output hold delay"] -pub type TOH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LTOH_SPEC, u8, u8, 4, O>; +pub type TOH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - Output hold delay"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { TOH_R::new((self.bits & 0x0f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LTOH") + .field("toh", &format_args!("{}", self.toh().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:3 - Output hold delay"] #[inline(always)] #[must_use] - pub fn toh(&mut self) -> TOH_W<0> { + pub fn toh(&mut self) -> TOH_W { TOH_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LoSSI output hold delay\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ltoh](index.html) module"] +#[doc = "LoSSI output hold delay\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ltoh::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ltoh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LTOH_SPEC; impl crate::RegisterSpec for LTOH_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ltoh::R](R) reader structure"] -impl crate::Readable for LTOH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ltoh::W](W) writer structure"] +#[doc = "`read()` method returns [`ltoh::R`](R) reader structure"] +impl crate::Readable for LTOH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ltoh::W`](W) writer structure"] impl crate::Writable for LTOH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/spi1.rs b/crates/bcm2837-lpa/src/spi1.rs index 1547fcc..0031aa9 100644 --- a/crates/bcm2837-lpa/src/spi1.rs +++ b/crates/bcm2837-lpa/src/spi1.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control 0"] pub cntl0: CNTL0, @@ -14,27 +15,33 @@ pub struct RegisterBlock { #[doc = "0x20..0x30 - Writing to the FIFO will maintain CS at the end of the access"] pub txhold: [TXHOLD; 4], } -#[doc = "CNTL0 (rw) register accessor: an alias for `Reg`"] +#[doc = "CNTL0 (rw) register accessor: Control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntl0`] +module"] pub type CNTL0 = crate::Reg; #[doc = "Control 0"] pub mod cntl0; -#[doc = "CNTL1 (rw) register accessor: an alias for `Reg`"] +#[doc = "CNTL1 (rw) register accessor: Control 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntl1`] +module"] pub type CNTL1 = crate::Reg; #[doc = "Control 1"] pub mod cntl1; -#[doc = "STAT (rw) register accessor: an alias for `Reg`"] +#[doc = "STAT (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] +module"] pub type STAT = crate::Reg; #[doc = "Status"] pub mod stat; -#[doc = "PEEK (r) register accessor: an alias for `Reg`"] +#[doc = "PEEK (r) register accessor: Read the RXFIFO without removing an entry\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peek`] +module"] pub type PEEK = crate::Reg; #[doc = "Read the RXFIFO without removing an entry"] pub mod peek; -#[doc = "IO (rw) register accessor: an alias for `Reg`"] +#[doc = "IO (rw) register accessor: Writing to the FIFO will deassert CS at the end of the access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io`] +module"] pub type IO = crate::Reg; #[doc = "Writing to the FIFO will deassert CS at the end of the access"] pub mod io; -#[doc = "TXHOLD (rw) register accessor: an alias for `Reg`"] +#[doc = "TXHOLD (rw) register accessor: Writing to the FIFO will maintain CS at the end of the access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txhold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txhold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txhold`] +module"] pub type TXHOLD = crate::Reg; #[doc = "Writing to the FIFO will maintain CS at the end of the access"] pub mod txhold; diff --git a/crates/bcm2837-lpa/src/spi1/cntl0.rs b/crates/bcm2837-lpa/src/spi1/cntl0.rs index b9354b5..df7d957 100644 --- a/crates/bcm2837-lpa/src/spi1/cntl0.rs +++ b/crates/bcm2837-lpa/src/spi1/cntl0.rs @@ -1,69 +1,37 @@ #[doc = "Register `CNTL0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CNTL0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SHIFT_LENGTH` reader - Number of bits to shift"] -pub type SHIFT_LENGTH_R = crate::FieldReader; +pub type SHIFT_LENGTH_R = crate::FieldReader; #[doc = "Field `SHIFT_LENGTH` writer - Number of bits to shift"] -pub type SHIFT_LENGTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u8, u8, 6, O>; +pub type SHIFT_LENGTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `MSB_FIRST` reader - Shift out the most significant bit (MSB) first"] -pub type MSB_FIRST_R = crate::BitReader; +pub type MSB_FIRST_R = crate::BitReader; #[doc = "Field `MSB_FIRST` writer - Shift out the most significant bit (MSB) first"] -pub type MSB_FIRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type MSB_FIRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INVERT_CLK` reader - Idle clock high"] -pub type INVERT_CLK_R = crate::BitReader; +pub type INVERT_CLK_R = crate::BitReader; #[doc = "Field `INVERT_CLK` writer - Idle clock high"] -pub type INVERT_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type INVERT_CLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OUT_RISING` reader - Data is clocked out on rising edge of CLK"] -pub type OUT_RISING_R = crate::BitReader; +pub type OUT_RISING_R = crate::BitReader; #[doc = "Field `OUT_RISING` writer - Data is clocked out on rising edge of CLK"] -pub type OUT_RISING_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type OUT_RISING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLEAR_FIFOS` reader - Clear FIFOs"] -pub type CLEAR_FIFOS_R = crate::BitReader; +pub type CLEAR_FIFOS_R = crate::BitReader; #[doc = "Field `CLEAR_FIFOS` writer - Clear FIFOs"] -pub type CLEAR_FIFOS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type CLEAR_FIFOS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IN_RISING` reader - Data is clocked in on rising edge of CLK"] -pub type IN_RISING_R = crate::BitReader; +pub type IN_RISING_R = crate::BitReader; #[doc = "Field `IN_RISING` writer - Data is clocked in on rising edge of CLK"] -pub type IN_RISING_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type IN_RISING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE` reader - Enable the interface"] -pub type ENABLE_R = crate::BitReader; +pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Enable the interface"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOUT_HOLD_TIME` reader - Controls extra DOUT hold time in system clock cycles"] -pub type DOUT_HOLD_TIME_R = crate::FieldReader; +pub type DOUT_HOLD_TIME_R = crate::FieldReader; #[doc = "Controls extra DOUT hold time in system clock cycles\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -83,10 +51,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for DOUT_HOLD_TIME_A { + type Ux = u8; +} impl DOUT_HOLD_TIME_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DOUT_HOLD_TIME_A { + pub const fn variant(&self) -> DOUT_HOLD_TIME_A { match self.bits { 0 => DOUT_HOLD_TIME_A::_0, 1 => DOUT_HOLD_TIME_A::_1, @@ -95,72 +66,76 @@ impl DOUT_HOLD_TIME_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_0`"] + #[doc = "`0`"] #[inline(always)] pub fn is_0(&self) -> bool { *self == DOUT_HOLD_TIME_A::_0 } - #[doc = "Checks if the value of the field is `_1`"] + #[doc = "`1`"] #[inline(always)] pub fn is_1(&self) -> bool { *self == DOUT_HOLD_TIME_A::_1 } - #[doc = "Checks if the value of the field is `_4`"] + #[doc = "`10`"] #[inline(always)] pub fn is_4(&self) -> bool { *self == DOUT_HOLD_TIME_A::_4 } - #[doc = "Checks if the value of the field is `_7`"] + #[doc = "`11`"] #[inline(always)] pub fn is_7(&self) -> bool { *self == DOUT_HOLD_TIME_A::_7 } } #[doc = "Field `DOUT_HOLD_TIME` writer - Controls extra DOUT hold time in system clock cycles"] -pub type DOUT_HOLD_TIME_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, CNTL0_SPEC, u8, DOUT_HOLD_TIME_A, 2, O>; -impl<'a, const O: u8> DOUT_HOLD_TIME_W<'a, O> { +pub type DOUT_HOLD_TIME_W<'a, REG, const O: u8> = + crate::FieldWriterSafe<'a, REG, 2, O, DOUT_HOLD_TIME_A>; +impl<'a, REG, const O: u8> DOUT_HOLD_TIME_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _0(self) -> &'a mut W { + pub fn _0(self) -> &'a mut crate::W { self.variant(DOUT_HOLD_TIME_A::_0) } #[doc = "`1`"] #[inline(always)] - pub fn _1(self) -> &'a mut W { + pub fn _1(self) -> &'a mut crate::W { self.variant(DOUT_HOLD_TIME_A::_1) } #[doc = "`10`"] #[inline(always)] - pub fn _4(self) -> &'a mut W { + pub fn _4(self) -> &'a mut crate::W { self.variant(DOUT_HOLD_TIME_A::_4) } #[doc = "`11`"] #[inline(always)] - pub fn _7(self) -> &'a mut W { + pub fn _7(self) -> &'a mut crate::W { self.variant(DOUT_HOLD_TIME_A::_7) } } #[doc = "Field `VARIABLE_WIDTH` reader - Take shift length and data from FIFO"] -pub type VARIABLE_WIDTH_R = crate::BitReader; +pub type VARIABLE_WIDTH_R = crate::BitReader; #[doc = "Field `VARIABLE_WIDTH` writer - Take shift length and data from FIFO"] -pub type VARIABLE_WIDTH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type VARIABLE_WIDTH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VARIABLE_CS` reader - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] -pub type VARIABLE_CS_R = crate::BitReader; +pub type VARIABLE_CS_R = crate::BitReader; #[doc = "Field `VARIABLE_CS` writer - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] -pub type VARIABLE_CS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type VARIABLE_CS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POST_INPUT` reader - Post input mode"] -pub type POST_INPUT_R = crate::BitReader; +pub type POST_INPUT_R = crate::BitReader; #[doc = "Field `POST_INPUT` writer - Post input mode"] -pub type POST_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL0_SPEC, bool, O>; +pub type POST_INPUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHIP_SELECTS` reader - The CS pattern when active"] -pub type CHIP_SELECTS_R = crate::FieldReader; +pub type CHIP_SELECTS_R = crate::FieldReader; #[doc = "Field `CHIP_SELECTS` writer - The CS pattern when active"] -pub type CHIP_SELECTS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u8, u8, 3, O>; +pub type CHIP_SELECTS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `SPEED` reader - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] -pub type SPEED_R = crate::FieldReader; +pub type SPEED_R = crate::FieldReader; #[doc = "Field `SPEED` writer - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] -pub type SPEED_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL0_SPEC, u16, u16, 12, O>; +pub type SPEED_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; impl R { #[doc = "Bits 0:5 - Number of bits to shift"] #[inline(always)] @@ -228,104 +203,141 @@ impl R { SPEED_R::new(((self.bits >> 20) & 0x0fff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CNTL0") + .field("speed", &format_args!("{}", self.speed().bits())) + .field( + "chip_selects", + &format_args!("{}", self.chip_selects().bits()), + ) + .field("post_input", &format_args!("{}", self.post_input().bit())) + .field("variable_cs", &format_args!("{}", self.variable_cs().bit())) + .field( + "variable_width", + &format_args!("{}", self.variable_width().bit()), + ) + .field( + "dout_hold_time", + &format_args!("{}", self.dout_hold_time().bits()), + ) + .field("enable", &format_args!("{}", self.enable().bit())) + .field("in_rising", &format_args!("{}", self.in_rising().bit())) + .field("clear_fifos", &format_args!("{}", self.clear_fifos().bit())) + .field("out_rising", &format_args!("{}", self.out_rising().bit())) + .field("invert_clk", &format_args!("{}", self.invert_clk().bit())) + .field("msb_first", &format_args!("{}", self.msb_first().bit())) + .field( + "shift_length", + &format_args!("{}", self.shift_length().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5 - Number of bits to shift"] #[inline(always)] #[must_use] - pub fn shift_length(&mut self) -> SHIFT_LENGTH_W<0> { + pub fn shift_length(&mut self) -> SHIFT_LENGTH_W { SHIFT_LENGTH_W::new(self) } #[doc = "Bit 6 - Shift out the most significant bit (MSB) first"] #[inline(always)] #[must_use] - pub fn msb_first(&mut self) -> MSB_FIRST_W<6> { + pub fn msb_first(&mut self) -> MSB_FIRST_W { MSB_FIRST_W::new(self) } #[doc = "Bit 7 - Idle clock high"] #[inline(always)] #[must_use] - pub fn invert_clk(&mut self) -> INVERT_CLK_W<7> { + pub fn invert_clk(&mut self) -> INVERT_CLK_W { INVERT_CLK_W::new(self) } #[doc = "Bit 8 - Data is clocked out on rising edge of CLK"] #[inline(always)] #[must_use] - pub fn out_rising(&mut self) -> OUT_RISING_W<8> { + pub fn out_rising(&mut self) -> OUT_RISING_W { OUT_RISING_W::new(self) } #[doc = "Bit 9 - Clear FIFOs"] #[inline(always)] #[must_use] - pub fn clear_fifos(&mut self) -> CLEAR_FIFOS_W<9> { + pub fn clear_fifos(&mut self) -> CLEAR_FIFOS_W { CLEAR_FIFOS_W::new(self) } #[doc = "Bit 10 - Data is clocked in on rising edge of CLK"] #[inline(always)] #[must_use] - pub fn in_rising(&mut self) -> IN_RISING_W<10> { + pub fn in_rising(&mut self) -> IN_RISING_W { IN_RISING_W::new(self) } #[doc = "Bit 11 - Enable the interface"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<11> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bits 12:13 - Controls extra DOUT hold time in system clock cycles"] #[inline(always)] #[must_use] - pub fn dout_hold_time(&mut self) -> DOUT_HOLD_TIME_W<12> { + pub fn dout_hold_time(&mut self) -> DOUT_HOLD_TIME_W { DOUT_HOLD_TIME_W::new(self) } #[doc = "Bit 14 - Take shift length and data from FIFO"] #[inline(always)] #[must_use] - pub fn variable_width(&mut self) -> VARIABLE_WIDTH_W<14> { + pub fn variable_width(&mut self) -> VARIABLE_WIDTH_W { VARIABLE_WIDTH_W::new(self) } #[doc = "Bit 15 - Take CS pattern and data from TX FIFO (along with VARIABLE_WIDTH)"] #[inline(always)] #[must_use] - pub fn variable_cs(&mut self) -> VARIABLE_CS_W<15> { + pub fn variable_cs(&mut self) -> VARIABLE_CS_W { VARIABLE_CS_W::new(self) } #[doc = "Bit 16 - Post input mode"] #[inline(always)] #[must_use] - pub fn post_input(&mut self) -> POST_INPUT_W<16> { + pub fn post_input(&mut self) -> POST_INPUT_W { POST_INPUT_W::new(self) } #[doc = "Bits 17:19 - The CS pattern when active"] #[inline(always)] #[must_use] - pub fn chip_selects(&mut self) -> CHIP_SELECTS_W<17> { + pub fn chip_selects(&mut self) -> CHIP_SELECTS_W { CHIP_SELECTS_W::new(self) } #[doc = "Bits 20:31 - SPI clock speed. clk = sys / 2 * (SPEED + 1)"] #[inline(always)] #[must_use] - pub fn speed(&mut self) -> SPEED_W<20> { + pub fn speed(&mut self) -> SPEED_W { SPEED_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl0](index.html) module"] +#[doc = "Control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CNTL0_SPEC; impl crate::RegisterSpec for CNTL0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cntl0::R](R) reader structure"] -impl crate::Readable for CNTL0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cntl0::W](W) writer structure"] +#[doc = "`read()` method returns [`cntl0::R`](R) reader structure"] +impl crate::Readable for CNTL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cntl0::W`](W) writer structure"] impl crate::Writable for CNTL0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/spi1/cntl1.rs b/crates/bcm2837-lpa/src/spi1/cntl1.rs index c7d627b..c1f0228 100644 --- a/crates/bcm2837-lpa/src/spi1/cntl1.rs +++ b/crates/bcm2837-lpa/src/spi1/cntl1.rs @@ -1,59 +1,27 @@ #[doc = "Register `CNTL1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CNTL1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `KEEP_INPUT` reader - Don't clear the RX shift register before a new transaction"] -pub type KEEP_INPUT_R = crate::BitReader; +pub type KEEP_INPUT_R = crate::BitReader; #[doc = "Field `KEEP_INPUT` writer - Don't clear the RX shift register before a new transaction"] -pub type KEEP_INPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +pub type KEEP_INPUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSB_FIRST` reader - Shift the most significant bit first (MSB)"] -pub type MSB_FIRST_R = crate::BitReader; +pub type MSB_FIRST_R = crate::BitReader; #[doc = "Field `MSB_FIRST` writer - Shift the most significant bit first (MSB)"] -pub type MSB_FIRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +pub type MSB_FIRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DONE_ENABLE` reader - Enable DONE interrupt"] -pub type DONE_ENABLE_R = crate::BitReader; +pub type DONE_ENABLE_R = crate::BitReader; #[doc = "Field `DONE_ENABLE` writer - Enable DONE interrupt"] -pub type DONE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +pub type DONE_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXE_ENABLE` reader - Enable TX empty interrupt"] -pub type TXE_ENABLE_R = crate::BitReader; +pub type TXE_ENABLE_R = crate::BitReader; #[doc = "Field `TXE_ENABLE` writer - Enable TX empty interrupt"] -pub type TXE_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL1_SPEC, bool, O>; +pub type TXE_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CS_HIGH_TIME` reader - Additional SPI clock cycles where CS is high"] -pub type CS_HIGH_TIME_R = crate::FieldReader; +pub type CS_HIGH_TIME_R = crate::FieldReader; #[doc = "Field `CS_HIGH_TIME` writer - Additional SPI clock cycles where CS is high"] -pub type CS_HIGH_TIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL1_SPEC, u8, u8, 3, O>; +pub type CS_HIGH_TIME_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bit 0 - Don't clear the RX shift register before a new transaction"] #[inline(always)] @@ -81,56 +49,76 @@ impl R { CS_HIGH_TIME_R::new(((self.bits >> 8) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CNTL1") + .field( + "cs_high_time", + &format_args!("{}", self.cs_high_time().bits()), + ) + .field("txe_enable", &format_args!("{}", self.txe_enable().bit())) + .field("done_enable", &format_args!("{}", self.done_enable().bit())) + .field("msb_first", &format_args!("{}", self.msb_first().bit())) + .field("keep_input", &format_args!("{}", self.keep_input().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Don't clear the RX shift register before a new transaction"] #[inline(always)] #[must_use] - pub fn keep_input(&mut self) -> KEEP_INPUT_W<0> { + pub fn keep_input(&mut self) -> KEEP_INPUT_W { KEEP_INPUT_W::new(self) } #[doc = "Bit 1 - Shift the most significant bit first (MSB)"] #[inline(always)] #[must_use] - pub fn msb_first(&mut self) -> MSB_FIRST_W<1> { + pub fn msb_first(&mut self) -> MSB_FIRST_W { MSB_FIRST_W::new(self) } #[doc = "Bit 6 - Enable DONE interrupt"] #[inline(always)] #[must_use] - pub fn done_enable(&mut self) -> DONE_ENABLE_W<6> { + pub fn done_enable(&mut self) -> DONE_ENABLE_W { DONE_ENABLE_W::new(self) } #[doc = "Bit 7 - Enable TX empty interrupt"] #[inline(always)] #[must_use] - pub fn txe_enable(&mut self) -> TXE_ENABLE_W<7> { + pub fn txe_enable(&mut self) -> TXE_ENABLE_W { TXE_ENABLE_W::new(self) } #[doc = "Bits 8:10 - Additional SPI clock cycles where CS is high"] #[inline(always)] #[must_use] - pub fn cs_high_time(&mut self) -> CS_HIGH_TIME_W<8> { + pub fn cs_high_time(&mut self) -> CS_HIGH_TIME_W { CS_HIGH_TIME_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl1](index.html) module"] +#[doc = "Control 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CNTL1_SPEC; impl crate::RegisterSpec for CNTL1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cntl1::R](R) reader structure"] -impl crate::Readable for CNTL1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cntl1::W](W) writer structure"] +#[doc = "`read()` method returns [`cntl1::R`](R) reader structure"] +impl crate::Readable for CNTL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cntl1::W`](W) writer structure"] impl crate::Writable for CNTL1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/spi1/io.rs b/crates/bcm2837-lpa/src/spi1/io.rs index 365004d..6564875 100644 --- a/crates/bcm2837-lpa/src/spi1/io.rs +++ b/crates/bcm2837-lpa/src/spi1/io.rs @@ -1,43 +1,11 @@ #[doc = "Register `IO%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IO%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - FIFO data access"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - FIFO data access"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO_SPEC, u16, u16, 16, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IO") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Writing to the FIFO will deassert CS at the end of the access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](index.html) module"] +#[doc = "Writing to the FIFO will deassert CS at the end of the access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IO_SPEC; impl crate::RegisterSpec for IO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [io::R](R) reader structure"] -impl crate::Readable for IO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [io::W](W) writer structure"] +#[doc = "`read()` method returns [`io::R`](R) reader structure"] +impl crate::Readable for IO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`io::W`](W) writer structure"] impl crate::Writable for IO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/spi1/peek.rs b/crates/bcm2837-lpa/src/spi1/peek.rs index b4a7333..7ceeb4a 100644 --- a/crates/bcm2837-lpa/src/spi1/peek.rs +++ b/crates/bcm2837-lpa/src/spi1/peek.rs @@ -1,20 +1,7 @@ #[doc = "Register `PEEK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DATA` reader - FIFO data access"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] @@ -22,15 +9,25 @@ impl R { DATA_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Read the RXFIFO without removing an entry\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PEEK") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Read the RXFIFO without removing an entry\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEEK_SPEC; impl crate::RegisterSpec for PEEK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [peek::R](R) reader structure"] -impl crate::Readable for PEEK_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`peek::R`](R) reader structure"] +impl crate::Readable for PEEK_SPEC {} #[doc = "`reset()` method sets PEEK to value 0"] impl crate::Resettable for PEEK_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/spi1/stat.rs b/crates/bcm2837-lpa/src/spi1/stat.rs index 0dd56f6..9fe3977 100644 --- a/crates/bcm2837-lpa/src/spi1/stat.rs +++ b/crates/bcm2837-lpa/src/spi1/stat.rs @@ -1,71 +1,39 @@ #[doc = "Register `STAT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STAT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BIT_COUNT` reader - Number of bits left to be processed."] -pub type BIT_COUNT_R = crate::FieldReader; +pub type BIT_COUNT_R = crate::FieldReader; #[doc = "Field `BIT_COUNT` writer - Number of bits left to be processed."] -pub type BIT_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 6, O>; +pub type BIT_COUNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `BUSY` reader - Indicates a transfer is ongoing"] -pub type BUSY_R = crate::BitReader; +pub type BUSY_R = crate::BitReader; #[doc = "Field `BUSY` writer - Indicates a transfer is ongoing"] -pub type BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type BUSY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_EMPTY` reader - RX FIFO is empty"] -pub type RX_EMPTY_R = crate::BitReader; +pub type RX_EMPTY_R = crate::BitReader; #[doc = "Field `RX_EMPTY` writer - RX FIFO is empty"] -pub type RX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_FULL` reader - RX FIFO is full"] -pub type RX_FULL_R = crate::BitReader; +pub type RX_FULL_R = crate::BitReader; #[doc = "Field `RX_FULL` writer - RX FIFO is full"] -pub type RX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_EMPTY` reader - TX FIFO is empty"] -pub type TX_EMPTY_R = crate::BitReader; +pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `TX_EMPTY` writer - TX FIFO is empty"] -pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_FULL` reader - TX FIFO is full"] -pub type TX_FULL_R = crate::BitReader; +pub type TX_FULL_R = crate::BitReader; #[doc = "Field `TX_FULL` writer - TX FIFO is full"] -pub type TX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_LEVEL` reader - Number of entries in RX FIFO"] -pub type RX_LEVEL_R = crate::FieldReader; +pub type RX_LEVEL_R = crate::FieldReader; #[doc = "Field `RX_LEVEL` writer - Number of entries in RX FIFO"] -pub type RX_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +pub type RX_LEVEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TX_LEVEL` reader - Number of entries in TX FIFO"] -pub type TX_LEVEL_R = crate::FieldReader; +pub type TX_LEVEL_R = crate::FieldReader; #[doc = "Field `TX_LEVEL` writer - Number of entries in TX FIFO"] -pub type TX_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +pub type TX_LEVEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:5 - Number of bits left to be processed."] #[inline(always)] @@ -108,74 +76,94 @@ impl R { TX_LEVEL_R::new(((self.bits >> 24) & 0x0f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STAT") + .field("tx_level", &format_args!("{}", self.tx_level().bits())) + .field("rx_level", &format_args!("{}", self.rx_level().bits())) + .field("tx_full", &format_args!("{}", self.tx_full().bit())) + .field("tx_empty", &format_args!("{}", self.tx_empty().bit())) + .field("rx_full", &format_args!("{}", self.rx_full().bit())) + .field("rx_empty", &format_args!("{}", self.rx_empty().bit())) + .field("busy", &format_args!("{}", self.busy().bit())) + .field("bit_count", &format_args!("{}", self.bit_count().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5 - Number of bits left to be processed."] #[inline(always)] #[must_use] - pub fn bit_count(&mut self) -> BIT_COUNT_W<0> { + pub fn bit_count(&mut self) -> BIT_COUNT_W { BIT_COUNT_W::new(self) } #[doc = "Bit 6 - Indicates a transfer is ongoing"] #[inline(always)] #[must_use] - pub fn busy(&mut self) -> BUSY_W<6> { + pub fn busy(&mut self) -> BUSY_W { BUSY_W::new(self) } #[doc = "Bit 7 - RX FIFO is empty"] #[inline(always)] #[must_use] - pub fn rx_empty(&mut self) -> RX_EMPTY_W<7> { + pub fn rx_empty(&mut self) -> RX_EMPTY_W { RX_EMPTY_W::new(self) } #[doc = "Bit 8 - RX FIFO is full"] #[inline(always)] #[must_use] - pub fn rx_full(&mut self) -> RX_FULL_W<8> { + pub fn rx_full(&mut self) -> RX_FULL_W { RX_FULL_W::new(self) } #[doc = "Bit 9 - TX FIFO is empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W<9> { + pub fn tx_empty(&mut self) -> TX_EMPTY_W { TX_EMPTY_W::new(self) } #[doc = "Bit 10 - TX FIFO is full"] #[inline(always)] #[must_use] - pub fn tx_full(&mut self) -> TX_FULL_W<10> { + pub fn tx_full(&mut self) -> TX_FULL_W { TX_FULL_W::new(self) } #[doc = "Bits 16:19 - Number of entries in RX FIFO"] #[inline(always)] #[must_use] - pub fn rx_level(&mut self) -> RX_LEVEL_W<16> { + pub fn rx_level(&mut self) -> RX_LEVEL_W { RX_LEVEL_W::new(self) } #[doc = "Bits 24:27 - Number of entries in TX FIFO"] #[inline(always)] #[must_use] - pub fn tx_level(&mut self) -> TX_LEVEL_W<24> { + pub fn tx_level(&mut self) -> TX_LEVEL_W { TX_LEVEL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"] +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STAT_SPEC; impl crate::RegisterSpec for STAT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [stat::R](R) reader structure"] -impl crate::Readable for STAT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"] +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] impl crate::Writable for STAT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/spi1/txhold.rs b/crates/bcm2837-lpa/src/spi1/txhold.rs index a2ca31b..8c29938 100644 --- a/crates/bcm2837-lpa/src/spi1/txhold.rs +++ b/crates/bcm2837-lpa/src/spi1/txhold.rs @@ -1,43 +1,11 @@ #[doc = "Register `TXHOLD%s` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TXHOLD%s` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - FIFO data access"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - FIFO data access"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXHOLD_SPEC, u16, u16, 16, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TXHOLD") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - FIFO data access"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Writing to the FIFO will maintain CS at the end of the access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txhold](index.html) module"] +#[doc = "Writing to the FIFO will maintain CS at the end of the access\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txhold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txhold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXHOLD_SPEC; impl crate::RegisterSpec for TXHOLD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txhold::R](R) reader structure"] -impl crate::Readable for TXHOLD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [txhold::W](W) writer structure"] +#[doc = "`read()` method returns [`txhold::R`](R) reader structure"] +impl crate::Readable for TXHOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txhold::W`](W) writer structure"] impl crate::Writable for TXHOLD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/systmr.rs b/crates/bcm2837-lpa/src/systmr.rs index 859ea09..31647d3 100644 --- a/crates/bcm2837-lpa/src/systmr.rs +++ b/crates/bcm2837-lpa/src/systmr.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Control / Status"] pub cs: CS, @@ -16,31 +17,38 @@ pub struct RegisterBlock { #[doc = "0x18 - Compare channel 3"] pub c3: C3, } -#[doc = "CS (rw) register accessor: an alias for `Reg`"] +#[doc = "CS (rw) register accessor: Control / Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cs`] +module"] pub type CS = crate::Reg; #[doc = "Control / Status"] pub mod cs; -#[doc = "CLO (r) register accessor: an alias for `Reg`"] +#[doc = "CLO (r) register accessor: Lower 32 bits for the free running counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clo`] +module"] pub type CLO = crate::Reg; #[doc = "Lower 32 bits for the free running counter"] pub mod clo; -#[doc = "CHI (r) register accessor: an alias for `Reg`"] +#[doc = "CHI (r) register accessor: Higher 32 bits for the free running counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chi`] +module"] pub type CHI = crate::Reg; #[doc = "Higher 32 bits for the free running counter"] pub mod chi; -#[doc = "C0 (rw) register accessor: an alias for `Reg`"] +#[doc = "C0 (rw) register accessor: Compare channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c0`] +module"] pub type C0 = crate::Reg; #[doc = "Compare channel 0"] pub mod c0; -#[doc = "C1 (rw) register accessor: an alias for `Reg`"] +#[doc = "C1 (rw) register accessor: Compare channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c1`] +module"] pub type C1 = crate::Reg; #[doc = "Compare channel 1"] pub mod c1; -#[doc = "C2 (rw) register accessor: an alias for `Reg`"] +#[doc = "C2 (rw) register accessor: Compare channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c2`] +module"] pub type C2 = crate::Reg; #[doc = "Compare channel 2"] pub mod c2; -#[doc = "C3 (rw) register accessor: an alias for `Reg`"] +#[doc = "C3 (rw) register accessor: Compare channel 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c3`] +module"] pub type C3 = crate::Reg; #[doc = "Compare channel 3"] pub mod c3; diff --git a/crates/bcm2837-lpa/src/systmr/c0.rs b/crates/bcm2837-lpa/src/systmr/c0.rs index 20b09d2..18be8a7 100644 --- a/crates/bcm2837-lpa/src/systmr/c0.rs +++ b/crates/bcm2837-lpa/src/systmr/c0.rs @@ -1,59 +1,38 @@ #[doc = "Register `C0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Compare channel 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c0](index.html) module"] +#[doc = "Compare channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C0_SPEC; impl crate::RegisterSpec for C0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c0::R](R) reader structure"] -impl crate::Readable for C0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c0::W](W) writer structure"] +#[doc = "`read()` method returns [`c0::R`](R) reader structure"] +impl crate::Readable for C0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c0::W`](W) writer structure"] impl crate::Writable for C0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/systmr/c1.rs b/crates/bcm2837-lpa/src/systmr/c1.rs index 87cf5ed..bcf565c 100644 --- a/crates/bcm2837-lpa/src/systmr/c1.rs +++ b/crates/bcm2837-lpa/src/systmr/c1.rs @@ -1,59 +1,38 @@ #[doc = "Register `C1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Compare channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c1](index.html) module"] +#[doc = "Compare channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C1_SPEC; impl crate::RegisterSpec for C1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c1::R](R) reader structure"] -impl crate::Readable for C1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c1::W](W) writer structure"] +#[doc = "`read()` method returns [`c1::R`](R) reader structure"] +impl crate::Readable for C1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c1::W`](W) writer structure"] impl crate::Writable for C1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/systmr/c2.rs b/crates/bcm2837-lpa/src/systmr/c2.rs index 8c9c84b..e91e152 100644 --- a/crates/bcm2837-lpa/src/systmr/c2.rs +++ b/crates/bcm2837-lpa/src/systmr/c2.rs @@ -1,59 +1,38 @@ #[doc = "Register `C2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Compare channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c2](index.html) module"] +#[doc = "Compare channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C2_SPEC; impl crate::RegisterSpec for C2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c2::R](R) reader structure"] -impl crate::Readable for C2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c2::W](W) writer structure"] +#[doc = "`read()` method returns [`c2::R`](R) reader structure"] +impl crate::Readable for C2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c2::W`](W) writer structure"] impl crate::Writable for C2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/systmr/c3.rs b/crates/bcm2837-lpa/src/systmr/c3.rs index 0ac0aa2..a33918f 100644 --- a/crates/bcm2837-lpa/src/systmr/c3.rs +++ b/crates/bcm2837-lpa/src/systmr/c3.rs @@ -1,59 +1,38 @@ #[doc = "Register `C3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `C3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Compare channel 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [c3](index.html) module"] +#[doc = "Compare channel 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct C3_SPEC; impl crate::RegisterSpec for C3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [c3::R](R) reader structure"] -impl crate::Readable for C3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [c3::W](W) writer structure"] +#[doc = "`read()` method returns [`c3::R`](R) reader structure"] +impl crate::Readable for C3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c3::W`](W) writer structure"] impl crate::Writable for C3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/systmr/chi.rs b/crates/bcm2837-lpa/src/systmr/chi.rs index 9f162ef..7313db2 100644 --- a/crates/bcm2837-lpa/src/systmr/chi.rs +++ b/crates/bcm2837-lpa/src/systmr/chi.rs @@ -1,27 +1,22 @@ #[doc = "Register `CHI` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } -#[doc = "Higher 32 bits for the free running counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chi](index.html) module"] +#[doc = "Higher 32 bits for the free running counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CHI_SPEC; impl crate::RegisterSpec for CHI_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [chi::R](R) reader structure"] -impl crate::Readable for CHI_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`chi::R`](R) reader structure"] +impl crate::Readable for CHI_SPEC {} #[doc = "`reset()` method sets CHI to value 0"] impl crate::Resettable for CHI_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/systmr/clo.rs b/crates/bcm2837-lpa/src/systmr/clo.rs index 0a4b01f..43986b1 100644 --- a/crates/bcm2837-lpa/src/systmr/clo.rs +++ b/crates/bcm2837-lpa/src/systmr/clo.rs @@ -1,27 +1,22 @@ #[doc = "Register `CLO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } -#[doc = "Lower 32 bits for the free running counter\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clo](index.html) module"] +#[doc = "Lower 32 bits for the free running counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLO_SPEC; impl crate::RegisterSpec for CLO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clo::R](R) reader structure"] -impl crate::Readable for CLO_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`clo::R`](R) reader structure"] +impl crate::Readable for CLO_SPEC {} #[doc = "`reset()` method sets CLO to value 0"] impl crate::Resettable for CLO_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/systmr/cs.rs b/crates/bcm2837-lpa/src/systmr/cs.rs index dcb8ec2..3e1660d 100644 --- a/crates/bcm2837-lpa/src/systmr/cs.rs +++ b/crates/bcm2837-lpa/src/systmr/cs.rs @@ -1,55 +1,23 @@ #[doc = "Register `CS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `M0` reader - System timer match 0"] -pub type M0_R = crate::BitReader; +pub type M0_R = crate::BitReader; #[doc = "Field `M0` writer - System timer match 0"] -pub type M0_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +pub type M0_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `M1` reader - System timer match 1"] -pub type M1_R = crate::BitReader; +pub type M1_R = crate::BitReader; #[doc = "Field `M1` writer - System timer match 1"] -pub type M1_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +pub type M1_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `M2` reader - System timer match 2"] -pub type M2_R = crate::BitReader; +pub type M2_R = crate::BitReader; #[doc = "Field `M2` writer - System timer match 2"] -pub type M2_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +pub type M2_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; #[doc = "Field `M3` reader - System timer match 3"] -pub type M3_R = crate::BitReader; +pub type M3_R = crate::BitReader; #[doc = "Field `M3` writer - System timer match 3"] -pub type M3_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CS_SPEC, bool, O>; +pub type M3_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>; impl R { #[doc = "Bit 0 - System timer match 0"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { M3_R::new(((self.bits >> 3) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CS") + .field("m3", &format_args!("{}", self.m3().bit())) + .field("m2", &format_args!("{}", self.m2().bit())) + .field("m1", &format_args!("{}", self.m1().bit())) + .field("m0", &format_args!("{}", self.m0().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - System timer match 0"] #[inline(always)] #[must_use] - pub fn m0(&mut self) -> M0_W<0> { + pub fn m0(&mut self) -> M0_W { M0_W::new(self) } #[doc = "Bit 1 - System timer match 1"] #[inline(always)] #[must_use] - pub fn m1(&mut self) -> M1_W<1> { + pub fn m1(&mut self) -> M1_W { M1_W::new(self) } #[doc = "Bit 2 - System timer match 2"] #[inline(always)] #[must_use] - pub fn m2(&mut self) -> M2_W<2> { + pub fn m2(&mut self) -> M2_W { M2_W::new(self) } #[doc = "Bit 3 - System timer match 3"] #[inline(always)] #[must_use] - pub fn m3(&mut self) -> M3_W<3> { + pub fn m3(&mut self) -> M3_W { M3_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control / Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs](index.html) module"] +#[doc = "Control / Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CS_SPEC; impl crate::RegisterSpec for CS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cs::R](R) reader structure"] -impl crate::Readable for CS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"] +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0f; } diff --git a/crates/bcm2837-lpa/src/uart0.rs b/crates/bcm2837-lpa/src/uart0.rs index aade8a9..a12a501 100644 --- a/crates/bcm2837-lpa/src/uart0.rs +++ b/crates/bcm2837-lpa/src/uart0.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Data Register"] pub dr: DR, @@ -41,59 +42,73 @@ impl RegisterBlock { unsafe { &*(self as *const Self).cast::().add(4usize).cast() } } } -#[doc = "DR (rw) register accessor: an alias for `Reg`"] +#[doc = "DR (rw) register accessor: Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`] +module"] pub type DR = crate::Reg; #[doc = "Data Register"] pub mod dr; -#[doc = "RSR (r) register accessor: an alias for `Reg`"] +#[doc = "RSR (r) register accessor: Receive Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsr`] +module"] pub type RSR = crate::Reg; #[doc = "Receive Status Register"] pub mod rsr; -#[doc = "ECR (w) register accessor: an alias for `Reg`"] +#[doc = "ECR (w) register accessor: Error Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr`] +module"] pub type ECR = crate::Reg; #[doc = "Error Clear Register"] pub mod ecr; -#[doc = "FR (rw) register accessor: an alias for `Reg`"] +#[doc = "FR (rw) register accessor: Flag Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fr`] +module"] pub type FR = crate::Reg; #[doc = "Flag Register"] pub mod fr; -#[doc = "IBRD (rw) register accessor: an alias for `Reg`"] +#[doc = "IBRD (rw) register accessor: Integer Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibrd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibrd`] +module"] pub type IBRD = crate::Reg; #[doc = "Integer Baud Rate Register"] pub mod ibrd; -#[doc = "FBRD (rw) register accessor: an alias for `Reg`"] +#[doc = "FBRD (rw) register accessor: Fractional Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fbrd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fbrd`] +module"] pub type FBRD = crate::Reg; #[doc = "Fractional Baud Rate Register"] pub mod fbrd; -#[doc = "LCR_H (rw) register accessor: an alias for `Reg`"] +#[doc = "LCR_H (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr_h::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr_h::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr_h`] +module"] pub type LCR_H = crate::Reg; #[doc = "Line Control Register"] pub mod lcr_h; -#[doc = "CR (rw) register accessor: an alias for `Reg`"] +#[doc = "CR (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "IFLS (rw) register accessor: an alias for `Reg`"] +#[doc = "IFLS (rw) register accessor: Interrupt FIFO Level Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifls::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifls::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ifls`] +module"] pub type IFLS = crate::Reg; #[doc = "Interrupt FIFO Level Select Register"] pub mod ifls; -#[doc = "IMSC (rw) register accessor: an alias for `Reg`"] +#[doc = "IMSC (rw) register accessor: Interrupt Mask set_Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imsc`] +module"] pub type IMSC = crate::Reg; #[doc = "Interrupt Mask set_Clear Register"] pub mod imsc; -#[doc = "RIS (r) register accessor: an alias for `Reg`"] +#[doc = "RIS (r) register accessor: Raw Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`] +module"] pub type RIS = crate::Reg; #[doc = "Raw Interrupt Status Register"] pub mod ris; -#[doc = "MIS (r) register accessor: an alias for `Reg`"] +#[doc = "MIS (r) register accessor: Masked Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`] +module"] pub type MIS = crate::Reg; #[doc = "Masked Interrupt Status Register"] pub mod mis; -#[doc = "ICR (w) register accessor: an alias for `Reg`"] +#[doc = "ICR (w) register accessor: Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`] +module"] pub type ICR = crate::Reg; #[doc = "Interrupt Clear Register"] pub mod icr; -#[doc = "DMACR (rw) register accessor: an alias for `Reg`"] +#[doc = "DMACR (rw) register accessor: DMA Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmacr`] +module"] pub type DMACR = crate::Reg; #[doc = "DMA Control Register"] pub mod dmacr; diff --git a/crates/bcm2837-lpa/src/uart0/cr.rs b/crates/bcm2837-lpa/src/uart0/cr.rs index 6c47a00..bfbc283 100644 --- a/crates/bcm2837-lpa/src/uart0/cr.rs +++ b/crates/bcm2837-lpa/src/uart0/cr.rs @@ -1,75 +1,43 @@ #[doc = "Register `CR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UARTEN` reader - UARTEN"] -pub type UARTEN_R = crate::BitReader; +pub type UARTEN_R = crate::BitReader; #[doc = "Field `UARTEN` writer - UARTEN"] -pub type UARTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type UARTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SIREN` reader - SIREN"] -pub type SIREN_R = crate::BitReader; +pub type SIREN_R = crate::BitReader; #[doc = "Field `SIREN` writer - SIREN"] -pub type SIREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type SIREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SIRLP` reader - SIRLP"] -pub type SIRLP_R = crate::BitReader; +pub type SIRLP_R = crate::BitReader; #[doc = "Field `SIRLP` writer - SIRLP"] -pub type SIRLP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type SIRLP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXE` reader - TXE"] -pub type TXE_R = crate::BitReader; +pub type TXE_R = crate::BitReader; #[doc = "Field `TXE` writer - TXE"] -pub type TXE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type TXE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXE` reader - RXE"] -pub type RXE_R = crate::BitReader; +pub type RXE_R = crate::BitReader; #[doc = "Field `RXE` writer - RXE"] -pub type RXE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type RXE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTR` reader - DTR"] -pub type DTR_R = crate::BitReader; +pub type DTR_R = crate::BitReader; #[doc = "Field `DTR` writer - DTR"] -pub type DTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type DTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTS` reader - RTS"] -pub type RTS_R = crate::BitReader; +pub type RTS_R = crate::BitReader; #[doc = "Field `RTS` writer - RTS"] -pub type RTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTSEN` reader - RTSEN"] -pub type RTSEN_R = crate::BitReader; +pub type RTSEN_R = crate::BitReader; #[doc = "Field `RTSEN` writer - RTSEN"] -pub type RTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type RTSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTSEN` reader - CTSEN"] -pub type CTSEN_R = crate::BitReader; +pub type CTSEN_R = crate::BitReader; #[doc = "Field `CTSEN` writer - CTSEN"] -pub type CTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>; +pub type CTSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - UARTEN"] #[inline(always)] @@ -117,80 +85,101 @@ impl R { CTSEN_R::new(((self.bits >> 15) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CR") + .field("uarten", &format_args!("{}", self.uarten().bit())) + .field("siren", &format_args!("{}", self.siren().bit())) + .field("sirlp", &format_args!("{}", self.sirlp().bit())) + .field("txe", &format_args!("{}", self.txe().bit())) + .field("rxe", &format_args!("{}", self.rxe().bit())) + .field("dtr", &format_args!("{}", self.dtr().bit())) + .field("rts", &format_args!("{}", self.rts().bit())) + .field("rtsen", &format_args!("{}", self.rtsen().bit())) + .field("ctsen", &format_args!("{}", self.ctsen().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - UARTEN"] #[inline(always)] #[must_use] - pub fn uarten(&mut self) -> UARTEN_W<0> { + pub fn uarten(&mut self) -> UARTEN_W { UARTEN_W::new(self) } #[doc = "Bit 1 - SIREN"] #[inline(always)] #[must_use] - pub fn siren(&mut self) -> SIREN_W<1> { + pub fn siren(&mut self) -> SIREN_W { SIREN_W::new(self) } #[doc = "Bit 2 - SIRLP"] #[inline(always)] #[must_use] - pub fn sirlp(&mut self) -> SIRLP_W<2> { + pub fn sirlp(&mut self) -> SIRLP_W { SIRLP_W::new(self) } #[doc = "Bit 8 - TXE"] #[inline(always)] #[must_use] - pub fn txe(&mut self) -> TXE_W<8> { + pub fn txe(&mut self) -> TXE_W { TXE_W::new(self) } #[doc = "Bit 9 - RXE"] #[inline(always)] #[must_use] - pub fn rxe(&mut self) -> RXE_W<9> { + pub fn rxe(&mut self) -> RXE_W { RXE_W::new(self) } #[doc = "Bit 10 - DTR"] #[inline(always)] #[must_use] - pub fn dtr(&mut self) -> DTR_W<10> { + pub fn dtr(&mut self) -> DTR_W { DTR_W::new(self) } #[doc = "Bit 11 - RTS"] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W<11> { + pub fn rts(&mut self) -> RTS_W { RTS_W::new(self) } #[doc = "Bit 14 - RTSEN"] #[inline(always)] #[must_use] - pub fn rtsen(&mut self) -> RTSEN_W<14> { + pub fn rtsen(&mut self) -> RTSEN_W { RTSEN_W::new(self) } #[doc = "Bit 15 - CTSEN"] #[inline(always)] #[must_use] - pub fn ctsen(&mut self) -> CTSEN_W<15> { + pub fn ctsen(&mut self) -> CTSEN_W { CTSEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cr::R](R) reader structure"] -impl crate::Readable for CR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`read()` method returns [`cr::R`](R) reader structure"] +impl crate::Readable for CR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart0/dmacr.rs b/crates/bcm2837-lpa/src/uart0/dmacr.rs index 8bd3632..40efa50 100644 --- a/crates/bcm2837-lpa/src/uart0/dmacr.rs +++ b/crates/bcm2837-lpa/src/uart0/dmacr.rs @@ -1,51 +1,19 @@ #[doc = "Register `DMACR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMACR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXDMAE` reader - RXDMAE"] -pub type RXDMAE_R = crate::BitReader; +pub type RXDMAE_R = crate::BitReader; #[doc = "Field `RXDMAE` writer - RXDMAE"] -pub type RXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +pub type RXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXDMAE` reader - TXDMAE"] -pub type TXDMAE_R = crate::BitReader; +pub type TXDMAE_R = crate::BitReader; #[doc = "Field `TXDMAE` writer - TXDMAE"] -pub type TXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +pub type TXDMAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMAONERR` reader - DMAONERR"] -pub type DMAONERR_R = crate::BitReader; +pub type DMAONERR_R = crate::BitReader; #[doc = "Field `DMAONERR` writer - DMAONERR"] -pub type DMAONERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>; +pub type DMAONERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - RXDMAE"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { DMAONERR_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMACR") + .field("rxdmae", &format_args!("{}", self.rxdmae().bit())) + .field("txdmae", &format_args!("{}", self.txdmae().bit())) + .field("dmaonerr", &format_args!("{}", self.dmaonerr().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - RXDMAE"] #[inline(always)] #[must_use] - pub fn rxdmae(&mut self) -> RXDMAE_W<0> { + pub fn rxdmae(&mut self) -> RXDMAE_W { RXDMAE_W::new(self) } #[doc = "Bit 1 - TXDMAE"] #[inline(always)] #[must_use] - pub fn txdmae(&mut self) -> TXDMAE_W<1> { + pub fn txdmae(&mut self) -> TXDMAE_W { TXDMAE_W::new(self) } #[doc = "Bit 2 - DMAONERR"] #[inline(always)] #[must_use] - pub fn dmaonerr(&mut self) -> DMAONERR_W<2> { + pub fn dmaonerr(&mut self) -> DMAONERR_W { DMAONERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacr](index.html) module"] +#[doc = "DMA Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMACR_SPEC; impl crate::RegisterSpec for DMACR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dmacr::R](R) reader structure"] -impl crate::Readable for DMACR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dmacr::W](W) writer structure"] +#[doc = "`read()` method returns [`dmacr::R`](R) reader structure"] +impl crate::Readable for DMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dmacr::W`](W) writer structure"] impl crate::Writable for DMACR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart0/dr.rs b/crates/bcm2837-lpa/src/uart0/dr.rs index 236d30b..3c7f81e 100644 --- a/crates/bcm2837-lpa/src/uart0/dr.rs +++ b/crates/bcm2837-lpa/src/uart0/dr.rs @@ -1,59 +1,27 @@ #[doc = "Register `DR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - DATA"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - DATA"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DR_SPEC, u8, u8, 8, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `FE` reader - FE"] -pub type FE_R = crate::BitReader; +pub type FE_R = crate::BitReader; #[doc = "Field `FE` writer - FE"] -pub type FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +pub type FE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PE` reader - PE"] -pub type PE_R = crate::BitReader; +pub type PE_R = crate::BitReader; #[doc = "Field `PE` writer - PE"] -pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +pub type PE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BE` reader - BE"] -pub type BE_R = crate::BitReader; +pub type BE_R = crate::BitReader; #[doc = "Field `BE` writer - BE"] -pub type BE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +pub type BE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OE` reader - OE"] -pub type OE_R = crate::BitReader; +pub type OE_R = crate::BitReader; #[doc = "Field `OE` writer - OE"] -pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>; +pub type OE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:7 - DATA"] #[inline(always)] @@ -81,56 +49,73 @@ impl R { OE_R::new(((self.bits >> 11) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DR") + .field("data", &format_args!("{}", self.data().bits())) + .field("fe", &format_args!("{}", self.fe().bit())) + .field("pe", &format_args!("{}", self.pe().bit())) + .field("be", &format_args!("{}", self.be().bit())) + .field("oe", &format_args!("{}", self.oe().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - DATA"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } #[doc = "Bit 8 - FE"] #[inline(always)] #[must_use] - pub fn fe(&mut self) -> FE_W<8> { + pub fn fe(&mut self) -> FE_W { FE_W::new(self) } #[doc = "Bit 9 - PE"] #[inline(always)] #[must_use] - pub fn pe(&mut self) -> PE_W<9> { + pub fn pe(&mut self) -> PE_W { PE_W::new(self) } #[doc = "Bit 10 - BE"] #[inline(always)] #[must_use] - pub fn be(&mut self) -> BE_W<10> { + pub fn be(&mut self) -> BE_W { BE_W::new(self) } #[doc = "Bit 11 - OE"] #[inline(always)] #[must_use] - pub fn oe(&mut self) -> OE_W<11> { + pub fn oe(&mut self) -> OE_W { OE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"] +#[doc = "Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DR_SPEC; impl crate::RegisterSpec for DR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dr::R](R) reader structure"] -impl crate::Readable for DR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"] +#[doc = "`read()` method returns [`dr::R`](R) reader structure"] +impl crate::Readable for DR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"] impl crate::Writable for DR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart0/ecr.rs b/crates/bcm2837-lpa/src/uart0/ecr.rs index f469e97..97efb0b 100644 --- a/crates/bcm2837-lpa/src/uart0/ecr.rs +++ b/crates/bcm2837-lpa/src/uart0/ecr.rs @@ -1,72 +1,61 @@ #[doc = "Register `ECR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FE` writer - FE"] -pub type FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +pub type FE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PE` writer - PE"] -pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +pub type PE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BE` writer - BE"] -pub type BE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +pub type BE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OE` writer - OE"] -pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ECR_SPEC, bool, O>; +pub type OE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - FE"] #[inline(always)] #[must_use] - pub fn fe(&mut self) -> FE_W<0> { + pub fn fe(&mut self) -> FE_W { FE_W::new(self) } #[doc = "Bit 1 - PE"] #[inline(always)] #[must_use] - pub fn pe(&mut self) -> PE_W<1> { + pub fn pe(&mut self) -> PE_W { PE_W::new(self) } #[doc = "Bit 2 - BE"] #[inline(always)] #[must_use] - pub fn be(&mut self) -> BE_W<2> { + pub fn be(&mut self) -> BE_W { BE_W::new(self) } #[doc = "Bit 3 - OE"] #[inline(always)] #[must_use] - pub fn oe(&mut self) -> OE_W<3> { + pub fn oe(&mut self) -> OE_W { OE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Error Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecr](index.html) module"] +#[doc = "Error Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ECR_SPEC; impl crate::RegisterSpec for ECR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ecr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ecr::W`](W) writer structure"] impl crate::Writable for ECR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart0/fbrd.rs b/crates/bcm2837-lpa/src/uart0/fbrd.rs index 14ae9a3..e0fe228 100644 --- a/crates/bcm2837-lpa/src/uart0/fbrd.rs +++ b/crates/bcm2837-lpa/src/uart0/fbrd.rs @@ -1,43 +1,11 @@ #[doc = "Register `FBRD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FBRD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BAUDDIVFRAC` reader - BAUDDIVFRAC"] -pub type BAUDDIVFRAC_R = crate::FieldReader; +pub type BAUDDIVFRAC_R = crate::FieldReader; #[doc = "Field `BAUDDIVFRAC` writer - BAUDDIVFRAC"] -pub type BAUDDIVFRAC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FBRD_SPEC, u8, u8, 6, O>; +pub type BAUDDIVFRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5 - BAUDDIVFRAC"] #[inline(always)] @@ -45,32 +13,48 @@ impl R { BAUDDIVFRAC_R::new((self.bits & 0x3f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FBRD") + .field( + "bauddivfrac", + &format_args!("{}", self.bauddivfrac().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:5 - BAUDDIVFRAC"] #[inline(always)] #[must_use] - pub fn bauddivfrac(&mut self) -> BAUDDIVFRAC_W<0> { + pub fn bauddivfrac(&mut self) -> BAUDDIVFRAC_W { BAUDDIVFRAC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Fractional Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fbrd](index.html) module"] +#[doc = "Fractional Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fbrd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FBRD_SPEC; impl crate::RegisterSpec for FBRD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fbrd::R](R) reader structure"] -impl crate::Readable for FBRD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fbrd::W](W) writer structure"] +#[doc = "`read()` method returns [`fbrd::R`](R) reader structure"] +impl crate::Readable for FBRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fbrd::W`](W) writer structure"] impl crate::Writable for FBRD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart0/fr.rs b/crates/bcm2837-lpa/src/uart0/fr.rs index 641becc..d70703c 100644 --- a/crates/bcm2837-lpa/src/uart0/fr.rs +++ b/crates/bcm2837-lpa/src/uart0/fr.rs @@ -1,75 +1,43 @@ #[doc = "Register `FR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CTS` reader - CTS"] -pub type CTS_R = crate::BitReader; +pub type CTS_R = crate::BitReader; #[doc = "Field `CTS` writer - CTS"] -pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type CTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSR` reader - DSR"] -pub type DSR_R = crate::BitReader; +pub type DSR_R = crate::BitReader; #[doc = "Field `DSR` writer - DSR"] -pub type DSR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type DSR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCD` reader - DCD"] -pub type DCD_R = crate::BitReader; +pub type DCD_R = crate::BitReader; #[doc = "Field `DCD` writer - DCD"] -pub type DCD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type DCD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUSY` reader - BUSY"] -pub type BUSY_R = crate::BitReader; +pub type BUSY_R = crate::BitReader; #[doc = "Field `BUSY` writer - BUSY"] -pub type BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type BUSY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFE` reader - RXFE"] -pub type RXFE_R = crate::BitReader; +pub type RXFE_R = crate::BitReader; #[doc = "Field `RXFE` writer - RXFE"] -pub type RXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type RXFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFF` reader - TXFF"] -pub type TXFF_R = crate::BitReader; +pub type TXFF_R = crate::BitReader; #[doc = "Field `TXFF` writer - TXFF"] -pub type TXFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type TXFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFF` reader - RXFF"] -pub type RXFF_R = crate::BitReader; +pub type RXFF_R = crate::BitReader; #[doc = "Field `RXFF` writer - RXFF"] -pub type RXFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type RXFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFE` reader - TXFE"] -pub type TXFE_R = crate::BitReader; +pub type TXFE_R = crate::BitReader; #[doc = "Field `TXFE` writer - TXFE"] -pub type TXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type TXFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RI` reader - RI"] -pub type RI_R = crate::BitReader; +pub type RI_R = crate::BitReader; #[doc = "Field `RI` writer - RI"] -pub type RI_W<'a, const O: u8> = crate::BitWriter<'a, u32, FR_SPEC, bool, O>; +pub type RI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - CTS"] #[inline(always)] @@ -117,80 +85,101 @@ impl R { RI_R::new(((self.bits >> 8) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FR") + .field("cts", &format_args!("{}", self.cts().bit())) + .field("dsr", &format_args!("{}", self.dsr().bit())) + .field("dcd", &format_args!("{}", self.dcd().bit())) + .field("busy", &format_args!("{}", self.busy().bit())) + .field("rxfe", &format_args!("{}", self.rxfe().bit())) + .field("txff", &format_args!("{}", self.txff().bit())) + .field("rxff", &format_args!("{}", self.rxff().bit())) + .field("txfe", &format_args!("{}", self.txfe().bit())) + .field("ri", &format_args!("{}", self.ri().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - CTS"] #[inline(always)] #[must_use] - pub fn cts(&mut self) -> CTS_W<0> { + pub fn cts(&mut self) -> CTS_W { CTS_W::new(self) } #[doc = "Bit 1 - DSR"] #[inline(always)] #[must_use] - pub fn dsr(&mut self) -> DSR_W<1> { + pub fn dsr(&mut self) -> DSR_W { DSR_W::new(self) } #[doc = "Bit 2 - DCD"] #[inline(always)] #[must_use] - pub fn dcd(&mut self) -> DCD_W<2> { + pub fn dcd(&mut self) -> DCD_W { DCD_W::new(self) } #[doc = "Bit 3 - BUSY"] #[inline(always)] #[must_use] - pub fn busy(&mut self) -> BUSY_W<3> { + pub fn busy(&mut self) -> BUSY_W { BUSY_W::new(self) } #[doc = "Bit 4 - RXFE"] #[inline(always)] #[must_use] - pub fn rxfe(&mut self) -> RXFE_W<4> { + pub fn rxfe(&mut self) -> RXFE_W { RXFE_W::new(self) } #[doc = "Bit 5 - TXFF"] #[inline(always)] #[must_use] - pub fn txff(&mut self) -> TXFF_W<5> { + pub fn txff(&mut self) -> TXFF_W { TXFF_W::new(self) } #[doc = "Bit 6 - RXFF"] #[inline(always)] #[must_use] - pub fn rxff(&mut self) -> RXFF_W<6> { + pub fn rxff(&mut self) -> RXFF_W { RXFF_W::new(self) } #[doc = "Bit 7 - TXFE"] #[inline(always)] #[must_use] - pub fn txfe(&mut self) -> TXFE_W<7> { + pub fn txfe(&mut self) -> TXFE_W { TXFE_W::new(self) } #[doc = "Bit 8 - RI"] #[inline(always)] #[must_use] - pub fn ri(&mut self) -> RI_W<8> { + pub fn ri(&mut self) -> RI_W { RI_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fr](index.html) module"] +#[doc = "Flag Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FR_SPEC; impl crate::RegisterSpec for FR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fr::R](R) reader structure"] -impl crate::Readable for FR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fr::W](W) writer structure"] +#[doc = "`read()` method returns [`fr::R`](R) reader structure"] +impl crate::Readable for FR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fr::W`](W) writer structure"] impl crate::Writable for FR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart0/ibrd.rs b/crates/bcm2837-lpa/src/uart0/ibrd.rs index 65af80e..07441c8 100644 --- a/crates/bcm2837-lpa/src/uart0/ibrd.rs +++ b/crates/bcm2837-lpa/src/uart0/ibrd.rs @@ -1,43 +1,11 @@ #[doc = "Register `IBRD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IBRD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BAUDDIVINT` reader - BAUDDIVINT"] -pub type BAUDDIVINT_R = crate::FieldReader; +pub type BAUDDIVINT_R = crate::FieldReader; #[doc = "Field `BAUDDIVINT` writer - BAUDDIVINT"] -pub type BAUDDIVINT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IBRD_SPEC, u16, u16, 16, O>; +pub type BAUDDIVINT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - BAUDDIVINT"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { BAUDDIVINT_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IBRD") + .field("bauddivint", &format_args!("{}", self.bauddivint().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - BAUDDIVINT"] #[inline(always)] #[must_use] - pub fn bauddivint(&mut self) -> BAUDDIVINT_W<0> { + pub fn bauddivint(&mut self) -> BAUDDIVINT_W { BAUDDIVINT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Integer Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ibrd](index.html) module"] +#[doc = "Integer Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibrd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IBRD_SPEC; impl crate::RegisterSpec for IBRD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ibrd::R](R) reader structure"] -impl crate::Readable for IBRD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ibrd::W](W) writer structure"] +#[doc = "`read()` method returns [`ibrd::R`](R) reader structure"] +impl crate::Readable for IBRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ibrd::W`](W) writer structure"] impl crate::Writable for IBRD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart0/icr.rs b/crates/bcm2837-lpa/src/uart0/icr.rs index 509869e..e69a3e9 100644 --- a/crates/bcm2837-lpa/src/uart0/icr.rs +++ b/crates/bcm2837-lpa/src/uart0/icr.rs @@ -1,128 +1,117 @@ #[doc = "Register `ICR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RIMIC` writer - RIMIC"] -pub type RIMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type RIMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTSMIC` writer - CTSMIC"] -pub type CTSMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type CTSMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCDMIC` writer - DCDMIC"] -pub type DCDMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type DCDMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSRMIC` writer - DSRMIC"] -pub type DSRMIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type DSRMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXIC` writer - RXIC"] -pub type RXIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type RXIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXIC` writer - TXIC"] -pub type TXIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type TXIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTIC` writer - RTIC"] -pub type RTIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type RTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEIC` writer - FEIC"] -pub type FEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type FEIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEIC` writer - PEIC"] -pub type PEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type PEIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BEIC` writer - BEIC"] -pub type BEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type BEIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEIC` writer - OEIC"] -pub type OEIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>; +pub type OEIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} impl W { #[doc = "Bit 0 - RIMIC"] #[inline(always)] #[must_use] - pub fn rimic(&mut self) -> RIMIC_W<0> { + pub fn rimic(&mut self) -> RIMIC_W { RIMIC_W::new(self) } #[doc = "Bit 1 - CTSMIC"] #[inline(always)] #[must_use] - pub fn ctsmic(&mut self) -> CTSMIC_W<1> { + pub fn ctsmic(&mut self) -> CTSMIC_W { CTSMIC_W::new(self) } #[doc = "Bit 2 - DCDMIC"] #[inline(always)] #[must_use] - pub fn dcdmic(&mut self) -> DCDMIC_W<2> { + pub fn dcdmic(&mut self) -> DCDMIC_W { DCDMIC_W::new(self) } #[doc = "Bit 3 - DSRMIC"] #[inline(always)] #[must_use] - pub fn dsrmic(&mut self) -> DSRMIC_W<3> { + pub fn dsrmic(&mut self) -> DSRMIC_W { DSRMIC_W::new(self) } #[doc = "Bit 4 - RXIC"] #[inline(always)] #[must_use] - pub fn rxic(&mut self) -> RXIC_W<4> { + pub fn rxic(&mut self) -> RXIC_W { RXIC_W::new(self) } #[doc = "Bit 5 - TXIC"] #[inline(always)] #[must_use] - pub fn txic(&mut self) -> TXIC_W<5> { + pub fn txic(&mut self) -> TXIC_W { TXIC_W::new(self) } #[doc = "Bit 6 - RTIC"] #[inline(always)] #[must_use] - pub fn rtic(&mut self) -> RTIC_W<6> { + pub fn rtic(&mut self) -> RTIC_W { RTIC_W::new(self) } #[doc = "Bit 7 - FEIC"] #[inline(always)] #[must_use] - pub fn feic(&mut self) -> FEIC_W<7> { + pub fn feic(&mut self) -> FEIC_W { FEIC_W::new(self) } #[doc = "Bit 8 - PEIC"] #[inline(always)] #[must_use] - pub fn peic(&mut self) -> PEIC_W<8> { + pub fn peic(&mut self) -> PEIC_W { PEIC_W::new(self) } #[doc = "Bit 9 - BEIC"] #[inline(always)] #[must_use] - pub fn beic(&mut self) -> BEIC_W<9> { + pub fn beic(&mut self) -> BEIC_W { BEIC_W::new(self) } #[doc = "Bit 10 - OEIC"] #[inline(always)] #[must_use] - pub fn oeic(&mut self) -> OEIC_W<10> { + pub fn oeic(&mut self) -> OEIC_W { OEIC_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"] +#[doc = "Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ICR_SPEC; impl crate::RegisterSpec for ICR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [icr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] impl crate::Writable for ICR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart0/ifls.rs b/crates/bcm2837-lpa/src/uart0/ifls.rs index 0cfe8d5..5119af0 100644 --- a/crates/bcm2837-lpa/src/uart0/ifls.rs +++ b/crates/bcm2837-lpa/src/uart0/ifls.rs @@ -1,47 +1,15 @@ #[doc = "Register `IFLS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IFLS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXIFLSEL` reader - TXIFLSEL"] -pub type TXIFLSEL_R = crate::FieldReader; +pub type TXIFLSEL_R = crate::FieldReader; #[doc = "Field `TXIFLSEL` writer - TXIFLSEL"] -pub type TXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFLS_SPEC, u8, u8, 3, O>; +pub type TXIFLSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `RXIFLSEL` reader - RXIFLSEL"] -pub type RXIFLSEL_R = crate::FieldReader; +pub type RXIFLSEL_R = crate::FieldReader; #[doc = "Field `RXIFLSEL` writer - RXIFLSEL"] -pub type RXIFLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFLS_SPEC, u8, u8, 3, O>; +pub type RXIFLSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:2 - TXIFLSEL"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { RXIFLSEL_R::new(((self.bits >> 3) & 7) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IFLS") + .field("txiflsel", &format_args!("{}", self.txiflsel().bits())) + .field("rxiflsel", &format_args!("{}", self.rxiflsel().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - TXIFLSEL"] #[inline(always)] #[must_use] - pub fn txiflsel(&mut self) -> TXIFLSEL_W<0> { + pub fn txiflsel(&mut self) -> TXIFLSEL_W { TXIFLSEL_W::new(self) } #[doc = "Bits 3:5 - RXIFLSEL"] #[inline(always)] #[must_use] - pub fn rxiflsel(&mut self) -> RXIFLSEL_W<3> { + pub fn rxiflsel(&mut self) -> RXIFLSEL_W { RXIFLSEL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt FIFO Level Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifls](index.html) module"] +#[doc = "Interrupt FIFO Level Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifls::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifls::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IFLS_SPEC; impl crate::RegisterSpec for IFLS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ifls::R](R) reader structure"] -impl crate::Readable for IFLS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ifls::W](W) writer structure"] +#[doc = "`read()` method returns [`ifls::R`](R) reader structure"] +impl crate::Readable for IFLS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ifls::W`](W) writer structure"] impl crate::Writable for IFLS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart0/imsc.rs b/crates/bcm2837-lpa/src/uart0/imsc.rs index 1b0fb46..80b23a4 100644 --- a/crates/bcm2837-lpa/src/uart0/imsc.rs +++ b/crates/bcm2837-lpa/src/uart0/imsc.rs @@ -1,83 +1,51 @@ #[doc = "Register `IMSC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IMSC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RIMIM` reader - RIMIM"] -pub type RIMIM_R = crate::BitReader; +pub type RIMIM_R = crate::BitReader; #[doc = "Field `RIMIM` writer - RIMIM"] -pub type RIMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type RIMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTSMIM` reader - CTSMIM"] -pub type CTSMIM_R = crate::BitReader; +pub type CTSMIM_R = crate::BitReader; #[doc = "Field `CTSMIM` writer - CTSMIM"] -pub type CTSMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type CTSMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCDMIM` reader - DCDMIM"] -pub type DCDMIM_R = crate::BitReader; +pub type DCDMIM_R = crate::BitReader; #[doc = "Field `DCDMIM` writer - DCDMIM"] -pub type DCDMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type DCDMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSRMIM` reader - DSRMIM"] -pub type DSRMIM_R = crate::BitReader; +pub type DSRMIM_R = crate::BitReader; #[doc = "Field `DSRMIM` writer - DSRMIM"] -pub type DSRMIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type DSRMIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXIM` reader - RXIM"] -pub type RXIM_R = crate::BitReader; +pub type RXIM_R = crate::BitReader; #[doc = "Field `RXIM` writer - RXIM"] -pub type RXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type RXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXIM` reader - TXIM"] -pub type TXIM_R = crate::BitReader; +pub type TXIM_R = crate::BitReader; #[doc = "Field `TXIM` writer - TXIM"] -pub type TXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type TXIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTIM` reader - RTIM"] -pub type RTIM_R = crate::BitReader; +pub type RTIM_R = crate::BitReader; #[doc = "Field `RTIM` writer - RTIM"] -pub type RTIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type RTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEIM` reader - FEIM"] -pub type FEIM_R = crate::BitReader; +pub type FEIM_R = crate::BitReader; #[doc = "Field `FEIM` writer - FEIM"] -pub type FEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type FEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEIM` reader - PEIM"] -pub type PEIM_R = crate::BitReader; +pub type PEIM_R = crate::BitReader; #[doc = "Field `PEIM` writer - PEIM"] -pub type PEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type PEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BEIM` reader - BEIM"] -pub type BEIM_R = crate::BitReader; +pub type BEIM_R = crate::BitReader; #[doc = "Field `BEIM` writer - BEIM"] -pub type BEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type BEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEIM` reader - OEIM"] -pub type OEIM_R = crate::BitReader; +pub type OEIM_R = crate::BitReader; #[doc = "Field `OEIM` writer - OEIM"] -pub type OEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>; +pub type OEIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - RIMIM"] #[inline(always)] @@ -135,92 +103,115 @@ impl R { OEIM_R::new(((self.bits >> 10) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IMSC") + .field("rimim", &format_args!("{}", self.rimim().bit())) + .field("ctsmim", &format_args!("{}", self.ctsmim().bit())) + .field("dcdmim", &format_args!("{}", self.dcdmim().bit())) + .field("dsrmim", &format_args!("{}", self.dsrmim().bit())) + .field("rxim", &format_args!("{}", self.rxim().bit())) + .field("txim", &format_args!("{}", self.txim().bit())) + .field("rtim", &format_args!("{}", self.rtim().bit())) + .field("feim", &format_args!("{}", self.feim().bit())) + .field("peim", &format_args!("{}", self.peim().bit())) + .field("beim", &format_args!("{}", self.beim().bit())) + .field("oeim", &format_args!("{}", self.oeim().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - RIMIM"] #[inline(always)] #[must_use] - pub fn rimim(&mut self) -> RIMIM_W<0> { + pub fn rimim(&mut self) -> RIMIM_W { RIMIM_W::new(self) } #[doc = "Bit 1 - CTSMIM"] #[inline(always)] #[must_use] - pub fn ctsmim(&mut self) -> CTSMIM_W<1> { + pub fn ctsmim(&mut self) -> CTSMIM_W { CTSMIM_W::new(self) } #[doc = "Bit 2 - DCDMIM"] #[inline(always)] #[must_use] - pub fn dcdmim(&mut self) -> DCDMIM_W<2> { + pub fn dcdmim(&mut self) -> DCDMIM_W { DCDMIM_W::new(self) } #[doc = "Bit 3 - DSRMIM"] #[inline(always)] #[must_use] - pub fn dsrmim(&mut self) -> DSRMIM_W<3> { + pub fn dsrmim(&mut self) -> DSRMIM_W { DSRMIM_W::new(self) } #[doc = "Bit 4 - RXIM"] #[inline(always)] #[must_use] - pub fn rxim(&mut self) -> RXIM_W<4> { + pub fn rxim(&mut self) -> RXIM_W { RXIM_W::new(self) } #[doc = "Bit 5 - TXIM"] #[inline(always)] #[must_use] - pub fn txim(&mut self) -> TXIM_W<5> { + pub fn txim(&mut self) -> TXIM_W { TXIM_W::new(self) } #[doc = "Bit 6 - RTIM"] #[inline(always)] #[must_use] - pub fn rtim(&mut self) -> RTIM_W<6> { + pub fn rtim(&mut self) -> RTIM_W { RTIM_W::new(self) } #[doc = "Bit 7 - FEIM"] #[inline(always)] #[must_use] - pub fn feim(&mut self) -> FEIM_W<7> { + pub fn feim(&mut self) -> FEIM_W { FEIM_W::new(self) } #[doc = "Bit 8 - PEIM"] #[inline(always)] #[must_use] - pub fn peim(&mut self) -> PEIM_W<8> { + pub fn peim(&mut self) -> PEIM_W { PEIM_W::new(self) } #[doc = "Bit 9 - BEIM"] #[inline(always)] #[must_use] - pub fn beim(&mut self) -> BEIM_W<9> { + pub fn beim(&mut self) -> BEIM_W { BEIM_W::new(self) } #[doc = "Bit 10 - OEIM"] #[inline(always)] #[must_use] - pub fn oeim(&mut self) -> OEIM_W<10> { + pub fn oeim(&mut self) -> OEIM_W { OEIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Mask set_Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imsc](index.html) module"] +#[doc = "Interrupt Mask set_Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imsc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMSC_SPEC; impl crate::RegisterSpec for IMSC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imsc::R](R) reader structure"] -impl crate::Readable for IMSC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [imsc::W](W) writer structure"] +#[doc = "`read()` method returns [`imsc::R`](R) reader structure"] +impl crate::Readable for IMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`imsc::W`](W) writer structure"] impl crate::Writable for IMSC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart0/lcr_h.rs b/crates/bcm2837-lpa/src/uart0/lcr_h.rs index 6e02317..b6c85cc 100644 --- a/crates/bcm2837-lpa/src/uart0/lcr_h.rs +++ b/crates/bcm2837-lpa/src/uart0/lcr_h.rs @@ -1,67 +1,35 @@ #[doc = "Register `LCR_H` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LCR_H` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BRK` reader - BRK"] -pub type BRK_R = crate::BitReader; +pub type BRK_R = crate::BitReader; #[doc = "Field `BRK` writer - BRK"] -pub type BRK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type BRK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEN` reader - PEN"] -pub type PEN_R = crate::BitReader; +pub type PEN_R = crate::BitReader; #[doc = "Field `PEN` writer - PEN"] -pub type PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPS` reader - EPS"] -pub type EPS_R = crate::BitReader; +pub type EPS_R = crate::BitReader; #[doc = "Field `EPS` writer - EPS"] -pub type EPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type EPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STP2` reader - STP2"] -pub type STP2_R = crate::BitReader; +pub type STP2_R = crate::BitReader; #[doc = "Field `STP2` writer - STP2"] -pub type STP2_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type STP2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FEN` reader - FEN"] -pub type FEN_R = crate::BitReader; +pub type FEN_R = crate::BitReader; #[doc = "Field `FEN` writer - FEN"] -pub type FEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type FEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WLEN` reader - WLEN"] -pub type WLEN_R = crate::FieldReader; +pub type WLEN_R = crate::FieldReader; #[doc = "Field `WLEN` writer - WLEN"] -pub type WLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LCR_H_SPEC, u8, u8, 2, O>; +pub type WLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `SPS` reader - SPS"] -pub type SPS_R = crate::BitReader; +pub type SPS_R = crate::BitReader; #[doc = "Field `SPS` writer - SPS"] -pub type SPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_H_SPEC, bool, O>; +pub type SPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - BRK"] #[inline(always)] @@ -99,68 +67,87 @@ impl R { SPS_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCR_H") + .field("brk", &format_args!("{}", self.brk().bit())) + .field("pen", &format_args!("{}", self.pen().bit())) + .field("eps", &format_args!("{}", self.eps().bit())) + .field("stp2", &format_args!("{}", self.stp2().bit())) + .field("fen", &format_args!("{}", self.fen().bit())) + .field("wlen", &format_args!("{}", self.wlen().bits())) + .field("sps", &format_args!("{}", self.sps().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - BRK"] #[inline(always)] #[must_use] - pub fn brk(&mut self) -> BRK_W<0> { + pub fn brk(&mut self) -> BRK_W { BRK_W::new(self) } #[doc = "Bit 1 - PEN"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W<1> { + pub fn pen(&mut self) -> PEN_W { PEN_W::new(self) } #[doc = "Bit 2 - EPS"] #[inline(always)] #[must_use] - pub fn eps(&mut self) -> EPS_W<2> { + pub fn eps(&mut self) -> EPS_W { EPS_W::new(self) } #[doc = "Bit 3 - STP2"] #[inline(always)] #[must_use] - pub fn stp2(&mut self) -> STP2_W<3> { + pub fn stp2(&mut self) -> STP2_W { STP2_W::new(self) } #[doc = "Bit 4 - FEN"] #[inline(always)] #[must_use] - pub fn fen(&mut self) -> FEN_W<4> { + pub fn fen(&mut self) -> FEN_W { FEN_W::new(self) } #[doc = "Bits 5:6 - WLEN"] #[inline(always)] #[must_use] - pub fn wlen(&mut self) -> WLEN_W<5> { + pub fn wlen(&mut self) -> WLEN_W { WLEN_W::new(self) } #[doc = "Bit 7 - SPS"] #[inline(always)] #[must_use] - pub fn sps(&mut self) -> SPS_W<7> { + pub fn sps(&mut self) -> SPS_W { SPS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Line Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr_h](index.html) module"] +#[doc = "Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr_h::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr_h::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LCR_H_SPEC; impl crate::RegisterSpec for LCR_H_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lcr_h::R](R) reader structure"] -impl crate::Readable for LCR_H_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [lcr_h::W](W) writer structure"] +#[doc = "`read()` method returns [`lcr_h::R`](R) reader structure"] +impl crate::Readable for LCR_H_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcr_h::W`](W) writer structure"] impl crate::Writable for LCR_H_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart0/mis.rs b/crates/bcm2837-lpa/src/uart0/mis.rs index ce802e5..8ecfc00 100644 --- a/crates/bcm2837-lpa/src/uart0/mis.rs +++ b/crates/bcm2837-lpa/src/uart0/mis.rs @@ -1,40 +1,27 @@ #[doc = "Register `MIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RIMMIS` reader - RIMMIS"] -pub type RIMMIS_R = crate::BitReader; +pub type RIMMIS_R = crate::BitReader; #[doc = "Field `CTSMMIS` reader - CTSMMIS"] -pub type CTSMMIS_R = crate::BitReader; +pub type CTSMMIS_R = crate::BitReader; #[doc = "Field `DCDMMIS` reader - DCDMMIS"] -pub type DCDMMIS_R = crate::BitReader; +pub type DCDMMIS_R = crate::BitReader; #[doc = "Field `DSRMMIS` reader - DSRMMIS"] -pub type DSRMMIS_R = crate::BitReader; +pub type DSRMMIS_R = crate::BitReader; #[doc = "Field `RXMIS` reader - RXMIS"] -pub type RXMIS_R = crate::BitReader; +pub type RXMIS_R = crate::BitReader; #[doc = "Field `TXMIS` reader - TXMIS"] -pub type TXMIS_R = crate::BitReader; +pub type TXMIS_R = crate::BitReader; #[doc = "Field `RTMIS` reader - RTMIS"] -pub type RTMIS_R = crate::BitReader; +pub type RTMIS_R = crate::BitReader; #[doc = "Field `FEMIS` reader - FEMIS"] -pub type FEMIS_R = crate::BitReader; +pub type FEMIS_R = crate::BitReader; #[doc = "Field `PEMIS` reader - PEMIS"] -pub type PEMIS_R = crate::BitReader; +pub type PEMIS_R = crate::BitReader; #[doc = "Field `BEMIS` reader - BEMIS"] -pub type BEMIS_R = crate::BitReader; +pub type BEMIS_R = crate::BitReader; #[doc = "Field `OEMIS` reader - OEMIS"] -pub type OEMIS_R = crate::BitReader; +pub type OEMIS_R = crate::BitReader; impl R { #[doc = "Bit 0 - RIMMIS"] #[inline(always)] @@ -92,15 +79,35 @@ impl R { OEMIS_R::new(((self.bits >> 10) & 1) != 0) } } -#[doc = "Masked Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mis](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MIS") + .field("rimmis", &format_args!("{}", self.rimmis().bit())) + .field("ctsmmis", &format_args!("{}", self.ctsmmis().bit())) + .field("dcdmmis", &format_args!("{}", self.dcdmmis().bit())) + .field("dsrmmis", &format_args!("{}", self.dsrmmis().bit())) + .field("rxmis", &format_args!("{}", self.rxmis().bit())) + .field("txmis", &format_args!("{}", self.txmis().bit())) + .field("rtmis", &format_args!("{}", self.rtmis().bit())) + .field("femis", &format_args!("{}", self.femis().bit())) + .field("pemis", &format_args!("{}", self.pemis().bit())) + .field("bemis", &format_args!("{}", self.bemis().bit())) + .field("oemis", &format_args!("{}", self.oemis().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Masked Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MIS_SPEC; impl crate::RegisterSpec for MIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mis::R](R) reader structure"] -impl crate::Readable for MIS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`mis::R`](R) reader structure"] +impl crate::Readable for MIS_SPEC {} #[doc = "`reset()` method sets MIS to value 0"] impl crate::Resettable for MIS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/uart0/ris.rs b/crates/bcm2837-lpa/src/uart0/ris.rs index 0ab6b9d..9da59ba 100644 --- a/crates/bcm2837-lpa/src/uart0/ris.rs +++ b/crates/bcm2837-lpa/src/uart0/ris.rs @@ -1,40 +1,27 @@ #[doc = "Register `RIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RIRMIS` reader - RIRMIS"] -pub type RIRMIS_R = crate::BitReader; +pub type RIRMIS_R = crate::BitReader; #[doc = "Field `CTSRMIS` reader - CTSRMIS"] -pub type CTSRMIS_R = crate::BitReader; +pub type CTSRMIS_R = crate::BitReader; #[doc = "Field `DCDRMIS` reader - DCDRMIS"] -pub type DCDRMIS_R = crate::BitReader; +pub type DCDRMIS_R = crate::BitReader; #[doc = "Field `DSRRMIS` reader - DSRRMIS"] -pub type DSRRMIS_R = crate::BitReader; +pub type DSRRMIS_R = crate::BitReader; #[doc = "Field `RXRIS` reader - RXRIS"] -pub type RXRIS_R = crate::BitReader; +pub type RXRIS_R = crate::BitReader; #[doc = "Field `TXRIS` reader - TXRIS"] -pub type TXRIS_R = crate::BitReader; +pub type TXRIS_R = crate::BitReader; #[doc = "Field `RTRIS` reader - RTRIS"] -pub type RTRIS_R = crate::BitReader; +pub type RTRIS_R = crate::BitReader; #[doc = "Field `FERIS` reader - FERIS"] -pub type FERIS_R = crate::BitReader; +pub type FERIS_R = crate::BitReader; #[doc = "Field `PERIS` reader - PERIS"] -pub type PERIS_R = crate::BitReader; +pub type PERIS_R = crate::BitReader; #[doc = "Field `BERIS` reader - BERIS"] -pub type BERIS_R = crate::BitReader; +pub type BERIS_R = crate::BitReader; #[doc = "Field `OERIS` reader - OERIS"] -pub type OERIS_R = crate::BitReader; +pub type OERIS_R = crate::BitReader; impl R { #[doc = "Bit 0 - RIRMIS"] #[inline(always)] @@ -92,15 +79,35 @@ impl R { OERIS_R::new(((self.bits >> 10) & 1) != 0) } } -#[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ris](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RIS") + .field("rirmis", &format_args!("{}", self.rirmis().bit())) + .field("ctsrmis", &format_args!("{}", self.ctsrmis().bit())) + .field("dcdrmis", &format_args!("{}", self.dcdrmis().bit())) + .field("dsrrmis", &format_args!("{}", self.dsrrmis().bit())) + .field("rxris", &format_args!("{}", self.rxris().bit())) + .field("txris", &format_args!("{}", self.txris().bit())) + .field("rtris", &format_args!("{}", self.rtris().bit())) + .field("feris", &format_args!("{}", self.feris().bit())) + .field("peris", &format_args!("{}", self.peris().bit())) + .field("beris", &format_args!("{}", self.beris().bit())) + .field("oeris", &format_args!("{}", self.oeris().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Raw Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RIS_SPEC; impl crate::RegisterSpec for RIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ris::R](R) reader structure"] -impl crate::Readable for RIS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ris::R`](R) reader structure"] +impl crate::Readable for RIS_SPEC {} #[doc = "`reset()` method sets RIS to value 0"] impl crate::Resettable for RIS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/uart0/rsr.rs b/crates/bcm2837-lpa/src/uart0/rsr.rs index 90a9e0d..524d503 100644 --- a/crates/bcm2837-lpa/src/uart0/rsr.rs +++ b/crates/bcm2837-lpa/src/uart0/rsr.rs @@ -1,26 +1,13 @@ #[doc = "Register `RSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FE` reader - FE"] -pub type FE_R = crate::BitReader; +pub type FE_R = crate::BitReader; #[doc = "Field `PE` reader - PE"] -pub type PE_R = crate::BitReader; +pub type PE_R = crate::BitReader; #[doc = "Field `BE` reader - BE"] -pub type BE_R = crate::BitReader; +pub type BE_R = crate::BitReader; #[doc = "Field `OE` reader - OE"] -pub type OE_R = crate::BitReader; +pub type OE_R = crate::BitReader; impl R { #[doc = "Bit 0 - FE"] #[inline(always)] @@ -43,15 +30,28 @@ impl R { OE_R::new(((self.bits >> 3) & 1) != 0) } } -#[doc = "Receive Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rsr](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSR") + .field("fe", &format_args!("{}", self.fe().bit())) + .field("pe", &format_args!("{}", self.pe().bit())) + .field("be", &format_args!("{}", self.be().bit())) + .field("oe", &format_args!("{}", self.oe().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Receive Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSR_SPEC; impl crate::RegisterSpec for RSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rsr::R](R) reader structure"] -impl crate::Readable for RSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rsr::R`](R) reader structure"] +impl crate::Readable for RSR_SPEC {} #[doc = "`reset()` method sets RSR to value 0"] impl crate::Resettable for RSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/uart1.rs b/crates/bcm2837-lpa/src/uart1.rs index a87a1e5..7cc03cc 100644 --- a/crates/bcm2837-lpa/src/uart1.rs +++ b/crates/bcm2837-lpa/src/uart1.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { _reserved_0_io: [u8; 0x04], _reserved_1_ier: [u8; 0x04], @@ -45,55 +46,68 @@ impl RegisterBlock { unsafe { &*(self as *const Self).cast::().add(4usize).cast() } } } -#[doc = "IO (rw) register accessor: an alias for `Reg`"] +#[doc = "IO (rw) register accessor: I/O Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@io`] +module"] pub type IO = crate::Reg; #[doc = "I/O Data"] pub mod io; -#[doc = "BAUDL (rw) register accessor: an alias for `Reg`"] +#[doc = "BAUDL (rw) register accessor: Lower bits of baudrate when DLAB is set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baudl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baudl`] +module"] pub type BAUDL = crate::Reg; #[doc = "Lower bits of baudrate when DLAB is set"] pub mod baudl; -#[doc = "IER (rw) register accessor: an alias for `Reg`"] +#[doc = "IER (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable"] pub mod ier; -#[doc = "BAUDH (rw) register accessor: an alias for `Reg`"] +#[doc = "BAUDH (rw) register accessor: High bits of baudrate when DLAB is set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baudh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baudh`] +module"] pub type BAUDH = crate::Reg; #[doc = "High bits of baudrate when DLAB is set"] pub mod baudh; -#[doc = "IIR (rw) register accessor: an alias for `Reg`"] +#[doc = "IIR (rw) register accessor: Interrupt Identify\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] +module"] pub type IIR = crate::Reg; #[doc = "Interrupt Identify"] pub mod iir; -#[doc = "LCR (rw) register accessor: an alias for `Reg`"] +#[doc = "LCR (rw) register accessor: Line control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] +module"] pub type LCR = crate::Reg; #[doc = "Line control"] pub mod lcr; -#[doc = "MCR (rw) register accessor: an alias for `Reg`"] +#[doc = "MCR (rw) register accessor: Modem Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] +module"] pub type MCR = crate::Reg; #[doc = "Modem Control"] pub mod mcr; -#[doc = "LSR (rw) register accessor: an alias for `Reg`"] +#[doc = "LSR (rw) register accessor: Line Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] +module"] pub type LSR = crate::Reg; #[doc = "Line Status"] pub mod lsr; -#[doc = "MSR (rw) register accessor: an alias for `Reg`"] +#[doc = "MSR (rw) register accessor: Modem Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] +module"] pub type MSR = crate::Reg; #[doc = "Modem Status"] pub mod msr; -#[doc = "SCRATCH (rw) register accessor: an alias for `Reg`"] +#[doc = "SCRATCH (rw) register accessor: Scratch\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scratch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scratch`] +module"] pub type SCRATCH = crate::Reg; #[doc = "Scratch"] pub mod scratch; -#[doc = "CNTL (rw) register accessor: an alias for `Reg`"] +#[doc = "CNTL (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntl`] +module"] pub type CNTL = crate::Reg; #[doc = "Control"] pub mod cntl; -#[doc = "STAT (rw) register accessor: an alias for `Reg`"] +#[doc = "STAT (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] +module"] pub type STAT = crate::Reg; #[doc = "Status"] pub mod stat; -#[doc = "BAUD (rw) register accessor: an alias for `Reg`"] +#[doc = "BAUD (rw) register accessor: Baudrate\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baud::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baud::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baud`] +module"] pub type BAUD = crate::Reg; #[doc = "Baudrate"] pub mod baud; diff --git a/crates/bcm2837-lpa/src/uart1/baud.rs b/crates/bcm2837-lpa/src/uart1/baud.rs index 088c774..4cc37c7 100644 --- a/crates/bcm2837-lpa/src/uart1/baud.rs +++ b/crates/bcm2837-lpa/src/uart1/baud.rs @@ -1,59 +1,38 @@ #[doc = "Register `BAUD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BAUD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Baudrate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +#[doc = "Baudrate\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baud::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baud::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BAUD_SPEC; impl crate::RegisterSpec for BAUD_SPEC { type Ux = u16; } -#[doc = "`read()` method returns [baud::R](R) reader structure"] -impl crate::Readable for BAUD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +#[doc = "`read()` method returns [`baud::R`](R) reader structure"] +impl crate::Readable for BAUD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`baud::W`](W) writer structure"] impl crate::Writable for BAUD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart1/baudh.rs b/crates/bcm2837-lpa/src/uart1/baudh.rs index 8c30695..aa2fa88 100644 --- a/crates/bcm2837-lpa/src/uart1/baudh.rs +++ b/crates/bcm2837-lpa/src/uart1/baudh.rs @@ -1,59 +1,38 @@ #[doc = "Register `BAUDH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BAUDH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "High bits of baudrate when DLAB is set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudh](index.html) module"] +#[doc = "High bits of baudrate when DLAB is set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baudh::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BAUDH_SPEC; impl crate::RegisterSpec for BAUDH_SPEC { type Ux = u8; } -#[doc = "`read()` method returns [baudh::R](R) reader structure"] -impl crate::Readable for BAUDH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [baudh::W](W) writer structure"] +#[doc = "`read()` method returns [`baudh::R`](R) reader structure"] +impl crate::Readable for BAUDH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`baudh::W`](W) writer structure"] impl crate::Writable for BAUDH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart1/baudl.rs b/crates/bcm2837-lpa/src/uart1/baudl.rs index ca7c9f0..a9c9850 100644 --- a/crates/bcm2837-lpa/src/uart1/baudl.rs +++ b/crates/bcm2837-lpa/src/uart1/baudl.rs @@ -1,59 +1,38 @@ #[doc = "Register `BAUDL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BAUDL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Lower bits of baudrate when DLAB is set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baudl](index.html) module"] +#[doc = "Lower bits of baudrate when DLAB is set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baudl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baudl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BAUDL_SPEC; impl crate::RegisterSpec for BAUDL_SPEC { type Ux = u8; } -#[doc = "`read()` method returns [baudl::R](R) reader structure"] -impl crate::Readable for BAUDL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [baudl::W](W) writer structure"] +#[doc = "`read()` method returns [`baudl::R`](R) reader structure"] +impl crate::Readable for BAUDL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`baudl::W`](W) writer structure"] impl crate::Writable for BAUDL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart1/cntl.rs b/crates/bcm2837-lpa/src/uart1/cntl.rs index 4125093..ca942f3 100644 --- a/crates/bcm2837-lpa/src/uart1/cntl.rs +++ b/crates/bcm2837-lpa/src/uart1/cntl.rs @@ -1,57 +1,25 @@ #[doc = "Register `CNTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CNTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RX_ENABLE` reader - Enable receive"] -pub type RX_ENABLE_R = crate::BitReader; +pub type RX_ENABLE_R = crate::BitReader; #[doc = "Field `RX_ENABLE` writer - Enable receive"] -pub type RX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +pub type RX_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_ENABLE` reader - Enable transmit"] -pub type TX_ENABLE_R = crate::BitReader; +pub type TX_ENABLE_R = crate::BitReader; #[doc = "Field `TX_ENABLE` writer - Enable transmit"] -pub type TX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +pub type TX_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTS_ENABLE` reader - Enable auto receive flow control with RTS"] -pub type RTS_ENABLE_R = crate::BitReader; +pub type RTS_ENABLE_R = crate::BitReader; #[doc = "Field `RTS_ENABLE` writer - Enable auto receive flow control with RTS"] -pub type RTS_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +pub type RTS_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTS_ENABLE` reader - Enable auto transmit flow control with CTS"] -pub type CTS_ENABLE_R = crate::BitReader; +pub type CTS_ENABLE_R = crate::BitReader; #[doc = "Field `CTS_ENABLE` writer - Enable auto transmit flow control with CTS"] -pub type CTS_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, bool, O>; +pub type CTS_ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTS_FIFO_LEVEL` reader - FIFO level to de-assert RTS"] -pub type RTS_FIFO_LEVEL_R = crate::FieldReader; +pub type RTS_FIFO_LEVEL_R = crate::FieldReader; #[doc = "FIFO level to de-assert RTS\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -71,10 +39,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FIFO_LEVEL_A { + type Ux = u8; +} impl RTS_FIFO_LEVEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FIFO_LEVEL_A { + pub const fn variant(&self) -> FIFO_LEVEL_A { match self.bits { 0 => FIFO_LEVEL_A::_3EMPTY, 1 => FIFO_LEVEL_A::_2EMPTY, @@ -83,49 +54,53 @@ impl RTS_FIFO_LEVEL_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_3EMPTY`"] + #[doc = "3 empty spaces"] #[inline(always)] pub fn is_3empty(&self) -> bool { *self == FIFO_LEVEL_A::_3EMPTY } - #[doc = "Checks if the value of the field is `_2EMPTY`"] + #[doc = "2 empty spaces"] #[inline(always)] pub fn is_2empty(&self) -> bool { *self == FIFO_LEVEL_A::_2EMPTY } - #[doc = "Checks if the value of the field is `_1EMPTY`"] + #[doc = "1 empty spaces"] #[inline(always)] pub fn is_1empty(&self) -> bool { *self == FIFO_LEVEL_A::_1EMPTY } - #[doc = "Checks if the value of the field is `_4EMPTY`"] + #[doc = "4 empty spaces"] #[inline(always)] pub fn is_4empty(&self) -> bool { *self == FIFO_LEVEL_A::_4EMPTY } } #[doc = "Field `RTS_FIFO_LEVEL` writer - FIFO level to de-assert RTS"] -pub type RTS_FIFO_LEVEL_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, CNTL_SPEC, u8, FIFO_LEVEL_A, 2, O>; -impl<'a, const O: u8> RTS_FIFO_LEVEL_W<'a, O> { +pub type RTS_FIFO_LEVEL_W<'a, REG, const O: u8> = + crate::FieldWriterSafe<'a, REG, 2, O, FIFO_LEVEL_A>; +impl<'a, REG, const O: u8> RTS_FIFO_LEVEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "3 empty spaces"] #[inline(always)] - pub fn _3empty(self) -> &'a mut W { + pub fn _3empty(self) -> &'a mut crate::W { self.variant(FIFO_LEVEL_A::_3EMPTY) } #[doc = "2 empty spaces"] #[inline(always)] - pub fn _2empty(self) -> &'a mut W { + pub fn _2empty(self) -> &'a mut crate::W { self.variant(FIFO_LEVEL_A::_2EMPTY) } #[doc = "1 empty spaces"] #[inline(always)] - pub fn _1empty(self) -> &'a mut W { + pub fn _1empty(self) -> &'a mut crate::W { self.variant(FIFO_LEVEL_A::_1EMPTY) } #[doc = "4 empty spaces"] #[inline(always)] - pub fn _4empty(self) -> &'a mut W { + pub fn _4empty(self) -> &'a mut crate::W { self.variant(FIFO_LEVEL_A::_4EMPTY) } } @@ -152,34 +127,37 @@ impl From for bool { impl CTS_ASSERT_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> ASSERT_LEVEL_A { + pub const fn variant(&self) -> ASSERT_LEVEL_A { match self.bits { false => ASSERT_LEVEL_A::HIGH, true => ASSERT_LEVEL_A::LOW, } } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "Assert high"] #[inline(always)] pub fn is_high(&self) -> bool { *self == ASSERT_LEVEL_A::HIGH } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "Assert low"] #[inline(always)] pub fn is_low(&self) -> bool { *self == ASSERT_LEVEL_A::LOW } } #[doc = "Field `CTS_ASSERT` writer - CTS assert level"] -pub type CTS_ASSERT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CNTL_SPEC, ASSERT_LEVEL_A, O>; -impl<'a, const O: u8> CTS_ASSERT_W<'a, O> { +pub type CTS_ASSERT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ASSERT_LEVEL_A>; +impl<'a, REG, const O: u8> CTS_ASSERT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Assert high"] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(ASSERT_LEVEL_A::HIGH) } #[doc = "Assert low"] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(ASSERT_LEVEL_A::LOW) } } @@ -220,68 +198,90 @@ impl R { CTS_ASSERT_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CNTL") + .field("cts_assert", &format_args!("{}", self.cts_assert().bit())) + .field("rts_assert", &format_args!("{}", self.rts_assert().bit())) + .field( + "rts_fifo_level", + &format_args!("{}", self.rts_fifo_level().bits()), + ) + .field("cts_enable", &format_args!("{}", self.cts_enable().bit())) + .field("rts_enable", &format_args!("{}", self.rts_enable().bit())) + .field("tx_enable", &format_args!("{}", self.tx_enable().bit())) + .field("rx_enable", &format_args!("{}", self.rx_enable().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable receive"] #[inline(always)] #[must_use] - pub fn rx_enable(&mut self) -> RX_ENABLE_W<0> { + pub fn rx_enable(&mut self) -> RX_ENABLE_W { RX_ENABLE_W::new(self) } #[doc = "Bit 1 - Enable transmit"] #[inline(always)] #[must_use] - pub fn tx_enable(&mut self) -> TX_ENABLE_W<1> { + pub fn tx_enable(&mut self) -> TX_ENABLE_W { TX_ENABLE_W::new(self) } #[doc = "Bit 2 - Enable auto receive flow control with RTS"] #[inline(always)] #[must_use] - pub fn rts_enable(&mut self) -> RTS_ENABLE_W<2> { + pub fn rts_enable(&mut self) -> RTS_ENABLE_W { RTS_ENABLE_W::new(self) } #[doc = "Bit 3 - Enable auto transmit flow control with CTS"] #[inline(always)] #[must_use] - pub fn cts_enable(&mut self) -> CTS_ENABLE_W<3> { + pub fn cts_enable(&mut self) -> CTS_ENABLE_W { CTS_ENABLE_W::new(self) } #[doc = "Bits 4:5 - FIFO level to de-assert RTS"] #[inline(always)] #[must_use] - pub fn rts_fifo_level(&mut self) -> RTS_FIFO_LEVEL_W<4> { + pub fn rts_fifo_level(&mut self) -> RTS_FIFO_LEVEL_W { RTS_FIFO_LEVEL_W::new(self) } #[doc = "Bit 6 - RTS assert level"] #[inline(always)] #[must_use] - pub fn rts_assert(&mut self) -> RTS_ASSERT_W<6> { + pub fn rts_assert(&mut self) -> RTS_ASSERT_W { RTS_ASSERT_W::new(self) } #[doc = "Bit 7 - CTS assert level"] #[inline(always)] #[must_use] - pub fn cts_assert(&mut self) -> CTS_ASSERT_W<7> { + pub fn cts_assert(&mut self) -> CTS_ASSERT_W { CTS_ASSERT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CNTL_SPEC; impl crate::RegisterSpec for CNTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cntl::R](R) reader structure"] -impl crate::Readable for CNTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cntl::W](W) writer structure"] +#[doc = "`read()` method returns [`cntl::R`](R) reader structure"] +impl crate::Readable for CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cntl::W`](W) writer structure"] impl crate::Writable for CNTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart1/ier.rs b/crates/bcm2837-lpa/src/uart1/ier.rs index 450afd5..f3188e7 100644 --- a/crates/bcm2837-lpa/src/uart1/ier.rs +++ b/crates/bcm2837-lpa/src/uart1/ier.rs @@ -1,47 +1,15 @@ #[doc = "Register `IER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA_READY` reader - Receive FIFO has at least 1 byte"] -pub type DATA_READY_R = crate::BitReader; +pub type DATA_READY_R = crate::BitReader; #[doc = "Field `DATA_READY` writer - Receive FIFO has at least 1 byte"] -pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>; +pub type DATA_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_READY` reader - Transmit FIFO is empty"] -pub type TX_READY_R = crate::BitReader; +pub type TX_READY_R = crate::BitReader; #[doc = "Field `TX_READY` writer - Transmit FIFO is empty"] -pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>; +pub type TX_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Receive FIFO has at least 1 byte"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { TX_READY_R::new(((self.bits >> 1) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IER") + .field("tx_ready", &format_args!("{}", self.tx_ready().bit())) + .field("data_ready", &format_args!("{}", self.data_ready().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Receive FIFO has at least 1 byte"] #[inline(always)] #[must_use] - pub fn data_ready(&mut self) -> DATA_READY_W<0> { + pub fn data_ready(&mut self) -> DATA_READY_W { DATA_READY_W::new(self) } #[doc = "Bit 1 - Transmit FIFO is empty"] #[inline(always)] #[must_use] - pub fn tx_ready(&mut self) -> TX_READY_W<1> { + pub fn tx_ready(&mut self) -> TX_READY_W { TX_READY_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ier::R](R) reader structure"] -impl crate::Readable for IER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`read()` method returns [`ier::R`](R) reader structure"] +impl crate::Readable for IER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart1/iir.rs b/crates/bcm2837-lpa/src/uart1/iir.rs index 6f66eac..b7a876b 100644 --- a/crates/bcm2837-lpa/src/uart1/iir.rs +++ b/crates/bcm2837-lpa/src/uart1/iir.rs @@ -1,51 +1,19 @@ #[doc = "Register `IIR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IIR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `nPENDING` reader - No pending interrupt"] -pub type N_PENDING_R = crate::BitReader; +pub type N_PENDING_R = crate::BitReader; #[doc = "Field `nPENDING` writer - No pending interrupt"] -pub type N_PENDING_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +pub type N_PENDING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATA_READY` reader - Receive FIFO has at least 1 byte"] -pub type DATA_READY_R = crate::BitReader; +pub type DATA_READY_R = crate::BitReader; #[doc = "Field `DATA_READY` writer - Receive FIFO has at least 1 byte"] -pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +pub type DATA_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_READY` reader - Transmit FIFO is empty"] -pub type TX_READY_R = crate::BitReader; +pub type TX_READY_R = crate::BitReader; #[doc = "Field `TX_READY` writer - Transmit FIFO is empty"] -pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IIR_SPEC, bool, O>; +pub type TX_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - No pending interrupt"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { TX_READY_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IIR") + .field("tx_ready", &format_args!("{}", self.tx_ready().bit())) + .field("data_ready", &format_args!("{}", self.data_ready().bit())) + .field("n_pending", &format_args!("{}", self.n_pending().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - No pending interrupt"] #[inline(always)] #[must_use] - pub fn n_pending(&mut self) -> N_PENDING_W<0> { + pub fn n_pending(&mut self) -> N_PENDING_W { N_PENDING_W::new(self) } #[doc = "Bit 1 - Receive FIFO has at least 1 byte"] #[inline(always)] #[must_use] - pub fn data_ready(&mut self) -> DATA_READY_W<1> { + pub fn data_ready(&mut self) -> DATA_READY_W { DATA_READY_W::new(self) } #[doc = "Bit 2 - Transmit FIFO is empty"] #[inline(always)] #[must_use] - pub fn tx_ready(&mut self) -> TX_READY_W<2> { + pub fn tx_ready(&mut self) -> TX_READY_W { TX_READY_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Identify\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iir](index.html) module"] +#[doc = "Interrupt Identify\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IIR_SPEC; impl crate::RegisterSpec for IIR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [iir::R](R) reader structure"] -impl crate::Readable for IIR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [iir::W](W) writer structure"] +#[doc = "`read()` method returns [`iir::R`](R) reader structure"] +impl crate::Readable for IIR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`iir::W`](W) writer structure"] impl crate::Writable for IIR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart1/io.rs b/crates/bcm2837-lpa/src/uart1/io.rs index 84cd075..1873e08 100644 --- a/crates/bcm2837-lpa/src/uart1/io.rs +++ b/crates/bcm2837-lpa/src/uart1/io.rs @@ -1,43 +1,11 @@ #[doc = "Register `IO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IO` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - FIFO access"] -pub type DATA_R = crate::FieldReader; +pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - FIFO access"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO_SPEC, u8, u8, 8, O>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - FIFO access"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DATA_R::new((self.bits & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IO") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:7 - FIFO access"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "I/O Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io](index.html) module"] +#[doc = "I/O Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`io::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`io::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IO_SPEC; impl crate::RegisterSpec for IO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [io::R](R) reader structure"] -impl crate::Readable for IO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [io::W](W) writer structure"] +#[doc = "`read()` method returns [`io::R`](R) reader structure"] +impl crate::Readable for IO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`io::W`](W) writer structure"] impl crate::Writable for IO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart1/lcr.rs b/crates/bcm2837-lpa/src/uart1/lcr.rs index 16b3c2b..38e7d1e 100644 --- a/crates/bcm2837-lpa/src/uart1/lcr.rs +++ b/crates/bcm2837-lpa/src/uart1/lcr.rs @@ -1,41 +1,9 @@ #[doc = "Register `LCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA_SIZE` reader - UART word size"] -pub type DATA_SIZE_R = crate::FieldReader; +pub type DATA_SIZE_R = crate::FieldReader; #[doc = "UART word size\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -51,49 +19,56 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for MODE_A { + type Ux = u8; +} impl DATA_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(MODE_A::_7BIT), 3 => Some(MODE_A::_8BIT), _ => None, } } - #[doc = "Checks if the value of the field is `_7BIT`"] + #[doc = "7 bit"] #[inline(always)] pub fn is_7bit(&self) -> bool { *self == MODE_A::_7BIT } - #[doc = "Checks if the value of the field is `_8BIT`"] + #[doc = "8 bit"] #[inline(always)] pub fn is_8bit(&self) -> bool { *self == MODE_A::_8BIT } } #[doc = "Field `DATA_SIZE` writer - UART word size"] -pub type DATA_SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LCR_SPEC, u8, MODE_A, 2, O>; -impl<'a, const O: u8> DATA_SIZE_W<'a, O> { +pub type DATA_SIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, MODE_A>; +impl<'a, REG, const O: u8> DATA_SIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "7 bit"] #[inline(always)] - pub fn _7bit(self) -> &'a mut W { + pub fn _7bit(self) -> &'a mut crate::W { self.variant(MODE_A::_7BIT) } #[doc = "8 bit"] #[inline(always)] - pub fn _8bit(self) -> &'a mut W { + pub fn _8bit(self) -> &'a mut crate::W { self.variant(MODE_A::_8BIT) } } #[doc = "Field `BREAK` reader - Pull TX low continuously to send break"] -pub type BREAK_R = crate::BitReader; +pub type BREAK_R = crate::BitReader; #[doc = "Field `BREAK` writer - Pull TX low continuously to send break"] -pub type BREAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_SPEC, bool, O>; +pub type BREAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DLAB` reader - First two registers are baudrate"] -pub type DLAB_R = crate::BitReader; +pub type DLAB_R = crate::BitReader; #[doc = "Field `DLAB` writer - First two registers are baudrate"] -pub type DLAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCR_SPEC, bool, O>; +pub type DLAB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:1 - UART word size"] #[inline(always)] @@ -111,44 +86,59 @@ impl R { DLAB_R::new(((self.bits >> 7) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCR") + .field("dlab", &format_args!("{}", self.dlab().bit())) + .field("break_", &format_args!("{}", self.break_().bit())) + .field("data_size", &format_args!("{}", self.data_size().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - UART word size"] #[inline(always)] #[must_use] - pub fn data_size(&mut self) -> DATA_SIZE_W<0> { + pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W::new(self) } #[doc = "Bit 6 - Pull TX low continuously to send break"] #[inline(always)] #[must_use] - pub fn break_(&mut self) -> BREAK_W<6> { + pub fn break_(&mut self) -> BREAK_W { BREAK_W::new(self) } #[doc = "Bit 7 - First two registers are baudrate"] #[inline(always)] #[must_use] - pub fn dlab(&mut self) -> DLAB_W<7> { + pub fn dlab(&mut self) -> DLAB_W { DLAB_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Line control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcr](index.html) module"] +#[doc = "Line control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LCR_SPEC; impl crate::RegisterSpec for LCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lcr::R](R) reader structure"] -impl crate::Readable for LCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [lcr::W](W) writer structure"] +#[doc = "`read()` method returns [`lcr::R`](R) reader structure"] +impl crate::Readable for LCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcr::W`](W) writer structure"] impl crate::Writable for LCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart1/lsr.rs b/crates/bcm2837-lpa/src/uart1/lsr.rs index ba34ba7..83455e7 100644 --- a/crates/bcm2837-lpa/src/uart1/lsr.rs +++ b/crates/bcm2837-lpa/src/uart1/lsr.rs @@ -1,55 +1,23 @@ #[doc = "Register `LSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA_READY` reader - Receive FIFO has at least one byte"] -pub type DATA_READY_R = crate::BitReader; +pub type DATA_READY_R = crate::BitReader; #[doc = "Field `DATA_READY` writer - Receive FIFO has at least one byte"] -pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +pub type DATA_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_OVERRUN` reader - Receive FIFO overrun"] -pub type RX_OVERRUN_R = crate::BitReader; +pub type RX_OVERRUN_R = crate::BitReader; #[doc = "Field `RX_OVERRUN` writer - Receive FIFO overrun"] -pub type RX_OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +pub type RX_OVERRUN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_EMPTY` reader - Transmit FIFO has room for at least one byte"] -pub type TX_EMPTY_R = crate::BitReader; +pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `TX_EMPTY` writer - Transmit FIFO has room for at least one byte"] -pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_IDLE` reader - Transmit FIFO empty and all bits shifted out"] -pub type TX_IDLE_R = crate::BitReader; +pub type TX_IDLE_R = crate::BitReader; #[doc = "Field `TX_IDLE` writer - Transmit FIFO empty and all bits shifted out"] -pub type TX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSR_SPEC, bool, O>; +pub type TX_IDLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Receive FIFO has at least one byte"] #[inline(always)] @@ -72,50 +40,66 @@ impl R { TX_IDLE_R::new(((self.bits >> 6) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LSR") + .field("tx_idle", &format_args!("{}", self.tx_idle().bit())) + .field("tx_empty", &format_args!("{}", self.tx_empty().bit())) + .field("rx_overrun", &format_args!("{}", self.rx_overrun().bit())) + .field("data_ready", &format_args!("{}", self.data_ready().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Receive FIFO has at least one byte"] #[inline(always)] #[must_use] - pub fn data_ready(&mut self) -> DATA_READY_W<0> { + pub fn data_ready(&mut self) -> DATA_READY_W { DATA_READY_W::new(self) } #[doc = "Bit 1 - Receive FIFO overrun"] #[inline(always)] #[must_use] - pub fn rx_overrun(&mut self) -> RX_OVERRUN_W<1> { + pub fn rx_overrun(&mut self) -> RX_OVERRUN_W { RX_OVERRUN_W::new(self) } #[doc = "Bit 5 - Transmit FIFO has room for at least one byte"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W<5> { + pub fn tx_empty(&mut self) -> TX_EMPTY_W { TX_EMPTY_W::new(self) } #[doc = "Bit 6 - Transmit FIFO empty and all bits shifted out"] #[inline(always)] #[must_use] - pub fn tx_idle(&mut self) -> TX_IDLE_W<6> { + pub fn tx_idle(&mut self) -> TX_IDLE_W { TX_IDLE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Line Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lsr](index.html) module"] +#[doc = "Line Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LSR_SPEC; impl crate::RegisterSpec for LSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lsr::R](R) reader structure"] -impl crate::Readable for LSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [lsr::W](W) writer structure"] +#[doc = "`read()` method returns [`lsr::R`](R) reader structure"] +impl crate::Readable for LSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lsr::W`](W) writer structure"] impl crate::Writable for LSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart1/mcr.rs b/crates/bcm2837-lpa/src/uart1/mcr.rs index 89de0a8..26a7cb4 100644 --- a/crates/bcm2837-lpa/src/uart1/mcr.rs +++ b/crates/bcm2837-lpa/src/uart1/mcr.rs @@ -1,43 +1,11 @@ #[doc = "Register `MCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RTS` reader - RTS is low"] -pub type RTS_R = crate::BitReader; +pub type RTS_R = crate::BitReader; #[doc = "Field `RTS` writer - RTS is low"] -pub type RTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>; +pub type RTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - RTS is low"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { RTS_R::new(((self.bits >> 1) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCR") + .field("rts", &format_args!("{}", self.rts().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - RTS is low"] #[inline(always)] #[must_use] - pub fn rts(&mut self) -> RTS_W<1> { + pub fn rts(&mut self) -> RTS_W { RTS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Modem Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr](index.html) module"] +#[doc = "Modem Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCR_SPEC; impl crate::RegisterSpec for MCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mcr::R](R) reader structure"] -impl crate::Readable for MCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mcr::W](W) writer structure"] +#[doc = "`read()` method returns [`mcr::R`](R) reader structure"] +impl crate::Readable for MCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] impl crate::Writable for MCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart1/msr.rs b/crates/bcm2837-lpa/src/uart1/msr.rs index 3960539..c6e81af 100644 --- a/crates/bcm2837-lpa/src/uart1/msr.rs +++ b/crates/bcm2837-lpa/src/uart1/msr.rs @@ -1,43 +1,11 @@ #[doc = "Register `MSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CTS` reader - CTS is low"] -pub type CTS_R = crate::BitReader; +pub type CTS_R = crate::BitReader; #[doc = "Field `CTS` writer - CTS is low"] -pub type CTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MSR_SPEC, bool, O>; +pub type CTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 4 - CTS is low"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { CTS_R::new(((self.bits >> 4) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MSR") + .field("cts", &format_args!("{}", self.cts().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 4 - CTS is low"] #[inline(always)] #[must_use] - pub fn cts(&mut self) -> CTS_W<4> { + pub fn cts(&mut self) -> CTS_W { CTS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Modem Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msr](index.html) module"] +#[doc = "Modem Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MSR_SPEC; impl crate::RegisterSpec for MSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [msr::R](R) reader structure"] -impl crate::Readable for MSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [msr::W](W) writer structure"] +#[doc = "`read()` method returns [`msr::R`](R) reader structure"] +impl crate::Readable for MSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`msr::W`](W) writer structure"] impl crate::Writable for MSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart1/scratch.rs b/crates/bcm2837-lpa/src/uart1/scratch.rs index c85f068..bd73381 100644 --- a/crates/bcm2837-lpa/src/uart1/scratch.rs +++ b/crates/bcm2837-lpa/src/uart1/scratch.rs @@ -1,59 +1,38 @@ #[doc = "Register `SCRATCH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCRATCH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Scratch\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scratch](index.html) module"] +#[doc = "Scratch\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scratch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCRATCH_SPEC; impl crate::RegisterSpec for SCRATCH_SPEC { type Ux = u8; } -#[doc = "`read()` method returns [scratch::R](R) reader structure"] -impl crate::Readable for SCRATCH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scratch::W](W) writer structure"] +#[doc = "`read()` method returns [`scratch::R`](R) reader structure"] +impl crate::Readable for SCRATCH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch::W`](W) writer structure"] impl crate::Writable for SCRATCH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/uart1/stat.rs b/crates/bcm2837-lpa/src/uart1/stat.rs index 114015e..b876fef 100644 --- a/crates/bcm2837-lpa/src/uart1/stat.rs +++ b/crates/bcm2837-lpa/src/uart1/stat.rs @@ -1,87 +1,55 @@ #[doc = "Register `STAT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STAT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA_READY` reader - Receive FIFO has at least one symbol"] -pub type DATA_READY_R = crate::BitReader; +pub type DATA_READY_R = crate::BitReader; #[doc = "Field `DATA_READY` writer - Receive FIFO has at least one symbol"] -pub type DATA_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type DATA_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_READY` reader - Transmit FIFO has space for at least one symbol"] -pub type TX_READY_R = crate::BitReader; +pub type TX_READY_R = crate::BitReader; #[doc = "Field `TX_READY` writer - Transmit FIFO has space for at least one symbol"] -pub type TX_READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_READY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_IDLE` reader - Receiver is idle"] -pub type RX_IDLE_R = crate::BitReader; +pub type RX_IDLE_R = crate::BitReader; #[doc = "Field `RX_IDLE` writer - Receiver is idle"] -pub type RX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RX_IDLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_IDLE` reader - Transmitter is idle"] -pub type TX_IDLE_R = crate::BitReader; +pub type TX_IDLE_R = crate::BitReader; #[doc = "Field `TX_IDLE` writer - Transmitter is idle"] -pub type TX_IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_IDLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_OVERRUN` reader - Receive FIFO overrun"] -pub type RX_OVERRUN_R = crate::BitReader; +pub type RX_OVERRUN_R = crate::BitReader; #[doc = "Field `RX_OVERRUN` writer - Receive FIFO overrun"] -pub type RX_OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RX_OVERRUN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_FULL` reader - Transmit FIFO is full"] -pub type TX_FULL_R = crate::BitReader; +pub type TX_FULL_R = crate::BitReader; #[doc = "Field `TX_FULL` writer - Transmit FIFO is full"] -pub type TX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTS_STATUS` reader - RTS state"] -pub type RTS_STATUS_R = crate::BitReader; +pub type RTS_STATUS_R = crate::BitReader; #[doc = "Field `RTS_STATUS` writer - RTS state"] -pub type RTS_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type RTS_STATUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTS_STATUS` reader - CTS state"] -pub type CTS_STATUS_R = crate::BitReader; +pub type CTS_STATUS_R = crate::BitReader; #[doc = "Field `CTS_STATUS` writer - CTS state"] -pub type CTS_STATUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type CTS_STATUS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_EMPTY` reader - Transmit FIFO is completely empty"] -pub type TX_EMPTY_R = crate::BitReader; +pub type TX_EMPTY_R = crate::BitReader; #[doc = "Field `TX_EMPTY` writer - Transmit FIFO is completely empty"] -pub type TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_EMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TX_DONE` reader - Transmit FIFO is empty and transmitter is idle"] -pub type TX_DONE_R = crate::BitReader; +pub type TX_DONE_R = crate::BitReader; #[doc = "Field `TX_DONE` writer - Transmit FIFO is empty and transmitter is idle"] -pub type TX_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, STAT_SPEC, bool, O>; +pub type TX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_FIFO_LEVEL` reader - How many entries are filled in the RX FIFO"] -pub type RX_FIFO_LEVEL_R = crate::FieldReader; +pub type RX_FIFO_LEVEL_R = crate::FieldReader; #[doc = "Field `RX_FIFO_LEVEL` writer - How many entries are filled in the RX FIFO"] -pub type RX_FIFO_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +pub type RX_FIFO_LEVEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TX_FIFO_LEVEL` reader - How many entries are filled in the TX FIFO"] -pub type TX_FIFO_LEVEL_R = crate::FieldReader; +pub type TX_FIFO_LEVEL_R = crate::FieldReader; #[doc = "Field `TX_FIFO_LEVEL` writer - How many entries are filled in the TX FIFO"] -pub type TX_FIFO_LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, STAT_SPEC, u8, u8, 4, O>; +pub type TX_FIFO_LEVEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bit 0 - Receive FIFO has at least one symbol"] #[inline(always)] @@ -144,98 +112,128 @@ impl R { TX_FIFO_LEVEL_R::new(((self.bits >> 24) & 0x0f) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STAT") + .field( + "tx_fifo_level", + &format_args!("{}", self.tx_fifo_level().bits()), + ) + .field( + "rx_fifo_level", + &format_args!("{}", self.rx_fifo_level().bits()), + ) + .field("tx_done", &format_args!("{}", self.tx_done().bit())) + .field("tx_empty", &format_args!("{}", self.tx_empty().bit())) + .field("cts_status", &format_args!("{}", self.cts_status().bit())) + .field("rts_status", &format_args!("{}", self.rts_status().bit())) + .field("tx_full", &format_args!("{}", self.tx_full().bit())) + .field("rx_overrun", &format_args!("{}", self.rx_overrun().bit())) + .field("tx_idle", &format_args!("{}", self.tx_idle().bit())) + .field("rx_idle", &format_args!("{}", self.rx_idle().bit())) + .field("tx_ready", &format_args!("{}", self.tx_ready().bit())) + .field("data_ready", &format_args!("{}", self.data_ready().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Receive FIFO has at least one symbol"] #[inline(always)] #[must_use] - pub fn data_ready(&mut self) -> DATA_READY_W<0> { + pub fn data_ready(&mut self) -> DATA_READY_W { DATA_READY_W::new(self) } #[doc = "Bit 1 - Transmit FIFO has space for at least one symbol"] #[inline(always)] #[must_use] - pub fn tx_ready(&mut self) -> TX_READY_W<1> { + pub fn tx_ready(&mut self) -> TX_READY_W { TX_READY_W::new(self) } #[doc = "Bit 2 - Receiver is idle"] #[inline(always)] #[must_use] - pub fn rx_idle(&mut self) -> RX_IDLE_W<2> { + pub fn rx_idle(&mut self) -> RX_IDLE_W { RX_IDLE_W::new(self) } #[doc = "Bit 3 - Transmitter is idle"] #[inline(always)] #[must_use] - pub fn tx_idle(&mut self) -> TX_IDLE_W<3> { + pub fn tx_idle(&mut self) -> TX_IDLE_W { TX_IDLE_W::new(self) } #[doc = "Bit 4 - Receive FIFO overrun"] #[inline(always)] #[must_use] - pub fn rx_overrun(&mut self) -> RX_OVERRUN_W<4> { + pub fn rx_overrun(&mut self) -> RX_OVERRUN_W { RX_OVERRUN_W::new(self) } #[doc = "Bit 5 - Transmit FIFO is full"] #[inline(always)] #[must_use] - pub fn tx_full(&mut self) -> TX_FULL_W<5> { + pub fn tx_full(&mut self) -> TX_FULL_W { TX_FULL_W::new(self) } #[doc = "Bit 6 - RTS state"] #[inline(always)] #[must_use] - pub fn rts_status(&mut self) -> RTS_STATUS_W<6> { + pub fn rts_status(&mut self) -> RTS_STATUS_W { RTS_STATUS_W::new(self) } #[doc = "Bit 7 - CTS state"] #[inline(always)] #[must_use] - pub fn cts_status(&mut self) -> CTS_STATUS_W<7> { + pub fn cts_status(&mut self) -> CTS_STATUS_W { CTS_STATUS_W::new(self) } #[doc = "Bit 8 - Transmit FIFO is completely empty"] #[inline(always)] #[must_use] - pub fn tx_empty(&mut self) -> TX_EMPTY_W<8> { + pub fn tx_empty(&mut self) -> TX_EMPTY_W { TX_EMPTY_W::new(self) } #[doc = "Bit 9 - Transmit FIFO is empty and transmitter is idle"] #[inline(always)] #[must_use] - pub fn tx_done(&mut self) -> TX_DONE_W<9> { + pub fn tx_done(&mut self) -> TX_DONE_W { TX_DONE_W::new(self) } #[doc = "Bits 16:19 - How many entries are filled in the RX FIFO"] #[inline(always)] #[must_use] - pub fn rx_fifo_level(&mut self) -> RX_FIFO_LEVEL_W<16> { + pub fn rx_fifo_level(&mut self) -> RX_FIFO_LEVEL_W { RX_FIFO_LEVEL_W::new(self) } #[doc = "Bits 24:27 - How many entries are filled in the TX FIFO"] #[inline(always)] #[must_use] - pub fn tx_fifo_level(&mut self) -> TX_FIFO_LEVEL_W<24> { + pub fn tx_fifo_level(&mut self) -> TX_FIFO_LEVEL_W { TX_FIFO_LEVEL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"] +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STAT_SPEC; impl crate::RegisterSpec for STAT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [stat::R](R) reader structure"] -impl crate::Readable for STAT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"] +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] impl crate::Writable for STAT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device.rs b/crates/bcm2837-lpa/src/usb_otg_device.rs index 8050e54..d432f5d 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - OTG_HS device configuration register"] pub dcfg: DCFG, @@ -107,63 +108,78 @@ pub struct RegisterBlock { #[doc = "0x460..0x478 - OUT Endpoint %s"] pub out_endpoint11: OUT_ENDPOINT, } -#[doc = "DCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "DCFG (rw) register accessor: OTG_HS device configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcfg`] +module"] pub type DCFG = crate::Reg; #[doc = "OTG_HS device configuration register"] pub mod dcfg; -#[doc = "DCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "DCTL (rw) register accessor: OTG_HS device control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dctl`] +module"] pub type DCTL = crate::Reg; #[doc = "OTG_HS device control register"] pub mod dctl; -#[doc = "DSTS (r) register accessor: an alias for `Reg`"] +#[doc = "DSTS (r) register accessor: OTG_HS device status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsts::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsts`] +module"] pub type DSTS = crate::Reg; #[doc = "OTG_HS device status register"] pub mod dsts; -#[doc = "DIEPMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPMSK (rw) register accessor: OTG_HS device IN endpoint common interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepmsk`] +module"] pub type DIEPMSK = crate::Reg; #[doc = "OTG_HS device IN endpoint common interrupt mask register"] pub mod diepmsk; -#[doc = "DOEPMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPMSK (rw) register accessor: OTG_HS device OUT endpoint common interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepmsk`] +module"] pub type DOEPMSK = crate::Reg; #[doc = "OTG_HS device OUT endpoint common interrupt mask register"] pub mod doepmsk; -#[doc = "DAINT (r) register accessor: an alias for `Reg`"] +#[doc = "DAINT (r) register accessor: OTG_HS device all endpoints interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daint::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daint`] +module"] pub type DAINT = crate::Reg; #[doc = "OTG_HS device all endpoints interrupt register"] pub mod daint; -#[doc = "DAINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DAINTMSK (rw) register accessor: OTG_HS all endpoints interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`daintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daintmsk`] +module"] pub type DAINTMSK = crate::Reg; #[doc = "OTG_HS all endpoints interrupt mask register"] pub mod daintmsk; -#[doc = "DVBUSDIS (rw) register accessor: an alias for `Reg`"] +#[doc = "DVBUSDIS (rw) register accessor: OTG_HS device VBUS discharge time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dvbusdis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dvbusdis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dvbusdis`] +module"] pub type DVBUSDIS = crate::Reg; #[doc = "OTG_HS device VBUS discharge time register"] pub mod dvbusdis; -#[doc = "DVBUSPULSE (rw) register accessor: an alias for `Reg`"] +#[doc = "DVBUSPULSE (rw) register accessor: OTG_HS device VBUS pulsing time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dvbuspulse::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dvbuspulse::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dvbuspulse`] +module"] pub type DVBUSPULSE = crate::Reg; #[doc = "OTG_HS device VBUS pulsing time register"] pub mod dvbuspulse; -#[doc = "DTHRCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "DTHRCTL (rw) register accessor: OTG_HS Device threshold control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dthrctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dthrctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dthrctl`] +module"] pub type DTHRCTL = crate::Reg; #[doc = "OTG_HS Device threshold control register"] pub mod dthrctl; -#[doc = "DIEPEMPMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPEMPMSK (rw) register accessor: OTG_HS device IN endpoint FIFO empty interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepempmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepempmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepempmsk`] +module"] pub type DIEPEMPMSK = crate::Reg; #[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register"] pub mod diepempmsk; -#[doc = "DEACHINT (rw) register accessor: an alias for `Reg`"] +#[doc = "DEACHINT (rw) register accessor: OTG_HS device each endpoint interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deachint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deachint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@deachint`] +module"] pub type DEACHINT = crate::Reg; #[doc = "OTG_HS device each endpoint interrupt register"] pub mod deachint; -#[doc = "DEACHINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "DEACHINTMSK (rw) register accessor: OTG_HS device each endpoint interrupt register mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deachintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deachintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@deachintmsk`] +module"] pub type DEACHINTMSK = crate::Reg; #[doc = "OTG_HS device each endpoint interrupt register mask"] pub mod deachintmsk; -#[doc = "DIEPEACHMSK1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPEACHMSK1 (rw) register accessor: OTG_HS device each in endpoint-1 interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepeachmsk1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepeachmsk1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepeachmsk1`] +module"] pub type DIEPEACHMSK1 = crate::Reg; #[doc = "OTG_HS device each in endpoint-1 interrupt register"] pub mod diepeachmsk1; -#[doc = "DOEPEACHMSK1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPEACHMSK1 (rw) register accessor: OTG_HS device each OUT endpoint-1 interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepeachmsk1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepeachmsk1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepeachmsk1`] +module"] pub type DOEPEACHMSK1 = crate::Reg; #[doc = "OTG_HS device each OUT endpoint-1 interrupt register"] pub mod doepeachmsk1; diff --git a/crates/bcm2837-lpa/src/usb_otg_device/daint.rs b/crates/bcm2837-lpa/src/usb_otg_device/daint.rs index 14c25b3..3210b36 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/daint.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/daint.rs @@ -1,22 +1,9 @@ #[doc = "Register `DAINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `IEPINT` reader - IN endpoint interrupt bits"] -pub type IEPINT_R = crate::FieldReader; +pub type IEPINT_R = crate::FieldReader; #[doc = "Field `OEPINT` reader - OUT endpoint interrupt bits"] -pub type OEPINT_R = crate::FieldReader; +pub type OEPINT_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - IN endpoint interrupt bits"] #[inline(always)] @@ -29,15 +16,26 @@ impl R { OEPINT_R::new(((self.bits >> 16) & 0xffff) as u16) } } -#[doc = "OTG_HS device all endpoints interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daint](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAINT") + .field("iepint", &format_args!("{}", self.iepint().bits())) + .field("oepint", &format_args!("{}", self.oepint().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS device all endpoints interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daint::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DAINT_SPEC; impl crate::RegisterSpec for DAINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [daint::R](R) reader structure"] -impl crate::Readable for DAINT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`daint::R`](R) reader structure"] +impl crate::Readable for DAINT_SPEC {} #[doc = "`reset()` method sets DAINT to value 0"] impl crate::Resettable for DAINT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/usb_otg_device/daintmsk.rs b/crates/bcm2837-lpa/src/usb_otg_device/daintmsk.rs index bf7c858..44196aa 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/daintmsk.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/daintmsk.rs @@ -1,47 +1,15 @@ #[doc = "Register `DAINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DAINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IEPM` reader - IN EP interrupt mask bits"] -pub type IEPM_R = crate::FieldReader; +pub type IEPM_R = crate::FieldReader; #[doc = "Field `IEPM` writer - IN EP interrupt mask bits"] -pub type IEPM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DAINTMSK_SPEC, u16, u16, 16, O>; +pub type IEPM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `OEPM` reader - OUT EP interrupt mask bits"] -pub type OEPM_R = crate::FieldReader; +pub type OEPM_R = crate::FieldReader; #[doc = "Field `OEPM` writer - OUT EP interrupt mask bits"] -pub type OEPM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DAINTMSK_SPEC, u16, u16, 16, O>; +pub type OEPM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN EP interrupt mask bits"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { OEPM_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAINTMSK") + .field("iepm", &format_args!("{}", self.iepm().bits())) + .field("oepm", &format_args!("{}", self.oepm().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN EP interrupt mask bits"] #[inline(always)] #[must_use] - pub fn iepm(&mut self) -> IEPM_W<0> { + pub fn iepm(&mut self) -> IEPM_W { IEPM_W::new(self) } #[doc = "Bits 16:31 - OUT EP interrupt mask bits"] #[inline(always)] #[must_use] - pub fn oepm(&mut self) -> OEPM_W<16> { + pub fn oepm(&mut self) -> OEPM_W { OEPM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS all endpoints interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daintmsk](index.html) module"] +#[doc = "OTG_HS all endpoints interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`daintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DAINTMSK_SPEC; impl crate::RegisterSpec for DAINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [daintmsk::R](R) reader structure"] -impl crate::Readable for DAINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [daintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`daintmsk::R`](R) reader structure"] +impl crate::Readable for DAINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`daintmsk::W`](W) writer structure"] impl crate::Writable for DAINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/dcfg.rs b/crates/bcm2837-lpa/src/usb_otg_device/dcfg.rs index ad6ef16..fc2bbc8 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/dcfg.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/dcfg.rs @@ -1,59 +1,27 @@ #[doc = "Register `DCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DSPD` reader - Device speed"] -pub type DSPD_R = crate::FieldReader; +pub type DSPD_R = crate::FieldReader; #[doc = "Field `DSPD` writer - Device speed"] -pub type DSPD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +pub type DSPD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `NZLSOHSK` reader - Nonzero-length status OUT handshake"] -pub type NZLSOHSK_R = crate::BitReader; +pub type NZLSOHSK_R = crate::BitReader; #[doc = "Field `NZLSOHSK` writer - Nonzero-length status OUT handshake"] -pub type NZLSOHSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCFG_SPEC, bool, O>; +pub type NZLSOHSK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DAD` reader - Device address"] -pub type DAD_R = crate::FieldReader; +pub type DAD_R = crate::FieldReader; #[doc = "Field `DAD` writer - Device address"] -pub type DAD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 7, O>; +pub type DAD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `PFIVL` reader - Periodic (micro)frame interval"] -pub type PFIVL_R = crate::FieldReader; +pub type PFIVL_R = crate::FieldReader; #[doc = "Field `PFIVL` writer - Periodic (micro)frame interval"] -pub type PFIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +pub type PFIVL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `PERSCHIVL` reader - Periodic scheduling interval"] -pub type PERSCHIVL_R = crate::FieldReader; +pub type PERSCHIVL_R = crate::FieldReader; #[doc = "Field `PERSCHIVL` writer - Periodic scheduling interval"] -pub type PERSCHIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u8, u8, 2, O>; +pub type PERSCHIVL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:1 - Device speed"] #[inline(always)] @@ -81,56 +49,73 @@ impl R { PERSCHIVL_R::new(((self.bits >> 24) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DCFG") + .field("dspd", &format_args!("{}", self.dspd().bits())) + .field("nzlsohsk", &format_args!("{}", self.nzlsohsk().bit())) + .field("dad", &format_args!("{}", self.dad().bits())) + .field("pfivl", &format_args!("{}", self.pfivl().bits())) + .field("perschivl", &format_args!("{}", self.perschivl().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - Device speed"] #[inline(always)] #[must_use] - pub fn dspd(&mut self) -> DSPD_W<0> { + pub fn dspd(&mut self) -> DSPD_W { DSPD_W::new(self) } #[doc = "Bit 2 - Nonzero-length status OUT handshake"] #[inline(always)] #[must_use] - pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<2> { + pub fn nzlsohsk(&mut self) -> NZLSOHSK_W { NZLSOHSK_W::new(self) } #[doc = "Bits 4:10 - Device address"] #[inline(always)] #[must_use] - pub fn dad(&mut self) -> DAD_W<4> { + pub fn dad(&mut self) -> DAD_W { DAD_W::new(self) } #[doc = "Bits 11:12 - Periodic (micro)frame interval"] #[inline(always)] #[must_use] - pub fn pfivl(&mut self) -> PFIVL_W<11> { + pub fn pfivl(&mut self) -> PFIVL_W { PFIVL_W::new(self) } #[doc = "Bits 24:25 - Periodic scheduling interval"] #[inline(always)] #[must_use] - pub fn perschivl(&mut self) -> PERSCHIVL_W<24> { + pub fn perschivl(&mut self) -> PERSCHIVL_W { PERSCHIVL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +#[doc = "OTG_HS device configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DCFG_SPEC; impl crate::RegisterSpec for DCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dcfg::R](R) reader structure"] -impl crate::Readable for DCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`dcfg::R`](R) reader structure"] +impl crate::Readable for DCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dcfg::W`](W) writer structure"] impl crate::Writable for DCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/dctl.rs b/crates/bcm2837-lpa/src/usb_otg_device/dctl.rs index ed73ebd..42ffebd 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/dctl.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/dctl.rs @@ -1,67 +1,35 @@ #[doc = "Register `DCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RWUSIG` reader - Remote wakeup signaling"] -pub type RWUSIG_R = crate::BitReader; +pub type RWUSIG_R = crate::BitReader; #[doc = "Field `RWUSIG` writer - Remote wakeup signaling"] -pub type RWUSIG_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type RWUSIG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SDIS` reader - Soft disconnect"] -pub type SDIS_R = crate::BitReader; +pub type SDIS_R = crate::BitReader; #[doc = "Field `SDIS` writer - Soft disconnect"] -pub type SDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type SDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GINSTS` reader - Global IN NAK status"] -pub type GINSTS_R = crate::BitReader; +pub type GINSTS_R = crate::BitReader; #[doc = "Field `GONSTS` reader - Global OUT NAK status"] -pub type GONSTS_R = crate::BitReader; +pub type GONSTS_R = crate::BitReader; #[doc = "Field `TCTL` reader - Test control"] -pub type TCTL_R = crate::FieldReader; +pub type TCTL_R = crate::FieldReader; #[doc = "Field `TCTL` writer - Test control"] -pub type TCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCTL_SPEC, u8, u8, 3, O>; +pub type TCTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `SGINAK` writer - Set global IN NAK"] -pub type SGINAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type SGINAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CGINAK` writer - Clear global IN NAK"] -pub type CGINAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type CGINAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SGONAK` writer - Set global OUT NAK"] -pub type SGONAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type SGONAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CGONAK` writer - Clear global OUT NAK"] -pub type CGONAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type CGONAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POPRGDNE` reader - Power-on programming done"] -pub type POPRGDNE_R = crate::BitReader; +pub type POPRGDNE_R = crate::BitReader; #[doc = "Field `POPRGDNE` writer - Power-on programming done"] -pub type POPRGDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCTL_SPEC, bool, O>; +pub type POPRGDNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Remote wakeup signaling"] #[inline(always)] @@ -94,74 +62,92 @@ impl R { POPRGDNE_R::new(((self.bits >> 11) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DCTL") + .field("rwusig", &format_args!("{}", self.rwusig().bit())) + .field("sdis", &format_args!("{}", self.sdis().bit())) + .field("ginsts", &format_args!("{}", self.ginsts().bit())) + .field("gonsts", &format_args!("{}", self.gonsts().bit())) + .field("tctl", &format_args!("{}", self.tctl().bits())) + .field("poprgdne", &format_args!("{}", self.poprgdne().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Remote wakeup signaling"] #[inline(always)] #[must_use] - pub fn rwusig(&mut self) -> RWUSIG_W<0> { + pub fn rwusig(&mut self) -> RWUSIG_W { RWUSIG_W::new(self) } #[doc = "Bit 1 - Soft disconnect"] #[inline(always)] #[must_use] - pub fn sdis(&mut self) -> SDIS_W<1> { + pub fn sdis(&mut self) -> SDIS_W { SDIS_W::new(self) } #[doc = "Bits 4:6 - Test control"] #[inline(always)] #[must_use] - pub fn tctl(&mut self) -> TCTL_W<4> { + pub fn tctl(&mut self) -> TCTL_W { TCTL_W::new(self) } #[doc = "Bit 7 - Set global IN NAK"] #[inline(always)] #[must_use] - pub fn sginak(&mut self) -> SGINAK_W<7> { + pub fn sginak(&mut self) -> SGINAK_W { SGINAK_W::new(self) } #[doc = "Bit 8 - Clear global IN NAK"] #[inline(always)] #[must_use] - pub fn cginak(&mut self) -> CGINAK_W<8> { + pub fn cginak(&mut self) -> CGINAK_W { CGINAK_W::new(self) } #[doc = "Bit 9 - Set global OUT NAK"] #[inline(always)] #[must_use] - pub fn sgonak(&mut self) -> SGONAK_W<9> { + pub fn sgonak(&mut self) -> SGONAK_W { SGONAK_W::new(self) } #[doc = "Bit 10 - Clear global OUT NAK"] #[inline(always)] #[must_use] - pub fn cgonak(&mut self) -> CGONAK_W<10> { + pub fn cgonak(&mut self) -> CGONAK_W { CGONAK_W::new(self) } #[doc = "Bit 11 - Power-on programming done"] #[inline(always)] #[must_use] - pub fn poprgdne(&mut self) -> POPRGDNE_W<11> { + pub fn poprgdne(&mut self) -> POPRGDNE_W { POPRGDNE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dctl](index.html) module"] +#[doc = "OTG_HS device control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DCTL_SPEC; impl crate::RegisterSpec for DCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dctl::R](R) reader structure"] -impl crate::Readable for DCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dctl::W](W) writer structure"] +#[doc = "`read()` method returns [`dctl::R`](R) reader structure"] +impl crate::Readable for DCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dctl::W`](W) writer structure"] impl crate::Writable for DCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/deachint.rs b/crates/bcm2837-lpa/src/usb_otg_device/deachint.rs index b2e2a0b..f8f0c35 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/deachint.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/deachint.rs @@ -1,47 +1,15 @@ #[doc = "Register `DEACHINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEACHINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IEP1INT` reader - IN endpoint 1interrupt bit"] -pub type IEP1INT_R = crate::BitReader; +pub type IEP1INT_R = crate::BitReader; #[doc = "Field `IEP1INT` writer - IN endpoint 1interrupt bit"] -pub type IEP1INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINT_SPEC, bool, O>; +pub type IEP1INT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEP1INT` reader - OUT endpoint 1 interrupt bit"] -pub type OEP1INT_R = crate::BitReader; +pub type OEP1INT_R = crate::BitReader; #[doc = "Field `OEP1INT` writer - OUT endpoint 1 interrupt bit"] -pub type OEP1INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINT_SPEC, bool, O>; +pub type OEP1INT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - IN endpoint 1interrupt bit"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { OEP1INT_R::new(((self.bits >> 17) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEACHINT") + .field("iep1int", &format_args!("{}", self.iep1int().bit())) + .field("oep1int", &format_args!("{}", self.oep1int().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - IN endpoint 1interrupt bit"] #[inline(always)] #[must_use] - pub fn iep1int(&mut self) -> IEP1INT_W<1> { + pub fn iep1int(&mut self) -> IEP1INT_W { IEP1INT_W::new(self) } #[doc = "Bit 17 - OUT endpoint 1 interrupt bit"] #[inline(always)] #[must_use] - pub fn oep1int(&mut self) -> OEP1INT_W<17> { + pub fn oep1int(&mut self) -> OEP1INT_W { OEP1INT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device each endpoint interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deachint](index.html) module"] +#[doc = "OTG_HS device each endpoint interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deachint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deachint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEACHINT_SPEC; impl crate::RegisterSpec for DEACHINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deachint::R](R) reader structure"] -impl crate::Readable for DEACHINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [deachint::W](W) writer structure"] +#[doc = "`read()` method returns [`deachint::R`](R) reader structure"] +impl crate::Readable for DEACHINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`deachint::W`](W) writer structure"] impl crate::Writable for DEACHINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/deachintmsk.rs b/crates/bcm2837-lpa/src/usb_otg_device/deachintmsk.rs index 635cecf..8979089 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/deachintmsk.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/deachintmsk.rs @@ -1,47 +1,15 @@ #[doc = "Register `DEACHINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEACHINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IEP1INTM` reader - IN Endpoint 1 interrupt mask bit"] -pub type IEP1INTM_R = crate::BitReader; +pub type IEP1INTM_R = crate::BitReader; #[doc = "Field `IEP1INTM` writer - IN Endpoint 1 interrupt mask bit"] -pub type IEP1INTM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINTMSK_SPEC, bool, O>; +pub type IEP1INTM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEP1INTM` reader - OUT Endpoint 1 interrupt mask bit"] -pub type OEP1INTM_R = crate::BitReader; +pub type OEP1INTM_R = crate::BitReader; #[doc = "Field `OEP1INTM` writer - OUT Endpoint 1 interrupt mask bit"] -pub type OEP1INTM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEACHINTMSK_SPEC, bool, O>; +pub type OEP1INTM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - IN Endpoint 1 interrupt mask bit"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { OEP1INTM_R::new(((self.bits >> 17) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEACHINTMSK") + .field("iep1intm", &format_args!("{}", self.iep1intm().bit())) + .field("oep1intm", &format_args!("{}", self.oep1intm().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - IN Endpoint 1 interrupt mask bit"] #[inline(always)] #[must_use] - pub fn iep1intm(&mut self) -> IEP1INTM_W<1> { + pub fn iep1intm(&mut self) -> IEP1INTM_W { IEP1INTM_W::new(self) } #[doc = "Bit 17 - OUT Endpoint 1 interrupt mask bit"] #[inline(always)] #[must_use] - pub fn oep1intm(&mut self) -> OEP1INTM_W<17> { + pub fn oep1intm(&mut self) -> OEP1INTM_W { OEP1INTM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device each endpoint interrupt register mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deachintmsk](index.html) module"] +#[doc = "OTG_HS device each endpoint interrupt register mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deachintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deachintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEACHINTMSK_SPEC; impl crate::RegisterSpec for DEACHINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deachintmsk::R](R) reader structure"] -impl crate::Readable for DEACHINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [deachintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`deachintmsk::R`](R) reader structure"] +impl crate::Readable for DEACHINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`deachintmsk::W`](W) writer structure"] impl crate::Writable for DEACHINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/diepeachmsk1.rs b/crates/bcm2837-lpa/src/usb_otg_device/diepeachmsk1.rs index 6e00947..b6d85a8 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/diepeachmsk1.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/diepeachmsk1.rs @@ -1,75 +1,43 @@ #[doc = "Register `DIEPEACHMSK1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPEACHMSK1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] -pub type EPDM_R = crate::BitReader; +pub type EPDM_R = crate::BitReader; #[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] -pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type EPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOM` reader - Timeout condition mask (nonisochronous endpoints)"] -pub type TOM_R = crate::BitReader; +pub type TOM_R = crate::BitReader; #[doc = "Field `TOM` writer - Timeout condition mask (nonisochronous endpoints)"] -pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type TOM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_R = crate::BitReader; +pub type ITTXFEMSK_R = crate::BitReader; #[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type ITTXFEMSK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] -pub type INEPNMM_R = crate::BitReader; +pub type INEPNMM_R = crate::BitReader; #[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] -pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type INEPNMM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] -pub type INEPNEM_R = crate::BitReader; +pub type INEPNEM_R = crate::BitReader; #[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] -pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type INEPNEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFURM` reader - FIFO underrun mask"] -pub type TXFURM_R = crate::BitReader; +pub type TXFURM_R = crate::BitReader; #[doc = "Field `TXFURM` writer - FIFO underrun mask"] -pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type TXFURM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BIM` reader - BNA interrupt mask"] -pub type BIM_R = crate::BitReader; +pub type BIM_R = crate::BitReader; #[doc = "Field `BIM` writer - BNA interrupt mask"] -pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type BIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKM` reader - NAK interrupt mask"] -pub type NAKM_R = crate::BitReader; +pub type NAKM_R = crate::BitReader; #[doc = "Field `NAKM` writer - NAK interrupt mask"] -pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPEACHMSK1_SPEC, bool, O>; +pub type NAKM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] @@ -117,80 +85,101 @@ impl R { NAKM_R::new(((self.bits >> 13) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPEACHMSK1") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("epdm", &format_args!("{}", self.epdm().bit())) + .field("tom", &format_args!("{}", self.tom().bit())) + .field("ittxfemsk", &format_args!("{}", self.ittxfemsk().bit())) + .field("inepnmm", &format_args!("{}", self.inepnmm().bit())) + .field("inepnem", &format_args!("{}", self.inepnem().bit())) + .field("txfurm", &format_args!("{}", self.txfurm().bit())) + .field("bim", &format_args!("{}", self.bim().bit())) + .field("nakm", &format_args!("{}", self.nakm().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt mask"] #[inline(always)] #[must_use] - pub fn epdm(&mut self) -> EPDM_W<1> { + pub fn epdm(&mut self) -> EPDM_W { EPDM_W::new(self) } #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] #[inline(always)] #[must_use] - pub fn tom(&mut self) -> TOM_W<3> { + pub fn tom(&mut self) -> TOM_W { TOM_W::new(self) } #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W { ITTXFEMSK_W::new(self) } #[doc = "Bit 5 - IN token received with EP mismatch mask"] #[inline(always)] #[must_use] - pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + pub fn inepnmm(&mut self) -> INEPNMM_W { INEPNMM_W::new(self) } #[doc = "Bit 6 - IN endpoint NAK effective mask"] #[inline(always)] #[must_use] - pub fn inepnem(&mut self) -> INEPNEM_W<6> { + pub fn inepnem(&mut self) -> INEPNEM_W { INEPNEM_W::new(self) } #[doc = "Bit 8 - FIFO underrun mask"] #[inline(always)] #[must_use] - pub fn txfurm(&mut self) -> TXFURM_W<8> { + pub fn txfurm(&mut self) -> TXFURM_W { TXFURM_W::new(self) } #[doc = "Bit 9 - BNA interrupt mask"] #[inline(always)] #[must_use] - pub fn bim(&mut self) -> BIM_W<9> { + pub fn bim(&mut self) -> BIM_W { BIM_W::new(self) } #[doc = "Bit 13 - NAK interrupt mask"] #[inline(always)] #[must_use] - pub fn nakm(&mut self) -> NAKM_W<13> { + pub fn nakm(&mut self) -> NAKM_W { NAKM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device each in endpoint-1 interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepeachmsk1](index.html) module"] +#[doc = "OTG_HS device each in endpoint-1 interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepeachmsk1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepeachmsk1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPEACHMSK1_SPEC; impl crate::RegisterSpec for DIEPEACHMSK1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepeachmsk1::R](R) reader structure"] -impl crate::Readable for DIEPEACHMSK1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepeachmsk1::W](W) writer structure"] +#[doc = "`read()` method returns [`diepeachmsk1::R`](R) reader structure"] +impl crate::Readable for DIEPEACHMSK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepeachmsk1::W`](W) writer structure"] impl crate::Writable for DIEPEACHMSK1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/diepempmsk.rs b/crates/bcm2837-lpa/src/usb_otg_device/diepempmsk.rs index 8e5b978..89831f3 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/diepempmsk.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/diepempmsk.rs @@ -1,44 +1,11 @@ #[doc = "Register `DIEPEMPMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPEMPMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXFEM` reader - IN EP Tx FIFO empty interrupt mask bits"] -pub type INEPTXFEM_R = crate::FieldReader; +pub type INEPTXFEM_R = crate::FieldReader; #[doc = "Field `INEPTXFEM` writer - IN EP Tx FIFO empty interrupt mask bits"] -pub type INEPTXFEM_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, DIEPEMPMSK_SPEC, u16, u16, 16, O>; +pub type INEPTXFEM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits"] #[inline(always)] @@ -46,32 +13,45 @@ impl R { INEPTXFEM_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPEMPMSK") + .field("ineptxfem", &format_args!("{}", self.ineptxfem().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits"] #[inline(always)] #[must_use] - pub fn ineptxfem(&mut self) -> INEPTXFEM_W<0> { + pub fn ineptxfem(&mut self) -> INEPTXFEM_W { INEPTXFEM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepempmsk](index.html) module"] +#[doc = "OTG_HS device IN endpoint FIFO empty interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepempmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepempmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPEMPMSK_SPEC; impl crate::RegisterSpec for DIEPEMPMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepempmsk::R](R) reader structure"] -impl crate::Readable for DIEPEMPMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepempmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`diepempmsk::R`](R) reader structure"] +impl crate::Readable for DIEPEMPMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepempmsk::W`](W) writer structure"] impl crate::Writable for DIEPEMPMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/diepmsk.rs b/crates/bcm2837-lpa/src/usb_otg_device/diepmsk.rs index 6411ce9..8bd397c 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/diepmsk.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/diepmsk.rs @@ -1,71 +1,39 @@ #[doc = "Register `DIEPMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] -pub type EPDM_R = crate::BitReader; +pub type EPDM_R = crate::BitReader; #[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] -pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type EPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOM` reader - Timeout condition mask (nonisochronous endpoints)"] -pub type TOM_R = crate::BitReader; +pub type TOM_R = crate::BitReader; #[doc = "Field `TOM` writer - Timeout condition mask (nonisochronous endpoints)"] -pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type TOM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_R = crate::BitReader; +pub type ITTXFEMSK_R = crate::BitReader; #[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type ITTXFEMSK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] -pub type INEPNMM_R = crate::BitReader; +pub type INEPNMM_R = crate::BitReader; #[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] -pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type INEPNMM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] -pub type INEPNEM_R = crate::BitReader; +pub type INEPNEM_R = crate::BitReader; #[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] -pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type INEPNEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFURM` reader - FIFO underrun mask"] -pub type TXFURM_R = crate::BitReader; +pub type TXFURM_R = crate::BitReader; #[doc = "Field `TXFURM` writer - FIFO underrun mask"] -pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type TXFURM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BIM` reader - BNA interrupt mask"] -pub type BIM_R = crate::BitReader; +pub type BIM_R = crate::BitReader; #[doc = "Field `BIM` writer - BNA interrupt mask"] -pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPMSK_SPEC, bool, O>; +pub type BIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] @@ -108,74 +76,94 @@ impl R { BIM_R::new(((self.bits >> 9) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPMSK") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("epdm", &format_args!("{}", self.epdm().bit())) + .field("tom", &format_args!("{}", self.tom().bit())) + .field("ittxfemsk", &format_args!("{}", self.ittxfemsk().bit())) + .field("inepnmm", &format_args!("{}", self.inepnmm().bit())) + .field("inepnem", &format_args!("{}", self.inepnem().bit())) + .field("txfurm", &format_args!("{}", self.txfurm().bit())) + .field("bim", &format_args!("{}", self.bim().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt mask"] #[inline(always)] #[must_use] - pub fn epdm(&mut self) -> EPDM_W<1> { + pub fn epdm(&mut self) -> EPDM_W { EPDM_W::new(self) } #[doc = "Bit 3 - Timeout condition mask (nonisochronous endpoints)"] #[inline(always)] #[must_use] - pub fn tom(&mut self) -> TOM_W<3> { + pub fn tom(&mut self) -> TOM_W { TOM_W::new(self) } #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W { ITTXFEMSK_W::new(self) } #[doc = "Bit 5 - IN token received with EP mismatch mask"] #[inline(always)] #[must_use] - pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + pub fn inepnmm(&mut self) -> INEPNMM_W { INEPNMM_W::new(self) } #[doc = "Bit 6 - IN endpoint NAK effective mask"] #[inline(always)] #[must_use] - pub fn inepnem(&mut self) -> INEPNEM_W<6> { + pub fn inepnem(&mut self) -> INEPNEM_W { INEPNEM_W::new(self) } #[doc = "Bit 8 - FIFO underrun mask"] #[inline(always)] #[must_use] - pub fn txfurm(&mut self) -> TXFURM_W<8> { + pub fn txfurm(&mut self) -> TXFURM_W { TXFURM_W::new(self) } #[doc = "Bit 9 - BNA interrupt mask"] #[inline(always)] #[must_use] - pub fn bim(&mut self) -> BIM_W<9> { + pub fn bim(&mut self) -> BIM_W { BIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint common interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepmsk](index.html) module"] +#[doc = "OTG_HS device IN endpoint common interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPMSK_SPEC; impl crate::RegisterSpec for DIEPMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepmsk::R](R) reader structure"] -impl crate::Readable for DIEPMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`diepmsk::R`](R) reader structure"] +impl crate::Readable for DIEPMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepmsk::W`](W) writer structure"] impl crate::Writable for DIEPMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/doepeachmsk1.rs b/crates/bcm2837-lpa/src/usb_otg_device/doepeachmsk1.rs index 31a5ab1..7c60dcc 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/doepeachmsk1.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/doepeachmsk1.rs @@ -1,83 +1,51 @@ #[doc = "Register `DOEPEACHMSK1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPEACHMSK1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] -pub type EPDM_R = crate::BitReader; +pub type EPDM_R = crate::BitReader; #[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] -pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type EPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOM` reader - Timeout condition mask"] -pub type TOM_R = crate::BitReader; +pub type TOM_R = crate::BitReader; #[doc = "Field `TOM` writer - Timeout condition mask"] -pub type TOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type TOM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITTXFEMSK` reader - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_R = crate::BitReader; +pub type ITTXFEMSK_R = crate::BitReader; #[doc = "Field `ITTXFEMSK` writer - IN token received when TxFIFO empty mask"] -pub type ITTXFEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type ITTXFEMSK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNMM` reader - IN token received with EP mismatch mask"] -pub type INEPNMM_R = crate::BitReader; +pub type INEPNMM_R = crate::BitReader; #[doc = "Field `INEPNMM` writer - IN token received with EP mismatch mask"] -pub type INEPNMM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type INEPNMM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNEM` reader - IN endpoint NAK effective mask"] -pub type INEPNEM_R = crate::BitReader; +pub type INEPNEM_R = crate::BitReader; #[doc = "Field `INEPNEM` writer - IN endpoint NAK effective mask"] -pub type INEPNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type INEPNEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFURM` reader - OUT packet error mask"] -pub type TXFURM_R = crate::BitReader; +pub type TXFURM_R = crate::BitReader; #[doc = "Field `TXFURM` writer - OUT packet error mask"] -pub type TXFURM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type TXFURM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BIM` reader - BNA interrupt mask"] -pub type BIM_R = crate::BitReader; +pub type BIM_R = crate::BitReader; #[doc = "Field `BIM` writer - BNA interrupt mask"] -pub type BIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type BIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BERRM` reader - Bubble error interrupt mask"] -pub type BERRM_R = crate::BitReader; +pub type BERRM_R = crate::BitReader; #[doc = "Field `BERRM` writer - Bubble error interrupt mask"] -pub type BERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type BERRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKM` reader - NAK interrupt mask"] -pub type NAKM_R = crate::BitReader; +pub type NAKM_R = crate::BitReader; #[doc = "Field `NAKM` writer - NAK interrupt mask"] -pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type NAKM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYETM` reader - NYET interrupt mask"] -pub type NYETM_R = crate::BitReader; +pub type NYETM_R = crate::BitReader; #[doc = "Field `NYETM` writer - NYET interrupt mask"] -pub type NYETM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPEACHMSK1_SPEC, bool, O>; +pub type NYETM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] @@ -135,92 +103,115 @@ impl R { NYETM_R::new(((self.bits >> 14) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPEACHMSK1") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("epdm", &format_args!("{}", self.epdm().bit())) + .field("tom", &format_args!("{}", self.tom().bit())) + .field("ittxfemsk", &format_args!("{}", self.ittxfemsk().bit())) + .field("inepnmm", &format_args!("{}", self.inepnmm().bit())) + .field("inepnem", &format_args!("{}", self.inepnem().bit())) + .field("txfurm", &format_args!("{}", self.txfurm().bit())) + .field("bim", &format_args!("{}", self.bim().bit())) + .field("berrm", &format_args!("{}", self.berrm().bit())) + .field("nakm", &format_args!("{}", self.nakm().bit())) + .field("nyetm", &format_args!("{}", self.nyetm().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt mask"] #[inline(always)] #[must_use] - pub fn epdm(&mut self) -> EPDM_W<1> { + pub fn epdm(&mut self) -> EPDM_W { EPDM_W::new(self) } #[doc = "Bit 3 - Timeout condition mask"] #[inline(always)] #[must_use] - pub fn tom(&mut self) -> TOM_W<3> { + pub fn tom(&mut self) -> TOM_W { TOM_W::new(self) } #[doc = "Bit 4 - IN token received when TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<4> { + pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W { ITTXFEMSK_W::new(self) } #[doc = "Bit 5 - IN token received with EP mismatch mask"] #[inline(always)] #[must_use] - pub fn inepnmm(&mut self) -> INEPNMM_W<5> { + pub fn inepnmm(&mut self) -> INEPNMM_W { INEPNMM_W::new(self) } #[doc = "Bit 6 - IN endpoint NAK effective mask"] #[inline(always)] #[must_use] - pub fn inepnem(&mut self) -> INEPNEM_W<6> { + pub fn inepnem(&mut self) -> INEPNEM_W { INEPNEM_W::new(self) } #[doc = "Bit 8 - OUT packet error mask"] #[inline(always)] #[must_use] - pub fn txfurm(&mut self) -> TXFURM_W<8> { + pub fn txfurm(&mut self) -> TXFURM_W { TXFURM_W::new(self) } #[doc = "Bit 9 - BNA interrupt mask"] #[inline(always)] #[must_use] - pub fn bim(&mut self) -> BIM_W<9> { + pub fn bim(&mut self) -> BIM_W { BIM_W::new(self) } #[doc = "Bit 12 - Bubble error interrupt mask"] #[inline(always)] #[must_use] - pub fn berrm(&mut self) -> BERRM_W<12> { + pub fn berrm(&mut self) -> BERRM_W { BERRM_W::new(self) } #[doc = "Bit 13 - NAK interrupt mask"] #[inline(always)] #[must_use] - pub fn nakm(&mut self) -> NAKM_W<13> { + pub fn nakm(&mut self) -> NAKM_W { NAKM_W::new(self) } #[doc = "Bit 14 - NYET interrupt mask"] #[inline(always)] #[must_use] - pub fn nyetm(&mut self) -> NYETM_W<14> { + pub fn nyetm(&mut self) -> NYETM_W { NYETM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device each OUT endpoint-1 interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepeachmsk1](index.html) module"] +#[doc = "OTG_HS device each OUT endpoint-1 interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepeachmsk1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepeachmsk1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPEACHMSK1_SPEC; impl crate::RegisterSpec for DOEPEACHMSK1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepeachmsk1::R](R) reader structure"] -impl crate::Readable for DOEPEACHMSK1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepeachmsk1::W](W) writer structure"] +#[doc = "`read()` method returns [`doepeachmsk1::R`](R) reader structure"] +impl crate::Readable for DOEPEACHMSK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepeachmsk1::W`](W) writer structure"] impl crate::Writable for DOEPEACHMSK1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/doepmsk.rs b/crates/bcm2837-lpa/src/usb_otg_device/doepmsk.rs index 46e5ca8..dbed437 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/doepmsk.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/doepmsk.rs @@ -1,67 +1,35 @@ #[doc = "Register `DOEPMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed interrupt mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed interrupt mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDM` reader - Endpoint disabled interrupt mask"] -pub type EPDM_R = crate::BitReader; +pub type EPDM_R = crate::BitReader; #[doc = "Field `EPDM` writer - Endpoint disabled interrupt mask"] -pub type EPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type EPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STUPM` reader - SETUP phase done mask"] -pub type STUPM_R = crate::BitReader; +pub type STUPM_R = crate::BitReader; #[doc = "Field `STUPM` writer - SETUP phase done mask"] -pub type STUPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type STUPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OTEPDM` reader - OUT token received when endpoint disabled mask"] -pub type OTEPDM_R = crate::BitReader; +pub type OTEPDM_R = crate::BitReader; #[doc = "Field `OTEPDM` writer - OUT token received when endpoint disabled mask"] -pub type OTEPDM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type OTEPDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `B2BSTUP` reader - Back-to-back SETUP packets received mask"] -pub type B2BSTUP_R = crate::BitReader; +pub type B2BSTUP_R = crate::BitReader; #[doc = "Field `B2BSTUP` writer - Back-to-back SETUP packets received mask"] -pub type B2BSTUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type B2BSTUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OPEM` reader - OUT packet error mask"] -pub type OPEM_R = crate::BitReader; +pub type OPEM_R = crate::BitReader; #[doc = "Field `OPEM` writer - OUT packet error mask"] -pub type OPEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type OPEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOIM` reader - BNA interrupt mask"] -pub type BOIM_R = crate::BitReader; +pub type BOIM_R = crate::BitReader; #[doc = "Field `BOIM` writer - BNA interrupt mask"] -pub type BOIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPMSK_SPEC, bool, O>; +pub type BOIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] @@ -99,68 +67,87 @@ impl R { BOIM_R::new(((self.bits >> 9) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPMSK") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("epdm", &format_args!("{}", self.epdm().bit())) + .field("stupm", &format_args!("{}", self.stupm().bit())) + .field("otepdm", &format_args!("{}", self.otepdm().bit())) + .field("b2bstup", &format_args!("{}", self.b2bstup().bit())) + .field("opem", &format_args!("{}", self.opem().bit())) + .field("boim", &format_args!("{}", self.boim().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt mask"] #[inline(always)] #[must_use] - pub fn epdm(&mut self) -> EPDM_W<1> { + pub fn epdm(&mut self) -> EPDM_W { EPDM_W::new(self) } #[doc = "Bit 3 - SETUP phase done mask"] #[inline(always)] #[must_use] - pub fn stupm(&mut self) -> STUPM_W<3> { + pub fn stupm(&mut self) -> STUPM_W { STUPM_W::new(self) } #[doc = "Bit 4 - OUT token received when endpoint disabled mask"] #[inline(always)] #[must_use] - pub fn otepdm(&mut self) -> OTEPDM_W<4> { + pub fn otepdm(&mut self) -> OTEPDM_W { OTEPDM_W::new(self) } #[doc = "Bit 6 - Back-to-back SETUP packets received mask"] #[inline(always)] #[must_use] - pub fn b2bstup(&mut self) -> B2BSTUP_W<6> { + pub fn b2bstup(&mut self) -> B2BSTUP_W { B2BSTUP_W::new(self) } #[doc = "Bit 8 - OUT packet error mask"] #[inline(always)] #[must_use] - pub fn opem(&mut self) -> OPEM_W<8> { + pub fn opem(&mut self) -> OPEM_W { OPEM_W::new(self) } #[doc = "Bit 9 - BNA interrupt mask"] #[inline(always)] #[must_use] - pub fn boim(&mut self) -> BOIM_W<9> { + pub fn boim(&mut self) -> BOIM_W { BOIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device OUT endpoint common interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepmsk](index.html) module"] +#[doc = "OTG_HS device OUT endpoint common interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPMSK_SPEC; impl crate::RegisterSpec for DOEPMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepmsk::R](R) reader structure"] -impl crate::Readable for DOEPMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`doepmsk::R`](R) reader structure"] +impl crate::Readable for DOEPMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepmsk::W`](W) writer structure"] impl crate::Writable for DOEPMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/dsts.rs b/crates/bcm2837-lpa/src/usb_otg_device/dsts.rs index ddf0900..3d4bf4f 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/dsts.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/dsts.rs @@ -1,26 +1,13 @@ #[doc = "Register `DSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SUSPSTS` reader - Suspend status"] -pub type SUSPSTS_R = crate::BitReader; +pub type SUSPSTS_R = crate::BitReader; #[doc = "Field `ENUMSPD` reader - Enumerated speed"] -pub type ENUMSPD_R = crate::FieldReader; +pub type ENUMSPD_R = crate::FieldReader; #[doc = "Field `EERR` reader - Erratic error"] -pub type EERR_R = crate::BitReader; +pub type EERR_R = crate::BitReader; #[doc = "Field `FNSOF` reader - Frame number of the received SOF"] -pub type FNSOF_R = crate::FieldReader; +pub type FNSOF_R = crate::FieldReader; impl R { #[doc = "Bit 0 - Suspend status"] #[inline(always)] @@ -43,15 +30,28 @@ impl R { FNSOF_R::new(((self.bits >> 8) & 0x3fff) as u16) } } -#[doc = "OTG_HS device status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dsts](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSTS") + .field("suspsts", &format_args!("{}", self.suspsts().bit())) + .field("enumspd", &format_args!("{}", self.enumspd().bits())) + .field("eerr", &format_args!("{}", self.eerr().bit())) + .field("fnsof", &format_args!("{}", self.fnsof().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS device status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsts::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DSTS_SPEC; impl crate::RegisterSpec for DSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dsts::R](R) reader structure"] -impl crate::Readable for DSTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`dsts::R`](R) reader structure"] +impl crate::Readable for DSTS_SPEC {} #[doc = "`reset()` method sets DSTS to value 0x10"] impl crate::Resettable for DSTS_SPEC { const RESET_VALUE: Self::Ux = 0x10; diff --git a/crates/bcm2837-lpa/src/usb_otg_device/dthrctl.rs b/crates/bcm2837-lpa/src/usb_otg_device/dthrctl.rs index ea85092..5044505 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/dthrctl.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/dthrctl.rs @@ -1,63 +1,31 @@ #[doc = "Register `DTHRCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DTHRCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NONISOTHREN` reader - Nonisochronous IN endpoints threshold enable"] -pub type NONISOTHREN_R = crate::BitReader; +pub type NONISOTHREN_R = crate::BitReader; #[doc = "Field `NONISOTHREN` writer - Nonisochronous IN endpoints threshold enable"] -pub type NONISOTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +pub type NONISOTHREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISOTHREN` reader - ISO IN endpoint threshold enable"] -pub type ISOTHREN_R = crate::BitReader; +pub type ISOTHREN_R = crate::BitReader; #[doc = "Field `ISOTHREN` writer - ISO IN endpoint threshold enable"] -pub type ISOTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +pub type ISOTHREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXTHRLEN` reader - Transmit threshold length"] -pub type TXTHRLEN_R = crate::FieldReader; +pub type TXTHRLEN_R = crate::FieldReader; #[doc = "Field `TXTHRLEN` writer - Transmit threshold length"] -pub type TXTHRLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DTHRCTL_SPEC, u16, u16, 9, O>; +pub type TXTHRLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 9, O, u16>; #[doc = "Field `RXTHREN` reader - Receive threshold enable"] -pub type RXTHREN_R = crate::BitReader; +pub type RXTHREN_R = crate::BitReader; #[doc = "Field `RXTHREN` writer - Receive threshold enable"] -pub type RXTHREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +pub type RXTHREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXTHRLEN` reader - Receive threshold length"] -pub type RXTHRLEN_R = crate::FieldReader; +pub type RXTHRLEN_R = crate::FieldReader; #[doc = "Field `RXTHRLEN` writer - Receive threshold length"] -pub type RXTHRLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DTHRCTL_SPEC, u16, u16, 9, O>; +pub type RXTHRLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 9, O, u16>; #[doc = "Field `ARPEN` reader - Arbiter parking enable"] -pub type ARPEN_R = crate::BitReader; +pub type ARPEN_R = crate::BitReader; #[doc = "Field `ARPEN` writer - Arbiter parking enable"] -pub type ARPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTHRCTL_SPEC, bool, O>; +pub type ARPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Nonisochronous IN endpoints threshold enable"] #[inline(always)] @@ -90,62 +58,80 @@ impl R { ARPEN_R::new(((self.bits >> 27) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DTHRCTL") + .field("nonisothren", &format_args!("{}", self.nonisothren().bit())) + .field("isothren", &format_args!("{}", self.isothren().bit())) + .field("txthrlen", &format_args!("{}", self.txthrlen().bits())) + .field("rxthren", &format_args!("{}", self.rxthren().bit())) + .field("rxthrlen", &format_args!("{}", self.rxthrlen().bits())) + .field("arpen", &format_args!("{}", self.arpen().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Nonisochronous IN endpoints threshold enable"] #[inline(always)] #[must_use] - pub fn nonisothren(&mut self) -> NONISOTHREN_W<0> { + pub fn nonisothren(&mut self) -> NONISOTHREN_W { NONISOTHREN_W::new(self) } #[doc = "Bit 1 - ISO IN endpoint threshold enable"] #[inline(always)] #[must_use] - pub fn isothren(&mut self) -> ISOTHREN_W<1> { + pub fn isothren(&mut self) -> ISOTHREN_W { ISOTHREN_W::new(self) } #[doc = "Bits 2:10 - Transmit threshold length"] #[inline(always)] #[must_use] - pub fn txthrlen(&mut self) -> TXTHRLEN_W<2> { + pub fn txthrlen(&mut self) -> TXTHRLEN_W { TXTHRLEN_W::new(self) } #[doc = "Bit 16 - Receive threshold enable"] #[inline(always)] #[must_use] - pub fn rxthren(&mut self) -> RXTHREN_W<16> { + pub fn rxthren(&mut self) -> RXTHREN_W { RXTHREN_W::new(self) } #[doc = "Bits 17:25 - Receive threshold length"] #[inline(always)] #[must_use] - pub fn rxthrlen(&mut self) -> RXTHRLEN_W<17> { + pub fn rxthrlen(&mut self) -> RXTHRLEN_W { RXTHRLEN_W::new(self) } #[doc = "Bit 27 - Arbiter parking enable"] #[inline(always)] #[must_use] - pub fn arpen(&mut self) -> ARPEN_W<27> { + pub fn arpen(&mut self) -> ARPEN_W { ARPEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS Device threshold control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dthrctl](index.html) module"] +#[doc = "OTG_HS Device threshold control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dthrctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dthrctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DTHRCTL_SPEC; impl crate::RegisterSpec for DTHRCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dthrctl::R](R) reader structure"] -impl crate::Readable for DTHRCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dthrctl::W](W) writer structure"] +#[doc = "`read()` method returns [`dthrctl::R`](R) reader structure"] +impl crate::Readable for DTHRCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dthrctl::W`](W) writer structure"] impl crate::Writable for DTHRCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/dvbusdis.rs b/crates/bcm2837-lpa/src/usb_otg_device/dvbusdis.rs index 403e00a..06b297e 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/dvbusdis.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/dvbusdis.rs @@ -1,43 +1,11 @@ #[doc = "Register `DVBUSDIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DVBUSDIS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VBUSDT` reader - Device VBUS discharge time"] -pub type VBUSDT_R = crate::FieldReader; +pub type VBUSDT_R = crate::FieldReader; #[doc = "Field `VBUSDT` writer - Device VBUS discharge time"] -pub type VBUSDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DVBUSDIS_SPEC, u16, u16, 16, O>; +pub type VBUSDT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Device VBUS discharge time"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { VBUSDT_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DVBUSDIS") + .field("vbusdt", &format_args!("{}", self.vbusdt().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Device VBUS discharge time"] #[inline(always)] #[must_use] - pub fn vbusdt(&mut self) -> VBUSDT_W<0> { + pub fn vbusdt(&mut self) -> VBUSDT_W { VBUSDT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device VBUS discharge time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbusdis](index.html) module"] +#[doc = "OTG_HS device VBUS discharge time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dvbusdis::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dvbusdis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DVBUSDIS_SPEC; impl crate::RegisterSpec for DVBUSDIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dvbusdis::R](R) reader structure"] -impl crate::Readable for DVBUSDIS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dvbusdis::W](W) writer structure"] +#[doc = "`read()` method returns [`dvbusdis::R`](R) reader structure"] +impl crate::Readable for DVBUSDIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dvbusdis::W`](W) writer structure"] impl crate::Writable for DVBUSDIS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/dvbuspulse.rs b/crates/bcm2837-lpa/src/usb_otg_device/dvbuspulse.rs index 4871f7b..52acecf 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/dvbuspulse.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/dvbuspulse.rs @@ -1,43 +1,11 @@ #[doc = "Register `DVBUSPULSE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DVBUSPULSE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DVBUSP` reader - Device VBUS pulsing time"] -pub type DVBUSP_R = crate::FieldReader; +pub type DVBUSP_R = crate::FieldReader; #[doc = "Field `DVBUSP` writer - Device VBUS pulsing time"] -pub type DVBUSP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DVBUSPULSE_SPEC, u16, u16, 12, O>; +pub type DVBUSP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; impl R { #[doc = "Bits 0:11 - Device VBUS pulsing time"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DVBUSP_R::new((self.bits & 0x0fff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DVBUSPULSE") + .field("dvbusp", &format_args!("{}", self.dvbusp().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:11 - Device VBUS pulsing time"] #[inline(always)] #[must_use] - pub fn dvbusp(&mut self) -> DVBUSP_W<0> { + pub fn dvbusp(&mut self) -> DVBUSP_W { DVBUSP_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device VBUS pulsing time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbuspulse](index.html) module"] +#[doc = "OTG_HS device VBUS pulsing time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dvbuspulse::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dvbuspulse::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DVBUSPULSE_SPEC; impl crate::RegisterSpec for DVBUSPULSE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dvbuspulse::R](R) reader structure"] -impl crate::Readable for DVBUSPULSE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dvbuspulse::W](W) writer structure"] +#[doc = "`read()` method returns [`dvbuspulse::R`](R) reader structure"] +impl crate::Readable for DVBUSPULSE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dvbuspulse::W`](W) writer structure"] impl crate::Writable for DVBUSPULSE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint.rs b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint.rs index 5fd5349..0e94feb 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct IN_ENDPOINT { #[doc = "0x00 - Control"] pub diepctl0: DIEPCTL0, @@ -14,23 +15,28 @@ pub struct IN_ENDPOINT { #[doc = "0x18 - Transmit FIFO status"] pub dtxfsts: DTXFSTS, } -#[doc = "DIEPCTL0 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPCTL0 (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepctl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepctl0`] +module"] pub type DIEPCTL0 = crate::Reg; #[doc = "Control"] pub mod diepctl0; -#[doc = "DIEPINT (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPINT (rw) register accessor: Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepint`] +module"] pub type DIEPINT = crate::Reg; #[doc = "Interrupt"] pub mod diepint; -#[doc = "DIEPTSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTSIZ (rw) register accessor: Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptsiz`] +module"] pub type DIEPTSIZ = crate::Reg; #[doc = "Transfer size"] pub mod dieptsiz; -#[doc = "DIEPDMA (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPDMA (rw) register accessor: DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepdma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepdma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@diepdma`] +module"] pub type DIEPDMA = crate::Reg; #[doc = "DMA address"] pub mod diepdma; -#[doc = "DTXFSTS (r) register accessor: an alias for `Reg`"] +#[doc = "DTXFSTS (r) register accessor: Transmit FIFO status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtxfsts::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtxfsts`] +module"] pub type DTXFSTS = crate::Reg; #[doc = "Transmit FIFO status"] pub mod dtxfsts; diff --git a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs index b8fa051..899b0d7 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepctl0.rs @@ -1,79 +1,47 @@ #[doc = "Register `DIEPCTL0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPCTL0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MPSIZ` reader - Maximum packet size"] -pub type MPSIZ_R = crate::FieldReader; +pub type MPSIZ_R = crate::FieldReader; #[doc = "Field `MPSIZ` writer - Maximum packet size"] -pub type MPSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u16, u16, 11, O>; +pub type MPSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 11, O, u16>; #[doc = "Field `USBAEP` reader - USB active endpoint"] -pub type USBAEP_R = crate::BitReader; +pub type USBAEP_R = crate::BitReader; #[doc = "Field `USBAEP` writer - USB active endpoint"] -pub type USBAEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type USBAEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EONUM_DPID` reader - Even/odd frame"] -pub type EONUM_DPID_R = crate::BitReader; +pub type EONUM_DPID_R = crate::BitReader; #[doc = "Field `NAKSTS` reader - NAK status"] -pub type NAKSTS_R = crate::BitReader; +pub type NAKSTS_R = crate::BitReader; #[doc = "Field `EPTYP` reader - Endpoint type"] -pub type EPTYP_R = crate::FieldReader; +pub type EPTYP_R = crate::FieldReader; #[doc = "Field `EPTYP` writer - Endpoint type"] -pub type EPTYP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u8, u8, 2, O>; +pub type EPTYP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `Stall` reader - STALL handshake"] -pub type STALL_R = crate::BitReader; +pub type STALL_R = crate::BitReader; #[doc = "Field `Stall` writer - STALL handshake"] -pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFNUM` reader - TxFIFO number"] -pub type TXFNUM_R = crate::FieldReader; +pub type TXFNUM_R = crate::FieldReader; #[doc = "Field `TXFNUM` writer - TxFIFO number"] -pub type TXFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPCTL0_SPEC, u8, u8, 4, O>; +pub type TXFNUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CNAK` writer - Clear NAK"] -pub type CNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type CNAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SNAK` writer - Set NAK"] -pub type SNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type SNAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SD0PID_SEVNFRM` writer - Set DATA0 PID"] -pub type SD0PID_SEVNFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type SD0PID_SEVNFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SODDFRM` writer - Set odd frame"] -pub type SODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type SODDFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDIS` reader - Endpoint disable"] -pub type EPDIS_R = crate::BitReader; +pub type EPDIS_R = crate::BitReader; #[doc = "Field `EPDIS` writer - Endpoint disable"] -pub type EPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type EPDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPENA` reader - Endpoint enable"] -pub type EPENA_R = crate::BitReader; +pub type EPENA_R = crate::BitReader; #[doc = "Field `EPENA` writer - Endpoint enable"] -pub type EPENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPCTL0_SPEC, bool, O>; +pub type EPENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] @@ -121,92 +89,113 @@ impl R { EPENA_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPCTL0") + .field("mpsiz", &format_args!("{}", self.mpsiz().bits())) + .field("usbaep", &format_args!("{}", self.usbaep().bit())) + .field("eonum_dpid", &format_args!("{}", self.eonum_dpid().bit())) + .field("naksts", &format_args!("{}", self.naksts().bit())) + .field("eptyp", &format_args!("{}", self.eptyp().bits())) + .field("stall", &format_args!("{}", self.stall().bit())) + .field("txfnum", &format_args!("{}", self.txfnum().bits())) + .field("epdis", &format_args!("{}", self.epdis().bit())) + .field("epena", &format_args!("{}", self.epena().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] #[must_use] - pub fn mpsiz(&mut self) -> MPSIZ_W<0> { + pub fn mpsiz(&mut self) -> MPSIZ_W { MPSIZ_W::new(self) } #[doc = "Bit 15 - USB active endpoint"] #[inline(always)] #[must_use] - pub fn usbaep(&mut self) -> USBAEP_W<15> { + pub fn usbaep(&mut self) -> USBAEP_W { USBAEP_W::new(self) } #[doc = "Bits 18:19 - Endpoint type"] #[inline(always)] #[must_use] - pub fn eptyp(&mut self) -> EPTYP_W<18> { + pub fn eptyp(&mut self) -> EPTYP_W { EPTYP_W::new(self) } #[doc = "Bit 21 - STALL handshake"] #[inline(always)] #[must_use] - pub fn stall(&mut self) -> STALL_W<21> { + pub fn stall(&mut self) -> STALL_W { STALL_W::new(self) } #[doc = "Bits 22:25 - TxFIFO number"] #[inline(always)] #[must_use] - pub fn txfnum(&mut self) -> TXFNUM_W<22> { + pub fn txfnum(&mut self) -> TXFNUM_W { TXFNUM_W::new(self) } #[doc = "Bit 26 - Clear NAK"] #[inline(always)] #[must_use] - pub fn cnak(&mut self) -> CNAK_W<26> { + pub fn cnak(&mut self) -> CNAK_W { CNAK_W::new(self) } #[doc = "Bit 27 - Set NAK"] #[inline(always)] #[must_use] - pub fn snak(&mut self) -> SNAK_W<27> { + pub fn snak(&mut self) -> SNAK_W { SNAK_W::new(self) } #[doc = "Bit 28 - Set DATA0 PID"] #[inline(always)] #[must_use] - pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<28> { + pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W { SD0PID_SEVNFRM_W::new(self) } #[doc = "Bit 29 - Set odd frame"] #[inline(always)] #[must_use] - pub fn soddfrm(&mut self) -> SODDFRM_W<29> { + pub fn soddfrm(&mut self) -> SODDFRM_W { SODDFRM_W::new(self) } #[doc = "Bit 30 - Endpoint disable"] #[inline(always)] #[must_use] - pub fn epdis(&mut self) -> EPDIS_W<30> { + pub fn epdis(&mut self) -> EPDIS_W { EPDIS_W::new(self) } #[doc = "Bit 31 - Endpoint enable"] #[inline(always)] #[must_use] - pub fn epena(&mut self) -> EPENA_W<31> { + pub fn epena(&mut self) -> EPENA_W { EPENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepctl0](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPCTL0_SPEC; impl crate::RegisterSpec for DIEPCTL0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepctl0::R](R) reader structure"] -impl crate::Readable for DIEPCTL0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepctl0::W](W) writer structure"] +#[doc = "`read()` method returns [`diepctl0::R`](R) reader structure"] +impl crate::Readable for DIEPCTL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepctl0::W`](W) writer structure"] impl crate::Writable for DIEPCTL0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepdma.rs b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepdma.rs index 321905e..18f13ad 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepdma.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepdma.rs @@ -1,43 +1,11 @@ #[doc = "Register `DIEPDMA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPDMA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMAADDR` reader - DMA address"] -pub type DMAADDR_R = crate::FieldReader; +pub type DMAADDR_R = crate::FieldReader; #[doc = "Field `DMAADDR` writer - DMA address"] -pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPDMA_SPEC, u32, u32, 32, O>; +pub type DMAADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DMAADDR_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPDMA") + .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] #[must_use] - pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + pub fn dmaaddr(&mut self) -> DMAADDR_W { DMAADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepdma](index.html) module"] +#[doc = "DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepdma::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepdma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPDMA_SPEC; impl crate::RegisterSpec for DIEPDMA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepdma::R](R) reader structure"] -impl crate::Readable for DIEPDMA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepdma::W](W) writer structure"] +#[doc = "`read()` method returns [`diepdma::R`](R) reader structure"] +impl crate::Readable for DIEPDMA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepdma::W`](W) writer structure"] impl crate::Writable for DIEPDMA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepint.rs b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepint.rs index f85ca85..bd21aa2 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepint.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/diepint.rs @@ -1,81 +1,49 @@ #[doc = "Register `DIEPINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRC` reader - Transfer completed interrupt"] -pub type XFRC_R = crate::BitReader; +pub type XFRC_R = crate::BitReader; #[doc = "Field `XFRC` writer - Transfer completed interrupt"] -pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type XFRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISD` reader - Endpoint disabled interrupt"] -pub type EPDISD_R = crate::BitReader; +pub type EPDISD_R = crate::BitReader; #[doc = "Field `EPDISD` writer - Endpoint disabled interrupt"] -pub type EPDISD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type EPDISD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOC` reader - Timeout condition"] -pub type TOC_R = crate::BitReader; +pub type TOC_R = crate::BitReader; #[doc = "Field `TOC` writer - Timeout condition"] -pub type TOC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type TOC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITTXFE` reader - IN token received when TxFIFO is empty"] -pub type ITTXFE_R = crate::BitReader; +pub type ITTXFE_R = crate::BitReader; #[doc = "Field `ITTXFE` writer - IN token received when TxFIFO is empty"] -pub type ITTXFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type ITTXFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INEPNE` reader - IN endpoint NAK effective"] -pub type INEPNE_R = crate::BitReader; +pub type INEPNE_R = crate::BitReader; #[doc = "Field `INEPNE` writer - IN endpoint NAK effective"] -pub type INEPNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type INEPNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFE` reader - Transmit FIFO empty"] -pub type TXFE_R = crate::BitReader; +pub type TXFE_R = crate::BitReader; #[doc = "Field `TXFIFOUDRN` reader - Transmit Fifo Underrun"] -pub type TXFIFOUDRN_R = crate::BitReader; +pub type TXFIFOUDRN_R = crate::BitReader; #[doc = "Field `TXFIFOUDRN` writer - Transmit Fifo Underrun"] -pub type TXFIFOUDRN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type TXFIFOUDRN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BNA` reader - Buffer not available interrupt"] -pub type BNA_R = crate::BitReader; +pub type BNA_R = crate::BitReader; #[doc = "Field `BNA` writer - Buffer not available interrupt"] -pub type BNA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type BNA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PKTDRPSTS` reader - Packet dropped status"] -pub type PKTDRPSTS_R = crate::BitReader; +pub type PKTDRPSTS_R = crate::BitReader; #[doc = "Field `PKTDRPSTS` writer - Packet dropped status"] -pub type PKTDRPSTS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type PKTDRPSTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BERR` reader - Babble error interrupt"] -pub type BERR_R = crate::BitReader; +pub type BERR_R = crate::BitReader; #[doc = "Field `BERR` writer - Babble error interrupt"] -pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type BERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAK` reader - NAK interrupt"] -pub type NAK_R = crate::BitReader; +pub type NAK_R = crate::BitReader; #[doc = "Field `NAK` writer - NAK interrupt"] -pub type NAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEPINT_SPEC, bool, O>; +pub type NAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt"] #[inline(always)] @@ -133,86 +101,109 @@ impl R { NAK_R::new(((self.bits >> 13) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPINT") + .field("xfrc", &format_args!("{}", self.xfrc().bit())) + .field("epdisd", &format_args!("{}", self.epdisd().bit())) + .field("toc", &format_args!("{}", self.toc().bit())) + .field("ittxfe", &format_args!("{}", self.ittxfe().bit())) + .field("inepne", &format_args!("{}", self.inepne().bit())) + .field("txfe", &format_args!("{}", self.txfe().bit())) + .field("txfifoudrn", &format_args!("{}", self.txfifoudrn().bit())) + .field("bna", &format_args!("{}", self.bna().bit())) + .field("pktdrpsts", &format_args!("{}", self.pktdrpsts().bit())) + .field("berr", &format_args!("{}", self.berr().bit())) + .field("nak", &format_args!("{}", self.nak().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt"] #[inline(always)] #[must_use] - pub fn xfrc(&mut self) -> XFRC_W<0> { + pub fn xfrc(&mut self) -> XFRC_W { XFRC_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt"] #[inline(always)] #[must_use] - pub fn epdisd(&mut self) -> EPDISD_W<1> { + pub fn epdisd(&mut self) -> EPDISD_W { EPDISD_W::new(self) } #[doc = "Bit 3 - Timeout condition"] #[inline(always)] #[must_use] - pub fn toc(&mut self) -> TOC_W<3> { + pub fn toc(&mut self) -> TOC_W { TOC_W::new(self) } #[doc = "Bit 4 - IN token received when TxFIFO is empty"] #[inline(always)] #[must_use] - pub fn ittxfe(&mut self) -> ITTXFE_W<4> { + pub fn ittxfe(&mut self) -> ITTXFE_W { ITTXFE_W::new(self) } #[doc = "Bit 6 - IN endpoint NAK effective"] #[inline(always)] #[must_use] - pub fn inepne(&mut self) -> INEPNE_W<6> { + pub fn inepne(&mut self) -> INEPNE_W { INEPNE_W::new(self) } #[doc = "Bit 8 - Transmit Fifo Underrun"] #[inline(always)] #[must_use] - pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<8> { + pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W { TXFIFOUDRN_W::new(self) } #[doc = "Bit 9 - Buffer not available interrupt"] #[inline(always)] #[must_use] - pub fn bna(&mut self) -> BNA_W<9> { + pub fn bna(&mut self) -> BNA_W { BNA_W::new(self) } #[doc = "Bit 11 - Packet dropped status"] #[inline(always)] #[must_use] - pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<11> { + pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W { PKTDRPSTS_W::new(self) } #[doc = "Bit 12 - Babble error interrupt"] #[inline(always)] #[must_use] - pub fn berr(&mut self) -> BERR_W<12> { + pub fn berr(&mut self) -> BERR_W { BERR_W::new(self) } #[doc = "Bit 13 - NAK interrupt"] #[inline(always)] #[must_use] - pub fn nak(&mut self) -> NAK_W<13> { + pub fn nak(&mut self) -> NAK_W { NAK_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepint](index.html) module"] +#[doc = "Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diepint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPINT_SPEC; impl crate::RegisterSpec for DIEPINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diepint::R](R) reader structure"] -impl crate::Readable for DIEPINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diepint::W](W) writer structure"] +#[doc = "`read()` method returns [`diepint::R`](R) reader structure"] +impl crate::Readable for DIEPINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diepint::W`](W) writer structure"] impl crate::Writable for DIEPINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs index 7f94dcb..72226f2 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dieptsiz.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRSIZ` reader - Transfer size"] -pub type XFRSIZ_R = crate::FieldReader; +pub type XFRSIZ_R = crate::FieldReader; #[doc = "Field `XFRSIZ` writer - Transfer size"] -pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTSIZ_SPEC, u8, u8, 7, O>; +pub type XFRSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `PKTCNT` reader - Packet count"] -pub type PKTCNT_R = crate::FieldReader; +pub type PKTCNT_R = crate::FieldReader; #[doc = "Field `PKTCNT` writer - Packet count"] -pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTSIZ_SPEC, u8, u8, 2, O>; +pub type PKTCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:6 - Transfer size"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { PKTCNT_R::new(((self.bits >> 19) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTSIZ") + .field("xfrsiz", &format_args!("{}", self.xfrsiz().bits())) + .field("pktcnt", &format_args!("{}", self.pktcnt().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - Transfer size"] #[inline(always)] #[must_use] - pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + pub fn xfrsiz(&mut self) -> XFRSIZ_W { XFRSIZ_W::new(self) } #[doc = "Bits 19:20 - Packet count"] #[inline(always)] #[must_use] - pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + pub fn pktcnt(&mut self) -> PKTCNT_W { PKTCNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptsiz](index.html) module"] +#[doc = "Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTSIZ_SPEC; impl crate::RegisterSpec for DIEPTSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptsiz::R](R) reader structure"] -impl crate::Readable for DIEPTSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptsiz::R`](R) reader structure"] +impl crate::Readable for DIEPTSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptsiz::W`](W) writer structure"] impl crate::Writable for DIEPTSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs index c962826..abe4eef 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/in_endpoint/dtxfsts.rs @@ -1,20 +1,7 @@ #[doc = "Register `DTXFSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `INEPTFSAV` reader - IN endpoint TxFIFO space avail"] -pub type INEPTFSAV_R = crate::FieldReader; +pub type INEPTFSAV_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - IN endpoint TxFIFO space avail"] #[inline(always)] @@ -22,15 +9,25 @@ impl R { INEPTFSAV_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Transmit FIFO status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dtxfsts](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DTXFSTS") + .field("ineptfsav", &format_args!("{}", self.ineptfsav().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Transmit FIFO status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtxfsts::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DTXFSTS_SPEC; impl crate::RegisterSpec for DTXFSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dtxfsts::R](R) reader structure"] -impl crate::Readable for DTXFSTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`dtxfsts::R`](R) reader structure"] +impl crate::Readable for DTXFSTS_SPEC {} #[doc = "`reset()` method sets DTXFSTS to value 0"] impl crate::Resettable for DTXFSTS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint.rs b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint.rs index a3a9e56..360b7f9 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct OUT_ENDPOINT { #[doc = "0x00 - Control"] pub doepctl: DOEPCTL, @@ -12,19 +13,23 @@ pub struct OUT_ENDPOINT { #[doc = "0x14 - DMA address"] pub doepdma: DOEPDMA, } -#[doc = "DOEPCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPCTL (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepctl`] +module"] pub type DOEPCTL = crate::Reg; #[doc = "Control"] pub mod doepctl; -#[doc = "DOEPINT (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPINT (rw) register accessor: Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepint`] +module"] pub type DOEPINT = crate::Reg; #[doc = "Interrupt"] pub mod doepint; -#[doc = "DOEPTSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPTSIZ (rw) register accessor: Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doeptsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doeptsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doeptsiz`] +module"] pub type DOEPTSIZ = crate::Reg; #[doc = "Transfer size"] pub mod doeptsiz; -#[doc = "DOEPDMA (rw) register accessor: an alias for `Reg`"] +#[doc = "DOEPDMA (rw) register accessor: DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepdma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepdma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doepdma`] +module"] pub type DOEPDMA = crate::Reg; #[doc = "DMA address"] pub mod doepdma; diff --git a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepctl.rs b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepctl.rs index 2f6baf5..47f7dd2 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepctl.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepctl.rs @@ -1,63 +1,31 @@ #[doc = "Register `DOEPCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MPSIZ` reader - Maximum packet size"] -pub type MPSIZ_R = crate::FieldReader; +pub type MPSIZ_R = crate::FieldReader; #[doc = "Field `USBAEP` reader - USB active endpoint"] -pub type USBAEP_R = crate::BitReader; +pub type USBAEP_R = crate::BitReader; #[doc = "Field `NAKSTS` reader - NAK status"] -pub type NAKSTS_R = crate::BitReader; +pub type NAKSTS_R = crate::BitReader; #[doc = "Field `EPTYP` reader - Endpoint type"] -pub type EPTYP_R = crate::FieldReader; +pub type EPTYP_R = crate::FieldReader; #[doc = "Field `SNPM` reader - Snoop mode"] -pub type SNPM_R = crate::BitReader; +pub type SNPM_R = crate::BitReader; #[doc = "Field `SNPM` writer - Snoop mode"] -pub type SNPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type SNPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `Stall` reader - STALL handshake"] -pub type STALL_R = crate::BitReader; +pub type STALL_R = crate::BitReader; #[doc = "Field `Stall` writer - STALL handshake"] -pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CNAK` writer - Clear NAK"] -pub type CNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type CNAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SNAK` writer - Set NAK"] -pub type SNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type SNAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDIS` reader - Endpoint disable"] -pub type EPDIS_R = crate::BitReader; +pub type EPDIS_R = crate::BitReader; #[doc = "Field `EPENA` writer - Endpoint enable"] -pub type EPENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPCTL_SPEC, bool, O>; +pub type EPENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:1 - Maximum packet size"] #[inline(always)] @@ -95,56 +63,75 @@ impl R { EPDIS_R::new(((self.bits >> 30) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPCTL") + .field("mpsiz", &format_args!("{}", self.mpsiz().bits())) + .field("usbaep", &format_args!("{}", self.usbaep().bit())) + .field("naksts", &format_args!("{}", self.naksts().bit())) + .field("eptyp", &format_args!("{}", self.eptyp().bits())) + .field("snpm", &format_args!("{}", self.snpm().bit())) + .field("stall", &format_args!("{}", self.stall().bit())) + .field("epdis", &format_args!("{}", self.epdis().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 20 - Snoop mode"] #[inline(always)] #[must_use] - pub fn snpm(&mut self) -> SNPM_W<20> { + pub fn snpm(&mut self) -> SNPM_W { SNPM_W::new(self) } #[doc = "Bit 21 - STALL handshake"] #[inline(always)] #[must_use] - pub fn stall(&mut self) -> STALL_W<21> { + pub fn stall(&mut self) -> STALL_W { STALL_W::new(self) } #[doc = "Bit 26 - Clear NAK"] #[inline(always)] #[must_use] - pub fn cnak(&mut self) -> CNAK_W<26> { + pub fn cnak(&mut self) -> CNAK_W { CNAK_W::new(self) } #[doc = "Bit 27 - Set NAK"] #[inline(always)] #[must_use] - pub fn snak(&mut self) -> SNAK_W<27> { + pub fn snak(&mut self) -> SNAK_W { SNAK_W::new(self) } #[doc = "Bit 31 - Endpoint enable"] #[inline(always)] #[must_use] - pub fn epena(&mut self) -> EPENA_W<31> { + pub fn epena(&mut self) -> EPENA_W { EPENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepctl](index.html) module"] +#[doc = "Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPCTL_SPEC; impl crate::RegisterSpec for DOEPCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepctl::R](R) reader structure"] -impl crate::Readable for DOEPCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepctl::W](W) writer structure"] +#[doc = "`read()` method returns [`doepctl::R`](R) reader structure"] +impl crate::Readable for DOEPCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepctl::W`](W) writer structure"] impl crate::Writable for DOEPCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepdma.rs b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepdma.rs index 92089f0..ab7d95d 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepdma.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepdma.rs @@ -1,43 +1,11 @@ #[doc = "Register `DOEPDMA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPDMA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMAADDR` reader - DMA address"] -pub type DMAADDR_R = crate::FieldReader; +pub type DMAADDR_R = crate::FieldReader; #[doc = "Field `DMAADDR` writer - DMA address"] -pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPDMA_SPEC, u32, u32, 32, O>; +pub type DMAADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DMAADDR_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPDMA") + .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] #[must_use] - pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + pub fn dmaaddr(&mut self) -> DMAADDR_W { DMAADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepdma](index.html) module"] +#[doc = "DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepdma::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepdma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPDMA_SPEC; impl crate::RegisterSpec for DOEPDMA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepdma::R](R) reader structure"] -impl crate::Readable for DOEPDMA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepdma::W](W) writer structure"] +#[doc = "`read()` method returns [`doepdma::R`](R) reader structure"] +impl crate::Readable for DOEPDMA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepdma::W`](W) writer structure"] impl crate::Writable for DOEPDMA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepint.rs b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepint.rs index 365d667..0552c9b 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepint.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doepint.rs @@ -1,63 +1,31 @@ #[doc = "Register `DOEPINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRC` reader - Transfer completed interrupt"] -pub type XFRC_R = crate::BitReader; +pub type XFRC_R = crate::BitReader; #[doc = "Field `XFRC` writer - Transfer completed interrupt"] -pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type XFRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISD` reader - Endpoint disabled interrupt"] -pub type EPDISD_R = crate::BitReader; +pub type EPDISD_R = crate::BitReader; #[doc = "Field `EPDISD` writer - Endpoint disabled interrupt"] -pub type EPDISD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type EPDISD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STUP` reader - SETUP phase done"] -pub type STUP_R = crate::BitReader; +pub type STUP_R = crate::BitReader; #[doc = "Field `STUP` writer - SETUP phase done"] -pub type STUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type STUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OTEPDIS` reader - OUT token received when endpoint disabled"] -pub type OTEPDIS_R = crate::BitReader; +pub type OTEPDIS_R = crate::BitReader; #[doc = "Field `OTEPDIS` writer - OUT token received when endpoint disabled"] -pub type OTEPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type OTEPDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `B2BSTUP` reader - Back-to-back SETUP packets received"] -pub type B2BSTUP_R = crate::BitReader; +pub type B2BSTUP_R = crate::BitReader; #[doc = "Field `B2BSTUP` writer - Back-to-back SETUP packets received"] -pub type B2BSTUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type B2BSTUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYET` reader - NYET interrupt"] -pub type NYET_R = crate::BitReader; +pub type NYET_R = crate::BitReader; #[doc = "Field `NYET` writer - NYET interrupt"] -pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPINT_SPEC, bool, O>; +pub type NYET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed interrupt"] #[inline(always)] @@ -90,62 +58,80 @@ impl R { NYET_R::new(((self.bits >> 14) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPINT") + .field("xfrc", &format_args!("{}", self.xfrc().bit())) + .field("epdisd", &format_args!("{}", self.epdisd().bit())) + .field("stup", &format_args!("{}", self.stup().bit())) + .field("otepdis", &format_args!("{}", self.otepdis().bit())) + .field("b2bstup", &format_args!("{}", self.b2bstup().bit())) + .field("nyet", &format_args!("{}", self.nyet().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed interrupt"] #[inline(always)] #[must_use] - pub fn xfrc(&mut self) -> XFRC_W<0> { + pub fn xfrc(&mut self) -> XFRC_W { XFRC_W::new(self) } #[doc = "Bit 1 - Endpoint disabled interrupt"] #[inline(always)] #[must_use] - pub fn epdisd(&mut self) -> EPDISD_W<1> { + pub fn epdisd(&mut self) -> EPDISD_W { EPDISD_W::new(self) } #[doc = "Bit 3 - SETUP phase done"] #[inline(always)] #[must_use] - pub fn stup(&mut self) -> STUP_W<3> { + pub fn stup(&mut self) -> STUP_W { STUP_W::new(self) } #[doc = "Bit 4 - OUT token received when endpoint disabled"] #[inline(always)] #[must_use] - pub fn otepdis(&mut self) -> OTEPDIS_W<4> { + pub fn otepdis(&mut self) -> OTEPDIS_W { OTEPDIS_W::new(self) } #[doc = "Bit 6 - Back-to-back SETUP packets received"] #[inline(always)] #[must_use] - pub fn b2bstup(&mut self) -> B2BSTUP_W<6> { + pub fn b2bstup(&mut self) -> B2BSTUP_W { B2BSTUP_W::new(self) } #[doc = "Bit 14 - NYET interrupt"] #[inline(always)] #[must_use] - pub fn nyet(&mut self) -> NYET_W<14> { + pub fn nyet(&mut self) -> NYET_W { NYET_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepint](index.html) module"] +#[doc = "Interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doepint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doepint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPINT_SPEC; impl crate::RegisterSpec for DOEPINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doepint::R](R) reader structure"] -impl crate::Readable for DOEPINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doepint::W](W) writer structure"] +#[doc = "`read()` method returns [`doepint::R`](R) reader structure"] +impl crate::Readable for DOEPINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doepint::W`](W) writer structure"] impl crate::Writable for DOEPINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs index 0f78e4d..4606c37 100644 --- a/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs +++ b/crates/bcm2837-lpa/src/usb_otg_device/out_endpoint/doeptsiz.rs @@ -1,51 +1,19 @@ #[doc = "Register `DOEPTSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DOEPTSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRSIZ` reader - Transfer size"] -pub type XFRSIZ_R = crate::FieldReader; +pub type XFRSIZ_R = crate::FieldReader; #[doc = "Field `XFRSIZ` writer - Transfer size"] -pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPTSIZ_SPEC, u8, u8, 7, O>; +pub type XFRSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `PKTCNT` reader - Packet count"] -pub type PKTCNT_R = crate::BitReader; +pub type PKTCNT_R = crate::BitReader; #[doc = "Field `PKTCNT` writer - Packet count"] -pub type PKTCNT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DOEPTSIZ_SPEC, bool, O>; +pub type PKTCNT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STUPCNT` reader - SETUP packet count"] -pub type STUPCNT_R = crate::FieldReader; +pub type STUPCNT_R = crate::FieldReader; #[doc = "Field `STUPCNT` writer - SETUP packet count"] -pub type STUPCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DOEPTSIZ_SPEC, u8, u8, 2, O>; +pub type STUPCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:6 - Transfer size"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { STUPCNT_R::new(((self.bits >> 29) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DOEPTSIZ") + .field("xfrsiz", &format_args!("{}", self.xfrsiz().bits())) + .field("pktcnt", &format_args!("{}", self.pktcnt().bit())) + .field("stupcnt", &format_args!("{}", self.stupcnt().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - Transfer size"] #[inline(always)] #[must_use] - pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + pub fn xfrsiz(&mut self) -> XFRSIZ_W { XFRSIZ_W::new(self) } #[doc = "Bit 19 - Packet count"] #[inline(always)] #[must_use] - pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + pub fn pktcnt(&mut self) -> PKTCNT_W { PKTCNT_W::new(self) } #[doc = "Bits 29:30 - SETUP packet count"] #[inline(always)] #[must_use] - pub fn stupcnt(&mut self) -> STUPCNT_W<29> { + pub fn stupcnt(&mut self) -> STUPCNT_W { STUPCNT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doeptsiz](index.html) module"] +#[doc = "Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doeptsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doeptsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DOEPTSIZ_SPEC; impl crate::RegisterSpec for DOEPTSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [doeptsiz::R](R) reader structure"] -impl crate::Readable for DOEPTSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [doeptsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`doeptsiz::R`](R) reader structure"] +impl crate::Readable for DOEPTSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doeptsiz::W`](W) writer structure"] impl crate::Writable for DOEPTSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global.rs b/crates/bcm2837-lpa/src/usb_otg_global.rs index a6b35cb..d8a5a57 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - OTG_HS control and status register"] pub gotgctl: GOTGCTL, @@ -84,115 +85,143 @@ impl RegisterBlock { unsafe { &*(self as *const Self).cast::().add(40usize).cast() } } } -#[doc = "GOTGCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "GOTGCTL (rw) register accessor: OTG_HS control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gotgctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gotgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gotgctl`] +module"] pub type GOTGCTL = crate::Reg; #[doc = "OTG_HS control and status register"] pub mod gotgctl; -#[doc = "GOTGINT (rw) register accessor: an alias for `Reg`"] +#[doc = "GOTGINT (rw) register accessor: OTG_HS interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gotgint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gotgint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gotgint`] +module"] pub type GOTGINT = crate::Reg; #[doc = "OTG_HS interrupt register"] pub mod gotgint; -#[doc = "GAHBCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "GAHBCFG (rw) register accessor: OTG_HS AHB configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gahbcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gahbcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gahbcfg`] +module"] pub type GAHBCFG = crate::Reg; #[doc = "OTG_HS AHB configuration register"] pub mod gahbcfg; -#[doc = "GUSBCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "GUSBCFG (rw) register accessor: OTG_HS USB configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gusbcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gusbcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gusbcfg`] +module"] pub type GUSBCFG = crate::Reg; #[doc = "OTG_HS USB configuration register"] pub mod gusbcfg; -#[doc = "GRSTCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "GRSTCTL (rw) register accessor: OTG_HS reset register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grstctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grstctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grstctl`] +module"] pub type GRSTCTL = crate::Reg; #[doc = "OTG_HS reset register"] pub mod grstctl; -#[doc = "GINTSTS (rw) register accessor: an alias for `Reg`"] +#[doc = "GINTSTS (rw) register accessor: OTG_HS core interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gintsts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gintsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gintsts`] +module"] pub type GINTSTS = crate::Reg; #[doc = "OTG_HS core interrupt register"] pub mod gintsts; -#[doc = "GINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "GINTMSK (rw) register accessor: OTG_HS interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gintmsk`] +module"] pub type GINTMSK = crate::Reg; #[doc = "OTG_HS interrupt mask register"] pub mod gintmsk; -#[doc = "GRXSTSR_Host (r) register accessor: an alias for `Reg`"] +#[doc = "GRXSTSR_Host (r) register accessor: OTG_HS Receive status debug read register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr_host::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsr_host`] +module"] pub type GRXSTSR_HOST = crate::Reg; #[doc = "OTG_HS Receive status debug read register (host mode)"] pub mod grxstsr_host; -#[doc = "GRXSTSP_Host (r) register accessor: an alias for `Reg`"] +#[doc = "GRXSTSP_Host (r) register accessor: OTG_HS status read and pop register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp_host::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsp_host`] +module"] pub type GRXSTSP_HOST = crate::Reg; #[doc = "OTG_HS status read and pop register (host mode)"] pub mod grxstsp_host; -#[doc = "GRXFSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "GRXFSIZ (rw) register accessor: OTG_HS Receive FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxfsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grxfsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxfsiz`] +module"] pub type GRXFSIZ = crate::Reg; #[doc = "OTG_HS Receive FIFO size register"] pub mod grxfsiz; -#[doc = "GNPTXFSIZ_Host (rw) register accessor: an alias for `Reg`"] +#[doc = "GNPTXFSIZ_Host (rw) register accessor: OTG_HS nonperiodic transmit FIFO size register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxfsiz_host::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gnptxfsiz_host::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gnptxfsiz_host`] +module"] pub type GNPTXFSIZ_HOST = crate::Reg; #[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)"] pub mod gnptxfsiz_host; -#[doc = "TX0FSIZ_Peripheral (rw) register accessor: an alias for `Reg`"] +#[doc = "TX0FSIZ_Peripheral (rw) register accessor: Endpoint 0 transmit FIFO size (peripheral mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx0fsiz_peripheral::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx0fsiz_peripheral::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx0fsiz_peripheral`] +module"] pub type TX0FSIZ_PERIPHERAL = crate::Reg; #[doc = "Endpoint 0 transmit FIFO size (peripheral mode)"] pub mod tx0fsiz_peripheral; -#[doc = "GNPTXSTS (r) register accessor: an alias for `Reg`"] +#[doc = "GNPTXSTS (r) register accessor: OTG_HS nonperiodic transmit FIFO/queue status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxsts::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gnptxsts`] +module"] pub type GNPTXSTS = crate::Reg; #[doc = "OTG_HS nonperiodic transmit FIFO/queue status register"] pub mod gnptxsts; -#[doc = "GCCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "GCCFG (rw) register accessor: OTG_HS general core configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gccfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gccfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gccfg`] +module"] pub type GCCFG = crate::Reg; #[doc = "OTG_HS general core configuration register"] pub mod gccfg; -#[doc = "CID (rw) register accessor: an alias for `Reg`"] +#[doc = "CID (rw) register accessor: OTG_HS core ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cid::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cid::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cid`] +module"] pub type CID = crate::Reg; #[doc = "OTG_HS core ID register"] pub mod cid; -#[doc = "VID (r) register accessor: an alias for `Reg`"] +#[doc = "VID (r) register accessor: OTG_HS vendor ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid`] +module"] pub type VID = crate::Reg; #[doc = "OTG_HS vendor ID register"] pub mod vid; -#[doc = "HW_DIRECTION (r) register accessor: an alias for `Reg`"] +#[doc = "HW_DIRECTION (r) register accessor: Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_direction::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_direction`] +module"] pub type HW_DIRECTION = crate::Reg; #[doc = "Direction"] pub mod hw_direction; -#[doc = "HW_CONFIG0 (r) register accessor: an alias for `Reg`"] +#[doc = "HW_CONFIG0 (r) register accessor: Hardware Config 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_config0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_config0`] +module"] pub type HW_CONFIG0 = crate::Reg; #[doc = "Hardware Config 0"] pub mod hw_config0; -#[doc = "HPTXFSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "HPTXFSIZ (rw) register accessor: OTG_HS Host periodic transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxfsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hptxfsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hptxfsiz`] +module"] pub type HPTXFSIZ = crate::Reg; #[doc = "OTG_HS Host periodic transmit FIFO size register"] pub mod hptxfsiz; -#[doc = "DIEPTXF1 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF1 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf1`] +module"] pub type DIEPTXF1 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf1; -#[doc = "DIEPTXF2 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF2 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf2`] +module"] pub type DIEPTXF2 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf2; -#[doc = "DIEPTXF3 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF3 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf3`] +module"] pub type DIEPTXF3 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf3; -#[doc = "DIEPTXF4 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF4 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf4`] +module"] pub type DIEPTXF4 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf4; -#[doc = "DIEPTXF5 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF5 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf5`] +module"] pub type DIEPTXF5 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf5; -#[doc = "DIEPTXF6 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF6 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf6`] +module"] pub type DIEPTXF6 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf6; -#[doc = "DIEPTXF7 (rw) register accessor: an alias for `Reg`"] +#[doc = "DIEPTXF7 (rw) register accessor: OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dieptxf7`] +module"] pub type DIEPTXF7 = crate::Reg; #[doc = "OTG_HS device IN endpoint transmit FIFO size register"] pub mod dieptxf7; -#[doc = "GRXSTSR_Peripheral (r) register accessor: an alias for `Reg`"] +#[doc = "GRXSTSR_Peripheral (r) register accessor: OTG_HS Receive status debug read register (peripheral mode mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr_peripheral::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsr_peripheral`] +module"] pub type GRXSTSR_PERIPHERAL = crate::Reg; #[doc = "OTG_HS Receive status debug read register (peripheral mode mode)"] pub mod grxstsr_peripheral; -#[doc = "GRXSTSP_Peripheral (r) register accessor: an alias for `Reg`"] +#[doc = "GRXSTSP_Peripheral (r) register accessor: OTG_HS status read and pop register (peripheral mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp_peripheral::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@grxstsp_peripheral`] +module"] pub type GRXSTSP_PERIPHERAL = crate::Reg; #[doc = "OTG_HS status read and pop register (peripheral mode)"] pub mod grxstsp_peripheral; diff --git a/crates/bcm2837-lpa/src/usb_otg_global/cid.rs b/crates/bcm2837-lpa/src/usb_otg_global/cid.rs index 5a8ef55..c840ab9 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/cid.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/cid.rs @@ -1,43 +1,11 @@ #[doc = "Register `CID` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CID` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PRODUCT_ID` reader - Product ID field"] -pub type PRODUCT_ID_R = crate::FieldReader; +pub type PRODUCT_ID_R = crate::FieldReader; #[doc = "Field `PRODUCT_ID` writer - Product ID field"] -pub type PRODUCT_ID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CID_SPEC, u32, u32, 32, O>; +pub type PRODUCT_ID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Product ID field"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { PRODUCT_ID_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CID") + .field("product_id", &format_args!("{}", self.product_id().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - Product ID field"] #[inline(always)] #[must_use] - pub fn product_id(&mut self) -> PRODUCT_ID_W<0> { + pub fn product_id(&mut self) -> PRODUCT_ID_W { PRODUCT_ID_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS core ID register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid](index.html) module"] +#[doc = "OTG_HS core ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cid::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cid::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CID_SPEC; impl crate::RegisterSpec for CID_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cid::R](R) reader structure"] -impl crate::Readable for CID_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cid::W](W) writer structure"] +#[doc = "`read()` method returns [`cid::R`](R) reader structure"] +impl crate::Readable for CID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cid::W`](W) writer structure"] impl crate::Writable for CID_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf1.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf1.rs index b79803c..52be8d1 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf1.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf1.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF1_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF1_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF1") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf1](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF1_SPEC; impl crate::RegisterSpec for DIEPTXF1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf1::R](R) reader structure"] -impl crate::Readable for DIEPTXF1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf1::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf1::R`](R) reader structure"] +impl crate::Readable for DIEPTXF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf1::W`](W) writer structure"] impl crate::Writable for DIEPTXF1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf2.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf2.rs index cdf9d1b..ce63253 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf2.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf2.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF2_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF2_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF2") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf2](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF2_SPEC; impl crate::RegisterSpec for DIEPTXF2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf2::R](R) reader structure"] -impl crate::Readable for DIEPTXF2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf2::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf2::R`](R) reader structure"] +impl crate::Readable for DIEPTXF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf2::W`](W) writer structure"] impl crate::Writable for DIEPTXF2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf3.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf3.rs index 8eaba75..18a518c 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf3.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf3.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF3_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF3_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF3") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf3](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF3_SPEC; impl crate::RegisterSpec for DIEPTXF3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf3::R](R) reader structure"] -impl crate::Readable for DIEPTXF3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf3::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf3::R`](R) reader structure"] +impl crate::Readable for DIEPTXF3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf3::W`](W) writer structure"] impl crate::Writable for DIEPTXF3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf4.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf4.rs index 6b30646..9b23f1d 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf4.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf4.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF4_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF4_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF4") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf4](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF4_SPEC; impl crate::RegisterSpec for DIEPTXF4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf4::R](R) reader structure"] -impl crate::Readable for DIEPTXF4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf4::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf4::R`](R) reader structure"] +impl crate::Readable for DIEPTXF4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf4::W`](W) writer structure"] impl crate::Writable for DIEPTXF4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf5.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf5.rs index e2b7d98..03b144c 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf5.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf5.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF5` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF5_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF5_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF5") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf5](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF5_SPEC; impl crate::RegisterSpec for DIEPTXF5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf5::R](R) reader structure"] -impl crate::Readable for DIEPTXF5_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf5::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf5::R`](R) reader structure"] +impl crate::Readable for DIEPTXF5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf5::W`](W) writer structure"] impl crate::Writable for DIEPTXF5_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf6.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf6.rs index da38751..57dcb25 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf6.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf6.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF6` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF6_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF6_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF6") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf6](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF6_SPEC; impl crate::RegisterSpec for DIEPTXF6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf6::R](R) reader structure"] -impl crate::Readable for DIEPTXF6_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf6::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf6::R`](R) reader structure"] +impl crate::Readable for DIEPTXF6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf6::W`](W) writer structure"] impl crate::Writable for DIEPTXF6_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf7.rs b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf7.rs index 811d528..7a99ea4 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/dieptxf7.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/dieptxf7.rs @@ -1,47 +1,15 @@ #[doc = "Register `DIEPTXF7` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIEPTXF7` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INEPTXSA` reader - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_R = crate::FieldReader; +pub type INEPTXSA_R = crate::FieldReader; #[doc = "Field `INEPTXSA` writer - IN endpoint FIFOx transmit RAM start address"] -pub type INEPTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF7_SPEC, u16, u16, 16, O>; +pub type INEPTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `INEPTXFD` reader - IN endpoint TxFIFO depth"] -pub type INEPTXFD_R = crate::FieldReader; +pub type INEPTXFD_R = crate::FieldReader; #[doc = "Field `INEPTXFD` writer - IN endpoint TxFIFO depth"] -pub type INEPTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEPTXF7_SPEC, u16, u16, 16, O>; +pub type INEPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { INEPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DIEPTXF7") + .field("ineptxsa", &format_args!("{}", self.ineptxsa().bits())) + .field("ineptxfd", &format_args!("{}", self.ineptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - IN endpoint FIFOx transmit RAM start address"] #[inline(always)] #[must_use] - pub fn ineptxsa(&mut self) -> INEPTXSA_W<0> { + pub fn ineptxsa(&mut self) -> INEPTXSA_W { INEPTXSA_W::new(self) } #[doc = "Bits 16:31 - IN endpoint TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ineptxfd(&mut self) -> INEPTXFD_W<16> { + pub fn ineptxfd(&mut self) -> INEPTXFD_W { INEPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf7](index.html) module"] +#[doc = "OTG_HS device IN endpoint transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dieptxf7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dieptxf7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIEPTXF7_SPEC; impl crate::RegisterSpec for DIEPTXF7_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dieptxf7::R](R) reader structure"] -impl crate::Readable for DIEPTXF7_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dieptxf7::W](W) writer structure"] +#[doc = "`read()` method returns [`dieptxf7::R`](R) reader structure"] +impl crate::Readable for DIEPTXF7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dieptxf7::W`](W) writer structure"] impl crate::Writable for DIEPTXF7_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gahbcfg.rs b/crates/bcm2837-lpa/src/usb_otg_global/gahbcfg.rs index 987d389..a135db6 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/gahbcfg.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/gahbcfg.rs @@ -1,45 +1,13 @@ #[doc = "Register `GAHBCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GAHBCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GINT` reader - Global interrupt mask"] -pub type GINT_R = crate::BitReader; +pub type GINT_R = crate::BitReader; #[doc = "Field `GINT` writer - Global interrupt mask"] -pub type GINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type GINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AXI_BURST` reader - Maximum AXI burst length"] -pub type AXI_BURST_R = crate::FieldReader; +pub type AXI_BURST_R = crate::FieldReader; #[doc = "Maximum AXI burst length\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -59,10 +27,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for BURST_A { + type Ux = u8; +} impl AXI_BURST_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> BURST_A { + pub const fn variant(&self) -> BURST_A { match self.bits { 0 => BURST_A::_4, 1 => BURST_A::_3, @@ -71,68 +42,71 @@ impl AXI_BURST_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_4`"] + #[doc = "`0`"] #[inline(always)] pub fn is_4(&self) -> bool { *self == BURST_A::_4 } - #[doc = "Checks if the value of the field is `_3`"] + #[doc = "`1`"] #[inline(always)] pub fn is_3(&self) -> bool { *self == BURST_A::_3 } - #[doc = "Checks if the value of the field is `_2`"] + #[doc = "`10`"] #[inline(always)] pub fn is_2(&self) -> bool { *self == BURST_A::_2 } - #[doc = "Checks if the value of the field is `_1`"] + #[doc = "`11`"] #[inline(always)] pub fn is_1(&self) -> bool { *self == BURST_A::_1 } } #[doc = "Field `AXI_BURST` writer - Maximum AXI burst length"] -pub type AXI_BURST_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, u32, GAHBCFG_SPEC, u8, BURST_A, 2, O>; -impl<'a, const O: u8> AXI_BURST_W<'a, O> { +pub type AXI_BURST_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, BURST_A>; +impl<'a, REG, const O: u8> AXI_BURST_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "`0`"] #[inline(always)] - pub fn _4(self) -> &'a mut W { + pub fn _4(self) -> &'a mut crate::W { self.variant(BURST_A::_4) } #[doc = "`1`"] #[inline(always)] - pub fn _3(self) -> &'a mut W { + pub fn _3(self) -> &'a mut crate::W { self.variant(BURST_A::_3) } #[doc = "`10`"] #[inline(always)] - pub fn _2(self) -> &'a mut W { + pub fn _2(self) -> &'a mut crate::W { self.variant(BURST_A::_2) } #[doc = "`11`"] #[inline(always)] - pub fn _1(self) -> &'a mut W { + pub fn _1(self) -> &'a mut crate::W { self.variant(BURST_A::_1) } } #[doc = "Field `AXI_WAIT` reader - Wait for all AXI writes before signaling DMA"] -pub type AXI_WAIT_R = crate::BitReader; +pub type AXI_WAIT_R = crate::BitReader; #[doc = "Field `AXI_WAIT` writer - Wait for all AXI writes before signaling DMA"] -pub type AXI_WAIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type AXI_WAIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMAEN` reader - DMA enable"] -pub type DMAEN_R = crate::BitReader; +pub type DMAEN_R = crate::BitReader; #[doc = "Field `DMAEN` writer - DMA enable"] -pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type DMAEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFELVL` reader - TxFIFO empty level"] -pub type TXFELVL_R = crate::BitReader; +pub type TXFELVL_R = crate::BitReader; #[doc = "Field `TXFELVL` writer - TxFIFO empty level"] -pub type TXFELVL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type TXFELVL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTXFELVL` reader - Periodic TxFIFO empty level"] -pub type PTXFELVL_R = crate::BitReader; +pub type PTXFELVL_R = crate::BitReader; #[doc = "Field `PTXFELVL` writer - Periodic TxFIFO empty level"] -pub type PTXFELVL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GAHBCFG_SPEC, bool, O>; +pub type PTXFELVL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Global interrupt mask"] #[inline(always)] @@ -165,62 +139,80 @@ impl R { PTXFELVL_R::new(((self.bits >> 8) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAHBCFG") + .field("gint", &format_args!("{}", self.gint().bit())) + .field("axi_wait", &format_args!("{}", self.axi_wait().bit())) + .field("axi_burst", &format_args!("{}", self.axi_burst().bits())) + .field("dmaen", &format_args!("{}", self.dmaen().bit())) + .field("txfelvl", &format_args!("{}", self.txfelvl().bit())) + .field("ptxfelvl", &format_args!("{}", self.ptxfelvl().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Global interrupt mask"] #[inline(always)] #[must_use] - pub fn gint(&mut self) -> GINT_W<0> { + pub fn gint(&mut self) -> GINT_W { GINT_W::new(self) } #[doc = "Bits 1:2 - Maximum AXI burst length"] #[inline(always)] #[must_use] - pub fn axi_burst(&mut self) -> AXI_BURST_W<1> { + pub fn axi_burst(&mut self) -> AXI_BURST_W { AXI_BURST_W::new(self) } #[doc = "Bit 4 - Wait for all AXI writes before signaling DMA"] #[inline(always)] #[must_use] - pub fn axi_wait(&mut self) -> AXI_WAIT_W<4> { + pub fn axi_wait(&mut self) -> AXI_WAIT_W { AXI_WAIT_W::new(self) } #[doc = "Bit 5 - DMA enable"] #[inline(always)] #[must_use] - pub fn dmaen(&mut self) -> DMAEN_W<5> { + pub fn dmaen(&mut self) -> DMAEN_W { DMAEN_W::new(self) } #[doc = "Bit 7 - TxFIFO empty level"] #[inline(always)] #[must_use] - pub fn txfelvl(&mut self) -> TXFELVL_W<7> { + pub fn txfelvl(&mut self) -> TXFELVL_W { TXFELVL_W::new(self) } #[doc = "Bit 8 - Periodic TxFIFO empty level"] #[inline(always)] #[must_use] - pub fn ptxfelvl(&mut self) -> PTXFELVL_W<8> { + pub fn ptxfelvl(&mut self) -> PTXFELVL_W { PTXFELVL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS AHB configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gahbcfg](index.html) module"] +#[doc = "OTG_HS AHB configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gahbcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gahbcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GAHBCFG_SPEC; impl crate::RegisterSpec for GAHBCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gahbcfg::R](R) reader structure"] -impl crate::Readable for GAHBCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gahbcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`gahbcfg::R`](R) reader structure"] +impl crate::Readable for GAHBCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gahbcfg::W`](W) writer structure"] impl crate::Writable for GAHBCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gccfg.rs b/crates/bcm2837-lpa/src/usb_otg_global/gccfg.rs index 4dbbf5c..6612077 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/gccfg.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/gccfg.rs @@ -1,63 +1,31 @@ #[doc = "Register `GCCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GCCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PWRDWN` reader - Power down"] -pub type PWRDWN_R = crate::BitReader; +pub type PWRDWN_R = crate::BitReader; #[doc = "Field `PWRDWN` writer - Power down"] -pub type PWRDWN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type PWRDWN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2CPADEN` reader - Enable I2C bus connection for the external I2C PHY interface"] -pub type I2CPADEN_R = crate::BitReader; +pub type I2CPADEN_R = crate::BitReader; #[doc = "Field `I2CPADEN` writer - Enable I2C bus connection for the external I2C PHY interface"] -pub type I2CPADEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type I2CPADEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUSASEN` reader - Enable the VBUS sensing device"] -pub type VBUSASEN_R = crate::BitReader; +pub type VBUSASEN_R = crate::BitReader; #[doc = "Field `VBUSASEN` writer - Enable the VBUS sensing device"] -pub type VBUSASEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type VBUSASEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUSBSEN` reader - Enable the VBUS sensing device"] -pub type VBUSBSEN_R = crate::BitReader; +pub type VBUSBSEN_R = crate::BitReader; #[doc = "Field `VBUSBSEN` writer - Enable the VBUS sensing device"] -pub type VBUSBSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type VBUSBSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOFOUTEN` reader - SOF output enable"] -pub type SOFOUTEN_R = crate::BitReader; +pub type SOFOUTEN_R = crate::BitReader; #[doc = "Field `SOFOUTEN` writer - SOF output enable"] -pub type SOFOUTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type SOFOUTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NOVBUSSENS` reader - VBUS sensing disable option"] -pub type NOVBUSSENS_R = crate::BitReader; +pub type NOVBUSSENS_R = crate::BitReader; #[doc = "Field `NOVBUSSENS` writer - VBUS sensing disable option"] -pub type NOVBUSSENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCFG_SPEC, bool, O>; +pub type NOVBUSSENS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 16 - Power down"] #[inline(always)] @@ -90,62 +58,80 @@ impl R { NOVBUSSENS_R::new(((self.bits >> 21) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCCFG") + .field("pwrdwn", &format_args!("{}", self.pwrdwn().bit())) + .field("i2cpaden", &format_args!("{}", self.i2cpaden().bit())) + .field("vbusasen", &format_args!("{}", self.vbusasen().bit())) + .field("vbusbsen", &format_args!("{}", self.vbusbsen().bit())) + .field("sofouten", &format_args!("{}", self.sofouten().bit())) + .field("novbussens", &format_args!("{}", self.novbussens().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 16 - Power down"] #[inline(always)] #[must_use] - pub fn pwrdwn(&mut self) -> PWRDWN_W<16> { + pub fn pwrdwn(&mut self) -> PWRDWN_W { PWRDWN_W::new(self) } #[doc = "Bit 17 - Enable I2C bus connection for the external I2C PHY interface"] #[inline(always)] #[must_use] - pub fn i2cpaden(&mut self) -> I2CPADEN_W<17> { + pub fn i2cpaden(&mut self) -> I2CPADEN_W { I2CPADEN_W::new(self) } #[doc = "Bit 18 - Enable the VBUS sensing device"] #[inline(always)] #[must_use] - pub fn vbusasen(&mut self) -> VBUSASEN_W<18> { + pub fn vbusasen(&mut self) -> VBUSASEN_W { VBUSASEN_W::new(self) } #[doc = "Bit 19 - Enable the VBUS sensing device"] #[inline(always)] #[must_use] - pub fn vbusbsen(&mut self) -> VBUSBSEN_W<19> { + pub fn vbusbsen(&mut self) -> VBUSBSEN_W { VBUSBSEN_W::new(self) } #[doc = "Bit 20 - SOF output enable"] #[inline(always)] #[must_use] - pub fn sofouten(&mut self) -> SOFOUTEN_W<20> { + pub fn sofouten(&mut self) -> SOFOUTEN_W { SOFOUTEN_W::new(self) } #[doc = "Bit 21 - VBUS sensing disable option"] #[inline(always)] #[must_use] - pub fn novbussens(&mut self) -> NOVBUSSENS_W<21> { + pub fn novbussens(&mut self) -> NOVBUSSENS_W { NOVBUSSENS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS general core configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gccfg](index.html) module"] +#[doc = "OTG_HS general core configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gccfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gccfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GCCFG_SPEC; impl crate::RegisterSpec for GCCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gccfg::R](R) reader structure"] -impl crate::Readable for GCCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gccfg::W](W) writer structure"] +#[doc = "`read()` method returns [`gccfg::R`](R) reader structure"] +impl crate::Readable for GCCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gccfg::W`](W) writer structure"] impl crate::Writable for GCCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gintmsk.rs b/crates/bcm2837-lpa/src/usb_otg_global/gintmsk.rs index d3fdb2d..1a856d7 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/gintmsk.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/gintmsk.rs @@ -1,141 +1,109 @@ #[doc = "Register `GINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MMISM` reader - Mode mismatch interrupt mask"] -pub type MMISM_R = crate::BitReader; +pub type MMISM_R = crate::BitReader; #[doc = "Field `MMISM` writer - Mode mismatch interrupt mask"] -pub type MMISM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type MMISM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OTGINT` reader - OTG interrupt mask"] -pub type OTGINT_R = crate::BitReader; +pub type OTGINT_R = crate::BitReader; #[doc = "Field `OTGINT` writer - OTG interrupt mask"] -pub type OTGINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type OTGINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOFM` reader - Start of frame mask"] -pub type SOFM_R = crate::BitReader; +pub type SOFM_R = crate::BitReader; #[doc = "Field `SOFM` writer - Start of frame mask"] -pub type SOFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type SOFM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFLVLM` reader - Receive FIFO nonempty mask"] -pub type RXFLVLM_R = crate::BitReader; +pub type RXFLVLM_R = crate::BitReader; #[doc = "Field `RXFLVLM` writer - Receive FIFO nonempty mask"] -pub type RXFLVLM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type RXFLVLM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NPTXFEM` reader - Nonperiodic TxFIFO empty mask"] -pub type NPTXFEM_R = crate::BitReader; +pub type NPTXFEM_R = crate::BitReader; #[doc = "Field `NPTXFEM` writer - Nonperiodic TxFIFO empty mask"] -pub type NPTXFEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type NPTXFEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GINAKEFFM` reader - Global nonperiodic IN NAK effective mask"] -pub type GINAKEFFM_R = crate::BitReader; +pub type GINAKEFFM_R = crate::BitReader; #[doc = "Field `GINAKEFFM` writer - Global nonperiodic IN NAK effective mask"] -pub type GINAKEFFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type GINAKEFFM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GONAKEFFM` reader - Global OUT NAK effective mask"] -pub type GONAKEFFM_R = crate::BitReader; +pub type GONAKEFFM_R = crate::BitReader; #[doc = "Field `GONAKEFFM` writer - Global OUT NAK effective mask"] -pub type GONAKEFFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type GONAKEFFM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ESUSPM` reader - Early suspend mask"] -pub type ESUSPM_R = crate::BitReader; +pub type ESUSPM_R = crate::BitReader; #[doc = "Field `ESUSPM` writer - Early suspend mask"] -pub type ESUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type ESUSPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBSUSPM` reader - USB suspend mask"] -pub type USBSUSPM_R = crate::BitReader; +pub type USBSUSPM_R = crate::BitReader; #[doc = "Field `USBSUSPM` writer - USB suspend mask"] -pub type USBSUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type USBSUSPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBRST` reader - USB reset mask"] -pub type USBRST_R = crate::BitReader; +pub type USBRST_R = crate::BitReader; #[doc = "Field `USBRST` writer - USB reset mask"] -pub type USBRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type USBRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENUMDNEM` reader - Enumeration done mask"] -pub type ENUMDNEM_R = crate::BitReader; +pub type ENUMDNEM_R = crate::BitReader; #[doc = "Field `ENUMDNEM` writer - Enumeration done mask"] -pub type ENUMDNEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type ENUMDNEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISOODRPM` reader - Isochronous OUT packet dropped interrupt mask"] -pub type ISOODRPM_R = crate::BitReader; +pub type ISOODRPM_R = crate::BitReader; #[doc = "Field `ISOODRPM` writer - Isochronous OUT packet dropped interrupt mask"] -pub type ISOODRPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type ISOODRPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOPFM` reader - End of periodic frame interrupt mask"] -pub type EOPFM_R = crate::BitReader; +pub type EOPFM_R = crate::BitReader; #[doc = "Field `EOPFM` writer - End of periodic frame interrupt mask"] -pub type EOPFM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type EOPFM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPMISM` reader - Endpoint mismatch interrupt mask"] -pub type EPMISM_R = crate::BitReader; +pub type EPMISM_R = crate::BitReader; #[doc = "Field `EPMISM` writer - Endpoint mismatch interrupt mask"] -pub type EPMISM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type EPMISM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IEPINT` reader - IN endpoints interrupt mask"] -pub type IEPINT_R = crate::BitReader; +pub type IEPINT_R = crate::BitReader; #[doc = "Field `IEPINT` writer - IN endpoints interrupt mask"] -pub type IEPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type IEPINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OEPINT` reader - OUT endpoints interrupt mask"] -pub type OEPINT_R = crate::BitReader; +pub type OEPINT_R = crate::BitReader; #[doc = "Field `OEPINT` writer - OUT endpoints interrupt mask"] -pub type OEPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type OEPINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IISOIXFRM` reader - Incomplete isochronous IN transfer mask"] -pub type IISOIXFRM_R = crate::BitReader; +pub type IISOIXFRM_R = crate::BitReader; #[doc = "Field `IISOIXFRM` writer - Incomplete isochronous IN transfer mask"] -pub type IISOIXFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type IISOIXFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PXFRM_IISOOXFRM` reader - Incomplete periodic transfer mask"] -pub type PXFRM_IISOOXFRM_R = crate::BitReader; +pub type PXFRM_IISOOXFRM_R = crate::BitReader; #[doc = "Field `PXFRM_IISOOXFRM` writer - Incomplete periodic transfer mask"] -pub type PXFRM_IISOOXFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type PXFRM_IISOOXFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSUSPM` reader - Data fetch suspended mask"] -pub type FSUSPM_R = crate::BitReader; +pub type FSUSPM_R = crate::BitReader; #[doc = "Field `FSUSPM` writer - Data fetch suspended mask"] -pub type FSUSPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type FSUSPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRTIM` reader - Host port interrupt mask"] -pub type PRTIM_R = crate::BitReader; +pub type PRTIM_R = crate::BitReader; #[doc = "Field `HCIM` reader - Host channels interrupt mask"] -pub type HCIM_R = crate::BitReader; +pub type HCIM_R = crate::BitReader; #[doc = "Field `HCIM` writer - Host channels interrupt mask"] -pub type HCIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type HCIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTXFEM` reader - Periodic TxFIFO empty mask"] -pub type PTXFEM_R = crate::BitReader; +pub type PTXFEM_R = crate::BitReader; #[doc = "Field `PTXFEM` writer - Periodic TxFIFO empty mask"] -pub type PTXFEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type PTXFEM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CIDSCHGM` reader - Connector ID status change mask"] -pub type CIDSCHGM_R = crate::BitReader; +pub type CIDSCHGM_R = crate::BitReader; #[doc = "Field `CIDSCHGM` writer - Connector ID status change mask"] -pub type CIDSCHGM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type CIDSCHGM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISCINT` reader - Disconnect detected interrupt mask"] -pub type DISCINT_R = crate::BitReader; +pub type DISCINT_R = crate::BitReader; #[doc = "Field `DISCINT` writer - Disconnect detected interrupt mask"] -pub type DISCINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type DISCINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRQIM` reader - Session request/new session detected interrupt mask"] -pub type SRQIM_R = crate::BitReader; +pub type SRQIM_R = crate::BitReader; #[doc = "Field `SRQIM` writer - Session request/new session detected interrupt mask"] -pub type SRQIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type SRQIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WUIM` reader - Resume/remote wakeup detected interrupt mask"] -pub type WUIM_R = crate::BitReader; +pub type WUIM_R = crate::BitReader; #[doc = "Field `WUIM` writer - Resume/remote wakeup detected interrupt mask"] -pub type WUIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTMSK_SPEC, bool, O>; +pub type WUIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - Mode mismatch interrupt mask"] #[inline(always)] @@ -268,176 +236,217 @@ impl R { WUIM_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GINTMSK") + .field("mmism", &format_args!("{}", self.mmism().bit())) + .field("otgint", &format_args!("{}", self.otgint().bit())) + .field("sofm", &format_args!("{}", self.sofm().bit())) + .field("rxflvlm", &format_args!("{}", self.rxflvlm().bit())) + .field("nptxfem", &format_args!("{}", self.nptxfem().bit())) + .field("ginakeffm", &format_args!("{}", self.ginakeffm().bit())) + .field("gonakeffm", &format_args!("{}", self.gonakeffm().bit())) + .field("esuspm", &format_args!("{}", self.esuspm().bit())) + .field("usbsuspm", &format_args!("{}", self.usbsuspm().bit())) + .field("usbrst", &format_args!("{}", self.usbrst().bit())) + .field("enumdnem", &format_args!("{}", self.enumdnem().bit())) + .field("isoodrpm", &format_args!("{}", self.isoodrpm().bit())) + .field("eopfm", &format_args!("{}", self.eopfm().bit())) + .field("epmism", &format_args!("{}", self.epmism().bit())) + .field("iepint", &format_args!("{}", self.iepint().bit())) + .field("oepint", &format_args!("{}", self.oepint().bit())) + .field("iisoixfrm", &format_args!("{}", self.iisoixfrm().bit())) + .field( + "pxfrm_iisooxfrm", + &format_args!("{}", self.pxfrm_iisooxfrm().bit()), + ) + .field("fsuspm", &format_args!("{}", self.fsuspm().bit())) + .field("prtim", &format_args!("{}", self.prtim().bit())) + .field("hcim", &format_args!("{}", self.hcim().bit())) + .field("ptxfem", &format_args!("{}", self.ptxfem().bit())) + .field("cidschgm", &format_args!("{}", self.cidschgm().bit())) + .field("discint", &format_args!("{}", self.discint().bit())) + .field("srqim", &format_args!("{}", self.srqim().bit())) + .field("wuim", &format_args!("{}", self.wuim().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Mode mismatch interrupt mask"] #[inline(always)] #[must_use] - pub fn mmism(&mut self) -> MMISM_W<1> { + pub fn mmism(&mut self) -> MMISM_W { MMISM_W::new(self) } #[doc = "Bit 2 - OTG interrupt mask"] #[inline(always)] #[must_use] - pub fn otgint(&mut self) -> OTGINT_W<2> { + pub fn otgint(&mut self) -> OTGINT_W { OTGINT_W::new(self) } #[doc = "Bit 3 - Start of frame mask"] #[inline(always)] #[must_use] - pub fn sofm(&mut self) -> SOFM_W<3> { + pub fn sofm(&mut self) -> SOFM_W { SOFM_W::new(self) } #[doc = "Bit 4 - Receive FIFO nonempty mask"] #[inline(always)] #[must_use] - pub fn rxflvlm(&mut self) -> RXFLVLM_W<4> { + pub fn rxflvlm(&mut self) -> RXFLVLM_W { RXFLVLM_W::new(self) } #[doc = "Bit 5 - Nonperiodic TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn nptxfem(&mut self) -> NPTXFEM_W<5> { + pub fn nptxfem(&mut self) -> NPTXFEM_W { NPTXFEM_W::new(self) } #[doc = "Bit 6 - Global nonperiodic IN NAK effective mask"] #[inline(always)] #[must_use] - pub fn ginakeffm(&mut self) -> GINAKEFFM_W<6> { + pub fn ginakeffm(&mut self) -> GINAKEFFM_W { GINAKEFFM_W::new(self) } #[doc = "Bit 7 - Global OUT NAK effective mask"] #[inline(always)] #[must_use] - pub fn gonakeffm(&mut self) -> GONAKEFFM_W<7> { + pub fn gonakeffm(&mut self) -> GONAKEFFM_W { GONAKEFFM_W::new(self) } #[doc = "Bit 10 - Early suspend mask"] #[inline(always)] #[must_use] - pub fn esuspm(&mut self) -> ESUSPM_W<10> { + pub fn esuspm(&mut self) -> ESUSPM_W { ESUSPM_W::new(self) } #[doc = "Bit 11 - USB suspend mask"] #[inline(always)] #[must_use] - pub fn usbsuspm(&mut self) -> USBSUSPM_W<11> { + pub fn usbsuspm(&mut self) -> USBSUSPM_W { USBSUSPM_W::new(self) } #[doc = "Bit 12 - USB reset mask"] #[inline(always)] #[must_use] - pub fn usbrst(&mut self) -> USBRST_W<12> { + pub fn usbrst(&mut self) -> USBRST_W { USBRST_W::new(self) } #[doc = "Bit 13 - Enumeration done mask"] #[inline(always)] #[must_use] - pub fn enumdnem(&mut self) -> ENUMDNEM_W<13> { + pub fn enumdnem(&mut self) -> ENUMDNEM_W { ENUMDNEM_W::new(self) } #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt mask"] #[inline(always)] #[must_use] - pub fn isoodrpm(&mut self) -> ISOODRPM_W<14> { + pub fn isoodrpm(&mut self) -> ISOODRPM_W { ISOODRPM_W::new(self) } #[doc = "Bit 15 - End of periodic frame interrupt mask"] #[inline(always)] #[must_use] - pub fn eopfm(&mut self) -> EOPFM_W<15> { + pub fn eopfm(&mut self) -> EOPFM_W { EOPFM_W::new(self) } #[doc = "Bit 17 - Endpoint mismatch interrupt mask"] #[inline(always)] #[must_use] - pub fn epmism(&mut self) -> EPMISM_W<17> { + pub fn epmism(&mut self) -> EPMISM_W { EPMISM_W::new(self) } #[doc = "Bit 18 - IN endpoints interrupt mask"] #[inline(always)] #[must_use] - pub fn iepint(&mut self) -> IEPINT_W<18> { + pub fn iepint(&mut self) -> IEPINT_W { IEPINT_W::new(self) } #[doc = "Bit 19 - OUT endpoints interrupt mask"] #[inline(always)] #[must_use] - pub fn oepint(&mut self) -> OEPINT_W<19> { + pub fn oepint(&mut self) -> OEPINT_W { OEPINT_W::new(self) } #[doc = "Bit 20 - Incomplete isochronous IN transfer mask"] #[inline(always)] #[must_use] - pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<20> { + pub fn iisoixfrm(&mut self) -> IISOIXFRM_W { IISOIXFRM_W::new(self) } #[doc = "Bit 21 - Incomplete periodic transfer mask"] #[inline(always)] #[must_use] - pub fn pxfrm_iisooxfrm(&mut self) -> PXFRM_IISOOXFRM_W<21> { + pub fn pxfrm_iisooxfrm(&mut self) -> PXFRM_IISOOXFRM_W { PXFRM_IISOOXFRM_W::new(self) } #[doc = "Bit 22 - Data fetch suspended mask"] #[inline(always)] #[must_use] - pub fn fsuspm(&mut self) -> FSUSPM_W<22> { + pub fn fsuspm(&mut self) -> FSUSPM_W { FSUSPM_W::new(self) } #[doc = "Bit 25 - Host channels interrupt mask"] #[inline(always)] #[must_use] - pub fn hcim(&mut self) -> HCIM_W<25> { + pub fn hcim(&mut self) -> HCIM_W { HCIM_W::new(self) } #[doc = "Bit 26 - Periodic TxFIFO empty mask"] #[inline(always)] #[must_use] - pub fn ptxfem(&mut self) -> PTXFEM_W<26> { + pub fn ptxfem(&mut self) -> PTXFEM_W { PTXFEM_W::new(self) } #[doc = "Bit 28 - Connector ID status change mask"] #[inline(always)] #[must_use] - pub fn cidschgm(&mut self) -> CIDSCHGM_W<28> { + pub fn cidschgm(&mut self) -> CIDSCHGM_W { CIDSCHGM_W::new(self) } #[doc = "Bit 29 - Disconnect detected interrupt mask"] #[inline(always)] #[must_use] - pub fn discint(&mut self) -> DISCINT_W<29> { + pub fn discint(&mut self) -> DISCINT_W { DISCINT_W::new(self) } #[doc = "Bit 30 - Session request/new session detected interrupt mask"] #[inline(always)] #[must_use] - pub fn srqim(&mut self) -> SRQIM_W<30> { + pub fn srqim(&mut self) -> SRQIM_W { SRQIM_W::new(self) } #[doc = "Bit 31 - Resume/remote wakeup detected interrupt mask"] #[inline(always)] #[must_use] - pub fn wuim(&mut self) -> WUIM_W<31> { + pub fn wuim(&mut self) -> WUIM_W { WUIM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintmsk](index.html) module"] +#[doc = "OTG_HS interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GINTMSK_SPEC; impl crate::RegisterSpec for GINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gintmsk::R](R) reader structure"] -impl crate::Readable for GINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`gintmsk::R`](R) reader structure"] +impl crate::Readable for GINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gintmsk::W`](W) writer structure"] impl crate::Writable for GINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gintsts.rs b/crates/bcm2837-lpa/src/usb_otg_global/gintsts.rs index 4dd3aa9..513d718 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/gintsts.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/gintsts.rs @@ -1,121 +1,89 @@ #[doc = "Register `GINTSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GINTSTS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMOD` reader - Current mode of operation"] -pub type CMOD_R = crate::BitReader; +pub type CMOD_R = crate::BitReader; #[doc = "Field `MMIS` reader - Mode mismatch interrupt"] -pub type MMIS_R = crate::BitReader; +pub type MMIS_R = crate::BitReader; #[doc = "Field `MMIS` writer - Mode mismatch interrupt"] -pub type MMIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type MMIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OTGINT` reader - OTG interrupt"] -pub type OTGINT_R = crate::BitReader; +pub type OTGINT_R = crate::BitReader; #[doc = "Field `SOF` reader - Start of frame"] -pub type SOF_R = crate::BitReader; +pub type SOF_R = crate::BitReader; #[doc = "Field `SOF` writer - Start of frame"] -pub type SOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type SOF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFLVL` reader - RxFIFO nonempty"] -pub type RXFLVL_R = crate::BitReader; +pub type RXFLVL_R = crate::BitReader; #[doc = "Field `NPTXFE` reader - Nonperiodic TxFIFO empty"] -pub type NPTXFE_R = crate::BitReader; +pub type NPTXFE_R = crate::BitReader; #[doc = "Field `GINAKEFF` reader - Global IN nonperiodic NAK effective"] -pub type GINAKEFF_R = crate::BitReader; +pub type GINAKEFF_R = crate::BitReader; #[doc = "Field `BOUTNAKEFF` reader - Global OUT NAK effective"] -pub type BOUTNAKEFF_R = crate::BitReader; +pub type BOUTNAKEFF_R = crate::BitReader; #[doc = "Field `ESUSP` reader - Early suspend"] -pub type ESUSP_R = crate::BitReader; +pub type ESUSP_R = crate::BitReader; #[doc = "Field `ESUSP` writer - Early suspend"] -pub type ESUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type ESUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBSUSP` reader - USB suspend"] -pub type USBSUSP_R = crate::BitReader; +pub type USBSUSP_R = crate::BitReader; #[doc = "Field `USBSUSP` writer - USB suspend"] -pub type USBSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type USBSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBRST` reader - USB reset"] -pub type USBRST_R = crate::BitReader; +pub type USBRST_R = crate::BitReader; #[doc = "Field `USBRST` writer - USB reset"] -pub type USBRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type USBRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENUMDNE` reader - Enumeration done"] -pub type ENUMDNE_R = crate::BitReader; +pub type ENUMDNE_R = crate::BitReader; #[doc = "Field `ENUMDNE` writer - Enumeration done"] -pub type ENUMDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type ENUMDNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISOODRP` reader - Isochronous OUT packet dropped interrupt"] -pub type ISOODRP_R = crate::BitReader; +pub type ISOODRP_R = crate::BitReader; #[doc = "Field `ISOODRP` writer - Isochronous OUT packet dropped interrupt"] -pub type ISOODRP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type ISOODRP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOPF` reader - End of periodic frame interrupt"] -pub type EOPF_R = crate::BitReader; +pub type EOPF_R = crate::BitReader; #[doc = "Field `EOPF` writer - End of periodic frame interrupt"] -pub type EOPF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type EOPF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IEPINT` reader - IN endpoint interrupt"] -pub type IEPINT_R = crate::BitReader; +pub type IEPINT_R = crate::BitReader; #[doc = "Field `OEPINT` reader - OUT endpoint interrupt"] -pub type OEPINT_R = crate::BitReader; +pub type OEPINT_R = crate::BitReader; #[doc = "Field `IISOIXFR` reader - Incomplete isochronous IN transfer"] -pub type IISOIXFR_R = crate::BitReader; +pub type IISOIXFR_R = crate::BitReader; #[doc = "Field `IISOIXFR` writer - Incomplete isochronous IN transfer"] -pub type IISOIXFR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type IISOIXFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PXFR_INCOMPISOOUT` reader - Incomplete periodic transfer"] -pub type PXFR_INCOMPISOOUT_R = crate::BitReader; +pub type PXFR_INCOMPISOOUT_R = crate::BitReader; #[doc = "Field `PXFR_INCOMPISOOUT` writer - Incomplete periodic transfer"] -pub type PXFR_INCOMPISOOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type PXFR_INCOMPISOOUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATAFSUSP` reader - Data fetch suspended"] -pub type DATAFSUSP_R = crate::BitReader; +pub type DATAFSUSP_R = crate::BitReader; #[doc = "Field `DATAFSUSP` writer - Data fetch suspended"] -pub type DATAFSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type DATAFSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HPRTINT` reader - Host port interrupt"] -pub type HPRTINT_R = crate::BitReader; +pub type HPRTINT_R = crate::BitReader; #[doc = "Field `HCINT` reader - Host channels interrupt"] -pub type HCINT_R = crate::BitReader; +pub type HCINT_R = crate::BitReader; #[doc = "Field `PTXFE` reader - Periodic TxFIFO empty"] -pub type PTXFE_R = crate::BitReader; +pub type PTXFE_R = crate::BitReader; #[doc = "Field `CIDSCHG` reader - Connector ID status change"] -pub type CIDSCHG_R = crate::BitReader; +pub type CIDSCHG_R = crate::BitReader; #[doc = "Field `CIDSCHG` writer - Connector ID status change"] -pub type CIDSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type CIDSCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISCINT` reader - Disconnect detected interrupt"] -pub type DISCINT_R = crate::BitReader; +pub type DISCINT_R = crate::BitReader; #[doc = "Field `DISCINT` writer - Disconnect detected interrupt"] -pub type DISCINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type DISCINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRQINT` reader - Session request/new session detected interrupt"] -pub type SRQINT_R = crate::BitReader; +pub type SRQINT_R = crate::BitReader; #[doc = "Field `SRQINT` writer - Session request/new session detected interrupt"] -pub type SRQINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type SRQINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WKUINT` reader - Resume/remote wakeup detected interrupt"] -pub type WKUINT_R = crate::BitReader; +pub type WKUINT_R = crate::BitReader; #[doc = "Field `WKUINT` writer - Resume/remote wakeup detected interrupt"] -pub type WKUINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GINTSTS_SPEC, bool, O>; +pub type WKUINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Current mode of operation"] #[inline(always)] @@ -248,116 +216,157 @@ impl R { WKUINT_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GINTSTS") + .field("cmod", &format_args!("{}", self.cmod().bit())) + .field("mmis", &format_args!("{}", self.mmis().bit())) + .field("otgint", &format_args!("{}", self.otgint().bit())) + .field("sof", &format_args!("{}", self.sof().bit())) + .field("rxflvl", &format_args!("{}", self.rxflvl().bit())) + .field("nptxfe", &format_args!("{}", self.nptxfe().bit())) + .field("ginakeff", &format_args!("{}", self.ginakeff().bit())) + .field("boutnakeff", &format_args!("{}", self.boutnakeff().bit())) + .field("esusp", &format_args!("{}", self.esusp().bit())) + .field("usbsusp", &format_args!("{}", self.usbsusp().bit())) + .field("usbrst", &format_args!("{}", self.usbrst().bit())) + .field("enumdne", &format_args!("{}", self.enumdne().bit())) + .field("isoodrp", &format_args!("{}", self.isoodrp().bit())) + .field("eopf", &format_args!("{}", self.eopf().bit())) + .field("iepint", &format_args!("{}", self.iepint().bit())) + .field("oepint", &format_args!("{}", self.oepint().bit())) + .field("iisoixfr", &format_args!("{}", self.iisoixfr().bit())) + .field( + "pxfr_incompisoout", + &format_args!("{}", self.pxfr_incompisoout().bit()), + ) + .field("datafsusp", &format_args!("{}", self.datafsusp().bit())) + .field("hprtint", &format_args!("{}", self.hprtint().bit())) + .field("hcint", &format_args!("{}", self.hcint().bit())) + .field("ptxfe", &format_args!("{}", self.ptxfe().bit())) + .field("cidschg", &format_args!("{}", self.cidschg().bit())) + .field("discint", &format_args!("{}", self.discint().bit())) + .field("srqint", &format_args!("{}", self.srqint().bit())) + .field("wkuint", &format_args!("{}", self.wkuint().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Mode mismatch interrupt"] #[inline(always)] #[must_use] - pub fn mmis(&mut self) -> MMIS_W<1> { + pub fn mmis(&mut self) -> MMIS_W { MMIS_W::new(self) } #[doc = "Bit 3 - Start of frame"] #[inline(always)] #[must_use] - pub fn sof(&mut self) -> SOF_W<3> { + pub fn sof(&mut self) -> SOF_W { SOF_W::new(self) } #[doc = "Bit 10 - Early suspend"] #[inline(always)] #[must_use] - pub fn esusp(&mut self) -> ESUSP_W<10> { + pub fn esusp(&mut self) -> ESUSP_W { ESUSP_W::new(self) } #[doc = "Bit 11 - USB suspend"] #[inline(always)] #[must_use] - pub fn usbsusp(&mut self) -> USBSUSP_W<11> { + pub fn usbsusp(&mut self) -> USBSUSP_W { USBSUSP_W::new(self) } #[doc = "Bit 12 - USB reset"] #[inline(always)] #[must_use] - pub fn usbrst(&mut self) -> USBRST_W<12> { + pub fn usbrst(&mut self) -> USBRST_W { USBRST_W::new(self) } #[doc = "Bit 13 - Enumeration done"] #[inline(always)] #[must_use] - pub fn enumdne(&mut self) -> ENUMDNE_W<13> { + pub fn enumdne(&mut self) -> ENUMDNE_W { ENUMDNE_W::new(self) } #[doc = "Bit 14 - Isochronous OUT packet dropped interrupt"] #[inline(always)] #[must_use] - pub fn isoodrp(&mut self) -> ISOODRP_W<14> { + pub fn isoodrp(&mut self) -> ISOODRP_W { ISOODRP_W::new(self) } #[doc = "Bit 15 - End of periodic frame interrupt"] #[inline(always)] #[must_use] - pub fn eopf(&mut self) -> EOPF_W<15> { + pub fn eopf(&mut self) -> EOPF_W { EOPF_W::new(self) } #[doc = "Bit 20 - Incomplete isochronous IN transfer"] #[inline(always)] #[must_use] - pub fn iisoixfr(&mut self) -> IISOIXFR_W<20> { + pub fn iisoixfr(&mut self) -> IISOIXFR_W { IISOIXFR_W::new(self) } #[doc = "Bit 21 - Incomplete periodic transfer"] #[inline(always)] #[must_use] - pub fn pxfr_incompisoout(&mut self) -> PXFR_INCOMPISOOUT_W<21> { + pub fn pxfr_incompisoout(&mut self) -> PXFR_INCOMPISOOUT_W { PXFR_INCOMPISOOUT_W::new(self) } #[doc = "Bit 22 - Data fetch suspended"] #[inline(always)] #[must_use] - pub fn datafsusp(&mut self) -> DATAFSUSP_W<22> { + pub fn datafsusp(&mut self) -> DATAFSUSP_W { DATAFSUSP_W::new(self) } #[doc = "Bit 28 - Connector ID status change"] #[inline(always)] #[must_use] - pub fn cidschg(&mut self) -> CIDSCHG_W<28> { + pub fn cidschg(&mut self) -> CIDSCHG_W { CIDSCHG_W::new(self) } #[doc = "Bit 29 - Disconnect detected interrupt"] #[inline(always)] #[must_use] - pub fn discint(&mut self) -> DISCINT_W<29> { + pub fn discint(&mut self) -> DISCINT_W { DISCINT_W::new(self) } #[doc = "Bit 30 - Session request/new session detected interrupt"] #[inline(always)] #[must_use] - pub fn srqint(&mut self) -> SRQINT_W<30> { + pub fn srqint(&mut self) -> SRQINT_W { SRQINT_W::new(self) } #[doc = "Bit 31 - Resume/remote wakeup detected interrupt"] #[inline(always)] #[must_use] - pub fn wkuint(&mut self) -> WKUINT_W<31> { + pub fn wkuint(&mut self) -> WKUINT_W { WKUINT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS core interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintsts](index.html) module"] +#[doc = "OTG_HS core interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gintsts::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gintsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GINTSTS_SPEC; impl crate::RegisterSpec for GINTSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gintsts::R](R) reader structure"] -impl crate::Readable for GINTSTS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gintsts::W](W) writer structure"] +#[doc = "`read()` method returns [`gintsts::R`](R) reader structure"] +impl crate::Readable for GINTSTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gintsts::W`](W) writer structure"] impl crate::Writable for GINTSTS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gnptxfsiz_host.rs b/crates/bcm2837-lpa/src/usb_otg_global/gnptxfsiz_host.rs index 89a5540..b2b7b4e 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/gnptxfsiz_host.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/gnptxfsiz_host.rs @@ -1,49 +1,15 @@ #[doc = "Register `GNPTXFSIZ_Host` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GNPTXFSIZ_Host` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NPTXFSA` reader - Nonperiodic transmit RAM start address"] -pub type NPTXFSA_R = crate::FieldReader; +pub type NPTXFSA_R = crate::FieldReader; #[doc = "Field `NPTXFSA` writer - Nonperiodic transmit RAM start address"] -pub type NPTXFSA_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GNPTXFSIZ_HOST_SPEC, u16, u16, 16, O>; +pub type NPTXFSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `NPTXFD` reader - Nonperiodic TxFIFO depth"] -pub type NPTXFD_R = crate::FieldReader; +pub type NPTXFD_R = crate::FieldReader; #[doc = "Field `NPTXFD` writer - Nonperiodic TxFIFO depth"] -pub type NPTXFD_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, GNPTXFSIZ_HOST_SPEC, u16, u16, 16, O>; +pub type NPTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Nonperiodic transmit RAM start address"] #[inline(always)] @@ -56,38 +22,52 @@ impl R { NPTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GNPTXFSIZ_Host") + .field("nptxfsa", &format_args!("{}", self.nptxfsa().bits())) + .field("nptxfd", &format_args!("{}", self.nptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Nonperiodic transmit RAM start address"] #[inline(always)] #[must_use] - pub fn nptxfsa(&mut self) -> NPTXFSA_W<0> { + pub fn nptxfsa(&mut self) -> NPTXFSA_W { NPTXFSA_W::new(self) } #[doc = "Bits 16:31 - Nonperiodic TxFIFO depth"] #[inline(always)] #[must_use] - pub fn nptxfd(&mut self) -> NPTXFD_W<16> { + pub fn nptxfd(&mut self) -> NPTXFD_W { NPTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxfsiz_host](index.html) module"] +#[doc = "OTG_HS nonperiodic transmit FIFO size register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxfsiz_host::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gnptxfsiz_host::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GNPTXFSIZ_HOST_SPEC; impl crate::RegisterSpec for GNPTXFSIZ_HOST_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gnptxfsiz_host::R](R) reader structure"] -impl crate::Readable for GNPTXFSIZ_HOST_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gnptxfsiz_host::W](W) writer structure"] +#[doc = "`read()` method returns [`gnptxfsiz_host::R`](R) reader structure"] +impl crate::Readable for GNPTXFSIZ_HOST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gnptxfsiz_host::W`](W) writer structure"] impl crate::Writable for GNPTXFSIZ_HOST_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gnptxsts.rs b/crates/bcm2837-lpa/src/usb_otg_global/gnptxsts.rs index 65ffd12..2b32a6f 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/gnptxsts.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/gnptxsts.rs @@ -1,24 +1,11 @@ #[doc = "Register `GNPTXSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NPTXFSAV` reader - Nonperiodic TxFIFO space available"] -pub type NPTXFSAV_R = crate::FieldReader; +pub type NPTXFSAV_R = crate::FieldReader; #[doc = "Field `NPTQXSAV` reader - Nonperiodic transmit request queue space available"] -pub type NPTQXSAV_R = crate::FieldReader; +pub type NPTQXSAV_R = crate::FieldReader; #[doc = "Field `NPTXQTOP` reader - Top of the nonperiodic transmit request queue"] -pub type NPTXQTOP_R = crate::FieldReader; +pub type NPTXQTOP_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - Nonperiodic TxFIFO space available"] #[inline(always)] @@ -36,15 +23,27 @@ impl R { NPTXQTOP_R::new(((self.bits >> 24) & 0x7f) as u8) } } -#[doc = "OTG_HS nonperiodic transmit FIFO/queue status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxsts](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GNPTXSTS") + .field("nptxfsav", &format_args!("{}", self.nptxfsav().bits())) + .field("nptqxsav", &format_args!("{}", self.nptqxsav().bits())) + .field("nptxqtop", &format_args!("{}", self.nptxqtop().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS nonperiodic transmit FIFO/queue status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxsts::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GNPTXSTS_SPEC; impl crate::RegisterSpec for GNPTXSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gnptxsts::R](R) reader structure"] -impl crate::Readable for GNPTXSTS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gnptxsts::R`](R) reader structure"] +impl crate::Readable for GNPTXSTS_SPEC {} #[doc = "`reset()` method sets GNPTXSTS to value 0x0008_0200"] impl crate::Resettable for GNPTXSTS_SPEC { const RESET_VALUE: Self::Ux = 0x0008_0200; diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gotgctl.rs b/crates/bcm2837-lpa/src/usb_otg_global/gotgctl.rs index 6576636..36b3f21 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/gotgctl.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/gotgctl.rs @@ -1,67 +1,35 @@ #[doc = "Register `GOTGCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GOTGCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SRQSCS` reader - Session request success"] -pub type SRQSCS_R = crate::BitReader; +pub type SRQSCS_R = crate::BitReader; #[doc = "Field `SRQ` reader - Session request"] -pub type SRQ_R = crate::BitReader; +pub type SRQ_R = crate::BitReader; #[doc = "Field `SRQ` writer - Session request"] -pub type SRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +pub type SRQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HNGSCS` reader - Host negotiation success"] -pub type HNGSCS_R = crate::BitReader; +pub type HNGSCS_R = crate::BitReader; #[doc = "Field `HNPRQ` reader - HNP request"] -pub type HNPRQ_R = crate::BitReader; +pub type HNPRQ_R = crate::BitReader; #[doc = "Field `HNPRQ` writer - HNP request"] -pub type HNPRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +pub type HNPRQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HSHNPEN` reader - Host set HNP enable"] -pub type HSHNPEN_R = crate::BitReader; +pub type HSHNPEN_R = crate::BitReader; #[doc = "Field `HSHNPEN` writer - Host set HNP enable"] -pub type HSHNPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +pub type HSHNPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DHNPEN` reader - Device HNP enabled"] -pub type DHNPEN_R = crate::BitReader; +pub type DHNPEN_R = crate::BitReader; #[doc = "Field `DHNPEN` writer - Device HNP enabled"] -pub type DHNPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGCTL_SPEC, bool, O>; +pub type DHNPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CIDSTS` reader - Connector ID status"] -pub type CIDSTS_R = crate::BitReader; +pub type CIDSTS_R = crate::BitReader; #[doc = "Field `DBCT` reader - Long/short debounce time"] -pub type DBCT_R = crate::BitReader; +pub type DBCT_R = crate::BitReader; #[doc = "Field `ASVLD` reader - A-session valid"] -pub type ASVLD_R = crate::BitReader; +pub type ASVLD_R = crate::BitReader; #[doc = "Field `BSVLD` reader - B-session valid"] -pub type BSVLD_R = crate::BitReader; +pub type BSVLD_R = crate::BitReader; impl R { #[doc = "Bit 0 - Session request success"] #[inline(always)] @@ -114,50 +82,72 @@ impl R { BSVLD_R::new(((self.bits >> 19) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GOTGCTL") + .field("srqscs", &format_args!("{}", self.srqscs().bit())) + .field("srq", &format_args!("{}", self.srq().bit())) + .field("hngscs", &format_args!("{}", self.hngscs().bit())) + .field("hnprq", &format_args!("{}", self.hnprq().bit())) + .field("hshnpen", &format_args!("{}", self.hshnpen().bit())) + .field("dhnpen", &format_args!("{}", self.dhnpen().bit())) + .field("cidsts", &format_args!("{}", self.cidsts().bit())) + .field("dbct", &format_args!("{}", self.dbct().bit())) + .field("asvld", &format_args!("{}", self.asvld().bit())) + .field("bsvld", &format_args!("{}", self.bsvld().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Session request"] #[inline(always)] #[must_use] - pub fn srq(&mut self) -> SRQ_W<1> { + pub fn srq(&mut self) -> SRQ_W { SRQ_W::new(self) } #[doc = "Bit 9 - HNP request"] #[inline(always)] #[must_use] - pub fn hnprq(&mut self) -> HNPRQ_W<9> { + pub fn hnprq(&mut self) -> HNPRQ_W { HNPRQ_W::new(self) } #[doc = "Bit 10 - Host set HNP enable"] #[inline(always)] #[must_use] - pub fn hshnpen(&mut self) -> HSHNPEN_W<10> { + pub fn hshnpen(&mut self) -> HSHNPEN_W { HSHNPEN_W::new(self) } #[doc = "Bit 11 - Device HNP enabled"] #[inline(always)] #[must_use] - pub fn dhnpen(&mut self) -> DHNPEN_W<11> { + pub fn dhnpen(&mut self) -> DHNPEN_W { DHNPEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgctl](index.html) module"] +#[doc = "OTG_HS control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gotgctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gotgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GOTGCTL_SPEC; impl crate::RegisterSpec for GOTGCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gotgctl::R](R) reader structure"] -impl crate::Readable for GOTGCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gotgctl::W](W) writer structure"] +#[doc = "`read()` method returns [`gotgctl::R`](R) reader structure"] +impl crate::Readable for GOTGCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gotgctl::W`](W) writer structure"] impl crate::Writable for GOTGCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gotgint.rs b/crates/bcm2837-lpa/src/usb_otg_global/gotgint.rs index b2c3ab9..a44613f 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/gotgint.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/gotgint.rs @@ -1,63 +1,31 @@ #[doc = "Register `GOTGINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GOTGINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SEDET` reader - Session end detected"] -pub type SEDET_R = crate::BitReader; +pub type SEDET_R = crate::BitReader; #[doc = "Field `SEDET` writer - Session end detected"] -pub type SEDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type SEDET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRSSCHG` reader - Session request success status change"] -pub type SRSSCHG_R = crate::BitReader; +pub type SRSSCHG_R = crate::BitReader; #[doc = "Field `SRSSCHG` writer - Session request success status change"] -pub type SRSSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type SRSSCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HNSSCHG` reader - Host negotiation success status change"] -pub type HNSSCHG_R = crate::BitReader; +pub type HNSSCHG_R = crate::BitReader; #[doc = "Field `HNSSCHG` writer - Host negotiation success status change"] -pub type HNSSCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type HNSSCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HNGDET` reader - Host negotiation detected"] -pub type HNGDET_R = crate::BitReader; +pub type HNGDET_R = crate::BitReader; #[doc = "Field `HNGDET` writer - Host negotiation detected"] -pub type HNGDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type HNGDET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ADTOCHG` reader - A-device timeout change"] -pub type ADTOCHG_R = crate::BitReader; +pub type ADTOCHG_R = crate::BitReader; #[doc = "Field `ADTOCHG` writer - A-device timeout change"] -pub type ADTOCHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type ADTOCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DBCDNE` reader - Debounce done"] -pub type DBCDNE_R = crate::BitReader; +pub type DBCDNE_R = crate::BitReader; #[doc = "Field `DBCDNE` writer - Debounce done"] -pub type DBCDNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GOTGINT_SPEC, bool, O>; +pub type DBCDNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 2 - Session end detected"] #[inline(always)] @@ -90,62 +58,80 @@ impl R { DBCDNE_R::new(((self.bits >> 19) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GOTGINT") + .field("sedet", &format_args!("{}", self.sedet().bit())) + .field("srsschg", &format_args!("{}", self.srsschg().bit())) + .field("hnsschg", &format_args!("{}", self.hnsschg().bit())) + .field("hngdet", &format_args!("{}", self.hngdet().bit())) + .field("adtochg", &format_args!("{}", self.adtochg().bit())) + .field("dbcdne", &format_args!("{}", self.dbcdne().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 2 - Session end detected"] #[inline(always)] #[must_use] - pub fn sedet(&mut self) -> SEDET_W<2> { + pub fn sedet(&mut self) -> SEDET_W { SEDET_W::new(self) } #[doc = "Bit 8 - Session request success status change"] #[inline(always)] #[must_use] - pub fn srsschg(&mut self) -> SRSSCHG_W<8> { + pub fn srsschg(&mut self) -> SRSSCHG_W { SRSSCHG_W::new(self) } #[doc = "Bit 9 - Host negotiation success status change"] #[inline(always)] #[must_use] - pub fn hnsschg(&mut self) -> HNSSCHG_W<9> { + pub fn hnsschg(&mut self) -> HNSSCHG_W { HNSSCHG_W::new(self) } #[doc = "Bit 17 - Host negotiation detected"] #[inline(always)] #[must_use] - pub fn hngdet(&mut self) -> HNGDET_W<17> { + pub fn hngdet(&mut self) -> HNGDET_W { HNGDET_W::new(self) } #[doc = "Bit 18 - A-device timeout change"] #[inline(always)] #[must_use] - pub fn adtochg(&mut self) -> ADTOCHG_W<18> { + pub fn adtochg(&mut self) -> ADTOCHG_W { ADTOCHG_W::new(self) } #[doc = "Bit 19 - Debounce done"] #[inline(always)] #[must_use] - pub fn dbcdne(&mut self) -> DBCDNE_W<19> { + pub fn dbcdne(&mut self) -> DBCDNE_W { DBCDNE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgint](index.html) module"] +#[doc = "OTG_HS interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gotgint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gotgint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GOTGINT_SPEC; impl crate::RegisterSpec for GOTGINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gotgint::R](R) reader structure"] -impl crate::Readable for GOTGINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gotgint::W](W) writer structure"] +#[doc = "`read()` method returns [`gotgint::R`](R) reader structure"] +impl crate::Readable for GOTGINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gotgint::W`](W) writer structure"] impl crate::Writable for GOTGINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/grstctl.rs b/crates/bcm2837-lpa/src/usb_otg_global/grstctl.rs index c3f83dc..799d4ca 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/grstctl.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/grstctl.rs @@ -1,67 +1,35 @@ #[doc = "Register `GRSTCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GRSTCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CSRST` reader - Core soft reset"] -pub type CSRST_R = crate::BitReader; +pub type CSRST_R = crate::BitReader; #[doc = "Field `CSRST` writer - Core soft reset"] -pub type CSRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type CSRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HSRST` reader - HCLK soft reset"] -pub type HSRST_R = crate::BitReader; +pub type HSRST_R = crate::BitReader; #[doc = "Field `HSRST` writer - HCLK soft reset"] -pub type HSRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type HSRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FCRST` reader - Host frame counter reset"] -pub type FCRST_R = crate::BitReader; +pub type FCRST_R = crate::BitReader; #[doc = "Field `FCRST` writer - Host frame counter reset"] -pub type FCRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type FCRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXFFLSH` reader - RxFIFO flush"] -pub type RXFFLSH_R = crate::BitReader; +pub type RXFFLSH_R = crate::BitReader; #[doc = "Field `RXFFLSH` writer - RxFIFO flush"] -pub type RXFFLSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type RXFFLSH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFFLSH` reader - TxFIFO flush"] -pub type TXFFLSH_R = crate::BitReader; +pub type TXFFLSH_R = crate::BitReader; #[doc = "Field `TXFFLSH` writer - TxFIFO flush"] -pub type TXFFLSH_W<'a, const O: u8> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, O>; +pub type TXFFLSH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXFNUM` reader - TxFIFO number"] -pub type TXFNUM_R = crate::FieldReader; +pub type TXFNUM_R = crate::FieldReader; #[doc = "Field `TXFNUM` writer - TxFIFO number"] -pub type TXFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GRSTCTL_SPEC, u8, u8, 5, O>; +pub type TXFNUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `DMAREQ` reader - DMA request signal"] -pub type DMAREQ_R = crate::BitReader; +pub type DMAREQ_R = crate::BitReader; #[doc = "Field `AHBIDL` reader - AHB master idle"] -pub type AHBIDL_R = crate::BitReader; +pub type AHBIDL_R = crate::BitReader; impl R { #[doc = "Bit 0 - Core soft reset"] #[inline(always)] @@ -104,62 +72,82 @@ impl R { AHBIDL_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRSTCTL") + .field("csrst", &format_args!("{}", self.csrst().bit())) + .field("hsrst", &format_args!("{}", self.hsrst().bit())) + .field("fcrst", &format_args!("{}", self.fcrst().bit())) + .field("rxfflsh", &format_args!("{}", self.rxfflsh().bit())) + .field("txfflsh", &format_args!("{}", self.txfflsh().bit())) + .field("txfnum", &format_args!("{}", self.txfnum().bits())) + .field("dmareq", &format_args!("{}", self.dmareq().bit())) + .field("ahbidl", &format_args!("{}", self.ahbidl().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Core soft reset"] #[inline(always)] #[must_use] - pub fn csrst(&mut self) -> CSRST_W<0> { + pub fn csrst(&mut self) -> CSRST_W { CSRST_W::new(self) } #[doc = "Bit 1 - HCLK soft reset"] #[inline(always)] #[must_use] - pub fn hsrst(&mut self) -> HSRST_W<1> { + pub fn hsrst(&mut self) -> HSRST_W { HSRST_W::new(self) } #[doc = "Bit 2 - Host frame counter reset"] #[inline(always)] #[must_use] - pub fn fcrst(&mut self) -> FCRST_W<2> { + pub fn fcrst(&mut self) -> FCRST_W { FCRST_W::new(self) } #[doc = "Bit 4 - RxFIFO flush"] #[inline(always)] #[must_use] - pub fn rxfflsh(&mut self) -> RXFFLSH_W<4> { + pub fn rxfflsh(&mut self) -> RXFFLSH_W { RXFFLSH_W::new(self) } #[doc = "Bit 5 - TxFIFO flush"] #[inline(always)] #[must_use] - pub fn txfflsh(&mut self) -> TXFFLSH_W<5> { + pub fn txfflsh(&mut self) -> TXFFLSH_W { TXFFLSH_W::new(self) } #[doc = "Bits 6:10 - TxFIFO number"] #[inline(always)] #[must_use] - pub fn txfnum(&mut self) -> TXFNUM_W<6> { + pub fn txfnum(&mut self) -> TXFNUM_W { TXFNUM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS reset register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grstctl](index.html) module"] +#[doc = "OTG_HS reset register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grstctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grstctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRSTCTL_SPEC; impl crate::RegisterSpec for GRSTCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grstctl::R](R) reader structure"] -impl crate::Readable for GRSTCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [grstctl::W](W) writer structure"] +#[doc = "`read()` method returns [`grstctl::R`](R) reader structure"] +impl crate::Readable for GRSTCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`grstctl::W`](W) writer structure"] impl crate::Writable for GRSTCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/grxfsiz.rs b/crates/bcm2837-lpa/src/usb_otg_global/grxfsiz.rs index ec6ba8c..b243ab8 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/grxfsiz.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/grxfsiz.rs @@ -1,43 +1,11 @@ #[doc = "Register `GRXFSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GRXFSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXFD` reader - RxFIFO depth"] -pub type RXFD_R = crate::FieldReader; +pub type RXFD_R = crate::FieldReader; #[doc = "Field `RXFD` writer - RxFIFO depth"] -pub type RXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GRXFSIZ_SPEC, u16, u16, 16, O>; +pub type RXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - RxFIFO depth"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { RXFD_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXFSIZ") + .field("rxfd", &format_args!("{}", self.rxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - RxFIFO depth"] #[inline(always)] #[must_use] - pub fn rxfd(&mut self) -> RXFD_W<0> { + pub fn rxfd(&mut self) -> RXFD_W { RXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS Receive FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxfsiz](index.html) module"] +#[doc = "OTG_HS Receive FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxfsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grxfsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXFSIZ_SPEC; impl crate::RegisterSpec for GRXFSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxfsiz::R](R) reader structure"] -impl crate::Readable for GRXFSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [grxfsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`grxfsiz::R`](R) reader structure"] +impl crate::Readable for GRXFSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`grxfsiz::W`](W) writer structure"] impl crate::Writable for GRXFSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_host.rs b/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_host.rs index a0231ff..5e8d3bb 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_host.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_host.rs @@ -1,26 +1,13 @@ #[doc = "Register `GRXSTSP_Host` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CHNUM` reader - Channel number"] -pub type CHNUM_R = crate::FieldReader; +pub type CHNUM_R = crate::FieldReader; #[doc = "Field `BCNT` reader - Byte count"] -pub type BCNT_R = crate::FieldReader; +pub type BCNT_R = crate::FieldReader; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `PKTSTS` reader - Packet status"] -pub type PKTSTS_R = crate::FieldReader; +pub type PKTSTS_R = crate::FieldReader; impl R { #[doc = "Bits 0:3 - Channel number"] #[inline(always)] @@ -43,15 +30,28 @@ impl R { PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) } } -#[doc = "OTG_HS status read and pop register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsp_host](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXSTSP_Host") + .field("chnum", &format_args!("{}", self.chnum().bits())) + .field("bcnt", &format_args!("{}", self.bcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .field("pktsts", &format_args!("{}", self.pktsts().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS status read and pop register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp_host::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXSTSP_HOST_SPEC; impl crate::RegisterSpec for GRXSTSP_HOST_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxstsp_host::R](R) reader structure"] -impl crate::Readable for GRXSTSP_HOST_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`grxstsp_host::R`](R) reader structure"] +impl crate::Readable for GRXSTSP_HOST_SPEC {} #[doc = "`reset()` method sets GRXSTSP_Host to value 0"] impl crate::Resettable for GRXSTSP_HOST_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_peripheral.rs b/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_peripheral.rs index 5de1533..e28018e 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_peripheral.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/grxstsp_peripheral.rs @@ -1,28 +1,15 @@ #[doc = "Register `GRXSTSP_Peripheral` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EPNUM` reader - Endpoint number"] -pub type EPNUM_R = crate::FieldReader; +pub type EPNUM_R = crate::FieldReader; #[doc = "Field `BCNT` reader - Byte count"] -pub type BCNT_R = crate::FieldReader; +pub type BCNT_R = crate::FieldReader; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `PKTSTS` reader - Packet status"] -pub type PKTSTS_R = crate::FieldReader; +pub type PKTSTS_R = crate::FieldReader; #[doc = "Field `FRMNUM` reader - Frame number"] -pub type FRMNUM_R = crate::FieldReader; +pub type FRMNUM_R = crate::FieldReader; impl R { #[doc = "Bits 0:3 - Endpoint number"] #[inline(always)] @@ -50,15 +37,29 @@ impl R { FRMNUM_R::new(((self.bits >> 21) & 0x0f) as u8) } } -#[doc = "OTG_HS status read and pop register (peripheral mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsp_peripheral](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXSTSP_Peripheral") + .field("epnum", &format_args!("{}", self.epnum().bits())) + .field("bcnt", &format_args!("{}", self.bcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .field("pktsts", &format_args!("{}", self.pktsts().bits())) + .field("frmnum", &format_args!("{}", self.frmnum().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS status read and pop register (peripheral mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp_peripheral::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXSTSP_PERIPHERAL_SPEC; impl crate::RegisterSpec for GRXSTSP_PERIPHERAL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxstsp_peripheral::R](R) reader structure"] -impl crate::Readable for GRXSTSP_PERIPHERAL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`grxstsp_peripheral::R`](R) reader structure"] +impl crate::Readable for GRXSTSP_PERIPHERAL_SPEC {} #[doc = "`reset()` method sets GRXSTSP_Peripheral to value 0"] impl crate::Resettable for GRXSTSP_PERIPHERAL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_host.rs b/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_host.rs index 399a9f8..e9e1ba6 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_host.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_host.rs @@ -1,26 +1,13 @@ #[doc = "Register `GRXSTSR_Host` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CHNUM` reader - Channel number"] -pub type CHNUM_R = crate::FieldReader; +pub type CHNUM_R = crate::FieldReader; #[doc = "Field `BCNT` reader - Byte count"] -pub type BCNT_R = crate::FieldReader; +pub type BCNT_R = crate::FieldReader; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `PKTSTS` reader - Packet status"] -pub type PKTSTS_R = crate::FieldReader; +pub type PKTSTS_R = crate::FieldReader; impl R { #[doc = "Bits 0:3 - Channel number"] #[inline(always)] @@ -43,15 +30,28 @@ impl R { PKTSTS_R::new(((self.bits >> 17) & 0x0f) as u8) } } -#[doc = "OTG_HS Receive status debug read register (host mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsr_host](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXSTSR_Host") + .field("chnum", &format_args!("{}", self.chnum().bits())) + .field("bcnt", &format_args!("{}", self.bcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .field("pktsts", &format_args!("{}", self.pktsts().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS Receive status debug read register (host mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr_host::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXSTSR_HOST_SPEC; impl crate::RegisterSpec for GRXSTSR_HOST_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxstsr_host::R](R) reader structure"] -impl crate::Readable for GRXSTSR_HOST_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`grxstsr_host::R`](R) reader structure"] +impl crate::Readable for GRXSTSR_HOST_SPEC {} #[doc = "`reset()` method sets GRXSTSR_Host to value 0"] impl crate::Resettable for GRXSTSR_HOST_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_peripheral.rs b/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_peripheral.rs index 89558d9..d6f8ca3 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_peripheral.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/grxstsr_peripheral.rs @@ -1,28 +1,15 @@ #[doc = "Register `GRXSTSR_Peripheral` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EPNUM` reader - Endpoint number"] -pub type EPNUM_R = crate::FieldReader; +pub type EPNUM_R = crate::FieldReader; #[doc = "Field `BCNT` reader - Byte count"] -pub type BCNT_R = crate::FieldReader; +pub type BCNT_R = crate::FieldReader; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `PKTSTS` reader - Packet status"] -pub type PKTSTS_R = crate::FieldReader; +pub type PKTSTS_R = crate::FieldReader; #[doc = "Field `FRMNUM` reader - Frame number"] -pub type FRMNUM_R = crate::FieldReader; +pub type FRMNUM_R = crate::FieldReader; impl R { #[doc = "Bits 0:3 - Endpoint number"] #[inline(always)] @@ -50,15 +37,29 @@ impl R { FRMNUM_R::new(((self.bits >> 21) & 0x0f) as u8) } } -#[doc = "OTG_HS Receive status debug read register (peripheral mode mode)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsr_peripheral](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GRXSTSR_Peripheral") + .field("epnum", &format_args!("{}", self.epnum().bits())) + .field("bcnt", &format_args!("{}", self.bcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .field("pktsts", &format_args!("{}", self.pktsts().bits())) + .field("frmnum", &format_args!("{}", self.frmnum().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS Receive status debug read register (peripheral mode mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr_peripheral::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRXSTSR_PERIPHERAL_SPEC; impl crate::RegisterSpec for GRXSTSR_PERIPHERAL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grxstsr_peripheral::R](R) reader structure"] -impl crate::Readable for GRXSTSR_PERIPHERAL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`grxstsr_peripheral::R`](R) reader structure"] +impl crate::Readable for GRXSTSR_PERIPHERAL_SPEC {} #[doc = "`reset()` method sets GRXSTSR_Peripheral to value 0"] impl crate::Resettable for GRXSTSR_PERIPHERAL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/usb_otg_global/gusbcfg.rs b/crates/bcm2837-lpa/src/usb_otg_global/gusbcfg.rs index a958441..b5f882e 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/gusbcfg.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/gusbcfg.rs @@ -1,43 +1,11 @@ #[doc = "Register `GUSBCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GUSBCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TOCAL` reader - FS timeout calibration"] -pub type TOCAL_R = crate::FieldReader; +pub type TOCAL_R = crate::FieldReader; #[doc = "Field `TOCAL` writer - FS timeout calibration"] -pub type TOCAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GUSBCFG_SPEC, u8, u8, 3, O>; +pub type TOCAL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `PHYIF` reader - PHY Interface width"] pub type PHYIF_R = crate::BitReader; #[doc = "PHY Interface width\n\nValue on reset: 0"] @@ -57,34 +25,37 @@ impl From for bool { impl PHYIF_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PHYIF_A { + pub const fn variant(&self) -> PHYIF_A { match self.bits { false => PHYIF_A::_8BIT, true => PHYIF_A::_16BIT, } } - #[doc = "Checks if the value of the field is `_8BIT`"] + #[doc = "`0`"] #[inline(always)] pub fn is_8bit(&self) -> bool { *self == PHYIF_A::_8BIT } - #[doc = "Checks if the value of the field is `_16BIT`"] + #[doc = "`1`"] #[inline(always)] pub fn is_16bit(&self) -> bool { *self == PHYIF_A::_16BIT } } #[doc = "Field `PHYIF` writer - PHY Interface width"] -pub type PHYIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYIF_A, O>; -impl<'a, const O: u8> PHYIF_W<'a, O> { +pub type PHYIF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PHYIF_A>; +impl<'a, REG, const O: u8> PHYIF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn _8bit(self) -> &'a mut W { + pub fn _8bit(self) -> &'a mut crate::W { self.variant(PHYIF_A::_8BIT) } #[doc = "`1`"] #[inline(always)] - pub fn _16bit(self) -> &'a mut W { + pub fn _16bit(self) -> &'a mut crate::W { self.variant(PHYIF_A::_16BIT) } } @@ -107,34 +78,37 @@ impl From for bool { impl PHYTYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PHYTYPE_A { + pub const fn variant(&self) -> PHYTYPE_A { match self.bits { false => PHYTYPE_A::UTMI, true => PHYTYPE_A::ULPI, } } - #[doc = "Checks if the value of the field is `UTMI`"] + #[doc = "`0`"] #[inline(always)] pub fn is_utmi(&self) -> bool { *self == PHYTYPE_A::UTMI } - #[doc = "Checks if the value of the field is `ULPI`"] + #[doc = "`1`"] #[inline(always)] pub fn is_ulpi(&self) -> bool { *self == PHYTYPE_A::ULPI } } #[doc = "Field `PHYTYPE` writer - PHY Type"] -pub type PHYTYPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYTYPE_A, O>; -impl<'a, const O: u8> PHYTYPE_W<'a, O> { +pub type PHYTYPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PHYTYPE_A>; +impl<'a, REG, const O: u8> PHYTYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn utmi(self) -> &'a mut W { + pub fn utmi(self) -> &'a mut crate::W { self.variant(PHYTYPE_A::UTMI) } #[doc = "`1`"] #[inline(always)] - pub fn ulpi(self) -> &'a mut W { + pub fn ulpi(self) -> &'a mut crate::W { self.variant(PHYTYPE_A::ULPI) } } @@ -157,34 +131,37 @@ impl From for bool { impl FSIF_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FSIF_A { + pub const fn variant(&self) -> FSIF_A { match self.bits { false => FSIF_A::_6PIN, true => FSIF_A::_3PIN, } } - #[doc = "Checks if the value of the field is `_6PIN`"] + #[doc = "`0`"] #[inline(always)] pub fn is_6pin(&self) -> bool { *self == FSIF_A::_6PIN } - #[doc = "Checks if the value of the field is `_3PIN`"] + #[doc = "`1`"] #[inline(always)] pub fn is_3pin(&self) -> bool { *self == FSIF_A::_3PIN } } #[doc = "Field `FSIF` writer - Full speed interface"] -pub type FSIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, FSIF_A, O>; -impl<'a, const O: u8> FSIF_W<'a, O> { +pub type FSIF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, FSIF_A>; +impl<'a, REG, const O: u8> FSIF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn _6pin(self) -> &'a mut W { + pub fn _6pin(self) -> &'a mut crate::W { self.variant(FSIF_A::_6PIN) } #[doc = "`1`"] #[inline(always)] - pub fn _3pin(self) -> &'a mut W { + pub fn _3pin(self) -> &'a mut crate::W { self.variant(FSIF_A::_3PIN) } } @@ -207,34 +184,37 @@ impl From for bool { impl PHYSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> PHYSEL_A { + pub const fn variant(&self) -> PHYSEL_A { match self.bits { false => PHYSEL_A::USB20, true => PHYSEL_A::USB11, } } - #[doc = "Checks if the value of the field is `USB20`"] + #[doc = "`0`"] #[inline(always)] pub fn is_usb20(&self) -> bool { *self == PHYSEL_A::USB20 } - #[doc = "Checks if the value of the field is `USB11`"] + #[doc = "`1`"] #[inline(always)] pub fn is_usb11(&self) -> bool { *self == PHYSEL_A::USB11 } } #[doc = "Field `PHYSEL` writer - Transceiver select"] -pub type PHYSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, PHYSEL_A, O>; -impl<'a, const O: u8> PHYSEL_W<'a, O> { +pub type PHYSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, PHYSEL_A>; +impl<'a, REG, const O: u8> PHYSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn usb20(self) -> &'a mut W { + pub fn usb20(self) -> &'a mut crate::W { self.variant(PHYSEL_A::USB20) } #[doc = "`1`"] #[inline(always)] - pub fn usb11(self) -> &'a mut W { + pub fn usb11(self) -> &'a mut crate::W { self.variant(PHYSEL_A::USB11) } } @@ -257,101 +237,104 @@ impl From for bool { impl DDRSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> DDRSEL_A { + pub const fn variant(&self) -> DDRSEL_A { match self.bits { false => DDRSEL_A::SINGLE, true => DDRSEL_A::DOUBLE, } } - #[doc = "Checks if the value of the field is `SINGLE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_single(&self) -> bool { *self == DDRSEL_A::SINGLE } - #[doc = "Checks if the value of the field is `DOUBLE`"] + #[doc = "`1`"] #[inline(always)] pub fn is_double(&self) -> bool { *self == DDRSEL_A::DOUBLE } } #[doc = "Field `DDRSEL` writer - ULPI data rate"] -pub type DDRSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, DDRSEL_A, O>; -impl<'a, const O: u8> DDRSEL_W<'a, O> { +pub type DDRSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DDRSEL_A>; +impl<'a, REG, const O: u8> DDRSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "`0`"] #[inline(always)] - pub fn single(self) -> &'a mut W { + pub fn single(self) -> &'a mut crate::W { self.variant(DDRSEL_A::SINGLE) } #[doc = "`1`"] #[inline(always)] - pub fn double(self) -> &'a mut W { + pub fn double(self) -> &'a mut crate::W { self.variant(DDRSEL_A::DOUBLE) } } #[doc = "Field `SRPCAP` reader - SRP-capable"] -pub type SRPCAP_R = crate::BitReader; +pub type SRPCAP_R = crate::BitReader; #[doc = "Field `SRPCAP` writer - SRP-capable"] -pub type SRPCAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type SRPCAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HNPCAP` reader - HNP-capable"] -pub type HNPCAP_R = crate::BitReader; +pub type HNPCAP_R = crate::BitReader; #[doc = "Field `HNPCAP` writer - HNP-capable"] -pub type HNPCAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type HNPCAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TRDT` reader - USB turnaround time"] -pub type TRDT_R = crate::FieldReader; +pub type TRDT_R = crate::FieldReader; #[doc = "Field `TRDT` writer - USB turnaround time"] -pub type TRDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GUSBCFG_SPEC, u8, u8, 4, O>; +pub type TRDT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `PHYLPCS` reader - PHY Low-power clock select"] -pub type PHYLPCS_R = crate::BitReader; +pub type PHYLPCS_R = crate::BitReader; #[doc = "Field `PHYLPCS` writer - PHY Low-power clock select"] -pub type PHYLPCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type PHYLPCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIFSLS` reader - ULPI FS/LS select"] -pub type ULPIFSLS_R = crate::BitReader; +pub type ULPIFSLS_R = crate::BitReader; #[doc = "Field `ULPIFSLS` writer - ULPI FS/LS select"] -pub type ULPIFSLS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIFSLS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIAR` reader - ULPI Auto-resume"] -pub type ULPIAR_R = crate::BitReader; +pub type ULPIAR_R = crate::BitReader; #[doc = "Field `ULPIAR` writer - ULPI Auto-resume"] -pub type ULPIAR_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPICSM` reader - ULPI Clock SuspendM"] -pub type ULPICSM_R = crate::BitReader; +pub type ULPICSM_R = crate::BitReader; #[doc = "Field `ULPICSM` writer - ULPI Clock SuspendM"] -pub type ULPICSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPICSM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIEVBUSD` reader - ULPI External VBUS Drive"] -pub type ULPIEVBUSD_R = crate::BitReader; +pub type ULPIEVBUSD_R = crate::BitReader; #[doc = "Field `ULPIEVBUSD` writer - ULPI External VBUS Drive"] -pub type ULPIEVBUSD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIEVBUSD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIEVBUSI` reader - ULPI external VBUS indicator"] -pub type ULPIEVBUSI_R = crate::BitReader; +pub type ULPIEVBUSI_R = crate::BitReader; #[doc = "Field `ULPIEVBUSI` writer - ULPI external VBUS indicator"] -pub type ULPIEVBUSI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIEVBUSI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSDPS` reader - TermSel DLine pulsing selection"] -pub type TSDPS_R = crate::BitReader; +pub type TSDPS_R = crate::BitReader; #[doc = "Field `TSDPS` writer - TermSel DLine pulsing selection"] -pub type TSDPS_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type TSDPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCCI` reader - Indicator complement"] -pub type PCCI_R = crate::BitReader; +pub type PCCI_R = crate::BitReader; #[doc = "Field `PCCI` writer - Indicator complement"] -pub type PCCI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type PCCI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTCI` reader - Indicator pass through"] -pub type PTCI_R = crate::BitReader; +pub type PTCI_R = crate::BitReader; #[doc = "Field `PTCI` writer - Indicator pass through"] -pub type PTCI_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type PTCI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULPIIPD` reader - ULPI interface protect disable"] -pub type ULPIIPD_R = crate::BitReader; +pub type ULPIIPD_R = crate::BitReader; #[doc = "Field `ULPIIPD` writer - ULPI interface protect disable"] -pub type ULPIIPD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type ULPIIPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FHMOD` reader - Forced host mode"] -pub type FHMOD_R = crate::BitReader; +pub type FHMOD_R = crate::BitReader; #[doc = "Field `FHMOD` writer - Forced host mode"] -pub type FHMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type FHMOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FDMOD` reader - Forced peripheral mode"] -pub type FDMOD_R = crate::BitReader; +pub type FDMOD_R = crate::BitReader; #[doc = "Field `FDMOD` writer - Forced peripheral mode"] -pub type FDMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type FDMOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTXPKT` reader - Corrupt Tx packet"] -pub type CTXPKT_R = crate::BitReader; +pub type CTXPKT_R = crate::BitReader; #[doc = "Field `CTXPKT` writer - Corrupt Tx packet"] -pub type CTXPKT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GUSBCFG_SPEC, bool, O>; +pub type CTXPKT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:2 - FS timeout calibration"] #[inline(always)] @@ -464,158 +447,192 @@ impl R { CTXPKT_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GUSBCFG") + .field("tocal", &format_args!("{}", self.tocal().bits())) + .field("phyif", &format_args!("{}", self.phyif().bit())) + .field("phytype", &format_args!("{}", self.phytype().bit())) + .field("fsif", &format_args!("{}", self.fsif().bit())) + .field("physel", &format_args!("{}", self.physel().bit())) + .field("ddrsel", &format_args!("{}", self.ddrsel().bit())) + .field("srpcap", &format_args!("{}", self.srpcap().bit())) + .field("hnpcap", &format_args!("{}", self.hnpcap().bit())) + .field("trdt", &format_args!("{}", self.trdt().bits())) + .field("phylpcs", &format_args!("{}", self.phylpcs().bit())) + .field("ulpifsls", &format_args!("{}", self.ulpifsls().bit())) + .field("ulpiar", &format_args!("{}", self.ulpiar().bit())) + .field("ulpicsm", &format_args!("{}", self.ulpicsm().bit())) + .field("ulpievbusd", &format_args!("{}", self.ulpievbusd().bit())) + .field("ulpievbusi", &format_args!("{}", self.ulpievbusi().bit())) + .field("tsdps", &format_args!("{}", self.tsdps().bit())) + .field("pcci", &format_args!("{}", self.pcci().bit())) + .field("ptci", &format_args!("{}", self.ptci().bit())) + .field("ulpiipd", &format_args!("{}", self.ulpiipd().bit())) + .field("fhmod", &format_args!("{}", self.fhmod().bit())) + .field("fdmod", &format_args!("{}", self.fdmod().bit())) + .field("ctxpkt", &format_args!("{}", self.ctxpkt().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:2 - FS timeout calibration"] #[inline(always)] #[must_use] - pub fn tocal(&mut self) -> TOCAL_W<0> { + pub fn tocal(&mut self) -> TOCAL_W { TOCAL_W::new(self) } #[doc = "Bit 3 - PHY Interface width"] #[inline(always)] #[must_use] - pub fn phyif(&mut self) -> PHYIF_W<3> { + pub fn phyif(&mut self) -> PHYIF_W { PHYIF_W::new(self) } #[doc = "Bit 4 - PHY Type"] #[inline(always)] #[must_use] - pub fn phytype(&mut self) -> PHYTYPE_W<4> { + pub fn phytype(&mut self) -> PHYTYPE_W { PHYTYPE_W::new(self) } #[doc = "Bit 5 - Full speed interface"] #[inline(always)] #[must_use] - pub fn fsif(&mut self) -> FSIF_W<5> { + pub fn fsif(&mut self) -> FSIF_W { FSIF_W::new(self) } #[doc = "Bit 6 - Transceiver select"] #[inline(always)] #[must_use] - pub fn physel(&mut self) -> PHYSEL_W<6> { + pub fn physel(&mut self) -> PHYSEL_W { PHYSEL_W::new(self) } #[doc = "Bit 7 - ULPI data rate"] #[inline(always)] #[must_use] - pub fn ddrsel(&mut self) -> DDRSEL_W<7> { + pub fn ddrsel(&mut self) -> DDRSEL_W { DDRSEL_W::new(self) } #[doc = "Bit 8 - SRP-capable"] #[inline(always)] #[must_use] - pub fn srpcap(&mut self) -> SRPCAP_W<8> { + pub fn srpcap(&mut self) -> SRPCAP_W { SRPCAP_W::new(self) } #[doc = "Bit 9 - HNP-capable"] #[inline(always)] #[must_use] - pub fn hnpcap(&mut self) -> HNPCAP_W<9> { + pub fn hnpcap(&mut self) -> HNPCAP_W { HNPCAP_W::new(self) } #[doc = "Bits 10:13 - USB turnaround time"] #[inline(always)] #[must_use] - pub fn trdt(&mut self) -> TRDT_W<10> { + pub fn trdt(&mut self) -> TRDT_W { TRDT_W::new(self) } #[doc = "Bit 15 - PHY Low-power clock select"] #[inline(always)] #[must_use] - pub fn phylpcs(&mut self) -> PHYLPCS_W<15> { + pub fn phylpcs(&mut self) -> PHYLPCS_W { PHYLPCS_W::new(self) } #[doc = "Bit 17 - ULPI FS/LS select"] #[inline(always)] #[must_use] - pub fn ulpifsls(&mut self) -> ULPIFSLS_W<17> { + pub fn ulpifsls(&mut self) -> ULPIFSLS_W { ULPIFSLS_W::new(self) } #[doc = "Bit 18 - ULPI Auto-resume"] #[inline(always)] #[must_use] - pub fn ulpiar(&mut self) -> ULPIAR_W<18> { + pub fn ulpiar(&mut self) -> ULPIAR_W { ULPIAR_W::new(self) } #[doc = "Bit 19 - ULPI Clock SuspendM"] #[inline(always)] #[must_use] - pub fn ulpicsm(&mut self) -> ULPICSM_W<19> { + pub fn ulpicsm(&mut self) -> ULPICSM_W { ULPICSM_W::new(self) } #[doc = "Bit 20 - ULPI External VBUS Drive"] #[inline(always)] #[must_use] - pub fn ulpievbusd(&mut self) -> ULPIEVBUSD_W<20> { + pub fn ulpievbusd(&mut self) -> ULPIEVBUSD_W { ULPIEVBUSD_W::new(self) } #[doc = "Bit 21 - ULPI external VBUS indicator"] #[inline(always)] #[must_use] - pub fn ulpievbusi(&mut self) -> ULPIEVBUSI_W<21> { + pub fn ulpievbusi(&mut self) -> ULPIEVBUSI_W { ULPIEVBUSI_W::new(self) } #[doc = "Bit 22 - TermSel DLine pulsing selection"] #[inline(always)] #[must_use] - pub fn tsdps(&mut self) -> TSDPS_W<22> { + pub fn tsdps(&mut self) -> TSDPS_W { TSDPS_W::new(self) } #[doc = "Bit 23 - Indicator complement"] #[inline(always)] #[must_use] - pub fn pcci(&mut self) -> PCCI_W<23> { + pub fn pcci(&mut self) -> PCCI_W { PCCI_W::new(self) } #[doc = "Bit 24 - Indicator pass through"] #[inline(always)] #[must_use] - pub fn ptci(&mut self) -> PTCI_W<24> { + pub fn ptci(&mut self) -> PTCI_W { PTCI_W::new(self) } #[doc = "Bit 25 - ULPI interface protect disable"] #[inline(always)] #[must_use] - pub fn ulpiipd(&mut self) -> ULPIIPD_W<25> { + pub fn ulpiipd(&mut self) -> ULPIIPD_W { ULPIIPD_W::new(self) } #[doc = "Bit 29 - Forced host mode"] #[inline(always)] #[must_use] - pub fn fhmod(&mut self) -> FHMOD_W<29> { + pub fn fhmod(&mut self) -> FHMOD_W { FHMOD_W::new(self) } #[doc = "Bit 30 - Forced peripheral mode"] #[inline(always)] #[must_use] - pub fn fdmod(&mut self) -> FDMOD_W<30> { + pub fn fdmod(&mut self) -> FDMOD_W { FDMOD_W::new(self) } #[doc = "Bit 31 - Corrupt Tx packet"] #[inline(always)] #[must_use] - pub fn ctxpkt(&mut self) -> CTXPKT_W<31> { + pub fn ctxpkt(&mut self) -> CTXPKT_W { CTXPKT_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS USB configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gusbcfg](index.html) module"] +#[doc = "OTG_HS USB configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gusbcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gusbcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GUSBCFG_SPEC; impl crate::RegisterSpec for GUSBCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gusbcfg::R](R) reader structure"] -impl crate::Readable for GUSBCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gusbcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`gusbcfg::R`](R) reader structure"] +impl crate::Readable for GUSBCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gusbcfg::W`](W) writer structure"] impl crate::Writable for GUSBCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/hptxfsiz.rs b/crates/bcm2837-lpa/src/usb_otg_global/hptxfsiz.rs index c50a180..cd99421 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/hptxfsiz.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/hptxfsiz.rs @@ -1,47 +1,15 @@ #[doc = "Register `HPTXFSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HPTXFSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PTXSA` reader - Host periodic TxFIFO start address"] -pub type PTXSA_R = crate::FieldReader; +pub type PTXSA_R = crate::FieldReader; #[doc = "Field `PTXSA` writer - Host periodic TxFIFO start address"] -pub type PTXSA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXFSIZ_SPEC, u16, u16, 16, O>; +pub type PTXSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `PTXFD` reader - Host periodic TxFIFO depth"] -pub type PTXFD_R = crate::FieldReader; +pub type PTXFD_R = crate::FieldReader; #[doc = "Field `PTXFD` writer - Host periodic TxFIFO depth"] -pub type PTXFD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXFSIZ_SPEC, u16, u16, 16, O>; +pub type PTXFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Host periodic TxFIFO start address"] #[inline(always)] @@ -54,38 +22,52 @@ impl R { PTXFD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HPTXFSIZ") + .field("ptxsa", &format_args!("{}", self.ptxsa().bits())) + .field("ptxfd", &format_args!("{}", self.ptxfd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Host periodic TxFIFO start address"] #[inline(always)] #[must_use] - pub fn ptxsa(&mut self) -> PTXSA_W<0> { + pub fn ptxsa(&mut self) -> PTXSA_W { PTXSA_W::new(self) } #[doc = "Bits 16:31 - Host periodic TxFIFO depth"] #[inline(always)] #[must_use] - pub fn ptxfd(&mut self) -> PTXFD_W<16> { + pub fn ptxfd(&mut self) -> PTXFD_W { PTXFD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS Host periodic transmit FIFO size register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxfsiz](index.html) module"] +#[doc = "OTG_HS Host periodic transmit FIFO size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxfsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hptxfsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HPTXFSIZ_SPEC; impl crate::RegisterSpec for HPTXFSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hptxfsiz::R](R) reader structure"] -impl crate::Readable for HPTXFSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hptxfsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`hptxfsiz::R`](R) reader structure"] +impl crate::Readable for HPTXFSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hptxfsiz::W`](W) writer structure"] impl crate::Writable for HPTXFSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/hw_config0.rs b/crates/bcm2837-lpa/src/usb_otg_global/hw_config0.rs index 13715b7..93348b4 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/hw_config0.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/hw_config0.rs @@ -1,20 +1,7 @@ #[doc = "Register `HW_CONFIG0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `OPERATING_MODE` reader - Operating Mode"] -pub type OPERATING_MODE_R = crate::FieldReader; +pub type OPERATING_MODE_R = crate::FieldReader; #[doc = "Operating Mode"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -40,10 +27,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for OPERATING_MODE_A { + type Ux = u8; +} impl OPERATING_MODE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(OPERATING_MODE_A::HNP_SRP_CAPABLE), 1 => Some(OPERATING_MODE_A::SRP_ONLY_CAPABLE), @@ -55,44 +45,44 @@ impl OPERATING_MODE_R { _ => None, } } - #[doc = "Checks if the value of the field is `HNP_SRP_CAPABLE`"] + #[doc = "`0`"] #[inline(always)] pub fn is_hnp_srp_capable(&self) -> bool { *self == OPERATING_MODE_A::HNP_SRP_CAPABLE } - #[doc = "Checks if the value of the field is `SRP_ONLY_CAPABLE`"] + #[doc = "`1`"] #[inline(always)] pub fn is_srp_only_capable(&self) -> bool { *self == OPERATING_MODE_A::SRP_ONLY_CAPABLE } - #[doc = "Checks if the value of the field is `NO_HNP_SRP_CAPABLE`"] + #[doc = "`10`"] #[inline(always)] pub fn is_no_hnp_srp_capable(&self) -> bool { *self == OPERATING_MODE_A::NO_HNP_SRP_CAPABLE } - #[doc = "Checks if the value of the field is `SRP_CAPABLE_DEVICE`"] + #[doc = "`11`"] #[inline(always)] pub fn is_srp_capable_device(&self) -> bool { *self == OPERATING_MODE_A::SRP_CAPABLE_DEVICE } - #[doc = "Checks if the value of the field is `NO_SRP_CAPABLE_DEVICE`"] + #[doc = "`100`"] #[inline(always)] pub fn is_no_srp_capable_device(&self) -> bool { *self == OPERATING_MODE_A::NO_SRP_CAPABLE_DEVICE } - #[doc = "Checks if the value of the field is `SRP_CAPABLE_HOST`"] + #[doc = "`101`"] #[inline(always)] pub fn is_srp_capable_host(&self) -> bool { *self == OPERATING_MODE_A::SRP_CAPABLE_HOST } - #[doc = "Checks if the value of the field is `NO_SRP_CAPABLE_HOST`"] + #[doc = "`110`"] #[inline(always)] pub fn is_no_srp_capable_host(&self) -> bool { *self == OPERATING_MODE_A::NO_SRP_CAPABLE_HOST } } #[doc = "Field `ARCHITECTURE` reader - Architecture"] -pub type ARCHITECTURE_R = crate::FieldReader; +pub type ARCHITECTURE_R = crate::FieldReader; #[doc = "Architecture"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -110,10 +100,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for ARCHITECTURE_A { + type Ux = u8; +} impl ARCHITECTURE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(ARCHITECTURE_A::SLAVE_ONLY), 1 => Some(ARCHITECTURE_A::EXTERNAL_DMA), @@ -121,26 +114,26 @@ impl ARCHITECTURE_R { _ => None, } } - #[doc = "Checks if the value of the field is `SLAVE_ONLY`"] + #[doc = "`0`"] #[inline(always)] pub fn is_slave_only(&self) -> bool { *self == ARCHITECTURE_A::SLAVE_ONLY } - #[doc = "Checks if the value of the field is `EXTERNAL_DMA`"] + #[doc = "`1`"] #[inline(always)] pub fn is_external_dma(&self) -> bool { *self == ARCHITECTURE_A::EXTERNAL_DMA } - #[doc = "Checks if the value of the field is `INTERNAL_DMA`"] + #[doc = "`10`"] #[inline(always)] pub fn is_internal_dma(&self) -> bool { *self == ARCHITECTURE_A::INTERNAL_DMA } } #[doc = "Field `POINT_TO_POINT` reader - Point to Point"] -pub type POINT_TO_POINT_R = crate::BitReader; +pub type POINT_TO_POINT_R = crate::BitReader; #[doc = "Field `HIGH_SPEED_PHY` reader - High Speed Physical"] -pub type HIGH_SPEED_PHY_R = crate::FieldReader; +pub type HIGH_SPEED_PHY_R = crate::FieldReader; #[doc = "High Speed Physical"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -160,10 +153,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for HIGH_SPEED_PHY_A { + type Ux = u8; +} impl HIGH_SPEED_PHY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> HIGH_SPEED_PHY_A { + pub const fn variant(&self) -> HIGH_SPEED_PHY_A { match self.bits { 0 => HIGH_SPEED_PHY_A::NOT_SUPPORTED, 1 => HIGH_SPEED_PHY_A::UTMI, @@ -172,29 +168,29 @@ impl HIGH_SPEED_PHY_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NOT_SUPPORTED`"] + #[doc = "`0`"] #[inline(always)] pub fn is_not_supported(&self) -> bool { *self == HIGH_SPEED_PHY_A::NOT_SUPPORTED } - #[doc = "Checks if the value of the field is `UTMI`"] + #[doc = "`1`"] #[inline(always)] pub fn is_utmi(&self) -> bool { *self == HIGH_SPEED_PHY_A::UTMI } - #[doc = "Checks if the value of the field is `ULPI`"] + #[doc = "`10`"] #[inline(always)] pub fn is_ulpi(&self) -> bool { *self == HIGH_SPEED_PHY_A::ULPI } - #[doc = "Checks if the value of the field is `UTMI_ULPI`"] + #[doc = "`11`"] #[inline(always)] pub fn is_utmi_ulpi(&self) -> bool { *self == HIGH_SPEED_PHY_A::UTMI_ULPI } } #[doc = "Field `FULL_SPEED_PHY` reader - Full Speed Physical"] -pub type FULL_SPEED_PHY_R = crate::FieldReader; +pub type FULL_SPEED_PHY_R = crate::FieldReader; #[doc = "Full Speed Physical"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -214,10 +210,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for FULL_SPEED_PHY_A { + type Ux = u8; +} impl FULL_SPEED_PHY_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> FULL_SPEED_PHY_A { + pub const fn variant(&self) -> FULL_SPEED_PHY_A { match self.bits { 0 => FULL_SPEED_PHY_A::PHY0, 1 => FULL_SPEED_PHY_A::DEDICATED, @@ -226,45 +225,45 @@ impl FULL_SPEED_PHY_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `PHY0`"] + #[doc = "`0`"] #[inline(always)] pub fn is_phy0(&self) -> bool { *self == FULL_SPEED_PHY_A::PHY0 } - #[doc = "Checks if the value of the field is `DEDICATED`"] + #[doc = "`1`"] #[inline(always)] pub fn is_dedicated(&self) -> bool { *self == FULL_SPEED_PHY_A::DEDICATED } - #[doc = "Checks if the value of the field is `PHY2`"] + #[doc = "`10`"] #[inline(always)] pub fn is_phy2(&self) -> bool { *self == FULL_SPEED_PHY_A::PHY2 } - #[doc = "Checks if the value of the field is `PHY3`"] + #[doc = "`11`"] #[inline(always)] pub fn is_phy3(&self) -> bool { *self == FULL_SPEED_PHY_A::PHY3 } } #[doc = "Field `DEVICE_END_POINT_COUNT` reader - Device end point count"] -pub type DEVICE_END_POINT_COUNT_R = crate::FieldReader; +pub type DEVICE_END_POINT_COUNT_R = crate::FieldReader; #[doc = "Field `HOST_CHANNEL_COUNT` reader - Host channel count"] -pub type HOST_CHANNEL_COUNT_R = crate::FieldReader; +pub type HOST_CHANNEL_COUNT_R = crate::FieldReader; #[doc = "Field `SUPPORTS_PERIODIC_ENDPOINTS` reader - Supports periodic endpoints"] -pub type SUPPORTS_PERIODIC_ENDPOINTS_R = crate::BitReader; +pub type SUPPORTS_PERIODIC_ENDPOINTS_R = crate::BitReader; #[doc = "Field `DYNAMIC_FIFO` reader - Dynamic FIFO"] -pub type DYNAMIC_FIFO_R = crate::BitReader; +pub type DYNAMIC_FIFO_R = crate::BitReader; #[doc = "Field `MULTI_PROC_INT` reader - Multi proc int"] -pub type MULTI_PROC_INT_R = crate::BitReader; +pub type MULTI_PROC_INT_R = crate::BitReader; #[doc = "Field `NON_PERIODIC_QUEUE_DEPTH` reader - Non periodic queue depth"] -pub type NON_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; +pub type NON_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; #[doc = "Field `HOST_PERIODIC_QUEUE_DEPTH` reader - Host periodic queue depth"] -pub type HOST_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; +pub type HOST_PERIODIC_QUEUE_DEPTH_R = crate::FieldReader; #[doc = "Field `DEVICE_TOKEN_QUEUE_DEPTH` reader - Device token queue depth"] -pub type DEVICE_TOKEN_QUEUE_DEPTH_R = crate::FieldReader; +pub type DEVICE_TOKEN_QUEUE_DEPTH_R = crate::FieldReader; #[doc = "Field `ENABLE_IC_USB` reader - Enable IC USB"] -pub type ENABLE_IC_USB_R = crate::BitReader; +pub type ENABLE_IC_USB_R = crate::BitReader; impl R { #[doc = "Bits 0:2 - Operating Mode"] #[inline(always)] @@ -337,12 +336,77 @@ impl R { ENABLE_IC_USB_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Hardware Config 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hw_config0](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HW_CONFIG0") + .field( + "operating_mode", + &format_args!("{}", self.operating_mode().bits()), + ) + .field( + "architecture", + &format_args!("{}", self.architecture().bits()), + ) + .field( + "point_to_point", + &format_args!("{}", self.point_to_point().bit()), + ) + .field( + "high_speed_phy", + &format_args!("{}", self.high_speed_phy().bits()), + ) + .field( + "full_speed_phy", + &format_args!("{}", self.full_speed_phy().bits()), + ) + .field( + "device_end_point_count", + &format_args!("{}", self.device_end_point_count().bits()), + ) + .field( + "host_channel_count", + &format_args!("{}", self.host_channel_count().bits()), + ) + .field( + "supports_periodic_endpoints", + &format_args!("{}", self.supports_periodic_endpoints().bit()), + ) + .field( + "dynamic_fifo", + &format_args!("{}", self.dynamic_fifo().bit()), + ) + .field( + "multi_proc_int", + &format_args!("{}", self.multi_proc_int().bit()), + ) + .field( + "non_periodic_queue_depth", + &format_args!("{}", self.non_periodic_queue_depth().bits()), + ) + .field( + "host_periodic_queue_depth", + &format_args!("{}", self.host_periodic_queue_depth().bits()), + ) + .field( + "device_token_queue_depth", + &format_args!("{}", self.device_token_queue_depth().bits()), + ) + .field( + "enable_ic_usb", + &format_args!("{}", self.enable_ic_usb().bit()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Hardware Config 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_config0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HW_CONFIG0_SPEC; impl crate::RegisterSpec for HW_CONFIG0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hw_config0::R](R) reader structure"] -impl crate::Readable for HW_CONFIG0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hw_config0::R`](R) reader structure"] +impl crate::Readable for HW_CONFIG0_SPEC {} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/hw_direction.rs b/crates/bcm2837-lpa/src/usb_otg_global/hw_direction.rs index 1ca29d0..3545475 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/hw_direction.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/hw_direction.rs @@ -1,20 +1,7 @@ #[doc = "Register `HW_DIRECTION` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DIRECTION[0-15]` reader - Direction %s"] -pub type DIRECTION_R = crate::FieldReader; +pub type DIRECTION_R = crate::FieldReader; #[doc = "Direction %s"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -32,10 +19,13 @@ impl From for u8 { variant as _ } } +impl crate::FieldSpec for DIRECTION_A { + type Ux = u8; +} impl DIRECTION_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub fn variant(&self) -> Option { + pub const fn variant(&self) -> Option { match self.bits { 0 => Some(DIRECTION_A::BIDIR), 1 => Some(DIRECTION_A::IN), @@ -43,17 +33,17 @@ impl DIRECTION_R { _ => None, } } - #[doc = "Checks if the value of the field is `BIDIR`"] + #[doc = "`0`"] #[inline(always)] pub fn is_bidir(&self) -> bool { *self == DIRECTION_A::BIDIR } - #[doc = "Checks if the value of the field is `IN`"] + #[doc = "`1`"] #[inline(always)] pub fn is_in(&self) -> bool { *self == DIRECTION_A::IN } - #[doc = "Checks if the value of the field is `OUT`"] + #[doc = "`10`"] #[inline(always)] pub fn is_out(&self) -> bool { *self == DIRECTION_A::OUT @@ -146,12 +136,55 @@ impl R { DIRECTION_R::new(((self.bits >> 30) & 3) as u8) } } -#[doc = "Direction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hw_direction](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HW_DIRECTION") + .field("direction0", &format_args!("{}", self.direction0().bits())) + .field("direction1", &format_args!("{}", self.direction1().bits())) + .field("direction2", &format_args!("{}", self.direction2().bits())) + .field("direction3", &format_args!("{}", self.direction3().bits())) + .field("direction4", &format_args!("{}", self.direction4().bits())) + .field("direction5", &format_args!("{}", self.direction5().bits())) + .field("direction6", &format_args!("{}", self.direction6().bits())) + .field("direction7", &format_args!("{}", self.direction7().bits())) + .field("direction8", &format_args!("{}", self.direction8().bits())) + .field("direction9", &format_args!("{}", self.direction9().bits())) + .field( + "direction10", + &format_args!("{}", self.direction10().bits()), + ) + .field( + "direction11", + &format_args!("{}", self.direction11().bits()), + ) + .field( + "direction12", + &format_args!("{}", self.direction12().bits()), + ) + .field( + "direction13", + &format_args!("{}", self.direction13().bits()), + ) + .field( + "direction14", + &format_args!("{}", self.direction14().bits()), + ) + .field( + "direction15", + &format_args!("{}", self.direction15().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_direction::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HW_DIRECTION_SPEC; impl crate::RegisterSpec for HW_DIRECTION_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hw_direction::R](R) reader structure"] -impl crate::Readable for HW_DIRECTION_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hw_direction::R`](R) reader structure"] +impl crate::Readable for HW_DIRECTION_SPEC {} diff --git a/crates/bcm2837-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs b/crates/bcm2837-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs index 8734146..73658ab 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/tx0fsiz_peripheral.rs @@ -1,49 +1,15 @@ #[doc = "Register `TX0FSIZ_Peripheral` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TX0FSIZ_Peripheral` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TX0FSA` reader - Endpoint 0 transmit RAM start address"] -pub type TX0FSA_R = crate::FieldReader; +pub type TX0FSA_R = crate::FieldReader; #[doc = "Field `TX0FSA` writer - Endpoint 0 transmit RAM start address"] -pub type TX0FSA_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, TX0FSIZ_PERIPHERAL_SPEC, u16, u16, 16, O>; +pub type TX0FSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `TX0FD` reader - Endpoint 0 TxFIFO depth"] -pub type TX0FD_R = crate::FieldReader; +pub type TX0FD_R = crate::FieldReader; #[doc = "Field `TX0FD` writer - Endpoint 0 TxFIFO depth"] -pub type TX0FD_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, TX0FSIZ_PERIPHERAL_SPEC, u16, u16, 16, O>; +pub type TX0FD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Endpoint 0 transmit RAM start address"] #[inline(always)] @@ -56,38 +22,52 @@ impl R { TX0FD_R::new(((self.bits >> 16) & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX0FSIZ_Peripheral") + .field("tx0fsa", &format_args!("{}", self.tx0fsa().bits())) + .field("tx0fd", &format_args!("{}", self.tx0fd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Endpoint 0 transmit RAM start address"] #[inline(always)] #[must_use] - pub fn tx0fsa(&mut self) -> TX0FSA_W<0> { + pub fn tx0fsa(&mut self) -> TX0FSA_W { TX0FSA_W::new(self) } #[doc = "Bits 16:31 - Endpoint 0 TxFIFO depth"] #[inline(always)] #[must_use] - pub fn tx0fd(&mut self) -> TX0FD_W<16> { + pub fn tx0fd(&mut self) -> TX0FD_W { TX0FD_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Endpoint 0 transmit FIFO size (peripheral mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx0fsiz_peripheral](index.html) module"] +#[doc = "Endpoint 0 transmit FIFO size (peripheral mode)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx0fsiz_peripheral::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx0fsiz_peripheral::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TX0FSIZ_PERIPHERAL_SPEC; impl crate::RegisterSpec for TX0FSIZ_PERIPHERAL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tx0fsiz_peripheral::R](R) reader structure"] -impl crate::Readable for TX0FSIZ_PERIPHERAL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tx0fsiz_peripheral::W](W) writer structure"] +#[doc = "`read()` method returns [`tx0fsiz_peripheral::R`](R) reader structure"] +impl crate::Readable for TX0FSIZ_PERIPHERAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx0fsiz_peripheral::W`](W) writer structure"] impl crate::Writable for TX0FSIZ_PERIPHERAL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_global/vid.rs b/crates/bcm2837-lpa/src/usb_otg_global/vid.rs index ae468f7..732dd16 100644 --- a/crates/bcm2837-lpa/src/usb_otg_global/vid.rs +++ b/crates/bcm2837-lpa/src/usb_otg_global/vid.rs @@ -1,24 +1,19 @@ #[doc = "Register `VID` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } -#[doc = "OTG_HS vendor ID register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vid](index.html) module"] +#[doc = "OTG_HS vendor ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct VID_SPEC; impl crate::RegisterSpec for VID_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [vid::R](R) reader structure"] -impl crate::Readable for VID_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`vid::R`](R) reader structure"] +impl crate::Readable for VID_SPEC {} diff --git a/crates/bcm2837-lpa/src/usb_otg_host.rs b/crates/bcm2837-lpa/src/usb_otg_host.rs index c2b6fb8..f40a06f 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - OTG_HS host configuration register"] pub hcfg: HCFG, @@ -54,31 +55,38 @@ pub struct RegisterBlock { #[doc = "0x260..0x278 - Host channel %s"] pub host_channel11: HOST_CHANNEL, } -#[doc = "HCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "HCFG (rw) register accessor: OTG_HS host configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcfg`] +module"] pub type HCFG = crate::Reg; #[doc = "OTG_HS host configuration register"] pub mod hcfg; -#[doc = "HFIR (rw) register accessor: an alias for `Reg`"] +#[doc = "HFIR (rw) register accessor: OTG_HS Host frame interval register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hfir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hfir`] +module"] pub type HFIR = crate::Reg; #[doc = "OTG_HS Host frame interval register"] pub mod hfir; -#[doc = "HFNUM (r) register accessor: an alias for `Reg`"] +#[doc = "HFNUM (r) register accessor: OTG_HS host frame number/frame time remaining register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfnum::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hfnum`] +module"] pub type HFNUM = crate::Reg; #[doc = "OTG_HS host frame number/frame time remaining register"] pub mod hfnum; -#[doc = "HPTXSTS (rw) register accessor: an alias for `Reg`"] +#[doc = "HPTXSTS (rw) register accessor: Host periodic transmit FIFO/queue status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxsts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hptxsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hptxsts`] +module"] pub type HPTXSTS = crate::Reg; #[doc = "Host periodic transmit FIFO/queue status register"] pub mod hptxsts; -#[doc = "HAINT (r) register accessor: an alias for `Reg`"] +#[doc = "HAINT (r) register accessor: OTG_HS Host all channels interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haint::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@haint`] +module"] pub type HAINT = crate::Reg; #[doc = "OTG_HS Host all channels interrupt register"] pub mod haint; -#[doc = "HAINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "HAINTMSK (rw) register accessor: OTG_HS host all channels interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`haintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@haintmsk`] +module"] pub type HAINTMSK = crate::Reg; #[doc = "OTG_HS host all channels interrupt mask register"] pub mod haintmsk; -#[doc = "HPRT (rw) register accessor: an alias for `Reg`"] +#[doc = "HPRT (rw) register accessor: OTG_HS host port control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hprt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hprt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hprt`] +module"] pub type HPRT = crate::Reg; #[doc = "OTG_HS host port control and status register"] pub mod hprt; diff --git a/crates/bcm2837-lpa/src/usb_otg_host/haint.rs b/crates/bcm2837-lpa/src/usb_otg_host/haint.rs index 16455f3..fd11584 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/haint.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/haint.rs @@ -1,20 +1,7 @@ #[doc = "Register `HAINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `HAINT` reader - Channel interrupts"] -pub type HAINT_R = crate::FieldReader; +pub type HAINT_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - Channel interrupts"] #[inline(always)] @@ -22,15 +9,25 @@ impl R { HAINT_R::new((self.bits & 0xffff) as u16) } } -#[doc = "OTG_HS Host all channels interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haint](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HAINT") + .field("haint", &format_args!("{}", self.haint().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS Host all channels interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haint::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HAINT_SPEC; impl crate::RegisterSpec for HAINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [haint::R](R) reader structure"] -impl crate::Readable for HAINT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`haint::R`](R) reader structure"] +impl crate::Readable for HAINT_SPEC {} #[doc = "`reset()` method sets HAINT to value 0"] impl crate::Resettable for HAINT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/crates/bcm2837-lpa/src/usb_otg_host/haintmsk.rs b/crates/bcm2837-lpa/src/usb_otg_host/haintmsk.rs index 69df5e9..f820459 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/haintmsk.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/haintmsk.rs @@ -1,43 +1,11 @@ #[doc = "Register `HAINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HAINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HAINTM` reader - Channel interrupt mask"] -pub type HAINTM_R = crate::FieldReader; +pub type HAINTM_R = crate::FieldReader; #[doc = "Field `HAINTM` writer - Channel interrupt mask"] -pub type HAINTM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HAINTMSK_SPEC, u16, u16, 16, O>; +pub type HAINTM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Channel interrupt mask"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { HAINTM_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HAINTMSK") + .field("haintm", &format_args!("{}", self.haintm().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Channel interrupt mask"] #[inline(always)] #[must_use] - pub fn haintm(&mut self) -> HAINTM_W<0> { + pub fn haintm(&mut self) -> HAINTM_W { HAINTM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS host all channels interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haintmsk](index.html) module"] +#[doc = "OTG_HS host all channels interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`haintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HAINTMSK_SPEC; impl crate::RegisterSpec for HAINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [haintmsk::R](R) reader structure"] -impl crate::Readable for HAINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [haintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`haintmsk::R`](R) reader structure"] +impl crate::Readable for HAINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`haintmsk::W`](W) writer structure"] impl crate::Writable for HAINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_host/hcfg.rs b/crates/bcm2837-lpa/src/usb_otg_host/hcfg.rs index 17f4b01..af6795d 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/hcfg.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/hcfg.rs @@ -1,45 +1,13 @@ #[doc = "Register `HCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSLSPCS` reader - FS/LS PHY clock select"] -pub type FSLSPCS_R = crate::FieldReader; +pub type FSLSPCS_R = crate::FieldReader; #[doc = "Field `FSLSPCS` writer - FS/LS PHY clock select"] -pub type FSLSPCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCFG_SPEC, u8, u8, 2, O>; +pub type FSLSPCS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `FSLSS` reader - FS- and LS-only support"] -pub type FSLSS_R = crate::BitReader; +pub type FSLSS_R = crate::BitReader; impl R { #[doc = "Bits 0:1 - FS/LS PHY clock select"] #[inline(always)] @@ -52,32 +20,46 @@ impl R { FSLSS_R::new(((self.bits >> 2) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCFG") + .field("fslspcs", &format_args!("{}", self.fslspcs().bits())) + .field("fslss", &format_args!("{}", self.fslss().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:1 - FS/LS PHY clock select"] #[inline(always)] #[must_use] - pub fn fslspcs(&mut self) -> FSLSPCS_W<0> { + pub fn fslspcs(&mut self) -> FSLSPCS_W { FSLSPCS_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS host configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcfg](index.html) module"] +#[doc = "OTG_HS host configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCFG_SPEC; impl crate::RegisterSpec for HCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcfg::R](R) reader structure"] -impl crate::Readable for HCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`hcfg::R`](R) reader structure"] +impl crate::Readable for HCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcfg::W`](W) writer structure"] impl crate::Writable for HCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_host/hfir.rs b/crates/bcm2837-lpa/src/usb_otg_host/hfir.rs index 9182ff2..d373916 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/hfir.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/hfir.rs @@ -1,43 +1,11 @@ #[doc = "Register `HFIR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HFIR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FRIVL` reader - Frame interval"] -pub type FRIVL_R = crate::FieldReader; +pub type FRIVL_R = crate::FieldReader; #[doc = "Field `FRIVL` writer - Frame interval"] -pub type FRIVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HFIR_SPEC, u16, u16, 16, O>; +pub type FRIVL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Frame interval"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { FRIVL_R::new((self.bits & 0xffff) as u16) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HFIR") + .field("frivl", &format_args!("{}", self.frivl().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Frame interval"] #[inline(always)] #[must_use] - pub fn frivl(&mut self) -> FRIVL_W<0> { + pub fn frivl(&mut self) -> FRIVL_W { FRIVL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS Host frame interval register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfir](index.html) module"] +#[doc = "OTG_HS Host frame interval register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hfir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HFIR_SPEC; impl crate::RegisterSpec for HFIR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hfir::R](R) reader structure"] -impl crate::Readable for HFIR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hfir::W](W) writer structure"] +#[doc = "`read()` method returns [`hfir::R`](R) reader structure"] +impl crate::Readable for HFIR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hfir::W`](W) writer structure"] impl crate::Writable for HFIR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_host/hfnum.rs b/crates/bcm2837-lpa/src/usb_otg_host/hfnum.rs index 0df982a..5bb48e9 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/hfnum.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/hfnum.rs @@ -1,22 +1,9 @@ #[doc = "Register `HFNUM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FRNUM` reader - Frame number"] -pub type FRNUM_R = crate::FieldReader; +pub type FRNUM_R = crate::FieldReader; #[doc = "Field `FTREM` reader - Frame time remaining"] -pub type FTREM_R = crate::FieldReader; +pub type FTREM_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - Frame number"] #[inline(always)] @@ -29,15 +16,26 @@ impl R { FTREM_R::new(((self.bits >> 16) & 0xffff) as u16) } } -#[doc = "OTG_HS host frame number/frame time remaining register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfnum](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HFNUM") + .field("frnum", &format_args!("{}", self.frnum().bits())) + .field("ftrem", &format_args!("{}", self.ftrem().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "OTG_HS host frame number/frame time remaining register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfnum::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HFNUM_SPEC; impl crate::RegisterSpec for HFNUM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hfnum::R](R) reader structure"] -impl crate::Readable for HFNUM_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hfnum::R`](R) reader structure"] +impl crate::Readable for HFNUM_SPEC {} #[doc = "`reset()` method sets HFNUM to value 0x3fff"] impl crate::Resettable for HFNUM_SPEC { const RESET_VALUE: Self::Ux = 0x3fff; diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel.rs index ee4a815..54d36d3 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/host_channel.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct HOST_CHANNEL { #[doc = "0x00 - Characteristics register"] pub hcchar: HCCHAR, @@ -14,27 +15,33 @@ pub struct HOST_CHANNEL { #[doc = "0x14 - DMA address"] pub hcdma: HCDMA, } -#[doc = "HCCHAR (rw) register accessor: an alias for `Reg`"] +#[doc = "HCCHAR (rw) register accessor: Characteristics register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcchar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcchar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcchar`] +module"] pub type HCCHAR = crate::Reg; #[doc = "Characteristics register"] pub mod hcchar; -#[doc = "HCSPLT (rw) register accessor: an alias for `Reg`"] +#[doc = "HCSPLT (rw) register accessor: Split control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcsplt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcsplt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcsplt`] +module"] pub type HCSPLT = crate::Reg; #[doc = "Split control register"] pub mod hcsplt; -#[doc = "HCINT (rw) register accessor: an alias for `Reg`"] +#[doc = "HCINT (rw) register accessor: Interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcint`] +module"] pub type HCINT = crate::Reg; #[doc = "Interrupt register"] pub mod hcint; -#[doc = "HCINTMSK (rw) register accessor: an alias for `Reg`"] +#[doc = "HCINTMSK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcintmsk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcintmsk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcintmsk`] +module"] pub type HCINTMSK = crate::Reg; #[doc = "Interrupt mask"] pub mod hcintmsk; -#[doc = "HCTSIZ (rw) register accessor: an alias for `Reg`"] +#[doc = "HCTSIZ (rw) register accessor: Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hctsiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hctsiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hctsiz`] +module"] pub type HCTSIZ = crate::Reg; #[doc = "Transfer size"] pub mod hctsiz; -#[doc = "HCDMA (rw) register accessor: an alias for `Reg`"] +#[doc = "HCDMA (rw) register accessor: DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcdma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcdma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcdma`] +module"] pub type HCDMA = crate::Reg; #[doc = "DMA address"] pub mod hcdma; diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcchar.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcchar.rs index d73f560..4bc5c53 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcchar.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcchar.rs @@ -1,79 +1,47 @@ #[doc = "Register `HCCHAR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCCHAR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MPSIZ` reader - Maximum packet size"] -pub type MPSIZ_R = crate::FieldReader; +pub type MPSIZ_R = crate::FieldReader; #[doc = "Field `MPSIZ` writer - Maximum packet size"] -pub type MPSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u16, u16, 11, O>; +pub type MPSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 11, O, u16>; #[doc = "Field `EPNUM` reader - Endpoint number"] -pub type EPNUM_R = crate::FieldReader; +pub type EPNUM_R = crate::FieldReader; #[doc = "Field `EPNUM` writer - Endpoint number"] -pub type EPNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 4, O>; +pub type EPNUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `EPDIR` reader - Endpoint direction"] -pub type EPDIR_R = crate::BitReader; +pub type EPDIR_R = crate::BitReader; #[doc = "Field `EPDIR` writer - Endpoint direction"] -pub type EPDIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type EPDIR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LSDEV` reader - Low-speed device"] -pub type LSDEV_R = crate::BitReader; +pub type LSDEV_R = crate::BitReader; #[doc = "Field `LSDEV` writer - Low-speed device"] -pub type LSDEV_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type LSDEV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPTYP` reader - Endpoint type"] -pub type EPTYP_R = crate::FieldReader; +pub type EPTYP_R = crate::FieldReader; #[doc = "Field `EPTYP` writer - Endpoint type"] -pub type EPTYP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 2, O>; +pub type EPTYP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `MC` reader - Multi Count (MC) / Error Count (EC)"] -pub type MC_R = crate::FieldReader; +pub type MC_R = crate::FieldReader; #[doc = "Field `MC` writer - Multi Count (MC) / Error Count (EC)"] -pub type MC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 2, O>; +pub type MC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `DAD` reader - Device address"] -pub type DAD_R = crate::FieldReader; +pub type DAD_R = crate::FieldReader; #[doc = "Field `DAD` writer - Device address"] -pub type DAD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCCHAR_SPEC, u8, u8, 7, O>; +pub type DAD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `ODDFRM` reader - Odd frame"] -pub type ODDFRM_R = crate::BitReader; +pub type ODDFRM_R = crate::BitReader; #[doc = "Field `ODDFRM` writer - Odd frame"] -pub type ODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type ODDFRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHDIS` reader - Channel disable"] -pub type CHDIS_R = crate::BitReader; +pub type CHDIS_R = crate::BitReader; #[doc = "Field `CHDIS` writer - Channel disable"] -pub type CHDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type CHDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHENA` reader - Channel enable"] -pub type CHENA_R = crate::BitReader; +pub type CHENA_R = crate::BitReader; #[doc = "Field `CHENA` writer - Channel enable"] -pub type CHENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCCHAR_SPEC, bool, O>; +pub type CHENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] @@ -126,86 +94,108 @@ impl R { CHENA_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCCHAR") + .field("mpsiz", &format_args!("{}", self.mpsiz().bits())) + .field("epnum", &format_args!("{}", self.epnum().bits())) + .field("epdir", &format_args!("{}", self.epdir().bit())) + .field("lsdev", &format_args!("{}", self.lsdev().bit())) + .field("eptyp", &format_args!("{}", self.eptyp().bits())) + .field("mc", &format_args!("{}", self.mc().bits())) + .field("dad", &format_args!("{}", self.dad().bits())) + .field("oddfrm", &format_args!("{}", self.oddfrm().bit())) + .field("chdis", &format_args!("{}", self.chdis().bit())) + .field("chena", &format_args!("{}", self.chena().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] #[must_use] - pub fn mpsiz(&mut self) -> MPSIZ_W<0> { + pub fn mpsiz(&mut self) -> MPSIZ_W { MPSIZ_W::new(self) } #[doc = "Bits 11:14 - Endpoint number"] #[inline(always)] #[must_use] - pub fn epnum(&mut self) -> EPNUM_W<11> { + pub fn epnum(&mut self) -> EPNUM_W { EPNUM_W::new(self) } #[doc = "Bit 15 - Endpoint direction"] #[inline(always)] #[must_use] - pub fn epdir(&mut self) -> EPDIR_W<15> { + pub fn epdir(&mut self) -> EPDIR_W { EPDIR_W::new(self) } #[doc = "Bit 17 - Low-speed device"] #[inline(always)] #[must_use] - pub fn lsdev(&mut self) -> LSDEV_W<17> { + pub fn lsdev(&mut self) -> LSDEV_W { LSDEV_W::new(self) } #[doc = "Bits 18:19 - Endpoint type"] #[inline(always)] #[must_use] - pub fn eptyp(&mut self) -> EPTYP_W<18> { + pub fn eptyp(&mut self) -> EPTYP_W { EPTYP_W::new(self) } #[doc = "Bits 20:21 - Multi Count (MC) / Error Count (EC)"] #[inline(always)] #[must_use] - pub fn mc(&mut self) -> MC_W<20> { + pub fn mc(&mut self) -> MC_W { MC_W::new(self) } #[doc = "Bits 22:28 - Device address"] #[inline(always)] #[must_use] - pub fn dad(&mut self) -> DAD_W<22> { + pub fn dad(&mut self) -> DAD_W { DAD_W::new(self) } #[doc = "Bit 29 - Odd frame"] #[inline(always)] #[must_use] - pub fn oddfrm(&mut self) -> ODDFRM_W<29> { + pub fn oddfrm(&mut self) -> ODDFRM_W { ODDFRM_W::new(self) } #[doc = "Bit 30 - Channel disable"] #[inline(always)] #[must_use] - pub fn chdis(&mut self) -> CHDIS_W<30> { + pub fn chdis(&mut self) -> CHDIS_W { CHDIS_W::new(self) } #[doc = "Bit 31 - Channel enable"] #[inline(always)] #[must_use] - pub fn chena(&mut self) -> CHENA_W<31> { + pub fn chena(&mut self) -> CHENA_W { CHENA_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Characteristics register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcchar](index.html) module"] +#[doc = "Characteristics register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcchar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcchar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCCHAR_SPEC; impl crate::RegisterSpec for HCCHAR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcchar::R](R) reader structure"] -impl crate::Readable for HCCHAR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcchar::W](W) writer structure"] +#[doc = "`read()` method returns [`hcchar::R`](R) reader structure"] +impl crate::Readable for HCCHAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcchar::W`](W) writer structure"] impl crate::Writable for HCCHAR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcdma.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcdma.rs index bfcef2a..49ce1a2 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcdma.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcdma.rs @@ -1,43 +1,11 @@ #[doc = "Register `HCDMA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCDMA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMAADDR` reader - DMA address"] -pub type DMAADDR_R = crate::FieldReader; +pub type DMAADDR_R = crate::FieldReader; #[doc = "Field `DMAADDR` writer - DMA address"] -pub type DMAADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCDMA_SPEC, u32, u32, 32, O>; +pub type DMAADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { DMAADDR_R::new(self.bits) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCDMA") + .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:31 - DMA address"] #[inline(always)] #[must_use] - pub fn dmaaddr(&mut self) -> DMAADDR_W<0> { + pub fn dmaaddr(&mut self) -> DMAADDR_W { DMAADDR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcdma](index.html) module"] +#[doc = "DMA address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcdma::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcdma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCDMA_SPEC; impl crate::RegisterSpec for HCDMA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcdma::R](R) reader structure"] -impl crate::Readable for HCDMA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcdma::W](W) writer structure"] +#[doc = "`read()` method returns [`hcdma::R`](R) reader structure"] +impl crate::Readable for HCDMA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcdma::W`](W) writer structure"] impl crate::Writable for HCDMA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcint.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcint.rs index a8ef9ea..0fd949e 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcint.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcint.rs @@ -1,83 +1,51 @@ #[doc = "Register `HCINT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCINT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRC` reader - Transfer completed"] -pub type XFRC_R = crate::BitReader; +pub type XFRC_R = crate::BitReader; #[doc = "Field `XFRC` writer - Transfer completed"] -pub type XFRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type XFRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHH` reader - Channel halted"] -pub type CHH_R = crate::BitReader; +pub type CHH_R = crate::BitReader; #[doc = "Field `CHH` writer - Channel halted"] -pub type CHH_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type CHH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AHBERR` reader - AHB error"] -pub type AHBERR_R = crate::BitReader; +pub type AHBERR_R = crate::BitReader; #[doc = "Field `AHBERR` writer - AHB error"] -pub type AHBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type AHBERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALL` reader - STALL response received interrupt"] -pub type STALL_R = crate::BitReader; +pub type STALL_R = crate::BitReader; #[doc = "Field `STALL` writer - STALL response received interrupt"] -pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAK` reader - NAK response received interrupt"] -pub type NAK_R = crate::BitReader; +pub type NAK_R = crate::BitReader; #[doc = "Field `NAK` writer - NAK response received interrupt"] -pub type NAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type NAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACK` reader - ACK response received/transmitted interrupt"] -pub type ACK_R = crate::BitReader; +pub type ACK_R = crate::BitReader; #[doc = "Field `ACK` writer - ACK response received/transmitted interrupt"] -pub type ACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type ACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYET` reader - Response received interrupt"] -pub type NYET_R = crate::BitReader; +pub type NYET_R = crate::BitReader; #[doc = "Field `NYET` writer - Response received interrupt"] -pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type NYET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXERR` reader - Transaction error"] -pub type TXERR_R = crate::BitReader; +pub type TXERR_R = crate::BitReader; #[doc = "Field `TXERR` writer - Transaction error"] -pub type TXERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type TXERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BBERR` reader - Babble error"] -pub type BBERR_R = crate::BitReader; +pub type BBERR_R = crate::BitReader; #[doc = "Field `BBERR` writer - Babble error"] -pub type BBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type BBERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRMOR` reader - Frame overrun"] -pub type FRMOR_R = crate::BitReader; +pub type FRMOR_R = crate::BitReader; #[doc = "Field `FRMOR` writer - Frame overrun"] -pub type FRMOR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type FRMOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTERR` reader - Data toggle error"] -pub type DTERR_R = crate::BitReader; +pub type DTERR_R = crate::BitReader; #[doc = "Field `DTERR` writer - Data toggle error"] -pub type DTERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINT_SPEC, bool, O>; +pub type DTERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed"] #[inline(always)] @@ -135,92 +103,115 @@ impl R { DTERR_R::new(((self.bits >> 10) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCINT") + .field("xfrc", &format_args!("{}", self.xfrc().bit())) + .field("chh", &format_args!("{}", self.chh().bit())) + .field("ahberr", &format_args!("{}", self.ahberr().bit())) + .field("stall", &format_args!("{}", self.stall().bit())) + .field("nak", &format_args!("{}", self.nak().bit())) + .field("ack", &format_args!("{}", self.ack().bit())) + .field("nyet", &format_args!("{}", self.nyet().bit())) + .field("txerr", &format_args!("{}", self.txerr().bit())) + .field("bberr", &format_args!("{}", self.bberr().bit())) + .field("frmor", &format_args!("{}", self.frmor().bit())) + .field("dterr", &format_args!("{}", self.dterr().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed"] #[inline(always)] #[must_use] - pub fn xfrc(&mut self) -> XFRC_W<0> { + pub fn xfrc(&mut self) -> XFRC_W { XFRC_W::new(self) } #[doc = "Bit 1 - Channel halted"] #[inline(always)] #[must_use] - pub fn chh(&mut self) -> CHH_W<1> { + pub fn chh(&mut self) -> CHH_W { CHH_W::new(self) } #[doc = "Bit 2 - AHB error"] #[inline(always)] #[must_use] - pub fn ahberr(&mut self) -> AHBERR_W<2> { + pub fn ahberr(&mut self) -> AHBERR_W { AHBERR_W::new(self) } #[doc = "Bit 3 - STALL response received interrupt"] #[inline(always)] #[must_use] - pub fn stall(&mut self) -> STALL_W<3> { + pub fn stall(&mut self) -> STALL_W { STALL_W::new(self) } #[doc = "Bit 4 - NAK response received interrupt"] #[inline(always)] #[must_use] - pub fn nak(&mut self) -> NAK_W<4> { + pub fn nak(&mut self) -> NAK_W { NAK_W::new(self) } #[doc = "Bit 5 - ACK response received/transmitted interrupt"] #[inline(always)] #[must_use] - pub fn ack(&mut self) -> ACK_W<5> { + pub fn ack(&mut self) -> ACK_W { ACK_W::new(self) } #[doc = "Bit 6 - Response received interrupt"] #[inline(always)] #[must_use] - pub fn nyet(&mut self) -> NYET_W<6> { + pub fn nyet(&mut self) -> NYET_W { NYET_W::new(self) } #[doc = "Bit 7 - Transaction error"] #[inline(always)] #[must_use] - pub fn txerr(&mut self) -> TXERR_W<7> { + pub fn txerr(&mut self) -> TXERR_W { TXERR_W::new(self) } #[doc = "Bit 8 - Babble error"] #[inline(always)] #[must_use] - pub fn bberr(&mut self) -> BBERR_W<8> { + pub fn bberr(&mut self) -> BBERR_W { BBERR_W::new(self) } #[doc = "Bit 9 - Frame overrun"] #[inline(always)] #[must_use] - pub fn frmor(&mut self) -> FRMOR_W<9> { + pub fn frmor(&mut self) -> FRMOR_W { FRMOR_W::new(self) } #[doc = "Bit 10 - Data toggle error"] #[inline(always)] #[must_use] - pub fn dterr(&mut self) -> DTERR_W<10> { + pub fn dterr(&mut self) -> DTERR_W { DTERR_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcint](index.html) module"] +#[doc = "Interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCINT_SPEC; impl crate::RegisterSpec for HCINT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcint::R](R) reader structure"] -impl crate::Readable for HCINT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcint::W](W) writer structure"] +#[doc = "`read()` method returns [`hcint::R`](R) reader structure"] +impl crate::Readable for HCINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcint::W`](W) writer structure"] impl crate::Writable for HCINT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcintmsk.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcintmsk.rs index e158cb4..03aa41c 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcintmsk.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcintmsk.rs @@ -1,83 +1,51 @@ #[doc = "Register `HCINTMSK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCINTMSK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRCM` reader - Transfer completed mask"] -pub type XFRCM_R = crate::BitReader; +pub type XFRCM_R = crate::BitReader; #[doc = "Field `XFRCM` writer - Transfer completed mask"] -pub type XFRCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type XFRCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHHM` reader - Channel halted mask"] -pub type CHHM_R = crate::BitReader; +pub type CHHM_R = crate::BitReader; #[doc = "Field `CHHM` writer - Channel halted mask"] -pub type CHHM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type CHHM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AHBERR` reader - AHB error"] -pub type AHBERR_R = crate::BitReader; +pub type AHBERR_R = crate::BitReader; #[doc = "Field `AHBERR` writer - AHB error"] -pub type AHBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type AHBERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLM` reader - STALL response received interrupt mask"] -pub type STALLM_R = crate::BitReader; +pub type STALLM_R = crate::BitReader; #[doc = "Field `STALLM` writer - STALL response received interrupt mask"] -pub type STALLM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type STALLM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKM` reader - NAK response received interrupt mask"] -pub type NAKM_R = crate::BitReader; +pub type NAKM_R = crate::BitReader; #[doc = "Field `NAKM` writer - NAK response received interrupt mask"] -pub type NAKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type NAKM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACKM` reader - ACK response received/transmitted interrupt mask"] -pub type ACKM_R = crate::BitReader; +pub type ACKM_R = crate::BitReader; #[doc = "Field `ACKM` writer - ACK response received/transmitted interrupt mask"] -pub type ACKM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type ACKM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYET` reader - response received interrupt mask"] -pub type NYET_R = crate::BitReader; +pub type NYET_R = crate::BitReader; #[doc = "Field `NYET` writer - response received interrupt mask"] -pub type NYET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type NYET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXERRM` reader - Transaction error mask"] -pub type TXERRM_R = crate::BitReader; +pub type TXERRM_R = crate::BitReader; #[doc = "Field `TXERRM` writer - Transaction error mask"] -pub type TXERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type TXERRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BBERRM` reader - Babble error mask"] -pub type BBERRM_R = crate::BitReader; +pub type BBERRM_R = crate::BitReader; #[doc = "Field `BBERRM` writer - Babble error mask"] -pub type BBERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type BBERRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRMORM` reader - Frame overrun mask"] -pub type FRMORM_R = crate::BitReader; +pub type FRMORM_R = crate::BitReader; #[doc = "Field `FRMORM` writer - Frame overrun mask"] -pub type FRMORM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type FRMORM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTERRM` reader - Data toggle error mask"] -pub type DTERRM_R = crate::BitReader; +pub type DTERRM_R = crate::BitReader; #[doc = "Field `DTERRM` writer - Data toggle error mask"] -pub type DTERRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCINTMSK_SPEC, bool, O>; +pub type DTERRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer completed mask"] #[inline(always)] @@ -135,92 +103,115 @@ impl R { DTERRM_R::new(((self.bits >> 10) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCINTMSK") + .field("xfrcm", &format_args!("{}", self.xfrcm().bit())) + .field("chhm", &format_args!("{}", self.chhm().bit())) + .field("ahberr", &format_args!("{}", self.ahberr().bit())) + .field("stallm", &format_args!("{}", self.stallm().bit())) + .field("nakm", &format_args!("{}", self.nakm().bit())) + .field("ackm", &format_args!("{}", self.ackm().bit())) + .field("nyet", &format_args!("{}", self.nyet().bit())) + .field("txerrm", &format_args!("{}", self.txerrm().bit())) + .field("bberrm", &format_args!("{}", self.bberrm().bit())) + .field("frmorm", &format_args!("{}", self.frmorm().bit())) + .field("dterrm", &format_args!("{}", self.dterrm().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Transfer completed mask"] #[inline(always)] #[must_use] - pub fn xfrcm(&mut self) -> XFRCM_W<0> { + pub fn xfrcm(&mut self) -> XFRCM_W { XFRCM_W::new(self) } #[doc = "Bit 1 - Channel halted mask"] #[inline(always)] #[must_use] - pub fn chhm(&mut self) -> CHHM_W<1> { + pub fn chhm(&mut self) -> CHHM_W { CHHM_W::new(self) } #[doc = "Bit 2 - AHB error"] #[inline(always)] #[must_use] - pub fn ahberr(&mut self) -> AHBERR_W<2> { + pub fn ahberr(&mut self) -> AHBERR_W { AHBERR_W::new(self) } #[doc = "Bit 3 - STALL response received interrupt mask"] #[inline(always)] #[must_use] - pub fn stallm(&mut self) -> STALLM_W<3> { + pub fn stallm(&mut self) -> STALLM_W { STALLM_W::new(self) } #[doc = "Bit 4 - NAK response received interrupt mask"] #[inline(always)] #[must_use] - pub fn nakm(&mut self) -> NAKM_W<4> { + pub fn nakm(&mut self) -> NAKM_W { NAKM_W::new(self) } #[doc = "Bit 5 - ACK response received/transmitted interrupt mask"] #[inline(always)] #[must_use] - pub fn ackm(&mut self) -> ACKM_W<5> { + pub fn ackm(&mut self) -> ACKM_W { ACKM_W::new(self) } #[doc = "Bit 6 - response received interrupt mask"] #[inline(always)] #[must_use] - pub fn nyet(&mut self) -> NYET_W<6> { + pub fn nyet(&mut self) -> NYET_W { NYET_W::new(self) } #[doc = "Bit 7 - Transaction error mask"] #[inline(always)] #[must_use] - pub fn txerrm(&mut self) -> TXERRM_W<7> { + pub fn txerrm(&mut self) -> TXERRM_W { TXERRM_W::new(self) } #[doc = "Bit 8 - Babble error mask"] #[inline(always)] #[must_use] - pub fn bberrm(&mut self) -> BBERRM_W<8> { + pub fn bberrm(&mut self) -> BBERRM_W { BBERRM_W::new(self) } #[doc = "Bit 9 - Frame overrun mask"] #[inline(always)] #[must_use] - pub fn frmorm(&mut self) -> FRMORM_W<9> { + pub fn frmorm(&mut self) -> FRMORM_W { FRMORM_W::new(self) } #[doc = "Bit 10 - Data toggle error mask"] #[inline(always)] #[must_use] - pub fn dterrm(&mut self) -> DTERRM_W<10> { + pub fn dterrm(&mut self) -> DTERRM_W { DTERRM_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcintmsk](index.html) module"] +#[doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcintmsk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcintmsk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCINTMSK_SPEC; impl crate::RegisterSpec for HCINTMSK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcintmsk::R](R) reader structure"] -impl crate::Readable for HCINTMSK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcintmsk::W](W) writer structure"] +#[doc = "`read()` method returns [`hcintmsk::R`](R) reader structure"] +impl crate::Readable for HCINTMSK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcintmsk::W`](W) writer structure"] impl crate::Writable for HCINTMSK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcsplt.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcsplt.rs index b20ca79..dfc4fa0 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcsplt.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hcsplt.rs @@ -1,59 +1,27 @@ #[doc = "Register `HCSPLT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCSPLT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PRTADDR` reader - Port address"] -pub type PRTADDR_R = crate::FieldReader; +pub type PRTADDR_R = crate::FieldReader; #[doc = "Field `PRTADDR` writer - Port address"] -pub type PRTADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 7, O>; +pub type PRTADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `HUBADDR` reader - Hub address"] -pub type HUBADDR_R = crate::FieldReader; +pub type HUBADDR_R = crate::FieldReader; #[doc = "Field `HUBADDR` writer - Hub address"] -pub type HUBADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 7, O>; +pub type HUBADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `XACTPOS` reader - XACTPOS"] -pub type XACTPOS_R = crate::FieldReader; +pub type XACTPOS_R = crate::FieldReader; #[doc = "Field `XACTPOS` writer - XACTPOS"] -pub type XACTPOS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCSPLT_SPEC, u8, u8, 2, O>; +pub type XACTPOS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `COMPLSPLT` reader - Do complete split"] -pub type COMPLSPLT_R = crate::BitReader; +pub type COMPLSPLT_R = crate::BitReader; #[doc = "Field `COMPLSPLT` writer - Do complete split"] -pub type COMPLSPLT_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCSPLT_SPEC, bool, O>; +pub type COMPLSPLT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPLITEN` reader - Split enable"] -pub type SPLITEN_R = crate::BitReader; +pub type SPLITEN_R = crate::BitReader; #[doc = "Field `SPLITEN` writer - Split enable"] -pub type SPLITEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCSPLT_SPEC, bool, O>; +pub type SPLITEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - Port address"] #[inline(always)] @@ -81,56 +49,73 @@ impl R { SPLITEN_R::new(((self.bits >> 31) & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCSPLT") + .field("prtaddr", &format_args!("{}", self.prtaddr().bits())) + .field("hubaddr", &format_args!("{}", self.hubaddr().bits())) + .field("xactpos", &format_args!("{}", self.xactpos().bits())) + .field("complsplt", &format_args!("{}", self.complsplt().bit())) + .field("spliten", &format_args!("{}", self.spliten().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:6 - Port address"] #[inline(always)] #[must_use] - pub fn prtaddr(&mut self) -> PRTADDR_W<0> { + pub fn prtaddr(&mut self) -> PRTADDR_W { PRTADDR_W::new(self) } #[doc = "Bits 7:13 - Hub address"] #[inline(always)] #[must_use] - pub fn hubaddr(&mut self) -> HUBADDR_W<7> { + pub fn hubaddr(&mut self) -> HUBADDR_W { HUBADDR_W::new(self) } #[doc = "Bits 14:15 - XACTPOS"] #[inline(always)] #[must_use] - pub fn xactpos(&mut self) -> XACTPOS_W<14> { + pub fn xactpos(&mut self) -> XACTPOS_W { XACTPOS_W::new(self) } #[doc = "Bit 16 - Do complete split"] #[inline(always)] #[must_use] - pub fn complsplt(&mut self) -> COMPLSPLT_W<16> { + pub fn complsplt(&mut self) -> COMPLSPLT_W { COMPLSPLT_W::new(self) } #[doc = "Bit 31 - Split enable"] #[inline(always)] #[must_use] - pub fn spliten(&mut self) -> SPLITEN_W<31> { + pub fn spliten(&mut self) -> SPLITEN_W { SPLITEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Split control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcsplt](index.html) module"] +#[doc = "Split control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcsplt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcsplt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCSPLT_SPEC; impl crate::RegisterSpec for HCSPLT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcsplt::R](R) reader structure"] -impl crate::Readable for HCSPLT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcsplt::W](W) writer structure"] +#[doc = "`read()` method returns [`hcsplt::R`](R) reader structure"] +impl crate::Readable for HCSPLT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcsplt::W`](W) writer structure"] impl crate::Writable for HCSPLT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hctsiz.rs b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hctsiz.rs index a7361fd..ebfe51b 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hctsiz.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/host_channel/hctsiz.rs @@ -1,51 +1,19 @@ #[doc = "Register `HCTSIZ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCTSIZ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XFRSIZ` reader - Transfer size"] -pub type XFRSIZ_R = crate::FieldReader; +pub type XFRSIZ_R = crate::FieldReader; #[doc = "Field `XFRSIZ` writer - Transfer size"] -pub type XFRSIZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u32, u32, 19, O>; +pub type XFRSIZ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 19, O, u32>; #[doc = "Field `PKTCNT` reader - Packet count"] -pub type PKTCNT_R = crate::FieldReader; +pub type PKTCNT_R = crate::FieldReader; #[doc = "Field `PKTCNT` writer - Packet count"] -pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u16, u16, 10, O>; +pub type PKTCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `DPID` reader - Data PID"] -pub type DPID_R = crate::FieldReader; +pub type DPID_R = crate::FieldReader; #[doc = "Field `DPID` writer - Data PID"] -pub type DPID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCTSIZ_SPEC, u8, u8, 2, O>; +pub type DPID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:18 - Transfer size"] #[inline(always)] @@ -63,44 +31,59 @@ impl R { DPID_R::new(((self.bits >> 29) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCTSIZ") + .field("xfrsiz", &format_args!("{}", self.xfrsiz().bits())) + .field("pktcnt", &format_args!("{}", self.pktcnt().bits())) + .field("dpid", &format_args!("{}", self.dpid().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:18 - Transfer size"] #[inline(always)] #[must_use] - pub fn xfrsiz(&mut self) -> XFRSIZ_W<0> { + pub fn xfrsiz(&mut self) -> XFRSIZ_W { XFRSIZ_W::new(self) } #[doc = "Bits 19:28 - Packet count"] #[inline(always)] #[must_use] - pub fn pktcnt(&mut self) -> PKTCNT_W<19> { + pub fn pktcnt(&mut self) -> PKTCNT_W { PKTCNT_W::new(self) } #[doc = "Bits 29:30 - Data PID"] #[inline(always)] #[must_use] - pub fn dpid(&mut self) -> DPID_W<29> { + pub fn dpid(&mut self) -> DPID_W { DPID_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transfer size\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hctsiz](index.html) module"] +#[doc = "Transfer size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hctsiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hctsiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCTSIZ_SPEC; impl crate::RegisterSpec for HCTSIZ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hctsiz::R](R) reader structure"] -impl crate::Readable for HCTSIZ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hctsiz::W](W) writer structure"] +#[doc = "`read()` method returns [`hctsiz::R`](R) reader structure"] +impl crate::Readable for HCTSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hctsiz::W`](W) writer structure"] impl crate::Writable for HCTSIZ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_host/hprt.rs b/crates/bcm2837-lpa/src/usb_otg_host/hprt.rs index cb893f3..ca27b6f 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/hprt.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/hprt.rs @@ -1,83 +1,51 @@ #[doc = "Register `HPRT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HPRT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PCSTS` reader - Port connect status"] -pub type PCSTS_R = crate::BitReader; +pub type PCSTS_R = crate::BitReader; #[doc = "Field `PCDET` reader - Port connect detected"] -pub type PCDET_R = crate::BitReader; +pub type PCDET_R = crate::BitReader; #[doc = "Field `PCDET` writer - Port connect detected"] -pub type PCDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PCDET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PENA` reader - Port enable"] -pub type PENA_R = crate::BitReader; +pub type PENA_R = crate::BitReader; #[doc = "Field `PENA` writer - Port enable"] -pub type PENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PENCHNG` reader - Port enable/disable change"] -pub type PENCHNG_R = crate::BitReader; +pub type PENCHNG_R = crate::BitReader; #[doc = "Field `PENCHNG` writer - Port enable/disable change"] -pub type PENCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PENCHNG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POCA` reader - Port overcurrent active"] -pub type POCA_R = crate::BitReader; +pub type POCA_R = crate::BitReader; #[doc = "Field `POCCHNG` reader - Port overcurrent change"] -pub type POCCHNG_R = crate::BitReader; +pub type POCCHNG_R = crate::BitReader; #[doc = "Field `POCCHNG` writer - Port overcurrent change"] -pub type POCCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type POCCHNG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRES` reader - Port resume"] -pub type PRES_R = crate::BitReader; +pub type PRES_R = crate::BitReader; #[doc = "Field `PRES` writer - Port resume"] -pub type PRES_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PSUSP` reader - Port suspend"] -pub type PSUSP_R = crate::BitReader; +pub type PSUSP_R = crate::BitReader; #[doc = "Field `PSUSP` writer - Port suspend"] -pub type PSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRST` reader - Port reset"] -pub type PRST_R = crate::BitReader; +pub type PRST_R = crate::BitReader; #[doc = "Field `PRST` writer - Port reset"] -pub type PRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PLSTS` reader - Port line status"] -pub type PLSTS_R = crate::FieldReader; +pub type PLSTS_R = crate::FieldReader; #[doc = "Field `PPWR` reader - Port power"] -pub type PPWR_R = crate::BitReader; +pub type PPWR_R = crate::BitReader; #[doc = "Field `PPWR` writer - Port power"] -pub type PPWR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>; +pub type PPWR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTCTL` reader - Port test control"] -pub type PTCTL_R = crate::FieldReader; +pub type PTCTL_R = crate::FieldReader; #[doc = "Field `PTCTL` writer - Port test control"] -pub type PTCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPRT_SPEC, u8, u8, 4, O>; +pub type PTCTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `PSPD` reader - Port speed"] -pub type PSPD_R = crate::FieldReader; +pub type PSPD_R = crate::FieldReader; impl R { #[doc = "Bit 0 - Port connect status"] #[inline(always)] @@ -145,80 +113,105 @@ impl R { PSPD_R::new(((self.bits >> 17) & 3) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HPRT") + .field("pcsts", &format_args!("{}", self.pcsts().bit())) + .field("pcdet", &format_args!("{}", self.pcdet().bit())) + .field("pena", &format_args!("{}", self.pena().bit())) + .field("penchng", &format_args!("{}", self.penchng().bit())) + .field("poca", &format_args!("{}", self.poca().bit())) + .field("pocchng", &format_args!("{}", self.pocchng().bit())) + .field("pres", &format_args!("{}", self.pres().bit())) + .field("psusp", &format_args!("{}", self.psusp().bit())) + .field("prst", &format_args!("{}", self.prst().bit())) + .field("plsts", &format_args!("{}", self.plsts().bits())) + .field("ppwr", &format_args!("{}", self.ppwr().bit())) + .field("ptctl", &format_args!("{}", self.ptctl().bits())) + .field("pspd", &format_args!("{}", self.pspd().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 1 - Port connect detected"] #[inline(always)] #[must_use] - pub fn pcdet(&mut self) -> PCDET_W<1> { + pub fn pcdet(&mut self) -> PCDET_W { PCDET_W::new(self) } #[doc = "Bit 2 - Port enable"] #[inline(always)] #[must_use] - pub fn pena(&mut self) -> PENA_W<2> { + pub fn pena(&mut self) -> PENA_W { PENA_W::new(self) } #[doc = "Bit 3 - Port enable/disable change"] #[inline(always)] #[must_use] - pub fn penchng(&mut self) -> PENCHNG_W<3> { + pub fn penchng(&mut self) -> PENCHNG_W { PENCHNG_W::new(self) } #[doc = "Bit 5 - Port overcurrent change"] #[inline(always)] #[must_use] - pub fn pocchng(&mut self) -> POCCHNG_W<5> { + pub fn pocchng(&mut self) -> POCCHNG_W { POCCHNG_W::new(self) } #[doc = "Bit 6 - Port resume"] #[inline(always)] #[must_use] - pub fn pres(&mut self) -> PRES_W<6> { + pub fn pres(&mut self) -> PRES_W { PRES_W::new(self) } #[doc = "Bit 7 - Port suspend"] #[inline(always)] #[must_use] - pub fn psusp(&mut self) -> PSUSP_W<7> { + pub fn psusp(&mut self) -> PSUSP_W { PSUSP_W::new(self) } #[doc = "Bit 8 - Port reset"] #[inline(always)] #[must_use] - pub fn prst(&mut self) -> PRST_W<8> { + pub fn prst(&mut self) -> PRST_W { PRST_W::new(self) } #[doc = "Bit 12 - Port power"] #[inline(always)] #[must_use] - pub fn ppwr(&mut self) -> PPWR_W<12> { + pub fn ppwr(&mut self) -> PPWR_W { PPWR_W::new(self) } #[doc = "Bits 13:16 - Port test control"] #[inline(always)] #[must_use] - pub fn ptctl(&mut self) -> PTCTL_W<13> { + pub fn ptctl(&mut self) -> PTCTL_W { PTCTL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OTG_HS host port control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hprt](index.html) module"] +#[doc = "OTG_HS host port control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hprt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hprt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HPRT_SPEC; impl crate::RegisterSpec for HPRT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hprt::R](R) reader structure"] -impl crate::Readable for HPRT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hprt::W](W) writer structure"] +#[doc = "`read()` method returns [`hprt::R`](R) reader structure"] +impl crate::Readable for HPRT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hprt::W`](W) writer structure"] impl crate::Writable for HPRT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_host/hptxsts.rs b/crates/bcm2837-lpa/src/usb_otg_host/hptxsts.rs index 3cb5895..ffb1b12 100644 --- a/crates/bcm2837-lpa/src/usb_otg_host/hptxsts.rs +++ b/crates/bcm2837-lpa/src/usb_otg_host/hptxsts.rs @@ -1,47 +1,15 @@ #[doc = "Register `HPTXSTS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HPTXSTS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PTXFSAVL` reader - Periodic transmit data FIFO space available"] -pub type PTXFSAVL_R = crate::FieldReader; +pub type PTXFSAVL_R = crate::FieldReader; #[doc = "Field `PTXFSAVL` writer - Periodic transmit data FIFO space available"] -pub type PTXFSAVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HPTXSTS_SPEC, u16, u16, 16, O>; +pub type PTXFSAVL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `PTXQSAV` reader - Periodic transmit request queue space available"] -pub type PTXQSAV_R = crate::FieldReader; +pub type PTXQSAV_R = crate::FieldReader; #[doc = "Field `PTXQTOP` reader - Top of the periodic transmit request queue"] -pub type PTXQTOP_R = crate::FieldReader; +pub type PTXQTOP_R = crate::FieldReader; impl R { #[doc = "Bits 0:15 - Periodic transmit data FIFO space available"] #[inline(always)] @@ -59,32 +27,47 @@ impl R { PTXQTOP_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HPTXSTS") + .field("ptxfsavl", &format_args!("{}", self.ptxfsavl().bits())) + .field("ptxqsav", &format_args!("{}", self.ptxqsav().bits())) + .field("ptxqtop", &format_args!("{}", self.ptxqtop().bits())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bits 0:15 - Periodic transmit data FIFO space available"] #[inline(always)] #[must_use] - pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<0> { + pub fn ptxfsavl(&mut self) -> PTXFSAVL_W { PTXFSAVL_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host periodic transmit FIFO/queue status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxsts](index.html) module"] +#[doc = "Host periodic transmit FIFO/queue status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxsts::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hptxsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HPTXSTS_SPEC; impl crate::RegisterSpec for HPTXSTS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hptxsts::R](R) reader structure"] -impl crate::Readable for HPTXSTS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hptxsts::W](W) writer structure"] +#[doc = "`read()` method returns [`hptxsts::R`](R) reader structure"] +impl crate::Readable for HPTXSTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hptxsts::W`](W) writer structure"] impl crate::Writable for HPTXSTS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/usb_otg_pwrclk.rs b/crates/bcm2837-lpa/src/usb_otg_pwrclk.rs index 67a9eb5..242f3b2 100644 --- a/crates/bcm2837-lpa/src/usb_otg_pwrclk.rs +++ b/crates/bcm2837-lpa/src/usb_otg_pwrclk.rs @@ -1,10 +1,12 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - power and clock gating control"] pub pcgcctl: PCGCCTL, } -#[doc = "PCGCCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "PCGCCTL (rw) register accessor: power and clock gating control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcgcctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcgcctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcgcctl`] +module"] pub type PCGCCTL = crate::Reg; #[doc = "power and clock gating control"] pub mod pcgcctl; diff --git a/crates/bcm2837-lpa/src/usb_otg_pwrclk/pcgcctl.rs b/crates/bcm2837-lpa/src/usb_otg_pwrclk/pcgcctl.rs index 061312d..97a2598 100644 --- a/crates/bcm2837-lpa/src/usb_otg_pwrclk/pcgcctl.rs +++ b/crates/bcm2837-lpa/src/usb_otg_pwrclk/pcgcctl.rs @@ -1,102 +1,67 @@ #[doc = "Register `PCGCCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PCGCCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `STPPCLK` reader - Stop PHY clock"] -pub type STPPCLK_R = crate::BitReader; +pub type STPPCLK_R = crate::BitReader; #[doc = "Field `STPPCLK` writer - Stop PHY clock"] -pub type STPPCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type STPPCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GATEHCLK` reader - Gate HCLK"] -pub type GATEHCLK_R = crate::BitReader; +pub type GATEHCLK_R = crate::BitReader; #[doc = "Field `GATEHCLK` writer - Gate HCLK"] -pub type GATEHCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type GATEHCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWRCLMP` reader - Power clamp"] -pub type PWRCLMP_R = crate::BitReader; +pub type PWRCLMP_R = crate::BitReader; #[doc = "Field `PWRCLMP` writer - Power clamp"] -pub type PWRCLMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type PWRCLMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTPDWNMODULE` reader - Power down modules"] -pub type RSTPDWNMODULE_R = crate::BitReader; +pub type RSTPDWNMODULE_R = crate::BitReader; #[doc = "Field `RSTPDWNMODULE` writer - Power down modules"] -pub type RSTPDWNMODULE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type RSTPDWNMODULE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PHYSUSP` reader - PHY Suspended"] -pub type PHYSUSP_R = crate::BitReader; +pub type PHYSUSP_R = crate::BitReader; #[doc = "Field `PHYSUSP` writer - PHY Suspended"] -pub type PHYSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type PHYSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENABLE_L1GATING` reader - Enable sleep clock gating"] -pub type ENABLE_L1GATING_R = crate::BitReader; +pub type ENABLE_L1GATING_R = crate::BitReader; #[doc = "Field `ENABLE_L1GATING` writer - Enable sleep clock gating"] -pub type ENABLE_L1GATING_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type ENABLE_L1GATING_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PHYSLEEP` reader - PHY is in sleep mode"] -pub type PHYSLEEP_R = crate::BitReader; +pub type PHYSLEEP_R = crate::BitReader; #[doc = "Field `PHYSLEEP` writer - PHY is in sleep mode"] -pub type PHYSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type PHYSLEEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DEEPSLEEP` reader - PHY is in deep sleep"] -pub type DEEPSLEEP_R = crate::BitReader; +pub type DEEPSLEEP_R = crate::BitReader; #[doc = "Field `DEEPSLEEP` writer - PHY is in deep sleep"] -pub type DEEPSLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type DEEPSLEEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESETAFTERSUSP` reader - Reset after suspend"] -pub type RESETAFTERSUSP_R = crate::BitReader; +pub type RESETAFTERSUSP_R = crate::BitReader; #[doc = "Field `RESETAFTERSUSP` writer - Reset after suspend"] -pub type RESETAFTERSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type RESETAFTERSUSP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESTOREMODE` reader - Restore mode"] -pub type RESTOREMODE_R = crate::BitReader; +pub type RESTOREMODE_R = crate::BitReader; #[doc = "Field `RESTOREMODE` writer - Restore mode"] -pub type RESTOREMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type RESTOREMODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENEXTNDEDHIBER` reader - Enable extended hibernation"] -pub type ENEXTNDEDHIBER_R = crate::BitReader; +pub type ENEXTNDEDHIBER_R = crate::BitReader; #[doc = "Field `ENEXTNDEDHIBER` writer - Enable extended hibernation"] -pub type ENEXTNDEDHIBER_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type ENEXTNDEDHIBER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EXTNDEDHIBERNATIONCLAMP` reader - Extended hibernation clamp"] -pub type EXTNDEDHIBERNATIONCLAMP_R = crate::BitReader; +pub type EXTNDEDHIBERNATIONCLAMP_R = crate::BitReader; #[doc = "Field `EXTNDEDHIBERNATIONCLAMP` writer - Extended hibernation clamp"] -pub type EXTNDEDHIBERNATIONCLAMP_W<'a, const O: u8> = - crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type EXTNDEDHIBERNATIONCLAMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EXTNDEDHIBERNATIONSWITCH` reader - Extended hibernation switch"] -pub type EXTNDEDHIBERNATIONSWITCH_R = crate::BitReader; +pub type EXTNDEDHIBERNATIONSWITCH_R = crate::BitReader; #[doc = "Field `EXTNDEDHIBERNATIONSWITCH` writer - Extended hibernation switch"] -pub type EXTNDEDHIBERNATIONSWITCH_W<'a, const O: u8> = - crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type EXTNDEDHIBERNATIONSWITCH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ESSREGRESTORED` reader - Essential register values restored"] -pub type ESSREGRESTORED_R = crate::BitReader; +pub type ESSREGRESTORED_R = crate::BitReader; #[doc = "Field `ESSREGRESTORED` writer - Essential register values restored"] -pub type ESSREGRESTORED_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>; +pub type ESSREGRESTORED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESTORE_VALUE` reader - Restore value"] -pub type RESTORE_VALUE_R = crate::FieldReader; +pub type RESTORE_VALUE_R = crate::FieldReader; #[doc = "Field `RESTORE_VALUE` writer - Restore value"] -pub type RESTORE_VALUE_W<'a, const O: u8> = - crate::FieldWriter<'a, u32, PCGCCTL_SPEC, u32, u32, 18, O>; +pub type RESTORE_VALUE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 18, O, u32>; impl R { #[doc = "Bit 0 - Stop PHY clock"] #[inline(always)] @@ -174,116 +139,167 @@ impl R { RESTORE_VALUE_R::new((self.bits >> 14) & 0x0003_ffff) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PCGCCTL") + .field("stppclk", &format_args!("{}", self.stppclk().bit())) + .field("gatehclk", &format_args!("{}", self.gatehclk().bit())) + .field("pwrclmp", &format_args!("{}", self.pwrclmp().bit())) + .field( + "rstpdwnmodule", + &format_args!("{}", self.rstpdwnmodule().bit()), + ) + .field("physusp", &format_args!("{}", self.physusp().bit())) + .field( + "enable_l1gating", + &format_args!("{}", self.enable_l1gating().bit()), + ) + .field("physleep", &format_args!("{}", self.physleep().bit())) + .field("deepsleep", &format_args!("{}", self.deepsleep().bit())) + .field( + "resetaftersusp", + &format_args!("{}", self.resetaftersusp().bit()), + ) + .field("restoremode", &format_args!("{}", self.restoremode().bit())) + .field( + "enextndedhiber", + &format_args!("{}", self.enextndedhiber().bit()), + ) + .field( + "extndedhibernationclamp", + &format_args!("{}", self.extndedhibernationclamp().bit()), + ) + .field( + "extndedhibernationswitch", + &format_args!("{}", self.extndedhibernationswitch().bit()), + ) + .field( + "essregrestored", + &format_args!("{}", self.essregrestored().bit()), + ) + .field( + "restore_value", + &format_args!("{}", self.restore_value().bits()), + ) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Stop PHY clock"] #[inline(always)] #[must_use] - pub fn stppclk(&mut self) -> STPPCLK_W<0> { + pub fn stppclk(&mut self) -> STPPCLK_W { STPPCLK_W::new(self) } #[doc = "Bit 1 - Gate HCLK"] #[inline(always)] #[must_use] - pub fn gatehclk(&mut self) -> GATEHCLK_W<1> { + pub fn gatehclk(&mut self) -> GATEHCLK_W { GATEHCLK_W::new(self) } #[doc = "Bit 2 - Power clamp"] #[inline(always)] #[must_use] - pub fn pwrclmp(&mut self) -> PWRCLMP_W<2> { + pub fn pwrclmp(&mut self) -> PWRCLMP_W { PWRCLMP_W::new(self) } #[doc = "Bit 3 - Power down modules"] #[inline(always)] #[must_use] - pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W<3> { + pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W { RSTPDWNMODULE_W::new(self) } #[doc = "Bit 4 - PHY Suspended"] #[inline(always)] #[must_use] - pub fn physusp(&mut self) -> PHYSUSP_W<4> { + pub fn physusp(&mut self) -> PHYSUSP_W { PHYSUSP_W::new(self) } #[doc = "Bit 5 - Enable sleep clock gating"] #[inline(always)] #[must_use] - pub fn enable_l1gating(&mut self) -> ENABLE_L1GATING_W<5> { + pub fn enable_l1gating(&mut self) -> ENABLE_L1GATING_W { ENABLE_L1GATING_W::new(self) } #[doc = "Bit 6 - PHY is in sleep mode"] #[inline(always)] #[must_use] - pub fn physleep(&mut self) -> PHYSLEEP_W<6> { + pub fn physleep(&mut self) -> PHYSLEEP_W { PHYSLEEP_W::new(self) } #[doc = "Bit 7 - PHY is in deep sleep"] #[inline(always)] #[must_use] - pub fn deepsleep(&mut self) -> DEEPSLEEP_W<7> { + pub fn deepsleep(&mut self) -> DEEPSLEEP_W { DEEPSLEEP_W::new(self) } #[doc = "Bit 8 - Reset after suspend"] #[inline(always)] #[must_use] - pub fn resetaftersusp(&mut self) -> RESETAFTERSUSP_W<8> { + pub fn resetaftersusp(&mut self) -> RESETAFTERSUSP_W { RESETAFTERSUSP_W::new(self) } #[doc = "Bit 9 - Restore mode"] #[inline(always)] #[must_use] - pub fn restoremode(&mut self) -> RESTOREMODE_W<9> { + pub fn restoremode(&mut self) -> RESTOREMODE_W { RESTOREMODE_W::new(self) } #[doc = "Bit 10 - Enable extended hibernation"] #[inline(always)] #[must_use] - pub fn enextndedhiber(&mut self) -> ENEXTNDEDHIBER_W<10> { + pub fn enextndedhiber(&mut self) -> ENEXTNDEDHIBER_W { ENEXTNDEDHIBER_W::new(self) } #[doc = "Bit 11 - Extended hibernation clamp"] #[inline(always)] #[must_use] - pub fn extndedhibernationclamp(&mut self) -> EXTNDEDHIBERNATIONCLAMP_W<11> { + pub fn extndedhibernationclamp(&mut self) -> EXTNDEDHIBERNATIONCLAMP_W { EXTNDEDHIBERNATIONCLAMP_W::new(self) } #[doc = "Bit 12 - Extended hibernation switch"] #[inline(always)] #[must_use] - pub fn extndedhibernationswitch(&mut self) -> EXTNDEDHIBERNATIONSWITCH_W<12> { + pub fn extndedhibernationswitch(&mut self) -> EXTNDEDHIBERNATIONSWITCH_W { EXTNDEDHIBERNATIONSWITCH_W::new(self) } #[doc = "Bit 13 - Essential register values restored"] #[inline(always)] #[must_use] - pub fn essregrestored(&mut self) -> ESSREGRESTORED_W<13> { + pub fn essregrestored(&mut self) -> ESSREGRESTORED_W { ESSREGRESTORED_W::new(self) } #[doc = "Bits 14:31 - Restore value"] #[inline(always)] #[must_use] - pub fn restore_value(&mut self) -> RESTORE_VALUE_W<14> { + pub fn restore_value(&mut self) -> RESTORE_VALUE_W { RESTORE_VALUE_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "power and clock gating control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcgcctl](index.html) module"] +#[doc = "power and clock gating control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcgcctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcgcctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCGCCTL_SPEC; impl crate::RegisterSpec for PCGCCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pcgcctl::R](R) reader structure"] -impl crate::Readable for PCGCCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [pcgcctl::W](W) writer structure"] +#[doc = "`read()` method returns [`pcgcctl::R`](R) reader structure"] +impl crate::Readable for PCGCCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pcgcctl::W`](W) writer structure"] impl crate::Writable for PCGCCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/vcmailbox.rs b/crates/bcm2837-lpa/src/vcmailbox.rs index 7490467..f3d9184 100644 --- a/crates/bcm2837-lpa/src/vcmailbox.rs +++ b/crates/bcm2837-lpa/src/vcmailbox.rs @@ -1,5 +1,6 @@ #[doc = r"Register block"] #[repr(C)] +#[derive(Debug)] pub struct RegisterBlock { #[doc = "0x00 - Read messages from the VideoCore"] pub read: READ, @@ -24,43 +25,53 @@ pub struct RegisterBlock { #[doc = "0x3c - "] pub config1: CONFIG1, } -#[doc = "READ (r) register accessor: an alias for `Reg`"] +#[doc = "READ (r) register accessor: Read messages from the VideoCore\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`read::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@read`] +module"] pub type READ = crate::Reg; #[doc = "Read messages from the VideoCore"] pub mod read; -#[doc = "PEEK0 (rw) register accessor: an alias for `Reg`"] +#[doc = "PEEK0 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peek0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peek0`] +module"] pub type PEEK0 = crate::Reg; #[doc = ""] pub mod peek0; -#[doc = "SENDER0 (rw) register accessor: an alias for `Reg`"] +#[doc = "SENDER0 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sender0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sender0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sender0`] +module"] pub type SENDER0 = crate::Reg; #[doc = ""] pub mod sender0; -#[doc = "STATUS0 (r) register accessor: an alias for `Reg`"] +#[doc = "STATUS0 (r) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status0`] +module"] pub type STATUS0 = crate::Reg; #[doc = ""] pub mod status0; -#[doc = "CONFIG0 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONFIG0 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config0::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config0`] +module"] pub type CONFIG0 = crate::Reg; #[doc = ""] pub mod config0; -#[doc = "WRITE (w) register accessor: an alias for `Reg`"] +#[doc = "WRITE (w) register accessor: Write messages to the VideoCore\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`write::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@write`] +module"] pub type WRITE = crate::Reg; #[doc = "Write messages to the VideoCore"] pub mod write; -#[doc = "PEEK1 (rw) register accessor: an alias for `Reg`"] +#[doc = "PEEK1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peek1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peek1`] +module"] pub type PEEK1 = crate::Reg; #[doc = ""] pub mod peek1; -#[doc = "SENDER1 (rw) register accessor: an alias for `Reg`"] +#[doc = "SENDER1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sender1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sender1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sender1`] +module"] pub type SENDER1 = crate::Reg; #[doc = ""] pub mod sender1; -#[doc = "STATUS1 (rw) register accessor: an alias for `Reg`"] +#[doc = "STATUS1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status1`] +module"] pub type STATUS1 = crate::Reg; #[doc = ""] pub mod status1; -#[doc = "CONFIG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "CONFIG1 (rw) register accessor: \n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config1::R`]. You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config1`] +module"] pub type CONFIG1 = crate::Reg; #[doc = ""] pub mod config1; diff --git a/crates/bcm2837-lpa/src/vcmailbox/config0.rs b/crates/bcm2837-lpa/src/vcmailbox/config0.rs index dce060f..b90c56d 100644 --- a/crates/bcm2837-lpa/src/vcmailbox/config0.rs +++ b/crates/bcm2837-lpa/src/vcmailbox/config0.rs @@ -1,43 +1,11 @@ #[doc = "Register `CONFIG0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONFIG0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IRQEN` reader - Enable the interrupt when data is available"] -pub type IRQEN_R = crate::BitReader; +pub type IRQEN_R = crate::BitReader; #[doc = "Field `IRQEN` writer - Enable the interrupt when data is available"] -pub type IRQEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG0_SPEC, bool, O>; +pub type IRQEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable the interrupt when data is available"] #[inline(always)] @@ -45,32 +13,45 @@ impl R { IRQEN_R::new((self.bits & 1) != 0) } } +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONFIG0") + .field("irqen", &format_args!("{}", self.irqen().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} impl W { #[doc = "Bit 0 - Enable the interrupt when data is available"] #[inline(always)] #[must_use] - pub fn irqen(&mut self) -> IRQEN_W<0> { + pub fn irqen(&mut self) -> IRQEN_W { IRQEN_W::new(self) } - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config0](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONFIG0_SPEC; impl crate::RegisterSpec for CONFIG0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [config0::R](R) reader structure"] -impl crate::Readable for CONFIG0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [config0::W](W) writer structure"] +#[doc = "`read()` method returns [`config0::R`](R) reader structure"] +impl crate::Readable for CONFIG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config0::W`](W) writer structure"] impl crate::Writable for CONFIG0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/vcmailbox/config1.rs b/crates/bcm2837-lpa/src/vcmailbox/config1.rs index 3c238a6..8a50eee 100644 --- a/crates/bcm2837-lpa/src/vcmailbox/config1.rs +++ b/crates/bcm2837-lpa/src/vcmailbox/config1.rs @@ -1,59 +1,38 @@ #[doc = "Register `CONFIG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CONFIG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config1](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CONFIG1_SPEC; impl crate::RegisterSpec for CONFIG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [config1::R](R) reader structure"] -impl crate::Readable for CONFIG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [config1::W](W) writer structure"] +#[doc = "`read()` method returns [`config1::R`](R) reader structure"] +impl crate::Readable for CONFIG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config1::W`](W) writer structure"] impl crate::Writable for CONFIG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/vcmailbox/peek0.rs b/crates/bcm2837-lpa/src/vcmailbox/peek0.rs index 3b63843..9119a22 100644 --- a/crates/bcm2837-lpa/src/vcmailbox/peek0.rs +++ b/crates/bcm2837-lpa/src/vcmailbox/peek0.rs @@ -1,59 +1,38 @@ #[doc = "Register `PEEK0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PEEK0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek0](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peek0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEEK0_SPEC; impl crate::RegisterSpec for PEEK0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [peek0::R](R) reader structure"] -impl crate::Readable for PEEK0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [peek0::W](W) writer structure"] +#[doc = "`read()` method returns [`peek0::R`](R) reader structure"] +impl crate::Readable for PEEK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peek0::W`](W) writer structure"] impl crate::Writable for PEEK0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/vcmailbox/peek1.rs b/crates/bcm2837-lpa/src/vcmailbox/peek1.rs index 2431cc4..221331c 100644 --- a/crates/bcm2837-lpa/src/vcmailbox/peek1.rs +++ b/crates/bcm2837-lpa/src/vcmailbox/peek1.rs @@ -1,59 +1,38 @@ #[doc = "Register `PEEK1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PEEK1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peek1](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peek1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peek1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEEK1_SPEC; impl crate::RegisterSpec for PEEK1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [peek1::R](R) reader structure"] -impl crate::Readable for PEEK1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [peek1::W](W) writer structure"] +#[doc = "`read()` method returns [`peek1::R`](R) reader structure"] +impl crate::Readable for PEEK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peek1::W`](W) writer structure"] impl crate::Writable for PEEK1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/vcmailbox/read.rs b/crates/bcm2837-lpa/src/vcmailbox/read.rs index 60b2d04..7328372 100644 --- a/crates/bcm2837-lpa/src/vcmailbox/read.rs +++ b/crates/bcm2837-lpa/src/vcmailbox/read.rs @@ -1,24 +1,19 @@ #[doc = "Register `READ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } -#[doc = "Read messages from the VideoCore\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [read](index.html) module"] +#[doc = "Read messages from the VideoCore\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`read::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct READ_SPEC; impl crate::RegisterSpec for READ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [read::R](R) reader structure"] -impl crate::Readable for READ_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`read::R`](R) reader structure"] +impl crate::Readable for READ_SPEC {} diff --git a/crates/bcm2837-lpa/src/vcmailbox/sender0.rs b/crates/bcm2837-lpa/src/vcmailbox/sender0.rs index cbeb2f1..4b8ec27 100644 --- a/crates/bcm2837-lpa/src/vcmailbox/sender0.rs +++ b/crates/bcm2837-lpa/src/vcmailbox/sender0.rs @@ -1,59 +1,38 @@ #[doc = "Register `SENDER0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SENDER0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sender0](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sender0::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sender0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SENDER0_SPEC; impl crate::RegisterSpec for SENDER0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sender0::R](R) reader structure"] -impl crate::Readable for SENDER0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sender0::W](W) writer structure"] +#[doc = "`read()` method returns [`sender0::R`](R) reader structure"] +impl crate::Readable for SENDER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sender0::W`](W) writer structure"] impl crate::Writable for SENDER0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/vcmailbox/sender1.rs b/crates/bcm2837-lpa/src/vcmailbox/sender1.rs index 1537c2d..f787ecb 100644 --- a/crates/bcm2837-lpa/src/vcmailbox/sender1.rs +++ b/crates/bcm2837-lpa/src/vcmailbox/sender1.rs @@ -1,59 +1,38 @@ #[doc = "Register `SENDER1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SENDER1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sender1](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sender1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sender1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SENDER1_SPEC; impl crate::RegisterSpec for SENDER1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sender1::R](R) reader structure"] -impl crate::Readable for SENDER1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sender1::W](W) writer structure"] +#[doc = "`read()` method returns [`sender1::R`](R) reader structure"] +impl crate::Readable for SENDER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sender1::W`](W) writer structure"] impl crate::Writable for SENDER1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/vcmailbox/status0.rs b/crates/bcm2837-lpa/src/vcmailbox/status0.rs index 035e2a4..92a12f6 100644 --- a/crates/bcm2837-lpa/src/vcmailbox/status0.rs +++ b/crates/bcm2837-lpa/src/vcmailbox/status0.rs @@ -1,22 +1,9 @@ #[doc = "Register `STATUS0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EMPTY` reader - "] -pub type EMPTY_R = crate::BitReader; +pub type EMPTY_R = crate::BitReader; #[doc = "Field `FULL` reader - "] -pub type FULL_R = crate::BitReader; +pub type FULL_R = crate::BitReader; impl R { #[doc = "Bit 30"] #[inline(always)] @@ -29,12 +16,23 @@ impl R { FULL_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status0](index.html) module"] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS0") + .field("full", &format_args!("{}", self.full().bit())) + .field("empty", &format_args!("{}", self.empty().bit())) + .finish() + } +} +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) + } +} +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STATUS0_SPEC; impl crate::RegisterSpec for STATUS0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [status0::R](R) reader structure"] -impl crate::Readable for STATUS0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`status0::R`](R) reader structure"] +impl crate::Readable for STATUS0_SPEC {} diff --git a/crates/bcm2837-lpa/src/vcmailbox/status1.rs b/crates/bcm2837-lpa/src/vcmailbox/status1.rs index 1a7b501..64ad85f 100644 --- a/crates/bcm2837-lpa/src/vcmailbox/status1.rs +++ b/crates/bcm2837-lpa/src/vcmailbox/status1.rs @@ -1,59 +1,38 @@ #[doc = "Register `STATUS1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `STATUS1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) } } -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + self.read().fmt(f) } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status1](index.html) module"] +#[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STATUS1_SPEC; impl crate::RegisterSpec for STATUS1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [status1::R](R) reader structure"] -impl crate::Readable for STATUS1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [status1::W](W) writer structure"] +#[doc = "`read()` method returns [`status1::R`](R) reader structure"] +impl crate::Readable for STATUS1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status1::W`](W) writer structure"] impl crate::Writable for STATUS1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/crates/bcm2837-lpa/src/vcmailbox/write.rs b/crates/bcm2837-lpa/src/vcmailbox/write.rs index 4e09735..f34b6af 100644 --- a/crates/bcm2837-lpa/src/vcmailbox/write.rs +++ b/crates/bcm2837-lpa/src/vcmailbox/write.rs @@ -1,40 +1,29 @@ #[doc = "Register `WRITE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) +pub type W = crate::W; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") } } impl W { - #[doc = "Writes raw bits to the register."] + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write messages to the VideoCore\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [write](index.html) module"] +#[doc = "Write messages to the VideoCore\n\nYou can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`write::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WRITE_SPEC; impl crate::RegisterSpec for WRITE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [write::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`write::W`](W) writer structure"] impl crate::Writable for WRITE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/gen.sh b/gen.sh index 0c9c7ce..eed86d9 100755 --- a/gen.sh +++ b/gen.sh @@ -14,7 +14,7 @@ mcu_name=$1 cd "crates/${mcu_name}-lpa/" svd2rust -i "../../peripherals/svd/gen/${mcu_name}_lpa.svd" --target none \ - --atomics + --atomics --impl_debug rm -rf src/ form -i lib.rs -o src/