ORCA_TOP.func.sdc

################################################################################
#
# Design name:  ORCA_TOP
#
# Created by icc2 write_sdc on Sun Jan 24 17:09:13 2021
#
################################################################################

set sdc_version 2.1
set_units -time ns -resistance MOhm -capacitance fF -voltage V -current uA

################################################################################
#
# Units
# time_unit               : 1e-09
# resistance_unit         : 1000000
# capacitive_load_unit    : 1e-15
# voltage_unit            : 1
# current_unit            : 1e-06
# power_unit              : 1e-12
################################################################################


# Mode: func
# Corner: ss0p75v125c_cmax
# Scenario: func_ss0p75v125c_cmax

# /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 7
set_case_analysis 0 [get_ports {test_mode}]
# /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 8
set_case_analysis 0 [get_ports {scan_enable}]
# /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 11
create_clock -name PCI_CLK -period 7.5 -waveform {0 3.75} [get_ports {pclk}]
# /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 12
create_clock -name v_PCI_CLK -period 7.5 -waveform {0 3.75}
# /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 15
create_clock -name SYS_2x_CLK -period 2.3 -waveform {0 1.15} [get_ports {sys_2x_clk}]
# /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 17; /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 17
create_generated_clock -name SYS_CLK -divide_by 2 -source [get_ports {sys_2x_clk}] -add -master_clock [get_clocks {SYS_2x_CLK}] [get_pins {I_CLOCKING/sys_clk_in_reg/Q}]
# /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 20
create_clock -name SDRAM_CLK -period 4.1 -waveform {0 2.05} [get_ports {sdram_clk}]
# /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 21
create_clock -name v_SDRAM_CLK -period 4.1 -waveform {0 2.05}
# /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 24; /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 24
create_generated_clock -name SD_DDR_CLK -divide_by 1 -combinational -source [get_ports {sdram_clk}] -add -master_clock [get_clocks {SDRAM_CLK}] [get_ports {sd_CK}]
# /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 26; /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 26
create_generated_clock -name SD_DDR_CLKn -divide_by 1 -combinational -invert -source [get_ports {sdram_clk}] -add -master_clock [get_clocks {SDRAM_CLK}] [get_ports {sd_CKn}]
# /disk/hd01/data/proj/labs/share/ORCA_TOP/constraints/ORCA_TOP_m_func.tcl, line 32
set_clock_groups -name func_async -asynchronous -group [get_clocks {SYS_2x_CLK SYS_CLK}] -group [get_clocks {PCI_CLK v_PCI_CLK}] -group [get_clocks {SDRAM_CLK v_SDRAM_CLK SD_DDR_CLK SD_DDR_CLKn}]
set_load -pin_load 30 [get_ports {test_so[5]}]
set_load -pin_load 30 [get_ports {test_so[4]}]
set_load -pin_load 30 [get_ports {test_so[3]}]
set_load -pin_load 30 [get_ports {test_so[2]}]
set_load -pin_load 30 [get_ports {test_so[1]}]
set_load -pin_load 30 [get_ports {test_so[0]}]
set_load -pin_load 100 [get_ports {pad_out[31]}]
set_load -pin_load 100 [get_ports {pad_out[30]}]
set_load -pin_load 100 [get_ports {pad_out[29]}]
set_load -pin_load 100 [get_ports {pad_out[28]}]
set_load -pin_load 100 [get_ports {pad_out[27]}]
set_load -pin_load 100 [get_ports {pad_out[26]}]
set_load -pin_load 100 [get_ports {pad_out[25]}]
set_load -pin_load 100 [get_ports {pad_out[24]}]
set_load -pin_load 100 [get_ports {pad_out[23]}]
set_load -pin_load 100 [get_ports {pad_out[22]}]
set_load -pin_load 100 [get_ports {pad_out[21]}]
set_load -pin_load 100 [get_ports {pad_out[20]}]
set_load -pin_load 100 [get_ports {pad_out[19]}]
set_load -pin_load 100 [get_ports {pad_out[18]}]
set_load -pin_load 100 [get_ports {pad_out[17]}]
set_load -pin_load 100 [get_ports {pad_out[16]}]
set_load -pin_load 100 [get_ports {pad_out[15]}]
set_load -pin_load 100 [get_ports {pad_out[14]}]
set_load -pin_load 100 [get_ports {pad_out[13]}]
set_load -pin_load 100 [get_ports {pad_out[12]}]
set_load -pin_load 100 [get_ports {pad_out[11]}]
set_load -pin_load 100 [get_ports {pad_out[10]}]
set_load -pin_load 100 [get_ports {pad_out[9]}]
set_load -pin_load 100 [get_ports {pad_out[8]}]
set_load -pin_load 100 [get_ports {pad_out[7]}]
set_load -pin_load 100 [get_ports {pad_out[6]}]
set_load -pin_load 100 [get_ports {pad_out[5]}]
set_load -pin_load 100 [get_ports {pad_out[4]}]
set_load -pin_load 100 [get_ports {pad_out[3]}]
set_load -pin_load 100 [get_ports {pad_out[2]}]
set_load -pin_load 100 [get_ports {pad_out[1]}]
set_load -pin_load 100 [get_ports {pad_out[0]}]
set_load -pin_load 100 [get_ports {pad_en}]
set_load -pin_load 100 [get_ports {ppar_out}]
set_load -pin_load 100 [get_ports {ppar_en}]
set_load -pin_load 100 [get_ports {pc_be_out[3]}]
set_load -pin_load 100 [get_ports {pc_be_out[2]}]
set_load -pin_load 100 [get_ports {pc_be_out[1]}]
set_load -pin_load 100 [get_ports {pc_be_out[0]}]
set_load -pin_load 100 [get_ports {pc_be_en}]
set_load -pin_load 100 [get_ports {pframe_n_out}]
set_load -pin_load 100 [get_ports {pframe_n_en}]
set_load -pin_load 100 [get_ports {ptrdy_n_out}]
set_load -pin_load 100 [get_ports {ptrdy_n_en}]
set_load -pin_load 100 [get_ports {pirdy_n_out}]
set_load -pin_load 100 [get_ports {pirdy_n_en}]
set_load -pin_load 100 [get_ports {pdevsel_n_out}]
set_load -pin_load 100 [get_ports {pdevsel_n_en}]
set_load -pin_load 100 [get_ports {pstop_n_out}]
set_load -pin_load 100 [get_ports {pstop_n_en}]
set_load -pin_load 100 [get_ports {pperr_n_out}]
set_load -pin_load 100 [get_ports {pperr_n_en}]
set_load -pin_load 100 [get_ports {pserr_n_out}]
set_load -pin_load 100 [get_ports {pserr_n_en}]
set_load -pin_load 100 [get_ports {preq_n}]
set_load -pin_load 100 [get_ports {pack_n}]
set_load -pin_load 10 [get_ports {sd_A[9]}]
set_load -pin_load 10 [get_ports {sd_A[8]}]
set_load -pin_load 10 [get_ports {sd_A[7]}]
set_load -pin_load 10 [get_ports {sd_A[6]}]
set_load -pin_load 10 [get_ports {sd_A[5]}]
set_load -pin_load 10 [get_ports {sd_A[4]}]
set_load -pin_load 10 [get_ports {sd_A[3]}]
set_load -pin_load 10 [get_ports {sd_A[2]}]
set_load -pin_load 10 [get_ports {sd_A[1]}]
set_load -pin_load 10 [get_ports {sd_A[0]}]
set_load -pin_load 10 [get_ports {sd_LD}]
set_load -pin_load 10 [get_ports {sd_RW}]
set_load -pin_load 10 [get_ports {sd_BWS[1]}]
set_load -pin_load 10 [get_ports {sd_BWS[0]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[31]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[30]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[29]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[28]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[27]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[26]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[25]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[24]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[23]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[22]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[21]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[20]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[19]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[18]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[17]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[16]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[15]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[14]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[13]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[12]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[11]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[10]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[9]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[8]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[7]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[6]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[5]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[4]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[3]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[2]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[1]}]
set_load -pin_load 10 [get_ports {sd_DQ_out[0]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[31]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[30]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[29]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[28]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[27]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[26]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[25]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[24]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[23]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[22]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[21]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[20]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[19]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[18]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[17]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[16]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[15]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[14]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[13]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[12]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[11]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[10]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[9]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[8]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[7]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[6]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[5]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[4]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[3]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[2]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[1]}]
set_load -pin_load 10 [get_ports {sd_DQ_en[0]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pidsel}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pidsel}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pgnt_n}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pgnt_n}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[31]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[31]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[30]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[30]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[29]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[29]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[28]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[28]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[27]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[27]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[26]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[26]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[25]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[25]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[24]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[24]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[23]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[23]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[22]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[22]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[21]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[21]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[20]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[20]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[19]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[19]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[18]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[18]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[17]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[17]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[16]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[16]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[15]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[15]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[14]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[14]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[13]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[13]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[12]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[12]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[11]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[11]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[10]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[10]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[9]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[9]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[8]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[8]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[7]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[7]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[6]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[6]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[5]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[5]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[4]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[4]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[3]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[3]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[2]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[2]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[1]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[1]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pad_in[0]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pad_in[0]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[31]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[31]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[30]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[30]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[29]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[29]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[28]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[28]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[27]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[27]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[26]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[26]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[25]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[25]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[24]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[24]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[23]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[23]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[22]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[22]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[21]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[21]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[20]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[20]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[19]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[19]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[18]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[18]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[17]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[17]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[16]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[16]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[15]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[15]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[14]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[14]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[13]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[13]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[12]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[12]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[11]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[11]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[10]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[10]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[9]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[9]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[8]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[8]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[7]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[7]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[6]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[6]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[5]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[5]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[4]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[4]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[3]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[3]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[2]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[2]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[1]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[1]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_out[0]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_out[0]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pad_en}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pad_en}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {ppar_in}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {ppar_in}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {ppar_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {ppar_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {ppar_en}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {ppar_en}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pc_be_in[3]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pc_be_in[3]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pc_be_in[2]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pc_be_in[2]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pc_be_in[1]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pc_be_in[1]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pc_be_in[0]}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pc_be_in[0]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pc_be_out[3]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pc_be_out[3]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pc_be_out[2]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pc_be_out[2]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pc_be_out[1]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pc_be_out[1]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pc_be_out[0]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pc_be_out[0]}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pc_be_en}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pc_be_en}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pframe_n_in}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pframe_n_in}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pframe_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pframe_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pframe_n_en}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pframe_n_en}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {ptrdy_n_in}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {ptrdy_n_in}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {ptrdy_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {ptrdy_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {ptrdy_n_en}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {ptrdy_n_en}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pirdy_n_in}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pirdy_n_in}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pirdy_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pirdy_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pirdy_n_en}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pirdy_n_en}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pdevsel_n_in}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pdevsel_n_in}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pdevsel_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pdevsel_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pdevsel_n_en}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pdevsel_n_en}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pstop_n_in}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pstop_n_in}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pstop_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pstop_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pstop_n_en}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pstop_n_en}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pperr_n_in}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pperr_n_in}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pperr_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pperr_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pperr_n_en}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pperr_n_en}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pserr_n_in}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pserr_n_in}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pserr_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pserr_n_out}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pserr_n_en}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pserr_n_en}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {preq_n}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {preq_n}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -min 0.5 [get_ports {pack_n}]
set_output_delay -clock [get_clocks {v_PCI_CLK}] -max 3 [get_ports {pack_n}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -min 2 [get_ports {pm66en}]
set_input_delay -clock [get_clocks {v_PCI_CLK}] -max 4 [get_ports {pm66en}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_A[9]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_A[9]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_A[8]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_A[8]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_A[7]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_A[7]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_A[6]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_A[6]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_A[5]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_A[5]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_A[4]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_A[4]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_A[3]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_A[3]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_A[2]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_A[2]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_A[1]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_A[1]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_A[0]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_A[0]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_LD}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_LD}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_RW}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_RW}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_BWS[1]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_BWS[1]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_BWS[0]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_BWS[0]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[31]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[31]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[31]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[31]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[30]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[30]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[30]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[30]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[29]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[29]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[29]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[29]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[28]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[28]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[28]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[28]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[27]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[27]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[27]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[27]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[26]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[26]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[26]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[26]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[25]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[25]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[25]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[25]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[24]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[24]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[24]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[24]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[23]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[23]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[23]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[23]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[22]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[22]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[22]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[22]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[21]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[21]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[21]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[21]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[20]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[20]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[20]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[20]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[19]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[19]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[19]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[19]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[18]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[18]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[18]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[18]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[17]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[17]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[17]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[17]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[16]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[16]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[16]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[16]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[15]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[15]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[15]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[15]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[14]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[14]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[14]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[14]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[13]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[13]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[13]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[13]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[12]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[12]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[12]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[12]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[11]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[11]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[11]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[11]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[10]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[10]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[10]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[10]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[9]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[9]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[9]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[9]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[8]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[8]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[8]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[8]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[7]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[7]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[7]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[7]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[6]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[6]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[6]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[6]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[5]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[5]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[5]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[5]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[4]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[4]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[4]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[4]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[3]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[3]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[3]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[3]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[2]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[2]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[2]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[2]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[1]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[1]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[1]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[1]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -min 0.2 [get_ports {sd_DQ_in[0]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -max 0.6 [get_ports {sd_DQ_in[0]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -min -add_delay 0.2 [get_ports {sd_DQ_in[0]}]
set_input_delay -clock [get_clocks {v_SDRAM_CLK}] -clock_fall -max -add_delay 0.6 [get_ports {sd_DQ_in[0]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[31]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[31]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[30]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[30]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[29]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[29]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[28]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[28]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[27]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[27]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[26]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[26]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[25]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[25]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[24]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[24]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[23]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[23]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[22]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[22]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[21]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[21]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[20]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[20]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[19]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[19]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[18]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[18]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[17]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[17]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[16]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[16]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[15]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[15]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[14]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[14]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[13]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[13]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[12]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[12]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[11]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[11]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[10]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[10]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[9]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[9]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[8]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[8]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[7]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[7]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[6]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[6]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[5]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[5]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[4]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[4]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[3]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[3]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[2]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[2]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[1]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[1]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -min 0.1 [get_ports {sd_DQ_out[0]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -clock_fall -max 0.75 [get_ports {sd_DQ_out[0]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[31]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[31]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[30]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[30]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[29]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[29]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[28]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[28]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[27]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[27]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[26]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[26]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[25]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[25]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[24]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[24]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[23]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[23]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[22]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[22]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[21]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[21]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[20]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[20]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[19]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[19]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[18]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[18]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[17]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[17]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[16]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[16]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[15]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[15]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[14]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[14]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[13]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[13]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[12]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[12]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[11]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[11]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[10]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[10]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[9]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[9]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[8]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[8]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[7]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[7]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[6]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[6]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[5]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[5]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[4]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[4]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[3]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[3]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[2]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[2]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[1]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[1]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -min 0.1 [get_ports {sd_DQ_en[0]}]
set_output_delay -clock [get_clocks {SD_DDR_CLK}] -max 0.75 [get_ports {sd_DQ_en[0]}]
set_max_transition 0.25 [get_clocks {PCI_CLK}] -data_path
set_max_transition 0.25 [get_clocks {v_PCI_CLK}] -data_path
set_max_transition 0.25 [get_clocks {SYS_2x_CLK}] -data_path
set_max_transition 0.25 [get_clocks {SYS_CLK}] -data_path
set_max_transition 0.25 [get_clocks {SDRAM_CLK}] -data_path
set_max_transition 0.25 [get_clocks {v_SDRAM_CLK}] -data_path
set_max_transition 0.25 [get_clocks {SD_DDR_CLK}] -data_path
set_max_transition 0.25 [get_clocks {SD_DDR_CLKn}] -data_path
set_max_transition 0.15 [get_clocks {PCI_CLK}] -clock_path
set_max_transition 0.15 [get_clocks {v_PCI_CLK}] -clock_path
set_max_transition 0.15 [get_clocks {SYS_2x_CLK}] -clock_path
set_max_transition 0.15 [get_clocks {SYS_CLK}] -clock_path
set_max_transition 0.15 [get_clocks {SDRAM_CLK}] -clock_path
set_max_transition 0.15 [get_clocks {v_SDRAM_CLK}] -clock_path
set_max_transition 0.15 [get_clocks {SD_DDR_CLK}] -clock_path
set_max_transition 0.15 [get_clocks {SD_DDR_CLKn}] -clock_path
set_max_capacitance 150 [current_design]