Yosys crash: Signal `\A' with invalid width range -1 in cells_map.v"

[1353369570]

Version

Yosys 0.46+124 (git sha1 d1695ad, g++ 9.4.0-1ubuntu1~20.04.3 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

read_verilog rtl.v ; synth_xilinx -arch xc7 -top modinst71 -widemux 5

Expected Behavior

The synthesis should complete without errors, generating the expected netlist for the specified Xilinx architecture

Actual Behavior

Yosys has the error"/usr/local/bin/../share/yosys/xilinx/cells_map.v:151: ERROR: Signal `\A' with invalid width range -1!"

rtl.txt

[georgerennie]

I believe this is the same as #4590, but I don't know enough about the xilinx cells to fix it myself