'synth_intel' command,synthesis result is wrong

[CL-liao]

Version

Yosys 0.32+51 (git sha1 6405bba, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os)

On which OS did this happen?

Linux

Reproduction Steps

execute : ./yosys -s /home/user/yosys/demo.ys -l /home/user/yosys/demo.log

demo.ys as followiing:
read_verilog /home/lcl/yosys/top1.v;
synth_intel -retime -family cycloneiv -top top1 -vqm top1.vqm;

top1.v as following:
module top1 (
in1,
clk1,
clk2,
aload,
aclr,
out1
);
input in1;
input clk1,clk2;
input aload,aclr;
output reg out1;
reg in1_reg;
always @(posedge clk1, posedge aload) begin
if (aload)
begin
in1_reg <= 1'b1;
end
else
begin
in1_reg <= in1;
end
end
always @(posedge clk2, negedge aclr) begin
if (!aclr)
begin
out1 <= 1'b0;
end
else
begin
out1 <= in1_reg && clk2;
end
end
endmodule

My input verilog is a $DFF_PP1 and a $DFF_PN0,but the output is $DFF_PN0 and $DFF_PP0. That's wrong.

Expected Behavior

I want to use the command for synthesis.

Actual Behavior

My input verilog is a $DFF_PP1 and a $DFF_PN0,but the output is $DFF_PN0 and $DFF_PP0. That's wrong.

[georgerennie]

I believe the output is still equivalent to your input. It is using different cells, but it adds comb logic around them so that the function is the same. Could you double check that you are actually seeing different behaviour before and after and not just different cells?

It may also be worth updating your Yosys, 0.32 is over a year old and I get different DFF representations with a more up to date version.