todo_notes.txt

//===- todo_notes.txt -----------------------------------------*- cmake -*-===//
//
// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2021 Xilinx Inc.
//
//===----------------------------------------------------------------------===//

=== Here are the list of things that can be improved (as of 08/20/2020)

1/ Some tests are failing due to code being generated in different orders when iterating over
some map data. However, they should be logically correct.

test_create_packet_flow*.mlir
test_herd_routing*.mlir
test_mmap0.mlir
test_xaie2.mlir
test_xaie3.mlir

2/ SelectOp and IterOp are basically describing loops and indexing. They can be refactored to a loop-like
operations (affine loop op?)

3/ HerdOp (for selecting a group of cores as opposed to Tile(x, y)) can only be used with switchbox()
for now

4/ Some DMA configurations are not yet modeling, such as PacketSwitch or FIFO mode.

5/ When lowering Core region to LLVM, we should generate LLVM Module instead of LLVM function (per
core). HerdOp can be leveraged here to generate the same code for multiple cores.

6/ The Routing algorithms are duplicated all over the places: AIECreateFlows, AIEHerdRouting, and
AIECreatePacketSwitchRouting, for different purposes. Need some effort to refactor them.

7/ Create an ARM op with a region to represent host code execution. We can do the same thing for the PL too.
(but maybe it's better to create a new Dialect for these?)

8/ Need a way to generate the statistics of a physical netlist.
How many cores are utilized?
Routing resource?

9/ DMA config in Mem region can be refactored to make it more compact.

10/ Support multi-dimensional buffers

11/ Support packet-switched routing with nested header to be able to route to more than 32 dests