SD Card Image Fails to Boot on VCK190 Board Using Vitis AI 3.0 TRD

[yunyi-zhao]

Hello,

I have been following the "VCK190 DPUCVDX8G Reference Design for Vitis AI" tutorial from Vitis AI 3.0 to build and run the Target Reference Design (TRD) flow on the VCK190 evaluation board. I successfully completed the build process, generating the SD card image located at $TRD_HOME/vitis_prj/package_out/sd_card.img.gz. I configured the VCK190 board for SD boot mode and flashed this image to an SD card using balenaEtcher with no issue.

However, the board fails to boot the Versal image from the SD card image build with reference design. There is no output on the serial communication port associated with the Versal side. Only the control system outputs are visible on the COM interface. I tested the board with Vitis AI pre-built SD card image with no issue at all.

Environment Details:

Vitis-AI 3.0
Vitis Version: 2022.2
PetaLinux Tools Version: 2022.2
Host OS: Ubuntu 22.04.5 LTS
Hardware: VCK190 Evaluation Board

Could you please assist me in troubleshooting this issue? Are there any additional steps, configurations, or known issues that might prevent the self-built SD card image from booting on the VCK190 board?

Following is a snipshot for build with Vitis-ai TRD, I noticed there is a warning saying Kernel image is not specified for linux domain:
INFO:- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
INFO:Packaging dpu.xclbin for hw...
Option Map File Used: '/tools/Xilinx/Vitis/2022.2/data/vitis/vpp/optMap.xml'

****** v++ v2022.2 (64-bit)
**** SW Build 3671529 on 2022-10-13-17:52:11
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ package can be found at:
Reports: /home/yunyi/DPUCVDX8G_VAI_v3.0/vitis_prj/hw/binary_container_1/reports/package
Log files: /home/yunyi/DPUCVDX8G_VAI_v3.0/vitis_prj/hw/binary_container_1/logs/package
Running Dispatch Server on port: 41263
INFO: [v++ 60-1548] Creating build summary session with primary output /home/yunyi/DPUCVDX8G_VAI_v3.0/vitis_prj/hw/hw/dpu.xclbin.package_summary, at Sun Nov 24 01:53:58 2024
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/yunyi/DPUCVDX8G_VAI_v3.0/vitis_prj/hw/binary_container_1/reports/package/v++_package_dpu_guidance.html', at Sun Nov 24 01:53:58 2024
INFO: [v++ 60-895] Target platform: /home/yunyi/DPUCVDX8G_VAI_v3.0/vck190_platform/platforms/xilinx_vck190_mipiRxSingle_hdmiTx_202220_1/vck190_mipiRxSingle_hdmiTx.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/home/yunyi/DPUCVDX8G_VAI_v3.0/vck190_platform/platforms/xilinx_vck190_mipiRxSingle_hdmiTx_202220_1/hw/vck190_mipiRxSingle_hdmiTx.xsa'
INFO: [v++ 60-2256] Packaging for hardware
INFO: [v++ 82-3881] device architecture set to versal
WARNING: [v++ 82-1147] Kernel image is not specified for linux domain
INFO: [v++ 82-1022] generating /home/yunyi/DPUCVDX8G_VAI_v3.0/vitis_prj/package_out/boot_image.bif
INFO: [v++ 82-3884] generating pdi for arch versal with bif /home/yunyi/DPUCVDX8G_VAI_v3.0/vitis_prj/package_out/boot_image.bif

****** Xilinx Bootgen v2022.2.0
**** Build date : Oct 13 2022-12:22:43
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

[INFO] : Bootimage generated successfully

Any guidance or suggestions would be greatly appreciated.

Thank you for your help.