From 48ed81adf4dbcb28d3cd1a058aea85d9aa4107bf Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 16 Mar 2021 13:52:17 -0700 Subject: [PATCH 001/117] initial setup and overview --- README.md | 14 ++++++++++++-- document/core/index.rst | 2 +- document/core/util/macros.def | 8 ++++---- proposals/relaxed-simd/Overview.md | 29 +++++++++++++++++++++++++++++ 4 files changed, 46 insertions(+), 7 deletions(-) create mode 100644 proposals/relaxed-simd/Overview.md diff --git a/README.md b/README.md index 83cdc4da6..d719087d3 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,16 @@ -[![Build Status](https://travis-ci.org/WebAssembly/spec.svg?branch=master)](https://travis-ci.org/WebAssembly/spec) +[![Build Status](https://travis-ci.org/WebAssembly/relaxed-simd.svg?branch=master)](https://travis-ci.org/WebAssembly/relaxed-simd) -# spec +# Relaxed SIMD proposal for WebAssembly + +This repository is a clone of [github.com/WebAssembly/spec/](https://github.com/WebAssembly/spec/). +It is meant for discussion, prototype specification and implementation of a proposal to +add support for SIMD instructions with relaxed determinism requirements to WebAssembly. + +* See the [overview](proposals/relaxed-simd/Overview.md) for a summary of the proposal. + +* See the [modified spec](https://webassembly.github.io/relaxed-simd/) for details. + +Original `README` from upstream repository follows… This repository holds the sources for the WebAssembly draft specification (to seed a future diff --git a/document/core/index.rst b/document/core/index.rst index 1d8d6a4aa..b69fa6f51 100644 --- a/document/core/index.rst +++ b/document/core/index.rst @@ -3,7 +3,7 @@ WebAssembly Specification .. only:: html - | Release |release| (Draft, |today|) + | Release |release| + relaxed-simd (Draft, |today|) | Editor: Andreas Rossberg diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 82928c6f8..cfed4ebf3 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -3,11 +3,11 @@ .. External Standards .. ------------------ -.. |WasmDraft| replace:: https://webassembly.github.io/spec/core/ -.. _WasmDraft: https://webassembly.github.io/spec/core/ +.. |WasmDraft| replace:: https://webassembly.github.io/relaxed-simd/core/ +.. _WasmDraft: https://webassembly.github.io/relaxed-simd/core/ -.. |WasmIssues| replace:: https://github.com/webassembly/spec/issues/ -.. _WasmIssues: https://github.com/webassembly/spec/issues/ +.. |WasmIssues| replace:: https://github.com/webassembly/relaxed-simd/issues/ +.. _WasmIssues: https://github.com/webassembly/relaxed-simd/issues/ .. |IEEE754| replace:: IEEE 754-2019 .. _IEEE754: https://ieeexplore.ieee.org/document/8766229 diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md new file mode 100644 index 000000000..a23c08b01 --- /dev/null +++ b/proposals/relaxed-simd/Overview.md @@ -0,0 +1,29 @@ +# Relaxed SIMD proposal + +## Summary + +This proposal adds a set of useful SIMD instructions that introduce local +non-determinism (where the results of the instructions may vary based on +hardware support). + +## Motivation + +Applications running on Wasm SIMD cannot take full advantage of hardware +capabilities. There are 3 reasons: + +1. Instruction depends on hardware support +2. Approximate instructions that are underspecified in hardware +3. Some SIMD instructions penalize particular architecture + +See [these +slides](https://docs.google.com/presentation/d/1Qnx0nbNTRYhMONLuKyygEduCXNOv3xtWODfXfYokx1Y/edit?usp=sharing) +for more details. + +## Overview + +Some instructions we would like to add: + +- Fused Multiply Add (single rounding if hardware supports it, double rounding if not) +- Approximate reciprocal/reciprocal sqrt +- Relaxed Swizzle (implementation defined out of bounds behavior) +- Relaxed Rounding Q-format Multiplication (optional saturation) From dd63aa28228b13d1ec5b886c1a86f5c28e7df600 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 17 Mar 2021 16:06:00 -0700 Subject: [PATCH 002/117] Add a references section with useful links --- proposals/relaxed-simd/Overview.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index a23c08b01..45901ec82 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -27,3 +27,11 @@ Some instructions we would like to add: - Approximate reciprocal/reciprocal sqrt - Relaxed Swizzle (implementation defined out of bounds behavior) - Relaxed Rounding Q-format Multiplication (optional saturation) + +## References + +- Poll for phase 1 + [presentation](https://docs.google.com/presentation/d/1Qnx0nbNTRYhMONLuKyygEduCXNOv3xtWODfXfYokx1Y/edit?usp=sharing) + and [meeting + notes](https://github.com/WebAssembly/meetings/blob/master/main/2021/CG-03-16.md) +- [SIMD proposal](https://github.com/WebAssembly/simd) From bf6a1bd069ac378ebe742375eef1956e1c3bae77 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 23 Mar 2021 13:32:04 -0700 Subject: [PATCH 003/117] Add description of categories of instructions (#8) --- proposals/relaxed-simd/Overview.md | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 45901ec82..6a7c6a840 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -21,7 +21,16 @@ for more details. ## Overview -Some instructions we would like to add: +Broadly, there are three categories of instructions that fit into the Relaxed SIMD proposal: + +1. Integer instructions where the inputs are interpreted differently (e.g. + swizzle, 4-D dot-product) +2. Floating-point instructions whose behavior for out-of-range and NaNs differ + (e.g. float-to-int conversions, float min/max) +3. Floating-point instructions where the precision or order of operations + differ (e.g. FMA, reciprocal instructions, sum reduction) + +Example of some instructions we would like to add: - Fused Multiply Add (single rounding if hardware supports it, double rounding if not) - Approximate reciprocal/reciprocal sqrt From 224627e6128a0aaa6a8f6f4611bdd77c60377a97 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 24 Mar 2021 09:09:48 -0700 Subject: [PATCH 004/117] Update issue templates (#14) Add template for suggesting new instructions. --- .../add-new-instructions--name-.md | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 .github/ISSUE_TEMPLATE/add-new-instructions--name-.md diff --git a/.github/ISSUE_TEMPLATE/add-new-instructions--name-.md b/.github/ISSUE_TEMPLATE/add-new-instructions--name-.md new file mode 100644 index 000000000..1bec883e0 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/add-new-instructions--name-.md @@ -0,0 +1,20 @@ +--- +name: Add new instructions {name} +about: Suggest new instructions for Relaxed SIMD +title: '' +labels: instruction-proposal +assignees: '' + +--- + +1. What are the instructions being proposed? + +2. What are the semantics of these instructions? + +3. How will these instructions be implemented? Give examples for at least + x86-64 and ARM64. Also provide reference implementation in terms of 128-bit + Wasm SIMD. + +4. How does behavior differ across processors? What new fingerprinting surfaces will be exposed? + +5. What use cases are there? From 77e5f06df5cf6751f33868f4cc8e73f18c12c935 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 25 Mar 2021 09:36:41 -0700 Subject: [PATCH 005/117] Add paragraph describing consistency using fpenv (#15) * Add paragraph on fpenv * Attribute must be 0 for now, call it a module element * Name fpu to make examples clearer * Reword paragraph on fpenv instantiation * Reword last paragraph describing what fpenv is * Add attribute 0 to import example --- proposals/relaxed-simd/Overview.md | 71 ++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 6a7c6a840..b72df934e 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -37,6 +37,77 @@ Example of some instructions we would like to add: - Relaxed Swizzle (implementation defined out of bounds behavior) - Relaxed Rounding Q-format Multiplication (optional saturation) +### Consistency + +This proposal introduces non-deterministic instructions - given the same +inputs, two calls to the same instruction can return different results. For +example: + +```wast +(module + (func (param v128 v128 v128) + (f32x4.qfma (local.get 0) (local.get 1) (local.get 2)) ;; (1) + ;; some other computation + (f32x4.qfma (local.get 0) (local.get 1) (local.get 2)))) ;; (2) +``` + +The same instruction at `(1)` and `(2)`, when given the same inputs, can return +two different results. This is compliant as the instruction is +non-deterministic, though unlikely on certain embeddings like the Web (where +the same implementation for `f32x4.qfma` is likely to be used for all calls to +that instruction). One can imagine splitting an application's module and +running them on multiple runtimes, where the runtimes produce +different results - this can be surprising to the application. + +Applications can specify their consistency needs using a new module-level +entity `fpenv` (name subject to change). A `fpenv` is defined in the `fpenv` +section of a module. All Relaxed SIMD instructions will take an additional +`varuint32` immediate, which is an index into the `fpenv` index space: + +```wast +(module + (func (param v128 v128 v128) + (f32x4.qfma $fpu (local.get 0) (local.get 1) (local.get 2)) ;; (1) + ;; ... + (f32x4.qfma $fpu (local.get 0) (local.get 1) (local.get 2)) ;; (2) + ) + (fpenv $fpu 0)) +``` + +In the example above, both `f32x4.qfma` instructions refer to the same `fpenv`, +and will get the same results when given the same input. + +A `fpenv` has a single `varuint32` attribute which is reserved for future +extensibility and must be `0` for now. The value of an `fpenv` is +non-deterministically computed when the module which declares it is +instantiated. This value determines the semantics of the instructions that +uses it as an immediate. + +As such, all the non-determinism of Relaxed SIMD is encapsulated in `fpenv`, +which makes Relaxed SIMD instructions themselves deterministic. + +Modules can import/export an `fpenv` to specify consistency requirements: + +```wast +;; module a +(module + (fpenv $fpu (export "foo") 0) + (func (param v128 v128 v128) + (f32x4.qfma $fpu (local.get 0) (local.get 1) (local.get 2)))) ;; (1) +``` + +```wast +;; module b +(module + (import "a" "foo" (fpenv $fpu 0)) + (func (param v128 v128 v128) + (f32x4.qfma $fpu (local.get 0) (local.get 1) (local.get 2)))) ;; (2) +``` + +In the above example, the same `fpenv` is exported by module `a`, and imported +by module `b`, so instructions `(1)` and `(2)` will consistently return the +same results when given the same inputs. + ## References - Poll for phase 1 From d87f9b2a593a0107318bfd01f092b219752bc6e9 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 29 Mar 2021 10:56:23 -0700 Subject: [PATCH 006/117] Add placeholder sections for instructions and binary format (#16) --- proposals/relaxed-simd/Overview.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index b72df934e..b563d0985 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -108,6 +108,14 @@ In the above example, the same `fpenv` is exported by module `a`, and imported by module `b`, so instructions `(1)` and `(2)` will consistently return the same results when given the same inputs. +## Instructions + +> This is a placeholder for instructions that this proposal adds. + +## Binary format + +> This is a placeholder for binary format of instructions and new constructs. + ## References - Poll for phase 1 From 023ce403b6afc5562657a9b0f5a29e4ee88b958e Mon Sep 17 00:00:00 2001 From: Deepti Gandluri Date: Wed, 14 Apr 2021 21:17:37 -0700 Subject: [PATCH 007/117] Add SIMD subgroup charter (#18) As this is the first time we have separate proposals under the same subgroup - I'm duplicating the charter here as well as in the flexible vectors proposal for discoverability, and for easy modification in case we decide to split the subgroup based on proposals in the future. --- proposals/relaxed-simd/Charter.md | 57 +++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 proposals/relaxed-simd/Charter.md diff --git a/proposals/relaxed-simd/Charter.md b/proposals/relaxed-simd/Charter.md new file mode 100644 index 000000000..975a3f9aa --- /dev/null +++ b/proposals/relaxed-simd/Charter.md @@ -0,0 +1,57 @@ +# WebAssembly SIMD Subgroup Charter + +The SIMD Subgroup is a sub-organization of the +[WebAssembly Community Group](https://www.w3.org/community/webassembly/) +of the W3C. +As such, it is intended that its charter align with that of the CG. In particular, +the sections of the [CG charter](https://webassembly.github.io/cg-charter/) relating to +[Community and Business Group Process](https://webassembly.github.io/cg-charter/#process), +[Contribution Mechanics](https://webassembly.github.io/cg-charter/#contrib), +[Transparency](https://webassembly.github.io/cg-charter/#transparency), +and +[Decision Process](https://webassembly.github.io/cg-charter/#decision) +also apply to the Subgroup. + +## Goals + +The mission of this subgroup is to provide a forum for collaboration on the standardisation of SIMD support for WebAssembly. This is inclusive of the fixed-width SIMD, relaxed-SIMD, and flexible vectors proposals. + +## Scope + +The Subgroup will consider topics related to SIMD for Wasm, including: + +- instruction sets for defining and manipulating vector types, +- code generation for compilers targeting Wasm with SIMD extensions, +- performance data for justifying the inclusion of instructions, +- hardware support for SIMD, as well as ease of use for applications + +## Deliverables + +### Specifications + +The Subgroup may produce several kinds of specification-related work output: + +- new specifications in standards bodies or working groups + (e.g. W3C WebAssembly WG or Ecma TC39), +- new specifications outside of standards bodies + (e.g. similar to the LLVM object file format documentation in Wasm tool conventions). + +### Non-normative reports + +The Subgroup may produce non-normative material such as requirements +documents, optimization guides, recommendations, and case studies. + +### Software + +The Subgroup may produce software related to SIMD in Wasm +(either as standalone libraries, tooling, or integration of interface-related functionality in existing CG software). +These may include: + +- extensions to the Wasm reference interpreter, +- extensions to the Wasm test suite, +- compilers and tools for producing code that uses Wasm SIMD, +- tools for debugging programs using Wasm SIMD. + +## Amendments to this Charter and Chair Selection + +This charter may be amended, and Subgroup Chairs may be selected by vote of the full WebAssembly Community Group. From e71547e1e37af81a7874b34ead4f710991684fba Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 10 Jun 2021 09:35:33 -0700 Subject: [PATCH 008/117] Add relaxed swizzle to overview (#24) #22 --- proposals/relaxed-simd/Overview.md | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index b563d0985..3cebd0604 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -110,7 +110,22 @@ same results when given the same inputs. ## Instructions -> This is a placeholder for instructions that this proposal adds. +### Relaxed swizzle + +- `relaxed i8x16.swizzle(a : v128, s : v128) -> v128` + +`relaxed i8x16.swizzle(a, s)` selects lanes from `a` using indices in `s`, indices in the range `[0,15]` will select the `i`-th element of `a`, the result for any out of range indices is implementation-defined (i.e. if the index is `[16-255]`. + +```python +def relaxed_i8x16_swizzle(a, s): + result = [] + for i in range(16): + if s[i] < 16: + result[i] = a[s[i]] + else: + result[i] = UNDEFINED + return result +``` ## Binary format From 4fced219f0fbb88d73a5ce05ea06f56289bfb906 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 24 Jun 2021 09:37:11 -0700 Subject: [PATCH 009/117] Add relaxed float to int conversions (#25) For #21. --- proposals/relaxed-simd/Overview.md | 36 ++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 3cebd0604..2c01a0035 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -127,6 +127,42 @@ def relaxed_i8x16_swizzle(a, s): return result ``` +### Float/Double to int conversions + +- `relaxed i32x4.trunc_f32x4_s` (relaxed version of `i32x4.trunc_sat_f32x4_s`) +- `relaxed i32x4.trunc_f32x4_u` (relaxed version of `i32x4.trunc_sat_f32x4_u`) +- `relaxed i32x4.trunc_f64x2_s_zero` (relaxed version of `i32x4.trunc_sat_f64x2_s_zero`) +- `relaxed i32x4.trunc_f64x2_u_zero` (relaxed version of `i32x4.trunc_sat_f64x2_u_zero`) + +These instructions have the same behavior as the non-relaxed instructions for +lanes that are in the range of an `i32` (signed or unsigned depending on the +instruction). For lanes that contain values which are out of bounds or NaN, the +result is implementation-defined. + +```python +def relaxed_i32x4_trunc_f32x4(a : f32x4, signed : bool) -> i32x4: + result = [] + min = signed ? INT32_MIN : UINT32_MIN + max = signed ? INT32_MAX : UINT32_MAX + for i in range(4): + r = truncate(a[i]) + if min <= r <= max: + result[i] = r + else: + result[i] = UNDEFINED + +def relaxed_i32x4_trunc_f64x2_zero(a : f64x2, signed : bool) -> i32x4: + result = [0, 0, 0, 0] + min = signed ? INT32_MIN : UINT32_MIN + max = signed ? INT32_MAX : UINT32_MAX + for i in range(2): + r = truncate(a[i]) + if min <= r <= max: + result[i] = r + else: + result[i] = UNDEFINED +``` + ## Binary format > This is a placeholder for binary format of instructions and new constructs. From 969876920538de69d9ee4bba31a31e6f2da816a4 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Fri, 2 Jul 2021 12:15:28 -0700 Subject: [PATCH 010/117] Add fma and fms (#28) See #27. --- proposals/relaxed-simd/Overview.md | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 2c01a0035..63aa6a4dd 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -163,6 +163,25 @@ def relaxed_i32x4_trunc_f64x2_zero(a : f64x2, signed : bool) -> i32x4: result[i] = UNDEFINED ``` +### Relaxed fused multiply-add and fused multiply-subtract + +- `relaxed f32x4.fma` +- `relaxed f32x4.fms` +- `relaxed f64x2.fma` +- `relaxed f64x2.fms` + +All the instructions take 3 operands, `a`, `b`, `c`, perform `a + (b * c)` or `a - (b * c)`: + +- `relaxed f32x4.fma(a, b, c) = a + (b * c)` +- `relaxed f32x4.fms(a, b, c) = a - (b * c)` +- `relaxed f64x2.fma(a, b, c) = a + (b * c)` +- `relaxed f64x2.fms(a, b, c) = a - (b * c)` + +where: + +- the intermediate `b * c` is be rounded first, and the final result rounded again (for a total of 2 roundings), or +- the the entire expression evaluated with higher precision and then only rounded once (if supported by hardware). + ## Binary format > This is a placeholder for binary format of instructions and new constructs. From 229516819d2444f69e5093db30447fb6d0f72182 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 21 Jul 2021 14:06:11 -0700 Subject: [PATCH 011/117] Add relaxed blend to overview (#29) --- proposals/relaxed-simd/Overview.md | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 63aa6a4dd..ed8e7dbf1 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -182,6 +182,29 @@ where: - the intermediate `b * c` is be rounded first, and the final result rounded again (for a total of 2 roundings), or - the the entire expression evaluated with higher precision and then only rounded once (if supported by hardware). +### Relaxed bitselect (blend/laneselect) + +- `i8x16.blend(a: v128, b: v128, m: v128) -> v128` +- `i16x8.blend(a: v128, b: v128, m: v128) -> v128` +- `i32x4.blend(a: v128, b: v128, m: v128) -> v128` +- `i64x2.blend(a: v128, b: v128, m: v128) -> v128` + +Select lanes from `a` or `b` based on masks in `m`. If each lane-sized mask in `m` has all bits set or all bits unset, these instructions behave the same as `v128.bitselect`. Otherwise, the result is implementation defined. + +```python +def blend(a : v128, b : v128, m: v128, lanes : int): + result = [] + for i in range(lanes): + mask = m[i] + if mask == ~0: + result[i] = a[i] + elif mask == 0: + result[i] = b[i] + else: + result[i] = UNDEFINED + return result +``` + ## Binary format > This is a placeholder for binary format of instructions and new constructs. From d7489cda801099945f372c6bab08f7ca2fc996d9 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 5 Aug 2021 09:08:29 -0700 Subject: [PATCH 012/117] Add binary opcodes for instructions in overview (#32) --- proposals/relaxed-simd/Overview.md | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index ed8e7dbf1..1cd3a58fb 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -207,7 +207,25 @@ def blend(a : v128, b : v128, m: v128, lanes : int): ## Binary format -> This is a placeholder for binary format of instructions and new constructs. +All opcodes have the `0xfd` prefix (same as SIMD proposal), which are omitted in the table below. + +| instruction | opcode | +| ---------------------------------- | -------- | +| `relaxed i8x16.swizzle` | 0xa2 | +| `relaxed i32x4.trunc_f32x4_s` | 0xa5 | +| `relaxed i32x4.trunc_f32x4_u` | 0xa6 | +| `relaxed i32x4.trunc_f64x2_s_zero` | 0xc5 | +| `relaxed i32x4.trunc_f64x2_u_zero` | 0xc6 | +| `f32x4.fma` | 0xaf | +| `f32x4.fms` | 0xb0 | +| `f64x2.fma` | 0xcf | +| `f64x2.fms` | 0xd0 | +| `i8x16.blend` | 0xb2 | +| `i16x8.blend` | 0xb3 | +| `i32x4.blend` | 0xd2 | +| `i64x2.blend` | 0xd3 | + +Note: the opcodes are chosen to fit into the existing opcode space of the SIMD proposal, see [Binary encoding of SIMD](https://github.com/WebAssembly/simd/blob/main/proposals/simd/BinarySIMD.md), or a [table view of the same opcodes](https://github.com/WebAssembly/simd/blob/main/proposals/simd/NewOpcodes.md) for a list of existing opcodes. ## References From 18c1b1d172db53eae343c096861dc4682dcde3a6 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 9 Aug 2021 14:52:28 -0700 Subject: [PATCH 013/117] Update issue templates --- .github/ISSUE_TEMPLATE/simd-meeting.md | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 .github/ISSUE_TEMPLATE/simd-meeting.md diff --git a/.github/ISSUE_TEMPLATE/simd-meeting.md b/.github/ISSUE_TEMPLATE/simd-meeting.md new file mode 100644 index 000000000..a256d2436 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/simd-meeting.md @@ -0,0 +1,14 @@ +--- +name: simd-meeting +about: SIMD subgroup meeting +title: SIMD subgroup meeting on YYYY-MM-DD +labels: '' +assignees: '' + +--- + +This is a joint meeting with flexible-vectors and any SIMD related presentations are also welcome, e.g. new architectures or toolchains, longer term discussion that don't fit into flexible-vectors or relaxed-simd. + +The meeting will be on Friday, {Month} {Day} at 9:00AM - 10:00AM PDT/ 5:00PM - 6:00PM CET. + +If this meeting doesn't already appear on your calendar, or you are a new attendee, please fill out this [form](https://forms.gle/9eB2ZYaziPEcTJabA) to attend. From ae132b37247bd529c706d97e5bd8635fddfe2807 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 7 Sep 2021 10:53:46 -0700 Subject: [PATCH 014/117] Add relaxed min and max (#36) For #33. --- proposals/relaxed-simd/Overview.md | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 1cd3a58fb..617c9d29c 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -205,6 +205,29 @@ def blend(a : v128, b : v128, m: v128, lanes : int): return result ``` +### Relaxed min and max + +- `f32x4.min(a: v128, b: v128) -> v128` +- `f32x4.max(a: v128, b: v128) -> v128` +- `f64x2.min(a: v128, b: v128) -> v128` +- `f64x2.max(a: v128, b: v128) -> v128` + +Return the lane-wise minimum or maximum of two values. If either values is NaN, or the values are -0.0 and +0.0, the return value is implementation-defined. + +```python +def min_or_max(a : v128, b : v128, lanes : int, is_min : bool): + result = [] + for i in range(lanes): + if isNaN(a[i]) or isNaN(b[i]): + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(a[i], b[i]) + elif (a[i] == -0.0 && b[i] == +0.0) or (a[i] == +0.0 && b[i] == -0.0): + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(a[i], b[i]) + else: + result[i] = is_min ? min(a, b) : max(a, b) +``` + +Where `IMPLEMENTATION_DEFINED_ONE_OF(x, y)` returns either `x` or `y`, depending on the implementation. + ## Binary format All opcodes have the `0xfd` prefix (same as SIMD proposal), which are omitted in the table below. @@ -224,6 +247,10 @@ All opcodes have the `0xfd` prefix (same as SIMD proposal), which are omitted in | `i16x8.blend` | 0xb3 | | `i32x4.blend` | 0xd2 | | `i64x2.blend` | 0xd3 | +| `f32x4.min` | 0xb4 | +| `f32x4.max` | 0xe2 | +| `f64x2.min` | 0xd4 | +| `f64x2.max` | 0xee | Note: the opcodes are chosen to fit into the existing opcode space of the SIMD proposal, see [Binary encoding of SIMD](https://github.com/WebAssembly/simd/blob/main/proposals/simd/BinarySIMD.md), or a [table view of the same opcodes](https://github.com/WebAssembly/simd/blob/main/proposals/simd/NewOpcodes.md) for a list of existing opcodes. From e53d41f9131a6db1e50435063361607a12789157 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 5 Oct 2021 10:33:50 -0700 Subject: [PATCH 015/117] Rename to laneselect (#41) As suggested in https://github.com/WebAssembly/relaxed-simd/issues/17#issuecomment-931927209. --- proposals/relaxed-simd/Overview.md | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 617c9d29c..7f5378bd6 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -182,17 +182,17 @@ where: - the intermediate `b * c` is be rounded first, and the final result rounded again (for a total of 2 roundings), or - the the entire expression evaluated with higher precision and then only rounded once (if supported by hardware). -### Relaxed bitselect (blend/laneselect) +### Relaxed laneselect -- `i8x16.blend(a: v128, b: v128, m: v128) -> v128` -- `i16x8.blend(a: v128, b: v128, m: v128) -> v128` -- `i32x4.blend(a: v128, b: v128, m: v128) -> v128` -- `i64x2.blend(a: v128, b: v128, m: v128) -> v128` +- `i8x16.laneselect(a: v128, b: v128, m: v128) -> v128` +- `i16x8.laneselect(a: v128, b: v128, m: v128) -> v128` +- `i32x4.laneselect(a: v128, b: v128, m: v128) -> v128` +- `i64x2.laneselect(a: v128, b: v128, m: v128) -> v128` Select lanes from `a` or `b` based on masks in `m`. If each lane-sized mask in `m` has all bits set or all bits unset, these instructions behave the same as `v128.bitselect`. Otherwise, the result is implementation defined. ```python -def blend(a : v128, b : v128, m: v128, lanes : int): +def laneselect(a : v128, b : v128, m: v128, lanes : int): result = [] for i in range(lanes): mask = m[i] @@ -243,10 +243,10 @@ All opcodes have the `0xfd` prefix (same as SIMD proposal), which are omitted in | `f32x4.fms` | 0xb0 | | `f64x2.fma` | 0xcf | | `f64x2.fms` | 0xd0 | -| `i8x16.blend` | 0xb2 | -| `i16x8.blend` | 0xb3 | -| `i32x4.blend` | 0xd2 | -| `i64x2.blend` | 0xd3 | +| `i8x16.laneselect` | 0xb2 | +| `i16x8.laneselect` | 0xb3 | +| `i32x4.laneselect` | 0xd2 | +| `i64x2.laneselect` | 0xd3 | | `f32x4.min` | 0xb4 | | `f32x4.max` | 0xe2 | | `f64x2.min` | 0xd4 | From 8f41b23273650d1ed0bf52c6af9d5d1d3b45cb8f Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 28 Oct 2021 14:22:23 -0700 Subject: [PATCH 016/117] Add implementation status document (#45) --- .../relaxed-simd/ImplementationStatus.md | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 proposals/relaxed-simd/ImplementationStatus.md diff --git a/proposals/relaxed-simd/ImplementationStatus.md b/proposals/relaxed-simd/ImplementationStatus.md new file mode 100644 index 000000000..7d8b534c3 --- /dev/null +++ b/proposals/relaxed-simd/ImplementationStatus.md @@ -0,0 +1,47 @@ +## Implementation in LLVM and various engines + +| Instruction | LLVM [1] | V8 [2] | SpiderMonkey | +|------------------------------------|----------------|--------------------|--------------| +| `relaxed i8x16.swizzle` | -mrelaxed-simd | :heavy_check_mark: | | +| `relaxed i32x4.trunc_f32x4_s` | -mrelaxed-simd | :heavy_check_mark: | | +| `relaxed i32x4.trunc_f32x4_u` | -mrelaxed-simd | :heavy_check_mark: | | +| `relaxed i32x4.trunc_f64x2_s_zero` | -mrelaxed-simd | :heavy_check_mark: | | +| `relaxed i32x4.trunc_f64x2_u_zero` | -mrelaxed-simd | :heavy_check_mark: | | +| `f32x4.fma` | -mrelaxed-simd | :heavy_check_mark: | | +| `f32x4.fms` | -mrelaxed-simd | :heavy_check_mark: | | +| `f64x2.fma` | -mrelaxed-simd | :heavy_check_mark: | | +| `f64x2.fms` | -mrelaxed-simd | :heavy_check_mark: | | +| `i8x16.laneselect` | -mrelaxed-simd | :heavy_check_mark: | | +| `i16x8.laneselect` | -mrelaxed-simd | :heavy_check_mark: | | +| `i32x4.laneselect` | -mrelaxed-simd | :heavy_check_mark: | | +| `i64x2.laneselect` | -mrelaxed-simd | :heavy_check_mark: | | +| `f32x4.min` | -mrelaxed-simd | :heavy_check_mark: | | +| `f32x4.max` | -mrelaxed-simd | :heavy_check_mark: | | +| `f64x2.min` | -mrelaxed-simd | :heavy_check_mark: | | +| `f64x2.max` | -mrelaxed-simd | :heavy_check_mark: | | + +[1] Tip of tree LLVM as of 2021-10-28 + +[2] V8 9.7.75 (only implemented on x64) + +## Name of builtins in LLVM + +| Instruction | LLVM | +|------------------------------------|---------------------------------------------------| +| `relaxed i8x16.swizzle` | `__builtin_wasm_relaxed_swizzle_i8x16` | +| `relaxed i32x4.trunc_f32x4_s` | `__builtin_wasm_relaxed_trunc_s_i32x4_f32x4` | +| `relaxed i32x4.trunc_f32x4_u` | `__builtin_wasm_relaxed_trunc_u_i32x4_f32x4` | +| `relaxed i32x4.trunc_f64x2_s_zero` | `__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2` | +| `relaxed i32x4.trunc_f64x2_u_zero` | `__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2` | +| `f32x4.fma` | `__builtin_wasm_fma_f32x4` | +| `f32x4.fms` | `__builtin_wasm_fms_f32x4` | +| `f64x2.fma` | `__builtin_wasm_fma_f64x2` | +| `f64x2.fms` | `__builtin_wasm_fms_f64x2` | +| `i8x16.laneselect` | `__builtin_wasm_laneselect_i8x16` | +| `i16x8.laneselect` | `__builtin_wasm_laneselect_i16x8` | +| `i32x4.laneselect` | `__builtin_wasm_laneselect_i32x4` | +| `i64x2.laneselect` | `__builtin_wasm_laneselect_i64x2` | +| `f32x4.min` | `__builtin_wasm_relaxed_min_f32x4` | +| `f32x4.max` | `__builtin_wasm_relaxed_max_f32x4` | +| `f64x2.min` | `__builtin_wasm_relaxed_min_f64x2` | +| `f64x2.max` | `__builtin_wasm_relaxed_max_f64x2` | From 383be574e75fcd5f73d17ead100cfdd21ddf794a Mon Sep 17 00:00:00 2001 From: Yury Delendik Date: Mon, 1 Nov 2021 13:24:43 -0500 Subject: [PATCH 017/117] Report status of SpiderMonkey implemention --- .../relaxed-simd/ImplementationStatus.md | 40 ++++++++++--------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/proposals/relaxed-simd/ImplementationStatus.md b/proposals/relaxed-simd/ImplementationStatus.md index 7d8b534c3..d17c7e090 100644 --- a/proposals/relaxed-simd/ImplementationStatus.md +++ b/proposals/relaxed-simd/ImplementationStatus.md @@ -1,29 +1,31 @@ ## Implementation in LLVM and various engines -| Instruction | LLVM [1] | V8 [2] | SpiderMonkey | -|------------------------------------|----------------|--------------------|--------------| -| `relaxed i8x16.swizzle` | -mrelaxed-simd | :heavy_check_mark: | | -| `relaxed i32x4.trunc_f32x4_s` | -mrelaxed-simd | :heavy_check_mark: | | -| `relaxed i32x4.trunc_f32x4_u` | -mrelaxed-simd | :heavy_check_mark: | | -| `relaxed i32x4.trunc_f64x2_s_zero` | -mrelaxed-simd | :heavy_check_mark: | | -| `relaxed i32x4.trunc_f64x2_u_zero` | -mrelaxed-simd | :heavy_check_mark: | | -| `f32x4.fma` | -mrelaxed-simd | :heavy_check_mark: | | -| `f32x4.fms` | -mrelaxed-simd | :heavy_check_mark: | | -| `f64x2.fma` | -mrelaxed-simd | :heavy_check_mark: | | -| `f64x2.fms` | -mrelaxed-simd | :heavy_check_mark: | | -| `i8x16.laneselect` | -mrelaxed-simd | :heavy_check_mark: | | -| `i16x8.laneselect` | -mrelaxed-simd | :heavy_check_mark: | | -| `i32x4.laneselect` | -mrelaxed-simd | :heavy_check_mark: | | -| `i64x2.laneselect` | -mrelaxed-simd | :heavy_check_mark: | | -| `f32x4.min` | -mrelaxed-simd | :heavy_check_mark: | | -| `f32x4.max` | -mrelaxed-simd | :heavy_check_mark: | | -| `f64x2.min` | -mrelaxed-simd | :heavy_check_mark: | | -| `f64x2.max` | -mrelaxed-simd | :heavy_check_mark: | | +| Instruction | LLVM [1] | V8 [2] | SpiderMonkey [3] | +|------------------------------------|----------------|--------------------|--------------------| +| `relaxed i8x16.swizzle` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `relaxed i32x4.trunc_f32x4_s` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `relaxed i32x4.trunc_f32x4_u` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `relaxed i32x4.trunc_f64x2_s_zero` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `relaxed i32x4.trunc_f64x2_u_zero` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.fma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.fms` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.fma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.fms` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i8x16.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i16x8.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i32x4.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i64x2.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.min` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.min` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | [1] Tip of tree LLVM as of 2021-10-28 [2] V8 9.7.75 (only implemented on x64) +[3] SpiderMonkey as of 2021-10-18 implemented on x86, x64 and Aarch64 + ## Name of builtins in LLVM | Instruction | LLVM | From a7f00a6b2c1908829cb9689a6cc245c194cc8e07 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 1 Mar 2022 17:40:39 +0000 Subject: [PATCH 018/117] Remove fpenv from overview, add proposed spec text on Relaxed operations --- proposals/relaxed-simd/Overview.md | 56 +++++------------------------- 1 file changed, 8 insertions(+), 48 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 7f5378bd6..39dcd90aa 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -59,54 +59,14 @@ that instruction). One can imagine splitting an application's module and running them on multiple runtimes, where the runtimes produce different results - this can be surprising to the application. -Applications can specify their consistency needs using a new module-level -entity `fpenv` (name subject to change). A `fpenv` is defined in the `fpenv` -section of a module. All Relaxed SIMD instructions will take an additional -`varuint32` immediate, which is an index into the `fpenv` index space: - -```wast -(module - (func (param v128 v128 v128) - (f32x4.qfma $fpu (local.get 0) (local.get 1) (local.get 2)) ;; (1) - ;; ... - (f32x4.qfma $fpu (local.get 0) (local.get 1) (local.get 2)) ;; (2) - ) - (fpenv $fpu 0)) -``` - -In the example above, both `f32x4.qfma` instructions refer to the same `fpenv`, -and will get the same results when given the same input. - -A `fpenv` has a single `varuint32` attribute which is reserved for future -extensibility and must be `0` for now. The value of an `fpenv` is -non-deterministically computed when the module which declares it is -instantiated. This value determines the semantics of the instructions that -uses it as an immediate. - -As such, all the non-determinism of Relaxed SIMD is encapsulated in `fpenv`, -which makes Relaxed SIMD instructions themselves deterministic. - -Modules can import/export an `fpenv` to specify consistency requirements: - -```wast -;; module a -(module - (fpenv $fpu (export "foo") 0) - (func (param v128 v128 v128) - (f32x4.qfma $fpu (local.get 0) (local.get 1) (local.get 2)))) ;; (1) -``` - -```wast -;; module b -(module - (import "a" "foo" (fpenv $fpu 0)) - (func (param v128 v128 v128) - (f32x4.qfma $fpu (local.get 0) (local.get 1) (local.get 2)))) ;; (2) -``` - -In the above example, the same `fpenv` is exported by module `a`, and imported -by module `b`, so instructions `(1)` and `(2)` will consistently return the -same results when given the same inputs. +The specification is updated with the idea of "Relaxed operations": + +> Some operators are host-dependent, because the set of possible results may +> depend on properties of the host environment (such as hardware). Technically, +> each such operator produces a fixed-size list of sets of allowed values. For +> each execution of the operator in the same environment, only values from the +> set at the same position in the list are returned, i.e., each environment +> globally chooses a fixed projection for each operator. ## Instructions From 7f65a2a5e4237d9a61be2fb2b684b3ec5b84dee4 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 1 Mar 2022 17:49:17 +0000 Subject: [PATCH 019/117] Add Relaxed Rounding Q-format Multiplication to overview --- proposals/relaxed-simd/Overview.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 39dcd90aa..e9edac63f 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -184,10 +184,30 @@ def min_or_max(a : v128, b : v128, lanes : int, is_min : bool): result[i] = IMPLEMENTATION_DEFINED_ONE_OF(a[i], b[i]) else: result[i] = is_min ? min(a, b) : max(a, b) + return result ``` Where `IMPLEMENTATION_DEFINED_ONE_OF(x, y)` returns either `x` or `y`, depending on the implementation. +### Relaxed Rounding Q-format Multiplication + +- `i16x8.q15mulr_s(a: v128, b: v128) -> v128` + +Returns the multiplication of 2 fixed-point numbers in Q15 format. If both +inputs are `INT16_MIN`, the result overflows, and the return value is +implementation defined (either wrap around, or saturate). + +```python +def q15mulr(a, b): + result = [] + for i in range(lanes): + result[i] = sat_or_wrap((a[i] * b[i] + 0x4000) >> 15) + return result +``` + +Where `sat_or_wrap` either saturates or wraps around the input, depending on the +implementation. + ## Binary format All opcodes have the `0xfd` prefix (same as SIMD proposal), which are omitted in the table below. @@ -211,6 +231,7 @@ All opcodes have the `0xfd` prefix (same as SIMD proposal), which are omitted in | `f32x4.max` | 0xe2 | | `f64x2.min` | 0xd4 | | `f64x2.max` | 0xee | +| `i16x8.q15mulr_s` | ???? | Note: the opcodes are chosen to fit into the existing opcode space of the SIMD proposal, see [Binary encoding of SIMD](https://github.com/WebAssembly/simd/blob/main/proposals/simd/BinarySIMD.md), or a [table view of the same opcodes](https://github.com/WebAssembly/simd/blob/main/proposals/simd/NewOpcodes.md) for a list of existing opcodes. From 8f47f243bca871166e2a251af3443f17d32e84d4 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Fri, 4 Mar 2022 00:35:01 +0000 Subject: [PATCH 020/117] Restrict set of possible output values for relaxed rounding --- proposals/relaxed-simd/Overview.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index e9edac63f..4dd08ab76 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -195,19 +195,19 @@ Where `IMPLEMENTATION_DEFINED_ONE_OF(x, y)` returns either `x` or `y`, depending Returns the multiplication of 2 fixed-point numbers in Q15 format. If both inputs are `INT16_MIN`, the result overflows, and the return value is -implementation defined (either wrap around, or saturate). +implementation defined (either `INT16_MIN` or `INT16_MAX`). ```python def q15mulr(a, b): result = [] for i in range(lanes): - result[i] = sat_or_wrap((a[i] * b[i] + 0x4000) >> 15) + if (a[i] == INT16_MIN && b[i] == INT16_MIN): + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(INT16_MIN, INT16_MAX) + else: + result[i] = (a[i] * b[i] + 0x4000) >> 15 return result ``` -Where `sat_or_wrap` either saturates or wraps around the input, depending on the -implementation. - ## Binary format All opcodes have the `0xfd` prefix (same as SIMD proposal), which are omitted in the table below. From 8a1eb2fb67fb414fe3b13681963d8907acda79cd Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 1 Mar 2022 19:06:23 +0000 Subject: [PATCH 021/117] Update binary opcodes based on #51 --- proposals/relaxed-simd/Overview.md | 57 ++++++++++++++++++------------ 1 file changed, 34 insertions(+), 23 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 4dd08ab76..73f07191a 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -211,29 +211,36 @@ def q15mulr(a, b): ## Binary format All opcodes have the `0xfd` prefix (same as SIMD proposal), which are omitted in the table below. - -| instruction | opcode | -| ---------------------------------- | -------- | -| `relaxed i8x16.swizzle` | 0xa2 | -| `relaxed i32x4.trunc_f32x4_s` | 0xa5 | -| `relaxed i32x4.trunc_f32x4_u` | 0xa6 | -| `relaxed i32x4.trunc_f64x2_s_zero` | 0xc5 | -| `relaxed i32x4.trunc_f64x2_u_zero` | 0xc6 | -| `f32x4.fma` | 0xaf | -| `f32x4.fms` | 0xb0 | -| `f64x2.fma` | 0xcf | -| `f64x2.fms` | 0xd0 | -| `i8x16.laneselect` | 0xb2 | -| `i16x8.laneselect` | 0xb3 | -| `i32x4.laneselect` | 0xd2 | -| `i64x2.laneselect` | 0xd3 | -| `f32x4.min` | 0xb4 | -| `f32x4.max` | 0xe2 | -| `f64x2.min` | 0xd4 | -| `f64x2.max` | 0xee | -| `i16x8.q15mulr_s` | ???? | - -Note: the opcodes are chosen to fit into the existing opcode space of the SIMD proposal, see [Binary encoding of SIMD](https://github.com/WebAssembly/simd/blob/main/proposals/simd/BinarySIMD.md), or a [table view of the same opcodes](https://github.com/WebAssembly/simd/blob/main/proposals/simd/NewOpcodes.md) for a list of existing opcodes. +Opcodes `0x100` to `0x12F` (32 opcodes) are reserved for this proposal. + +Note: "prototype opcode" refers to the opcodes that were used in prototyping, which +where chosen to fit into the holes in the opcode space of SIMD proposal. Going +forward, the opcodes for relaxed-simd specification will be the ones in the +"opcode" column, and it will take some time for tools and engines to update. + +| instruction | opcode | prototype opcode | +| ----------------------------------| -------------- | ---------------- | +| `relaxed i8x16.swizzle` | 0x100 | 0xa2 | +| `relaxed i32x4.trunc_f32x4_s` | 0x101 | 0xa5 | +| `relaxed i32x4.trunc_f32x4_u` | 0x102 | 0xa6 | +| `relaxed i32x4.trunc_f64x2_s_zero`| 0x103 | 0xc5 | +| `relaxed i32x4.trunc_f64x2_u_zero`| 0x104 | 0xc6 | +| `f32x4.fma` | 0x105 | 0xaf | +| `f32x4.fms` | 0x106 | 0xb0 | +| `f64x2.fma` | 0x107 | 0xcf | +| `f64x2.fms` | 0x108 | 0xd0 | +| `i8x16.laneselect` | 0x109 | 0xb2 | +| `i16x8.laneselect` | 0x10a | 0xb3 | +| `i32x4.laneselect` | 0x10b | 0xd2 | +| `i64x2.laneselect` | 0x10c | 0xd3 | +| `f32x4.min` | 0x10d | 0xb4 | +| `f32x4.max` | 0x10e | 0xe2 | +| `f64x2.min` | 0x10f | 0xd4 | +| `f64x2.max` | 0x110 | 0xee | +| `i16x8.q15mulr_s` | 0x111 | unimplemented | +| Reserved for dot product | 0x112 | unimplemented | +| Reserved for dot product | 0x113 | unimplemented | +| Reserved | 0x114 - 0x12F | | ## References @@ -241,4 +248,8 @@ Note: the opcodes are chosen to fit into the existing opcode space of the SIMD p [presentation](https://docs.google.com/presentation/d/1Qnx0nbNTRYhMONLuKyygEduCXNOv3xtWODfXfYokx1Y/edit?usp=sharing) and [meeting notes](https://github.com/WebAssembly/meetings/blob/master/main/2021/CG-03-16.md) +- Poll for phase 2 + [slides](https://docs.google.com/presentation/d/1zyRqfgGU7HdoVw9QiKaVYifozbytPhNLHUW9jQjPzLk/edit?usp=sharing) + and [meeting + notes](https://github.com/WebAssembly/meetings/blob/main/main/2021/CG-11-09.md#update-on-relaxed-simd-fpenv-discussions-and-poll-for-phase-2-zhi-an-ng-15-min) - [SIMD proposal](https://github.com/WebAssembly/simd) From 5c175d8be92fdfb066f295f97b46d19bbebca3cb Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Fri, 4 Mar 2022 19:16:22 +0000 Subject: [PATCH 022/117] Fix reserved dot products instructions and add bfloat16 --- proposals/relaxed-simd/Overview.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 73f07191a..4e0b475a3 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -238,9 +238,9 @@ forward, the opcodes for relaxed-simd specification will be the ones in the | `f64x2.min` | 0x10f | 0xd4 | | `f64x2.max` | 0x110 | 0xee | | `i16x8.q15mulr_s` | 0x111 | unimplemented | -| Reserved for dot product | 0x112 | unimplemented | -| Reserved for dot product | 0x113 | unimplemented | -| Reserved | 0x114 - 0x12F | | +| Reserved for dot product | 0x112 - 0x115 | unimplemented | +| Reserved for bfloat16 dot product | 0x116 | unimplemented | +| Reserved | 0x117 - 0x12F | | ## References From fe473a7626219ed85f000062c75f2ccb33cb60d3 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 1 Mar 2022 01:06:22 +0000 Subject: [PATCH 023/117] Copy "either" result pattern from threads proposal "either" allows us to assert that the a value is in a set of expected values. This is copied from threads proposal and updated accordingly to compile. --- interpreter/script/js.ml | 17 +++++++++++-- interpreter/script/run.ml | 48 ++++++++++++++++++++++-------------- interpreter/script/script.ml | 1 + interpreter/text/arrange.ml | 3 ++- interpreter/text/lexer.mll | 1 + interpreter/text/parser.mly | 5 ++-- 6 files changed, 52 insertions(+), 23 deletions(-) diff --git a/interpreter/script/js.ml b/interpreter/script/js.ml index 093da2463..9d8b3cc91 100644 --- a/interpreter/script/js.ml +++ b/interpreter/script/js.ml @@ -278,7 +278,7 @@ let run ts at = [], [] let assert_return ress ts at = - let test res = + let rec test res = let nan_bitmask_of = function | CanonicalNan -> abs_mask_of (* must only differ from the canonical NaN in its sign bit *) | ArithmeticNan -> canonical_nan_of (* can be any NaN that's one everywhere the canonical NaN is one *) @@ -374,6 +374,17 @@ let assert_return ress ts at = [ Call (is_ref_idx @@ at) @@ at; Test (Values.I32 I32Op.Eqz) @@ at; BrIf (0l @@ at) @@ at ] + | EitherResult ress -> + [ Block (ValBlockType None, + List.map (fun res -> + Block (ValBlockType None, + test res @ + [Br (1l @@ res.at) @@ res.at] + ) @@ res.at + ) ress @ + [Br (1l @@ at) @@ at] + ) @@ at + ] in [], List.flatten (List.rev_map test ress) let wrap item_name wrap_action wrap_assertion at = @@ -514,11 +525,13 @@ let of_ref_pat = function | RefPat r -> of_ref r.it | RefTypePat t -> "\"ref." ^ string_of_refed_type t ^ "\"" -let of_result res = +let rec of_result res = match res.it with | NumResult np -> of_num_pat np | VecResult vp -> of_vec_pat vp | RefResult rp -> of_ref_pat rp + | EitherResult ress -> + "[" ^ String.concat ", " (List.map of_result ress) ^ "]" let rec of_definition def = match def.it with diff --git a/interpreter/script/run.ml b/interpreter/script/run.ml index e0019d84a..8bfa8fdd7 100644 --- a/interpreter/script/run.ml +++ b/interpreter/script/run.ml @@ -250,13 +250,16 @@ let string_of_nan = function | CanonicalNan -> "nan:canonical" | ArithmeticNan -> "nan:arithmetic" -let type_of_result r = - match r with - | NumResult (NumPat n) -> Types.NumType (Values.type_of_num n.it) - | NumResult (NanPat n) -> Types.NumType (Values.type_of_num n.it) - | VecResult (VecPat _) -> Types.VecType Types.V128Type - | RefResult (RefPat r) -> Types.RefType (Values.type_of_ref r.it) - | RefResult (RefTypePat t) -> Types.RefType t +let rec type_of_result r = + match r.it with + | NumResult (NumPat n) -> Some (Types.NumType (Values.type_of_num n.it)) + | NumResult (NanPat n) -> Some (Types.NumType (Values.type_of_num n.it)) + | VecResult (VecPat _) -> Some (Types.VecType Types.V128Type) + | RefResult (RefPat r) -> Some (Types.RefType (Values.type_of_ref r.it)) + | RefResult (RefTypePat t) -> Some (Types.RefType t) + | EitherResult rs -> + let ts = List.map type_of_result rs in + List.fold_left (fun t1 t2 -> if t1 = t2 then t1 else None) (List.hd ts) ts let string_of_num_pat (p : num_pat) = match p with @@ -276,20 +279,30 @@ let string_of_ref_pat (p : ref_pat) = | RefPat r -> Values.string_of_ref r.it | RefTypePat t -> Types.string_of_refed_type t -let string_of_result r = - match r with +let rec string_of_result r = + match r.it with | NumResult np -> string_of_num_pat np | VecResult vp -> string_of_vec_pat vp | RefResult rp -> string_of_ref_pat rp + | EitherResult rs -> + "(" ^ String.concat " | " (List.map string_of_result rs) ^ ")" let string_of_results = function | [r] -> string_of_result r | rs -> "[" ^ String.concat " " (List.map string_of_result rs) ^ "]" +let string_of_value_type_opt = function + | Some t -> Types.string_of_value_type t + | None -> "?" + +let string_of_value_type_opts = function + | [t] -> string_of_value_type_opt t + | ts -> "[" ^ String.concat " " (List.map string_of_value_type_opt ts) ^ "]" + let print_results rs = let ts = List.map type_of_result rs in Printf.printf "%s : %s\n" - (string_of_results rs) (Types.string_of_value_types ts); + (string_of_results rs) (string_of_value_type_opts ts); flush_all () @@ -368,7 +381,6 @@ let run_action act : Values.value list = | None -> Assert.error act.at "undefined export" ) - let assert_nan_pat n nan = let open Values in match n, nan.it with @@ -409,18 +421,19 @@ let assert_ref_pat r p = | ExternRef _, RefTypePat Types.ExternRefType -> true | _ -> false -let assert_pat v r = +let rec match_result at v r = let open Values in - match v, r with - | Num n, NumResult np -> assert_num_pat n np + match v, r.it with + | Num n, NumResult n' -> assert_num_pat n n' | Vec v, VecResult vp -> assert_vec_pat v vp - | Ref r, RefResult rp -> assert_ref_pat r rp + | Ref r, RefResult r' -> assert_ref_pat r r' + | _, EitherResult rs -> List.exists (match_result at v) rs | _, _ -> false let assert_result at got expect = if List.length got <> List.length expect || - List.exists2 (fun v r -> not (assert_pat v r)) got expect + not (List.for_all2 (match_result at) got expect) then begin print_string "Result: "; print_values got; print_string "Expect: "; print_results expect; @@ -487,8 +500,7 @@ let run_assertion ass = | AssertReturn (act, rs) -> trace ("Asserting return..."); let got_vs = run_action act in - let expect_rs = List.map (fun r -> r.it) rs in - assert_result ass.at got_vs expect_rs + assert_result ass.at got_vs rs | AssertTrap (act, re) -> trace ("Asserting trap..."); diff --git a/interpreter/script/script.ml b/interpreter/script/script.ml index 4c4f550f2..4004cef61 100644 --- a/interpreter/script/script.ml +++ b/interpreter/script/script.ml @@ -36,6 +36,7 @@ and result' = | NumResult of num_pat | VecResult of vec_pat | RefResult of ref_pat + | EitherResult of result list type assertion = assertion' Source.phrase and assertion' = diff --git a/interpreter/text/arrange.ml b/interpreter/text/arrange.ml index cdcd4f84d..fe99abdad 100644 --- a/interpreter/text/arrange.ml +++ b/interpreter/text/arrange.ml @@ -737,11 +737,12 @@ let ref_pat = function | RefPat r -> ref_ r.it | RefTypePat t -> Node ("ref." ^ refed_type t, []) -let result mode res = +let rec result mode res = match res.it with | NumResult np -> num_pat mode np | VecResult vp -> vec_pat mode vp | RefResult rp -> ref_pat rp + | EitherResult ress -> Node ("either", List.map (result mode) ress) let assertion mode ass = match ass.it with diff --git a/interpreter/text/lexer.mll b/interpreter/text/lexer.mll index c5d759fb8..fab9048eb 100644 --- a/interpreter/text/lexer.mll +++ b/interpreter/text/lexer.mll @@ -480,6 +480,7 @@ rule token = parse | "assert_exhaustion" { ASSERT_EXHAUSTION } | "nan:canonical" { NAN Script.CanonicalNan } | "nan:arithmetic" { NAN Script.ArithmeticNan } + | "either" { EITHER } | "input" { INPUT } | "output" { OUTPUT } diff --git a/interpreter/text/parser.mly b/interpreter/text/parser.mly index e91c3fe86..9068bb024 100644 --- a/interpreter/text/parser.mly +++ b/interpreter/text/parser.mly @@ -227,7 +227,7 @@ let inline_type_explicit (c : context) x ft at = %token SCRIPT REGISTER INVOKE GET %token ASSERT_MALFORMED ASSERT_INVALID ASSERT_SOFT_INVALID ASSERT_UNLINKABLE %token ASSERT_RETURN ASSERT_TRAP ASSERT_EXHAUSTION -%token NAN +%token NAN EITHER %token INPUT OUTPUT %token EOF @@ -1157,7 +1157,8 @@ result : if V128.num_lanes $3 <> List.length $4 then error (at ()) "wrong number of lane literals"; VecResult (VecPat (Values.V128 ($3, List.map (fun lit -> lit $3) $4))) @@ at () - } + } + | LPAR EITHER result result_list RPAR { EitherResult ($3 :: $4) @@ at () } result_list : | /* empty */ { [] } From 8da282571655e1ed06432e8b31a75e43128b87a6 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 14 Mar 2022 20:43:37 +0000 Subject: [PATCH 024/117] Update instruction names in opcode table based on #42 --- proposals/relaxed-simd/Overview.md | 36 +++++++++++++++--------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 4e0b475a3..27c6702c0 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -220,24 +220,24 @@ forward, the opcodes for relaxed-simd specification will be the ones in the | instruction | opcode | prototype opcode | | ----------------------------------| -------------- | ---------------- | -| `relaxed i8x16.swizzle` | 0x100 | 0xa2 | -| `relaxed i32x4.trunc_f32x4_s` | 0x101 | 0xa5 | -| `relaxed i32x4.trunc_f32x4_u` | 0x102 | 0xa6 | -| `relaxed i32x4.trunc_f64x2_s_zero`| 0x103 | 0xc5 | -| `relaxed i32x4.trunc_f64x2_u_zero`| 0x104 | 0xc6 | -| `f32x4.fma` | 0x105 | 0xaf | -| `f32x4.fms` | 0x106 | 0xb0 | -| `f64x2.fma` | 0x107 | 0xcf | -| `f64x2.fms` | 0x108 | 0xd0 | -| `i8x16.laneselect` | 0x109 | 0xb2 | -| `i16x8.laneselect` | 0x10a | 0xb3 | -| `i32x4.laneselect` | 0x10b | 0xd2 | -| `i64x2.laneselect` | 0x10c | 0xd3 | -| `f32x4.min` | 0x10d | 0xb4 | -| `f32x4.max` | 0x10e | 0xe2 | -| `f64x2.min` | 0x10f | 0xd4 | -| `f64x2.max` | 0x110 | 0xee | -| `i16x8.q15mulr_s` | 0x111 | unimplemented | +| `i8x16.relaxed_swizzle` | 0x100 | 0xa2 | +| `i32x4.relaxed_trunc_f32x4_s` | 0x101 | 0xa5 | +| `i32x4.relaxed_trunc_f32x4_u` | 0x102 | 0xa6 | +| `i32x4.relaxed_trunc_f64x2_s_zero`| 0x103 | 0xc5 | +| `i32x4.relaxed_trunc_f64x2_u_zero`| 0x104 | 0xc6 | +| `f32x4.relaxed_fma` | 0x105 | 0xaf | +| `f32x4.relaxed_fms` | 0x106 | 0xb0 | +| `f64x2.relaxed_fma` | 0x107 | 0xcf | +| `f64x2.relaxed_fms` | 0x108 | 0xd0 | +| `i8x16.relaxed_laneselect` | 0x109 | 0xb2 | +| `i16x8.relaxed_laneselect` | 0x10a | 0xb3 | +| `i32x4.relaxed_laneselect` | 0x10b | 0xd2 | +| `i64x2.relaxed_laneselect` | 0x10c | 0xd3 | +| `f32x4.relaxed_min` | 0x10d | 0xb4 | +| `f32x4.relaxed_max` | 0x10e | 0xe2 | +| `f64x2.relaxed_min` | 0x10f | 0xd4 | +| `f64x2.relaxed_max` | 0x110 | 0xee | +| `i16x8.relaxed_q15mulr_s` | 0x111 | unimplemented | | Reserved for dot product | 0x112 - 0x115 | unimplemented | | Reserved for bfloat16 dot product | 0x116 | unimplemented | | Reserved | 0x117 - 0x12F | | From dafba4f9215ecc2cdb6a448867d4dfbc643a308d Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 9 Mar 2022 23:24:24 +0000 Subject: [PATCH 025/117] Add tests for relaxed simd instructions Test cases are not exhaustive and only exercises edge cases (where results differ across hardware). No implementation in the interpreter, only parsing, encoding, and decoding is supported. --- interpreter/binary/encode.ml | 20 ++++ interpreter/syntax/ast.ml | 9 ++ interpreter/syntax/free.ml | 2 +- interpreter/syntax/operators.ml | 19 ++++ interpreter/text/arrange.ml | 17 +++ interpreter/text/lexer.mll | 20 ++++ interpreter/valid/valid.ml | 4 + .../relaxed-simd/i16x8_relaxed_q15mulr_s.wast | 13 +++ .../relaxed-simd/i32x4_relaxed_trunc.wast | 54 +++++++++ .../relaxed-simd/i8x16_relaxed_swizzle.wast | 25 +++++ test/core/relaxed-simd/relaxed_fma_fms.wast | 66 +++++++++++ .../core/relaxed-simd/relaxed_laneselect.wast | 43 ++++++++ test/core/relaxed-simd/relaxed_min_max.wast | 104 ++++++++++++++++++ 13 files changed, 395 insertions(+), 1 deletion(-) create mode 100644 test/core/relaxed-simd/i16x8_relaxed_q15mulr_s.wast create mode 100644 test/core/relaxed-simd/i32x4_relaxed_trunc.wast create mode 100644 test/core/relaxed-simd/i8x16_relaxed_swizzle.wast create mode 100644 test/core/relaxed-simd/relaxed_fma_fms.wast create mode 100644 test/core/relaxed-simd/relaxed_laneselect.wast create mode 100644 test/core/relaxed-simd/relaxed_min_max.wast diff --git a/interpreter/binary/encode.ml b/interpreter/binary/encode.ml index 254b341b2..3f735b08c 100644 --- a/interpreter/binary/encode.ml +++ b/interpreter/binary/encode.ml @@ -560,6 +560,7 @@ struct | VecBinary (V128 (I8x16 V128Op.MaxS)) -> vecop 0x78l | VecBinary (V128 (I8x16 V128Op.MaxU)) -> vecop 0x79l | VecBinary (V128 (I8x16 V128Op.AvgrU)) -> vecop 0x7bl + | VecBinary (V128 (I8x16 V128Op.RelaxedSwizzle)) -> vecop 0x100l | VecBinary (V128 (I16x8 V128Op.NarrowS)) -> vecop 0x85l | VecBinary (V128 (I16x8 V128Op.NarrowU)) -> vecop 0x86l | VecBinary (V128 (I16x8 V128Op.Add)) -> vecop 0x8el @@ -579,6 +580,7 @@ struct | VecBinary (V128 (I16x8 V128Op.ExtMulLowU)) -> vecop 0x9el | VecBinary (V128 (I16x8 V128Op.ExtMulHighU)) -> vecop 0x9fl | VecBinary (V128 (I16x8 V128Op.Q15MulRSatS)) -> vecop 0x82l + | VecBinary (V128 (I16x8 V128Op.RelaxedQ15MulRS)) -> vecop 0x111l | VecBinary (V128 (I32x4 V128Op.Add)) -> vecop 0xael | VecBinary (V128 (I32x4 V128Op.Sub)) -> vecop 0xb1l | VecBinary (V128 (I32x4 V128Op.MinS)) -> vecop 0xb6l @@ -606,6 +608,8 @@ struct | VecBinary (V128 (F32x4 V128Op.Max)) -> vecop 0xe9l | VecBinary (V128 (F32x4 V128Op.Pmin)) -> vecop 0xeal | VecBinary (V128 (F32x4 V128Op.Pmax)) -> vecop 0xebl + | VecBinary (V128 (F32x4 V128Op.RelaxedMin)) -> vecop 0x10dl + | VecBinary (V128 (F32x4 V128Op.RelaxedMax)) -> vecop 0x10el | VecBinary (V128 (F64x2 V128Op.Add)) -> vecop 0xf0l | VecBinary (V128 (F64x2 V128Op.Sub)) -> vecop 0xf1l | VecBinary (V128 (F64x2 V128Op.Mul)) -> vecop 0xf2l @@ -614,8 +618,20 @@ struct | VecBinary (V128 (F64x2 V128Op.Max)) -> vecop 0xf5l | VecBinary (V128 (F64x2 V128Op.Pmin)) -> vecop 0xf6l | VecBinary (V128 (F64x2 V128Op.Pmax)) -> vecop 0xf7l + | VecBinary (V128 (F64x2 V128Op.RelaxedMin)) -> vecop 0x10fl + | VecBinary (V128 (F64x2 V128Op.RelaxedMax)) -> vecop 0x110l | VecBinary (V128 _) -> assert false + | VecTernary (V128 (F32x4 V128Op.RelaxedFma)) -> vecop 0x105l + | VecTernary (V128 (F32x4 V128Op.RelaxedFms)) -> vecop 0x106l + | VecTernary (V128 (F64x2 V128Op.RelaxedFma)) -> vecop 0x107l + | VecTernary (V128 (F64x2 V128Op.RelaxedFms)) -> vecop 0x108l + | VecTernary (V128 (I8x16 V128Op.RelaxedLaneselect)) -> vecop 0x109l + | VecTernary (V128 (I16x8 V128Op.RelaxedLaneselect)) -> vecop 0x10al + | VecTernary (V128 (I32x4 V128Op.RelaxedLaneselect)) -> vecop 0x10bl + | VecTernary (V128 (I64x2 V128Op.RelaxedLaneselect)) -> vecop 0x10cl + | VecTernary (V128 _) -> . + | VecConvert (V128 (I8x16 _)) -> assert false | VecConvert (V128 (I16x8 V128Op.ExtendLowS)) -> vecop 0x87l | VecConvert (V128 (I16x8 V128Op.ExtendHighS)) -> vecop 0x88l @@ -634,6 +650,10 @@ struct | VecConvert (V128 (I32x4 V128Op.TruncSatUF32x4)) -> vecop 0xf9l | VecConvert (V128 (I32x4 V128Op.TruncSatSZeroF64x2)) -> vecop 0xfcl | VecConvert (V128 (I32x4 V128Op.TruncSatUZeroF64x2)) -> vecop 0xfdl + | VecConvert (V128 (I32x4 V128Op.RelaxedTruncSF32x4)) -> vecop 0x101l + | VecConvert (V128 (I32x4 V128Op.RelaxedTruncUF32x4)) -> vecop 0x102l + | VecConvert (V128 (I32x4 V128Op.RelaxedTruncSZeroF64x2)) -> vecop 0x103l + | VecConvert (V128 (I32x4 V128Op.RelaxedTruncUZeroF64x2)) -> vecop 0x104l | VecConvert (V128 (I64x2 V128Op.ExtendLowS)) -> vecop 0xc7l | VecConvert (V128 (I64x2 V128Op.ExtendHighS)) -> vecop 0xc8l | VecConvert (V128 (I64x2 V128Op.ExtendLowU)) -> vecop 0xc9l diff --git a/interpreter/syntax/ast.ml b/interpreter/syntax/ast.ml index b5e3ae6ee..c5f9b5c1f 100644 --- a/interpreter/syntax/ast.ml +++ b/interpreter/syntax/ast.ml @@ -61,13 +61,19 @@ struct | AddSatS | AddSatU | SubSatS | SubSatU | DotS | Q15MulRSatS | ExtMulLowS | ExtMulHighS | ExtMulLowU | ExtMulHighU | Swizzle | Shuffle of int list | NarrowS | NarrowU + | RelaxedSwizzle | RelaxedQ15MulRS type fbinop = Add | Sub | Mul | Div | Min | Max | Pmin | Pmax + | RelaxedMin | RelaxedMax + type iternop = RelaxedLaneselect + type fternop = RelaxedFma | RelaxedFms type irelop = Eq | Ne | LtS | LtU | LeS | LeU | GtS | GtU | GeS | GeU type frelop = Eq | Ne | Lt | Le | Gt | Ge type icvtop = ExtendLowS | ExtendLowU | ExtendHighS | ExtendHighU | ExtAddPairwiseS | ExtAddPairwiseU | TruncSatSF32x4 | TruncSatUF32x4 | TruncSatSZeroF64x2 | TruncSatUZeroF64x2 + | RelaxedTruncSF32x4 | RelaxedTruncUF32x4 + | RelaxedTruncSZeroF64x2 | RelaxedTruncUZeroF64x2 type fcvtop = DemoteZeroF64x2 | PromoteLowF32x4 | ConvertSI32x4 | ConvertUI32x4 type ishiftop = Shl | ShrS | ShrU @@ -81,6 +87,7 @@ struct type testop = (itestop, itestop, itestop, itestop, void, void) V128.laneop type unop = (iunop, iunop, iunop, iunop, funop, funop) V128.laneop type binop = (ibinop, ibinop, ibinop, ibinop, fbinop, fbinop) V128.laneop + type ternop = (iternop, iternop, iternop, iternop, fternop, fternop) V128.laneop type relop = (irelop, irelop, irelop, irelop, frelop, frelop) V128.laneop type cvtop = (icvtop, icvtop, icvtop, icvtop, fcvtop, fcvtop) V128.laneop type shiftop = (ishiftop, ishiftop, ishiftop, ishiftop, void, void) V128.laneop @@ -105,6 +112,7 @@ type vec_testop = (V128Op.testop) Values.vecop type vec_relop = (V128Op.relop) Values.vecop type vec_unop = (V128Op.unop) Values.vecop type vec_binop = (V128Op.binop) Values.vecop +type vec_ternop = (V128Op.ternop) Values.vecop type vec_cvtop = (V128Op.cvtop) Values.vecop type vec_shiftop = (V128Op.shiftop) Values.vecop type vec_bitmaskop = (V128Op.bitmaskop) Values.vecop @@ -188,6 +196,7 @@ and instr' = | VecCompare of vec_relop (* vector comparison *) | VecUnary of vec_unop (* unary vector operator *) | VecBinary of vec_binop (* binary vector operator *) + | VecTernary of vec_ternop (* ternary vector operator *) | VecConvert of vec_cvtop (* vector conversion *) | VecShift of vec_shiftop (* vector shifts *) | VecBitmask of vec_bitmaskop (* vector masking *) diff --git a/interpreter/syntax/free.ml b/interpreter/syntax/free.ml index 78c09baf3..b70ac7969 100644 --- a/interpreter/syntax/free.ml +++ b/interpreter/syntax/free.ml @@ -87,7 +87,7 @@ let rec instr (e : instr) = | VecLoad _ | VecStore _ | VecLoadLane _ | VecStoreLane _ | MemorySize | MemoryGrow | MemoryCopy | MemoryFill -> memories zero - | VecConst _ | VecTest _ | VecUnary _ | VecBinary _ | VecCompare _ + | VecConst _ | VecTest _ | VecUnary _ | VecBinary _ | VecTernary _ | VecCompare _ | VecConvert _ | VecShift _ | VecBitmask _ | VecTestBits _ | VecUnaryBits _ | VecBinaryBits _ | VecTernaryBits _ | VecSplat _ | VecExtract _ | VecReplace _ -> diff --git a/interpreter/syntax/operators.ml b/interpreter/syntax/operators.ml index 296bb1e77..fc135534a 100644 --- a/interpreter/syntax/operators.ml +++ b/interpreter/syntax/operators.ml @@ -500,3 +500,22 @@ let f64x2_pmax = VecBinary (V128 (F64x2 V128Op.Pmax)) let f64x2_promote_low_f32x4 = VecConvert (V128 (F64x2 V128Op.PromoteLowF32x4)) let f64x2_convert_low_i32x4_s = VecConvert (V128 (F64x2 V128Op.ConvertSI32x4)) let f64x2_convert_low_i32x4_u = VecConvert (V128 (F64x2 V128Op.ConvertUI32x4)) + +let i8x16_relaxed_swizzle = VecBinary (V128 (I8x16 V128Op.RelaxedSwizzle)) +let i8x16_relaxed_laneselect = VecTernary (V128 (I8x16 V128Op.RelaxedLaneselect)) +let i16x8_relaxed_q15mulr_s = VecBinary (V128 (I16x8 V128Op.RelaxedQ15MulRS)) +let i16x8_relaxed_laneselect = VecTernary (V128 (I16x8 V128Op.RelaxedLaneselect)) +let i32x4_relaxed_trunc_f32x4_s = VecConvert (V128 (I32x4 V128Op.RelaxedTruncSF32x4)) +let i32x4_relaxed_trunc_f32x4_u = VecConvert (V128 (I32x4 V128Op.RelaxedTruncUF32x4)) +let i32x4_relaxed_trunc_f64x2_s_zero = VecConvert (V128 (I32x4 V128Op.RelaxedTruncSZeroF64x2)) +let i32x4_relaxed_trunc_f64x2_u_zero = VecConvert (V128 (I32x4 V128Op.RelaxedTruncUZeroF64x2)) +let i32x4_relaxed_laneselect = VecTernary (V128 (I32x4 V128Op.RelaxedLaneselect)) +let i64x2_relaxed_laneselect = VecTernary (V128 (I64x2 V128Op.RelaxedLaneselect)) +let f32x4_relaxed_fma = VecTernary (V128 (F32x4 V128Op.RelaxedFma)) +let f32x4_relaxed_fms = VecTernary (V128 (F32x4 V128Op.RelaxedFms)) +let f32x4_relaxed_min = VecBinary (V128 (F32x4 V128Op.RelaxedMin)) +let f32x4_relaxed_max = VecBinary (V128 (F32x4 V128Op.RelaxedMax)) +let f64x2_relaxed_fma = VecTernary (V128 (F64x2 V128Op.RelaxedFma)) +let f64x2_relaxed_fms = VecTernary (V128 (F64x2 V128Op.RelaxedFms)) +let f64x2_relaxed_min = VecBinary (V128 (F64x2 V128Op.RelaxedMin)) +let f64x2_relaxed_max = VecBinary (V128 (F64x2 V128Op.RelaxedMax)) diff --git a/interpreter/text/arrange.ml b/interpreter/text/arrange.ml index fe99abdad..4db4fb11e 100644 --- a/interpreter/text/arrange.ml +++ b/interpreter/text/arrange.ml @@ -255,6 +255,11 @@ struct | NarrowU -> "narrow_i" ^ double xxxx ^ "_u" | Shuffle is -> "shuffle " ^ String.concat " " (List.map nat is) | Swizzle -> "swizzle" + | RelaxedSwizzle -> "relaxed_swizzle" + | RelaxedQ15MulRS -> "relaxed_q15mulr_s" + + let iternop xxxx (op : iternop) = match op with + | RelaxedLaneselect -> "relaxed_laneselect" let fbinop xxxx (op : fbinop) = match op with | Add -> "add" @@ -265,6 +270,12 @@ struct | Max -> "max" | Pmin -> "pmin" | Pmax -> "pmax" + | RelaxedMin -> "relaxed_min" + | RelaxedMax -> "relaxed_max" + + let fternop xxxx (op : fternop) = match op with + | RelaxedFma -> "relaxed_fma" + | RelaxedFms -> "relaxed_fms" let irelop xxxx (op : irelop) = match op with | Eq -> "eq" @@ -297,6 +308,10 @@ struct | TruncSatUF32x4 -> "trunc_sat_f32x4_u" | TruncSatSZeroF64x2 -> "trunc_sat_f64x2_s_zero" | TruncSatUZeroF64x2 -> "trunc_sat_f64x2_u_zero" + | RelaxedTruncSF32x4 -> "relaxed_trunc_f32x4_s" + | RelaxedTruncUF32x4 -> "relaxed_trunc_f32x4_u" + | RelaxedTruncSZeroF64x2 -> "relaxed_trunc_f64x2_s_zero" + | RelaxedTruncUZeroF64x2 -> "relaxed_trunc_f64x2_u_zero" let fcvtop xxxx (op : fcvtop) = match op with | DemoteZeroF64x2 -> "demote_f64x2_zero" @@ -376,6 +391,7 @@ let cvtop = oper (IntOp.cvtop, FloatOp.cvtop) let vec_unop = vec_shape_oper (V128Op.iunop, V128Op.iunop, V128Op.funop) let vec_binop = vec_shape_oper (V128Op.ibinop, V128Op.ibinop, V128Op.fbinop) +let vec_ternop = vec_shape_oper (V128Op.iternop, V128Op.iternop, V128Op.fternop) let vec_testop = vec_shape_oper (V128Op.itestop, V128Op.itestop, V128Op.voidop) let vec_relop = vec_shape_oper (V128Op.irelop, V128Op.irelop, V128Op.frelop) let vec_cvtop = vec_shape_oper (V128Op.icvtop, V128Op.icvtop, V128Op.fcvtop) @@ -491,6 +507,7 @@ let rec instr e = | VecTest op -> vec_testop op, [] | VecUnary op -> vec_unop op, [] | VecBinary op -> vec_binop op, [] + | VecTernary op -> vec_ternop op, [] | VecCompare op -> vec_relop op, [] | VecConvert op -> vec_cvtop op, [] | VecShift op -> vec_shiftop op, [] diff --git a/interpreter/text/lexer.mll b/interpreter/text/lexer.mll index fab9048eb..8cce2a27d 100644 --- a/interpreter/text/lexer.mll +++ b/interpreter/text/lexer.mll @@ -674,6 +674,26 @@ rule token = parse (v128op s i8x16_replace_lane i16x8_replace_lane i32x4_replace_lane i64x2_replace_lane f32x4_replace_lane f64x2_replace_lane) } + | "i8x16.relaxed_swizzle" { VEC_BINARY i8x16_relaxed_swizzle } + | "i8x16.relaxed_swizzle" { VEC_BINARY i8x16_relaxed_swizzle } + | "i32x4.relaxed_trunc_f32x4_"(sign as s) + { VEC_UNARY (ext s i32x4_relaxed_trunc_f32x4_s i32x4_relaxed_trunc_f32x4_u) } + | "i32x4.relaxed_trunc_f64x2_"(sign as s)"_zero" + { VEC_UNARY (ext s i32x4_relaxed_trunc_f64x2_s_zero i32x4_relaxed_trunc_f64x2_u_zero) } + | (v128_float_shape as s)".relaxed_fma" + { VEC_UNARY (v128floatop s f32x4_relaxed_fma f64x2_relaxed_fma) } + | (v128_float_shape as s)".relaxed_fms" + { VEC_UNARY (v128floatop s f32x4_relaxed_fms f64x2_relaxed_fms) } + | (v128_int_shape as s)".relaxed_laneselect" + { VEC_TERNARY + (v128intop s i8x16_relaxed_laneselect i16x8_relaxed_laneselect + i32x4_relaxed_laneselect i64x2_relaxed_laneselect)} + | (v128_float_shape as s)".relaxed_min" + { VEC_UNARY (v128floatop s f32x4_relaxed_min f64x2_relaxed_min) } + | (v128_float_shape as s)".relaxed_max" + { VEC_UNARY (v128floatop s f32x4_relaxed_max f64x2_relaxed_max) } + | "i16x8.relaxed_q15mulr_s" { VEC_BINARY i16x8_relaxed_q15mulr_s } + | name as s { VAR s } | ";;"utf8_no_nl*eof { EOF } diff --git a/interpreter/valid/valid.ml b/interpreter/valid/valid.ml index 780404e50..34d99b782 100644 --- a/interpreter/valid/valid.ml +++ b/interpreter/valid/valid.ml @@ -463,6 +463,10 @@ let rec check_instr (c : context) (e : instr) (s : infer_result_type) : op_type let t = VecType (type_vec binop) in [t; t] --> [t] + | VecTernary ternop -> + let t = VecType (type_vec ternop) in + [t; t; t] --> [t] + | VecCompare relop -> let t = VecType (type_vec relop) in [t; t] --> [t] diff --git a/test/core/relaxed-simd/i16x8_relaxed_q15mulr_s.wast b/test/core/relaxed-simd/i16x8_relaxed_q15mulr_s.wast new file mode 100644 index 000000000..9dcb54de2 --- /dev/null +++ b/test/core/relaxed-simd/i16x8_relaxed_q15mulr_s.wast @@ -0,0 +1,13 @@ +;; Tests for i16x8.relaxed_q15mulr_s. +(module + (func (export "i16x8.relaxed_q15mulr_s") (param v128 v128) (result v128) (i16x8.relaxed_q15mulr_s (local.get 0) (local.get 1))) +) + +;; INT16_MIN = -32768 +(assert_return (invoke "i16x8.relaxed_q15mulr_s" + (v128.const i16x8 -32768 -32767 32767 0 0 0 0 0) + (v128.const i16x8 -32768 -32768 32767 0 0 0 0 0)) + ;; overflows, return either INT16_MIN or INT16_MAX + (either (v128.const i16x8 -32768 32767 32766 0 0 0 0 0) + (v128.const i16x8 32767 32767 32766 0 0 0 0 0))) + diff --git a/test/core/relaxed-simd/i32x4_relaxed_trunc.wast b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast new file mode 100644 index 000000000..55f923690 --- /dev/null +++ b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast @@ -0,0 +1,54 @@ +;; Tests for i32x4.relaxed_trunc_f32x4_s, i32x4.relaxed_trunc_f32x4_u, i32x4.relaxed_trunc_f64x2_s_zero, and i32x4.relaxed_trunc_f64x2_u_zero. + +(module + (func (export "i32x4.relaxed_trunc_f32x4_s") (param v128) (result v128) (i32x4.relaxed_trunc_f32x4_s (local.get 0))) + (func (export "i32x4.relaxed_trunc_f32x4_u") (param v128) (result v128) (i32x4.relaxed_trunc_f32x4_u (local.get 0))) + (func (export "i32x4.relaxed_trunc_f64x2_s_zero") (param v128) (result v128) (i32x4.relaxed_trunc_f64x2_s_zero (local.get 0))) + (func (export "i32x4.relaxed_trunc_f64x2_u_zero") (param v128) (result v128) (i32x4.relaxed_trunc_f64x2_u_zero (local.get 0))) +) + +(assert_return (invoke "i32x4.relaxed_trunc_f32x4_s" + ;; INT32_MIN INT32_MAX + (v128.const f32x4 -2147483648.0 -2147483904.0 2147483647.0 2147483904.0)) + ;; out of range -> 0 or INT32_MIN + (either (v128.const i32x4 0x80000000 0 0x4f000000 0) + (v128.const i32x4 0xcf000000 0x8000000 0x4f000000 0x8000000))) + +(assert_return (invoke "i32x4.relaxed_trunc_f32x4_s" + (v128.const f32x4 nan -nan nan:0x444444 -nan:0x444444)) + ;; nans -> 0 or INT32_MIN + (either (v128.const i32x4 0 0 0 0) + (v128.const i32x4 0x8000000 0x8000000 0x8000000 0x8000000))) + +(assert_return (invoke "i32x4.relaxed_trunc_f32x4_u" + ;; UINT32_MIN UINT32_MIN-1 0 or UINT32_MAX + (either (v128.const i32x4 0 0 4294967040 0) + (v128.const i32x4 0 0xffffffff 4294967040 0xffffffff))) + +(assert_return (invoke "i32x4.relaxed_trunc_f32x4_u" + (v128.const f32x4 nan -nan nan:0x444444 -nan:0x444444)) + ;; nans -> 0 or UINT32_MAX + (either (v128.const i32x4 0 0 0 0) + (v128.const i32x4 0xffffffff 0xffffffff 0xffffffff 0xffffffff))) + +(assert_return (invoke "i32x4.relaxed_trunc_f64x2_s_zero" + (v128.const f64x2 -2147483904.0 2147483904.0)) + (either (v128.const i32x4 0 0 0 0) + (v128.const i32x4 0 0 0x8000000 0x8000000))) + +(assert_return (invoke "i32x4.relaxed_trunc_f64x2_s_zero" + (v128.const f64x2 nan -nan)) + (either (v128.const i32x4 0 0 0 0) + (v128.const i32x4 0 0 0x8000000 0x8000000))) + +(assert_return (invoke "i32x4.relaxed_trunc_f64x2_u_zero" + (v128.const f64x2 -1.0 4294967296.0)) + (either (v128.const i32x4 0 0 0 0) + (v128.const i32x4 0 0 0xffffffff 0xffffffff))) + +(assert_return (invoke "i32x4.relaxed_trunc_f64x2_u_zero" + (v128.const f64x2 nan -nan)) + (either (v128.const i32x4 0 0 0 0) + (v128.const i32x4 0 0 0xffffffff 0xffffffff))) diff --git a/test/core/relaxed-simd/i8x16_relaxed_swizzle.wast b/test/core/relaxed-simd/i8x16_relaxed_swizzle.wast new file mode 100644 index 000000000..22c11efb2 --- /dev/null +++ b/test/core/relaxed-simd/i8x16_relaxed_swizzle.wast @@ -0,0 +1,25 @@ +;; Tests for relaxed i8x16 swizzle. + +(module + (func (export "i8x16.relaxed_swizzle") (param v128 v128) (result v128) (i8x16.relaxed_swizzle (local.get 0) (local.get 1))) +) + +(assert_return (invoke "i8x16.relaxed_swizzle" + (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) + (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) + (either (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) + (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15))) + +;; out of range, returns 0 or modulo 15 if < 128 +(assert_return (invoke "i8x16.relaxed_swizzle" + (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) + (v128.const i8x16 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31)) + (either (v128.const i8x16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15))) + +;; out of range, returns 0 if >= 128 +(assert_return (invoke "i8x16.relaxed_swizzle" + (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) + (v128.const i8x16 128 129 130 131 132 133 134 135 248 249 250 251 252 253 254 255)) + (either (v128.const i8x16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15))) diff --git a/test/core/relaxed-simd/relaxed_fma_fms.wast b/test/core/relaxed-simd/relaxed_fma_fms.wast new file mode 100644 index 000000000..cba4ba601 --- /dev/null +++ b/test/core/relaxed-simd/relaxed_fma_fms.wast @@ -0,0 +1,66 @@ +;; Tests for f32x4.relaxed_fma, f32x4.relaxed_fms, f64x2.relaxed_fma, and f64x2.relaxed_fms. + +(module + (func (export "f32x4.relaxed_fma") (param v128 v128 v128) (result v128) (f32x4.relaxed_fma (local.get 0) (local.get 1) (local.get 2))) + (func (export "f32x4.relaxed_fms") (param v128 v128 v128) (result v128) (f32x4.relaxed_fms (local.get 0) (local.get 1) (local.get 2))) + (func (export "f64x2.relaxed_fms") (param v128 v128 v128) (result v128) (f64x2.relaxed_fms (local.get 0) (local.get 1) (local.get 2))) + (func (export "f64x2.relaxed_fma") (param v128 v128 v128) (result v128) (f64x2.relaxed_fma (local.get 0) (local.get 1) (local.get 2))) +) + + +;; FLT_MAX == 0x1.fffffep+127 +;; FLT_MAX * 2 - FLT_MAX == +;; FLT_MAX (if fma) +;; 0 (if no fma) +;; from https://www.vinc17.net/software/fma-tests.c +(assert_return (invoke "f32x4.relaxed_fma" + (v128.const f32x4 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 ) + (v128.const f32x4 2.0 2.0 2.0 2.0) + (v128.const f32x4 -0x1.fffffep+127 -0x1.fffffep+127 -0x1.fffffep+127 -0x1.fffffep+127)) + (either (v128.const f32x4 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127) + (v128.const f32x4 inf inf inf inf))) + +;; Special values for float: +;; x = 0x1.000004p+0 (1 + 2^-22) +;; y = 0x1.0002p+0 (1 + 2^-15) +;; z = -(1.0 + 0x0.0002p+0 + 0x0.000004p+0) +;; = -0x1.000204p+0 +;; x.y = 1.0 + 0x0.0002p+0 + 0x0.000004p+0 + 0x1p-37 (round bit) +;; x.y+z = 0 (2 roundings) +;; fma(x, y, z) = (0x1p-37) 2^-37 +;; from https://accurate-algorithms.readthedocs.io/en/latest/ch09appendix.html#test-system-information +(assert_return (invoke "f32x4.relaxed_fms" + (v128.const f32x4 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0) + (v128.const f32x4 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0) + (v128.const f32x4 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0)) + (either (v128.const f32x4 0x1p-37 0x1p-37 0x1p-37 0x1p-37) + (v128.const f32x4 0 0 0 0))) + +;; DBL_MAX = 0x1.fffffffffffffp+1023 +;; DLB_MAX * 2 - DLB_MAX == +;; DLB_MAX (if fma) +;; 0 (if no fma) +;; form https://www.vinc17.net/software/fma-tests.c +;; from https://www.vinc17.net/software/fma-tests.c +(assert_return (invoke "f64x2.relaxed_fma" + (v128.const f64x2 0x1.fffffffffffffp+1023 0x1.fffffffffffffp+1023) + (v128.const f64x2 2.0 2.0) + (v128.const f64x2 -0x1.fffffffffffffp+1023 -0x1.fffffffffffffp+1023)) + (either (v128.const f64x2 0x1.fffffffffffffp+1023 0x1.fffffffffffffp+1023) + (v128.const f64x2 inf inf))) + +;; Special values for double: +;; x = 0x1.00000004p+0 (1 + 2^-30) +;; y = 0x1.000002p+0 (1 + 2^-23) +;; z = -(1.0 + 0x0.000002p+0 + 0x0.00000004p+0) +;; = -0x1.00000204p+0 +;; x.y = 1.0 + 0x0.000002p+0 + 0x0.00000004p+0 + 0x1p-53 (round bit) +;; x.y+z = 0 (2 roundings) +;; fma(x, y, z) = 0x1p-53 +;; from https://accurate-algorithms.readthedocs.io/en/latest/ch09appendix.html#test-system-information +(assert_return (invoke "f64x2.relaxed_fms" + (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) + (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) + (v128.const f64x2 -0x1.00000204p+0 -0x1.00000204p+0)) + (either (v128.const f64x2 0x1p-53 0x1p-53) + (v128.const f64x2 0 0))) diff --git a/test/core/relaxed-simd/relaxed_laneselect.wast b/test/core/relaxed-simd/relaxed_laneselect.wast new file mode 100644 index 000000000..e1a246fe3 --- /dev/null +++ b/test/core/relaxed-simd/relaxed_laneselect.wast @@ -0,0 +1,43 @@ +;; Tests for i8x16.relaxed_laneselect, i16x8.relaxed_laneselect, i32x4.relaxed_laneselect, and i64x2.relaxed_laneselect. + +(module + (func (export "i8x16.relaxed_laneselect") (param v128 v128 v128) (result v128) (i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))) + (func (export "i16x8.relaxed_laneselect") (param v128 v128 v128) (result v128) (i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))) + (func (export "i32x4.relaxed_laneselect") (param v128 v128 v128) (result v128) (i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))) + (func (export "i64x2.relaxed_laneselect") (param v128 v128 v128) (result v128) (i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))) +) + +(assert_return (invoke "i8x16.relaxed_laneselect" + (v128.const i8x16 0 1 0x12 0x12 4 5 6 7 8 9 10 11 12 13 14 15) + (v128.const i8x16 16 17 0x34 0x34 20 21 22 23 24 25 26 27 28 29 30 31) + (v128.const i8x16 0xff 0 0xf0 0x0f 0 0 0 0 0 0 0 0 0 0 0 0)) + (either (v128.const i8x16 0 17 0x14 0x32 20 21 22 23 24 25 26 27 28 29 30 31) + (v128.const i8x16 0 17 0x12 0x34 20 21 22 23 24 25 26 27 28 29 30 31))) + +(assert_return (invoke "i16x8.relaxed_laneselect" + (v128.const i16x8 0 1 0x1234 0x1234 4 5 6 7) + (v128.const i16x8 8 9 0x5678 0x5678 12 13 14 15) + (v128.const i16x8 0xffff 0 0xff00 0x00ff 0 0 0 0)) + (either (v128.const i16x8 0 9 0x1278 0x5634 12 13 14 15) + (v128.const i16x8 0 9 0x1234 0x5678 12 13 14 15))) + +(assert_return (invoke "i32x4.relaxed_laneselect" + (v128.const i32x4 0 1 0x12341234 0x12341234) + (v128.const i32x4 4 5 0x56785678 0x56785678) + (v128.const i32x4 0xffffffff 0 0xffff0000 0x0000ffff)) + (either (v128.const i32x4 0 5 0x12345678 0x56781234) + (v128.const i32x4 0 5 0x12341234 0x56785678))) + +(assert_return (invoke "i64x2.relaxed_laneselect" + (v128.const i64x2 0 1) + (v128.const i64x2 2 3) + (v128.const i64x2 0xffffffffffffffff 0)) + (either (v128.const i64x2 0 3) + (v128.const i64x2 0 3))) + +(assert_return (invoke "i64x2.relaxed_laneselect" + (v128.const i64x2 0x1234123412341234 0x1234123412341234) + (v128.const i64x2 0x5678567856785678 0x5678567856785678) + (v128.const i64x2 0xffffffff00000000 0x00000000ffffffff)) + (either (v128.const i64x2 0x1234123456785678 0x5678567812341234) + (v128.const i64x2 0x1234123412341234 0x5678567856785678))) diff --git a/test/core/relaxed-simd/relaxed_min_max.wast b/test/core/relaxed-simd/relaxed_min_max.wast new file mode 100644 index 000000000..5e49ac673 --- /dev/null +++ b/test/core/relaxed-simd/relaxed_min_max.wast @@ -0,0 +1,104 @@ +;; Tests for f32x4.min, f32x4.max, f64x2.min, and f64x2.max. + +(module + (func (export "f32x4.relaxed_min") (param v128 v128) (result v128) (f32x4.relaxed_min (local.get 0) (local.get 1))) + (func (export "f32x4.relaxed_max") (param v128 v128) (result v128) (f32x4.relaxed_max (local.get 0) (local.get 1))) + (func (export "f64x2.relaxed_max") (param v128 v128) (result v128) (f64x2.relaxed_max (local.get 0) (local.get 1))) + (func (export "f64x2.relaxed_min") (param v128 v128) (result v128) (f64x2.relaxed_min (local.get 0) (local.get 1))) +) + +(assert_return (invoke "f32x4.relaxed_min" + (v128.const f32x4 -nan nan 0 0) + (v128.const f32x4 0 0 -nan nan)) + (either (v128.const f32x4 nan:canonical nan:canonical nan:canonical nan:canonical) + (v128.const f32x4 nan:canonical nan:canonical 0 0) + (v128.const f32x4 0 0 nan:canonical nan:canonical) + (v128.const f32x4 0 0 0 0))) + +(assert_return (invoke "f32x4.relaxed_min" + (v128.const f32x4 +0.0 -0.0 +0.0 -0.0) + (v128.const f32x4 -0.0 +0.0 +0.0 -0.0)) + (either (v128.const f32x4 -0.0 -0.0 +0.0 -0.0) + (v128.const f32x4 +0.0 -0.0 +0.0 -0.0) + (v128.const f32x4 -0.0 +0.0 +0.0 -0.0) + (v128.const f32x4 -0.0 -0.0 +0.0 -0.0))) + +(assert_return (invoke "f32x4.relaxed_max" + (v128.const f32x4 -nan nan 0 0) + (v128.const f32x4 0 0 -nan nan)) + (either (v128.const f32x4 nan:canonical nan:canonical nan:canonical nan:canonical) + (v128.const f32x4 nan:canonical nan:canonical 0 0) + (v128.const f32x4 0 0 nan:canonical nan:canonical) + (v128.const f32x4 0 0 0 0))) + +(assert_return (invoke "f32x4.relaxed_max" + (v128.const f32x4 +0.0 -0.0 +0.0 -0.0) + (v128.const f32x4 -0.0 +0.0 +0.0 -0.0)) + (either (v128.const f32x4 +0.0 +0.0 +0.0 -0.0) + (v128.const f32x4 +0.0 -0.0 +0.0 -0.0) + (v128.const f32x4 -0.0 +0.0 +0.0 -0.0) + (v128.const f32x4 -0.0 -0.0 +0.0 -0.0))) + +(assert_return (invoke "f64x2.relaxed_min" + (v128.const f64x2 -nan nan) + (v128.const f64x2 0 0)) + (either (v128.const f64x2 nan:canonical nan:canonical) + (v128.const f64x2 nan:canonical nan:canonical) + (v128.const f64x2 0 0) + (v128.const f64x2 0 0))) + +(assert_return (invoke "f64x2.relaxed_min" + (v128.const f64x2 0 0) + (v128.const f64x2 -nan nan)) + (either (v128.const f64x2 nan:canonical nan:canonical) + (v128.const f64x2 0 0) + (v128.const f64x2 nan:canonical nan:canonical) + (v128.const f64x2 0 0))) + +(assert_return (invoke "f64x2.relaxed_min" + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 -0.0 +0.0)) + (either (v128.const f64x2 -0.0 -0.0) + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 -0.0 +0.0) + (v128.const f64x2 -0.0 -0.0))) + +(assert_return (invoke "f64x2.relaxed_min" + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 +0.0 -0.0)) + (either (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 +0.0 -0.0))) + +(assert_return (invoke "f64x2.relaxed_max" + (v128.const f64x2 -nan nan) + (v128.const f64x2 0 0)) + (either (v128.const f64x2 nan:canonical nan:canonical) + (v128.const f64x2 nan:canonical nan:canonical) + (v128.const f64x2 0 0) + (v128.const f64x2 0 0))) + +(assert_return (invoke "f64x2.relaxed_max" + (v128.const f64x2 0 0) + (v128.const f64x2 -nan nan)) + (either (v128.const f64x2 nan:canonical nan:canonical) + (v128.const f64x2 0 0) + (v128.const f64x2 nan:canonical nan:canonical) + (v128.const f64x2 0 0))) + +(assert_return (invoke "f64x2.relaxed_max" + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 -0.0 +0.0)) + (either (v128.const f64x2 +0.0 +0.0) + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 -0.0 +0.0) + (v128.const f64x2 -0.0 -0.0))) + +(assert_return (invoke "f64x2.relaxed_max" + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 +0.0 -0.0)) + (either (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 +0.0 -0.0))) From 3f9570148fbd736b9f0a6678e6eb9039e4a997b6 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 14 Mar 2022 20:34:38 +0000 Subject: [PATCH 026/117] Fixes to test --- .../relaxed-simd/i32x4_relaxed_trunc.wast | 22 ++++++++++++------- test/core/relaxed-simd/relaxed_fma_fms.wast | 18 ++++++++++++--- 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/test/core/relaxed-simd/i32x4_relaxed_trunc.wast b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast index 55f923690..c19f120a9 100644 --- a/test/core/relaxed-simd/i32x4_relaxed_trunc.wast +++ b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast @@ -10,9 +10,10 @@ (assert_return (invoke "i32x4.relaxed_trunc_f32x4_s" ;; INT32_MIN INT32_MAX (v128.const f32x4 -2147483648.0 -2147483904.0 2147483647.0 2147483904.0)) - ;; out of range -> 0 or INT32_MIN - (either (v128.const i32x4 0x80000000 0 0x4f000000 0) - (v128.const i32x4 0xcf000000 0x8000000 0x4f000000 0x8000000))) + ;; out of range -> 0 or saturate or INT32_MIN + (either (v128.const i32x4 -2147483648 0 2147483647 0) + (v128.const i32x4 -2147483648 -2147483648 2147483647 2147483647) + (v128.const i32x4 -2147483648 -2147483648 2147483647 -2147483648))) (assert_return (invoke "i32x4.relaxed_trunc_f32x4_s" (v128.const f32x4 nan -nan nan:0x444444 -nan:0x444444)) @@ -22,9 +23,10 @@ (assert_return (invoke "i32x4.relaxed_trunc_f32x4_u" ;; UINT32_MIN UINT32_MIN-1 0 or UINT32_MAX + (v128.const f32x4 0 -1.0 4294967040.0 4294967296.0)) + ;; out of range -> 0 or saturate or UINT32_MAX (either (v128.const i32x4 0 0 4294967040 0) + (v128.const i32x4 0 0 4294967040 0xffffffff) (v128.const i32x4 0 0xffffffff 4294967040 0xffffffff))) (assert_return (invoke "i32x4.relaxed_trunc_f32x4_u" @@ -35,18 +37,22 @@ (assert_return (invoke "i32x4.relaxed_trunc_f64x2_s_zero" (v128.const f64x2 -2147483904.0 2147483904.0)) + ;; out of range -> 0 or saturate or INT32_MIN (either (v128.const i32x4 0 0 0 0) - (v128.const i32x4 0 0 0x8000000 0x8000000))) + (v128.const i32x4 -2147483648 2147483647 0 0) + (v128.const i32x4 -2147483648 -2147483648 0 0))) (assert_return (invoke "i32x4.relaxed_trunc_f64x2_s_zero" (v128.const f64x2 nan -nan)) (either (v128.const i32x4 0 0 0 0) - (v128.const i32x4 0 0 0x8000000 0x8000000))) + (v128.const i32x4 0x8000000 0x8000000 0 0))) (assert_return (invoke "i32x4.relaxed_trunc_f64x2_u_zero" (v128.const f64x2 -1.0 4294967296.0)) + ;; out of range -> 0 or saturate or UINT32_MAX (either (v128.const i32x4 0 0 0 0) - (v128.const i32x4 0 0 0xffffffff 0xffffffff))) + (v128.const i32x4 0 0xffffffff 0 0) + (v128.const i32x4 0xffffffff 0xffffffff 0 0))) (assert_return (invoke "i32x4.relaxed_trunc_f64x2_u_zero" (v128.const f64x2 nan -nan)) diff --git a/test/core/relaxed-simd/relaxed_fma_fms.wast b/test/core/relaxed-simd/relaxed_fma_fms.wast index cba4ba601..d895d88d6 100644 --- a/test/core/relaxed-simd/relaxed_fma_fms.wast +++ b/test/core/relaxed-simd/relaxed_fma_fms.wast @@ -29,12 +29,18 @@ ;; x.y+z = 0 (2 roundings) ;; fma(x, y, z) = (0x1p-37) 2^-37 ;; from https://accurate-algorithms.readthedocs.io/en/latest/ch09appendix.html#test-system-information -(assert_return (invoke "f32x4.relaxed_fms" +(assert_return (invoke "f32x4.relaxed_fma" (v128.const f32x4 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0) (v128.const f32x4 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0) (v128.const f32x4 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0)) (either (v128.const f32x4 0x1p-37 0x1p-37 0x1p-37 0x1p-37) (v128.const f32x4 0 0 0 0))) +(assert_return (invoke "f32x4.relaxed_fms" + (v128.const f32x4 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0) + (v128.const f32x4 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0) + (v128.const f32x4 0x1.000204p+0 0x1.000204p+0 0x1.000204p+0 0x1.000204p+0)) + (either (v128.const f32x4 0x1p-37 0x1p-37 0x1p-37 0x1p-37) + (v128.const f32x4 0 0 0 0))) ;; DBL_MAX = 0x1.fffffffffffffp+1023 ;; DLB_MAX * 2 - DLB_MAX == @@ -58,9 +64,15 @@ ;; x.y+z = 0 (2 roundings) ;; fma(x, y, z) = 0x1p-53 ;; from https://accurate-algorithms.readthedocs.io/en/latest/ch09appendix.html#test-system-information -(assert_return (invoke "f64x2.relaxed_fms" - (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) +(assert_return (invoke "f64x2.relaxed_fma" (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) + (v128.const f64x2 0x1.000002p+0 0x1.000002p+0) (v128.const f64x2 -0x1.00000204p+0 -0x1.00000204p+0)) (either (v128.const f64x2 0x1p-53 0x1p-53) (v128.const f64x2 0 0))) +(assert_return (invoke "f64x2.relaxed_fms" + (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) + (v128.const f64x2 0x1.000002p+0 0x1.000002p+0) + (v128.const f64x2 0x1.00000204p+0 0x1.00000204p+0)) + (either (v128.const f64x2 0x1p-53 0x1p-53) + (v128.const f64x2 0 0))) From bfb6b0ad9b81eecfc65b21a4a2854ec0934deeb4 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 14 Mar 2022 22:19:26 +0000 Subject: [PATCH 027/117] Fix relaxed trunc expected results --- .../relaxed-simd/i32x4_relaxed_trunc.wast | 20 ++++++++----------- 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/test/core/relaxed-simd/i32x4_relaxed_trunc.wast b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast index c19f120a9..c31195d04 100644 --- a/test/core/relaxed-simd/i32x4_relaxed_trunc.wast +++ b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast @@ -10,9 +10,8 @@ (assert_return (invoke "i32x4.relaxed_trunc_f32x4_s" ;; INT32_MIN INT32_MAX (v128.const f32x4 -2147483648.0 -2147483904.0 2147483647.0 2147483904.0)) - ;; out of range -> 0 or saturate or INT32_MIN - (either (v128.const i32x4 -2147483648 0 2147483647 0) - (v128.const i32x4 -2147483648 -2147483648 2147483647 2147483647) + ;; out of range -> saturate or INT32_MIN + (either (v128.const i32x4 -2147483648 -2147483648 2147483647 2147483647) (v128.const i32x4 -2147483648 -2147483648 2147483647 -2147483648))) (assert_return (invoke "i32x4.relaxed_trunc_f32x4_s" @@ -24,9 +23,8 @@ (assert_return (invoke "i32x4.relaxed_trunc_f32x4_u" ;; UINT32_MIN UINT32_MIN-1 0 or saturate or UINT32_MAX - (either (v128.const i32x4 0 0 4294967040 0) - (v128.const i32x4 0 0 4294967040 0xffffffff) + ;; out of range -> saturate or UINT32_MAX + (either (v128.const i32x4 0 0 4294967040 0xffffffff) (v128.const i32x4 0 0xffffffff 4294967040 0xffffffff))) (assert_return (invoke "i32x4.relaxed_trunc_f32x4_u" @@ -37,9 +35,8 @@ (assert_return (invoke "i32x4.relaxed_trunc_f64x2_s_zero" (v128.const f64x2 -2147483904.0 2147483904.0)) - ;; out of range -> 0 or saturate or INT32_MIN - (either (v128.const i32x4 0 0 0 0) - (v128.const i32x4 -2147483648 2147483647 0 0) + ;; out of range -> saturate or INT32_MIN + (either (v128.const i32x4 -2147483648 2147483647 0 0) (v128.const i32x4 -2147483648 -2147483648 0 0))) (assert_return (invoke "i32x4.relaxed_trunc_f64x2_s_zero" @@ -49,9 +46,8 @@ (assert_return (invoke "i32x4.relaxed_trunc_f64x2_u_zero" (v128.const f64x2 -1.0 4294967296.0)) - ;; out of range -> 0 or saturate or UINT32_MAX - (either (v128.const i32x4 0 0 0 0) - (v128.const i32x4 0 0xffffffff 0 0) + ;; out of range -> saturate or UINT32_MAX + (either (v128.const i32x4 0 0xffffffff 0 0) (v128.const i32x4 0xffffffff 0xffffffff 0 0))) (assert_return (invoke "i32x4.relaxed_trunc_f64x2_u_zero" From 9b8c69ba56ac15a6ee1c1c2cee0b4079163075fc Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 10 Mar 2022 00:23:26 +0000 Subject: [PATCH 028/117] Restrict allowed return values --- proposals/relaxed-simd/Overview.md | 60 ++++++++++++++++++++---------- 1 file changed, 41 insertions(+), 19 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 27c6702c0..2d563ff1a 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -70,11 +70,16 @@ The specification is updated with the idea of "Relaxed operations": ## Instructions +`IMPLEMENTATION_DEFINED_ONE_OF(...)` returns any one of the results in the argument list, depending on the implementation. + ### Relaxed swizzle - `relaxed i8x16.swizzle(a : v128, s : v128) -> v128` -`relaxed i8x16.swizzle(a, s)` selects lanes from `a` using indices in `s`, indices in the range `[0,15]` will select the `i`-th element of `a`, the result for any out of range indices is implementation-defined (i.e. if the index is `[16-255]`. +`relaxed i8x16.swizzle(a, s)` selects lanes from `a` using indices in `s`, +indices in the range `[0,15]` will select the `i`-th element of `a`, the result +for any out of range indices is implementation-defined (i.e. if the index is +`[16-255]`. ```python def relaxed_i8x16_swizzle(a, s): @@ -82,8 +87,10 @@ def relaxed_i8x16_swizzle(a, s): for i in range(16): if s[i] < 16: result[i] = a[s[i]] + else if s[i] < 128: + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, a[s[i]%16]) else: - result[i] = UNDEFINED + result[i] = 0 return result ``` @@ -97,30 +104,45 @@ def relaxed_i8x16_swizzle(a, s): These instructions have the same behavior as the non-relaxed instructions for lanes that are in the range of an `i32` (signed or unsigned depending on the instruction). For lanes that contain values which are out of bounds or NaN, the -result is implementation-defined. +result is implementation-defined, either 0, or `INT32_MAX` for signed, and +`UINT32_MAX` for unsigned. ```python -def relaxed_i32x4_trunc_f32x4(a : f32x4, signed : bool) -> i32x4: - result = [] - min = signed ? INT32_MIN : UINT32_MIN - max = signed ? INT32_MAX : UINT32_MAX +def relaxed_i32x4_trunc_f32x4_s(a : f32x4) -> i32x4: + result = [0, 0, 0, 0] for i in range(4): r = truncate(a[i]) - if min <= r <= max: + if isnan(a[i]) or INT32_MIN <= r <= INT32_MAX: result[i] = r else: - result[i] = UNDEFINED + result[i] = signed IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MAX) -def relaxed_i32x4_trunc_f64x2_zero(a : f64x2, signed : bool) -> i32x4: +def relaxed_i32x4_trunc_f32x4_u(a : f32x4) -> i32x4: result = [0, 0, 0, 0] - min = signed ? INT32_MIN : UINT32_MIN - max = signed ? INT32_MAX : UINT32_MAX - for i in range(2): + for i in range(4): r = truncate(a[i]) - if min <= r <= max: + if isnan(a[i]) or UINT32_MIN <= r <= UINT32_MAX: + result[i] = r + else: + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, UINT32_MAX) + +def relaxed_i32x4_trunc_f64x2_zero_s(a : f64x2) -> i32x4: + result = [0, 0, 0, 0] + for i in range(2): + r = isnan(a[i]) or truncate(a[i]) + if INT32_MIN <= r <= INT32_MAX: result[i] = r else: - result[i] = UNDEFINED + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MAX) + +def relaxed_i32x4_trunc_f64x2_zero_u(a : f64x2) -> i32x4: + result = [0, 0, 0, 0] + for i in range(2): + r = isnan(a[i]) or truncate(a[i]) + if UINT32_MIN <= r <= UINT32_MAX: + result[i] = r + else: + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, UINT32_MAX) ``` ### Relaxed fused multiply-add and fused multiply-subtract @@ -153,15 +175,17 @@ Select lanes from `a` or `b` based on masks in `m`. If each lane-sized mask in ` ```python def laneselect(a : v128, b : v128, m: v128, lanes : int): - result = [] + result = [0] * lanes for i in range(lanes): mask = m[i] if mask == ~0: result[i] = a[i] elif mask == 0: result[i] = b[i] + else topbit(mask) == 1: + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(bitselect(a[i], b[i], mask), a[i]) else: - result[i] = UNDEFINED + result[i] = b[i] return result ``` @@ -187,8 +211,6 @@ def min_or_max(a : v128, b : v128, lanes : int, is_min : bool): return result ``` -Where `IMPLEMENTATION_DEFINED_ONE_OF(x, y)` returns either `x` or `y`, depending on the implementation. - ### Relaxed Rounding Q-format Multiplication - `i16x8.q15mulr_s(a: v128, b: v128) -> v128` From fbfb92f1091f00896a62a782577e0c28fa7c79bd Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 10 Mar 2022 00:29:21 +0000 Subject: [PATCH 029/117] Fix typos --- proposals/relaxed-simd/Overview.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 2d563ff1a..28d8b55c0 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -82,7 +82,7 @@ for any out of range indices is implementation-defined (i.e. if the index is `[16-255]`. ```python -def relaxed_i8x16_swizzle(a, s): +def relaxed_i8x16_swizzle(a : i8x16, s : i8x16): result = [] for i in range(16): if s[i] < 16: @@ -115,7 +115,7 @@ def relaxed_i32x4_trunc_f32x4_s(a : f32x4) -> i32x4: if isnan(a[i]) or INT32_MIN <= r <= INT32_MAX: result[i] = r else: - result[i] = signed IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MAX) + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MAX) def relaxed_i32x4_trunc_f32x4_u(a : f32x4) -> i32x4: result = [0, 0, 0, 0] @@ -129,8 +129,8 @@ def relaxed_i32x4_trunc_f32x4_u(a : f32x4) -> i32x4: def relaxed_i32x4_trunc_f64x2_zero_s(a : f64x2) -> i32x4: result = [0, 0, 0, 0] for i in range(2): - r = isnan(a[i]) or truncate(a[i]) - if INT32_MIN <= r <= INT32_MAX: + r = truncate(a[i]) + if isnan(a[i]) or INT32_MIN <= r <= INT32_MAX: result[i] = r else: result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MAX) @@ -138,8 +138,8 @@ def relaxed_i32x4_trunc_f64x2_zero_s(a : f64x2) -> i32x4: def relaxed_i32x4_trunc_f64x2_zero_u(a : f64x2) -> i32x4: result = [0, 0, 0, 0] for i in range(2): - r = isnan(a[i]) or truncate(a[i]) - if UINT32_MIN <= r <= UINT32_MAX: + r = truncate(a[i]) + if isnan(a[i]) or UINT32_MIN <= r <= UINT32_MAX: result[i] = r else: result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, UINT32_MAX) From c1a56b597745502e605cc57f9f00dc49d557b4df Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 14 Mar 2022 21:22:13 +0000 Subject: [PATCH 030/117] Fix trunc --- proposals/relaxed-simd/Overview.md | 40 +++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 28d8b55c0..d020e2f4a 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -111,38 +111,54 @@ result is implementation-defined, either 0, or `INT32_MAX` for signed, and def relaxed_i32x4_trunc_f32x4_s(a : f32x4) -> i32x4: result = [0, 0, 0, 0] for i in range(4): + if isnan(a[i]): + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MAX) r = truncate(a[i]) - if isnan(a[i]) or INT32_MIN <= r <= INT32_MAX: - result[i] = r + if r < INT32_MIN: + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(INT32_MIN, INT32_MAX) + elif r > INT32_MAX + result[i] = INT32_MAX else: - result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MAX) + result[i] = r def relaxed_i32x4_trunc_f32x4_u(a : f32x4) -> i32x4: result = [0, 0, 0, 0] for i in range(4): + if isnan(a[i]): + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, UINT32_MAX) r = truncate(a[i]) - if isnan(a[i]) or UINT32_MIN <= r <= UINT32_MAX: - result[i] = r + if r < UINT32_MIN: + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(UINT32_MIN, UINT32_MAX) + elif r > UINT32_MAX: + result[i] = UINT32_MAX else: - result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, UINT32_MAX) + result[i] = r def relaxed_i32x4_trunc_f64x2_zero_s(a : f64x2) -> i32x4: result = [0, 0, 0, 0] for i in range(2): + if isnan(a[i]): + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MAX) r = truncate(a[i]) - if isnan(a[i]) or INT32_MIN <= r <= INT32_MAX: - result[i] = r + if r < INT32_MIN: + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(INT32_MIN, INT32_MAX) + elif r > INT32_MAX + result[i] = INT32_MAX else: - result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MAX) + result[i] = r def relaxed_i32x4_trunc_f64x2_zero_u(a : f64x2) -> i32x4: result = [0, 0, 0, 0] for i in range(2): + if isnan(a[i]): + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, UINT32_MAX) r = truncate(a[i]) - if isnan(a[i]) or UINT32_MIN <= r <= UINT32_MAX: - result[i] = r + if r < UINT32_MIN: + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(UINT32_MIN, UINT32_MAX) + elif r > UINT32_MAX: + result[i] = UINT32_MAX else: - result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, UINT32_MAX) + result[i] = r ``` ### Relaxed fused multiply-add and fused multiply-subtract From 8413b4237e8738436829e5e7d2be67aad28ec1c5 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 14 Mar 2022 21:25:43 +0000 Subject: [PATCH 031/117] Update trunc description --- proposals/relaxed-simd/Overview.md | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index d020e2f4a..d76712980 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -103,9 +103,11 @@ def relaxed_i8x16_swizzle(a : i8x16, s : i8x16): These instructions have the same behavior as the non-relaxed instructions for lanes that are in the range of an `i32` (signed or unsigned depending on the -instruction). For lanes that contain values which are out of bounds or NaN, the -result is implementation-defined, either 0, or `INT32_MAX` for signed, and -`UINT32_MAX` for unsigned. +instruction). The result of lanes which contain NaN is implementation defined, +either 0 or `INT32_MAX` for signed and `UINT32_MAX` for unsigned. The result of +lanes which are out of bounds of `INT32` or `UINT32` is implementation defined, +it can be either the saturated result or `INT32_MAX` for signed and `UINT32_MAX` +for unsigned. ```python def relaxed_i32x4_trunc_f32x4_s(a : f32x4) -> i32x4: From 2e66ec6ca22fc442c5dadf605f56fd125a596445 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Fri, 18 Mar 2022 15:25:48 -0700 Subject: [PATCH 032/117] Update ImplementationStatus.md --- proposals/relaxed-simd/ImplementationStatus.md | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/proposals/relaxed-simd/ImplementationStatus.md b/proposals/relaxed-simd/ImplementationStatus.md index d17c7e090..fa3457a65 100644 --- a/proposals/relaxed-simd/ImplementationStatus.md +++ b/proposals/relaxed-simd/ImplementationStatus.md @@ -19,6 +19,12 @@ | `f32x4.max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | | `f64x2.min` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | | `f64x2.max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i16x8.relaxed_q15mulr_s` | | | | +| `i16x8.dot_i8x16_i7x16_s` | | | | +| `i16x8.dot_i8x16_i7x16_u` | | | | +| `i32x4.dot_i8x16_i7x16_add_s` | | | | +| `i32x4.dot_i8x16_i7x16_add_u` | | | | + [1] Tip of tree LLVM as of 2021-10-28 @@ -47,3 +53,8 @@ | `f32x4.max` | `__builtin_wasm_relaxed_max_f32x4` | | `f64x2.min` | `__builtin_wasm_relaxed_min_f64x2` | | `f64x2.max` | `__builtin_wasm_relaxed_max_f64x2` | +| `i16x8.relaxed_q15mulr_s` | | +| `i16x8.dot_i8x16_i7x16_s` | | +| `i16x8.dot_i8x16_i7x16_u` | | +| `i32x4.dot_i8x16_i7x16_add_s` | | +| `i32x4.dot_i8x16_i7x16_add_u` | | From 1f29e464eeebd3b7b53b918c73048dca316f90f1 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 22 Mar 2022 17:10:51 +0000 Subject: [PATCH 033/117] Add dot product to overview --- proposals/relaxed-simd/Overview.md | 85 ++++++++++++++++++++++-------- 1 file changed, 62 insertions(+), 23 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index d76712980..7b92d3c84 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -248,6 +248,42 @@ def q15mulr(a, b): return result ``` +### Relaxed integer dot product + +- `i16x8.dot_i8x16_i7x16_s(a: v128, b: v128) -> v128` +- `i16x8.dot_i8x16_i7x16_u(a: v128, b: v128) -> v128` +- `i32x4.dot_i8x16_i7x16_add_s(a: v128, b:v128, c:v128) -> v128` +- `i32x4.dot_i8x16_i7x16_add_u(a: v128, b:v128, c:v128) -> v128` + +Returns the multiplication of 8-bit elements (signed or unsigned) by 7-bit +elements (unsigned) with accumulation of adjacent products. The `i32x4` versions +allows for accumulation into another vector. + +When the second operand of the product has the high bit set in a lane, that +lane's result is implementation defined. + +```python +def dot_product(signed, elements, a, b, c): + intermediate = [] + result = [] + for i in range(16): + if (b[i] & 0x80): + lhs = as_signed(a[i]) if signed else a[i] + rhs = IMPLEMENTATION_DEFINED_ONE_OF(as_signed(b[i]), b[i]) + intermediate[i] = lhs + rhs + else: + intermediate[i] = (as_signed(a[i]) if signed else a[i]) * b[i] + for i in range(0, 16, elements): + result[i/elements] == sum(intermediate[i:i+elements]) + result[i/elements] += c[i/elements] if c else 0 + +i16x8_dot_i8x16_i7x16_s(a, b) = dot_product(signed=True, elements=2, a, b) +i16x8_dot_i8x16_i7x16_u(a, b) = dot_product(signed=False, elements=2, a, b) +i32x4.dot_i8x16_i7x16_add_s(a, b, c) = dot_product(signed=True, elements=4, a, b, c) +i32x4.dot_i8x16_i7x16_add_s(a, b, c) = dot_product(signed=False, elements=4, a, b, c) +``` + + ## Binary format All opcodes have the `0xfd` prefix (same as SIMD proposal), which are omitted in the table below. @@ -258,29 +294,32 @@ where chosen to fit into the holes in the opcode space of SIMD proposal. Going forward, the opcodes for relaxed-simd specification will be the ones in the "opcode" column, and it will take some time for tools and engines to update. -| instruction | opcode | prototype opcode | -| ----------------------------------| -------------- | ---------------- | -| `i8x16.relaxed_swizzle` | 0x100 | 0xa2 | -| `i32x4.relaxed_trunc_f32x4_s` | 0x101 | 0xa5 | -| `i32x4.relaxed_trunc_f32x4_u` | 0x102 | 0xa6 | -| `i32x4.relaxed_trunc_f64x2_s_zero`| 0x103 | 0xc5 | -| `i32x4.relaxed_trunc_f64x2_u_zero`| 0x104 | 0xc6 | -| `f32x4.relaxed_fma` | 0x105 | 0xaf | -| `f32x4.relaxed_fms` | 0x106 | 0xb0 | -| `f64x2.relaxed_fma` | 0x107 | 0xcf | -| `f64x2.relaxed_fms` | 0x108 | 0xd0 | -| `i8x16.relaxed_laneselect` | 0x109 | 0xb2 | -| `i16x8.relaxed_laneselect` | 0x10a | 0xb3 | -| `i32x4.relaxed_laneselect` | 0x10b | 0xd2 | -| `i64x2.relaxed_laneselect` | 0x10c | 0xd3 | -| `f32x4.relaxed_min` | 0x10d | 0xb4 | -| `f32x4.relaxed_max` | 0x10e | 0xe2 | -| `f64x2.relaxed_min` | 0x10f | 0xd4 | -| `f64x2.relaxed_max` | 0x110 | 0xee | -| `i16x8.relaxed_q15mulr_s` | 0x111 | unimplemented | -| Reserved for dot product | 0x112 - 0x115 | unimplemented | -| Reserved for bfloat16 dot product | 0x116 | unimplemented | -| Reserved | 0x117 - 0x12F | | +| instruction | opcode | prototype opcode | +| ---------------------------------- | -------------- | ---------------- | +| `i8x16.relaxed_swizzle` | 0x100 | 0xa2 | +| `i32x4.relaxed_trunc_f32x4_s` | 0x101 | 0xa5 | +| `i32x4.relaxed_trunc_f32x4_u` | 0x102 | 0xa6 | +| `i32x4.relaxed_trunc_f64x2_s_zero` | 0x103 | 0xc5 | +| `i32x4.relaxed_trunc_f64x2_u_zero` | 0x104 | 0xc6 | +| `f32x4.relaxed_fma` | 0x105 | 0xaf | +| `f32x4.relaxed_fms` | 0x106 | 0xb0 | +| `f64x2.relaxed_fma` | 0x107 | 0xcf | +| `f64x2.relaxed_fms` | 0x108 | 0xd0 | +| `i8x16.relaxed_laneselect` | 0x109 | 0xb2 | +| `i16x8.relaxed_laneselect` | 0x10a | 0xb3 | +| `i32x4.relaxed_laneselect` | 0x10b | 0xd2 | +| `i64x2.relaxed_laneselect` | 0x10c | 0xd3 | +| `f32x4.relaxed_min` | 0x10d | 0xb4 | +| `f32x4.relaxed_max` | 0x10e | 0xe2 | +| `f64x2.relaxed_min` | 0x10f | 0xd4 | +| `f64x2.relaxed_max` | 0x110 | 0xee | +| `i16x8.relaxed_q15mulr_s` | 0x111 | unimplemented | +| `i16x8.dot_i8x16_i7x16_s` | 0x112 | unimplemented | +| `i16x8.dot_i8x16_i7x16_u` | 0x113 | unimplemented | +| `i32x4.dot_i8x16_i7x16_add_s` | 0x114 | unimplemented | +| `i32x4.dot_i8x16_i7x16_add_u` | 0x115 | unimplemented | +| Reserved for bfloat16 | 0x116 | unimplemented | +| Reserved | 0x117 - 0x12F | | ## References From 2d63360478bf71da060ad0c63c16646c93a87bf0 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Fri, 13 May 2022 09:49:56 -0700 Subject: [PATCH 034/117] Remove unsigned dot product from overview (#73) --- proposals/relaxed-simd/Overview.md | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 7b92d3c84..f7eb71036 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -251,9 +251,7 @@ def q15mulr(a, b): ### Relaxed integer dot product - `i16x8.dot_i8x16_i7x16_s(a: v128, b: v128) -> v128` -- `i16x8.dot_i8x16_i7x16_u(a: v128, b: v128) -> v128` - `i32x4.dot_i8x16_i7x16_add_s(a: v128, b:v128, c:v128) -> v128` -- `i32x4.dot_i8x16_i7x16_add_u(a: v128, b:v128, c:v128) -> v128` Returns the multiplication of 8-bit elements (signed or unsigned) by 7-bit elements (unsigned) with accumulation of adjacent products. The `i32x4` versions @@ -278,9 +276,7 @@ def dot_product(signed, elements, a, b, c): result[i/elements] += c[i/elements] if c else 0 i16x8_dot_i8x16_i7x16_s(a, b) = dot_product(signed=True, elements=2, a, b) -i16x8_dot_i8x16_i7x16_u(a, b) = dot_product(signed=False, elements=2, a, b) -i32x4.dot_i8x16_i7x16_add_s(a, b, c) = dot_product(signed=True, elements=4, a, b, c) -i32x4.dot_i8x16_i7x16_add_s(a, b, c) = dot_product(signed=False, elements=4, a, b, c) +i32x4.dot_i8x16_i7x16_add_s(a, b, c) = dot_product(signed=False, elements=2, a, b, c) ``` @@ -315,11 +311,9 @@ forward, the opcodes for relaxed-simd specification will be the ones in the | `f64x2.relaxed_max` | 0x110 | 0xee | | `i16x8.relaxed_q15mulr_s` | 0x111 | unimplemented | | `i16x8.dot_i8x16_i7x16_s` | 0x112 | unimplemented | -| `i16x8.dot_i8x16_i7x16_u` | 0x113 | unimplemented | -| `i32x4.dot_i8x16_i7x16_add_s` | 0x114 | unimplemented | -| `i32x4.dot_i8x16_i7x16_add_u` | 0x115 | unimplemented | -| Reserved for bfloat16 | 0x116 | unimplemented | -| Reserved | 0x117 - 0x12F | | +| `i32x4.dot_i8x16_i7x16_add_s` | 0x113 | unimplemented | +| Reserved for bfloat16 | 0x114 | unimplemented | +| Reserved | 0x115 - 0x12F | | ## References From 0d63afae1c9cb22dbd4e6441a9e51cfafb0b379d Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 7 Jul 2022 22:34:41 +0000 Subject: [PATCH 035/117] More fixes for merge commits --- interpreter/binary/encode.ml | 2 -- interpreter/text/lexer.mll | 37 ++++++++++++++++++------------------ 2 files changed, 18 insertions(+), 21 deletions(-) diff --git a/interpreter/binary/encode.ml b/interpreter/binary/encode.ml index edbca5da6..59a1ad929 100644 --- a/interpreter/binary/encode.ml +++ b/interpreter/binary/encode.ml @@ -654,8 +654,6 @@ struct | VecTernary (V128 (I16x8 V128Op.RelaxedLaneselect)) -> vecop 0x10al | VecTernary (V128 (I32x4 V128Op.RelaxedLaneselect)) -> vecop 0x10bl | VecTernary (V128 (I64x2 V128Op.RelaxedLaneselect)) -> vecop 0x10cl - | VecTernary (V128 _) -> - error e.at "illegal ternary vector instruction" | VecConvert (V128 (I8x16 _)) -> error e.at "illegal i8x16 conversion instruction" diff --git a/interpreter/text/lexer.mll b/interpreter/text/lexer.mll index 22e36fe7b..ebc4fb6be 100644 --- a/interpreter/text/lexer.mll +++ b/interpreter/text/lexer.mll @@ -653,25 +653,24 @@ rule token = parse | "f32x4.replace_lane" -> VEC_REPLACE f32x4_replace_lane | "f64x2.replace_lane" -> VEC_REPLACE f64x2_replace_lane - | "i8x16.relaxed_swizzle" { VEC_BINARY i8x16_relaxed_swizzle } - | "i8x16.relaxed_swizzle" { VEC_BINARY i8x16_relaxed_swizzle } - | "i32x4.relaxed_trunc_f32x4_"(sign as s) - { VEC_UNARY (ext s i32x4_relaxed_trunc_f32x4_s i32x4_relaxed_trunc_f32x4_u) } - | "i32x4.relaxed_trunc_f64x2_"(sign as s)"_zero" - { VEC_UNARY (ext s i32x4_relaxed_trunc_f64x2_s_zero i32x4_relaxed_trunc_f64x2_u_zero) } - | (v128_float_shape as s)".relaxed_fma" - { VEC_UNARY (v128floatop s f32x4_relaxed_fma f64x2_relaxed_fma) } - | (v128_float_shape as s)".relaxed_fms" - { VEC_UNARY (v128floatop s f32x4_relaxed_fms f64x2_relaxed_fms) } - | (v128_int_shape as s)".relaxed_laneselect" - { VEC_TERNARY - (v128intop s i8x16_relaxed_laneselect i16x8_relaxed_laneselect - i32x4_relaxed_laneselect i64x2_relaxed_laneselect)} - | (v128_float_shape as s)".relaxed_min" - { VEC_UNARY (v128floatop s f32x4_relaxed_min f64x2_relaxed_min) } - | (v128_float_shape as s)".relaxed_max" - { VEC_UNARY (v128floatop s f32x4_relaxed_max f64x2_relaxed_max) } - | "i16x8.relaxed_q15mulr_s" { VEC_BINARY i16x8_relaxed_q15mulr_s } + | "i8x16.relaxed_swizzle" -> VEC_BINARY i8x16_relaxed_swizzle + | "i32x4.relaxed_trunc_f32x4_u" -> VEC_UNARY i32x4_relaxed_trunc_f32x4_u + | "i32x4.relaxed_trunc_f32x4_s" -> VEC_UNARY i32x4_relaxed_trunc_f32x4_s + | "i32x4.relaxed_trunc_f64x2_u_zero" -> VEC_UNARY i32x4_relaxed_trunc_f64x2_u_zero + | "i32x4.relaxed_trunc_f64x2_s_zero" -> VEC_UNARY i32x4_relaxed_trunc_f64x2_s_zero + | "f32x4.relaxed_fma" -> VEC_UNARY f32x4_relaxed_fma + | "f64x2.relaxed_fma" -> VEC_UNARY f64x2_relaxed_fma + | "f32x4.relaxed_fms" -> VEC_UNARY f32x4_relaxed_fms + | "f64x2.relaxed_fms" -> VEC_UNARY f64x2_relaxed_fms + | "i8x16.relaxed_laneselect" -> VEC_TERNARY i8x16_relaxed_laneselect + | "i16x8.relaxed_laneselect" -> VEC_TERNARY i16x8_relaxed_laneselect + | "i32x4.relaxed_laneselect" -> VEC_TERNARY i32x4_relaxed_laneselect + | "i64x2.relaxed_laneselect" -> VEC_TERNARY i64x2_relaxed_laneselect + | "f32x4.relaxed_min" -> VEC_UNARY f32x4_relaxed_min + | "f64x2.relaxed_min" -> VEC_UNARY f64x2_relaxed_min + | "f32x4.relaxed_max" -> VEC_UNARY f32x4_relaxed_max + | "f64x2.relaxed_max" -> VEC_UNARY f64x2_relaxed_max + | "i16x8.relaxed_q15mulr_s" -> VEC_BINARY i16x8_relaxed_q15mulr_s | "type" -> TYPE | "func" -> FUNC From a3f00372545a5f03be5f4f5fab8bfb49db0328d8 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 7 Jul 2022 22:42:17 +0000 Subject: [PATCH 036/117] More merge conflict fixes --- interpreter/text/lexer.mll | 1 + 1 file changed, 1 insertion(+) diff --git a/interpreter/text/lexer.mll b/interpreter/text/lexer.mll index ebc4fb6be..c969842a7 100644 --- a/interpreter/text/lexer.mll +++ b/interpreter/text/lexer.mll @@ -705,6 +705,7 @@ rule token = parse | "assert_exhaustion" -> ASSERT_EXHAUSTION | "nan:canonical" -> NAN Script.CanonicalNan | "nan:arithmetic" -> NAN Script.ArithmeticNan + | "either" -> EITHER | "input" -> INPUT | "output" -> OUTPUT From aff5ae08eab2e84ae8df249059bd2afa0f2c60bc Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 4 Aug 2022 23:24:29 +0000 Subject: [PATCH 037/117] Fix ordering for FMA and change FMS to FNMA (fused negative multiply add) For #27. --- proposals/relaxed-simd/Overview.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index f7eb71036..f9888e092 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -163,19 +163,19 @@ def relaxed_i32x4_trunc_f64x2_zero_u(a : f64x2) -> i32x4: result[i] = r ``` -### Relaxed fused multiply-add and fused multiply-subtract +### Relaxed fused multiply-add and fused negative multiply-add - `relaxed f32x4.fma` -- `relaxed f32x4.fms` +- `relaxed f32x4.fnma` - `relaxed f64x2.fma` -- `relaxed f64x2.fms` +- `relaxed f64x2.fnma` -All the instructions take 3 operands, `a`, `b`, `c`, perform `a + (b * c)` or `a - (b * c)`: +All the instructions take 3 operands, `a`, `b`, `c`, perform `a * b + c` or `-(a * b) + c`: -- `relaxed f32x4.fma(a, b, c) = a + (b * c)` -- `relaxed f32x4.fms(a, b, c) = a - (b * c)` -- `relaxed f64x2.fma(a, b, c) = a + (b * c)` -- `relaxed f64x2.fms(a, b, c) = a - (b * c)` +- `relaxed f32x4.fma(a, b, c) = a * b + c` +- `relaxed f32x4.fnma(a, b, c) = -(a * b) + c` +- `relaxed f64x2.fma(a, b, c) = a * b + c` +- `relaxed f64x2.fnma(a, b, c) = -(a * b) + c` where: From b58bb2e3ccf0df1db0c4826c8d5439dfb8b665f2 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 12 Sep 2022 21:48:24 +0000 Subject: [PATCH 038/117] Add BFloat16 dot product --- proposals/relaxed-simd/Overview.md | 76 ++++++++++++++++++++---------- 1 file changed, 51 insertions(+), 25 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index f9888e092..de962cbbb 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -180,7 +180,7 @@ All the instructions take 3 operands, `a`, `b`, `c`, perform `a * b + c` or `-(a where: - the intermediate `b * c` is be rounded first, and the final result rounded again (for a total of 2 roundings), or -- the the entire expression evaluated with higher precision and then only rounded once (if supported by hardware). +- the entire expression evaluated with higher precision and then only rounded once (if supported by hardware). ### Relaxed laneselect @@ -279,6 +279,32 @@ i16x8_dot_i8x16_i7x16_s(a, b) = dot_product(signed=True, elements=2, a, b i32x4.dot_i8x16_i7x16_add_s(a, b, c) = dot_product(signed=False, elements=2, a, b, c) ``` +### Relaxed BFloat16 dot product + +- `f32x4.relaxed_dot_bf16x8_add_f32x4(a: v128, b: v128, c: v128) -> v128` + +BFloat16 is a 16-bit floating-point format that represents the IEEE FP32 numbers +truncated to the high 16 bits. This instruction computes a FP32 dot product of 2 +BFloat16 with accumulation into another FP32. + +```python +def bfloat16_dot_product(a, b, c): + for i in range(8): + y.fp32[i] = + y.fp32[i] + + cast(a.bf16[2*i]) * cast(b.bf16[2*i]) + + cast(a.bf16[2*i+1]) * cast(b.bf16[2*i+1]) +``` + +This instruction is implementation defined in the following ways: + +- evaluation order + - can compute dot product in one step, then accumulation in another, or + - accumulate first product in one step, then accumulate second product in + another step +- fusion, the steps described above can be both fused or both unfused +- the intermediate results can be Round-to-Nearest-Even or Round-to-Odd. + ## Binary format @@ -290,30 +316,30 @@ where chosen to fit into the holes in the opcode space of SIMD proposal. Going forward, the opcodes for relaxed-simd specification will be the ones in the "opcode" column, and it will take some time for tools and engines to update. -| instruction | opcode | prototype opcode | -| ---------------------------------- | -------------- | ---------------- | -| `i8x16.relaxed_swizzle` | 0x100 | 0xa2 | -| `i32x4.relaxed_trunc_f32x4_s` | 0x101 | 0xa5 | -| `i32x4.relaxed_trunc_f32x4_u` | 0x102 | 0xa6 | -| `i32x4.relaxed_trunc_f64x2_s_zero` | 0x103 | 0xc5 | -| `i32x4.relaxed_trunc_f64x2_u_zero` | 0x104 | 0xc6 | -| `f32x4.relaxed_fma` | 0x105 | 0xaf | -| `f32x4.relaxed_fms` | 0x106 | 0xb0 | -| `f64x2.relaxed_fma` | 0x107 | 0xcf | -| `f64x2.relaxed_fms` | 0x108 | 0xd0 | -| `i8x16.relaxed_laneselect` | 0x109 | 0xb2 | -| `i16x8.relaxed_laneselect` | 0x10a | 0xb3 | -| `i32x4.relaxed_laneselect` | 0x10b | 0xd2 | -| `i64x2.relaxed_laneselect` | 0x10c | 0xd3 | -| `f32x4.relaxed_min` | 0x10d | 0xb4 | -| `f32x4.relaxed_max` | 0x10e | 0xe2 | -| `f64x2.relaxed_min` | 0x10f | 0xd4 | -| `f64x2.relaxed_max` | 0x110 | 0xee | -| `i16x8.relaxed_q15mulr_s` | 0x111 | unimplemented | -| `i16x8.dot_i8x16_i7x16_s` | 0x112 | unimplemented | -| `i32x4.dot_i8x16_i7x16_add_s` | 0x113 | unimplemented | -| Reserved for bfloat16 | 0x114 | unimplemented | -| Reserved | 0x115 - 0x12F | | +| instruction | opcode | prototype opcode | +| ------------------------------------ | -------------- | ---------------- | +| `i8x16.relaxed_swizzle` | 0x100 | 0xa2 | +| `i32x4.relaxed_trunc_f32x4_s` | 0x101 | 0xa5 | +| `i32x4.relaxed_trunc_f32x4_u` | 0x102 | 0xa6 | +| `i32x4.relaxed_trunc_f64x2_s_zero` | 0x103 | 0xc5 | +| `i32x4.relaxed_trunc_f64x2_u_zero` | 0x104 | 0xc6 | +| `f32x4.relaxed_fma` | 0x105 | 0xaf | +| `f32x4.relaxed_fms` | 0x106 | 0xb0 | +| `f64x2.relaxed_fma` | 0x107 | 0xcf | +| `f64x2.relaxed_fms` | 0x108 | 0xd0 | +| `i8x16.relaxed_laneselect` | 0x109 | 0xb2 | +| `i16x8.relaxed_laneselect` | 0x10a | 0xb3 | +| `i32x4.relaxed_laneselect` | 0x10b | 0xd2 | +| `i64x2.relaxed_laneselect` | 0x10c | 0xd3 | +| `f32x4.relaxed_min` | 0x10d | 0xb4 | +| `f32x4.relaxed_max` | 0x10e | 0xe2 | +| `f64x2.relaxed_min` | 0x10f | 0xd4 | +| `f64x2.relaxed_max` | 0x110 | 0xee | +| `i16x8.relaxed_q15mulr_s` | 0x111 | unimplemented | +| `i16x8.dot_i8x16_i7x16_s` | 0x112 | unimplemented | +| `i32x4.dot_i8x16_i7x16_add_s` | 0x113 | unimplemented | +| `f32x4.relaxed_dot_bf16x8_add_f32x4` | 0x114 | unimplemented | +| Reserved | 0x115 - 0x12F | | ## References From 0018aeb4ff8236119495116a3ed88b814f3c9673 Mon Sep 17 00:00:00 2001 From: Yury Delendik Date: Wed, 21 Sep 2022 10:31:02 -0500 Subject: [PATCH 039/117] Fix fnma instruction name and details --- proposals/relaxed-simd/Overview.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index de962cbbb..8cc77d369 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -179,7 +179,7 @@ All the instructions take 3 operands, `a`, `b`, `c`, perform `a * b + c` or `-(a where: -- the intermediate `b * c` is be rounded first, and the final result rounded again (for a total of 2 roundings), or +- the intermediate `a * b` is be rounded first, and the final result rounded again (for a total of 2 roundings), or - the entire expression evaluated with higher precision and then only rounded once (if supported by hardware). ### Relaxed laneselect @@ -324,9 +324,9 @@ forward, the opcodes for relaxed-simd specification will be the ones in the | `i32x4.relaxed_trunc_f64x2_s_zero` | 0x103 | 0xc5 | | `i32x4.relaxed_trunc_f64x2_u_zero` | 0x104 | 0xc6 | | `f32x4.relaxed_fma` | 0x105 | 0xaf | -| `f32x4.relaxed_fms` | 0x106 | 0xb0 | +| `f32x4.relaxed_fnma` | 0x106 | 0xb0 | | `f64x2.relaxed_fma` | 0x107 | 0xcf | -| `f64x2.relaxed_fms` | 0x108 | 0xd0 | +| `f64x2.relaxed_fnma` | 0x108 | 0xd0 | | `i8x16.relaxed_laneselect` | 0x109 | 0xb2 | | `i16x8.relaxed_laneselect` | 0x10a | 0xb3 | | `i32x4.relaxed_laneselect` | 0x10b | 0xd2 | From 8cbfd34a7f546fad6f92bb0c8848d18a0da14e4b Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 24 Oct 2022 19:58:19 +0000 Subject: [PATCH 040/117] Update implementation status with bf16 dot product and fnma --- .../relaxed-simd/ImplementationStatus.md | 94 +++++++++---------- 1 file changed, 46 insertions(+), 48 deletions(-) diff --git a/proposals/relaxed-simd/ImplementationStatus.md b/proposals/relaxed-simd/ImplementationStatus.md index fa3457a65..4360ec9ea 100644 --- a/proposals/relaxed-simd/ImplementationStatus.md +++ b/proposals/relaxed-simd/ImplementationStatus.md @@ -1,29 +1,28 @@ ## Implementation in LLVM and various engines -| Instruction | LLVM [1] | V8 [2] | SpiderMonkey [3] | -|------------------------------------|----------------|--------------------|--------------------| -| `relaxed i8x16.swizzle` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `relaxed i32x4.trunc_f32x4_s` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `relaxed i32x4.trunc_f32x4_u` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `relaxed i32x4.trunc_f64x2_s_zero` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `relaxed i32x4.trunc_f64x2_u_zero` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.fma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.fms` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.fma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.fms` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `i64x2.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.min` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.min` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.relaxed_q15mulr_s` | | | | -| `i16x8.dot_i8x16_i7x16_s` | | | | -| `i16x8.dot_i8x16_i7x16_u` | | | | -| `i32x4.dot_i8x16_i7x16_add_s` | | | | -| `i32x4.dot_i8x16_i7x16_add_u` | | | | +| Instruction | LLVM [1] | V8 [2] | SpiderMonkey [3] | +|--------------------------------------|----------------|--------------------|--------------------| +| `relaxed i8x16.swizzle` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `relaxed i32x4.trunc_f32x4_s` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `relaxed i32x4.trunc_f32x4_u` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `relaxed i32x4.trunc_f64x2_s_zero` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `relaxed i32x4.trunc_f64x2_u_zero` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.fma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.fnma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.fma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.fnma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i8x16.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i16x8.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i32x4.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i64x2.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.min` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.min` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i16x8.relaxed_q15mulr_s` | | | | +| `i16x8.dot_i8x16_i7x16_s` | | | | +| `i32x4.dot_i8x16_i7x16_add_s` | | | | +| `f32x4.relaxed_dot_bf16x8_add_f32x4` | | | | [1] Tip of tree LLVM as of 2021-10-28 @@ -34,27 +33,26 @@ ## Name of builtins in LLVM -| Instruction | LLVM | -|------------------------------------|---------------------------------------------------| -| `relaxed i8x16.swizzle` | `__builtin_wasm_relaxed_swizzle_i8x16` | -| `relaxed i32x4.trunc_f32x4_s` | `__builtin_wasm_relaxed_trunc_s_i32x4_f32x4` | -| `relaxed i32x4.trunc_f32x4_u` | `__builtin_wasm_relaxed_trunc_u_i32x4_f32x4` | -| `relaxed i32x4.trunc_f64x2_s_zero` | `__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2` | -| `relaxed i32x4.trunc_f64x2_u_zero` | `__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2` | -| `f32x4.fma` | `__builtin_wasm_fma_f32x4` | -| `f32x4.fms` | `__builtin_wasm_fms_f32x4` | -| `f64x2.fma` | `__builtin_wasm_fma_f64x2` | -| `f64x2.fms` | `__builtin_wasm_fms_f64x2` | -| `i8x16.laneselect` | `__builtin_wasm_laneselect_i8x16` | -| `i16x8.laneselect` | `__builtin_wasm_laneselect_i16x8` | -| `i32x4.laneselect` | `__builtin_wasm_laneselect_i32x4` | -| `i64x2.laneselect` | `__builtin_wasm_laneselect_i64x2` | -| `f32x4.min` | `__builtin_wasm_relaxed_min_f32x4` | -| `f32x4.max` | `__builtin_wasm_relaxed_max_f32x4` | -| `f64x2.min` | `__builtin_wasm_relaxed_min_f64x2` | -| `f64x2.max` | `__builtin_wasm_relaxed_max_f64x2` | -| `i16x8.relaxed_q15mulr_s` | | -| `i16x8.dot_i8x16_i7x16_s` | | -| `i16x8.dot_i8x16_i7x16_u` | | -| `i32x4.dot_i8x16_i7x16_add_s` | | -| `i32x4.dot_i8x16_i7x16_add_u` | | +| Instruction | LLVM | +|--------------------------------------|---------------------------------------------------| +| `relaxed i8x16.swizzle` | `__builtin_wasm_relaxed_swizzle_i8x16` | +| `relaxed i32x4.trunc_f32x4_s` | `__builtin_wasm_relaxed_trunc_s_i32x4_f32x4` | +| `relaxed i32x4.trunc_f32x4_u` | `__builtin_wasm_relaxed_trunc_u_i32x4_f32x4` | +| `relaxed i32x4.trunc_f64x2_s_zero` | `__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2` | +| `relaxed i32x4.trunc_f64x2_u_zero` | `__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2` | +| `f32x4.fma` | `__builtin_wasm_fma_f32x4` | +| `f32x4.fnma` | `__builtin_wasm_fnma_f32x4` | +| `f64x2.fma` | `__builtin_wasm_fma_f64x2` | +| `f64x2.fnma` | `__builtin_wasm_fnma_f64x2` | +| `i8x16.laneselect` | `__builtin_wasm_laneselect_i8x16` | +| `i16x8.laneselect` | `__builtin_wasm_laneselect_i16x8` | +| `i32x4.laneselect` | `__builtin_wasm_laneselect_i32x4` | +| `i64x2.laneselect` | `__builtin_wasm_laneselect_i64x2` | +| `f32x4.min` | `__builtin_wasm_relaxed_min_f32x4` | +| `f32x4.max` | `__builtin_wasm_relaxed_max_f32x4` | +| `f64x2.min` | `__builtin_wasm_relaxed_min_f64x2` | +| `f64x2.max` | `__builtin_wasm_relaxed_max_f64x2` | +| `i16x8.relaxed_q15mulr_s` | | +| `i16x8.dot_i8x16_i7x16_s` | | +| `i32x4.dot_i8x16_i7x16_add_s` | | +| `f32x4.relaxed_dot_bf16x8_add_f32x4` | | From 65707248e8d1c9f2d7fbd92679640781d2ef4c0a Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 24 Oct 2022 20:37:13 +0000 Subject: [PATCH 041/117] Fix overview for integer dot products and implementation status --- proposals/relaxed-simd/ImplementationStatus.md | 16 ++++++++-------- proposals/relaxed-simd/Overview.md | 6 +++--- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/proposals/relaxed-simd/ImplementationStatus.md b/proposals/relaxed-simd/ImplementationStatus.md index 4360ec9ea..6e6acfaaa 100644 --- a/proposals/relaxed-simd/ImplementationStatus.md +++ b/proposals/relaxed-simd/ImplementationStatus.md @@ -19,10 +19,10 @@ | `f32x4.max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | | `f64x2.min` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | | `f64x2.max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.relaxed_q15mulr_s` | | | | -| `i16x8.dot_i8x16_i7x16_s` | | | | -| `i32x4.dot_i8x16_i7x16_add_s` | | | | -| `f32x4.relaxed_dot_bf16x8_add_f32x4` | | | | +| `i16x8.relaxed_q15mulr_s` | -mrelaxed-simd | | | +| `i16x8.dot_i8x16_i7x16_s` | -mrelaxed-simd | | | +| `i32x4.dot_i8x16_i7x16_add_s` | -mrelaxed-simd | | | +| `f32x4.relaxed_dot_bf16x8_add_f32x4` | -mrelaxed-simd | | | [1] Tip of tree LLVM as of 2021-10-28 @@ -52,7 +52,7 @@ | `f32x4.max` | `__builtin_wasm_relaxed_max_f32x4` | | `f64x2.min` | `__builtin_wasm_relaxed_min_f64x2` | | `f64x2.max` | `__builtin_wasm_relaxed_max_f64x2` | -| `i16x8.relaxed_q15mulr_s` | | -| `i16x8.dot_i8x16_i7x16_s` | | -| `i32x4.dot_i8x16_i7x16_add_s` | | -| `f32x4.relaxed_dot_bf16x8_add_f32x4` | | +| `i16x8.relaxed_q15mulr_s` | `__builtin_wasm_relaxed_q15mulr_s_i16x8` | +| `i16x8.dot_i8x16_i7x16_s` | `__builtin_wasm_dot_i8x16_i7x16_s_i16x8` | +| `i32x4.dot_i8x16_i7x16_add_s` | `__builtin_wasm_dot_i8x16_i7x16_add_s_i32x4` | +| `f32x4.relaxed_dot_bf16x8_add_f32x4` | `__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4` | diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 8cc77d369..27d45bb74 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -268,15 +268,15 @@ def dot_product(signed, elements, a, b, c): if (b[i] & 0x80): lhs = as_signed(a[i]) if signed else a[i] rhs = IMPLEMENTATION_DEFINED_ONE_OF(as_signed(b[i]), b[i]) - intermediate[i] = lhs + rhs + intermediate[i] = lhs * rhs else: intermediate[i] = (as_signed(a[i]) if signed else a[i]) * b[i] for i in range(0, 16, elements): - result[i/elements] == sum(intermediate[i:i+elements]) + result[i/elements] = sum(intermediate[i:i+elements]) result[i/elements] += c[i/elements] if c else 0 i16x8_dot_i8x16_i7x16_s(a, b) = dot_product(signed=True, elements=2, a, b) -i32x4.dot_i8x16_i7x16_add_s(a, b, c) = dot_product(signed=False, elements=2, a, b, c) +i32x4.dot_i8x16_i7x16_add_s(a, b, c) = dot_product(signed=True, elements=4, a, b, c) ``` ### Relaxed BFloat16 dot product From 8697e477a2f052c47a3664a9be77971ba50ece02 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 24 Oct 2022 20:29:20 +0000 Subject: [PATCH 042/117] Add some relaxed dot product tests For #94. --- .../relaxed-simd/relaxed_dot_product.wast | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 test/core/relaxed-simd/relaxed_dot_product.wast diff --git a/test/core/relaxed-simd/relaxed_dot_product.wast b/test/core/relaxed-simd/relaxed_dot_product.wast new file mode 100644 index 000000000..d819c7a0f --- /dev/null +++ b/test/core/relaxed-simd/relaxed_dot_product.wast @@ -0,0 +1,43 @@ +;; Tests for relaxed dot products. + +(module + (func (export "i16x8.dot_i8x16_i7x16_s") (param v128 v128) (result v128) (i16x8.dot_i8x16_i7x16_s (local.get 0) (local.get 1))) + (func (export "i32x4.dot_i8x16_i7x16_add_s") (param v128 v128 v128) (result v128) (i32x4.dot_i8x16_i7x16_add_s (local.get 0) (local.get 1) (local.get 2))) + (func (export "f32x4.relaxed_dot_bf16x8_add_f32x4") (param v128 v128 v128) (result v128) (f32x4.relaxed_dot_bf16x8_add_f32x4 (local.get 0) (local.get 1) (local.get 2))) +) + +;; Simple values to ensure things are functional. +(assert_return (invoke "i16x8.dot_i8x16_i7x16_s" + (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) + (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) + (v128.const i16x8 1 13 41 85 145 221 313 421)) + +;; Test max and min i8 values; +(assert_return (invoke "i16x8.dot_i8x16_i7x16_s" + (v128.const i8x16 -128 -128 127 127 0 0 0 0 0 0 0 0 0 0 0 0) + (v128.const i8x16 127 127 127 127 0 0 0 0 0 0 0 0 0 0 0 0 0)) + (v128.const i16x8 -32512 32512 0 0 0 0 0 0)) + +;; Simple values to ensure things are functional. +(assert_return (invoke "i32x4.dot_i8x16_i7x16_add_s" + (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) + (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) + (v128.const i32x4 0 1 2 3)) + ;; intermediate result is [14, 126, 366, 734] + (v128.const f32x4 14 127 368 737)) + +;; Test max and min i8 values; +(assert_return (invoke "i32x4.dot_i8x16_i7x16_add_s" + (v128.const i8x16 -128 -128 -128 -128 127 127 127 127 0 0 0 0 0 0 0 0) + (v128.const i8x16 127 127 127 127 127 127 127 127 0 0 0 0 0 0 0 0) + (v128.const i32x4 0 1 2 3)) + ;; intermediate result is [-65024, 65024, 0, 0] + (v128.const f32x4 -65024 65024 0 0)) + +;; Simple values to ensure things are functional. +(assert_return (invoke "f32x4.relaxed_dot_bf16x8_add_f32x4" + (v128.const i16x8 0x0000 0x3f80 0x4000 0x4040 0x4080 0x40a0 0x40c0 0x40e0) ;; [0.0f, 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f] + (v128.const i16x8 0x0000 0x3f80 0x4000 0x4040 0x4080 0x40a0 0x40c0 0x40e0) + (v128.const f32x4 0 1 2 3)) + ;; intermediate result is [1, 13, 41, 85] + (v128.const f32x4 1 14 43 88)) From 3935fe9215c501f395f6a1222f0038b04f5431a4 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 24 Oct 2022 21:14:03 +0000 Subject: [PATCH 043/117] Fix number of lane literals --- test/core/relaxed-simd/relaxed_dot_product.wast | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/core/relaxed-simd/relaxed_dot_product.wast b/test/core/relaxed-simd/relaxed_dot_product.wast index d819c7a0f..a74c43e02 100644 --- a/test/core/relaxed-simd/relaxed_dot_product.wast +++ b/test/core/relaxed-simd/relaxed_dot_product.wast @@ -15,7 +15,7 @@ ;; Test max and min i8 values; (assert_return (invoke "i16x8.dot_i8x16_i7x16_s" (v128.const i8x16 -128 -128 127 127 0 0 0 0 0 0 0 0 0 0 0 0) - (v128.const i8x16 127 127 127 127 0 0 0 0 0 0 0 0 0 0 0 0 0)) + (v128.const i8x16 127 127 127 127 0 0 0 0 0 0 0 0 0 0 0 0)) (v128.const i16x8 -32512 32512 0 0 0 0 0 0)) ;; Simple values to ensure things are functional. From e35df3a0011a34b3a51dc3298c1687d62af19a75 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 24 Oct 2022 21:21:15 +0000 Subject: [PATCH 044/117] Fix test results --- test/core/relaxed-simd/relaxed_dot_product.wast | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/test/core/relaxed-simd/relaxed_dot_product.wast b/test/core/relaxed-simd/relaxed_dot_product.wast index a74c43e02..245b1db17 100644 --- a/test/core/relaxed-simd/relaxed_dot_product.wast +++ b/test/core/relaxed-simd/relaxed_dot_product.wast @@ -16,7 +16,7 @@ (assert_return (invoke "i16x8.dot_i8x16_i7x16_s" (v128.const i8x16 -128 -128 127 127 0 0 0 0 0 0 0 0 0 0 0 0) (v128.const i8x16 127 127 127 127 0 0 0 0 0 0 0 0 0 0 0 0)) - (v128.const i16x8 -32512 32512 0 0 0 0 0 0)) + (v128.const i16x8 -32512 32258 0 0 0 0 0 0)) ;; Simple values to ensure things are functional. (assert_return (invoke "i32x4.dot_i8x16_i7x16_add_s" @@ -30,9 +30,9 @@ (assert_return (invoke "i32x4.dot_i8x16_i7x16_add_s" (v128.const i8x16 -128 -128 -128 -128 127 127 127 127 0 0 0 0 0 0 0 0) (v128.const i8x16 127 127 127 127 127 127 127 127 0 0 0 0 0 0 0 0) - (v128.const i32x4 0 1 2 3)) - ;; intermediate result is [-65024, 65024, 0, 0] - (v128.const f32x4 -65024 65024 0 0)) + (v128.const i32x4 1 2 3 4)) + ;; intermediate result is [-65024, 64516, 0, 0] + (v128.const f32x4 -65023 64518 3 4)) ;; Simple values to ensure things are functional. (assert_return (invoke "f32x4.relaxed_dot_bf16x8_add_f32x4" From 2dc7f2fb0be71a26ad0f6dfbe5790aaedd6e3cbe Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 24 Oct 2022 21:01:25 +0000 Subject: [PATCH 045/117] Fix fms -> fnma, add relaxed dot --- interpreter/binary/encode.ml | 9 +++++++-- interpreter/syntax/ast.ml | 6 +++--- interpreter/syntax/operators.ml | 7 +++++-- interpreter/text/arrange.ml | 9 ++++++++- interpreter/text/lexer.mll | 7 +++++-- test/core/relaxed-simd/relaxed_fma_fms.wast | 10 +++++----- 6 files changed, 33 insertions(+), 15 deletions(-) diff --git a/interpreter/binary/encode.ml b/interpreter/binary/encode.ml index 59a1ad929..b61fb29ec 100644 --- a/interpreter/binary/encode.ml +++ b/interpreter/binary/encode.ml @@ -604,6 +604,7 @@ struct | VecBinary (V128 (I16x8 V128Op.ExtMulHighU)) -> vecop 0x9fl | VecBinary (V128 (I16x8 V128Op.Q15MulRSatS)) -> vecop 0x82l | VecBinary (V128 (I16x8 V128Op.RelaxedQ15MulRS)) -> vecop 0x111l + | VecBinary (V128 (I16x8 V128Op.RelaxedDot)) -> vecop 0x112l | VecBinary (V128 (I32x4 V128Op.Add)) -> vecop 0xael | VecBinary (V128 (I32x4 V128Op.Sub)) -> vecop 0xb1l | VecBinary (V128 (I32x4 V128Op.MinS)) -> vecop 0xb6l @@ -647,13 +648,17 @@ struct error e.at "illegal binary vector instruction" | VecTernary (V128 (F32x4 V128Op.RelaxedFma)) -> vecop 0x105l - | VecTernary (V128 (F32x4 V128Op.RelaxedFms)) -> vecop 0x106l + | VecTernary (V128 (F32x4 V128Op.RelaxedFnma)) -> vecop 0x106l | VecTernary (V128 (F64x2 V128Op.RelaxedFma)) -> vecop 0x107l - | VecTernary (V128 (F64x2 V128Op.RelaxedFms)) -> vecop 0x108l + | VecTernary (V128 (F64x2 V128Op.RelaxedFnma)) -> vecop 0x108l | VecTernary (V128 (I8x16 V128Op.RelaxedLaneselect)) -> vecop 0x109l | VecTernary (V128 (I16x8 V128Op.RelaxedLaneselect)) -> vecop 0x10al | VecTernary (V128 (I32x4 V128Op.RelaxedLaneselect)) -> vecop 0x10bl | VecTernary (V128 (I64x2 V128Op.RelaxedLaneselect)) -> vecop 0x10cl + | VecTernary (V128 (I32x4 V128Op.RelaxedDotAccum)) -> vecop 0x113l + | VecTernary (V128 (F32x4 V128Op.RelaxedDotAccum)) -> vecop 0x114l + | VecTernary (V128 _) -> + error e.at "illegal ternary vector instruction" | VecConvert (V128 (I8x16 _)) -> error e.at "illegal i8x16 conversion instruction" diff --git a/interpreter/syntax/ast.ml b/interpreter/syntax/ast.ml index f6c9ac696..b2d7803e4 100644 --- a/interpreter/syntax/ast.ml +++ b/interpreter/syntax/ast.ml @@ -61,11 +61,11 @@ struct | AddSatS | AddSatU | SubSatS | SubSatU | DotS | Q15MulRSatS | ExtMulLowS | ExtMulHighS | ExtMulLowU | ExtMulHighU | Swizzle | Shuffle of int list | NarrowS | NarrowU - | RelaxedSwizzle | RelaxedQ15MulRS + | RelaxedSwizzle | RelaxedQ15MulRS | RelaxedDot type fbinop = Add | Sub | Mul | Div | Min | Max | Pmin | Pmax | RelaxedMin | RelaxedMax - type iternop = RelaxedLaneselect - type fternop = RelaxedFma | RelaxedFms + type iternop = RelaxedLaneselect | RelaxedDotAccum + type fternop = RelaxedFma | RelaxedFnma | RelaxedDotAccum type irelop = Eq | Ne | LtS | LtU | LeS | LeU | GtS | GtU | GeS | GeU type frelop = Eq | Ne | Lt | Le | Gt | Ge type icvtop = ExtendLowS | ExtendLowU | ExtendHighS | ExtendHighU diff --git a/interpreter/syntax/operators.ml b/interpreter/syntax/operators.ml index fc135534a..60f5a9d6e 100644 --- a/interpreter/syntax/operators.ml +++ b/interpreter/syntax/operators.ml @@ -512,10 +512,13 @@ let i32x4_relaxed_trunc_f64x2_u_zero = VecConvert (V128 (I32x4 V128Op.RelaxedTru let i32x4_relaxed_laneselect = VecTernary (V128 (I32x4 V128Op.RelaxedLaneselect)) let i64x2_relaxed_laneselect = VecTernary (V128 (I64x2 V128Op.RelaxedLaneselect)) let f32x4_relaxed_fma = VecTernary (V128 (F32x4 V128Op.RelaxedFma)) -let f32x4_relaxed_fms = VecTernary (V128 (F32x4 V128Op.RelaxedFms)) +let f32x4_relaxed_fnma = VecTernary (V128 (F32x4 V128Op.RelaxedFnma)) let f32x4_relaxed_min = VecBinary (V128 (F32x4 V128Op.RelaxedMin)) let f32x4_relaxed_max = VecBinary (V128 (F32x4 V128Op.RelaxedMax)) let f64x2_relaxed_fma = VecTernary (V128 (F64x2 V128Op.RelaxedFma)) -let f64x2_relaxed_fms = VecTernary (V128 (F64x2 V128Op.RelaxedFms)) +let f64x2_relaxed_fnma = VecTernary (V128 (F64x2 V128Op.RelaxedFnma)) let f64x2_relaxed_min = VecBinary (V128 (F64x2 V128Op.RelaxedMin)) let f64x2_relaxed_max = VecBinary (V128 (F64x2 V128Op.RelaxedMax)) +let i16x8_dot_i8x16_i7x16_s = VecBinary (V128 (I16x8 V128Op.RelaxedDot)) +let i32x4_dot_i8x16_i7x16_add_s = VecTernary (V128 (I32x4 V128Op.RelaxedDotAccum)) +let f32x4_relaxed_dot_bf16x8_add_f32x4 = VecTernary (V128 (F32x4 V128Op.RelaxedDotAccum)) diff --git a/interpreter/text/arrange.ml b/interpreter/text/arrange.ml index 7d67a9777..c3997d4c6 100644 --- a/interpreter/text/arrange.ml +++ b/interpreter/text/arrange.ml @@ -213,6 +213,10 @@ struct | "32x4" -> "64x2" | _ -> assert false + let without_high_bit = function + | "8x16" -> "7x16" + | _ -> assert false + let voidop xxxx = function (_ : void) -> . let itestop xxxx (op : itestop) = match op with @@ -257,9 +261,11 @@ struct | Swizzle -> "swizzle" | RelaxedSwizzle -> "relaxed_swizzle" | RelaxedQ15MulRS -> "relaxed_q15mulr_s" + | RelaxedDot -> "relaxed_dot_i" ^ half xxxx ^ "_i" ^ without_high_bit (half xxxx) ^ "_s" let iternop xxxx (op : iternop) = match op with | RelaxedLaneselect -> "relaxed_laneselect" + | RelaxedDotAccum -> "relaxed_dot_i" ^ half (half xxxx) ^ "_i" ^ without_high_bit (half (half xxxx)) ^ "add_s" let fbinop xxxx (op : fbinop) = match op with | Add -> "add" @@ -275,7 +281,8 @@ struct let fternop xxxx (op : fternop) = match op with | RelaxedFma -> "relaxed_fma" - | RelaxedFms -> "relaxed_fms" + | RelaxedFnma-> "relaxed_fnma" + | RelaxedDotAccum -> "relaxed_dot_bf" ^ half (half xxxx) ^ "_add_" ^ xxxx let irelop xxxx (op : irelop) = match op with | Eq -> "eq" diff --git a/interpreter/text/lexer.mll b/interpreter/text/lexer.mll index c969842a7..82da94df9 100644 --- a/interpreter/text/lexer.mll +++ b/interpreter/text/lexer.mll @@ -660,8 +660,8 @@ rule token = parse | "i32x4.relaxed_trunc_f64x2_s_zero" -> VEC_UNARY i32x4_relaxed_trunc_f64x2_s_zero | "f32x4.relaxed_fma" -> VEC_UNARY f32x4_relaxed_fma | "f64x2.relaxed_fma" -> VEC_UNARY f64x2_relaxed_fma - | "f32x4.relaxed_fms" -> VEC_UNARY f32x4_relaxed_fms - | "f64x2.relaxed_fms" -> VEC_UNARY f64x2_relaxed_fms + | "f32x4.relaxed_fnma" -> VEC_UNARY f32x4_relaxed_fnma + | "f64x2.relaxed_fnma" -> VEC_UNARY f64x2_relaxed_fnma | "i8x16.relaxed_laneselect" -> VEC_TERNARY i8x16_relaxed_laneselect | "i16x8.relaxed_laneselect" -> VEC_TERNARY i16x8_relaxed_laneselect | "i32x4.relaxed_laneselect" -> VEC_TERNARY i32x4_relaxed_laneselect @@ -671,6 +671,9 @@ rule token = parse | "f32x4.relaxed_max" -> VEC_UNARY f32x4_relaxed_max | "f64x2.relaxed_max" -> VEC_UNARY f64x2_relaxed_max | "i16x8.relaxed_q15mulr_s" -> VEC_BINARY i16x8_relaxed_q15mulr_s + | "i16x8.dot_i8x16_i7x16_s" -> VEC_BINARY i16x8_dot_i8x16_i7x16_s + | "i32x4.dot_i8x16_i7x16_add_s" -> VEC_BINARY i32x4_dot_i8x16_i7x16_add_s + | "f32x4.relaxed_dot_bf16x8_add_f32x4" -> VEC_BINARY f32x4_relaxed_dot_bf16x8_add_f32x4 | "type" -> TYPE | "func" -> FUNC diff --git a/test/core/relaxed-simd/relaxed_fma_fms.wast b/test/core/relaxed-simd/relaxed_fma_fms.wast index d895d88d6..03666a02a 100644 --- a/test/core/relaxed-simd/relaxed_fma_fms.wast +++ b/test/core/relaxed-simd/relaxed_fma_fms.wast @@ -1,9 +1,9 @@ -;; Tests for f32x4.relaxed_fma, f32x4.relaxed_fms, f64x2.relaxed_fma, and f64x2.relaxed_fms. +;; Tests for f32x4.relaxed_fma, f32x4.relaxed_fnma, f64x2.relaxed_fma, and f64x2.relaxed_fnma. (module (func (export "f32x4.relaxed_fma") (param v128 v128 v128) (result v128) (f32x4.relaxed_fma (local.get 0) (local.get 1) (local.get 2))) - (func (export "f32x4.relaxed_fms") (param v128 v128 v128) (result v128) (f32x4.relaxed_fms (local.get 0) (local.get 1) (local.get 2))) - (func (export "f64x2.relaxed_fms") (param v128 v128 v128) (result v128) (f64x2.relaxed_fms (local.get 0) (local.get 1) (local.get 2))) + (func (export "f32x4.relaxed_fnma") (param v128 v128 v128) (result v128) (f32x4.relaxed_fnma (local.get 0) (local.get 1) (local.get 2))) + (func (export "f64x2.relaxed_fnma") (param v128 v128 v128) (result v128) (f64x2.relaxed_fnma (local.get 0) (local.get 1) (local.get 2))) (func (export "f64x2.relaxed_fma") (param v128 v128 v128) (result v128) (f64x2.relaxed_fma (local.get 0) (local.get 1) (local.get 2))) ) @@ -35,7 +35,7 @@ (v128.const f32x4 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0)) (either (v128.const f32x4 0x1p-37 0x1p-37 0x1p-37 0x1p-37) (v128.const f32x4 0 0 0 0))) -(assert_return (invoke "f32x4.relaxed_fms" +(assert_return (invoke "f32x4.relaxed_fnma" (v128.const f32x4 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0) (v128.const f32x4 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0) (v128.const f32x4 0x1.000204p+0 0x1.000204p+0 0x1.000204p+0 0x1.000204p+0)) @@ -70,7 +70,7 @@ (v128.const f64x2 -0x1.00000204p+0 -0x1.00000204p+0)) (either (v128.const f64x2 0x1p-53 0x1p-53) (v128.const f64x2 0 0))) -(assert_return (invoke "f64x2.relaxed_fms" +(assert_return (invoke "f64x2.relaxed_fnma" (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) (v128.const f64x2 0x1.000002p+0 0x1.000002p+0) (v128.const f64x2 0x1.00000204p+0 0x1.00000204p+0)) From 0f19aecbbf3a05c285f7e3e9d7f8150182ce85a0 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 24 Oct 2022 21:19:21 +0000 Subject: [PATCH 046/117] Rename fma test file --- .../relaxed-simd/{relaxed_fma_fms.wast => relaxed_fma_fnma.wast} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename test/core/relaxed-simd/{relaxed_fma_fms.wast => relaxed_fma_fnma.wast} (100%) diff --git a/test/core/relaxed-simd/relaxed_fma_fms.wast b/test/core/relaxed-simd/relaxed_fma_fnma.wast similarity index 100% rename from test/core/relaxed-simd/relaxed_fma_fms.wast rename to test/core/relaxed-simd/relaxed_fma_fnma.wast From c37343389e2b34ad425adcfa388b85c6b511dcf2 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 24 Oct 2022 21:10:34 +0000 Subject: [PATCH 047/117] Fix to instruction names in overview and implementation status --- .../relaxed-simd/ImplementationStatus.md | 92 +++++++++---------- proposals/relaxed-simd/Overview.md | 48 +++++----- 2 files changed, 70 insertions(+), 70 deletions(-) diff --git a/proposals/relaxed-simd/ImplementationStatus.md b/proposals/relaxed-simd/ImplementationStatus.md index 6e6acfaaa..59bcf0bc0 100644 --- a/proposals/relaxed-simd/ImplementationStatus.md +++ b/proposals/relaxed-simd/ImplementationStatus.md @@ -1,28 +1,28 @@ ## Implementation in LLVM and various engines -| Instruction | LLVM [1] | V8 [2] | SpiderMonkey [3] | -|--------------------------------------|----------------|--------------------|--------------------| -| `relaxed i8x16.swizzle` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `relaxed i32x4.trunc_f32x4_s` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `relaxed i32x4.trunc_f32x4_u` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `relaxed i32x4.trunc_f64x2_s_zero` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `relaxed i32x4.trunc_f64x2_u_zero` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.fma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.fnma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.fma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.fnma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `i8x16.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `i32x4.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `i64x2.laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.min` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.min` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.relaxed_q15mulr_s` | -mrelaxed-simd | | | -| `i16x8.dot_i8x16_i7x16_s` | -mrelaxed-simd | | | -| `i32x4.dot_i8x16_i7x16_add_s` | -mrelaxed-simd | | | -| `f32x4.relaxed_dot_bf16x8_add_f32x4` | -mrelaxed-simd | | | +| Instruction | LLVM [1] | V8 [2] | SpiderMonkey [3] | +|---------------------------------------|----------------|--------------------|--------------------| +| `i8x16.relaxed_swizzle` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i32x4.relaxed_trunc_f32x4_s` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i32x4.relaxed_trunc_f32x4_u` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i32x4.relaxed_trunc_f64x2_s_zero` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i32x4.relaxed_trunc_f64x2_u_zero` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.relaxed_fma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.relaxed_fnma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.relaxed_fma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.relaxed_fnma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i8x16.relaxed_laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i16x8.relaxed_laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i32x4.relaxed_laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i64x2.relaxed_laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.relaxed_min` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.relaxed_max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.relaxed_min` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.relaxed_max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i16x8.relaxed_q15mulr_s` | -mrelaxed-simd | | | +| `i16x8.relaxed_dot_i8x16_i7x16_s` | -mrelaxed-simd | | | +| `i32x4.relaxed_dot_i8x16_i7x16_add_s` | -mrelaxed-simd | | | +| `f32x4.relaxed_dot_bf16x8_add_f32x4` | -mrelaxed-simd | | | [1] Tip of tree LLVM as of 2021-10-28 @@ -33,26 +33,26 @@ ## Name of builtins in LLVM -| Instruction | LLVM | -|--------------------------------------|---------------------------------------------------| -| `relaxed i8x16.swizzle` | `__builtin_wasm_relaxed_swizzle_i8x16` | -| `relaxed i32x4.trunc_f32x4_s` | `__builtin_wasm_relaxed_trunc_s_i32x4_f32x4` | -| `relaxed i32x4.trunc_f32x4_u` | `__builtin_wasm_relaxed_trunc_u_i32x4_f32x4` | -| `relaxed i32x4.trunc_f64x2_s_zero` | `__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2` | -| `relaxed i32x4.trunc_f64x2_u_zero` | `__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2` | -| `f32x4.fma` | `__builtin_wasm_fma_f32x4` | -| `f32x4.fnma` | `__builtin_wasm_fnma_f32x4` | -| `f64x2.fma` | `__builtin_wasm_fma_f64x2` | -| `f64x2.fnma` | `__builtin_wasm_fnma_f64x2` | -| `i8x16.laneselect` | `__builtin_wasm_laneselect_i8x16` | -| `i16x8.laneselect` | `__builtin_wasm_laneselect_i16x8` | -| `i32x4.laneselect` | `__builtin_wasm_laneselect_i32x4` | -| `i64x2.laneselect` | `__builtin_wasm_laneselect_i64x2` | -| `f32x4.min` | `__builtin_wasm_relaxed_min_f32x4` | -| `f32x4.max` | `__builtin_wasm_relaxed_max_f32x4` | -| `f64x2.min` | `__builtin_wasm_relaxed_min_f64x2` | -| `f64x2.max` | `__builtin_wasm_relaxed_max_f64x2` | -| `i16x8.relaxed_q15mulr_s` | `__builtin_wasm_relaxed_q15mulr_s_i16x8` | -| `i16x8.dot_i8x16_i7x16_s` | `__builtin_wasm_dot_i8x16_i7x16_s_i16x8` | -| `i32x4.dot_i8x16_i7x16_add_s` | `__builtin_wasm_dot_i8x16_i7x16_add_s_i32x4` | -| `f32x4.relaxed_dot_bf16x8_add_f32x4` | `__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4` | +| Instruction | LLVM | +|---------------------------------------|---------------------------------------------------| +| `i8x16.relaxed_swizzle` | `__builtin_wasm_relaxed_swizzle_i8x16` | +| `i32x4.relaxed_trunc_f32x4_s` | `__builtin_wasm_relaxed_trunc_s_i32x4_f32x4` | +| `i32x4.relaxed_trunc_f32x4_u` | `__builtin_wasm_relaxed_trunc_u_i32x4_f32x4` | +| `i32x4.relaxed_trunc_f64x2_s_zero` | `__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2` | +| `i32x4.relaxed_trunc_f64x2_u_zero` | `__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2` | +| `f32x4.relaxed_fma` | `__builtin_wasm_fma_f32x4` | +| `f32x4.relaxed_fnma` | `__builtin_wasm_fnma_f32x4` | +| `f64x2.relaxed_fma` | `__builtin_wasm_fma_f64x2` | +| `f64x2.relaxed_fnma` | `__builtin_wasm_fnma_f64x2` | +| `i8x16.relaxed_laneselect` | `__builtin_wasm_laneselect_i8x16` | +| `i16x8.relaxed_laneselect` | `__builtin_wasm_laneselect_i16x8` | +| `i32x4.relaxed_laneselect` | `__builtin_wasm_laneselect_i32x4` | +| `i64x2.relaxed_laneselect` | `__builtin_wasm_laneselect_i64x2` | +| `f32x4.relaxed_min` | `__builtin_wasm_relaxed_min_f32x4` | +| `f32x4.relaxed_max` | `__builtin_wasm_relaxed_max_f32x4` | +| `f64x2.relaxed_min` | `__builtin_wasm_relaxed_min_f64x2` | +| `f64x2.relaxed_max` | `__builtin_wasm_relaxed_max_f64x2` | +| `i16x8.relaxed_q15mulr_s` | `__builtin_wasm_relaxed_q15mulr_s_i16x8` | +| `i16x8.relaxed_dot_i8x16_i7x16_s` | `__builtin_wasm_dot_i8x16_i7x16_s_i16x8` | +| `i32x4.relaxed_dot_i8x16_i7x16_add_s` | `__builtin_wasm_dot_i8x16_i7x16_add_s_i32x4` | +| `f32x4.relaxed_dot_bf16x8_add_f32x4` | `__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4` | diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 27d45bb74..f11f990e6 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -316,30 +316,30 @@ where chosen to fit into the holes in the opcode space of SIMD proposal. Going forward, the opcodes for relaxed-simd specification will be the ones in the "opcode" column, and it will take some time for tools and engines to update. -| instruction | opcode | prototype opcode | -| ------------------------------------ | -------------- | ---------------- | -| `i8x16.relaxed_swizzle` | 0x100 | 0xa2 | -| `i32x4.relaxed_trunc_f32x4_s` | 0x101 | 0xa5 | -| `i32x4.relaxed_trunc_f32x4_u` | 0x102 | 0xa6 | -| `i32x4.relaxed_trunc_f64x2_s_zero` | 0x103 | 0xc5 | -| `i32x4.relaxed_trunc_f64x2_u_zero` | 0x104 | 0xc6 | -| `f32x4.relaxed_fma` | 0x105 | 0xaf | -| `f32x4.relaxed_fnma` | 0x106 | 0xb0 | -| `f64x2.relaxed_fma` | 0x107 | 0xcf | -| `f64x2.relaxed_fnma` | 0x108 | 0xd0 | -| `i8x16.relaxed_laneselect` | 0x109 | 0xb2 | -| `i16x8.relaxed_laneselect` | 0x10a | 0xb3 | -| `i32x4.relaxed_laneselect` | 0x10b | 0xd2 | -| `i64x2.relaxed_laneselect` | 0x10c | 0xd3 | -| `f32x4.relaxed_min` | 0x10d | 0xb4 | -| `f32x4.relaxed_max` | 0x10e | 0xe2 | -| `f64x2.relaxed_min` | 0x10f | 0xd4 | -| `f64x2.relaxed_max` | 0x110 | 0xee | -| `i16x8.relaxed_q15mulr_s` | 0x111 | unimplemented | -| `i16x8.dot_i8x16_i7x16_s` | 0x112 | unimplemented | -| `i32x4.dot_i8x16_i7x16_add_s` | 0x113 | unimplemented | -| `f32x4.relaxed_dot_bf16x8_add_f32x4` | 0x114 | unimplemented | -| Reserved | 0x115 - 0x12F | | +| instruction | opcode | prototype opcode | +| ------------------------------------- | -------------- | ---------------- | +| `i8x16.relaxed_swizzle` | 0x100 | 0xa2 | +| `i32x4.relaxed_trunc_f32x4_s` | 0x101 | 0xa5 | +| `i32x4.relaxed_trunc_f32x4_u` | 0x102 | 0xa6 | +| `i32x4.relaxed_trunc_f64x2_s_zero` | 0x103 | 0xc5 | +| `i32x4.relaxed_trunc_f64x2_u_zero` | 0x104 | 0xc6 | +| `f32x4.relaxed_fma` | 0x105 | 0xaf | +| `f32x4.relaxed_fnma` | 0x106 | 0xb0 | +| `f64x2.relaxed_fma` | 0x107 | 0xcf | +| `f64x2.relaxed_fnma` | 0x108 | 0xd0 | +| `i8x16.relaxed_laneselect` | 0x109 | 0xb2 | +| `i16x8.relaxed_laneselect` | 0x10a | 0xb3 | +| `i32x4.relaxed_laneselect` | 0x10b | 0xd2 | +| `i64x2.relaxed_laneselect` | 0x10c | 0xd3 | +| `f32x4.relaxed_min` | 0x10d | 0xb4 | +| `f32x4.relaxed_max` | 0x10e | 0xe2 | +| `f64x2.relaxed_min` | 0x10f | 0xd4 | +| `f64x2.relaxed_max` | 0x110 | 0xee | +| `i16x8.relaxed_q15mulr_s` | 0x111 | unimplemented | +| `i16x8.relaxed_dot_i8x16_i7x16_s` | 0x112 | unimplemented | +| `i32x4.relaxed_dot_i8x16_i7x16_add_s` | 0x113 | unimplemented | +| `f32x4.relaxed_dot_bf16x8_add_f32x4` | 0x114 | unimplemented | +| Reserved | 0x115 - 0x12F | | ## References From fda767d358d08f7248485e38b142cdb06e055070 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 24 Oct 2022 21:30:13 +0000 Subject: [PATCH 048/117] Update prototype opcodes --- proposals/relaxed-simd/Overview.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index f11f990e6..34d18cb69 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -335,10 +335,10 @@ forward, the opcodes for relaxed-simd specification will be the ones in the | `f32x4.relaxed_max` | 0x10e | 0xe2 | | `f64x2.relaxed_min` | 0x10f | 0xd4 | | `f64x2.relaxed_max` | 0x110 | 0xee | -| `i16x8.relaxed_q15mulr_s` | 0x111 | unimplemented | -| `i16x8.relaxed_dot_i8x16_i7x16_s` | 0x112 | unimplemented | -| `i32x4.relaxed_dot_i8x16_i7x16_add_s` | 0x113 | unimplemented | -| `f32x4.relaxed_dot_bf16x8_add_f32x4` | 0x114 | unimplemented | +| `i16x8.relaxed_q15mulr_s` | 0x111 | 0x111 | +| `i16x8.relaxed_dot_i8x16_i7x16_s` | 0x112 | 0x112 | +| `i32x4.relaxed_dot_i8x16_i7x16_add_s` | 0x113 | 0x113 | +| `f32x4.relaxed_dot_bf16x8_add_f32x4` | 0x114 | 0x114 | | Reserved | 0x115 - 0x12F | | ## References From 5b727ca3ede5cc565ea1a97eec793539cc5751a5 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 24 Oct 2022 21:50:21 +0000 Subject: [PATCH 049/117] Add link to phase 3 to overview --- proposals/relaxed-simd/Overview.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 34d18cb69..5a17a9ff0 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -351,4 +351,8 @@ forward, the opcodes for relaxed-simd specification will be the ones in the [slides](https://docs.google.com/presentation/d/1zyRqfgGU7HdoVw9QiKaVYifozbytPhNLHUW9jQjPzLk/edit?usp=sharing) and [meeting notes](https://github.com/WebAssembly/meetings/blob/main/main/2021/CG-11-09.md#update-on-relaxed-simd-fpenv-discussions-and-poll-for-phase-2-zhi-an-ng-15-min) +- Poll for phase 3 + [slides](https://docs.google.com/presentation/d/1ofBkgbW2AjYM4oayjTPTH3PCbyEn6W-q3GN67qSEigQ/edit?usp=sharing) + and [meeting + notes](https://github.com/WebAssembly/meetings/blob/main/main/2022/CG-04-12.md) - [SIMD proposal](https://github.com/WebAssembly/simd) From 484c78b97a83bdf696e5b4918ebb0a292ba321d6 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 25 Oct 2022 21:50:23 +0000 Subject: [PATCH 050/117] Rename relaxed_fma to relaxed_madd (fnma to nmadd) --- interpreter/binary/encode.ml | 8 +++---- interpreter/syntax/ast.ml | 2 +- interpreter/syntax/operators.ml | 8 +++---- interpreter/text/arrange.ml | 4 ++-- interpreter/text/lexer.mll | 8 +++---- .../relaxed-simd/ImplementationStatus.md | 16 ++++++------- proposals/relaxed-simd/Overview.md | 24 +++++++++---------- ..._fma_fnma.wast => relaxed_madd_nmadd.wast} | 22 ++++++++--------- 8 files changed, 46 insertions(+), 46 deletions(-) rename test/core/relaxed-simd/{relaxed_fma_fnma.wast => relaxed_madd_nmadd.wast} (79%) diff --git a/interpreter/binary/encode.ml b/interpreter/binary/encode.ml index b61fb29ec..2f2648336 100644 --- a/interpreter/binary/encode.ml +++ b/interpreter/binary/encode.ml @@ -647,10 +647,10 @@ struct | VecBinary (V128 _) -> error e.at "illegal binary vector instruction" - | VecTernary (V128 (F32x4 V128Op.RelaxedFma)) -> vecop 0x105l - | VecTernary (V128 (F32x4 V128Op.RelaxedFnma)) -> vecop 0x106l - | VecTernary (V128 (F64x2 V128Op.RelaxedFma)) -> vecop 0x107l - | VecTernary (V128 (F64x2 V128Op.RelaxedFnma)) -> vecop 0x108l + | VecTernary (V128 (F32x4 V128Op.RelaxedMadd)) -> vecop 0x105l + | VecTernary (V128 (F32x4 V128Op.RelaxedNmadd)) -> vecop 0x106l + | VecTernary (V128 (F64x2 V128Op.RelaxedMadd)) -> vecop 0x107l + | VecTernary (V128 (F64x2 V128Op.RelaxedNmadd)) -> vecop 0x108l | VecTernary (V128 (I8x16 V128Op.RelaxedLaneselect)) -> vecop 0x109l | VecTernary (V128 (I16x8 V128Op.RelaxedLaneselect)) -> vecop 0x10al | VecTernary (V128 (I32x4 V128Op.RelaxedLaneselect)) -> vecop 0x10bl diff --git a/interpreter/syntax/ast.ml b/interpreter/syntax/ast.ml index b2d7803e4..4f4f9d68b 100644 --- a/interpreter/syntax/ast.ml +++ b/interpreter/syntax/ast.ml @@ -65,7 +65,7 @@ struct type fbinop = Add | Sub | Mul | Div | Min | Max | Pmin | Pmax | RelaxedMin | RelaxedMax type iternop = RelaxedLaneselect | RelaxedDotAccum - type fternop = RelaxedFma | RelaxedFnma | RelaxedDotAccum + type fternop = RelaxedMadd | RelaxedNmadd | RelaxedDotAccum type irelop = Eq | Ne | LtS | LtU | LeS | LeU | GtS | GtU | GeS | GeU type frelop = Eq | Ne | Lt | Le | Gt | Ge type icvtop = ExtendLowS | ExtendLowU | ExtendHighS | ExtendHighU diff --git a/interpreter/syntax/operators.ml b/interpreter/syntax/operators.ml index 60f5a9d6e..33fe9f248 100644 --- a/interpreter/syntax/operators.ml +++ b/interpreter/syntax/operators.ml @@ -511,12 +511,12 @@ let i32x4_relaxed_trunc_f64x2_s_zero = VecConvert (V128 (I32x4 V128Op.RelaxedTru let i32x4_relaxed_trunc_f64x2_u_zero = VecConvert (V128 (I32x4 V128Op.RelaxedTruncUZeroF64x2)) let i32x4_relaxed_laneselect = VecTernary (V128 (I32x4 V128Op.RelaxedLaneselect)) let i64x2_relaxed_laneselect = VecTernary (V128 (I64x2 V128Op.RelaxedLaneselect)) -let f32x4_relaxed_fma = VecTernary (V128 (F32x4 V128Op.RelaxedFma)) -let f32x4_relaxed_fnma = VecTernary (V128 (F32x4 V128Op.RelaxedFnma)) +let f32x4_relaxed_madd = VecTernary (V128 (F32x4 V128Op.RelaxedMadd)) +let f32x4_relaxed_nmadd = VecTernary (V128 (F32x4 V128Op.RelaxedNmadd)) let f32x4_relaxed_min = VecBinary (V128 (F32x4 V128Op.RelaxedMin)) let f32x4_relaxed_max = VecBinary (V128 (F32x4 V128Op.RelaxedMax)) -let f64x2_relaxed_fma = VecTernary (V128 (F64x2 V128Op.RelaxedFma)) -let f64x2_relaxed_fnma = VecTernary (V128 (F64x2 V128Op.RelaxedFnma)) +let f64x2_relaxed_madd = VecTernary (V128 (F64x2 V128Op.RelaxedMadd)) +let f64x2_relaxed_nmadd = VecTernary (V128 (F64x2 V128Op.RelaxedNmadd)) let f64x2_relaxed_min = VecBinary (V128 (F64x2 V128Op.RelaxedMin)) let f64x2_relaxed_max = VecBinary (V128 (F64x2 V128Op.RelaxedMax)) let i16x8_dot_i8x16_i7x16_s = VecBinary (V128 (I16x8 V128Op.RelaxedDot)) diff --git a/interpreter/text/arrange.ml b/interpreter/text/arrange.ml index c3997d4c6..1f52eb446 100644 --- a/interpreter/text/arrange.ml +++ b/interpreter/text/arrange.ml @@ -280,8 +280,8 @@ struct | RelaxedMax -> "relaxed_max" let fternop xxxx (op : fternop) = match op with - | RelaxedFma -> "relaxed_fma" - | RelaxedFnma-> "relaxed_fnma" + | RelaxedMadd -> "relaxed_madd" + | RelaxedNmadd-> "relaxed_nmadd" | RelaxedDotAccum -> "relaxed_dot_bf" ^ half (half xxxx) ^ "_add_" ^ xxxx let irelop xxxx (op : irelop) = match op with diff --git a/interpreter/text/lexer.mll b/interpreter/text/lexer.mll index 82da94df9..e3e0e064a 100644 --- a/interpreter/text/lexer.mll +++ b/interpreter/text/lexer.mll @@ -658,10 +658,10 @@ rule token = parse | "i32x4.relaxed_trunc_f32x4_s" -> VEC_UNARY i32x4_relaxed_trunc_f32x4_s | "i32x4.relaxed_trunc_f64x2_u_zero" -> VEC_UNARY i32x4_relaxed_trunc_f64x2_u_zero | "i32x4.relaxed_trunc_f64x2_s_zero" -> VEC_UNARY i32x4_relaxed_trunc_f64x2_s_zero - | "f32x4.relaxed_fma" -> VEC_UNARY f32x4_relaxed_fma - | "f64x2.relaxed_fma" -> VEC_UNARY f64x2_relaxed_fma - | "f32x4.relaxed_fnma" -> VEC_UNARY f32x4_relaxed_fnma - | "f64x2.relaxed_fnma" -> VEC_UNARY f64x2_relaxed_fnma + | "f32x4.relaxed_madd" -> VEC_UNARY f32x4_relaxed_madd + | "f64x2.relaxed_madd" -> VEC_UNARY f64x2_relaxed_madd + | "f32x4.relaxed_nmadd" -> VEC_UNARY f32x4_relaxed_nmadd + | "f64x2.relaxed_nmadd" -> VEC_UNARY f64x2_relaxed_nmadd | "i8x16.relaxed_laneselect" -> VEC_TERNARY i8x16_relaxed_laneselect | "i16x8.relaxed_laneselect" -> VEC_TERNARY i16x8_relaxed_laneselect | "i32x4.relaxed_laneselect" -> VEC_TERNARY i32x4_relaxed_laneselect diff --git a/proposals/relaxed-simd/ImplementationStatus.md b/proposals/relaxed-simd/ImplementationStatus.md index 59bcf0bc0..14d4f6b0a 100644 --- a/proposals/relaxed-simd/ImplementationStatus.md +++ b/proposals/relaxed-simd/ImplementationStatus.md @@ -7,10 +7,10 @@ | `i32x4.relaxed_trunc_f32x4_u` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | | `i32x4.relaxed_trunc_f64x2_s_zero` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | | `i32x4.relaxed_trunc_f64x2_u_zero` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.relaxed_fma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f32x4.relaxed_fnma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.relaxed_fma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `f64x2.relaxed_fnma` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.relaxed_madd` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f32x4.relaxed_nmadd` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.relaxed_madd` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `f64x2.relaxed_nmadd` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | | `i8x16.relaxed_laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | | `i16x8.relaxed_laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | | `i32x4.relaxed_laneselect` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | @@ -40,10 +40,10 @@ | `i32x4.relaxed_trunc_f32x4_u` | `__builtin_wasm_relaxed_trunc_u_i32x4_f32x4` | | `i32x4.relaxed_trunc_f64x2_s_zero` | `__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2` | | `i32x4.relaxed_trunc_f64x2_u_zero` | `__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2` | -| `f32x4.relaxed_fma` | `__builtin_wasm_fma_f32x4` | -| `f32x4.relaxed_fnma` | `__builtin_wasm_fnma_f32x4` | -| `f64x2.relaxed_fma` | `__builtin_wasm_fma_f64x2` | -| `f64x2.relaxed_fnma` | `__builtin_wasm_fnma_f64x2` | +| `f32x4.relaxed_madd` | `__builtin_wasm_fma_f32x4` | +| `f32x4.relaxed_nmadd` | `__builtin_wasm_fnma_f32x4` | +| `f64x2.relaxed_madd` | `__builtin_wasm_fma_f64x2` | +| `f64x2.relaxed_nmadd` | `__builtin_wasm_fnma_f64x2` | | `i8x16.relaxed_laneselect` | `__builtin_wasm_laneselect_i8x16` | | `i16x8.relaxed_laneselect` | `__builtin_wasm_laneselect_i16x8` | | `i32x4.relaxed_laneselect` | `__builtin_wasm_laneselect_i32x4` | diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 5a17a9ff0..b1d17cec5 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -165,17 +165,17 @@ def relaxed_i32x4_trunc_f64x2_zero_u(a : f64x2) -> i32x4: ### Relaxed fused multiply-add and fused negative multiply-add -- `relaxed f32x4.fma` -- `relaxed f32x4.fnma` -- `relaxed f64x2.fma` -- `relaxed f64x2.fnma` +- `relaxed f32x4.madd` +- `relaxed f32x4.nmadd` +- `relaxed f64x2.madd` +- `relaxed f64x2.nmadd` All the instructions take 3 operands, `a`, `b`, `c`, perform `a * b + c` or `-(a * b) + c`: -- `relaxed f32x4.fma(a, b, c) = a * b + c` -- `relaxed f32x4.fnma(a, b, c) = -(a * b) + c` -- `relaxed f64x2.fma(a, b, c) = a * b + c` -- `relaxed f64x2.fnma(a, b, c) = -(a * b) + c` +- `relaxed f32x4.madd(a, b, c) = a * b + c` +- `relaxed f32x4.nmadd(a, b, c) = -(a * b) + c` +- `relaxed f64x2.madd(a, b, c) = a * b + c` +- `relaxed f64x2.nmadd(a, b, c) = -(a * b) + c` where: @@ -323,10 +323,10 @@ forward, the opcodes for relaxed-simd specification will be the ones in the | `i32x4.relaxed_trunc_f32x4_u` | 0x102 | 0xa6 | | `i32x4.relaxed_trunc_f64x2_s_zero` | 0x103 | 0xc5 | | `i32x4.relaxed_trunc_f64x2_u_zero` | 0x104 | 0xc6 | -| `f32x4.relaxed_fma` | 0x105 | 0xaf | -| `f32x4.relaxed_fnma` | 0x106 | 0xb0 | -| `f64x2.relaxed_fma` | 0x107 | 0xcf | -| `f64x2.relaxed_fnma` | 0x108 | 0xd0 | +| `f32x4.relaxed_madd` | 0x105 | 0xaf | +| `f32x4.relaxed_nmadd` | 0x106 | 0xb0 | +| `f64x2.relaxed_madd` | 0x107 | 0xcf | +| `f64x2.relaxed_nmadd` | 0x108 | 0xd0 | | `i8x16.relaxed_laneselect` | 0x109 | 0xb2 | | `i16x8.relaxed_laneselect` | 0x10a | 0xb3 | | `i32x4.relaxed_laneselect` | 0x10b | 0xd2 | diff --git a/test/core/relaxed-simd/relaxed_fma_fnma.wast b/test/core/relaxed-simd/relaxed_madd_nmadd.wast similarity index 79% rename from test/core/relaxed-simd/relaxed_fma_fnma.wast rename to test/core/relaxed-simd/relaxed_madd_nmadd.wast index 03666a02a..d212d53fc 100644 --- a/test/core/relaxed-simd/relaxed_fma_fnma.wast +++ b/test/core/relaxed-simd/relaxed_madd_nmadd.wast @@ -1,10 +1,10 @@ -;; Tests for f32x4.relaxed_fma, f32x4.relaxed_fnma, f64x2.relaxed_fma, and f64x2.relaxed_fnma. +;; Tests for f32x4.relaxed_madd, f32x4.relaxed_nmadd, f64x2.relaxed_madd, and f64x2.relaxed_nmadd. (module - (func (export "f32x4.relaxed_fma") (param v128 v128 v128) (result v128) (f32x4.relaxed_fma (local.get 0) (local.get 1) (local.get 2))) - (func (export "f32x4.relaxed_fnma") (param v128 v128 v128) (result v128) (f32x4.relaxed_fnma (local.get 0) (local.get 1) (local.get 2))) - (func (export "f64x2.relaxed_fnma") (param v128 v128 v128) (result v128) (f64x2.relaxed_fnma (local.get 0) (local.get 1) (local.get 2))) - (func (export "f64x2.relaxed_fma") (param v128 v128 v128) (result v128) (f64x2.relaxed_fma (local.get 0) (local.get 1) (local.get 2))) + (func (export "f32x4.relaxed_madd") (param v128 v128 v128) (result v128) (f32x4.relaxed_madd (local.get 0) (local.get 1) (local.get 2))) + (func (export "f32x4.relaxed_nmadd") (param v128 v128 v128) (result v128) (f32x4.relaxed_nmadd (local.get 0) (local.get 1) (local.get 2))) + (func (export "f64x2.relaxed_nmadd") (param v128 v128 v128) (result v128) (f64x2.relaxed_nmadd (local.get 0) (local.get 1) (local.get 2))) + (func (export "f64x2.relaxed_madd") (param v128 v128 v128) (result v128) (f64x2.relaxed_madd (local.get 0) (local.get 1) (local.get 2))) ) @@ -13,7 +13,7 @@ ;; FLT_MAX (if fma) ;; 0 (if no fma) ;; from https://www.vinc17.net/software/fma-tests.c -(assert_return (invoke "f32x4.relaxed_fma" +(assert_return (invoke "f32x4.relaxed_madd" (v128.const f32x4 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 ) (v128.const f32x4 2.0 2.0 2.0 2.0) (v128.const f32x4 -0x1.fffffep+127 -0x1.fffffep+127 -0x1.fffffep+127 -0x1.fffffep+127)) @@ -29,13 +29,13 @@ ;; x.y+z = 0 (2 roundings) ;; fma(x, y, z) = (0x1p-37) 2^-37 ;; from https://accurate-algorithms.readthedocs.io/en/latest/ch09appendix.html#test-system-information -(assert_return (invoke "f32x4.relaxed_fma" +(assert_return (invoke "f32x4.relaxed_madd" (v128.const f32x4 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0) (v128.const f32x4 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0) (v128.const f32x4 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0)) (either (v128.const f32x4 0x1p-37 0x1p-37 0x1p-37 0x1p-37) (v128.const f32x4 0 0 0 0))) -(assert_return (invoke "f32x4.relaxed_fnma" +(assert_return (invoke "f32x4.relaxed_nmadd" (v128.const f32x4 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0) (v128.const f32x4 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0) (v128.const f32x4 0x1.000204p+0 0x1.000204p+0 0x1.000204p+0 0x1.000204p+0)) @@ -48,7 +48,7 @@ ;; 0 (if no fma) ;; form https://www.vinc17.net/software/fma-tests.c ;; from https://www.vinc17.net/software/fma-tests.c -(assert_return (invoke "f64x2.relaxed_fma" +(assert_return (invoke "f64x2.relaxed_madd" (v128.const f64x2 0x1.fffffffffffffp+1023 0x1.fffffffffffffp+1023) (v128.const f64x2 2.0 2.0) (v128.const f64x2 -0x1.fffffffffffffp+1023 -0x1.fffffffffffffp+1023)) @@ -64,13 +64,13 @@ ;; x.y+z = 0 (2 roundings) ;; fma(x, y, z) = 0x1p-53 ;; from https://accurate-algorithms.readthedocs.io/en/latest/ch09appendix.html#test-system-information -(assert_return (invoke "f64x2.relaxed_fma" +(assert_return (invoke "f64x2.relaxed_madd" (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) (v128.const f64x2 0x1.000002p+0 0x1.000002p+0) (v128.const f64x2 -0x1.00000204p+0 -0x1.00000204p+0)) (either (v128.const f64x2 0x1p-53 0x1p-53) (v128.const f64x2 0 0))) -(assert_return (invoke "f64x2.relaxed_fnma" +(assert_return (invoke "f64x2.relaxed_nmadd" (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) (v128.const f64x2 0x1.000002p+0 0x1.000002p+0) (v128.const f64x2 0x1.00000204p+0 0x1.00000204p+0)) From c199565743b079b61c1229b66ae694e4f420fc98 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 6 Dec 2022 20:57:02 +0000 Subject: [PATCH 051/117] Remove bf16 from overview and implementation status --- .../relaxed-simd/ImplementationStatus.md | 2 -- proposals/relaxed-simd/Overview.md | 30 +------------------ 2 files changed, 1 insertion(+), 31 deletions(-) diff --git a/proposals/relaxed-simd/ImplementationStatus.md b/proposals/relaxed-simd/ImplementationStatus.md index 14d4f6b0a..e621fcf19 100644 --- a/proposals/relaxed-simd/ImplementationStatus.md +++ b/proposals/relaxed-simd/ImplementationStatus.md @@ -22,7 +22,6 @@ | `i16x8.relaxed_q15mulr_s` | -mrelaxed-simd | | | | `i16x8.relaxed_dot_i8x16_i7x16_s` | -mrelaxed-simd | | | | `i32x4.relaxed_dot_i8x16_i7x16_add_s` | -mrelaxed-simd | | | -| `f32x4.relaxed_dot_bf16x8_add_f32x4` | -mrelaxed-simd | | | [1] Tip of tree LLVM as of 2021-10-28 @@ -55,4 +54,3 @@ | `i16x8.relaxed_q15mulr_s` | `__builtin_wasm_relaxed_q15mulr_s_i16x8` | | `i16x8.relaxed_dot_i8x16_i7x16_s` | `__builtin_wasm_dot_i8x16_i7x16_s_i16x8` | | `i32x4.relaxed_dot_i8x16_i7x16_add_s` | `__builtin_wasm_dot_i8x16_i7x16_add_s_i32x4` | -| `f32x4.relaxed_dot_bf16x8_add_f32x4` | `__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4` | diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index b1d17cec5..4278cb930 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -279,33 +279,6 @@ i16x8_dot_i8x16_i7x16_s(a, b) = dot_product(signed=True, elements=2, a, b i32x4.dot_i8x16_i7x16_add_s(a, b, c) = dot_product(signed=True, elements=4, a, b, c) ``` -### Relaxed BFloat16 dot product - -- `f32x4.relaxed_dot_bf16x8_add_f32x4(a: v128, b: v128, c: v128) -> v128` - -BFloat16 is a 16-bit floating-point format that represents the IEEE FP32 numbers -truncated to the high 16 bits. This instruction computes a FP32 dot product of 2 -BFloat16 with accumulation into another FP32. - -```python -def bfloat16_dot_product(a, b, c): - for i in range(8): - y.fp32[i] = - y.fp32[i] + - cast(a.bf16[2*i]) * cast(b.bf16[2*i]) + - cast(a.bf16[2*i+1]) * cast(b.bf16[2*i+1]) -``` - -This instruction is implementation defined in the following ways: - -- evaluation order - - can compute dot product in one step, then accumulation in another, or - - accumulate first product in one step, then accumulate second product in - another step -- fusion, the steps described above can be both fused or both unfused -- the intermediate results can be Round-to-Nearest-Even or Round-to-Odd. - - ## Binary format All opcodes have the `0xfd` prefix (same as SIMD proposal), which are omitted in the table below. @@ -338,8 +311,7 @@ forward, the opcodes for relaxed-simd specification will be the ones in the | `i16x8.relaxed_q15mulr_s` | 0x111 | 0x111 | | `i16x8.relaxed_dot_i8x16_i7x16_s` | 0x112 | 0x112 | | `i32x4.relaxed_dot_i8x16_i7x16_add_s` | 0x113 | 0x113 | -| `f32x4.relaxed_dot_bf16x8_add_f32x4` | 0x114 | 0x114 | -| Reserved | 0x115 - 0x12F | | +| Reserved | 0x114 - 0x12F | | ## References From 22eb1c0db9b6957502c7ee322899fb10f26398ad Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 18:22:06 +0000 Subject: [PATCH 052/117] Remove bf16 dot For #117 --- interpreter/binary/encode.ml | 1 - interpreter/syntax/ast.ml | 2 +- interpreter/syntax/operators.ml | 1 - interpreter/text/arrange.ml | 1 - interpreter/text/lexer.mll | 1 - test/core/relaxed-simd/relaxed_dot_product.wast | 9 --------- 6 files changed, 1 insertion(+), 14 deletions(-) diff --git a/interpreter/binary/encode.ml b/interpreter/binary/encode.ml index 2f2648336..352338568 100644 --- a/interpreter/binary/encode.ml +++ b/interpreter/binary/encode.ml @@ -656,7 +656,6 @@ struct | VecTernary (V128 (I32x4 V128Op.RelaxedLaneselect)) -> vecop 0x10bl | VecTernary (V128 (I64x2 V128Op.RelaxedLaneselect)) -> vecop 0x10cl | VecTernary (V128 (I32x4 V128Op.RelaxedDotAccum)) -> vecop 0x113l - | VecTernary (V128 (F32x4 V128Op.RelaxedDotAccum)) -> vecop 0x114l | VecTernary (V128 _) -> error e.at "illegal ternary vector instruction" diff --git a/interpreter/syntax/ast.ml b/interpreter/syntax/ast.ml index 4f4f9d68b..30f567990 100644 --- a/interpreter/syntax/ast.ml +++ b/interpreter/syntax/ast.ml @@ -65,7 +65,7 @@ struct type fbinop = Add | Sub | Mul | Div | Min | Max | Pmin | Pmax | RelaxedMin | RelaxedMax type iternop = RelaxedLaneselect | RelaxedDotAccum - type fternop = RelaxedMadd | RelaxedNmadd | RelaxedDotAccum + type fternop = RelaxedMadd | RelaxedNmadd type irelop = Eq | Ne | LtS | LtU | LeS | LeU | GtS | GtU | GeS | GeU type frelop = Eq | Ne | Lt | Le | Gt | Ge type icvtop = ExtendLowS | ExtendLowU | ExtendHighS | ExtendHighU diff --git a/interpreter/syntax/operators.ml b/interpreter/syntax/operators.ml index 33fe9f248..66444caf9 100644 --- a/interpreter/syntax/operators.ml +++ b/interpreter/syntax/operators.ml @@ -521,4 +521,3 @@ let f64x2_relaxed_min = VecBinary (V128 (F64x2 V128Op.RelaxedMin)) let f64x2_relaxed_max = VecBinary (V128 (F64x2 V128Op.RelaxedMax)) let i16x8_dot_i8x16_i7x16_s = VecBinary (V128 (I16x8 V128Op.RelaxedDot)) let i32x4_dot_i8x16_i7x16_add_s = VecTernary (V128 (I32x4 V128Op.RelaxedDotAccum)) -let f32x4_relaxed_dot_bf16x8_add_f32x4 = VecTernary (V128 (F32x4 V128Op.RelaxedDotAccum)) diff --git a/interpreter/text/arrange.ml b/interpreter/text/arrange.ml index 1f52eb446..c6704e30c 100644 --- a/interpreter/text/arrange.ml +++ b/interpreter/text/arrange.ml @@ -282,7 +282,6 @@ struct let fternop xxxx (op : fternop) = match op with | RelaxedMadd -> "relaxed_madd" | RelaxedNmadd-> "relaxed_nmadd" - | RelaxedDotAccum -> "relaxed_dot_bf" ^ half (half xxxx) ^ "_add_" ^ xxxx let irelop xxxx (op : irelop) = match op with | Eq -> "eq" diff --git a/interpreter/text/lexer.mll b/interpreter/text/lexer.mll index e3e0e064a..a8899c0af 100644 --- a/interpreter/text/lexer.mll +++ b/interpreter/text/lexer.mll @@ -673,7 +673,6 @@ rule token = parse | "i16x8.relaxed_q15mulr_s" -> VEC_BINARY i16x8_relaxed_q15mulr_s | "i16x8.dot_i8x16_i7x16_s" -> VEC_BINARY i16x8_dot_i8x16_i7x16_s | "i32x4.dot_i8x16_i7x16_add_s" -> VEC_BINARY i32x4_dot_i8x16_i7x16_add_s - | "f32x4.relaxed_dot_bf16x8_add_f32x4" -> VEC_BINARY f32x4_relaxed_dot_bf16x8_add_f32x4 | "type" -> TYPE | "func" -> FUNC diff --git a/test/core/relaxed-simd/relaxed_dot_product.wast b/test/core/relaxed-simd/relaxed_dot_product.wast index 245b1db17..e84dcf96d 100644 --- a/test/core/relaxed-simd/relaxed_dot_product.wast +++ b/test/core/relaxed-simd/relaxed_dot_product.wast @@ -3,7 +3,6 @@ (module (func (export "i16x8.dot_i8x16_i7x16_s") (param v128 v128) (result v128) (i16x8.dot_i8x16_i7x16_s (local.get 0) (local.get 1))) (func (export "i32x4.dot_i8x16_i7x16_add_s") (param v128 v128 v128) (result v128) (i32x4.dot_i8x16_i7x16_add_s (local.get 0) (local.get 1) (local.get 2))) - (func (export "f32x4.relaxed_dot_bf16x8_add_f32x4") (param v128 v128 v128) (result v128) (f32x4.relaxed_dot_bf16x8_add_f32x4 (local.get 0) (local.get 1) (local.get 2))) ) ;; Simple values to ensure things are functional. @@ -33,11 +32,3 @@ (v128.const i32x4 1 2 3 4)) ;; intermediate result is [-65024, 64516, 0, 0] (v128.const f32x4 -65023 64518 3 4)) - -;; Simple values to ensure things are functional. -(assert_return (invoke "f32x4.relaxed_dot_bf16x8_add_f32x4" - (v128.const i16x8 0x0000 0x3f80 0x4000 0x4040 0x4080 0x40a0 0x40c0 0x40e0) ;; [0.0f, 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f] - (v128.const i16x8 0x0000 0x3f80 0x4000 0x4040 0x4080 0x40a0 0x40c0 0x40e0) - (v128.const f32x4 0 1 2 3)) - ;; intermediate result is [1, 13, 41, 85] - (v128.const f32x4 1 14 43 88)) From 5f39b1fd9472b1f8e91f6a1ef4b0ee10851e6227 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 18:26:02 +0000 Subject: [PATCH 053/117] Fix names of dot instructions For #117 --- interpreter/syntax/operators.ml | 4 ++-- interpreter/text/lexer.mll | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/interpreter/syntax/operators.ml b/interpreter/syntax/operators.ml index 66444caf9..7053793f2 100644 --- a/interpreter/syntax/operators.ml +++ b/interpreter/syntax/operators.ml @@ -519,5 +519,5 @@ let f64x2_relaxed_madd = VecTernary (V128 (F64x2 V128Op.RelaxedMadd)) let f64x2_relaxed_nmadd = VecTernary (V128 (F64x2 V128Op.RelaxedNmadd)) let f64x2_relaxed_min = VecBinary (V128 (F64x2 V128Op.RelaxedMin)) let f64x2_relaxed_max = VecBinary (V128 (F64x2 V128Op.RelaxedMax)) -let i16x8_dot_i8x16_i7x16_s = VecBinary (V128 (I16x8 V128Op.RelaxedDot)) -let i32x4_dot_i8x16_i7x16_add_s = VecTernary (V128 (I32x4 V128Op.RelaxedDotAccum)) +let i16x8_relaxed_dot_i8x16_i7x16_s = VecBinary (V128 (I16x8 V128Op.RelaxedDot)) +let i32x4_relaxed_dot_i8x16_i7x16_add_s = VecTernary (V128 (I32x4 V128Op.RelaxedDotAccum)) diff --git a/interpreter/text/lexer.mll b/interpreter/text/lexer.mll index a8899c0af..75e9cfea8 100644 --- a/interpreter/text/lexer.mll +++ b/interpreter/text/lexer.mll @@ -671,8 +671,8 @@ rule token = parse | "f32x4.relaxed_max" -> VEC_UNARY f32x4_relaxed_max | "f64x2.relaxed_max" -> VEC_UNARY f64x2_relaxed_max | "i16x8.relaxed_q15mulr_s" -> VEC_BINARY i16x8_relaxed_q15mulr_s - | "i16x8.dot_i8x16_i7x16_s" -> VEC_BINARY i16x8_dot_i8x16_i7x16_s - | "i32x4.dot_i8x16_i7x16_add_s" -> VEC_BINARY i32x4_dot_i8x16_i7x16_add_s + | "i16x8.relaxed_dot_i8x16_i7x16_s" -> VEC_BINARY i16x8_relaxed_dot_i8x16_i7x16_s + | "i32x4.relaxed_dot_i8x16_i7x16_add_s" -> VEC_BINARY i32x4_relaxed_dot_i8x16_i7x16_add_s | "type" -> TYPE | "func" -> FUNC From c7f2df122f3cf5778f792ea0d097a42c436886f6 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 19:23:03 +0000 Subject: [PATCH 054/117] Rename relaxed dot in tests --- test/core/relaxed-simd/relaxed_dot_product.wast | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/test/core/relaxed-simd/relaxed_dot_product.wast b/test/core/relaxed-simd/relaxed_dot_product.wast index e84dcf96d..80e9f4a26 100644 --- a/test/core/relaxed-simd/relaxed_dot_product.wast +++ b/test/core/relaxed-simd/relaxed_dot_product.wast @@ -1,24 +1,24 @@ ;; Tests for relaxed dot products. (module - (func (export "i16x8.dot_i8x16_i7x16_s") (param v128 v128) (result v128) (i16x8.dot_i8x16_i7x16_s (local.get 0) (local.get 1))) - (func (export "i32x4.dot_i8x16_i7x16_add_s") (param v128 v128 v128) (result v128) (i32x4.dot_i8x16_i7x16_add_s (local.get 0) (local.get 1) (local.get 2))) + (func (export "i16x8.relaxed_dot_i8x16_i7x16_s") (param v128 v128) (result v128) (i16x8.relaxed_dot_i8x16_i7x16_s (local.get 0) (local.get 1))) + (func (export "i32x4.relaxed_dot_i8x16_i7x16_add_s") (param v128 v128 v128) (result v128) (i32x4.relaxed_dot_i8x16_i7x16_add_s (local.get 0) (local.get 1) (local.get 2))) ) ;; Simple values to ensure things are functional. -(assert_return (invoke "i16x8.dot_i8x16_i7x16_s" +(assert_return (invoke "i16x8.relaxed_dot_i8x16_i7x16_s" (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) (v128.const i16x8 1 13 41 85 145 221 313 421)) ;; Test max and min i8 values; -(assert_return (invoke "i16x8.dot_i8x16_i7x16_s" +(assert_return (invoke "i16x8.relaxed_dot_i8x16_i7x16_s" (v128.const i8x16 -128 -128 127 127 0 0 0 0 0 0 0 0 0 0 0 0) (v128.const i8x16 127 127 127 127 0 0 0 0 0 0 0 0 0 0 0 0)) (v128.const i16x8 -32512 32258 0 0 0 0 0 0)) ;; Simple values to ensure things are functional. -(assert_return (invoke "i32x4.dot_i8x16_i7x16_add_s" +(assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s" (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (v128.const i32x4 0 1 2 3)) @@ -26,7 +26,7 @@ (v128.const f32x4 14 127 368 737)) ;; Test max and min i8 values; -(assert_return (invoke "i32x4.dot_i8x16_i7x16_add_s" +(assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s" (v128.const i8x16 -128 -128 -128 -128 127 127 127 127 0 0 0 0 0 0 0 0) (v128.const i8x16 127 127 127 127 127 127 127 127 0 0 0 0 0 0 0 0) (v128.const i32x4 1 2 3 4)) From d908cd438e8aae8ecf2c7e06022b630cab61db7c Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 21:10:09 +0000 Subject: [PATCH 055/117] Fix expected result type in relaxed dot product tests --- test/core/relaxed-simd/relaxed_dot_product.wast | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/core/relaxed-simd/relaxed_dot_product.wast b/test/core/relaxed-simd/relaxed_dot_product.wast index 80e9f4a26..e5e6e3041 100644 --- a/test/core/relaxed-simd/relaxed_dot_product.wast +++ b/test/core/relaxed-simd/relaxed_dot_product.wast @@ -23,7 +23,7 @@ (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) (v128.const i32x4 0 1 2 3)) ;; intermediate result is [14, 126, 366, 734] - (v128.const f32x4 14 127 368 737)) + (v128.const i32x4 14 127 368 737)) ;; Test max and min i8 values; (assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s" @@ -31,4 +31,4 @@ (v128.const i8x16 127 127 127 127 127 127 127 127 0 0 0 0 0 0 0 0) (v128.const i32x4 1 2 3 4)) ;; intermediate result is [-65024, 64516, 0, 0] - (v128.const f32x4 -65023 64518 3 4)) + (v128.const i32x4 -65023 64518 3 4)) From 961e0dbd52e09f0d8b1aa1f37bce83b2020d8472 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 15 Feb 2023 19:24:36 +0000 Subject: [PATCH 056/117] Check multiple calls to relaxed instructions return same results Fixes #110 --- .../relaxed-simd/i16x8_relaxed_q15mulr_s.wast | 13 +++ .../relaxed-simd/i32x4_relaxed_trunc.wast | 59 +++++++++++++ .../relaxed-simd/i8x16_relaxed_swizzle.wast | 19 +++++ .../relaxed-simd/relaxed_dot_product.wast | 25 ++++++ .../core/relaxed-simd/relaxed_laneselect.wast | 55 ++++++++++++- .../core/relaxed-simd/relaxed_madd_nmadd.wast | 82 +++++++++++++++++++ test/core/relaxed-simd/relaxed_min_max.wast | 81 +++++++++++++++++- 7 files changed, 330 insertions(+), 4 deletions(-) diff --git a/test/core/relaxed-simd/i16x8_relaxed_q15mulr_s.wast b/test/core/relaxed-simd/i16x8_relaxed_q15mulr_s.wast index 9dcb54de2..265d99160 100644 --- a/test/core/relaxed-simd/i16x8_relaxed_q15mulr_s.wast +++ b/test/core/relaxed-simd/i16x8_relaxed_q15mulr_s.wast @@ -1,6 +1,11 @@ ;; Tests for i16x8.relaxed_q15mulr_s. (module (func (export "i16x8.relaxed_q15mulr_s") (param v128 v128) (result v128) (i16x8.relaxed_q15mulr_s (local.get 0) (local.get 1))) + + (func (export "i16x8.relaxed_q15mulr_s_cmp") (param v128 v128) (result v128) + (i16x8.eq + (i16x8.relaxed_q15mulr_s (local.get 0) (local.get 1)) + (i16x8.relaxed_q15mulr_s (local.get 0) (local.get 1)))) ) ;; INT16_MIN = -32768 @@ -11,3 +16,11 @@ (either (v128.const i16x8 -32768 32767 32766 0 0 0 0 0) (v128.const i16x8 32767 32767 32766 0 0 0 0 0))) +;; Check that multiple calls to the relaxed instruction with same inputs returns same results. + +(assert_return (invoke "i16x8.relaxed_q15mulr_s_cmp" + (v128.const i16x8 -32768 -32767 32767 0 0 0 0 0) + (v128.const i16x8 -32768 -32768 32767 0 0 0 0 0)) + ;; overflows, return either INT16_MIN or INT16_MAX + (v128.const i16x8 -1 -1 -1 -1 -1 -1 -1 -1)) + diff --git a/test/core/relaxed-simd/i32x4_relaxed_trunc.wast b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast index c31195d04..2628bad4d 100644 --- a/test/core/relaxed-simd/i32x4_relaxed_trunc.wast +++ b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast @@ -5,6 +5,23 @@ (func (export "i32x4.relaxed_trunc_f32x4_u") (param v128) (result v128) (i32x4.relaxed_trunc_f32x4_u (local.get 0))) (func (export "i32x4.relaxed_trunc_f64x2_s_zero") (param v128) (result v128) (i32x4.relaxed_trunc_f64x2_s_zero (local.get 0))) (func (export "i32x4.relaxed_trunc_f64x2_u_zero") (param v128) (result v128) (i32x4.relaxed_trunc_f64x2_u_zero (local.get 0))) + + (func (export "i32x4.relaxed_trunc_f32x4_s_cmp") (param v128) (result v128) + (i32x4.eq + (i32x4.relaxed_trunc_f32x4_s (local.get 0)) + (i32x4.relaxed_trunc_f32x4_s (local.get 0)))) + (func (export "i32x4.relaxed_trunc_f32x4_u_cmp") (param v128) (result v128) + (i32x4.eq + (i32x4.relaxed_trunc_f32x4_u (local.get 0)) + (i32x4.relaxed_trunc_f32x4_u (local.get 0)))) + (func (export "i32x4.relaxed_trunc_f64x2_s_zero_cmp") (param v128) (result v128) + (i32x4.eq + (i32x4.relaxed_trunc_f64x2_s_zero (local.get 0)) + (i32x4.relaxed_trunc_f64x2_s_zero (local.get 0)))) + (func (export "i32x4.relaxed_trunc_f64x2_u_zero_cmp") (param v128) (result v128) + (i32x4.eq + (i32x4.relaxed_trunc_f64x2_u_zero (local.get 0)) + (i32x4.relaxed_trunc_f64x2_u_zero (local.get 0)))) ) (assert_return (invoke "i32x4.relaxed_trunc_f32x4_s" @@ -54,3 +71,45 @@ (v128.const f64x2 nan -nan)) (either (v128.const i32x4 0 0 0 0) (v128.const i32x4 0 0 0xffffffff 0xffffffff))) + +;; Check that multiple calls to the relaxed instruction with same inputs returns same results. + +(assert_return (invoke "i32x4.relaxed_trunc_f32x4_s_cmp" + ;; INT32_MIN INT32_MAX + (v128.const f32x4 -2147483648.0 -2147483904.0 2147483647.0 2147483904.0)) + ;; out of range -> saturate or INT32_MIN + (v128.const i32x4 -1 -1 -1 -1)) + +(assert_return (invoke "i32x4.relaxed_trunc_f32x4_s_cmp" + (v128.const f32x4 nan -nan nan:0x444444 -nan:0x444444)) + ;; nans -> 0 or INT32_MIN + (v128.const i32x4 -1 -1 -1 -1)) + +(assert_return (invoke "i32x4.relaxed_trunc_f32x4_u_cmp" + ;; UINT32_MIN UINT32_MIN-1 saturate or UINT32_MAX + (v128.const i32x4 -1 -1 -1 -1)) + +(assert_return (invoke "i32x4.relaxed_trunc_f32x4_u_cmp" + (v128.const f32x4 nan -nan nan:0x444444 -nan:0x444444)) + ;; nans -> 0 or UINT32_MAX + (v128.const i32x4 -1 -1 -1 -1)) + +(assert_return (invoke "i32x4.relaxed_trunc_f64x2_s_zero_cmp" + (v128.const f64x2 -2147483904.0 2147483904.0)) + ;; out of range -> saturate or INT32_MIN + (v128.const i32x4 -1 -1 -1 -1)) + +(assert_return (invoke "i32x4.relaxed_trunc_f64x2_s_zero_cmp" + (v128.const f64x2 nan -nan)) + (v128.const i32x4 -1 -1 -1 -1)) + +(assert_return (invoke "i32x4.relaxed_trunc_f64x2_u_zero_cmp" + (v128.const f64x2 -1.0 4294967296.0)) + ;; out of range -> saturate or UINT32_MAX + (v128.const i32x4 -1 -1 -1 -1)) + +(assert_return (invoke "i32x4.relaxed_trunc_f64x2_u_zero_cmp" + (v128.const f64x2 nan -nan)) + (v128.const i32x4 -1 -1 -1 -1)) diff --git a/test/core/relaxed-simd/i8x16_relaxed_swizzle.wast b/test/core/relaxed-simd/i8x16_relaxed_swizzle.wast index 22c11efb2..1b20668d3 100644 --- a/test/core/relaxed-simd/i8x16_relaxed_swizzle.wast +++ b/test/core/relaxed-simd/i8x16_relaxed_swizzle.wast @@ -2,6 +2,11 @@ (module (func (export "i8x16.relaxed_swizzle") (param v128 v128) (result v128) (i8x16.relaxed_swizzle (local.get 0) (local.get 1))) + + (func (export "i8x16.relaxed_swizzle_cmp") (param v128 v128) (result v128) + (i8x16.eq + (i8x16.relaxed_swizzle (local.get 0) (local.get 1)) + (i8x16.relaxed_swizzle (local.get 0) (local.get 1)))) ) (assert_return (invoke "i8x16.relaxed_swizzle" @@ -23,3 +28,17 @@ (v128.const i8x16 128 129 130 131 132 133 134 135 248 249 250 251 252 253 254 255)) (either (v128.const i8x16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15))) + +;; Check that multiple calls to the relaxed instruction with same inputs returns same results. + +;; out of range, returns 0 or modulo 15 if < 128 +(assert_return (invoke "i8x16.relaxed_swizzle_cmp" + (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) + (v128.const i8x16 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31)) + (v128.const i8x16 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1)) + +;; out of range, returns 0 if >= 128 +(assert_return (invoke "i8x16.relaxed_swizzle_cmp" + (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) + (v128.const i8x16 128 129 130 131 132 133 134 135 248 249 250 251 252 253 254 255)) + (v128.const i8x16 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1)) diff --git a/test/core/relaxed-simd/relaxed_dot_product.wast b/test/core/relaxed-simd/relaxed_dot_product.wast index e5e6e3041..ff8a90151 100644 --- a/test/core/relaxed-simd/relaxed_dot_product.wast +++ b/test/core/relaxed-simd/relaxed_dot_product.wast @@ -3,6 +3,15 @@ (module (func (export "i16x8.relaxed_dot_i8x16_i7x16_s") (param v128 v128) (result v128) (i16x8.relaxed_dot_i8x16_i7x16_s (local.get 0) (local.get 1))) (func (export "i32x4.relaxed_dot_i8x16_i7x16_add_s") (param v128 v128 v128) (result v128) (i32x4.relaxed_dot_i8x16_i7x16_add_s (local.get 0) (local.get 1) (local.get 2))) + + (func (export "i16x8.relaxed_dot_i8x16_i7x16_s_cmp") (param v128 v128) (result v128) + (i16x8.eq + (i16x8.relaxed_dot_i8x16_i7x16_s (local.get 0) (local.get 1)) + (i16x8.relaxed_dot_i8x16_i7x16_s (local.get 0) (local.get 1)))) + (func (export "i32x4.relaxed_dot_i8x16_i7x16_add_s_cmp") (param v128 v128 v128) (result v128) + (i16x8.eq + (i32x4.relaxed_dot_i8x16_i7x16_add_s (local.get 0) (local.get 1) (local.get 2)) + (i32x4.relaxed_dot_i8x16_i7x16_add_s (local.get 0) (local.get 1) (local.get 2)))) ) ;; Simple values to ensure things are functional. @@ -32,3 +41,19 @@ (v128.const i32x4 1 2 3 4)) ;; intermediate result is [-65024, 64516, 0, 0] (v128.const i32x4 -65023 64518 3 4)) + +;; Check that multiple calls to the relaxed instruction with same inputs returns same results. + +;; Test max and min i8 values; +(assert_return (invoke "i16x8.relaxed_dot_i8x16_i7x16_s_cmp" + (v128.const i8x16 -128 -128 127 127 0 0 0 0 0 0 0 0 0 0 0 0) + (v128.const i8x16 127 127 127 127 0 0 0 0 0 0 0 0 0 0 0 0)) + (v128.const i16x8 -1 -1 -1 -1 -1 -1 -1 -1)) + +;; Test max and min i8 values; +(assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s_cmp" + (v128.const i8x16 -128 -128 -128 -128 127 127 127 127 0 0 0 0 0 0 0 0) + (v128.const i8x16 127 127 127 127 127 127 127 127 0 0 0 0 0 0 0 0) + (v128.const i32x4 1 2 3 4)) + ;; intermediate result is [-65024, 64516, 0, 0] + (v128.const i32x4 -1 -1 -1 -1)) diff --git a/test/core/relaxed-simd/relaxed_laneselect.wast b/test/core/relaxed-simd/relaxed_laneselect.wast index e1a246fe3..4ea6eb818 100644 --- a/test/core/relaxed-simd/relaxed_laneselect.wast +++ b/test/core/relaxed-simd/relaxed_laneselect.wast @@ -2,9 +2,26 @@ (module (func (export "i8x16.relaxed_laneselect") (param v128 v128 v128) (result v128) (i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))) - (func (export "i16x8.relaxed_laneselect") (param v128 v128 v128) (result v128) (i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))) - (func (export "i32x4.relaxed_laneselect") (param v128 v128 v128) (result v128) (i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))) - (func (export "i64x2.relaxed_laneselect") (param v128 v128 v128) (result v128) (i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))) + (func (export "i16x8.relaxed_laneselect") (param v128 v128 v128) (result v128) (i16x8.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))) + (func (export "i32x4.relaxed_laneselect") (param v128 v128 v128) (result v128) (i32x4.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))) + (func (export "i64x2.relaxed_laneselect") (param v128 v128 v128) (result v128) (i64x2.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))) + + (func (export "i8x16.relaxed_laneselect_cmp") (param v128 v128 v128) (result v128) + (i8x16.eq + (i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2)) + (i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2)))) + (func (export "i16x8.relaxed_laneselect_cmp") (param v128 v128 v128) (result v128) + (i16x8.eq + (i16x8.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2)) + (i16x8.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2)))) + (func (export "i32x4.relaxed_laneselect_cmp") (param v128 v128 v128) (result v128) + (i32x4.eq + (i32x4.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2)) + (i32x4.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2)))) + (func (export "i64x2.relaxed_laneselect_cmp") (param v128 v128 v128) (result v128) + (i64x2.eq + (i64x2.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2)) + (i64x2.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2)))) ) (assert_return (invoke "i8x16.relaxed_laneselect" @@ -41,3 +58,35 @@ (v128.const i64x2 0xffffffff00000000 0x00000000ffffffff)) (either (v128.const i64x2 0x1234123456785678 0x5678567812341234) (v128.const i64x2 0x1234123412341234 0x5678567856785678))) + +;; Check that multiple calls to the relaxed instruction with same inputs returns same results. + +(assert_return (invoke "i8x16.relaxed_laneselect_cmp" + (v128.const i8x16 0 1 0x12 0x12 4 5 6 7 8 9 10 11 12 13 14 15) + (v128.const i8x16 16 17 0x34 0x34 20 21 22 23 24 25 26 27 28 29 30 31) + (v128.const i8x16 0xff 0 0xf0 0x0f 0 0 0 0 0 0 0 0 0 0 0 0)) + (v128.const i8x16 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1)) + +(assert_return (invoke "i16x8.relaxed_laneselect_cmp" + (v128.const i16x8 0 1 0x1234 0x1234 4 5 6 7) + (v128.const i16x8 8 9 0x5678 0x5678 12 13 14 15) + (v128.const i16x8 0xffff 0 0xff00 0x00ff 0 0 0 0)) + (v128.const i16x8 -1 -1 -1 -1 -1 -1 -1 -1)) + +(assert_return (invoke "i32x4.relaxed_laneselect_cmp" + (v128.const i32x4 0 1 0x12341234 0x12341234) + (v128.const i32x4 4 5 0x56785678 0x56785678) + (v128.const i32x4 0xffffffff 0 0xffff0000 0x0000ffff)) + (v128.const i32x4 -1 -1 -1 -1)) + +(assert_return (invoke "i64x2.relaxed_laneselect_cmp" + (v128.const i64x2 0 1) + (v128.const i64x2 2 3) + (v128.const i64x2 0xffffffffffffffff 0)) + (v128.const i64x2 -1 -1)) + +(assert_return (invoke "i64x2.relaxed_laneselect_cmp" + (v128.const i64x2 0x1234123412341234 0x1234123412341234) + (v128.const i64x2 0x5678567856785678 0x5678567856785678) + (v128.const i64x2 0xffffffff00000000 0x00000000ffffffff)) + (v128.const i64x2 -1 -1)) diff --git a/test/core/relaxed-simd/relaxed_madd_nmadd.wast b/test/core/relaxed-simd/relaxed_madd_nmadd.wast index d212d53fc..2339d3773 100644 --- a/test/core/relaxed-simd/relaxed_madd_nmadd.wast +++ b/test/core/relaxed-simd/relaxed_madd_nmadd.wast @@ -5,6 +5,23 @@ (func (export "f32x4.relaxed_nmadd") (param v128 v128 v128) (result v128) (f32x4.relaxed_nmadd (local.get 0) (local.get 1) (local.get 2))) (func (export "f64x2.relaxed_nmadd") (param v128 v128 v128) (result v128) (f64x2.relaxed_nmadd (local.get 0) (local.get 1) (local.get 2))) (func (export "f64x2.relaxed_madd") (param v128 v128 v128) (result v128) (f64x2.relaxed_madd (local.get 0) (local.get 1) (local.get 2))) + + (func (export "f32x4.relaxed_madd_cmp") (param v128 v128 v128) (result v128) + (f32x4.eq + (f32x4.relaxed_madd (local.get 0) (local.get 1) (local.get 2)) + (f32x4.relaxed_madd (local.get 0) (local.get 1) (local.get 2)))) + (func (export "f32x4.relaxed_nmadd_cmp") (param v128 v128 v128) (result v128) + (f32x4.eq + (f32x4.relaxed_nmadd (local.get 0) (local.get 1) (local.get 2)) + (f32x4.relaxed_nmadd (local.get 0) (local.get 1) (local.get 2)))) + (func (export "f64x2.relaxed_nmadd_cmp") (param v128 v128 v128) (result v128) + (f64x2.eq + (f64x2.relaxed_nmadd (local.get 0) (local.get 1) (local.get 2)) + (f64x2.relaxed_nmadd (local.get 0) (local.get 1) (local.get 2)))) + (func (export "f64x2.relaxed_madd_cmp") (param v128 v128 v128) (result v128) + (f64x2.eq + (f64x2.relaxed_madd (local.get 0) (local.get 1) (local.get 2)) + (f64x2.relaxed_madd (local.get 0) (local.get 1) (local.get 2)))) ) @@ -76,3 +93,68 @@ (v128.const f64x2 0x1.00000204p+0 0x1.00000204p+0)) (either (v128.const f64x2 0x1p-53 0x1p-53) (v128.const f64x2 0 0))) + +;; Check that multiple calls to the relaxed instruction with same inputs returns same results. + +;; FLT_MAX == 0x1.fffffep+127 +;; FLT_MAX * 2 - FLT_MAX == +;; FLT_MAX (if fma) +;; 0 (if no fma) +;; from https://www.vinc17.net/software/fma-tests.c +(assert_return (invoke "f32x4.relaxed_madd_cmp" + (v128.const f32x4 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 ) + (v128.const f32x4 2.0 2.0 2.0 2.0) + (v128.const f32x4 -0x1.fffffep+127 -0x1.fffffep+127 -0x1.fffffep+127 -0x1.fffffep+127)) + (v128.const i32x4 -1 -1 -1 -1)) + +;; Special values for float: +;; x = 0x1.000004p+0 (1 + 2^-22) +;; y = 0x1.0002p+0 (1 + 2^-15) +;; z = -(1.0 + 0x0.0002p+0 + 0x0.000004p+0) +;; = -0x1.000204p+0 +;; x.y = 1.0 + 0x0.0002p+0 + 0x0.000004p+0 + 0x1p-37 (round bit) +;; x.y+z = 0 (2 roundings) +;; fma(x, y, z) = (0x1p-37) 2^-37 +;; from https://accurate-algorithms.readthedocs.io/en/latest/ch09appendix.html#test-system-information +(assert_return (invoke "f32x4.relaxed_madd_cmp" + (v128.const f32x4 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0) + (v128.const f32x4 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0) + (v128.const f32x4 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0)) + (v128.const i32x4 -1 -1 -1 -1)) +(assert_return (invoke "f32x4.relaxed_nmadd_cmp" + (v128.const f32x4 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0) + (v128.const f32x4 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0) + (v128.const f32x4 0x1.000204p+0 0x1.000204p+0 0x1.000204p+0 0x1.000204p+0)) + (v128.const i32x4 -1 -1 -1 -1)) + +;; DBL_MAX = 0x1.fffffffffffffp+1023 +;; DLB_MAX * 2 - DLB_MAX == +;; DLB_MAX (if fma) +;; 0 (if no fma) +;; form https://www.vinc17.net/software/fma-tests.c +;; from https://www.vinc17.net/software/fma-tests.c +(assert_return (invoke "f64x2.relaxed_madd_cmp" + (v128.const f64x2 0x1.fffffffffffffp+1023 0x1.fffffffffffffp+1023) + (v128.const f64x2 2.0 2.0) + (v128.const f64x2 -0x1.fffffffffffffp+1023 -0x1.fffffffffffffp+1023)) + (v128.const i64x2 -1 -1)) + +;; Special values for double: +;; x = 0x1.00000004p+0 (1 + 2^-30) +;; y = 0x1.000002p+0 (1 + 2^-23) +;; z = -(1.0 + 0x0.000002p+0 + 0x0.00000004p+0) +;; = -0x1.00000204p+0 +;; x.y = 1.0 + 0x0.000002p+0 + 0x0.00000004p+0 + 0x1p-53 (round bit) +;; x.y+z = 0 (2 roundings) +;; fma(x, y, z) = 0x1p-53 +;; from https://accurate-algorithms.readthedocs.io/en/latest/ch09appendix.html#test-system-information +(assert_return (invoke "f64x2.relaxed_madd_cmp" + (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) + (v128.const f64x2 0x1.000002p+0 0x1.000002p+0) + (v128.const f64x2 -0x1.00000204p+0 -0x1.00000204p+0)) + (v128.const i64x2 -1 -1)) +(assert_return (invoke "f64x2.relaxed_nmadd_cmp" + (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) + (v128.const f64x2 0x1.000002p+0 0x1.000002p+0) + (v128.const f64x2 0x1.00000204p+0 0x1.00000204p+0)) + (v128.const i64x2 -1 -1)) diff --git a/test/core/relaxed-simd/relaxed_min_max.wast b/test/core/relaxed-simd/relaxed_min_max.wast index 5e49ac673..d8a04ba4d 100644 --- a/test/core/relaxed-simd/relaxed_min_max.wast +++ b/test/core/relaxed-simd/relaxed_min_max.wast @@ -3,8 +3,25 @@ (module (func (export "f32x4.relaxed_min") (param v128 v128) (result v128) (f32x4.relaxed_min (local.get 0) (local.get 1))) (func (export "f32x4.relaxed_max") (param v128 v128) (result v128) (f32x4.relaxed_max (local.get 0) (local.get 1))) - (func (export "f64x2.relaxed_max") (param v128 v128) (result v128) (f64x2.relaxed_max (local.get 0) (local.get 1))) (func (export "f64x2.relaxed_min") (param v128 v128) (result v128) (f64x2.relaxed_min (local.get 0) (local.get 1))) + (func (export "f64x2.relaxed_max") (param v128 v128) (result v128) (f64x2.relaxed_max (local.get 0) (local.get 1))) + + (func (export "f32x4.relaxed_min_cmp") (param v128 v128) (result v128) + (i32x4.eq + (f32x4.relaxed_min (local.get 0) (local.get 1)) + (f32x4.relaxed_min (local.get 0) (local.get 1)))) + (func (export "f32x4.relaxed_max_cmp") (param v128 v128) (result v128) + (i32x4.eq + (f32x4.relaxed_max (local.get 0) (local.get 1)) + (f32x4.relaxed_max (local.get 0) (local.get 1)))) + (func (export "f64x2.relaxed_min_cmp") (param v128 v128) (result v128) + (i64x2.eq + (f64x2.relaxed_min (local.get 0) (local.get 1)) + (f64x2.relaxed_min (local.get 0) (local.get 1)))) + (func (export "f64x2.relaxed_max_cmp") (param v128 v128) (result v128) + (i64x2.eq + (f64x2.relaxed_max (local.get 0) (local.get 1)) + (f64x2.relaxed_max (local.get 0) (local.get 1)))) ) (assert_return (invoke "f32x4.relaxed_min" @@ -102,3 +119,65 @@ (v128.const f64x2 +0.0 -0.0) (v128.const f64x2 +0.0 -0.0) (v128.const f64x2 +0.0 -0.0))) + +;; Check that multiple calls to the relaxed instruction with same inputs returns same results. + +(assert_return (invoke "f32x4.relaxed_min_cmp" + (v128.const f32x4 -nan nan 0 0) + (v128.const f32x4 0 0 -nan nan)) + (v128.const i32x4 -1 -1 -1 -1)) + +(assert_return (invoke "f32x4.relaxed_min_cmp" + (v128.const f32x4 +0.0 -0.0 +0.0 -0.0) + (v128.const f32x4 -0.0 +0.0 +0.0 -0.0)) + (v128.const i32x4 -1 -1 -1 -1)) + +(assert_return (invoke "f32x4.relaxed_max_cmp" + (v128.const f32x4 -nan nan 0 0) + (v128.const f32x4 0 0 -nan nan)) + (v128.const i32x4 -1 -1 -1 -1)) + +(assert_return (invoke "f32x4.relaxed_max_cmp" + (v128.const f32x4 +0.0 -0.0 +0.0 -0.0) + (v128.const f32x4 -0.0 +0.0 +0.0 -0.0)) + (v128.const i32x4 -1 -1 -1 -1)) + +(assert_return (invoke "f64x2.relaxed_min_cmp" + (v128.const f64x2 -nan nan) + (v128.const f64x2 0 0)) + (v128.const i64x2 -1 -1)) + +(assert_return (invoke "f64x2.relaxed_min_cmp" + (v128.const f64x2 0 0) + (v128.const f64x2 -nan nan)) + (v128.const i64x2 -1 -1)) + +(assert_return (invoke "f64x2.relaxed_min_cmp" + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 -0.0 +0.0)) + (v128.const i64x2 -1 -1)) + +(assert_return (invoke "f64x2.relaxed_min_cmp" + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 +0.0 -0.0)) + (v128.const i64x2 -1 -1)) + +(assert_return (invoke "f64x2.relaxed_max_cmp" + (v128.const f64x2 -nan nan) + (v128.const f64x2 0 0)) + (v128.const i64x2 -1 -1)) + +(assert_return (invoke "f64x2.relaxed_max_cmp" + (v128.const f64x2 0 0) + (v128.const f64x2 -nan nan)) + (v128.const i64x2 -1 -1)) + +(assert_return (invoke "f64x2.relaxed_max_cmp" + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 -0.0 +0.0)) + (v128.const i64x2 -1 -1)) + +(assert_return (invoke "f64x2.relaxed_max_cmp" + (v128.const f64x2 +0.0 -0.0) + (v128.const f64x2 +0.0 -0.0)) + (v128.const i64x2 -1 -1)) From e53cbc98cef179c8b027d58a80f82012d30549f8 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 15 Feb 2023 22:50:48 +0000 Subject: [PATCH 057/117] Add expected results for relaxed dot --- .../relaxed-simd/relaxed_dot_product.wast | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/test/core/relaxed-simd/relaxed_dot_product.wast b/test/core/relaxed-simd/relaxed_dot_product.wast index ff8a90151..720719ae5 100644 --- a/test/core/relaxed-simd/relaxed_dot_product.wast +++ b/test/core/relaxed-simd/relaxed_dot_product.wast @@ -26,6 +26,17 @@ (v128.const i8x16 127 127 127 127 0 0 0 0 0 0 0 0 0 0 0 0)) (v128.const i16x8 -32512 32258 0 0 0 0 0 0)) +;; signed * unsigned : -128 * 129 * 2 = -33,024 saturated to -32,768 +;; signed * signed : -128 * -127 * 2 = 32,512 +;; unsigned * unsigned : 128 * 129 * 2 = 33,024 +(assert_return (invoke "i16x8.relaxed_dot_i8x16_i7x16_s" + (v128.const i8x16 -128 -128 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (v128.const i8x16 -127 -127 0 0 0 0 0 0 0 0 0 0 0 0 0 0)) + (either + (v128.const i16x8 -32768 0 0 0 0 0 0 0) + (v128.const i16x8 32512 0 0 0 0 0 0 0) + (v128.const i16x8 33024 0 0 0 0 0 0 0))) + ;; Simple values to ensure things are functional. (assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s" (v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) @@ -42,6 +53,18 @@ ;; intermediate result is [-65024, 64516, 0, 0] (v128.const i32x4 -65023 64518 3 4)) +;; signed * unsigned : -128 * 129 * 4 = -66,048 (+ 1) +;; signed * signed : -128 * -127 * 4 = 65,024 (+ 1) +;; unsigned * unsigned : 128 * 129 * 2 = 66,048 (+ 1) +(assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s" + (v128.const i8x16 -128 -128 -128 -128 0 0 0 0 0 0 0 0 0 0 0 0) + (v128.const i8x16 -127 -127 -127 -127 0 0 0 0 0 0 0 0 0 0 0 0) + (v128.const i32x4 1 2 3 4)) + (either + (v128.const i32x4 -66047 2 3 4) + (v128.const i32x4 65025 2 3 4) + (v128.const i32x4 66049 2 3 4))) + ;; Check that multiple calls to the relaxed instruction with same inputs returns same results. ;; Test max and min i8 values; @@ -57,3 +80,20 @@ (v128.const i32x4 1 2 3 4)) ;; intermediate result is [-65024, 64516, 0, 0] (v128.const i32x4 -1 -1 -1 -1)) + +;; signed * unsigned : -128 * 129 * 2 = -33,024 saturated to -32,768 +;; signed * signed : -128 * -127 * 2 = 32,512 +;; unsigned * unsigned : 128 * 129 * 2 = 33,024 +(assert_return (invoke "i16x8.relaxed_dot_i8x16_i7x16_s_cmp" + (v128.const i8x16 -128 -128 0 0 0 0 0 0 0 0 0 0 0 0 0 0) + (v128.const i8x16 -127 -127 0 0 0 0 0 0 0 0 0 0 0 0 0 0)) + (v128.const i16x8 -1 -1 -1 -1 -1 -1 -1 -1)) + +;; signed * unsigned : -128 * 129 * 4 = -66,048 (+ 1) +;; signed * signed : -128 * -127 * 4 = 65,024 (+ 1) +;; unsigned * unsigned : 128 * 129 * 2 = 66,048 (+ 1) +(assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s_cmp" + (v128.const i8x16 -128 -128 -128 -128 0 0 0 0 0 0 0 0 0 0 0 0) + (v128.const i8x16 -127 -127 -127 -127 0 0 0 0 0 0 0 0 0 0 0 0) + (v128.const i32x4 1 2 3 4)) + (v128.const i32x4 -1 -1 -1 -1)) From d847308e99b86dfcc4dcea772b438aba12b9340b Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 16 Feb 2023 15:51:33 -0800 Subject: [PATCH 058/117] Fix relaxed nmadd tests (#124) nmadd(x, y, z) == nmadd(-x, y, z) the tests were doing -z instead. --- .../core/relaxed-simd/relaxed_madd_nmadd.wast | 46 +++++++++++++++---- 1 file changed, 38 insertions(+), 8 deletions(-) diff --git a/test/core/relaxed-simd/relaxed_madd_nmadd.wast b/test/core/relaxed-simd/relaxed_madd_nmadd.wast index 2339d3773..d3f76f810 100644 --- a/test/core/relaxed-simd/relaxed_madd_nmadd.wast +++ b/test/core/relaxed-simd/relaxed_madd_nmadd.wast @@ -52,10 +52,18 @@ (v128.const f32x4 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0)) (either (v128.const f32x4 0x1p-37 0x1p-37 0x1p-37 0x1p-37) (v128.const f32x4 0 0 0 0))) +;; nmadd tests with negated x, same answers are expected. (assert_return (invoke "f32x4.relaxed_nmadd" - (v128.const f32x4 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0) + (v128.const f32x4 -0x1.000004p+0 -0x1.000004p+0 -0x1.000004p+0 -0x1.000004p+0) (v128.const f32x4 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0) - (v128.const f32x4 0x1.000204p+0 0x1.000204p+0 0x1.000204p+0 0x1.000204p+0)) + (v128.const f32x4 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0)) + (either (v128.const f32x4 0x1p-37 0x1p-37 0x1p-37 0x1p-37) + (v128.const f32x4 0 0 0 0))) +;; nmadd tests with negated y, same answers are expected. +(assert_return (invoke "f32x4.relaxed_nmadd" + (v128.const f32x4 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0) + (v128.const f32x4 -0x1.0002p+0 -0x1.0002p+0 -0x1.0002p+0 -0x1.0002p+0) + (v128.const f32x4 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0)) (either (v128.const f32x4 0x1p-37 0x1p-37 0x1p-37 0x1p-37) (v128.const f32x4 0 0 0 0))) @@ -87,10 +95,18 @@ (v128.const f64x2 -0x1.00000204p+0 -0x1.00000204p+0)) (either (v128.const f64x2 0x1p-53 0x1p-53) (v128.const f64x2 0 0))) +;; nmadd tests with negated x, same answers are expected. (assert_return (invoke "f64x2.relaxed_nmadd" - (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) + (v128.const f64x2 -0x1.00000004p+0 -0x1.00000004p+0) (v128.const f64x2 0x1.000002p+0 0x1.000002p+0) - (v128.const f64x2 0x1.00000204p+0 0x1.00000204p+0)) + (v128.const f64x2 -0x1.00000204p+0 -0x1.00000204p+0)) + (either (v128.const f64x2 0x1p-53 0x1p-53) + (v128.const f64x2 0 0))) +;; nmadd tests with negated y, same answers are expected. +(assert_return (invoke "f64x2.relaxed_nmadd" + (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) + (v128.const f64x2 -0x1.000002p+0 -0x1.000002p+0) + (v128.const f64x2 -0x1.00000204p+0 -0x1.00000204p+0)) (either (v128.const f64x2 0x1p-53 0x1p-53) (v128.const f64x2 0 0))) @@ -121,10 +137,17 @@ (v128.const f32x4 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0) (v128.const f32x4 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0)) (v128.const i32x4 -1 -1 -1 -1)) +;; nmadd tests with negated x, same answers are expected. (assert_return (invoke "f32x4.relaxed_nmadd_cmp" - (v128.const f32x4 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0) + (v128.const f32x4 -0x1.000004p+0 -0x1.000004p+0 -0x1.000004p+0 -0x1.000004p+0) (v128.const f32x4 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0 0x1.0002p+0) - (v128.const f32x4 0x1.000204p+0 0x1.000204p+0 0x1.000204p+0 0x1.000204p+0)) + (v128.const f32x4 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0)) + (v128.const i32x4 -1 -1 -1 -1)) +;; nmadd tests with negated y, same answers are expected. +(assert_return (invoke "f32x4.relaxed_nmadd_cmp" + (v128.const f32x4 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0 0x1.000004p+0) + (v128.const f32x4 -0x1.0002p+0 -0x1.0002p+0 -0x1.0002p+0 -0x1.0002p+0) + (v128.const f32x4 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0 -0x1.000204p+0)) (v128.const i32x4 -1 -1 -1 -1)) ;; DBL_MAX = 0x1.fffffffffffffp+1023 @@ -153,8 +176,15 @@ (v128.const f64x2 0x1.000002p+0 0x1.000002p+0) (v128.const f64x2 -0x1.00000204p+0 -0x1.00000204p+0)) (v128.const i64x2 -1 -1)) +;; nmadd tests with negated x, same answers are expected. (assert_return (invoke "f64x2.relaxed_nmadd_cmp" - (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) + (v128.const f64x2 -0x1.00000004p+0 -0x1.00000004p+0) (v128.const f64x2 0x1.000002p+0 0x1.000002p+0) - (v128.const f64x2 0x1.00000204p+0 0x1.00000204p+0)) + (v128.const f64x2 -0x1.00000204p+0 -0x1.00000204p+0)) + (v128.const i64x2 -1 -1)) +;; nmadd tests with negated y, same answers are expected. +(assert_return (invoke "f64x2.relaxed_nmadd_cmp" + (v128.const f64x2 0x1.00000004p+0 0x1.00000004p+0) + (v128.const f64x2 -0x1.000002p+0 -0x1.000002p+0) + (v128.const f64x2 -0x1.00000204p+0 -0x1.00000204p+0)) (v128.const i64x2 -1 -1)) From f4435904c2ad6c912a56d22faba8fd5ff15bde12 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 22 Feb 2023 13:54:13 -0800 Subject: [PATCH 059/117] Fix relaxed trunc signed (#127) Fixes #126. --- proposals/relaxed-simd/Overview.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 4278cb930..61b18fbe0 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -114,12 +114,12 @@ def relaxed_i32x4_trunc_f32x4_s(a : f32x4) -> i32x4: result = [0, 0, 0, 0] for i in range(4): if isnan(a[i]): - result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MAX) + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MIN) r = truncate(a[i]) if r < INT32_MIN: - result[i] = IMPLEMENTATION_DEFINED_ONE_OF(INT32_MIN, INT32_MAX) + result[i] = INT32_MIN elif r > INT32_MAX - result[i] = INT32_MAX + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(INT32_MIN, INT32_MAX) else: result[i] = r @@ -140,12 +140,12 @@ def relaxed_i32x4_trunc_f64x2_zero_s(a : f64x2) -> i32x4: result = [0, 0, 0, 0] for i in range(2): if isnan(a[i]): - result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MAX) + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MIN) r = truncate(a[i]) if r < INT32_MIN: - result[i] = IMPLEMENTATION_DEFINED_ONE_OF(INT32_MIN, INT32_MAX) + result[i] = INT32_MIN elif r > INT32_MAX - result[i] = INT32_MAX + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(INT32_MIN, INT32_MAX) else: result[i] = r From 917bd5c842f704416c2515693e9820b9acafb49e Mon Sep 17 00:00:00 2001 From: Zhi An Ng Date: Mon, 27 Feb 2023 09:47:50 -0800 Subject: [PATCH 060/117] Update int dot tests to allow for saturation of intermediate 16-bit --- test/core/relaxed-simd/relaxed_dot_product.wast | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/test/core/relaxed-simd/relaxed_dot_product.wast b/test/core/relaxed-simd/relaxed_dot_product.wast index 720719ae5..a3f6e7caa 100644 --- a/test/core/relaxed-simd/relaxed_dot_product.wast +++ b/test/core/relaxed-simd/relaxed_dot_product.wast @@ -53,7 +53,10 @@ ;; intermediate result is [-65024, 64516, 0, 0] (v128.const i32x4 -65023 64518 3 4)) -;; signed * unsigned : -128 * 129 * 4 = -66,048 (+ 1) +;; signed * unsigned : -128 * 129 * 4 = -66,048 (+ 1) VPDPBUSD AVX2-VNNI or AVX512-VNNI +;; signed * unsigned with intermediate saturation : +;; (-128 * 129) + (-128 * 129) = -33024 saturated to -32768 (PMADDUBSW) +;; -32768 + -32768 = -65536 (+ 1) ;; signed * signed : -128 * -127 * 4 = 65,024 (+ 1) ;; unsigned * unsigned : 128 * 129 * 2 = 66,048 (+ 1) (assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s" @@ -62,6 +65,7 @@ (v128.const i32x4 1 2 3 4)) (either (v128.const i32x4 -66047 2 3 4) + (v128.const i32x4 -65536 2 3 4) (v128.const i32x4 65025 2 3 4) (v128.const i32x4 66049 2 3 4))) @@ -89,7 +93,10 @@ (v128.const i8x16 -127 -127 0 0 0 0 0 0 0 0 0 0 0 0 0 0)) (v128.const i16x8 -1 -1 -1 -1 -1 -1 -1 -1)) -;; signed * unsigned : -128 * 129 * 4 = -66,048 (+ 1) +;; signed * unsigned : -128 * 129 * 4 = -66,048 (+ 1) VPDPBUSD AVX2-VNNI or AVX512-VNNI +;; signed * unsigned with intermediate saturation : +;; (-128 * 129) + (-128 * 129) = -33024 saturated to -32768 (PMADDUBSW) +;; -32768 + -32768 = -65536 (+ 1) ;; signed * signed : -128 * -127 * 4 = 65,024 (+ 1) ;; unsigned * unsigned : 128 * 129 * 2 = 66,048 (+ 1) (assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s_cmp" From c423e6306becfbc7ad42976e1c536bd2b9bd9268 Mon Sep 17 00:00:00 2001 From: Zhi An Ng Date: Mon, 27 Feb 2023 09:57:30 -0800 Subject: [PATCH 061/117] Fix overview for int dot to allow saturation of 16-bit intermediates --- proposals/relaxed-simd/Overview.md | 41 +++++++++++++++++++++++------- 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 61b18fbe0..30b9a1733 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -261,22 +261,45 @@ When the second operand of the product has the high bit set in a lane, that lane's result is implementation defined. ```python -def dot_product(signed, elements, a, b, c): +def i16x8_dot_i8x16_i7x16_s(a, b): intermediate = [] result = [] for i in range(16): if (b[i] & 0x80): - lhs = as_signed(a[i]) if signed else a[i] - rhs = IMPLEMENTATION_DEFINED_ONE_OF(as_signed(b[i]), b[i]) + lhs = as_signed(a[i]) + rhs = IMPLEMENTATION_DEFINED_ONE_OF(as_signed(b[i]), as_unsigned(b[i])) intermediate[i] = lhs * rhs else: - intermediate[i] = (as_signed(a[i]) if signed else a[i]) * b[i] - for i in range(0, 16, elements): - result[i/elements] = sum(intermediate[i:i+elements]) - result[i/elements] += c[i/elements] if c else 0 + intermediate[i] = as_signed(a[i]) * b[i] + for i in range(0, 16, 2): + result[i/2] = IMPLEMENTATION_DEFINED_ONE_OF( + intermediate[i] + intermediate[i+1], + saturate(intermediate[i] + intermediate[i+1])) -i16x8_dot_i8x16_i7x16_s(a, b) = dot_product(signed=True, elements=2, a, b) -i32x4.dot_i8x16_i7x16_add_s(a, b, c) = dot_product(signed=True, elements=4, a, b, c) +def i32x4.dot_i8x16_i7x16_add_s(a, b, c): + intermediate = [] + tmp = [] + result = [] + for i in range(16): + if (b[i] & 0x80): + lhs = as_signed(a[i]) + rhs = IMPLEMENTATION_DEFINED_ONE_OF(as_signed(b[i]), as_unsigned(b[i])) + intermediate[i] = lhs * rhs + else: + intermediate[i] = as_signed(a[i]) * b[i] + + for i in range(0, 16, 2): + tmp[i/2] = IMPLEMENTATION_DEFINED_ONE_OF( + intermediate[i] + intermediate[i+1], + saturate(intermediate[i] + intermediate[i+1])) + + for i in range(0, 8, 2): + dst[i/4] = tmp[i] + tmp[i+1] + + for i in range(0, 4): + dst[i] += c[i] + +saturate(x) = min(INT16_MAX, max(INT16_MIN, x)) ``` ## Binary format From a9ad83903f4bcfeb9350ec052761c283dff2b3b4 Mon Sep 17 00:00:00 2001 From: Zhi An Ng Date: Mon, 27 Feb 2023 10:18:19 -0800 Subject: [PATCH 062/117] Fix typo in relaxed dot test --- test/core/relaxed-simd/relaxed_dot_product.wast | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/core/relaxed-simd/relaxed_dot_product.wast b/test/core/relaxed-simd/relaxed_dot_product.wast index a3f6e7caa..41dee0afc 100644 --- a/test/core/relaxed-simd/relaxed_dot_product.wast +++ b/test/core/relaxed-simd/relaxed_dot_product.wast @@ -65,7 +65,7 @@ (v128.const i32x4 1 2 3 4)) (either (v128.const i32x4 -66047 2 3 4) - (v128.const i32x4 -65536 2 3 4) + (v128.const i32x4 -65535 2 3 4) (v128.const i32x4 65025 2 3 4) (v128.const i32x4 66049 2 3 4))) From ae8a9f98d0125838973b36b01b9fa0aceb3c847d Mon Sep 17 00:00:00 2001 From: Alex Crichton Date: Mon, 27 Feb 2023 10:12:32 -0800 Subject: [PATCH 063/117] Fix some tests in `i32x4_relaxed_trunc.wast` This fixes some minor issues I encountered when running these tests. The first is a test for the `i32x4.relaxed_trunc_f32x4_s` instruction which asserted that `2147483647.0` (INT_MAX) would get translated to INT_MAX through the conversion. This float value, however, is not representable in `f32`. The two other closest integers that `f32` can represent are 2147483648 and 2147483520, so it's not actually possible to exercise a conversion from precisely INT_MAX to INT_MAX. Due to float parsing this meant that the value was getting rounded up to 2147483648 which exceeded INT_MAX which when using `cvttpd2dq` on x86 would cause INT_MIN to get returning, failing the test. I updated the test to pass something in-bounds (2 in this case) since the other edge cases are already tested. The other issue fixed in this commit is that many tests asserted that INT_MIN was a possible result but the representation of INT_MIN was missing a 0 in its hexadecimal representation, so zeros were appended. --- test/core/relaxed-simd/i32x4_relaxed_trunc.wast | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/test/core/relaxed-simd/i32x4_relaxed_trunc.wast b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast index 2628bad4d..6e6edd7bd 100644 --- a/test/core/relaxed-simd/i32x4_relaxed_trunc.wast +++ b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast @@ -25,17 +25,17 @@ ) (assert_return (invoke "i32x4.relaxed_trunc_f32x4_s" - ;; INT32_MIN INT32_MAX - (v128.const f32x4 -2147483648.0 -2147483904.0 2147483647.0 2147483904.0)) + ;; INT32_MIN INT32_MAX + (v128.const f32x4 -2147483648.0 -2147483904.0 2.0 2147483904.0)) ;; out of range -> saturate or INT32_MIN - (either (v128.const i32x4 -2147483648 -2147483648 2147483647 2147483647) - (v128.const i32x4 -2147483648 -2147483648 2147483647 -2147483648))) + (either (v128.const i32x4 -2147483648 -2147483648 2 2147483647) + (v128.const i32x4 -2147483648 -2147483648 2 -2147483648))) (assert_return (invoke "i32x4.relaxed_trunc_f32x4_s" (v128.const f32x4 nan -nan nan:0x444444 -nan:0x444444)) ;; nans -> 0 or INT32_MIN (either (v128.const i32x4 0 0 0 0) - (v128.const i32x4 0x8000000 0x8000000 0x8000000 0x8000000))) + (v128.const i32x4 0x80000000 0x80000000 0x80000000 0x80000000))) (assert_return (invoke "i32x4.relaxed_trunc_f32x4_u" ;; UINT32_MIN UINT32_MIN-1 Date: Mon, 27 Feb 2023 10:24:02 -0800 Subject: [PATCH 064/117] Add a note about the integer value of INT_MAX --- test/core/relaxed-simd/i32x4_relaxed_trunc.wast | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/test/core/relaxed-simd/i32x4_relaxed_trunc.wast b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast index 6e6edd7bd..889542c6a 100644 --- a/test/core/relaxed-simd/i32x4_relaxed_trunc.wast +++ b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast @@ -24,6 +24,14 @@ (i32x4.relaxed_trunc_f64x2_u_zero (local.get 0)))) ) +;; Test some edge cases around min/max to ensure that the instruction either +;; saturates correctly or returns INT_MIN. +;; +;; Note, though, that INT_MAX itself is not tested. The value for INT_MAX is +;; 2147483647 but that is not representable in a `f32` since it requires 31 bits +;; when a f32 has only 24 bits available. This means that the closest integers +;; to INT_MAX which can be represented are 2147483520 and 2147483648, meaning +;; that the INT_MAX test case cannot be tested. (assert_return (invoke "i32x4.relaxed_trunc_f32x4_s" ;; INT32_MIN INT32_MAX (v128.const f32x4 -2147483648.0 -2147483904.0 2.0 2147483904.0)) From 476802d1206661a29fe50dfc480450668cb91c43 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 27 Feb 2023 12:17:06 -0800 Subject: [PATCH 065/117] Implement relaxed instructions using the non-relaxed counterpart (#65) relaxed swizzle -> swizzle relaxed trunc -> trunc sat madd/nmadd -> fused multiply add/sub (2 roundings) relaxed laneselect -> bitselect relaxed min/max -> min/max i16x8 q15mulr -> i16x8.q15mulr with sat Co-authored-by: Andreas Rossberg --- interpreter/binary/decode.ml | 20 ++++++++++++++++++++ interpreter/exec/eval.ml | 4 ++++ interpreter/exec/eval_vec.ml | 26 ++++++++++++++++++++++++++ interpreter/exec/eval_vec.mli | 1 + interpreter/exec/fxx.ml | 7 +++++++ interpreter/exec/v128.ml | 30 ++++++++++++++++++++++++++++++ interpreter/exec/v128.mli | 4 ++++ interpreter/text/arrange.ml | 2 +- interpreter/util/lib.ml | 6 ++++++ interpreter/util/lib.mli | 1 + test/core/run.py | 6 +++++- 11 files changed, 105 insertions(+), 2 deletions(-) diff --git a/interpreter/binary/decode.ml b/interpreter/binary/decode.ml index fa3a0ef9e..004d0d315 100644 --- a/interpreter/binary/decode.ml +++ b/interpreter/binary/decode.ml @@ -772,6 +772,26 @@ let rec instr s = | 0xfdl -> i32x4_trunc_sat_f64x2_u_zero | 0xfel -> f64x2_convert_low_i32x4_s | 0xffl -> f64x2_convert_low_i32x4_u + | 0x100l -> i8x16_relaxed_swizzle + | 0x101l -> i32x4_relaxed_trunc_f32x4_s + | 0x102l -> i32x4_relaxed_trunc_f32x4_u + | 0x103l -> i32x4_relaxed_trunc_f64x2_s_zero + | 0x104l -> i32x4_relaxed_trunc_f64x2_u_zero + | 0x105l -> f32x4_relaxed_madd + | 0x106l -> f32x4_relaxed_nmadd + | 0x107l -> f64x2_relaxed_madd + | 0x108l -> f64x2_relaxed_nmadd + | 0x109l -> i8x16_relaxed_laneselect + | 0x10al -> i16x8_relaxed_laneselect + | 0x10bl -> i32x4_relaxed_laneselect + | 0x10cl -> i64x2_relaxed_laneselect + | 0x10dl -> f32x4_relaxed_min + | 0x10el -> f32x4_relaxed_max + | 0x10fl -> f64x2_relaxed_min + | 0x110l -> f64x2_relaxed_max + | 0x111l -> i16x8_relaxed_q15mulr_s + | 0x112l -> i16x8_relaxed_dot_i8x16_i7x16_s + | 0x113l -> i32x4_relaxed_dot_i8x16_i7x16_add_s | n -> illegal s pos (I32.to_int_u n) ) diff --git a/interpreter/exec/eval.ml b/interpreter/exec/eval.ml index 18ff7150d..7938eea14 100644 --- a/interpreter/exec/eval.ml +++ b/interpreter/exec/eval.ml @@ -538,6 +538,10 @@ let rec step (c : config) : config = (try Vec (Eval_vec.eval_binop binop n1 n2) :: vs', [] with exn -> vs', [Trapping (numeric_error e.at exn) @@ e.at]) + | VecTernary ternop, Vec v3 :: Vec v2 :: Vec v1 :: vs' -> + (try Vec (Eval_vec.eval_ternop ternop v1 v2 v3) :: vs', [] + with exn -> vs', [Trapping (numeric_error e.at exn) @@ e.at]) + | VecCompare relop, Vec n2 :: Vec n1 :: vs' -> (try Vec (Eval_vec.eval_relop relop n1 n2) :: vs', [] with exn -> vs', [Trapping (numeric_error e.at exn) @@ e.at]) diff --git a/interpreter/exec/eval_vec.ml b/interpreter/exec/eval_vec.ml index d4c6e9648..68596dc58 100644 --- a/interpreter/exec/eval_vec.ml +++ b/interpreter/exec/eval_vec.ml @@ -61,6 +61,7 @@ struct | I8x16 MaxS -> V128.I8x16.max_s | I8x16 MaxU -> V128.I8x16.max_u | I8x16 AvgrU -> V128.I8x16.avgr_u + | I8x16 RelaxedSwizzle -> V128.V8x16.swizzle | I16x8 NarrowS -> V128.I16x8_convert.narrow_s | I16x8 NarrowU -> V128.I16x8_convert.narrow_u | I16x8 Add -> V128.I16x8.add @@ -80,6 +81,8 @@ struct | I16x8 ExtMulLowU -> V128.I16x8_convert.extmul_low_u | I16x8 ExtMulHighU -> V128.I16x8_convert.extmul_high_u | I16x8 Q15MulRSatS -> V128.I16x8.q15mulr_sat_s + | I16x8 RelaxedQ15MulRS -> V128.I16x8.q15mulr_sat_s + | I16x8 RelaxedDot -> V128.I16x8_convert.dot_s | I32x4 Add -> V128.I32x4.add | I32x4 Sub -> V128.I32x4.sub | I32x4 MinS -> V128.I32x4.min_s @@ -107,6 +110,8 @@ struct | F32x4 Max -> V128.F32x4.max | F32x4 Pmin -> V128.F32x4.pmin | F32x4 Pmax -> V128.F32x4.pmax + | F32x4 RelaxedMin -> V128.F32x4.min + | F32x4 RelaxedMax -> V128.F32x4.max | F64x2 Add -> V128.F64x2.add | F64x2 Sub -> V128.F64x2.sub | F64x2 Mul -> V128.F64x2.mul @@ -115,9 +120,25 @@ struct | F64x2 Max -> V128.F64x2.max | F64x2 Pmin -> V128.F64x2.pmin | F64x2 Pmax -> V128.F64x2.pmax + | F64x2 RelaxedMin -> V128.F64x2.min + | F64x2 RelaxedMax -> V128.F64x2.max | _ -> assert false in fun v1 v2 -> to_vec (f (of_vec 1 v1) (of_vec 2 v2)) + let ternop (op : ternop) = + let f = match op with + | F32x4 RelaxedMadd -> V128.F32x4.fma + | F32x4 RelaxedNmadd -> V128.F32x4.fnma + | F64x2 RelaxedMadd -> V128.F64x2.fma + | F64x2 RelaxedNmadd -> V128.F64x2.fnma + | I8x16 RelaxedLaneselect -> V128.V1x128.bitselect + | I16x8 RelaxedLaneselect -> V128.V1x128.bitselect + | I32x4 RelaxedLaneselect -> V128.V1x128.bitselect + | I64x2 RelaxedLaneselect -> V128.V1x128.bitselect + | I32x4 RelaxedDotAccum -> V128.I32x4_convert.dot_s_accum + | _ -> assert false + in fun v1 v2 v3 -> to_vec (f (of_vec 1 v1) (of_vec 2 v2) (of_vec 3 v3)) + let relop (op : relop) = let f = match op with | I8x16 Eq -> V128.I8x16.eq @@ -187,6 +208,10 @@ struct | I32x4 TruncSatUF32x4 -> V128.I32x4_convert.trunc_sat_f32x4_u | I32x4 TruncSatSZeroF64x2 -> V128.I32x4_convert.trunc_sat_f64x2_s_zero | I32x4 TruncSatUZeroF64x2 -> V128.I32x4_convert.trunc_sat_f64x2_u_zero + | I32x4 RelaxedTruncSF32x4 -> V128.I32x4_convert.trunc_sat_f32x4_s + | I32x4 RelaxedTruncUF32x4 -> V128.I32x4_convert.trunc_sat_f32x4_u + | I32x4 RelaxedTruncSZeroF64x2 -> V128.I32x4_convert.trunc_sat_f64x2_s_zero + | I32x4 RelaxedTruncUZeroF64x2 -> V128.I32x4_convert.trunc_sat_f64x2_u_zero | I32x4 ExtAddPairwiseS -> V128.I32x4_convert.extadd_pairwise_s | I32x4 ExtAddPairwiseU -> V128.I32x4_convert.extadd_pairwise_u | I64x2 ExtendLowS -> V128.I64x2_convert.extend_low_s @@ -301,6 +326,7 @@ let op v128 = function let eval_testop = op V128Op.testop let eval_unop = op V128Op.unop let eval_binop = op V128Op.binop +let eval_ternop = op V128Op.ternop let eval_relop = op V128Op.relop let eval_cvtop = op V128Op.cvtop let eval_shiftop = op V128Op.shiftop diff --git a/interpreter/exec/eval_vec.mli b/interpreter/exec/eval_vec.mli index be54f20b7..bc68ed120 100644 --- a/interpreter/exec/eval_vec.mli +++ b/interpreter/exec/eval_vec.mli @@ -3,6 +3,7 @@ open Values val eval_testop : Ast.vec_testop -> vec -> bool val eval_unop : Ast.vec_unop -> vec -> vec val eval_binop : Ast.vec_binop -> vec -> vec -> vec +val eval_ternop : Ast.vec_ternop -> vec -> vec -> vec -> vec val eval_relop : Ast.vec_relop -> vec -> vec -> vec val eval_cvtop : Ast.vec_cvtop -> vec -> vec val eval_shiftop : Ast.vec_shiftop -> vec -> num -> vec diff --git a/interpreter/exec/fxx.ml b/interpreter/exec/fxx.ml index 2385d194d..e695e0673 100644 --- a/interpreter/exec/fxx.ml +++ b/interpreter/exec/fxx.ml @@ -43,6 +43,7 @@ sig val sub : t -> t -> t val mul : t -> t -> t val div : t -> t -> t + val fma : t -> t -> t -> t val sqrt : t -> t val min : t -> t -> t val max : t -> t -> t @@ -137,6 +138,12 @@ struct let sub x y = binary x (-.) y let mul x y = binary x ( *.) y let div x y = binary x (/.) y + let fma x y z = + let xf = to_float x in + let yf = to_float y in + let zf = to_float z in + let t = Float.fma xf yf zf in + if t = t then of_float t else determine_binary_nan x y let sqrt x = unary Stdlib.sqrt x diff --git a/interpreter/exec/v128.ml b/interpreter/exec/v128.ml index 550fd9bfa..8800347fd 100644 --- a/interpreter/exec/v128.ml +++ b/interpreter/exec/v128.ml @@ -191,6 +191,8 @@ sig val sub : t -> t -> t val mul : t -> t -> t val div : t -> t -> t + val fma : t -> t -> t -> t + val fnma : t -> t -> t -> t val min : t -> t -> t val max : t -> t -> t val pmin : t -> t -> t @@ -233,6 +235,9 @@ struct let sub = binop FXX.sub let mul = binop FXX.mul let div = binop FXX.div + let fma x y z = + of_lanes (Lib.List.map3 FXX.fma (to_lanes x) (to_lanes y) (to_lanes z)) + let fnma x y z = fma (unop FXX.neg x) y z let min = binop FXX.min let max = binop FXX.max let pmin = binop (fun x y -> if FXX.lt y x then y else x) @@ -378,6 +383,17 @@ struct I16x8.of_lanes (Lib.List.pairwise (extadd ext_s) (I8x16.to_lanes x)) let extadd_pairwise_u x = I16x8.of_lanes (Lib.List.pairwise (extadd ext_u) (I8x16.to_lanes x)) + + let dot_s x y = + let xs = I8x16.to_lanes x in + let ys = I8x16.to_lanes y in + let rec dot xs ys = + match xs, ys with + | x1::x2::xs', y1::y2::ys' -> + Int32.(add (mul x1 y1) (mul x2 y2)) :: dot xs' ys' + | [], [] -> [] + | _, _ -> assert false + in I16x8.of_lanes (dot xs ys) end module I32x4_convert = @@ -412,6 +428,20 @@ struct | _, _ -> assert false in I32x4.of_lanes (dot xs ys) + let dot_s_accum x y z = + let xs = I8x16.to_lanes x in + let ys = I8x16.to_lanes y in + let rec dot xs ys = + match xs, ys with + | x1::x2::x3::x4::xs', y1::y2::y3::y4::ys' -> + Int32.(add + (add (mul x1 y1) (mul x2 y2)) + (add (mul x3 y3) (mul x4 y4))) + :: dot xs' ys' + | [], [] -> [] + | _, _ -> assert false + in I32x4.add (I32x4.of_lanes (dot xs ys)) z + let extmul_low_s x y = I32x4.mul (extend_low_s x) (extend_low_s y) let extmul_high_s x y = I32x4.mul (extend_high_s x) (extend_high_s y) let extmul_low_u x y = I32x4.mul (extend_low_u x) (extend_low_u y) diff --git a/interpreter/exec/v128.mli b/interpreter/exec/v128.mli index f9535c158..e29477945 100644 --- a/interpreter/exec/v128.mli +++ b/interpreter/exec/v128.mli @@ -108,6 +108,8 @@ sig val sub : t -> t -> t val mul : t -> t -> t val div : t -> t -> t + val fma : t -> t -> t -> t + val fnma : t -> t -> t -> t val min : t -> t -> t val max : t -> t -> t val pmin : t -> t -> t @@ -163,6 +165,7 @@ sig val extmul_high_u : t -> t -> t val extadd_pairwise_s : t -> t val extadd_pairwise_u : t -> t + val dot_s : t -> t -> t end module I32x4_convert : @@ -176,6 +179,7 @@ sig val extend_low_u : t -> t val extend_high_u : t -> t val dot_s : t -> t -> t + val dot_s_accum : t -> t -> t -> t val extmul_low_s : t -> t -> t val extmul_high_s : t -> t -> t val extmul_low_u : t -> t -> t diff --git a/interpreter/text/arrange.ml b/interpreter/text/arrange.ml index c6704e30c..6e3b6dc3a 100644 --- a/interpreter/text/arrange.ml +++ b/interpreter/text/arrange.ml @@ -265,7 +265,7 @@ struct let iternop xxxx (op : iternop) = match op with | RelaxedLaneselect -> "relaxed_laneselect" - | RelaxedDotAccum -> "relaxed_dot_i" ^ half (half xxxx) ^ "_i" ^ without_high_bit (half (half xxxx)) ^ "add_s" + | RelaxedDotAccum -> "relaxed_dot_i" ^ half (half xxxx) ^ "_i" ^ without_high_bit (half (half xxxx)) ^ "_add_s" let fbinop xxxx (op : fbinop) = match op with | Add -> "add" diff --git a/interpreter/util/lib.ml b/interpreter/util/lib.ml index 76757eb72..3d7754f0b 100644 --- a/interpreter/util/lib.ml +++ b/interpreter/util/lib.ml @@ -105,6 +105,12 @@ struct | None -> map_filter f xs | Some y -> y :: map_filter f xs + let rec map3 f xs ys zs = + match xs, ys, zs with + | [], [], [] -> [] + | x::xs', y::ys', z::zs' -> f x y z :: map3 f xs' ys' zs' + | _ -> raise (Invalid_argument "Lib.List.map3") + let rec concat_map f = function | [] -> [] | x::xs -> f x @ concat_map f xs diff --git a/interpreter/util/lib.mli b/interpreter/util/lib.mli index b66b8b0e8..badc34bc5 100644 --- a/interpreter/util/lib.mli +++ b/interpreter/util/lib.mli @@ -24,6 +24,7 @@ sig val index_of : 'a -> 'a list -> int option val index_where : ('a -> bool) -> 'a list -> int option val map_filter : ('a -> 'b option) -> 'a list -> 'b list + val map3 : ('a -> 'b -> 'c -> 'd) -> 'a list -> 'b list -> 'c list -> 'd list val concat_map : ('a -> 'b list) -> 'a list -> 'b list val pairwise : ('a -> 'a -> 'b) -> 'a list -> 'b list end diff --git a/test/core/run.py b/test/core/run.py index 27c069436..d3d5229f9 100755 --- a/test/core/run.py +++ b/test/core/run.py @@ -26,12 +26,13 @@ main_test_files = glob.glob(os.path.join(inputDir, "*.wast")) # SIMD test files are in a subdirectory. simd_test_files = glob.glob(os.path.join(inputDir, "simd", "*.wast")) +relaxed_simd_test_files = glob.glob(os.path.join(inputDir, "relaxed-simd", "*.wast")) wasmCommand = arguments.wasm jsCommand = arguments.js generateJsOnly = arguments.generate_js_only outputDir = arguments.out -inputFiles = arguments.file if arguments.file else main_test_files + simd_test_files +inputFiles = arguments.file if arguments.file else main_test_files + simd_test_files + relaxed_simd_test_files if not os.path.exists(wasmCommand): sys.stderr.write("""\ @@ -107,6 +108,9 @@ def _runTestFile(self, inputPath): self._compareFile(wastPath, wast2Path) if jsCommand != None: + # TODO: node does not support relaxed-simd yet. + if 'node' in jsCommand and 'relaxed-simd' in jsPath: + return self._runCommand(('%s "%s"') % (jsCommand, jsPath), logPath) From 1bb54a7521db20e8890d9a11cbd8bd2f977b6277 Mon Sep 17 00:00:00 2001 From: Alex Crichton Date: Mon, 27 Feb 2023 11:50:57 -0800 Subject: [PATCH 066/117] Update overview spec of `laneselect` instructions Currently the overview indicates that if the mask lane is not zero, not all-ones, and the top bit is 0 then the output must be the `b` element. This doesn't match (what I believe is) the intended implementation on AArch64 using the `bsl` instruction which is the same as `v128.bitselect`. --- proposals/relaxed-simd/Overview.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 30b9a1733..1c627e7b8 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -203,7 +203,7 @@ def laneselect(a : v128, b : v128, m: v128, lanes : int): else topbit(mask) == 1: result[i] = IMPLEMENTATION_DEFINED_ONE_OF(bitselect(a[i], b[i], mask), a[i]) else: - result[i] = b[i] + result[i] = IMPLEMENTATION_DEFINED_ONE_OF(bitselect(a[i], b[i], mask), b[i]) return result ``` From 786f84dc1a2cc1fa096694d88c7bf18d6a249ff0 Mon Sep 17 00:00:00 2001 From: Andreas Rossberg Date: Mon, 12 Dec 2022 14:08:53 +0100 Subject: [PATCH 067/117] Spec profiles --- document/core/appendix/index.rst | 1 + document/core/appendix/profiles.rst | 129 ++++++++++++++++++++++++++++ document/core/exec/instructions.rst | 4 +- document/core/exec/numerics.rst | 17 ++-- document/core/util/macros.def | 9 ++ 5 files changed, 152 insertions(+), 8 deletions(-) create mode 100644 document/core/appendix/profiles.rst diff --git a/document/core/appendix/index.rst b/document/core/appendix/index.rst index c4173e955..bf66222e0 100644 --- a/document/core/appendix/index.rst +++ b/document/core/appendix/index.rst @@ -7,6 +7,7 @@ Appendix :maxdepth: 2 embedding + profiles implementation algorithm custom diff --git a/document/core/appendix/profiles.rst b/document/core/appendix/profiles.rst new file mode 100644 index 000000000..d0ebb0ccd --- /dev/null +++ b/document/core/appendix/profiles.rst @@ -0,0 +1,129 @@ +.. index:: ! profile, abstract syntax, validation, execution, binary format, text format +.. _profiles: + +Profiles +-------- + +To enable the use of WebAssembly in as many environments as possible, *profiles* specify coherent language subsets that fit constraints imposed by common classes of host environments. +A host platform can thereby decide to support the language only under a restricted profile, or even the intersection of multiple profiles. + + +Conventions +~~~~~~~~~~~ + +A profile modification is specified by decorating selected rules in the main body of this specification with a *profile annotation* that defines them as "conditional" on the choice of profile. + +For that purpose, every profile defines a *profile marker*, an alphanumeric short-hand like :math:`\profile{Abc}`. +A profile annotation of the form :math:`\exprofiles{\profile{Abc},\profile{Xyz}}` on a rule indicates that this rule is *excluded* for either of the profiles whose marker is :math:`\profile{Abc}` or :math:`\profile{Xyz}`. + +There are two ways of subsetting the language in a profile: + +* *Syntactic*, by *omitting* a feature, in which case certain constructs are removed from the syntax altogether. + +* *Semantic*, by *restricting* a feature, in which case certain constructs are still present but some behaviours are ruled out. + + +Syntax Annotations +.................. + +To omit a construct from a profile syntactically, respective productions in the grammar of the :ref:`abstract syntax ` are annotated with an associated profile marker. +This is defined to have the following implications: + +1. Any production in the :ref:`binary ` or :ref:`textual ` syntax that produces abstract syntax with a marked construct is omitted by extension. + +2. Any :ref:`validation ` or :ref:`execution ` rule that handles a marked construct is omitted by extension. + +The overall effect is that the respective construct is no longer part of the language under a respective profile. + +.. note:: + For example, a "busy" profile marked :math:`\profile{Busy}` could rule out the |NOP| instruction by marking the production for it in the abstract syntax as follows: + + .. math:: + \begin{array}{llcl} + \production{instruction} & \instr &::=& + \dots \\ + & \exprofiles{\profile{Busy}} &|& \NOP \\ + & &|& \UNREACHABLE \\ + \end{array} + + A rule may be annotated by multiple markers, which might be the case if a construct is in the intersection of multiple features. + + +Semantics Annotations +..................... + +To restrict certain behaviours in a profile, individual :ref:`validation ` or :ref:`reduction ` rules or auxiliary definitions are annotated with an associated marker. + +This has the simple consequence that the respective rule is no longer applicable under the given profile. + +.. note:: + For example, an "infinite" profile marked :math:`\profile{Inf}` could define that growing memory never fails: + + .. math:: + \begin{array}{llcl@{\qquad}l} + & S; F; (\I32.\CONST~n)~\MEMORYGROW &\stepto& S'; F; (\I32.\CONST~\X{sz}) + \\&&& + \begin{array}[t]{@{}r@{~}l@{}} + (\iff & F.\AMODULE.\MIMEMS[0] = a \\ + \wedge & \X{sz} = |S.\SMEMS[a].\MIDATA|/64\,\F{Ki} \\ + \wedge & S' = S \with \SMEMS[a] = \growmem(S.\SMEMS[a], n)) \\[1ex] + \end{array} + \\[1ex] + \exprofiles{\profile{Inf}} & S; F; (\I32.\CONST~n)~\MEMORYGROW &\stepto& S; F; (\I32.\CONST~\signed_{32}^{-1}(-1)) + \end{array} + + +Properties +.......... + +All profiles are defined such that the following properties are preserved: + +* All profiles represent syntactic and semantic subsets of the :ref:`full profile `, i.e., they do not *add* syntax or *alter* behaviour. + +* All profiles are mutually compatible, i.e., no two profiles subset semantic behaviour in inconsistent ways, and any intersection of profiles preserves the properties described here. + +* Profiles that restrict execution do not violate :ref:`soundness `, i.e., all :ref:`configurations ` valid under that profile still have well-defined execution behaviour. + +.. note:: + Tools are generally expected to handle and produce code for the full profile by default. + In particular, producers should not generate code that *depends* on specific profiles. Instead, all code should preserve correctness when executed under the full profile. + + Moreover, profiles should be considered static and fixed for a given platform or ecosystem. Runtime conditioning on the "current" profile should especially be avoided. + + + +Defined Profiles +~~~~~~~~~~~~~~~~ + +.. note:: + The number of defined profiles is expected to remain small in the future. Profiles are intended for broad and permanent use cases only. In particular, profiles are not intended for language versioning. + + +.. index:: full profile + single: profile; full +.. _profile-full: + +Full Profile (:math:`\textsc{Ful}`) +................................... + +The *full* profile contains the complete language and all possible behaviours. +It imposes no restrictions, i.e., all rules and definitions are active. +All other profiles define sub-languages of this profile. + + +.. index:: determinism, non-determinism, deterministic profile + single: profile; deterministic +.. _profile-deterministic: + +Deterministic Profile (:math:`\textsc{Det}`) +............................................ + +The *deterministic* profile excludes all rules marked :math:`\exprofiles{\PROFDET}`. +It defines a sub-language that does not exhibit any incidental non-deterministic behaviour: + +* All :ref:`NaN ` values :ref:`generated ` by :ref:`floating-point instructions ` are canonical and positive. + +Even under this profile, the |MEMORYGROW| and |TABLEGROW| instructions technically remain :ref:`non-deterministic `, in order to be able to indicate resource exhaustion. + +.. note:: + In future versions of WebAssembly, new non-deterministic behaviour may be added to the language, such that the deterministic profile will induce additional restrictions. diff --git a/document/core/exec/instructions.rst b/document/core/exec/instructions.rst index 3f82dce39..828ff5d91 100644 --- a/document/core/exec/instructions.rst +++ b/document/core/exec/instructions.rst @@ -7,7 +7,7 @@ Instructions WebAssembly computation is performed by executing individual :ref:`instructions `. -.. index:: numeric instruction, determinism, trap, NaN, value, value type +.. index:: numeric instruction, determinism, non-determinism, trap, NaN, value, value type pair: execution; instruction single: abstract syntax; instruction .. _exec-instr-numeric: @@ -1263,6 +1263,7 @@ Table Instructions \end{array} +.. index:: determinism, non-determinism .. _exec-table.grow: :math:`\TABLEGROW~x` @@ -2129,6 +2130,7 @@ Memory Instructions \end{array} +.. index:: determinism, non-determinism .. _exec-memory.grow: :math:`\MEMORYGROW` diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 71dfef6a9..868ca10d3 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -1,4 +1,4 @@ -.. index:: value, integer, floating-point, bit width, determinism, NaN +.. index:: value, integer, floating-point, bit width, determinism, non-determinism, NaN .. _exec-op-partial: .. _exec-numeric: @@ -1025,7 +1025,7 @@ where: \end{array} -.. index:: NaN +.. index:: NaN, determinism, non-determinism .. _aux-nans: NaN Propagation @@ -1038,14 +1038,17 @@ then its sign is non-deterministic and the :ref:`payload ` is co * Otherwise the payload is picked non-deterministically among all :ref:`arithmetic NaNs `; that is, its most significant bit is :math:`1` and all others are unspecified. +* In the :ref:`deterministic profile `, only positive canonical NaN outputs are produced. + This non-deterministic result is expressed by the following auxiliary function producing a set of allowed outputs from a set of inputs: .. math:: - \begin{array}{lll@{\qquad}l} - \nans_N\{z^\ast\} &=& \{ + \NAN(n), - \NAN(n) ~|~ n = \canon_N \} - & (\iff \forall \NAN(n) \in z^\ast,~ n = \canon_N) \\ - \nans_N\{z^\ast\} &=& \{ + \NAN(n), - \NAN(n) ~|~ n \geq \canon_N \} - & (\otherwise) \\ + \begin{array}{llcl@{\qquad}l} + & \nans_N\{z^\ast\} &=& \{ + \NAN(\canon_N) \} \\ + \exprofiles{\PROFDET} & \nans_N\{z^\ast\} &=& \{ + \NAN(n), - \NAN(n) ~|~ n = \canon_N \} + & (\iff \forall \,{\pm \NAN(n)} \in z^\ast,~ n = \canon_N) \\ + \exprofiles{\PROFDET} & \nans_N\{z^\ast\} &=& \{ + \NAN(n), - \NAN(n) ~|~ n \geq \canon_N \} + & (\iff \exists \,{\pm \NAN(n)} \in z^\ast,~ n \neq \canon_N) \\ \end{array} diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 3ab6d5480..16ee13d94 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -108,6 +108,15 @@ .. |bigcompose| mathdef:: \xref{syntax/conventions}{notation-compose}{\bigoplus} +.. Notation for Profiles + +.. |exprofiles#1| mathdef:: {[\mbox{\bf !}#1]} +.. |profile#1| mathdef:: {\textsc{#1}} + +.. |PROFFULL| mathdef:: \xref{appendix/profiles}{profile-full}{\profile{Ful}} +.. |PROFDET| mathdef:: \xref{appendix/profiles}{profile-deterministic}{\profile{Det}} + + .. Abstract Syntax .. --------------- From 16f6d1f00039e6dd4d8c6335bc2a2900bfa73754 Mon Sep 17 00:00:00 2001 From: Andreas Rossberg Date: Mon, 12 Dec 2022 16:54:06 +0100 Subject: [PATCH 068/117] Work around MathJax limitations --- document/core/appendix/profiles.rst | 20 ++++++++++---------- document/core/util/bikeshed_fixup.py | 2 ++ document/core/util/macros.def | 9 +++++---- 3 files changed, 17 insertions(+), 14 deletions(-) diff --git a/document/core/appendix/profiles.rst b/document/core/appendix/profiles.rst index d0ebb0ccd..8d360834d 100644 --- a/document/core/appendix/profiles.rst +++ b/document/core/appendix/profiles.rst @@ -13,8 +13,8 @@ Conventions A profile modification is specified by decorating selected rules in the main body of this specification with a *profile annotation* that defines them as "conditional" on the choice of profile. -For that purpose, every profile defines a *profile marker*, an alphanumeric short-hand like :math:`\profile{Abc}`. -A profile annotation of the form :math:`\exprofiles{\profile{Abc},\profile{Xyz}}` on a rule indicates that this rule is *excluded* for either of the profiles whose marker is :math:`\profile{Abc}` or :math:`\profile{Xyz}`. +For that purpose, every profile defines a *profile marker*, an alphanumeric short-hand like :math:`\profilename{ABC}`. +A profile annotation of the form :math:`\exprofiles{\profile{ABC}~\profile{XYZ}}` on a rule indicates that this rule is *excluded* for either of the profiles whose marker is :math:`\profilename{ABC}` or :math:`\profilename{XYZ}`. There are two ways of subsetting the language in a profile: @@ -36,13 +36,13 @@ This is defined to have the following implications: The overall effect is that the respective construct is no longer part of the language under a respective profile. .. note:: - For example, a "busy" profile marked :math:`\profile{Busy}` could rule out the |NOP| instruction by marking the production for it in the abstract syntax as follows: + For example, a "busy" profile marked :math:`\profilename{BUSY}` could rule out the |NOP| instruction by marking the production for it in the abstract syntax as follows: .. math:: \begin{array}{llcl} \production{instruction} & \instr &::=& \dots \\ - & \exprofiles{\profile{Busy}} &|& \NOP \\ + & \exprofiles{\profile{BUSY}} &|& \NOP \\ & &|& \UNREACHABLE \\ \end{array} @@ -57,7 +57,7 @@ To restrict certain behaviours in a profile, individual :ref:`validation This has the simple consequence that the respective rule is no longer applicable under the given profile. .. note:: - For example, an "infinite" profile marked :math:`\profile{Inf}` could define that growing memory never fails: + For example, an "infinite" profile marked :math:`\profilename{INF}` could define that growing memory never fails: .. math:: \begin{array}{llcl@{\qquad}l} @@ -69,7 +69,7 @@ This has the simple consequence that the respective rule is no longer applicable \wedge & S' = S \with \SMEMS[a] = \growmem(S.\SMEMS[a], n)) \\[1ex] \end{array} \\[1ex] - \exprofiles{\profile{Inf}} & S; F; (\I32.\CONST~n)~\MEMORYGROW &\stepto& S; F; (\I32.\CONST~\signed_{32}^{-1}(-1)) + \exprofiles{\profile{INF}} & S; F; (\I32.\CONST~n)~\MEMORYGROW &\stepto& S; F; (\I32.\CONST~\signed_{32}^{-1}(-1)) \end{array} @@ -103,8 +103,8 @@ Defined Profiles single: profile; full .. _profile-full: -Full Profile (:math:`\textsc{Ful}`) -................................... +Full Profile (:math:`{\small{\mathrm{FUL}}}`) +............................................. The *full* profile contains the complete language and all possible behaviours. It imposes no restrictions, i.e., all rules and definitions are active. @@ -115,8 +115,8 @@ All other profiles define sub-languages of this profile. single: profile; deterministic .. _profile-deterministic: -Deterministic Profile (:math:`\textsc{Det}`) -............................................ +Deterministic Profile (:math:`{\small{\mathrm{DET}}}`) +...................................................... The *deterministic* profile excludes all rules marked :math:`\exprofiles{\PROFDET}`. It defines a sub-language that does not exhibit any incidental non-deterministic behaviour: diff --git a/document/core/util/bikeshed_fixup.py b/document/core/util/bikeshed_fixup.py index dcd4fd070..6cfdaa2c7 100755 --- a/document/core/util/bikeshed_fixup.py +++ b/document/core/util/bikeshed_fixup.py @@ -22,10 +22,12 @@ def Main(): number = 1 for section in [ 'Embedding', + 'Profiles', 'Implementation Limitations', 'Validation Algorithm', 'Custom Sections', 'Soundness', + 'Changes', 'Index of Types', 'Index of Instructions', 'Index of Semantic Rules']: diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 16ee13d94..1a4dd1d20 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -110,11 +110,12 @@ .. Notation for Profiles -.. |exprofiles#1| mathdef:: {[\mbox{\bf !}#1]} -.. |profile#1| mathdef:: {\textsc{#1}} +.. |exprofiles#1| mathdef:: {^{\small{[!#1]}}} +.. |profilename#1| mathdef:: {\small{\mathrm{#1}}} +.. |profile| mathdef:: \mathrm -.. |PROFFULL| mathdef:: \xref{appendix/profiles}{profile-full}{\profile{Ful}} -.. |PROFDET| mathdef:: \xref{appendix/profiles}{profile-deterministic}{\profile{Det}} +.. |PROFFULL| mathdef:: \xref{appendix/profiles}{profile-full}{\profile{FUL}} +.. |PROFDET| mathdef:: \xref{appendix/profiles}{profile-deterministic}{\profile{DET}} From 3c78e14f880ac3c8641f63d2657f895c066e006c Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 12 Oct 2021 13:29:09 -0700 Subject: [PATCH 069/117] First pass at semantics --- document/core/exec/numerics.rst | 101 ++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 868ca10d3..f284f2da1 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -1970,3 +1970,104 @@ Conversions \begin{array}{lll@{\qquad}l} \narrowu_{M,N}(i) &=& \satu_N(\signed_M(i)) \end{array} + +.. _relaxed-ops: + +Relaxed operators +~~~~~~~~~~~~~~~~~ + +.. todo:: + This paragraph should go to the top of this document, but for ease of + reading, put it together with the description of all the relaxed operations + here. + +The result of *relaxed* operators are *host-dependent*, because the set of +possible results may depend on properties of the host environment (such as +hardware). Technically, each such operator produces a fixed-size *list of sets* +of allowed values. For each execution of the operator in the same environment, +only values from the set at the same position in the list are returned, i.e., +each environment globally chooses a fixed projection for each operator. + +.. note:: + Each operator can be thought of as a family of operations that is fixed to + one particular choice by the execution environment. The fixed operation + itself can still be non-deterministic or partial. + +.. todo:: + Below is a draft of concrete definitions for relaxed-simd operations. The + text description is an informal description of the instructions and are not + the final text. + +Relaxed Multiply Add (madd) and Relaxed Negative Multiply Add (nmadd) +allows for fused or unfused results. :math:`fma` is defined by |IEEE754|_ +(Section 5.4.1) as *fusedMultiplyAdd*. + +.. math:: + \begin{array}{@{}lcll} + relaxed\_madd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), fma_N(z_1, z_2, z_3) ] \\ + \\ + relaxed\_fnma_N(z_1, z_2, z_3) &=& relaxed\_madd_N(-z_1, z_2, z_3) \\ + \end{array} + +Relaxed swizzle lane is a helper for relaxed swizzle. Result is deterministic +if the signed interpretation of the index is less than 16 (including negative). +:math:`j` is a 8-bit int. + +.. math:: + \begin{array}{@{}lcll} + relaxed\_swizzle\_lane(i^n, j) &=& [ i[j], i[j] ] & (\iff j < 16) \\ + relaxed\_swizzle\_lane(i^n, j) &=& [ 0, 0 ] & (\iff \signed_8(j) < 0) \\ + relaxed\_swizzle\_lane(i^n, j) &=& [ 0, i[j \mod n] ] & (\otherwise) \\ + \\ + relaxed\_swizzle(a^n, s^n) &=& rsl_0 \dots rsl_{n-1} \\ + \qquad \where rsl_i &=& relaxed\_swizzle\_lane(a^n, s^n[i]) + \end{array} + +Relaxed truncate converts float to int, NaN and out of range values are +hardware dependent. + +.. math:: + \begin{array}{@{}lcll} + relaxed\_trunc^s_{M,N}(\pm \NAN(n)) &=& [ 0, -2^{N-1} ] \\ + relaxed\_trunc^s_{M,N}(\pm q) &=& \truncs_{M,N}(\pm q) & (\iff -2^{N-1} - 1 < \trunc(\pm q) < 2^{N-1}) \\ + relaxed\_trunc^s_{M,N}(\pm p) &=& [ \truncsats_{M,N}(\pm p), -2^{N-1} ] & (\otherwise) \\ + \\ + relaxed\_trunc^u_{M,N}(\pm \NAN(n)) &=& [ 0, 2^{N}-1 ] \\ + relaxed\_trunc^u_{M,N}(\pm q) &=& \truncu_{M,N}(\pm q) & (\iff -1 < \trunc(\pm q) < 2^N) \\ + relaxed\_trunc^u_{M,N}(\pm p) &=& [ \truncsatu_{M,N}(\pm p), 2^{N}-1 ] & (\otherwise) \\ + \end{array} + +Relaxed lane select is deterministic where all bits are set or unset in the +mask. Otherwise depending on hardware, either only the top bit is examined, or +all bits are examined (becomes a bitselect). + +.. math:: + \begin{array}{@{}lcll} + relaxed\_laneselect\_lane_N(i_1, i_2, 2^N-1) &=& [ i_1, i_1 ] \\ + relaxed\_laneselect\_lane_N(i_1, i_2, 0) &=& [ i_2, i_2 ] \\ + relaxed\_laneselect\_lane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_1 ] & (\iff \signed_N(i_3) < 0) \\ + relaxed\_laneselect\_lane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_2 ] & (\otherwise) \\ + \\ + relaxed\_laneselect_W(a^n, b^n, c^n) &=& rll_0 \dots rll_{n-1} \\ + \qquad \where rll_i &=& relaxed\_laneselect\_lane_W(a^n, b^n, c^n[i]) + \end{array} + +Relaxed min and max differs from min and max when inputs are NaNs or different +signs of 0. It allows for implementation to return the first or second input +when either input is a NaN. + +.. math:: + \begin{array}{@{}lcll} + relaxed\_min_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ + relaxed\_min_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ + relaxed\_min_N(\pm 0, \mp 0) &=& [ -0, \pm 0, \mp 0, -0 ] \\ + relaxed\_min_N(z_1, z_2) &=& \fmin_N(z_1, z_2) & (\otherwise) \\ + \end{array} + +.. math:: + \begin{array}{@{}lcll} + relaxed\_max_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ + relaxed\_max_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ + relaxed\_max_N(\pm 0, \mp 0) &=& [ +0, \pm 0, \mp 0, +0 ] \\ + relaxed\_max_N(z_1, z_2) &=& \fmax_N(z_1, z_2) & (\otherwise) \\ + \end{array} From 70008acdcb7766e3d29221311358b75e22abbc6e Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 17 Jan 2023 23:28:01 +0000 Subject: [PATCH 070/117] Changes atop profiles --- .../core/appendix/gen-index-instructions.py | 2 +- document/core/appendix/index-instructions.rst | 2 +- document/core/binary/instructions.rst | 25 +++++++++++ document/core/exec/instructions.rst | 45 ++++++++++++++++--- document/core/syntax/instructions.rst | 34 ++++++++++++-- document/core/text/instructions.rst | 25 +++++++++++ document/core/util/macros.def | 6 +++ document/core/valid/instructions.rst | 10 ++--- 8 files changed, 132 insertions(+), 17 deletions(-) diff --git a/document/core/appendix/gen-index-instructions.py b/document/core/appendix/gen-index-instructions.py index fffa2b329..b533ae3c9 100755 --- a/document/core/appendix/gen-index-instructions.py +++ b/document/core/appendix/gen-index-instructions.py @@ -421,7 +421,7 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\V128.\VANDNOT', r'\hex{FD}~~\hex{4F}', r'[\V128~\V128] \to [\V128]', r'valid-vvbinop', r'exec-vvbinop', r'op-iandnot'), Instruction(r'\V128.\VOR', r'\hex{FD}~~\hex{50}', r'[\V128~\V128] \to [\V128]', r'valid-vvbinop', r'exec-vvbinop', r'op-ior'), Instruction(r'\V128.\VXOR', r'\hex{FD}~~\hex{51}', r'[\V128~\V128] \to [\V128]', r'valid-vvbinop', r'exec-vvbinop', r'op-ixor'), - Instruction(r'\V128.\BITSELECT', r'\hex{FD}~~\hex{52}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vvternop', r'exec-vvternop', r'op-ibitselect'), + Instruction(r'\V128.\BITSELECT', r'\hex{FD}~~\hex{52}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-ibitselect'), Instruction(r'\V128.\ANYTRUE', r'\hex{FD}~~\hex{53}', r'[\V128] \to [\I32]', r'valid-vvtestop', r'exec-vvtestop'), Instruction(r'\V128.\LOAD\K{8\_lane}~\memarg~\laneidx', r'\hex{FD}~~\hex{54}', r'[\I32~\V128] \to [\V128]', r'valid-load-lane', r'exec-load-lane'), Instruction(r'\V128.\LOAD\K{16\_lane}~\memarg~\laneidx', r'\hex{FD}~~\hex{55}', r'[\I32~\V128] \to [\V128]', r'valid-load-lane', r'exec-load-lane'), diff --git a/document/core/appendix/index-instructions.rst b/document/core/appendix/index-instructions.rst index 977c21fb3..8ebfc2b82 100644 --- a/document/core/appendix/index-instructions.rst +++ b/document/core/appendix/index-instructions.rst @@ -361,7 +361,7 @@ Instruction Binary Opcode :math:`\V128.\VANDNOT` :math:`\hex{FD}~~\hex{4F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\V128.\VOR` :math:`\hex{FD}~~\hex{50}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\V128.\VXOR` :math:`\hex{FD}~~\hex{51}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\BITSELECT` :math:`\hex{FD}~~\hex{52}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\BITSELECT` :math:`\hex{FD}~~\hex{52}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\V128.\ANYTRUE` :math:`\hex{FD}~~\hex{53}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` :math:`\V128.\LOAD\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{54}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\V128.\LOAD\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{55}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` diff --git a/document/core/binary/instructions.rst b/document/core/binary/instructions.rst index e13a03236..f6ea313e8 100644 --- a/document/core/binary/instructions.rst +++ b/document/core/binary/instructions.rst @@ -838,6 +838,31 @@ All other vector instructions are plain opcodes without any immediates. \hex{FD}~~95{:}\Bu32 &\Rightarrow& \F64X2.\VPROMOTE\K{\_low\_f32x4}\\ \end{array} +.. math:: + \begin{array}{llclll} + \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|& + \hex{FD}~~256{:}\Bu32 &\Rightarrow& \I16X8.\RSWIZZLE \\ &&|& + \hex{FD}~~257{:}\Bu32 &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_s} \\ &&|& + \hex{FD}~~258{:}\Bu32 &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_u} \\ &&|& + \hex{FD}~~259{:}\Bu32 &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_s\_zero} \\ &&|& + \hex{FD}~~260{:}\Bu32 &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_u\_zero} \\ &&|& + \hex{FD}~~261{:}\Bu32 &\Rightarrow& \F32X4.\K{relaxed\_madd} \\ &&|& + \hex{FD}~~262{:}\Bu32 &\Rightarrow& \F32X4.\K{relaxed\_nmadd} \\ &&|& + \hex{FD}~~263{:}\Bu32 &\Rightarrow& \F64X2.\K{relaxed\_madd} \\ &&|& + \hex{FD}~~264{:}\Bu32 &\Rightarrow& \F64X2.\K{relaxed\_nmadd} \\ &&|& + \hex{FD}~~265{:}\Bu32 &\Rightarrow& \I8X16.\K{relaxed\_laneselect} \\ &&|& + \hex{FD}~~266{:}\Bu32 &\Rightarrow& \I16X8.\K{relaxed\_laneselect} \\ &&|& + \hex{FD}~~267{:}\Bu32 &\Rightarrow& \I32X4.\K{relaxed\_laneselect} \\ &&|& + \hex{FD}~~268{:}\Bu32 &\Rightarrow& \I64X2.\K{relaxed\_laneselect} \\ &&|& + \hex{FD}~~269{:}\Bu32 &\Rightarrow& \F32X4.\K{relaxed\_min} \\ &&|& + \hex{FD}~~270{:}\Bu32 &\Rightarrow& \F32X4.\K{relaxed\_max} \\ &&|& + \hex{FD}~~271{:}\Bu32 &\Rightarrow& \F64X2.\K{relaxed\_min} \\ &&|& + \hex{FD}~~272{:}\Bu32 &\Rightarrow& \F64X2.\K{relaxed\_max} \\ &&|& + \hex{FD}~~273{:}\Bu32 &\Rightarrow& \I16X8.\RQ15MULRS \\ &&|& + \hex{FD}~~274{:}\Bu32 &\Rightarrow& \I16X8.\K{relaxed\_dot\_i8x16\_i7x16\_s} \\ &&|& + \hex{FD}~~275{:}\Bu32 &\Rightarrow& \I16X8.\K{relaxed\_dot\_i8x16\_i7x16\_add\_s} \\ + \end{array} + .. index:: expression pair: binary format; expression diff --git a/document/core/exec/instructions.rst b/document/core/exec/instructions.rst index 828ff5d91..c89774273 100644 --- a/document/core/exec/instructions.rst +++ b/document/core/exec/instructions.rst @@ -325,12 +325,12 @@ Most vector instructions are defined in terms of generic numeric operators appli \end{array} -.. _exec-vvternop: +.. _exec-vternop: -:math:`\V128\K{.}\vvternop` +:math:`\V128\K{.}\vternop` ........................... -1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. +1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. 2. Pop the value :math:`\V128.\VCONST~c_3` from the stack. @@ -338,14 +338,14 @@ Most vector instructions are defined in terms of generic numeric operators appli 4. Pop the value :math:`\V128.\VCONST~c_1` from the stack. -5. Let :math:`c` be the result of computing :math:`\vvternop_{\I128}(c_1, c_2, c_3)`. +5. Let :math:`c` be the result of computing :math:`\vternop{\I128}(c_1, c_2, c_3)`. 6. Push the value :math:`\V128.\VCONST~c` to the stack. .. math:: \begin{array}{lcl@{\qquad}l} - (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\V128\K{.}\vvternop &\stepto& (\V128\K{.}\VCONST~c) - & (\iff c = \vvternop_{\I128}(c_1, c_2, c_3)) \\ + (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\V128\K{.}\vternop &\stepto& (\V128\K{.}\VCONST~c) + & (\iff c = \vternop{\I128}(c_1, c_2, c_3)) \\ \end{array} @@ -405,6 +405,39 @@ Most vector instructions are defined in terms of generic numeric operators appli \end{array} +.. _exec-vec-relaxed-swizzle: + +:math:`\K{i8x16.}\RSWIZZLE` +........................... + +1. Assert: due to :ref:`validation `, two values of :ref:`value type ` |V128| are on the top of the stack. + +2. Pop the value :math:`\V128.\VCONST~c_2` from the stack. + +3. Let :math:`i^\ast` be the sequence :math:`\lanes_{i8x16}(c_2)`. + +4. Pop the value :math:`\V128.\VCONST~c_1` from the stack. + +5. Let :math:`j^\ast` be the sequence :math:`\lanes_{i8x16}(c_1)`. + +6. Let :math:`c'` be the result of computing :math:`\RSWIZZLE(j^\ast, i^\ast)`. + +7. Push the value :math:`\V128.\VCONST~c'` onto the stack. + +.. math:: + \begin{array}{l} + \begin{array}{lcl@{\qquad}l} + (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i8x16}\K{.}\RSWIZZLE &\stepto& (\V128\K{.}\VCONST~c') + \end{array} + \\ \qquad + \begin{array}[t]{@{}r@{~}l@{}} + (\iff & i^\ast = \lanes_{i8x16}(c_2) \\ + \wedge & c^\ast = \lanes_{i8x16}(c_1)~0^{240} \\ + \wedge & c' = \lanes^{-1}_{i8x16}(c^\ast[ i^\ast[0] ] \dots c^\ast[ i^\ast[15] ])) + \end{array} + \end{array} + + .. _exec-vec-shuffle: :math:`\K{i8x16.}\SHUFFLE~x^\ast` diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst index 9c48736b0..5e8888421 100644 --- a/document/core/syntax/instructions.rst +++ b/document/core/syntax/instructions.rst @@ -190,6 +190,9 @@ Occasionally, it is convenient to group operators together according to the foll .. _syntax-visatbinop: .. _syntax-vfunop: .. _syntax-vfbinop: +.. _syntax-rvfbinop: +.. _syntax-rvfternop: +.. _syntax-rvftruncop: .. _syntax-instr-vec: Vector Instructions @@ -273,8 +276,16 @@ Vector instructions (also known as *SIMD* instructions, *single instruction mult \K{f32x4.}\VCONVERT\K{\_i32x4\_}\sx ~|~ \K{f32x4.}\VDEMOTE\K{\_f64x2\_zero} \\&&|& \K{f64x2.}\VCONVERT\K{\_low\_i32x4\_}\sx ~|~ - \K{f64x2.}\VPROMOTE\K{\_low\_f32x4} \\&&|& - \dots \\ + \K{f64x2.}\VPROMOTE\K{\_low\_f32x4} \\ + & \exprofiles{\PROFDET} &|& \K{i8x16.relaxed\_swizzle} \\ + & \exprofiles{\PROFDET} &|& \K{i32x4.}\RVTRUNC\K{\_f32x4\_}\sx \\ + & \exprofiles{\PROFDET} &|& \fshape\K{.}\rvfternop \\ + & \exprofiles{\PROFDET} &|& \ishape\K{.relaxed\_laneselect} \\ + & \exprofiles{\PROFDET} &|& \fshape\K{.}\rvfbinop \\ + & \exprofiles{\PROFDET} &|& \K{i16x8.}\RQ15MULRS \\ + & \exprofiles{\PROFDET} &|& \K{i16x8.relaxed\_dot\_i8x16\_i7x16\_s} \\ + & \exprofiles{\PROFDET} &|& \K{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s} \\ + & &|& \dots \\ \end{array} .. math:: @@ -338,6 +349,12 @@ Vector instructions (also known as *SIMD* instructions, *single instruction mult \K{max} ~|~ \K{pmin} ~|~ \K{pmax} \\ + \production{relaxed vector floating-point binary operator} & \rvfbinop &::=& + \K{relaxed\_min} ~|~ + \K{relaxed\_max} \\ + \production{relaxed vector floating-point ternary operator} & \rvfternop &::=& + \K{relaxed\_madd} ~|~ + \K{relaxed\_nmadd} \\ \end{array} .. _syntax-vec-shape: @@ -399,9 +416,17 @@ Occasionally, it is convenient to group operators together according to the foll \production{binary operator} & \vbinop &::=& \vibinop ~|~ \vfbinop \\&&|& \viminmaxop ~|~ \visatbinop \\&&|& + \rvfbinop \\&&|& \VMUL ~|~ \AVGR\K{\_u} ~|~ - \Q15MULRSAT\K{\_s} \\ + \Q15MULRSAT\K{\_s} \\&&|& + \RQ15MULRS\K{\_s} ~|~ + \K{relaxed\_dot\_i8x16\_i7x16\_s} \\ + \production{ternary operator} & \vternop &::=& + \vvternop ~|~ + \rvfternop \\&&|& + \K{relaxed\_laneselect} ~|~ + \K{relaxed\_dot\_i8x16\_i7x16\_add\_s} \\ \production{test operator} & \vtestop &::=& \vitestop \\ \production{relational operator} & \vrelop &::=& @@ -411,7 +436,8 @@ Occasionally, it is convenient to group operators together according to the foll \VTRUNC\K{\_sat} ~|~ \VCONVERT ~|~ \VDEMOTE ~|~ - \VPROMOTE \\ + \VPROMOTE ~|~ + \RVTRUNC \\ \end{array} diff --git a/document/core/text/instructions.rst b/document/core/text/instructions.rst index 0e8c577de..e0ec41e4c 100644 --- a/document/core/text/instructions.rst +++ b/document/core/text/instructions.rst @@ -894,6 +894,31 @@ Vector constant instructions have a mandatory :ref:`shape ` de \text{f64x2.promote\_low\_f32x4} &\Rightarrow& \F64X2.\VPROMOTE\K{\_low\_f32x4}\\ \end{array} +.. math:: + \begin{array}{llclll} + \phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averyveryverylonginstructionnameforvectext} && \phantom{vechasreallyreallyreallylonginstructionnames} \\[-2ex] &&|& + \text{i16x8.relaxed\_swizzle} &\Rightarrow& \I16X8.\RSWIZZLE \\ &&|& + \text{i32x4.relaxed\_trunc\_f32x4\_s} &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_s} \\ &&|& + \text{i32x4.relaxed\_trunc\_f32x4\_u} &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_u} \\ &&|& + \text{i32x4.relaxed\_trunc\_f32x4\_s\_zero} &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_s\_zero} \\ &&|& + \text{i32x4.relaxed\_trunc\_f32x4\_u\_zero} &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_u\_zero} \\ &&|& + \text{f32x4.relaxed\_madd} &\Rightarrow& \F32X4.\K{relaxed\_madd} \\ &&|& + \text{f32x4.relaxed\_nmadd} &\Rightarrow& \F32X4.\K{relaxed\_nmadd} \\ &&|& + \text{f64x2.relaxed\_madd} &\Rightarrow& \F64X2.\K{relaxed\_madd} \\ &&|& + \text{f64x2.relaxed\_nmadd} &\Rightarrow& \F64X2.\K{relaxed\_nmadd} \\ &&|& + \text{i8x16.relaxed\_laneselect} &\Rightarrow& \I8X16.\K{relaxed\_laneselect} \\ &&|& + \text{i16x8.relaxed\_laneselect} &\Rightarrow& \I16X8.\K{relaxed\_laneselect} \\ &&|& + \text{i32x4.relaxed\_laneselect} &\Rightarrow& \I32X4.\K{relaxed\_laneselect} \\ &&|& + \text{i64x2.relaxed\_laneselect} &\Rightarrow& \I64X2.\K{relaxed\_laneselect} \\ &&|& + \text{f32x4.relaxed\_min} &\Rightarrow& \F32X4.\K{relaxed\_min} \\ &&|& + \text{f32x4.relaxed\_max} &\Rightarrow& \F32X4.\K{relaxed\_max} \\ &&|& + \text{f64x2.relaxed\_min} &\Rightarrow& \F64X2.\K{relaxed\_min} \\ &&|& + \text{f64x2.relaxed\_max} &\Rightarrow& \F64X2.\K{relaxed\_max} \\ &&|& + \text{i16x8.relaxed\_q15mulr\_s} &\Rightarrow& \I16X8.\RQ15MULRS \\ &&|& + \text{i16x8.relaxed\_dot\_i8x16\_i7x16\_s} &\Rightarrow& \I16X8.\K{relaxed\_dot\_i8x16\_i7x16\_s} \\ &&|& + \text{i16x8.relaxed\_dot\_i8x16\_i7x16\_add\_s} &\Rightarrow& \I16X8.\K{relaxed\_dot\_i8x16\_i7x16\_add\_s} + \end{array} + .. index:: ! folded instruction, S-expression .. _text-foldedinstr: diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 1a4dd1d20..a3c91298f 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -498,6 +498,9 @@ .. |EXTADDPAIRWISE| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{extadd\_pairwise}} .. |VDEMOTE| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{demote}} .. |VPROMOTE| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{promote}} +.. |RSWIZZLE| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_swizzle}} +.. |RQ15MULRS| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_q15mulr\_s}} +.. |RVTRUNC| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_trunc}} .. Instructions, non-terminals @@ -545,6 +548,9 @@ .. |vfrelop| mathdef:: \xref{syntax/instructions}{syntax-vfrelop}{\X{vfrelop}} .. |vitestop| mathdef:: \xref{syntax/instructions}{syntax-vitestop}{\X{vitestop}} .. |vtestop| mathdef:: \xref{syntax/instructions}{syntax-vtestop}{\X{vtestop}} +.. |rvfbinop| mathdef:: \xref{syntax/instructions}{syntax-rvfbinop}{\X{rvfbinop}} +.. |rvfternop| mathdef:: \xref{syntax/instructions}{syntax-rvfternop}{\X{rvfternop}} +.. |rvftruncop| mathdef:: \xref{syntax/instructions}{syntax-rvftruncop}{\X{rvftruncop}} .. |sx| mathdef:: \xref{syntax/instructions}{syntax-sx}{\X{sx}} .. |half| mathdef:: \xref{syntax/instructions}{syntax-half}{\X{half}} diff --git a/document/core/valid/instructions.rst b/document/core/valid/instructions.rst index afcda69c0..d15c0f257 100644 --- a/document/core/valid/instructions.rst +++ b/document/core/valid/instructions.rst @@ -320,9 +320,9 @@ The following auxiliary function denotes the number of lanes in a vector shape, } -.. _valid-vvternop: +.. _valid-vternop: -:math:`\V128\K{.}\vvternop` +:math:`\V128\K{.}\vternop` ........................... * The instruction is valid with type :math:`[\V128~\V128~\V128] \to [\V128]`. @@ -330,7 +330,7 @@ The following auxiliary function denotes the number of lanes in a vector shape, .. math:: \frac{ }{ - C \vdashinstr \V128\K{.}\vvternop : [\V128~\V128~\V128] \to [\V128] + C \vdashinstr \V128\K{.}\vternop : [\V128~\V128~\V128] \to [\V128] } @@ -350,8 +350,8 @@ The following auxiliary function denotes the number of lanes in a vector shape, .. _valid-vec-swizzle: -:math:`\K{i8x16.}\SWIZZLE` -.......................... +:math:`\K{i8x16.}\SWIZZLE` :math:`\K{i8x16.relaxed\_swizzle}` +............................................................. * The instruction is valid with type :math:`[\V128~\V128] \to [\V128]`. From ab7d0be29469efd1a8d582219ca4f4817bb17b72 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 25 Jan 2023 21:12:03 +0000 Subject: [PATCH 071/117] Changes to execution and validation --- document/core/exec/instructions.rst | 104 ++++++++++++++++++++++++-- document/core/exec/numerics.rst | 81 ++++++++++++-------- document/core/syntax/instructions.rst | 23 +++--- document/core/util/macros.def | 3 + document/core/valid/instructions.rst | 60 +++++++++++++-- 5 files changed, 215 insertions(+), 56 deletions(-) diff --git a/document/core/exec/instructions.rst b/document/core/exec/instructions.rst index c89774273..16771a852 100644 --- a/document/core/exec/instructions.rst +++ b/document/core/exec/instructions.rst @@ -325,12 +325,12 @@ Most vector instructions are defined in terms of generic numeric operators appli \end{array} -.. _exec-vternop: +.. _exec-vvternop: -:math:`\V128\K{.}\vternop` +:math:`\V128\K{.}\vvternop` ........................... -1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. +1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. 2. Pop the value :math:`\V128.\VCONST~c_3` from the stack. @@ -338,14 +338,14 @@ Most vector instructions are defined in terms of generic numeric operators appli 4. Pop the value :math:`\V128.\VCONST~c_1` from the stack. -5. Let :math:`c` be the result of computing :math:`\vternop{\I128}(c_1, c_2, c_3)`. +5. Let :math:`c` be the result of computing :math:`\vvternop_{\I128}(c_1, c_2, c_3)`. 6. Push the value :math:`\V128.\VCONST~c` to the stack. .. math:: \begin{array}{lcl@{\qquad}l} - (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\V128\K{.}\vternop &\stepto& (\V128\K{.}\VCONST~c) - & (\iff c = \vternop{\I128}(c_1, c_2, c_3)) \\ + (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\V128\K{.}\vvternop &\stepto& (\V128\K{.}\VCONST~c) + & (\iff c = \vvternop_{\I128}(c_1, c_2, c_3)) \\ \end{array} @@ -618,6 +618,28 @@ Most vector instructions are defined in terms of generic numeric operators appli \end{array} +:math:`\shape\K{.}\vternop` +........................... + +1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. + +2. Pop the value :math:`\V128.\VCONST~c_3` from the stack. + +3. Pop the value :math:`\V128.\VCONST~c_2` from the stack. + +4. Pop the value :math:`\V128.\VCONST~c_1` from the stack. + +5. Let :math:`c` be the result of computing :math:`\vternop_{\shape}(c_1, c_2, c_3)`. + +6. Push the value :math:`\V128.\VCONST~c` to the stack. + +.. math:: + \begin{array}{lcl@{\qquad}l} + (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\V128\K{.}\vternop &\stepto& (\V128\K{.}\VCONST~c) + & (\iff c = \vternop_{\shape}(c_1, c_2, c_3)) \\ + \end{array} + + .. _exec-vrelop: :math:`t\K{x}N\K{.}\vrelop` @@ -901,6 +923,76 @@ where: \end{array} +.. _exec-vec-rdot: + + +:math:`\K{i16x8.}\_dot\K{\_i8x16\_i7x16\_s}` +................................................... + +1. Assert: due to :ref:`validation `, two values of :ref:`value type ` |V128| are on the top of the stack. + +2. Pop the value :math:`\V128.\VCONST~c_2` from the stack. + +3. Pop the value :math:`\V128.\VCONST~c_1` from the stack. + +4. Let :math:`(i_1~i_2)^8` be the result of computing :math:`\ridotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` + +5. Let :math:`j^8` be the result of computing :math:`\iadd_{16}(i_1, i_2)^8`. + +6. Let :math:`c` be the result of computing :math:`\lanes^{-1}_{\I16X8}(j^8)`. + +7. Push the value :math:`\V128.\VCONST~c` onto the stack. + +.. math:: + \begin{array}{l} + \begin{array}{llcl@{\qquad}l} + & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i16x8.}relaxed\_dot\K{\_i8x16\_i7x16\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ + \end{array} + \\ \qquad + \begin{array}[t]{@{}r@{~}l@{}} + (\iff & (i_1~i_2)^8 = \ridotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ + \wedge & j^8 = \iadd_{16}(i_1, i_2)^8 \\ + \wedge & c = \lanes^{-1}_{\I16X8}(j^8)) + \end{array} + \end{array} + + +:math:`\K{i32x4.}\_dot\K{\_i8x16\_i7x16\_add\_s}` +........................................................ + +1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. + +2. Pop the value :math:`\V128.\VCONST~c_3` from the stack. + +3. Pop the value :math:`\V128.\VCONST~c_2` from the stack. + +4. Pop the value :math:`\V128.\VCONST~c_1` from the stack. + +5. Let :math:`(i_1~i_2~i_3~i_4)^4` be the result of computing :math:`\ridotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` + +6. Let :math:`k^4` be the result of computing :math:`\lanes_{\I32X4}(c_3)`. + +7. Let :math:`j^4` be the result of computing :math:`\iadd_{32}(i_1, i_2, i_3, i_4, k)^4`. + +8. Let :math:`c` be the result of computing :math:`\lanes^{-1}_{\I32X4}(j^4)`. + +9. Push the value :math:`\V128.\VCONST~c` onto the stack. + +.. math:: + \begin{array}{l} + \begin{array}{llcl@{\qquad}l} + & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\K{i32x4.}\_dot\K{\_i8x16\_i7x16\_add\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ + \end{array} + \\ \qquad + \begin{array}[t]{@{}r@{~}l@{}} + (\iff & (i_1~i_2~i_3~i_4)^4 = \ridotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ + \wedge & k^4 = \lanes_{\I32X4}(c_3) \\ + \wedge & j^4 = \iadd_{16}(i_1, i_2, i_3, i_4, k)^4 \\ + \wedge & c = \lanes^{-1}_{\I32X4}(j^4)) + \end{array} + \end{array} + + .. _exec-vec-extmul: :math:`t_2\K{x}N\K{.}\EXTMUL\K{\_}\half\K{\_}t_1\K{x}M\K{\_}\sx` diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index f284f2da1..2da425417 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2003,10 +2003,11 @@ allows for fused or unfused results. :math:`fma` is defined by |IEEE754|_ (Section 5.4.1) as *fusedMultiplyAdd*. .. math:: - \begin{array}{@{}lcll} - relaxed\_madd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), fma_N(z_1, z_2, z_3) ] \\ + \begin{array}{@{}llcll} + \EXPROFDET & relaxed\_madd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), fma_N(z_1, z_2, z_3) ] \\ + & relaxed\_madd_N(z_1, z_2, z_3) &=& \fadd_N(\fmul_N(z_1, z_2), z_3) \\ \\ - relaxed\_fnma_N(z_1, z_2, z_3) &=& relaxed\_madd_N(-z_1, z_2, z_3) \\ + & relaxed\_fnma_N(z_1, z_2, z_3) &=& relaxed\_madd_N(-z_1, z_2, z_3) \\ \end{array} Relaxed swizzle lane is a helper for relaxed swizzle. Result is deterministic @@ -2014,27 +2015,30 @@ if the signed interpretation of the index is less than 16 (including negative). :math:`j` is a 8-bit int. .. math:: - \begin{array}{@{}lcll} - relaxed\_swizzle\_lane(i^n, j) &=& [ i[j], i[j] ] & (\iff j < 16) \\ - relaxed\_swizzle\_lane(i^n, j) &=& [ 0, 0 ] & (\iff \signed_8(j) < 0) \\ - relaxed\_swizzle\_lane(i^n, j) &=& [ 0, i[j \mod n] ] & (\otherwise) \\ + \begin{array}{@{}llcll} + & relaxed\_swizzle\_lane(i^n, j) &=& i[j] & (\iff j < 16) \\ + & relaxed\_swizzle\_lane(i^n, j) &=& 0 & (\iff \signed_8(j) < 0) \\ + \EXPROFDET & relaxed\_swizzle\_lane(i^n, j) &=& [ 0, i[j \mod n] ] & (\otherwise) \\ + & relaxed\_swizzle\_lane(i^n, j) &=& 0 & (\otherwise) \\ \\ - relaxed\_swizzle(a^n, s^n) &=& rsl_0 \dots rsl_{n-1} \\ - \qquad \where rsl_i &=& relaxed\_swizzle\_lane(a^n, s^n[i]) + & relaxed\_swizzle(a^n, s^n) &=& rsl_0 \dots rsl_{n-1} \\ + & \qquad \where rsl_i &=& relaxed\_swizzle\_lane(a^n, s^n[i]) \end{array} Relaxed truncate converts float to int, NaN and out of range values are hardware dependent. .. math:: - \begin{array}{@{}lcll} - relaxed\_trunc^s_{M,N}(\pm \NAN(n)) &=& [ 0, -2^{N-1} ] \\ - relaxed\_trunc^s_{M,N}(\pm q) &=& \truncs_{M,N}(\pm q) & (\iff -2^{N-1} - 1 < \trunc(\pm q) < 2^{N-1}) \\ - relaxed\_trunc^s_{M,N}(\pm p) &=& [ \truncsats_{M,N}(\pm p), -2^{N-1} ] & (\otherwise) \\ + \begin{array}{@{}llcll} + \EXPROFDET & relaxed\_trunc^s_{M,N}(\pm \NAN(n)) &=& [ 0, -2^{N-1} ] \\ + \EXPROFDET & relaxed\_trunc^s_{M,N}(\pm q) &=& \truncs_{M,N}(\pm q) & (\iff -2^{N-1} - 1 < \trunc(\pm q) < 2^{N-1}) \\ + \EXPROFDET & relaxed\_trunc^s_{M,N}(\pm p) &=& [ \truncsats_{M,N}(\pm p), -2^{N-1} ] & (\otherwise) \\ + & relaxed\_trunc^s_{M,N}(\pm p) &=& \truncsats_{M,N}(\pm p) & (\otherwise) \\ \\ - relaxed\_trunc^u_{M,N}(\pm \NAN(n)) &=& [ 0, 2^{N}-1 ] \\ - relaxed\_trunc^u_{M,N}(\pm q) &=& \truncu_{M,N}(\pm q) & (\iff -1 < \trunc(\pm q) < 2^N) \\ - relaxed\_trunc^u_{M,N}(\pm p) &=& [ \truncsatu_{M,N}(\pm p), 2^{N}-1 ] & (\otherwise) \\ + \EXPROFDET & relaxed\_trunc^u_{M,N}(\pm \NAN(n)) &=& [ 0, 2^{N}-1 ] \\ + \EXPROFDET & relaxed\_trunc^u_{M,N}(\pm q) &=& \truncu_{M,N}(\pm q) & (\iff -1 < \trunc(\pm q) < 2^N) \\ + \EXPROFDET & relaxed\_trunc^u_{M,N}(\pm p) &=& [ \truncsatu_{M,N}(\pm p), 2^{N}-1 ] & (\otherwise) \\ + & relaxed\_trunc^u_{M,N}(\pm p) &=& \truncsatu_{M,N}(\pm p) & (\otherwise) \\ \end{array} Relaxed lane select is deterministic where all bits are set or unset in the @@ -2042,14 +2046,15 @@ mask. Otherwise depending on hardware, either only the top bit is examined, or all bits are examined (becomes a bitselect). .. math:: - \begin{array}{@{}lcll} - relaxed\_laneselect\_lane_N(i_1, i_2, 2^N-1) &=& [ i_1, i_1 ] \\ - relaxed\_laneselect\_lane_N(i_1, i_2, 0) &=& [ i_2, i_2 ] \\ - relaxed\_laneselect\_lane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_1 ] & (\iff \signed_N(i_3) < 0) \\ - relaxed\_laneselect\_lane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_2 ] & (\otherwise) \\ + \begin{array}{@{}llcll} + & relaxed\_laneselect\_lane_N(i_1, i_2, 2^N-1) &=& i_1 \\ + & relaxed\_laneselect\_lane_N(i_1, i_2, 0) &=& i_2 \\ + \EXPROFDET & relaxed\_laneselect\_lane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_1 ] & (\iff \signed_N(i_3) < 0) \\ + \EXPROFDET & relaxed\_laneselect\_lane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_2 ] & (\otherwise) \\ + & relaxed\_laneselect\_lane_N(i_1, i_2, i_3) &=& \ibitselect_N(i_1, i_2, i_3) & (\otherwise) \\ \\ - relaxed\_laneselect_W(a^n, b^n, c^n) &=& rll_0 \dots rll_{n-1} \\ - \qquad \where rll_i &=& relaxed\_laneselect\_lane_W(a^n, b^n, c^n[i]) + & relaxed\_laneselect_W(a^n, b^n, c^n) &=& rll_0 \dots rll_{n-1} \\ + & \qquad \where rll_i &=& relaxed\_laneselect\_lane_W(a^n[i], b^n[i], c^n[i]) \\ \end{array} Relaxed min and max differs from min and max when inputs are NaNs or different @@ -2057,17 +2062,27 @@ signs of 0. It allows for implementation to return the first or second input when either input is a NaN. .. math:: - \begin{array}{@{}lcll} - relaxed\_min_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ - relaxed\_min_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ - relaxed\_min_N(\pm 0, \mp 0) &=& [ -0, \pm 0, \mp 0, -0 ] \\ - relaxed\_min_N(z_1, z_2) &=& \fmin_N(z_1, z_2) & (\otherwise) \\ + \begin{array}{@{}llcll} + \EXPROFDET & relaxed\_min_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ + \EXPROFDET & relaxed\_min_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ + \EXPROFDET & relaxed\_min_N(\pm 0, \mp 0) &=& [ -0, \pm 0, \mp 0, -0 ] \\ + & relaxed\_min_N(z_1, z_2) &=& \fmin_N(z_1, z_2) & (\otherwise) \\ \end{array} .. math:: - \begin{array}{@{}lcll} - relaxed\_max_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ - relaxed\_max_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ - relaxed\_max_N(\pm 0, \mp 0) &=& [ +0, \pm 0, \mp 0, +0 ] \\ - relaxed\_max_N(z_1, z_2) &=& \fmax_N(z_1, z_2) & (\otherwise) \\ + \begin{array}{@{}llcll} + \EXPROFDET & relaxed\_max_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ + \EXPROFDET & relaxed\_max_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ + \EXPROFDET & relaxed\_max_N(\pm 0, \mp 0) &=& [ +0, \pm 0, \mp 0, +0 ] \\ + & relaxed\_max_N(z_1, z_2) &=& \fmax_N(z_1, z_2) & (\otherwise) \\ + \end{array} + +.. _op-ridotmul: + +Relaxed integer dot product differs from integer dot product when the elements of the input have top bit set. + +.. math:: + \begin{array}{@{}llcll} + \EXPROFDET & relaxed\_dot\_mul_{M,N}(i_1, i_2) &=& [ \imul_N(\signed_M(i_1), i_2), \imul_N(\signed_M(i_1), \signed_M(i_2)) ] \\ + & relaxed\_dot\_mul_{M,N}(i_1, i_2) &=& \imul_N(\extends_{M,N}(i_1), \extends_{M,N}(i_2)) \\ \end{array} diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst index 5e8888421..5f912a2b2 100644 --- a/document/core/syntax/instructions.rst +++ b/document/core/syntax/instructions.rst @@ -277,14 +277,14 @@ Vector instructions (also known as *SIMD* instructions, *single instruction mult \K{f32x4.}\VDEMOTE\K{\_f64x2\_zero} \\&&|& \K{f64x2.}\VCONVERT\K{\_low\_i32x4\_}\sx ~|~ \K{f64x2.}\VPROMOTE\K{\_low\_f32x4} \\ - & \exprofiles{\PROFDET} &|& \K{i8x16.relaxed\_swizzle} \\ - & \exprofiles{\PROFDET} &|& \K{i32x4.}\RVTRUNC\K{\_f32x4\_}\sx \\ - & \exprofiles{\PROFDET} &|& \fshape\K{.}\rvfternop \\ - & \exprofiles{\PROFDET} &|& \ishape\K{.relaxed\_laneselect} \\ - & \exprofiles{\PROFDET} &|& \fshape\K{.}\rvfbinop \\ - & \exprofiles{\PROFDET} &|& \K{i16x8.}\RQ15MULRS \\ - & \exprofiles{\PROFDET} &|& \K{i16x8.relaxed\_dot\_i8x16\_i7x16\_s} \\ - & \exprofiles{\PROFDET} &|& \K{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s} \\ + & &|& \K{i8x16.relaxed\_swizzle} \\ + & &|& \K{i32x4.}\RVTRUNC\K{\_f32x4\_}\sx \\ + & &|& \fshape\K{.}\rvfternop \\ + & &|& \ishape\K{.relaxed\_laneselect} \\ + & &|& \fshape\K{.}\rvfbinop \\ + & &|& \K{i16x8.}\RQ15MULRS \\ + & &|& \K{i16x8.relaxed\_dot\_i8x16\_i7x16\_s} \\ + & &|& \K{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s} \\ & &|& \dots \\ \end{array} @@ -399,6 +399,7 @@ For the other vector instructions, the use of two's complement for the signed in .. _syntax-vunop: .. _syntax-vbinop: .. _syntax-vrelop: +.. _syntax-vternop: .. _syntax-vtestop: .. _syntax-vcvtop: @@ -420,13 +421,11 @@ Occasionally, it is convenient to group operators together according to the foll \VMUL ~|~ \AVGR\K{\_u} ~|~ \Q15MULRSAT\K{\_s} \\&&|& - \RQ15MULRS\K{\_s} ~|~ - \K{relaxed\_dot\_i8x16\_i7x16\_s} \\ + \RQ15MULRS\K{\_s} \\ \production{ternary operator} & \vternop &::=& \vvternop ~|~ \rvfternop \\&&|& - \K{relaxed\_laneselect} ~|~ - \K{relaxed\_dot\_i8x16\_i7x16\_add\_s} \\ + \K{relaxed\_laneselect} \\ \production{test operator} & \vtestop &::=& \vitestop \\ \production{relational operator} & \vrelop &::=& diff --git a/document/core/util/macros.def b/document/core/util/macros.def index a3c91298f..a41c701ff 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -116,6 +116,7 @@ .. |PROFFULL| mathdef:: \xref{appendix/profiles}{profile-full}{\profile{FUL}} .. |PROFDET| mathdef:: \xref{appendix/profiles}{profile-deterministic}{\profile{DET}} +.. |EXPROFDET| mathdef:: \exprofiles{\PROFDET} @@ -1197,6 +1198,8 @@ .. |narrowu| mathdef:: \xref{exec/numerics}{op-narrow_u}{\F{narrow}^{\K{u}}} .. |narrows| mathdef:: \xref{exec/numerics}{op-narrow_s}{\F{narrow}^{\K{s}}} +.. |ridotmul| mathdef:: \xref{exec/numerics}{op-ridotmul}{\F{relaxed\_dot\_mul}} + .. Numerics, meta functions diff --git a/document/core/valid/instructions.rst b/document/core/valid/instructions.rst index d15c0f257..c5544f97e 100644 --- a/document/core/valid/instructions.rst +++ b/document/core/valid/instructions.rst @@ -320,9 +320,9 @@ The following auxiliary function denotes the number of lanes in a vector shape, } -.. _valid-vternop: +.. _valid-vvternop: -:math:`\V128\K{.}\vternop` +:math:`\V128\K{.}\vvternop` ........................... * The instruction is valid with type :math:`[\V128~\V128~\V128] \to [\V128]`. @@ -330,7 +330,7 @@ The following auxiliary function denotes the number of lanes in a vector shape, .. math:: \frac{ }{ - C \vdashinstr \V128\K{.}\vternop : [\V128~\V128~\V128] \to [\V128] + C \vdashinstr \V128\K{.}\vvternop : [\V128~\V128~\V128] \to [\V128] } @@ -350,8 +350,8 @@ The following auxiliary function denotes the number of lanes in a vector shape, .. _valid-vec-swizzle: -:math:`\K{i8x16.}\SWIZZLE` :math:`\K{i8x16.relaxed\_swizzle}` -............................................................. +:math:`\K{i8x16.}\SWIZZLE` +..................................... * The instruction is valid with type :math:`[\V128~\V128] \to [\V128]`. @@ -362,6 +362,20 @@ The following auxiliary function denotes the number of lanes in a vector shape, } +.. _valid-vec-rswizzle: + +:math:`\K{i8x16.}relaxed\_\SWIZZLE` +..................................... + +* The instruction is valid with type :math:`[\V128~\V128] \to [\V128]`. + +.. math:: + \frac{ + }{ + C \vdashinstr \K{i8x16.}relaxed\_\SWIZZLE : [\V128~\V128] \to [\V128] + } + + .. _valid-vec-shuffle: :math:`\K{i8x16.}\SHUFFLE~\laneidx^{16}` @@ -459,6 +473,20 @@ The following auxiliary function denotes the number of lanes in a vector shape, } +.. _valid-vternop: + +:math:`\shape\K{.}\vternop` +........................... + +* The instruction is valid with type :math:`[\V128~\V128~\V128] \to [\V128]`. + +.. math:: + \frac{ + }{ + C \vdashinstr \shape\K{.}\vternop : [\V128~\V128~\V128] \to [\V128] + } + + .. _valid-vrelop: :math:`\shape\K{.}\vrelop` @@ -556,6 +584,28 @@ The following auxiliary function denotes the number of lanes in a vector shape, C \vdashinstr \ishape_1\K{.}\DOT\K{\_}\ishape_2\K{\_s} : [\V128~\V128] \to [\V128] } +:math:`\ishape_1\K{.}\DOT\K{\_}\ishape_2\_\K{i7x16\_s}` +....................................................... + +* The instruction is valid with type :math:`[\V128~\V128] \to [\V128]`. + +.. math:: + \frac{ + }{ + C \vdashinstr \ishape_1\K{.}\DOT\K{\_}\ishape_2\_\K{i7x16\_s} : [\V128~\V128] \to [\V128] + } + +:math:`\ishape_1\K{.}\DOT\K{\_}\ishape_2\_\K{i7x16\_add\_\_s}` +.............................................................. + +* The instruction is valid with type :math:`[\V128~\V128~\V128] \to [\V128]`. + +.. math:: + \frac{ + }{ + C \vdashinstr \ishape_1\K{.}\DOT\K{\_}\ishape_2\_\K{i7x16\_add\_\_s} : [\V128~\V128~\V128] \to [\V128] + } + .. _valid-vec-extmul: From 1cf8ca9b880d47e98f6b767273a3c16fa4c9427c Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 25 Jan 2023 21:12:58 +0000 Subject: [PATCH 072/117] Fix to index instructions --- document/core/appendix/index-instructions.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/document/core/appendix/index-instructions.rst b/document/core/appendix/index-instructions.rst index 8ebfc2b82..977c21fb3 100644 --- a/document/core/appendix/index-instructions.rst +++ b/document/core/appendix/index-instructions.rst @@ -361,7 +361,7 @@ Instruction Binary Opcode :math:`\V128.\VANDNOT` :math:`\hex{FD}~~\hex{4F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\V128.\VOR` :math:`\hex{FD}~~\hex{50}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\V128.\VXOR` :math:`\hex{FD}~~\hex{51}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\BITSELECT` :math:`\hex{FD}~~\hex{52}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\BITSELECT` :math:`\hex{FD}~~\hex{52}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\V128.\ANYTRUE` :math:`\hex{FD}~~\hex{53}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` :math:`\V128.\LOAD\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{54}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` :math:`\V128.\LOAD\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{55}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` From 52668fa048399e517fa6e2bae22a8df11bbcb5bb Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 25 Jan 2023 21:15:19 +0000 Subject: [PATCH 073/117] Fix instruction generation script --- document/core/appendix/gen-index-instructions.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/document/core/appendix/gen-index-instructions.py b/document/core/appendix/gen-index-instructions.py index b533ae3c9..fffa2b329 100755 --- a/document/core/appendix/gen-index-instructions.py +++ b/document/core/appendix/gen-index-instructions.py @@ -421,7 +421,7 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\V128.\VANDNOT', r'\hex{FD}~~\hex{4F}', r'[\V128~\V128] \to [\V128]', r'valid-vvbinop', r'exec-vvbinop', r'op-iandnot'), Instruction(r'\V128.\VOR', r'\hex{FD}~~\hex{50}', r'[\V128~\V128] \to [\V128]', r'valid-vvbinop', r'exec-vvbinop', r'op-ior'), Instruction(r'\V128.\VXOR', r'\hex{FD}~~\hex{51}', r'[\V128~\V128] \to [\V128]', r'valid-vvbinop', r'exec-vvbinop', r'op-ixor'), - Instruction(r'\V128.\BITSELECT', r'\hex{FD}~~\hex{52}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-ibitselect'), + Instruction(r'\V128.\BITSELECT', r'\hex{FD}~~\hex{52}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vvternop', r'exec-vvternop', r'op-ibitselect'), Instruction(r'\V128.\ANYTRUE', r'\hex{FD}~~\hex{53}', r'[\V128] \to [\I32]', r'valid-vvtestop', r'exec-vvtestop'), Instruction(r'\V128.\LOAD\K{8\_lane}~\memarg~\laneidx', r'\hex{FD}~~\hex{54}', r'[\I32~\V128] \to [\V128]', r'valid-load-lane', r'exec-load-lane'), Instruction(r'\V128.\LOAD\K{16\_lane}~\memarg~\laneidx', r'\hex{FD}~~\hex{55}', r'[\I32~\V128] \to [\V128]', r'valid-load-lane', r'exec-load-lane'), From 83b983d4d46070860ffbae736a2c0ec3de5cc938 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 25 Jan 2023 21:28:35 +0000 Subject: [PATCH 074/117] Add macros --- document/core/exec/instructions.rst | 8 ++--- document/core/exec/numerics.rst | 42 +++++++++++++++++++-------- document/core/syntax/instructions.rst | 1 - document/core/util/macros.def | 10 +++++-- document/core/valid/instructions.rst | 8 ++--- 5 files changed, 46 insertions(+), 23 deletions(-) diff --git a/document/core/exec/instructions.rst b/document/core/exec/instructions.rst index 16771a852..5989a1fdd 100644 --- a/document/core/exec/instructions.rst +++ b/document/core/exec/instructions.rst @@ -926,7 +926,7 @@ where: .. _exec-vec-rdot: -:math:`\K{i16x8.}\_dot\K{\_i8x16\_i7x16\_s}` +:math:`\K{i16x8.}\DOT\K{\_i8x16\_i7x16\_s}` ................................................... 1. Assert: due to :ref:`validation `, two values of :ref:`value type ` |V128| are on the top of the stack. @@ -946,7 +946,7 @@ where: .. math:: \begin{array}{l} \begin{array}{llcl@{\qquad}l} - & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i16x8.}relaxed\_dot\K{\_i8x16\_i7x16\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ + & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i16x8.}\DOT\K{\_i8x16\_i7x16\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} @@ -957,7 +957,7 @@ where: \end{array} -:math:`\K{i32x4.}\_dot\K{\_i8x16\_i7x16\_add\_s}` +:math:`\K{i32x4.}\DOT\K{\_i8x16\_i7x16\_add\_s}` ........................................................ 1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. @@ -981,7 +981,7 @@ where: .. math:: \begin{array}{l} \begin{array}{llcl@{\qquad}l} - & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\K{i32x4.}\_dot\K{\_i8x16\_i7x16\_add\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ + & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\K{i32x4.}\DOT\K{\_i8x16\_i7x16\_add\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 2da425417..c327cc8cc 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -1998,18 +1998,25 @@ each environment globally chooses a fixed projection for each operator. text description is an informal description of the instructions and are not the final text. + +.. _op-relaxed_madd: +.. _op-relaxed_nmadd: + Relaxed Multiply Add (madd) and Relaxed Negative Multiply Add (nmadd) allows for fused or unfused results. :math:`fma` is defined by |IEEE754|_ (Section 5.4.1) as *fusedMultiplyAdd*. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & relaxed\_madd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), fma_N(z_1, z_2, z_3) ] \\ - & relaxed\_madd_N(z_1, z_2, z_3) &=& \fadd_N(\fmul_N(z_1, z_2), z_3) \\ + \EXPROFDET & \rmadd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), fma_N(z_1, z_2, z_3) ] \\ + & \rmadd_N(z_1, z_2, z_3) &=& \fadd_N(\fmul_N(z_1, z_2), z_3) \\ \\ - & relaxed\_fnma_N(z_1, z_2, z_3) &=& relaxed\_madd_N(-z_1, z_2, z_3) \\ + & \rnmadd_N(z_1, z_2, z_3) &=& \rmadd_N(-z_1, z_2, z_3) \\ \end{array} + +.. _op-relaxed_swizzle: + Relaxed swizzle lane is a helper for relaxed swizzle. Result is deterministic if the signed interpretation of the index is less than 16 (including negative). :math:`j` is a 8-bit int. @@ -2021,10 +2028,13 @@ if the signed interpretation of the index is less than 16 (including negative). \EXPROFDET & relaxed\_swizzle\_lane(i^n, j) &=& [ 0, i[j \mod n] ] & (\otherwise) \\ & relaxed\_swizzle\_lane(i^n, j) &=& 0 & (\otherwise) \\ \\ - & relaxed\_swizzle(a^n, s^n) &=& rsl_0 \dots rsl_{n-1} \\ + & \rswizzle(a^n, s^n) &=& rsl_0 \dots rsl_{n-1} \\ & \qquad \where rsl_i &=& relaxed\_swizzle\_lane(a^n, s^n[i]) \end{array} + +.. _op-relaxed_trunc: + Relaxed truncate converts float to int, NaN and out of range values are hardware dependent. @@ -2033,14 +2043,17 @@ hardware dependent. \EXPROFDET & relaxed\_trunc^s_{M,N}(\pm \NAN(n)) &=& [ 0, -2^{N-1} ] \\ \EXPROFDET & relaxed\_trunc^s_{M,N}(\pm q) &=& \truncs_{M,N}(\pm q) & (\iff -2^{N-1} - 1 < \trunc(\pm q) < 2^{N-1}) \\ \EXPROFDET & relaxed\_trunc^s_{M,N}(\pm p) &=& [ \truncsats_{M,N}(\pm p), -2^{N-1} ] & (\otherwise) \\ - & relaxed\_trunc^s_{M,N}(\pm p) &=& \truncsats_{M,N}(\pm p) & (\otherwise) \\ + & \rtrunc^s_{M,N}(\pm p) &=& \truncsats_{M,N}(\pm p) & (\otherwise) \\ \\ \EXPROFDET & relaxed\_trunc^u_{M,N}(\pm \NAN(n)) &=& [ 0, 2^{N}-1 ] \\ \EXPROFDET & relaxed\_trunc^u_{M,N}(\pm q) &=& \truncu_{M,N}(\pm q) & (\iff -1 < \trunc(\pm q) < 2^N) \\ \EXPROFDET & relaxed\_trunc^u_{M,N}(\pm p) &=& [ \truncsatu_{M,N}(\pm p), 2^{N}-1 ] & (\otherwise) \\ - & relaxed\_trunc^u_{M,N}(\pm p) &=& \truncsatu_{M,N}(\pm p) & (\otherwise) \\ + & \rtrunc^u_{M,N}(\pm p) &=& \truncsatu_{M,N}(\pm p) & (\otherwise) \\ \end{array} + +.. _op-relaxed_laneselect: + Relaxed lane select is deterministic where all bits are set or unset in the mask. Otherwise depending on hardware, either only the top bit is examined, or all bits are examined (becomes a bitselect). @@ -2053,10 +2066,14 @@ all bits are examined (becomes a bitselect). \EXPROFDET & relaxed\_laneselect\_lane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_2 ] & (\otherwise) \\ & relaxed\_laneselect\_lane_N(i_1, i_2, i_3) &=& \ibitselect_N(i_1, i_2, i_3) & (\otherwise) \\ \\ - & relaxed\_laneselect_W(a^n, b^n, c^n) &=& rll_0 \dots rll_{n-1} \\ + & \rlaneselect_W(a^n, b^n, c^n) &=& rll_0 \dots rll_{n-1} \\ & \qquad \where rll_i &=& relaxed\_laneselect\_lane_W(a^n[i], b^n[i], c^n[i]) \\ \end{array} + +.. _op-relaxed_min: +.. _op-relaxed_max: + Relaxed min and max differs from min and max when inputs are NaNs or different signs of 0. It allows for implementation to return the first or second input when either input is a NaN. @@ -2066,7 +2083,7 @@ when either input is a NaN. \EXPROFDET & relaxed\_min_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ \EXPROFDET & relaxed\_min_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ \EXPROFDET & relaxed\_min_N(\pm 0, \mp 0) &=& [ -0, \pm 0, \mp 0, -0 ] \\ - & relaxed\_min_N(z_1, z_2) &=& \fmin_N(z_1, z_2) & (\otherwise) \\ + & \rmin(z_1, z_2) &=& \fmin_N(z_1, z_2) & (\otherwise) \\ \end{array} .. math:: @@ -2074,15 +2091,16 @@ when either input is a NaN. \EXPROFDET & relaxed\_max_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ \EXPROFDET & relaxed\_max_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ \EXPROFDET & relaxed\_max_N(\pm 0, \mp 0) &=& [ +0, \pm 0, \mp 0, +0 ] \\ - & relaxed\_max_N(z_1, z_2) &=& \fmax_N(z_1, z_2) & (\otherwise) \\ + & \rmax(z_1, z_2) &=& \fmax_N(z_1, z_2) & (\otherwise) \\ \end{array} -.. _op-ridotmul: + +.. _op-relaxed_idotmul: Relaxed integer dot product differs from integer dot product when the elements of the input have top bit set. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & relaxed\_dot\_mul_{M,N}(i_1, i_2) &=& [ \imul_N(\signed_M(i_1), i_2), \imul_N(\signed_M(i_1), \signed_M(i_2)) ] \\ - & relaxed\_dot\_mul_{M,N}(i_1, i_2) &=& \imul_N(\extends_{M,N}(i_1), \extends_{M,N}(i_2)) \\ + \EXPROFDET & \ridotmul{M,N}(i_1, i_2) &=& [ \imul_N(\signed_M(i_1), i_2), \imul_N(\signed_M(i_1), \signed_M(i_2)) ] \\ + & \ridotmul{M,N}(i_1, i_2) &=& \imul_N(\extends_{M,N}(i_1), \extends_{M,N}(i_2)) \\ \end{array} diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst index 5f912a2b2..63aaaa44b 100644 --- a/document/core/syntax/instructions.rst +++ b/document/core/syntax/instructions.rst @@ -192,7 +192,6 @@ Occasionally, it is convenient to group operators together according to the foll .. _syntax-vfbinop: .. _syntax-rvfbinop: .. _syntax-rvfternop: -.. _syntax-rvftruncop: .. _syntax-instr-vec: Vector Instructions diff --git a/document/core/util/macros.def b/document/core/util/macros.def index a41c701ff..31383012d 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -551,7 +551,6 @@ .. |vtestop| mathdef:: \xref{syntax/instructions}{syntax-vtestop}{\X{vtestop}} .. |rvfbinop| mathdef:: \xref{syntax/instructions}{syntax-rvfbinop}{\X{rvfbinop}} .. |rvfternop| mathdef:: \xref{syntax/instructions}{syntax-rvfternop}{\X{rvfternop}} -.. |rvftruncop| mathdef:: \xref{syntax/instructions}{syntax-rvftruncop}{\X{rvftruncop}} .. |sx| mathdef:: \xref{syntax/instructions}{syntax-sx}{\X{sx}} .. |half| mathdef:: \xref{syntax/instructions}{syntax-half}{\X{half}} @@ -1198,7 +1197,14 @@ .. |narrowu| mathdef:: \xref{exec/numerics}{op-narrow_u}{\F{narrow}^{\K{u}}} .. |narrows| mathdef:: \xref{exec/numerics}{op-narrow_s}{\F{narrow}^{\K{s}}} -.. |ridotmul| mathdef:: \xref{exec/numerics}{op-ridotmul}{\F{relaxed\_dot\_mul}} +.. |rmadd| mathdef:: \xref{exec/numerics}{op-relaxed_madd}{\F{relaxed\_madd}} +.. |rnmadd| mathdef:: \xref{exec/numerics}{op-relaxed_nmadd}{\F{relaxed\_nmadd}} +.. |rswizzle| mathdef:: \xref{exec/numerics}{op-relaxed_swizzle}{\F{relaxed\_swizzle}} +.. |rtrunc| mathdef:: \xref{exec/numerics}{op-relaxed_trunc}{\F{relaxed\_trunc}} +.. |rlaneselect| mathdef:: \xref{exec/numerics}{op-relaxed_laneselect}{\F{relaxed\_laneselect}} +.. |rmin| mathdef:: \xref{exec/numerics}{op-relaxed_min}{\F{relaxed\_min}} +.. |rmax| mathdef:: \xref{exec/numerics}{op-relaxed_max}{\F{relaxed\_max}} +.. |ridotmul| mathdef:: \xref{exec/numerics}{op-relaxed_idotmul}{\F{relaxed\_dot\_mul}} .. Numerics, meta functions diff --git a/document/core/valid/instructions.rst b/document/core/valid/instructions.rst index c5544f97e..6d2783e73 100644 --- a/document/core/valid/instructions.rst +++ b/document/core/valid/instructions.rst @@ -351,7 +351,7 @@ The following auxiliary function denotes the number of lanes in a vector shape, .. _valid-vec-swizzle: :math:`\K{i8x16.}\SWIZZLE` -..................................... +.......................... * The instruction is valid with type :math:`[\V128~\V128] \to [\V128]`. @@ -364,15 +364,15 @@ The following auxiliary function denotes the number of lanes in a vector shape, .. _valid-vec-rswizzle: -:math:`\K{i8x16.}relaxed\_\SWIZZLE` -..................................... +:math:`\K{i8x16.}\RSWIZZLE` +................................... * The instruction is valid with type :math:`[\V128~\V128] \to [\V128]`. .. math:: \frac{ }{ - C \vdashinstr \K{i8x16.}relaxed\_\SWIZZLE : [\V128~\V128] \to [\V128] + C \vdashinstr \K{i8x16.}\RSWIZZLE : [\V128~\V128] \to [\V128] } From 8824d97dcb8f6448fd8c33d309b3bb10bd34cc5d Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 25 Jan 2023 23:23:54 +0000 Subject: [PATCH 075/117] Update index of instructions, exec/numerics --- .../core/appendix/gen-index-instructions.py | 20 + document/core/appendix/index-instructions.rst | 1040 +++++++++-------- document/core/exec/instructions.rst | 64 +- document/core/exec/numerics.rst | 151 ++- document/core/syntax/instructions.rst | 17 +- document/core/util/macros.def | 25 +- document/core/valid/instructions.rst | 17 + 7 files changed, 740 insertions(+), 594 deletions(-) diff --git a/document/core/appendix/gen-index-instructions.py b/document/core/appendix/gen-index-instructions.py index fffa2b329..b0aba79c2 100755 --- a/document/core/appendix/gen-index-instructions.py +++ b/document/core/appendix/gen-index-instructions.py @@ -575,6 +575,26 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}', r'\hex{FD}~~\hex{FD}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_u'), Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_s}', r'\hex{FD}~~\hex{FE}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_s'), Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_u}', r'\hex{FD}~~\hex{FF}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_u'), + Instruction(r'\I8X16.\RSWIZZLE', r'\hex{FD}~~\hex{80}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vec-rswizzle', r'exec-vec-rswizzle', r'op-rswizzle'), + Instruction(r'\I32X4.\RTRUNC\K{\_f32x4\_s}', r'\hex{FD}~~\hex{81}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_s'), + Instruction(r'\I32X4.\RTRUNC\K{\_f32x4\_u}', r'\hex{FD}~~\hex{82}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_u'), + Instruction(r'\I32X4.\RTRUNC\K{\_f64x2\_s}', r'\hex{FD}~~\hex{83}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_s'), + Instruction(r'\I32X4.\RTRUNC\K{\_f64x2\_u}', r'\hex{FD}~~\hex{84}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_u'), + Instruction(r'\F32X4.\RMADD', r'\hex{FD}~~\hex{85}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frmadd'), + Instruction(r'\F32X4.\RNMADD', r'\hex{FD}~~\hex{86}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frnmadd'), + Instruction(r'\F64X2.\RMADD', r'\hex{FD}~~\hex{87}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frmadd'), + Instruction(r'\F64X2.\RNMADD', r'\hex{FD}~~\hex{88}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frnmadd'), + Instruction(r'\I8X16.\RLANESELECT', r'\hex{FD}~~\hex{89}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), + Instruction(r'\I16X8.\RLANESELECT', r'\hex{FD}~~\hex{8A}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), + Instruction(r'\I32X4.\RLANESELECT', r'\hex{FD}~~\hex{8B}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), + Instruction(r'\I64X2.\RLANESELECT', r'\hex{FD}~~\hex{8C}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), + Instruction(r'\F32X4.\RMIN', r'\hex{FD}~~\hex{8D}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmin'), + Instruction(r'\F32X4.\RMAX', r'\hex{FD}~~\hex{8E}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmax'), + Instruction(r'\F64X2.\RMIN', r'\hex{FD}~~\hex{8F}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmin'), + Instruction(r'\F64X2.\RMAX', r'\hex{FD}~~\hex{90}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmax'), + Instruction(r'\I16X8.\RQ15MULRS', r'\hex{FD}~~\hex{91}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-irq15mulr_s'), + Instruction(r'\I16X8.\RDOT\K{\_i8x16\_i7x16\_s}', r'\hex{FD}~~\hex{92}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vec-rdot', r'exec-vec-rdot', r'op-ridotmul'), + Instruction(r'\I32X4.\RDOT\K{\_i8x16\_i7x16\_add\_s}', r'\hex{FD}~~\hex{93}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vec-rdot', r'exec-vec-rdot', r'op-ridotmul'), ] diff --git a/document/core/appendix/index-instructions.rst b/document/core/appendix/index-instructions.rst index 977c21fb3..502935af0 100644 --- a/document/core/appendix/index-instructions.rst +++ b/document/core/appendix/index-instructions.rst @@ -6,516 +6,536 @@ Index of Instructions --------------------- -================================================= ==================================== ============================================= ============================================= ================================================================== -Instruction Binary Opcode Type Validation Execution -================================================= ==================================== ============================================= ============================================= ================================================================== -:math:`\UNREACHABLE` :math:`\hex{00}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\NOP` :math:`\hex{01}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` -:math:`\BLOCK~\X{bt}` :math:`\hex{02}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\LOOP~\X{bt}` :math:`\hex{03}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\IF~\X{bt}` :math:`\hex{04}` :math:`[t_1^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\ELSE` :math:`\hex{05}` -(reserved) :math:`\hex{06}` -(reserved) :math:`\hex{07}` -(reserved) :math:`\hex{08}` -(reserved) :math:`\hex{09}` -(reserved) :math:`\hex{0A}` -:math:`\END` :math:`\hex{0B}` -:math:`\BR~l` :math:`\hex{0C}` :math:`[t_1^\ast~t^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\BRIF~l` :math:`\hex{0D}` :math:`[t^\ast~\I32] \to [t^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\BRTABLE~l^\ast~l` :math:`\hex{0E}` :math:`[t_1^\ast~t^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\RETURN` :math:`\hex{0F}` :math:`[t_1^\ast~t^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\CALL~x` :math:`\hex{10}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\CALLINDIRECT~x~y` :math:`\hex{11}` :math:`[t_1^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -(reserved) :math:`\hex{12}` -(reserved) :math:`\hex{13}` -(reserved) :math:`\hex{14}` -(reserved) :math:`\hex{15}` -(reserved) :math:`\hex{16}` -(reserved) :math:`\hex{17}` -(reserved) :math:`\hex{18}` -(reserved) :math:`\hex{19}` -:math:`\DROP` :math:`\hex{1A}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` -:math:`\SELECT` :math:`\hex{1B}` :math:`[t~t~\I32] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\SELECT~t` :math:`\hex{1C}` :math:`[t~t~\I32] \to [t]` :ref:`validation ` :ref:`execution ` -(reserved) :math:`\hex{1D}` -(reserved) :math:`\hex{1E}` -(reserved) :math:`\hex{1F}` -:math:`\LOCALGET~x` :math:`\hex{20}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\LOCALSET~x` :math:`\hex{21}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` -:math:`\LOCALTEE~x` :math:`\hex{22}` :math:`[t] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\GLOBALGET~x` :math:`\hex{23}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\GLOBALSET~x` :math:`\hex{24}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` -:math:`\TABLEGET~x` :math:`\hex{25}` :math:`[\I32] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\TABLESET~x` :math:`\hex{26}` :math:`[\I32~t] \to []` :ref:`validation ` :ref:`execution ` -(reserved) :math:`\hex{27}` -:math:`\I32.\LOAD~\memarg` :math:`\hex{28}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD~\memarg` :math:`\hex{29}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\F32.\LOAD~\memarg` :math:`\hex{2A}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution ` -:math:`\F64.\LOAD~\memarg` :math:`\hex{2B}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\LOAD\K{8\_s}~\memarg` :math:`\hex{2C}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\LOAD\K{8\_u}~\memarg` :math:`\hex{2D}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\LOAD\K{16\_s}~\memarg` :math:`\hex{2E}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\LOAD\K{16\_u}~\memarg` :math:`\hex{2F}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{8\_s}~\memarg` :math:`\hex{30}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{8\_u}~\memarg` :math:`\hex{31}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{16\_s}~\memarg` :math:`\hex{32}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{16\_u}~\memarg` :math:`\hex{33}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{32\_s}~\memarg` :math:`\hex{34}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{32\_u}~\memarg` :math:`\hex{35}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\STORE~\memarg` :math:`\hex{36}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I64.\STORE~\memarg` :math:`\hex{37}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\F32.\STORE~\memarg` :math:`\hex{38}` :math:`[\I32~\F32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\F64.\STORE~\memarg` :math:`\hex{39}` :math:`[\I32~\F64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I32.\STORE\K{8}~\memarg` :math:`\hex{3A}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I32.\STORE\K{16}~\memarg` :math:`\hex{3B}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I64.\STORE\K{8}~\memarg` :math:`\hex{3C}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I64.\STORE\K{16}~\memarg` :math:`\hex{3D}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I64.\STORE\K{32}~\memarg` :math:`\hex{3E}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\MEMORYSIZE` :math:`\hex{3F}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\MEMORYGROW` :math:`\hex{40}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\CONST~\i32` :math:`\hex{41}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\CONST~\i64` :math:`\hex{42}` :math:`[] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\F32.\CONST~\f32` :math:`\hex{43}` :math:`[] \to [\F32]` :ref:`validation ` :ref:`execution ` -:math:`\F64.\CONST~\f64` :math:`\hex{44}` :math:`[] \to [\F64]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\EQZ` :math:`\hex{45}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\EQ` :math:`\hex{46}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\NE` :math:`\hex{47}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\LT\K{\_s}` :math:`\hex{48}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\LT\K{\_u}` :math:`\hex{49}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\GT\K{\_s}` :math:`\hex{4A}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\GT\K{\_u}` :math:`\hex{4B}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\LE\K{\_s}` :math:`\hex{4C}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\LE\K{\_u}` :math:`\hex{4D}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\GE\K{\_s}` :math:`\hex{4E}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\GE\K{\_u}` :math:`\hex{4F}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EQZ` :math:`\hex{50}` :math:`[\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EQ` :math:`\hex{51}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\NE` :math:`\hex{52}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\LT\K{\_s}` :math:`\hex{53}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\LT\K{\_u}` :math:`\hex{54}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\GT\K{\_s}` :math:`\hex{55}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\GT\K{\_u}` :math:`\hex{56}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\LE\K{\_s}` :math:`\hex{57}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\LE\K{\_u}` :math:`\hex{58}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\GE\K{\_s}` :math:`\hex{59}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\GE\K{\_u}` :math:`\hex{5A}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\EQ` :math:`\hex{5B}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\NE` :math:`\hex{5C}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\LT` :math:`\hex{5D}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\GT` :math:`\hex{5E}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\LE` :math:`\hex{5F}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\GE` :math:`\hex{60}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\EQ` :math:`\hex{61}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\NE` :math:`\hex{62}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\LT` :math:`\hex{63}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\GT` :math:`\hex{64}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\LE` :math:`\hex{65}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\GE` :math:`\hex{66}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\CLZ` :math:`\hex{67}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\CTZ` :math:`\hex{68}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\POPCNT` :math:`\hex{69}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\ADD` :math:`\hex{6A}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\SUB` :math:`\hex{6B}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\MUL` :math:`\hex{6C}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\DIV\K{\_s}` :math:`\hex{6D}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\DIV\K{\_u}` :math:`\hex{6E}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\REM\K{\_s}` :math:`\hex{6F}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\REM\K{\_u}` :math:`\hex{70}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\AND` :math:`\hex{71}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\OR` :math:`\hex{72}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\XOR` :math:`\hex{73}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\SHL` :math:`\hex{74}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\SHR\K{\_s}` :math:`\hex{75}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\SHR\K{\_u}` :math:`\hex{76}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\ROTL` :math:`\hex{77}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\ROTR` :math:`\hex{78}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\CLZ` :math:`\hex{79}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\CTZ` :math:`\hex{7A}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\POPCNT` :math:`\hex{7B}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\ADD` :math:`\hex{7C}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\SUB` :math:`\hex{7D}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\MUL` :math:`\hex{7E}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\DIV\K{\_s}` :math:`\hex{7F}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\DIV\K{\_u}` :math:`\hex{80}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\REM\K{\_s}` :math:`\hex{81}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\REM\K{\_u}` :math:`\hex{82}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\AND` :math:`\hex{83}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\OR` :math:`\hex{84}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\XOR` :math:`\hex{85}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\SHL` :math:`\hex{86}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\SHR\K{\_s}` :math:`\hex{87}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\SHR\K{\_u}` :math:`\hex{88}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\ROTL` :math:`\hex{89}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\ROTR` :math:`\hex{8A}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\ABS` :math:`\hex{8B}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\NEG` :math:`\hex{8C}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CEIL` :math:`\hex{8D}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\FLOOR` :math:`\hex{8E}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\TRUNC` :math:`\hex{8F}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\NEAREST` :math:`\hex{90}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\SQRT` :math:`\hex{91}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\ADD` :math:`\hex{92}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\SUB` :math:`\hex{93}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\MUL` :math:`\hex{94}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\DIV` :math:`\hex{95}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\FMIN` :math:`\hex{96}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\FMAX` :math:`\hex{97}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\COPYSIGN` :math:`\hex{98}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\ABS` :math:`\hex{99}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\NEG` :math:`\hex{9A}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CEIL` :math:`\hex{9B}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\FLOOR` :math:`\hex{9C}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\TRUNC` :math:`\hex{9D}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\NEAREST` :math:`\hex{9E}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\SQRT` :math:`\hex{9F}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\ADD` :math:`\hex{A0}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\SUB` :math:`\hex{A1}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\MUL` :math:`\hex{A2}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\DIV` :math:`\hex{A3}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\FMIN` :math:`\hex{A4}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\FMAX` :math:`\hex{A5}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\COPYSIGN` :math:`\hex{A6}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\WRAP\K{\_}\I64` :math:`\hex{A7}` :math:`[\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_}\F32\K{\_s}` :math:`\hex{A8}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_}\F32\K{\_u}` :math:`\hex{A9}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_}\F64\K{\_s}` :math:`\hex{AA}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_}\F64\K{\_u}` :math:`\hex{AB}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{\_}\I32\K{\_s}` :math:`\hex{AC}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{\_}\I32\K{\_u}` :math:`\hex{AD}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_}\F32\K{\_s}` :math:`\hex{AE}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_}\F32\K{\_u}` :math:`\hex{AF}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_}\F64\K{\_s}` :math:`\hex{B0}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_}\F64\K{\_u}` :math:`\hex{B1}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CONVERT\K{\_}\I32\K{\_s}` :math:`\hex{B2}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CONVERT\K{\_}\I32\K{\_u}` :math:`\hex{B3}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CONVERT\K{\_}\I64\K{\_s}` :math:`\hex{B4}` :math:`[\I64] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CONVERT\K{\_}\I64\K{\_u}` :math:`\hex{B5}` :math:`[\I64] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\DEMOTE\K{\_}\F64` :math:`\hex{B6}` :math:`[\F64] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CONVERT\K{\_}\I32\K{\_s}` :math:`\hex{B7}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CONVERT\K{\_}\I32\K{\_u}` :math:`\hex{B8}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CONVERT\K{\_}\I64\K{\_s}` :math:`\hex{B9}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CONVERT\K{\_}\I64\K{\_u}` :math:`\hex{BA}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\PROMOTE\K{\_}\F32` :math:`\hex{BB}` :math:`[\F32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\REINTERPRET\K{\_}\F32` :math:`\hex{BC}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\REINTERPRET\K{\_}\F64` :math:`\hex{BD}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\REINTERPRET\K{\_}\I32` :math:`\hex{BE}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\REINTERPRET\K{\_}\I64` :math:`\hex{BF}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\EXTEND\K{8\_s}` :math:`\hex{C0}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\EXTEND\K{16\_s}` :math:`\hex{C1}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{8\_s}` :math:`\hex{C2}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{16\_s}` :math:`\hex{C3}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{32\_s}` :math:`\hex{C4}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -(reserved) :math:`\hex{C5}` -(reserved) :math:`\hex{C6}` -(reserved) :math:`\hex{C7}` -(reserved) :math:`\hex{C8}` -(reserved) :math:`\hex{C9}` -(reserved) :math:`\hex{CA}` -(reserved) :math:`\hex{CB}` -(reserved) :math:`\hex{CC}` -(reserved) :math:`\hex{CD}` -(reserved) :math:`\hex{CE}` -(reserved) :math:`\hex{CF}` -:math:`\REFNULL~t` :math:`\hex{D0}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\REFISNULL` :math:`\hex{D1}` :math:`[t] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\REFFUNC~x` :math:`\hex{D2}` :math:`[] \to [\FUNCREF]` :ref:`validation ` :ref:`execution ` -(reserved) :math:`\hex{D3}` -(reserved) :math:`\hex{D4}` -(reserved) :math:`\hex{D5}` -(reserved) :math:`\hex{D6}` -(reserved) :math:`\hex{D7}` -(reserved) :math:`\hex{D8}` -(reserved) :math:`\hex{D9}` -(reserved) :math:`\hex{DA}` -(reserved) :math:`\hex{DB}` -(reserved) :math:`\hex{DC}` -(reserved) :math:`\hex{DD}` -(reserved) :math:`\hex{DE}` -(reserved) :math:`\hex{DF}` -(reserved) :math:`\hex{E0}` -(reserved) :math:`\hex{E1}` -(reserved) :math:`\hex{E2}` -(reserved) :math:`\hex{E3}` -(reserved) :math:`\hex{E4}` -(reserved) :math:`\hex{E5}` -(reserved) :math:`\hex{E6}` -(reserved) :math:`\hex{E7}` -(reserved) :math:`\hex{E8}` -(reserved) :math:`\hex{E9}` -(reserved) :math:`\hex{EA}` -(reserved) :math:`\hex{EB}` -(reserved) :math:`\hex{EC}` -(reserved) :math:`\hex{ED}` -(reserved) :math:`\hex{EE}` -(reserved) :math:`\hex{EF}` -(reserved) :math:`\hex{F0}` -(reserved) :math:`\hex{F1}` -(reserved) :math:`\hex{F2}` -(reserved) :math:`\hex{F3}` -(reserved) :math:`\hex{F4}` -(reserved) :math:`\hex{F5}` -(reserved) :math:`\hex{F6}` -(reserved) :math:`\hex{F7}` -(reserved) :math:`\hex{F8}` -(reserved) :math:`\hex{F9}` -(reserved) :math:`\hex{FA}` -(reserved) :math:`\hex{FB}` -:math:`\I32.\TRUNC\K{\_sat\_}\F32\K{\_s}` :math:`\hex{FC}~\hex{00}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_sat\_}\F32\K{\_u}` :math:`\hex{FC}~\hex{01}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_sat\_}\F64\K{\_s}` :math:`\hex{FC}~\hex{02}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_sat\_}\F64\K{\_u}` :math:`\hex{FC}~\hex{03}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_sat\_}\F32\K{\_s}` :math:`\hex{FC}~\hex{04}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_sat\_}\F32\K{\_u}` :math:`\hex{FC}~\hex{05}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_sat\_}\F64\K{\_s}` :math:`\hex{FC}~\hex{06}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_sat\_}\F64\K{\_u}` :math:`\hex{FC}~\hex{07}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\MEMORYINIT~x` :math:`\hex{FC}~\hex{08}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\DATADROP~x` :math:`\hex{FC}~\hex{09}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` -:math:`\MEMORYCOPY` :math:`\hex{FC}~\hex{0A}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\MEMORYFILL` :math:`\hex{FC}~\hex{0B}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\TABLEINIT~x~y` :math:`\hex{FC}~\hex{0C}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\ELEMDROP~x` :math:`\hex{FC}~\hex{0D}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` -:math:`\TABLECOPY~x~y` :math:`\hex{FC}~\hex{0E}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\TABLEGROW~x` :math:`\hex{FC}~\hex{0F}` :math:`[t~\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\TABLESIZE~x` :math:`\hex{FC}~\hex{10}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\TABLEFILL~x` :math:`\hex{FC}~\hex{11}` :math:`[\I32~t~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD~\memarg` :math:`\hex{FD}~~\hex{00}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{8x8\_s}~\memarg` :math:`\hex{FD}~~\hex{01}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{8x8\_u}~\memarg` :math:`\hex{FD}~~\hex{02}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{16x4\_s}~\memarg` :math:`\hex{FD}~~\hex{03}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{16x4\_u}~\memarg` :math:`\hex{FD}~~\hex{04}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32x2\_s}~\memarg` :math:`\hex{FD}~~\hex{05}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32x2\_u}~\memarg` :math:`\hex{FD}~~\hex{06}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{8\_splat}~\memarg` :math:`\hex{FD}~~\hex{07}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{16\_splat}~\memarg` :math:`\hex{FD}~~\hex{08}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32\_splat}~\memarg` :math:`\hex{FD}~~\hex{09}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{64\_splat}~\memarg` :math:`\hex{FD}~~\hex{0A}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE~\memarg` :math:`\hex{FD}~~\hex{0B}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\VCONST~\i128` :math:`\hex{FD}~~\hex{0C}` :math:`[] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\SHUFFLE~\laneidx^{16}` :math:`\hex{FD}~~\hex{0D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\SWIZZLE` :math:`\hex{FD}~~\hex{0E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\SPLAT` :math:`\hex{FD}~~\hex{0F}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\SPLAT` :math:`\hex{FD}~~\hex{10}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\SPLAT` :math:`\hex{FD}~~\hex{11}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\SPLAT` :math:`\hex{FD}~~\hex{12}` :math:`[\I64] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\SPLAT` :math:`\hex{FD}~~\hex{13}` :math:`[\F32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F64X2.\SPLAT` :math:`\hex{FD}~~\hex{14}` :math:`[\F64] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\EXTRACTLANE\K{\_s}~\laneidx` :math:`\hex{FD}~~\hex{15}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\EXTRACTLANE\K{\_u}~\laneidx` :math:`\hex{FD}~~\hex{16}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{17}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTRACTLANE\K{\_s}~\laneidx` :math:`\hex{FD}~~\hex{18}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTRACTLANE\K{\_u}~\laneidx` :math:`\hex{FD}~~\hex{19}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1A}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1B}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1C}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1D}` :math:`[\V128] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1E}` :math:`[\V128~\I64] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1F}` :math:`[\V128] \to [\F32]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{20}` :math:`[\V128~\F32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F64X2.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{21}` :math:`[\V128] \to [\F64]` :ref:`validation ` :ref:`execution ` -:math:`\F64X2.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{22}` :math:`[\V128~\F64] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\VEQ` :math:`\hex{FD}~~\hex{23}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VNE` :math:`\hex{FD}~~\hex{24}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{25}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{26}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{27}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{28}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{29}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{2A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{2B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{2C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VEQ` :math:`\hex{FD}~~\hex{2D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VNE` :math:`\hex{FD}~~\hex{2E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{2F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{30}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{31}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{32}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{33}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{34}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{35}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{36}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VEQ` :math:`\hex{FD}~~\hex{37}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VNE` :math:`\hex{FD}~~\hex{38}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{39}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{3A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{3B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{3C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{3D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{3E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{3F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{40}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VEQ` :math:`\hex{FD}~~\hex{41}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VNE` :math:`\hex{FD}~~\hex{42}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VLT` :math:`\hex{FD}~~\hex{43}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VGT` :math:`\hex{FD}~~\hex{44}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VLE` :math:`\hex{FD}~~\hex{45}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VGE` :math:`\hex{FD}~~\hex{46}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VEQ` :math:`\hex{FD}~~\hex{47}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VNE` :math:`\hex{FD}~~\hex{48}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VLT` :math:`\hex{FD}~~\hex{49}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VGT` :math:`\hex{FD}~~\hex{4A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VLE` :math:`\hex{FD}~~\hex{4B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VGE` :math:`\hex{FD}~~\hex{4C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VNOT` :math:`\hex{FD}~~\hex{4D}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VAND` :math:`\hex{FD}~~\hex{4E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VANDNOT` :math:`\hex{FD}~~\hex{4F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VOR` :math:`\hex{FD}~~\hex{50}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VXOR` :math:`\hex{FD}~~\hex{51}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\BITSELECT` :math:`\hex{FD}~~\hex{52}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\ANYTRUE` :math:`\hex{FD}~~\hex{53}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{54}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{55}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{56}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{57}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{58}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{59}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5A}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5B}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5C}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{64\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5D}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\VDEMOTE\K{\_f64x2\_zero}` :math:`\hex{FD}~~\hex{5E}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VPROMOTE\K{\_low\_f32x4}` :math:`\hex{FD}~~\hex{5F}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VABS` :math:`\hex{FD}~~\hex{60}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VNEG` :math:`\hex{FD}~~\hex{61}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VPOPCNT` :math:`\hex{FD}~~\hex{62}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\ALLTRUE` :math:`\hex{FD}~~\hex{63}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\BITMASK` :math:`\hex{FD}~~\hex{64}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\NARROW\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{65}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\NARROW\K{\_i16x8\_u}` :math:`\hex{FD}~~\hex{66}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\VCEIL` :math:`\hex{FD}~~\hex{67}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VFLOOR` :math:`\hex{FD}~~\hex{68}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VTRUNC` :math:`\hex{FD}~~\hex{69}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VNEAREST` :math:`\hex{FD}~~\hex{6A}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSHL` :math:`\hex{FD}~~\hex{6B}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{6C}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{6D}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VADD` :math:`\hex{FD}~~\hex{6E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VADD\K{\_sat\_s}` :math:`\hex{FD}~~\hex{6F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VADD\K{\_sat\_u}` :math:`\hex{FD}~~\hex{70}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSUB` :math:`\hex{FD}~~\hex{71}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~\hex{72}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~\hex{73}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VCEIL` :math:`\hex{FD}~~\hex{74}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VFLOOR` :math:`\hex{FD}~~\hex{75}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{76}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{77}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{78}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{79}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VTRUNC` :math:`\hex{FD}~~\hex{7A}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\AVGR\K{\_u}` :math:`\hex{FD}~~\hex{7B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}` :math:`\hex{FD}~~\hex{7C}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}` :math:`\hex{FD}~~\hex{7D}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{7E}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}` :math:`\hex{FD}~~\hex{7F}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VABS` :math:`\hex{FD}~~\hex{80}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VNEG` :math:`\hex{FD}~~\hex{81}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\Q15MULRSAT\K{\_s}` :math:`\hex{FD}~~\hex{82}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\ALLTRUE` :math:`\hex{FD}~~\hex{83}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\BITMASK` :math:`\hex{FD}~~\hex{84}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\NARROW\K{\_i32x4\_s}` :math:`\hex{FD}~~\hex{85}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\NARROW\K{\_i32x4\_u}` :math:`\hex{FD}~~\hex{86}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~\hex{87}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~\hex{88}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~\hex{89}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~\hex{8A}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VSHL` :math:`\hex{FD}~~\hex{8B}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{8C}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{8D}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VADD` :math:`\hex{FD}~~\hex{8E}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VADD\K{\_sat\_s}` :math:`\hex{FD}~~\hex{8F}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VADD\K{\_sat\_u}` :math:`\hex{FD}~~\hex{90}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSUB` :math:`\hex{FD}~~\hex{91}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~\hex{92}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~\hex{93}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VNEAREST` :math:`\hex{FD}~~\hex{94}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMUL` :math:`\hex{FD}~~\hex{95}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{96}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{97}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{98}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{99}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\AVGR\K{\_u}` :math:`\hex{FD}~~\hex{9B}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~\hex{9C}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~\hex{9D}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~\hex{9E}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~\hex{9F}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VABS` :math:`\hex{FD}~~\hex{A0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VNEG` :math:`\hex{FD}~~\hex{A1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\ALLTRUE` :math:`\hex{FD}~~\hex{A3}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\BITMASK` :math:`\hex{FD}~~\hex{A4}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~\hex{A7}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~\hex{A8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~\hex{A9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~\hex{AA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VSHL` :math:`\hex{FD}~~\hex{AB}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{AC}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{AD}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VADD` :math:`\hex{FD}~~\hex{AE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VSUB` :math:`\hex{FD}~~\hex{B1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMUL` :math:`\hex{FD}~~\hex{B5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{B6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{B7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{B8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{B9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\DOT\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{BA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~\hex{BC}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~\hex{BD}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~\hex{BE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~\hex{BF}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VABS` :math:`\hex{FD}~~\hex{C0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VNEG` :math:`\hex{FD}~~\hex{C1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\ALLTRUE` :math:`\hex{FD}~~\hex{C3}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\BITMASK` :math:`\hex{FD}~~\hex{C4}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{C7}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~\hex{C8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{C9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~\hex{CA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VSHL` :math:`\hex{FD}~~\hex{CB}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{CC}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{CD}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VADD` :math:`\hex{FD}~~\hex{CE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VSUB` :math:`\hex{FD}~~\hex{D1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VMUL` :math:`\hex{FD}~~\hex{D5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VEQ` :math:`\hex{FD}~~\hex{D6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VNE` :math:`\hex{FD}~~\hex{D7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{D8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{D9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{DA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{DB}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{DC}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~\hex{DD}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{DE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~\hex{DF}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\VABS` :math:`\hex{FD}~~\hex{E0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VNEG` :math:`\hex{FD}~~\hex{E1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VSQRT` :math:`\hex{FD}~~\hex{E3}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VADD` :math:`\hex{FD}~~\hex{E4}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VSUB` :math:`\hex{FD}~~\hex{E5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VMUL` :math:`\hex{FD}~~\hex{E6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VDIV` :math:`\hex{FD}~~\hex{E7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VMIN` :math:`\hex{FD}~~\hex{E8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VMAX` :math:`\hex{FD}~~\hex{E9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VPMIN` :math:`\hex{FD}~~\hex{EA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VPMAX` :math:`\hex{FD}~~\hex{EB}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VABS` :math:`\hex{FD}~~\hex{EC}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VNEG` :math:`\hex{FD}~~\hex{ED}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VSQRT` :math:`\hex{FD}~~\hex{EF}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VADD` :math:`\hex{FD}~~\hex{F0}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VSUB` :math:`\hex{FD}~~\hex{F1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VMUL` :math:`\hex{FD}~~\hex{F2}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VDIV` :math:`\hex{FD}~~\hex{F3}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VMIN` :math:`\hex{FD}~~\hex{F4}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VMAX` :math:`\hex{FD}~~\hex{F5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VPMIN` :math:`\hex{FD}~~\hex{F6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VPMAX` :math:`\hex{FD}~~\hex{F7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_s}` :math:`\hex{FD}~~\hex{F8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_u}` :math:`\hex{FD}~~\hex{F9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VCONVERT\K{\_i32x4\_s}` :math:`\hex{FD}~~\hex{FA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VCONVERT\K{\_i32x4\_u}` :math:`\hex{FD}~~\hex{FB}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_s\_zero}` :math:`\hex{FD}~~\hex{FC}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}` :math:`\hex{FD}~~\hex{FD}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{FE}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{FF}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -================================================= ==================================== ============================================= ============================================= ================================================================== +================================================= ==================================== ============================================= ============================================= ===================================================================== +Instruction Binary Opcode Type Validation Execution +================================================= ==================================== ============================================= ============================================= ===================================================================== +:math:`\UNREACHABLE` :math:`\hex{00}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\NOP` :math:`\hex{01}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` +:math:`\BLOCK~\X{bt}` :math:`\hex{02}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\LOOP~\X{bt}` :math:`\hex{03}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\IF~\X{bt}` :math:`\hex{04}` :math:`[t_1^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\ELSE` :math:`\hex{05}` +(reserved) :math:`\hex{06}` +(reserved) :math:`\hex{07}` +(reserved) :math:`\hex{08}` +(reserved) :math:`\hex{09}` +(reserved) :math:`\hex{0A}` +:math:`\END` :math:`\hex{0B}` +:math:`\BR~l` :math:`\hex{0C}` :math:`[t_1^\ast~t^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\BRIF~l` :math:`\hex{0D}` :math:`[t^\ast~\I32] \to [t^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\BRTABLE~l^\ast~l` :math:`\hex{0E}` :math:`[t_1^\ast~t^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\RETURN` :math:`\hex{0F}` :math:`[t_1^\ast~t^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\CALL~x` :math:`\hex{10}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\CALLINDIRECT~x~y` :math:`\hex{11}` :math:`[t_1^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +(reserved) :math:`\hex{12}` +(reserved) :math:`\hex{13}` +(reserved) :math:`\hex{14}` +(reserved) :math:`\hex{15}` +(reserved) :math:`\hex{16}` +(reserved) :math:`\hex{17}` +(reserved) :math:`\hex{18}` +(reserved) :math:`\hex{19}` +:math:`\DROP` :math:`\hex{1A}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` +:math:`\SELECT` :math:`\hex{1B}` :math:`[t~t~\I32] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\SELECT~t` :math:`\hex{1C}` :math:`[t~t~\I32] \to [t]` :ref:`validation ` :ref:`execution ` +(reserved) :math:`\hex{1D}` +(reserved) :math:`\hex{1E}` +(reserved) :math:`\hex{1F}` +:math:`\LOCALGET~x` :math:`\hex{20}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\LOCALSET~x` :math:`\hex{21}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` +:math:`\LOCALTEE~x` :math:`\hex{22}` :math:`[t] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\GLOBALGET~x` :math:`\hex{23}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\GLOBALSET~x` :math:`\hex{24}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` +:math:`\TABLEGET~x` :math:`\hex{25}` :math:`[\I32] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\TABLESET~x` :math:`\hex{26}` :math:`[\I32~t] \to []` :ref:`validation ` :ref:`execution ` +(reserved) :math:`\hex{27}` +:math:`\I32.\LOAD~\memarg` :math:`\hex{28}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD~\memarg` :math:`\hex{29}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\F32.\LOAD~\memarg` :math:`\hex{2A}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution ` +:math:`\F64.\LOAD~\memarg` :math:`\hex{2B}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\LOAD\K{8\_s}~\memarg` :math:`\hex{2C}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\LOAD\K{8\_u}~\memarg` :math:`\hex{2D}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\LOAD\K{16\_s}~\memarg` :math:`\hex{2E}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\LOAD\K{16\_u}~\memarg` :math:`\hex{2F}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD\K{8\_s}~\memarg` :math:`\hex{30}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD\K{8\_u}~\memarg` :math:`\hex{31}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD\K{16\_s}~\memarg` :math:`\hex{32}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD\K{16\_u}~\memarg` :math:`\hex{33}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD\K{32\_s}~\memarg` :math:`\hex{34}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD\K{32\_u}~\memarg` :math:`\hex{35}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\STORE~\memarg` :math:`\hex{36}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I64.\STORE~\memarg` :math:`\hex{37}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\F32.\STORE~\memarg` :math:`\hex{38}` :math:`[\I32~\F32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\F64.\STORE~\memarg` :math:`\hex{39}` :math:`[\I32~\F64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I32.\STORE\K{8}~\memarg` :math:`\hex{3A}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I32.\STORE\K{16}~\memarg` :math:`\hex{3B}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I64.\STORE\K{8}~\memarg` :math:`\hex{3C}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I64.\STORE\K{16}~\memarg` :math:`\hex{3D}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I64.\STORE\K{32}~\memarg` :math:`\hex{3E}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\MEMORYSIZE` :math:`\hex{3F}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\MEMORYGROW` :math:`\hex{40}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\CONST~\i32` :math:`\hex{41}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\CONST~\i64` :math:`\hex{42}` :math:`[] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\F32.\CONST~\f32` :math:`\hex{43}` :math:`[] \to [\F32]` :ref:`validation ` :ref:`execution ` +:math:`\F64.\CONST~\f64` :math:`\hex{44}` :math:`[] \to [\F64]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\EQZ` :math:`\hex{45}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\EQ` :math:`\hex{46}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\NE` :math:`\hex{47}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\LT\K{\_s}` :math:`\hex{48}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\LT\K{\_u}` :math:`\hex{49}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\GT\K{\_s}` :math:`\hex{4A}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\GT\K{\_u}` :math:`\hex{4B}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\LE\K{\_s}` :math:`\hex{4C}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\LE\K{\_u}` :math:`\hex{4D}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\GE\K{\_s}` :math:`\hex{4E}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\GE\K{\_u}` :math:`\hex{4F}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EQZ` :math:`\hex{50}` :math:`[\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EQ` :math:`\hex{51}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\NE` :math:`\hex{52}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\LT\K{\_s}` :math:`\hex{53}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\LT\K{\_u}` :math:`\hex{54}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\GT\K{\_s}` :math:`\hex{55}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\GT\K{\_u}` :math:`\hex{56}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\LE\K{\_s}` :math:`\hex{57}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\LE\K{\_u}` :math:`\hex{58}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\GE\K{\_s}` :math:`\hex{59}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\GE\K{\_u}` :math:`\hex{5A}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\EQ` :math:`\hex{5B}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\NE` :math:`\hex{5C}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\LT` :math:`\hex{5D}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\GT` :math:`\hex{5E}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\LE` :math:`\hex{5F}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` 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` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_}\F32\K{\_u}` :math:`\hex{A9}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_}\F64\K{\_s}` :math:`\hex{AA}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_}\F64\K{\_u}` :math:`\hex{AB}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{\_}\I32\K{\_s}` :math:`\hex{AC}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{\_}\I32\K{\_u}` :math:`\hex{AD}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_}\F32\K{\_s}` :math:`\hex{AE}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_}\F32\K{\_u}` :math:`\hex{AF}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` 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:math:`\hex{B7}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\CONVERT\K{\_}\I32\K{\_u}` :math:`\hex{B8}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\CONVERT\K{\_}\I64\K{\_s}` :math:`\hex{B9}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\CONVERT\K{\_}\I64\K{\_u}` :math:`\hex{BA}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\PROMOTE\K{\_}\F32` :math:`\hex{BB}` :math:`[\F32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\REINTERPRET\K{\_}\F32` :math:`\hex{BC}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\REINTERPRET\K{\_}\F64` :math:`\hex{BD}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\REINTERPRET\K{\_}\I32` :math:`\hex{BE}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\REINTERPRET\K{\_}\I64` :math:`\hex{BF}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\EXTEND\K{8\_s}` :math:`\hex{C0}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\EXTEND\K{16\_s}` :math:`\hex{C1}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{8\_s}` :math:`\hex{C2}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{16\_s}` :math:`\hex{C3}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{32\_s}` :math:`\hex{C4}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +(reserved) :math:`\hex{C5}` +(reserved) :math:`\hex{C6}` +(reserved) :math:`\hex{C7}` +(reserved) :math:`\hex{C8}` +(reserved) :math:`\hex{C9}` +(reserved) :math:`\hex{CA}` +(reserved) :math:`\hex{CB}` +(reserved) :math:`\hex{CC}` +(reserved) :math:`\hex{CD}` +(reserved) :math:`\hex{CE}` +(reserved) :math:`\hex{CF}` +:math:`\REFNULL~t` :math:`\hex{D0}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\REFISNULL` :math:`\hex{D1}` :math:`[t] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\REFFUNC~x` :math:`\hex{D2}` :math:`[] \to [\FUNCREF]` :ref:`validation ` :ref:`execution ` +(reserved) :math:`\hex{D3}` +(reserved) :math:`\hex{D4}` +(reserved) :math:`\hex{D5}` +(reserved) :math:`\hex{D6}` +(reserved) :math:`\hex{D7}` +(reserved) :math:`\hex{D8}` +(reserved) :math:`\hex{D9}` +(reserved) :math:`\hex{DA}` +(reserved) :math:`\hex{DB}` +(reserved) :math:`\hex{DC}` +(reserved) :math:`\hex{DD}` +(reserved) :math:`\hex{DE}` +(reserved) :math:`\hex{DF}` +(reserved) :math:`\hex{E0}` +(reserved) :math:`\hex{E1}` +(reserved) :math:`\hex{E2}` +(reserved) :math:`\hex{E3}` +(reserved) :math:`\hex{E4}` +(reserved) :math:`\hex{E5}` +(reserved) :math:`\hex{E6}` +(reserved) :math:`\hex{E7}` +(reserved) :math:`\hex{E8}` +(reserved) :math:`\hex{E9}` +(reserved) :math:`\hex{EA}` +(reserved) :math:`\hex{EB}` +(reserved) :math:`\hex{EC}` +(reserved) :math:`\hex{ED}` +(reserved) :math:`\hex{EE}` +(reserved) :math:`\hex{EF}` +(reserved) :math:`\hex{F0}` +(reserved) :math:`\hex{F1}` +(reserved) :math:`\hex{F2}` +(reserved) :math:`\hex{F3}` +(reserved) :math:`\hex{F4}` +(reserved) :math:`\hex{F5}` +(reserved) :math:`\hex{F6}` +(reserved) :math:`\hex{F7}` +(reserved) :math:`\hex{F8}` +(reserved) :math:`\hex{F9}` +(reserved) :math:`\hex{FA}` +(reserved) :math:`\hex{FB}` +:math:`\I32.\TRUNC\K{\_sat\_}\F32\K{\_s}` :math:`\hex{FC}~\hex{00}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_sat\_}\F32\K{\_u}` :math:`\hex{FC}~\hex{01}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_sat\_}\F64\K{\_s}` :math:`\hex{FC}~\hex{02}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_sat\_}\F64\K{\_u}` :math:`\hex{FC}~\hex{03}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_sat\_}\F32\K{\_s}` :math:`\hex{FC}~\hex{04}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_sat\_}\F32\K{\_u}` :math:`\hex{FC}~\hex{05}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_sat\_}\F64\K{\_s}` :math:`\hex{FC}~\hex{06}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_sat\_}\F64\K{\_u}` :math:`\hex{FC}~\hex{07}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\MEMORYINIT~x` :math:`\hex{FC}~\hex{08}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\DATADROP~x` :math:`\hex{FC}~\hex{09}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` +:math:`\MEMORYCOPY` :math:`\hex{FC}~\hex{0A}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\MEMORYFILL` :math:`\hex{FC}~\hex{0B}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\TABLEINIT~x~y` :math:`\hex{FC}~\hex{0C}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\ELEMDROP~x` :math:`\hex{FC}~\hex{0D}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` +:math:`\TABLECOPY~x~y` :math:`\hex{FC}~\hex{0E}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\TABLEGROW~x` :math:`\hex{FC}~\hex{0F}` :math:`[t~\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\TABLESIZE~x` :math:`\hex{FC}~\hex{10}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\TABLEFILL~x` :math:`\hex{FC}~\hex{11}` :math:`[\I32~t~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD~\memarg` :math:`\hex{FD}~~\hex{00}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{8x8\_s}~\memarg` :math:`\hex{FD}~~\hex{01}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{8x8\_u}~\memarg` :math:`\hex{FD}~~\hex{02}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{16x4\_s}~\memarg` :math:`\hex{FD}~~\hex{03}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{16x4\_u}~\memarg` :math:`\hex{FD}~~\hex{04}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32x2\_s}~\memarg` :math:`\hex{FD}~~\hex{05}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32x2\_u}~\memarg` :math:`\hex{FD}~~\hex{06}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{8\_splat}~\memarg` :math:`\hex{FD}~~\hex{07}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{16\_splat}~\memarg` :math:`\hex{FD}~~\hex{08}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32\_splat}~\memarg` :math:`\hex{FD}~~\hex{09}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{64\_splat}~\memarg` :math:`\hex{FD}~~\hex{0A}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE~\memarg` :math:`\hex{FD}~~\hex{0B}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\VCONST~\i128` :math:`\hex{FD}~~\hex{0C}` :math:`[] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\SHUFFLE~\laneidx^{16}` :math:`\hex{FD}~~\hex{0D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\SWIZZLE` :math:`\hex{FD}~~\hex{0E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\SPLAT` :math:`\hex{FD}~~\hex{0F}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\SPLAT` :math:`\hex{FD}~~\hex{10}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\SPLAT` :math:`\hex{FD}~~\hex{11}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\SPLAT` :math:`\hex{FD}~~\hex{12}` :math:`[\I64] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\SPLAT` :math:`\hex{FD}~~\hex{13}` :math:`[\F32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F64X2.\SPLAT` :math:`\hex{FD}~~\hex{14}` :math:`[\F64] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\EXTRACTLANE\K{\_s}~\laneidx` :math:`\hex{FD}~~\hex{15}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\EXTRACTLANE\K{\_u}~\laneidx` :math:`\hex{FD}~~\hex{16}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{17}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTRACTLANE\K{\_s}~\laneidx` :math:`\hex{FD}~~\hex{18}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTRACTLANE\K{\_u}~\laneidx` :math:`\hex{FD}~~\hex{19}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1A}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1B}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1C}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1D}` :math:`[\V128] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1E}` :math:`[\V128~\I64] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1F}` :math:`[\V128] \to [\F32]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{20}` :math:`[\V128~\F32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F64X2.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{21}` :math:`[\V128] \to [\F64]` :ref:`validation ` :ref:`execution ` +:math:`\F64X2.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{22}` :math:`[\V128~\F64] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\VEQ` :math:`\hex{FD}~~\hex{23}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VNE` :math:`\hex{FD}~~\hex{24}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{25}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{26}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{27}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{28}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{29}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{2A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{2B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{2C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VEQ` :math:`\hex{FD}~~\hex{2D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VNE` :math:`\hex{FD}~~\hex{2E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{2F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{30}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{31}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{32}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{33}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{34}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{35}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{36}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VEQ` :math:`\hex{FD}~~\hex{37}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VNE` :math:`\hex{FD}~~\hex{38}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{39}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{3A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{3B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{3C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{3D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{3E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{3F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{40}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VEQ` :math:`\hex{FD}~~\hex{41}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VNE` :math:`\hex{FD}~~\hex{42}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VLT` :math:`\hex{FD}~~\hex{43}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VGT` :math:`\hex{FD}~~\hex{44}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VLE` :math:`\hex{FD}~~\hex{45}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VGE` :math:`\hex{FD}~~\hex{46}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VEQ` :math:`\hex{FD}~~\hex{47}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VNE` :math:`\hex{FD}~~\hex{48}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VLT` :math:`\hex{FD}~~\hex{49}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VGT` :math:`\hex{FD}~~\hex{4A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VLE` :math:`\hex{FD}~~\hex{4B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VGE` :math:`\hex{FD}~~\hex{4C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VNOT` :math:`\hex{FD}~~\hex{4D}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VAND` :math:`\hex{FD}~~\hex{4E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VANDNOT` :math:`\hex{FD}~~\hex{4F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VOR` :math:`\hex{FD}~~\hex{50}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VXOR` :math:`\hex{FD}~~\hex{51}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\BITSELECT` :math:`\hex{FD}~~\hex{52}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\ANYTRUE` :math:`\hex{FD}~~\hex{53}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{54}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{55}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{56}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{57}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{58}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{59}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5A}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5B}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5C}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{64\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5D}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\VDEMOTE\K{\_f64x2\_zero}` :math:`\hex{FD}~~\hex{5E}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPROMOTE\K{\_low\_f32x4}` :math:`\hex{FD}~~\hex{5F}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VABS` :math:`\hex{FD}~~\hex{60}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VNEG` :math:`\hex{FD}~~\hex{61}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VPOPCNT` :math:`\hex{FD}~~\hex{62}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\ALLTRUE` :math:`\hex{FD}~~\hex{63}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\BITMASK` :math:`\hex{FD}~~\hex{64}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\NARROW\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{65}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\NARROW\K{\_i16x8\_u}` :math:`\hex{FD}~~\hex{66}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\VCEIL` :math:`\hex{FD}~~\hex{67}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VFLOOR` :math:`\hex{FD}~~\hex{68}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VTRUNC` :math:`\hex{FD}~~\hex{69}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VNEAREST` :math:`\hex{FD}~~\hex{6A}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSHL` :math:`\hex{FD}~~\hex{6B}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{6C}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{6D}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VADD` :math:`\hex{FD}~~\hex{6E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VADD\K{\_sat\_s}` :math:`\hex{FD}~~\hex{6F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VADD\K{\_sat\_u}` :math:`\hex{FD}~~\hex{70}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSUB` :math:`\hex{FD}~~\hex{71}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~\hex{72}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~\hex{73}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VCEIL` :math:`\hex{FD}~~\hex{74}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VFLOOR` :math:`\hex{FD}~~\hex{75}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{76}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{77}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{78}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{79}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VTRUNC` :math:`\hex{FD}~~\hex{7A}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\AVGR\K{\_u}` :math:`\hex{FD}~~\hex{7B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}` :math:`\hex{FD}~~\hex{7C}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}` :math:`\hex{FD}~~\hex{7D}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{7E}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}` :math:`\hex{FD}~~\hex{7F}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VABS` :math:`\hex{FD}~~\hex{80}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VNEG` :math:`\hex{FD}~~\hex{81}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\Q15MULRSAT\K{\_s}` :math:`\hex{FD}~~\hex{82}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\ALLTRUE` :math:`\hex{FD}~~\hex{83}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\BITMASK` :math:`\hex{FD}~~\hex{84}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\NARROW\K{\_i32x4\_s}` :math:`\hex{FD}~~\hex{85}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\NARROW\K{\_i32x4\_u}` :math:`\hex{FD}~~\hex{86}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~\hex{87}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~\hex{88}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~\hex{89}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~\hex{8A}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VSHL` :math:`\hex{FD}~~\hex{8B}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{8C}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{8D}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VADD` :math:`\hex{FD}~~\hex{8E}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VADD\K{\_sat\_s}` :math:`\hex{FD}~~\hex{8F}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VADD\K{\_sat\_u}` :math:`\hex{FD}~~\hex{90}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSUB` :math:`\hex{FD}~~\hex{91}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~\hex{92}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~\hex{93}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VNEAREST` :math:`\hex{FD}~~\hex{94}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMUL` :math:`\hex{FD}~~\hex{95}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{96}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{97}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{98}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{99}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\AVGR\K{\_u}` :math:`\hex{FD}~~\hex{9B}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~\hex{9C}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~\hex{9D}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~\hex{9E}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~\hex{9F}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VABS` :math:`\hex{FD}~~\hex{A0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VNEG` :math:`\hex{FD}~~\hex{A1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\ALLTRUE` :math:`\hex{FD}~~\hex{A3}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\BITMASK` :math:`\hex{FD}~~\hex{A4}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~\hex{A7}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~\hex{A8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~\hex{A9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~\hex{AA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VSHL` :math:`\hex{FD}~~\hex{AB}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{AC}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{AD}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VADD` :math:`\hex{FD}~~\hex{AE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VSUB` :math:`\hex{FD}~~\hex{B1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMUL` :math:`\hex{FD}~~\hex{B5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{B6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{B7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{B8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{B9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\DOT\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{BA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~\hex{BC}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~\hex{BD}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~\hex{BE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~\hex{BF}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VABS` :math:`\hex{FD}~~\hex{C0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VNEG` :math:`\hex{FD}~~\hex{C1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\ALLTRUE` :math:`\hex{FD}~~\hex{C3}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\BITMASK` :math:`\hex{FD}~~\hex{C4}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{C7}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~\hex{C8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{C9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~\hex{CA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VSHL` :math:`\hex{FD}~~\hex{CB}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{CC}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{CD}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VADD` :math:`\hex{FD}~~\hex{CE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VSUB` :math:`\hex{FD}~~\hex{D1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VMUL` :math:`\hex{FD}~~\hex{D5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VEQ` :math:`\hex{FD}~~\hex{D6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VNE` :math:`\hex{FD}~~\hex{D7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{D8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{D9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{DA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{DB}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{DC}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~\hex{DD}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{DE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~\hex{DF}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\VABS` :math:`\hex{FD}~~\hex{E0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VNEG` :math:`\hex{FD}~~\hex{E1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VSQRT` :math:`\hex{FD}~~\hex{E3}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VADD` :math:`\hex{FD}~~\hex{E4}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VSUB` :math:`\hex{FD}~~\hex{E5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VMUL` :math:`\hex{FD}~~\hex{E6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VDIV` :math:`\hex{FD}~~\hex{E7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VMIN` :math:`\hex{FD}~~\hex{E8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VMAX` :math:`\hex{FD}~~\hex{E9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VPMIN` :math:`\hex{FD}~~\hex{EA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VPMAX` :math:`\hex{FD}~~\hex{EB}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VABS` :math:`\hex{FD}~~\hex{EC}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VNEG` :math:`\hex{FD}~~\hex{ED}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VSQRT` :math:`\hex{FD}~~\hex{EF}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VADD` :math:`\hex{FD}~~\hex{F0}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VSUB` :math:`\hex{FD}~~\hex{F1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VMUL` :math:`\hex{FD}~~\hex{F2}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VDIV` :math:`\hex{FD}~~\hex{F3}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VMIN` :math:`\hex{FD}~~\hex{F4}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VMAX` :math:`\hex{FD}~~\hex{F5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPMIN` :math:`\hex{FD}~~\hex{F6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPMAX` :math:`\hex{FD}~~\hex{F7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_s}` :math:`\hex{FD}~~\hex{F8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_u}` :math:`\hex{FD}~~\hex{F9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VCONVERT\K{\_i32x4\_s}` :math:`\hex{FD}~~\hex{FA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VCONVERT\K{\_i32x4\_u}` :math:`\hex{FD}~~\hex{FB}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_s\_zero}` :math:`\hex{FD}~~\hex{FC}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}` :math:`\hex{FD}~~\hex{FD}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{FE}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{FF}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\RSWIZZLE` :math:`\hex{FD}~~\hex{80}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RTRUNC\K{\_f32x4\_s}` :math:`\hex{FD}~~\hex{81}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RTRUNC\K{\_f32x4\_u}` :math:`\hex{FD}~~\hex{82}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RTRUNC\K{\_f64x2\_s}` :math:`\hex{FD}~~\hex{83}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RTRUNC\K{\_f64x2\_u}` :math:`\hex{FD}~~\hex{84}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\RMADD` :math:`\hex{FD}~~\hex{85}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\RNMADD` :math:`\hex{FD}~~\hex{86}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\RMADD` :math:`\hex{FD}~~\hex{87}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\RNMADD` :math:`\hex{FD}~~\hex{88}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\RLANESELECT` :math:`\hex{FD}~~\hex{89}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\RLANESELECT` :math:`\hex{FD}~~\hex{8A}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RLANESELECT` :math:`\hex{FD}~~\hex{8B}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\RLANESELECT` :math:`\hex{FD}~~\hex{8C}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\RMIN` :math:`\hex{FD}~~\hex{8D}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\RMAX` :math:`\hex{FD}~~\hex{8E}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\RMIN` :math:`\hex{FD}~~\hex{8F}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\RMAX` :math:`\hex{FD}~~\hex{90}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\RQ15MULRS` :math:`\hex{FD}~~\hex{91}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\RDOT\K{\_i8x16\_i7x16\_s}` :math:`\hex{FD}~~\hex{92}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RDOT\K{\_i8x16\_i7x16\_add\_s}` :math:`\hex{FD}~~\hex{93}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +================================================= ==================================== ============================================= ============================================= ===================================================================== .. note:: Multi-byte opcodes are given with the shortest possible encoding in the table. diff --git a/document/core/exec/instructions.rst b/document/core/exec/instructions.rst index 5989a1fdd..51728124a 100644 --- a/document/core/exec/instructions.rst +++ b/document/core/exec/instructions.rst @@ -405,7 +405,7 @@ Most vector instructions are defined in terms of generic numeric operators appli \end{array} -.. _exec-vec-relaxed-swizzle: +.. _exec-vec-rswizzle: :math:`\K{i8x16.}\RSWIZZLE` ........................... @@ -414,26 +414,20 @@ Most vector instructions are defined in terms of generic numeric operators appli 2. Pop the value :math:`\V128.\VCONST~c_2` from the stack. -3. Let :math:`i^\ast` be the sequence :math:`\lanes_{i8x16}(c_2)`. - -4. Pop the value :math:`\V128.\VCONST~c_1` from the stack. - -5. Let :math:`j^\ast` be the sequence :math:`\lanes_{i8x16}(c_1)`. +3. Pop the value :math:`\V128.\VCONST~c_1` from the stack. -6. Let :math:`c'` be the result of computing :math:`\RSWIZZLE(j^\ast, i^\ast)`. +4. Let :math:`c'` be the result of computing :math:`\lanes^{-1}_{\I8X16}(\rswizzle(\lanes_{i8x16}(c_1), \lanes_{i8x16}(c_2)))`. -7. Push the value :math:`\V128.\VCONST~c'` onto the stack. +5. Push the value :math:`\V128.\VCONST~c'` onto the stack. .. math:: \begin{array}{l} \begin{array}{lcl@{\qquad}l} - (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i8x16}\K{.}\RSWIZZLE &\stepto& (\V128\K{.}\VCONST~c') + (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i8x16}\K{.}\rswizzle &\stepto& (\V128\K{.}\VCONST~c') \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} - (\iff & i^\ast = \lanes_{i8x16}(c_2) \\ - \wedge & c^\ast = \lanes_{i8x16}(c_1)~0^{240} \\ - \wedge & c' = \lanes^{-1}_{i8x16}(c^\ast[ i^\ast[0] ] \dots c^\ast[ i^\ast[15] ])) + (\iff & c' = \lanes^{-1}_{i8x16}(\rswizzle(\lanes_{i8x16}(c_1), \lanes_{i8x16}(c_2))) \end{array} \end{array} @@ -618,6 +612,8 @@ Most vector instructions are defined in terms of generic numeric operators appli \end{array} +.. _exec-vternop: + :math:`\shape\K{.}\vternop` ........................... @@ -634,9 +630,45 @@ Most vector instructions are defined in terms of generic numeric operators appli 6. Push the value :math:`\V128.\VCONST~c` to the stack. .. math:: + \begin{array}{l} \begin{array}{lcl@{\qquad}l} - (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\V128\K{.}\vternop &\stepto& (\V128\K{.}\VCONST~c) - & (\iff c = \vternop_{\shape}(c_1, c_2, c_3)) \\ + (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\V128\K{.}\vternop &\stepto& (\V128\K{.}\VCONST~c) & + \end{array} + \\ \qquad + \begin{array}[t]{@{}r@{~}l@{}} + (\iff c = \vternop_{\shape}(c_1, c_2, c_3)) \\ + \end{array} + \end{array} + + +.. _exec-rlaneselect: + +:math:`t\K{x}N\K{.}\RLANESELECT` +................................ + +1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. + +2. Pop the value :math:`\V128.\VCONST~c_3` from the stack. + +3. Pop the value :math:`\V128.\VCONST~c_2` from the stack. + +4. Pop the value :math:`\V128.\VCONST~c_1` from the stack. + +5. Let :math:`B` be the :ref:`bit width ` :math:`|t|` of :ref:`value type ` :math:`t`. + +6. Let :math:`c` be the result of computing :math:`\lanes^{-1}_{t\K{x}N}(\rlaneselect_{B}(\lanes_{t\K{x}N}(c_1), \lanes_{t\K{x}N}(c_2), \lanes_{t\K{x}N}(c_3)))`. + +7. Push the value :math:`\V128.\VCONST~c` to the stack. + +.. math:: + \begin{array}{l} + \begin{array}{lcl@{\qquad}l} + (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\V128\K{.}\RLANESELECT &\stepto& (\V128\K{.}\VCONST~c) & \\ + \end{array} + \\ \qquad + \begin{array}[t]{@{}r@{~}l@{}} + (\iff c = \lanes^{-1}_{t\K{x}N}(\rlaneselect_{|t|}(\lanes_{t\K{x}N}(c_1), \lanes_{t\K{x}N}(c_2), \lanes_{t\K{x}N}(c_3)))) \\ + \end{array} \end{array} @@ -929,7 +961,7 @@ where: :math:`\K{i16x8.}\DOT\K{\_i8x16\_i7x16\_s}` ................................................... -1. Assert: due to :ref:`validation `, two values of :ref:`value type ` |V128| are on the top of the stack. +1. Assert: due to :ref:`validation `, two values of :ref:`value type ` |V128| are on the top of the stack. 2. Pop the value :math:`\V128.\VCONST~c_2` from the stack. @@ -960,7 +992,7 @@ where: :math:`\K{i32x4.}\DOT\K{\_i8x16\_i7x16\_add\_s}` ........................................................ -1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. +1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. 2. Pop the value :math:`\V128.\VCONST~c_3` from the stack. diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index c327cc8cc..24d552229 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -1976,11 +1976,6 @@ Conversions Relaxed operators ~~~~~~~~~~~~~~~~~ -.. todo:: - This paragraph should go to the top of this document, but for ease of - reading, put it together with the description of all the relaxed operations - here. - The result of *relaxed* operators are *host-dependent*, because the set of possible results may depend on properties of the host environment (such as hardware). Technically, each such operator produces a fixed-size *list of sets* @@ -1993,29 +1988,39 @@ each environment globally chooses a fixed projection for each operator. one particular choice by the execution environment. The fixed operation itself can still be non-deterministic or partial. -.. todo:: - Below is a draft of concrete definitions for relaxed-simd operations. The - text description is an informal description of the instructions and are not - the final text. +.. _op-frmadd: -.. _op-relaxed_madd: -.. _op-relaxed_nmadd: +:math:`\frmadd_N(z_1, z_2, z_3)` +................................ -Relaxed Multiply Add (madd) and Relaxed Negative Multiply Add (nmadd) -allows for fused or unfused results. :math:`fma` is defined by |IEEE754|_ -(Section 5.4.1) as *fusedMultiplyAdd*. +Relaxed Multiply Add (madd) allows for fused or unfused results. :math:`fma` is +defined by |IEEE754|_ (Section 5.4.1) as *fusedMultiplyAdd*. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & \rmadd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), fma_N(z_1, z_2, z_3) ] \\ - & \rmadd_N(z_1, z_2, z_3) &=& \fadd_N(\fmul_N(z_1, z_2), z_3) \\ - \\ - & \rnmadd_N(z_1, z_2, z_3) &=& \rmadd_N(-z_1, z_2, z_3) \\ + \EXPROFDET & \frmadd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), fma_N(z_1, z_2, z_3) ] \\ + & \frmadd_N(z_1, z_2, z_3) &=& \fadd_N(\fmul_N(z_1, z_2), z_3) \\ + \end{array} + + +.. _op-frnmadd: + +:math:`\frnmadd_N(z_1, z_2, z_3)` +................................. + +Relaxed Negative Multiply Add (nmadd) allows for fused or unfused results. + +.. math:: + \begin{array}{@{}llcll} + & \frnmadd_N(z_1, z_2, z_3) &=& \frmadd_N(-z_1, z_2, z_3) \\ \end{array} -.. _op-relaxed_swizzle: +.. _op-rswizzle: + +:math:`\rswizzle(a^n, s^n)` +........................... Relaxed swizzle lane is a helper for relaxed swizzle. Result is deterministic if the signed interpretation of the index is less than 16 (including negative). @@ -2033,26 +2038,45 @@ if the signed interpretation of the index is less than 16 (including negative). \end{array} -.. _op-relaxed_trunc: +.. _op-rtrunc: +.. _op-rtrunc_u: + +:math:`\rtrunc^u_{M,N}(z)` +.......................... Relaxed truncate converts float to int, NaN and out of range values are hardware dependent. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & relaxed\_trunc^s_{M,N}(\pm \NAN(n)) &=& [ 0, -2^{N-1} ] \\ - \EXPROFDET & relaxed\_trunc^s_{M,N}(\pm q) &=& \truncs_{M,N}(\pm q) & (\iff -2^{N-1} - 1 < \trunc(\pm q) < 2^{N-1}) \\ - \EXPROFDET & relaxed\_trunc^s_{M,N}(\pm p) &=& [ \truncsats_{M,N}(\pm p), -2^{N-1} ] & (\otherwise) \\ - & \rtrunc^s_{M,N}(\pm p) &=& \truncsats_{M,N}(\pm p) & (\otherwise) \\ - \\ - \EXPROFDET & relaxed\_trunc^u_{M,N}(\pm \NAN(n)) &=& [ 0, 2^{N}-1 ] \\ - \EXPROFDET & relaxed\_trunc^u_{M,N}(\pm q) &=& \truncu_{M,N}(\pm q) & (\iff -1 < \trunc(\pm q) < 2^N) \\ - \EXPROFDET & relaxed\_trunc^u_{M,N}(\pm p) &=& [ \truncsatu_{M,N}(\pm p), 2^{N}-1 ] & (\otherwise) \\ + \EXPROFDET & \rtrunc^u_{M,N}(\pm \NAN(n)) &=& [ 0, 2^{N}-1 ] \\ + \EXPROFDET & \rtrunc^u_{M,N}(\pm q) &=& \truncu_{M,N}(\pm q) & (\iff -1 < \trunc(\pm q) < 2^N) \\ + \EXPROFDET & \rtrunc^u_{M,N}(\pm p) &=& [ \truncsatu_{M,N}(\pm p), 2^{N}-1 ] & (\otherwise) \\ & \rtrunc^u_{M,N}(\pm p) &=& \truncsatu_{M,N}(\pm p) & (\otherwise) \\ \end{array} -.. _op-relaxed_laneselect: +.. _op-rtrunc_s: + +:math:`\rtrunc^s_{M,N}(z)` +.......................... + +Relaxed truncate converts float to int, NaN and out of range values are +hardware dependent. + +.. math:: + \begin{array}{@{}llcll} + \EXPROFDET & \rtrunc^s_{M,N}(\pm \NAN(n)) &=& [ 0, -2^{N-1} ] \\ + \EXPROFDET & \rtrunc^s_{M,N}(\pm q) &=& \truncs_{M,N}(\pm q) & (\iff -2^{N-1} - 1 < \trunc(\pm q) < 2^{N-1}) \\ + \EXPROFDET & \rtrunc^s_{M,N}(\pm p) &=& [ \truncsats_{M,N}(\pm p), -2^{N-1} ] & (\otherwise) \\ + & \rtrunc^s_{M,N}(\pm p) &=& \truncsats_{M,N}(\pm p) & (\otherwise) \\ + \end{array} + + +.. _op-rlaneselect: + +:math:`\rlaneselect_B(a^n, b^n, c^n)` +..................................... Relaxed lane select is deterministic where all bits are set or unset in the mask. Otherwise depending on hardware, either only the top bit is examined, or @@ -2060,47 +2084,74 @@ all bits are examined (becomes a bitselect). .. math:: \begin{array}{@{}llcll} - & relaxed\_laneselect\_lane_N(i_1, i_2, 2^N-1) &=& i_1 \\ - & relaxed\_laneselect\_lane_N(i_1, i_2, 0) &=& i_2 \\ - \EXPROFDET & relaxed\_laneselect\_lane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_1 ] & (\iff \signed_N(i_3) < 0) \\ - \EXPROFDET & relaxed\_laneselect\_lane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_2 ] & (\otherwise) \\ - & relaxed\_laneselect\_lane_N(i_1, i_2, i_3) &=& \ibitselect_N(i_1, i_2, i_3) & (\otherwise) \\ + & relaxed\_lane_N(i_1, i_2, 2^N-1) &=& i_1 \\ + & relaxed\_lane_N(i_1, i_2, 0) &=& i_2 \\ + \EXPROFDET & relaxed\_lane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_1 ] & (\iff \signed_N(i_3) < 0) \\ + \EXPROFDET & relaxed\_lane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_2 ] & (\otherwise) \\ + & relaxed\_lane_N(i_1, i_2, i_3) &=& \ibitselect_N(i_1, i_2, i_3) & (\otherwise) \\ \\ - & \rlaneselect_W(a^n, b^n, c^n) &=& rll_0 \dots rll_{n-1} \\ - & \qquad \where rll_i &=& relaxed\_laneselect\_lane_W(a^n[i], b^n[i], c^n[i]) \\ + & \rlaneselect_B(a^n, b^n, c^n) &=& rll_0 \dots rll_{n-1} \\ + & \qquad \where rll_i &=& relaxed\_lane_B(a^n[i], b^n[i], c^n[i]) \\ + \end{array} + + +.. _op-frmin: + +:math:`\frmin_N(z_1, z_2)` +.......................... + +Relaxed min differs from min when inputs are NaNs or different +signs of 0. It allows for implementation to return the first or second input +when either input is a NaN. + +.. math:: + \begin{array}{@{}llcll} + \EXPROFDET & \frmin_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ + \EXPROFDET & \frmin_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ + \EXPROFDET & \frmin_N(\pm 0, \mp 0) &=& [ -0, \pm 0, \mp 0, -0 ] \\ + & \frmin_N(z_1, z_2) &=& \fmin_N(z_1, z_2) & (\otherwise) \\ \end{array} -.. _op-relaxed_min: -.. _op-relaxed_max: +.. _op-frmax: + +:math:`\frmax_N(z_1, z_2)` +.......................... -Relaxed min and max differs from min and max when inputs are NaNs or different +Relaxed max differs from max when inputs are NaNs or different signs of 0. It allows for implementation to return the first or second input when either input is a NaN. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & relaxed\_min_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ - \EXPROFDET & relaxed\_min_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ - \EXPROFDET & relaxed\_min_N(\pm 0, \mp 0) &=& [ -0, \pm 0, \mp 0, -0 ] \\ - & \rmin(z_1, z_2) &=& \fmin_N(z_1, z_2) & (\otherwise) \\ + \EXPROFDET & \frmax_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ + \EXPROFDET & \frmax_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ + \EXPROFDET & \frmax_N(\pm 0, \mp 0) &=& [ +0, \pm 0, \mp 0, +0 ] \\ + & \frmax_N(z_1, z_2) &=& \fmax_N(z_1, z_2) & (\otherwise) \\ \end{array} + +.. _op-irq15mulr_s: + +:math:`\irq15mulrs_N(i_1, i_2)` +............................... + .. math:: \begin{array}{@{}llcll} - \EXPROFDET & relaxed\_max_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ - \EXPROFDET & relaxed\_max_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ - \EXPROFDET & relaxed\_max_N(\pm 0, \mp 0) &=& [ +0, \pm 0, \mp 0, +0 ] \\ - & \rmax(z_1, z_2) &=& \fmax_N(z_1, z_2) & (\otherwise) \\ + \EXPROFDET & \irq15mulrs_N(i_1, i_2) &=& [ \sats_N(i), i \mod 2^N ] & (\iff i = \ishrs_N(i_1 \cdot i_2 + 2^{14}, 15)) \\ + & \irq15mulrs_N(i_1, i_2) &=& \iq15mulrsats(i_1, i_2) \end{array} -.. _op-relaxed_idotmul: +.. _op-ridotmul: + +:math:`\ridotmul_{M,N}(i_1, i_2)` +................................. Relaxed integer dot product differs from integer dot product when the elements of the input have top bit set. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & \ridotmul{M,N}(i_1, i_2) &=& [ \imul_N(\signed_M(i_1), i_2), \imul_N(\signed_M(i_1), \signed_M(i_2)) ] \\ - & \ridotmul{M,N}(i_1, i_2) &=& \imul_N(\extends_{M,N}(i_1), \extends_{M,N}(i_2)) \\ + \EXPROFDET & \ridotmul_{M,N}(i_1, i_2) &=& [ \imul_N(\signed_M(i_1), i_2), \imul_N(\signed_M(i_1), \signed_M(i_2)) ] \\ + & \ridotmul_{M,N}(i_1, i_2) &=& \imul_N(\extends_{M,N}(i_1), \extends_{M,N}(i_2)) \\ \end{array} diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst index 63aaaa44b..49fd639a7 100644 --- a/document/core/syntax/instructions.rst +++ b/document/core/syntax/instructions.rst @@ -276,14 +276,14 @@ Vector instructions (also known as *SIMD* instructions, *single instruction mult \K{f32x4.}\VDEMOTE\K{\_f64x2\_zero} \\&&|& \K{f64x2.}\VCONVERT\K{\_low\_i32x4\_}\sx ~|~ \K{f64x2.}\VPROMOTE\K{\_low\_f32x4} \\ - & &|& \K{i8x16.relaxed\_swizzle} \\ - & &|& \K{i32x4.}\RVTRUNC\K{\_f32x4\_}\sx \\ + & &|& \K{i8x16.}\RSWIZZLE \\ + & &|& \K{i16x8.}\RQ15MULRS \\ + & &|& \K{i32x4.}\RTRUNC\K{\_f32x4\_}\sx \\ + & &|& \K{i16x8.}\RDOT\K{\_i8x16\_i7x16\_s} \\ + & &|& \K{i32x4.}\RDOT\K{\_i8x16\_i7x16\_add\_s} \\ + & &|& \ishape\K{.}\RLANESELECT \\ & &|& \fshape\K{.}\rvfternop \\ - & &|& \ishape\K{.relaxed\_laneselect} \\ & &|& \fshape\K{.}\rvfbinop \\ - & &|& \K{i16x8.}\RQ15MULRS \\ - & &|& \K{i16x8.relaxed\_dot\_i8x16\_i7x16\_s} \\ - & &|& \K{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s} \\ & &|& \dots \\ \end{array} @@ -423,8 +423,7 @@ Occasionally, it is convenient to group operators together according to the foll \RQ15MULRS\K{\_s} \\ \production{ternary operator} & \vternop &::=& \vvternop ~|~ - \rvfternop \\&&|& - \K{relaxed\_laneselect} \\ + \rvfternop \\ \production{test operator} & \vtestop &::=& \vitestop \\ \production{relational operator} & \vrelop &::=& @@ -435,7 +434,7 @@ Occasionally, it is convenient to group operators together according to the foll \VCONVERT ~|~ \VDEMOTE ~|~ \VPROMOTE ~|~ - \RVTRUNC \\ + \RTRUNC \\ \end{array} diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 31383012d..7fa5ff0f2 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -499,9 +499,15 @@ .. |EXTADDPAIRWISE| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{extadd\_pairwise}} .. |VDEMOTE| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{demote}} .. |VPROMOTE| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{promote}} +.. |RMADD| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_madd}} +.. |RNMADD| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_nmadd}} .. |RSWIZZLE| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_swizzle}} +.. |RLANESELECT| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_laneselect}} +.. |RMIN| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_min}} +.. |RMAX| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_max}} .. |RQ15MULRS| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_q15mulr\_s}} -.. |RVTRUNC| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_trunc}} +.. |RTRUNC| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_trunc}} +.. |RDOT| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{\_dot}} .. Instructions, non-terminals @@ -1197,14 +1203,15 @@ .. |narrowu| mathdef:: \xref{exec/numerics}{op-narrow_u}{\F{narrow}^{\K{u}}} .. |narrows| mathdef:: \xref{exec/numerics}{op-narrow_s}{\F{narrow}^{\K{s}}} -.. |rmadd| mathdef:: \xref{exec/numerics}{op-relaxed_madd}{\F{relaxed\_madd}} -.. |rnmadd| mathdef:: \xref{exec/numerics}{op-relaxed_nmadd}{\F{relaxed\_nmadd}} -.. |rswizzle| mathdef:: \xref{exec/numerics}{op-relaxed_swizzle}{\F{relaxed\_swizzle}} -.. |rtrunc| mathdef:: \xref{exec/numerics}{op-relaxed_trunc}{\F{relaxed\_trunc}} -.. |rlaneselect| mathdef:: \xref{exec/numerics}{op-relaxed_laneselect}{\F{relaxed\_laneselect}} -.. |rmin| mathdef:: \xref{exec/numerics}{op-relaxed_min}{\F{relaxed\_min}} -.. |rmax| mathdef:: \xref{exec/numerics}{op-relaxed_max}{\F{relaxed\_max}} -.. |ridotmul| mathdef:: \xref{exec/numerics}{op-relaxed_idotmul}{\F{relaxed\_dot\_mul}} +.. |frmadd| mathdef:: \xref{exec/numerics}{op-frmaddd}{\F{frelaxed\_madd}} +.. |frnmadd| mathdef:: \xref{exec/numerics}{op-frnmadd}{\F{frelaxed\_nmadd}} +.. |rswizzle| mathdef:: \xref{exec/numerics}{op-rswizzle}{\F{relaxed\_swizzle}} +.. |rtrunc| mathdef:: \xref{exec/numerics}{op-rtrunc}{\F{relaxed\_trunc}} +.. |rlaneselect| mathdef:: \xref{exec/numerics}{op-rlaneselect}{\F{relaxed\_laneselect}} +.. |frmin| mathdef:: \xref{exec/numerics}{op-frmin}{\F{frelaxed\_min}} +.. |frmax| mathdef:: \xref{exec/numerics}{op-frmax}{\F{frelaxed\_max}} +.. |irq15mulrs| mathdef:: \xref{exec/numerics}{op-irq15mulr_s}{\F{irelaxed\_q15mulr\_s}} +.. |ridotmul| mathdef:: \xref{exec/numerics}{op-ridotmul}{\F{relaxed\_dot\_mul}} .. Numerics, meta functions diff --git a/document/core/valid/instructions.rst b/document/core/valid/instructions.rst index 6d2783e73..33222a3b8 100644 --- a/document/core/valid/instructions.rst +++ b/document/core/valid/instructions.rst @@ -487,6 +487,20 @@ The following auxiliary function denotes the number of lanes in a vector shape, } +.. _valid-rlaneselect: + +:math:`\shape\K{.}\RLANESELECT` +............................... + +* The instruction is valid with type :math:`[\V128~\V128~\V128] \to [\V128]`. + +.. math:: + \frac{ + }{ + C \vdashinstr \shape\K{.}\vternop : [\V128~\V128~\V128] \to [\V128] + } + + .. _valid-vrelop: :math:`\shape\K{.}\vrelop` @@ -584,6 +598,9 @@ The following auxiliary function denotes the number of lanes in a vector shape, C \vdashinstr \ishape_1\K{.}\DOT\K{\_}\ishape_2\K{\_s} : [\V128~\V128] \to [\V128] } + +.. _valid-vec-rdot: + :math:`\ishape_1\K{.}\DOT\K{\_}\ishape_2\_\K{i7x16\_s}` ....................................................... From 2a8208ec72f5c5344c3453111571dcdeff7e7573 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 25 Jan 2023 23:35:00 +0000 Subject: [PATCH 076/117] Fix binary and text --- document/core/binary/instructions.rst | 36 ++++++++++++------------- document/core/exec/instructions.rst | 8 +++--- document/core/text/instructions.rst | 38 +++++++++++++-------------- document/core/util/macros.def | 2 +- 4 files changed, 42 insertions(+), 42 deletions(-) diff --git a/document/core/binary/instructions.rst b/document/core/binary/instructions.rst index f6ea313e8..9c9bd18b8 100644 --- a/document/core/binary/instructions.rst +++ b/document/core/binary/instructions.rst @@ -842,25 +842,25 @@ All other vector instructions are plain opcodes without any immediates. \begin{array}{llclll} \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|& \hex{FD}~~256{:}\Bu32 &\Rightarrow& \I16X8.\RSWIZZLE \\ &&|& - \hex{FD}~~257{:}\Bu32 &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_s} \\ &&|& - \hex{FD}~~258{:}\Bu32 &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_u} \\ &&|& - \hex{FD}~~259{:}\Bu32 &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_s\_zero} \\ &&|& - \hex{FD}~~260{:}\Bu32 &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_u\_zero} \\ &&|& - \hex{FD}~~261{:}\Bu32 &\Rightarrow& \F32X4.\K{relaxed\_madd} \\ &&|& - \hex{FD}~~262{:}\Bu32 &\Rightarrow& \F32X4.\K{relaxed\_nmadd} \\ &&|& - \hex{FD}~~263{:}\Bu32 &\Rightarrow& \F64X2.\K{relaxed\_madd} \\ &&|& - \hex{FD}~~264{:}\Bu32 &\Rightarrow& \F64X2.\K{relaxed\_nmadd} \\ &&|& - \hex{FD}~~265{:}\Bu32 &\Rightarrow& \I8X16.\K{relaxed\_laneselect} \\ &&|& - \hex{FD}~~266{:}\Bu32 &\Rightarrow& \I16X8.\K{relaxed\_laneselect} \\ &&|& - \hex{FD}~~267{:}\Bu32 &\Rightarrow& \I32X4.\K{relaxed\_laneselect} \\ &&|& - \hex{FD}~~268{:}\Bu32 &\Rightarrow& \I64X2.\K{relaxed\_laneselect} \\ &&|& - \hex{FD}~~269{:}\Bu32 &\Rightarrow& \F32X4.\K{relaxed\_min} \\ &&|& - \hex{FD}~~270{:}\Bu32 &\Rightarrow& \F32X4.\K{relaxed\_max} \\ &&|& - \hex{FD}~~271{:}\Bu32 &\Rightarrow& \F64X2.\K{relaxed\_min} \\ &&|& - \hex{FD}~~272{:}\Bu32 &\Rightarrow& \F64X2.\K{relaxed\_max} \\ &&|& + \hex{FD}~~257{:}\Bu32 &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_s} \\ &&|& + \hex{FD}~~258{:}\Bu32 &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_u} \\ &&|& + \hex{FD}~~259{:}\Bu32 &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_s\_zero} \\ &&|& + \hex{FD}~~260{:}\Bu32 &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_u\_zero} \\ &&|& + \hex{FD}~~261{:}\Bu32 &\Rightarrow& \F32X4.\RMADD \\ &&|& + \hex{FD}~~262{:}\Bu32 &\Rightarrow& \F32X4.\RNMADD \\ &&|& + \hex{FD}~~263{:}\Bu32 &\Rightarrow& \F64X2.\RMADD \\ &&|& + \hex{FD}~~264{:}\Bu32 &\Rightarrow& \F64X2.\RNMADD \\ &&|& + \hex{FD}~~265{:}\Bu32 &\Rightarrow& \I8X16.\RLANESELECT \\ &&|& + \hex{FD}~~266{:}\Bu32 &\Rightarrow& \I16X8.\RLANESELECT \\ &&|& + \hex{FD}~~267{:}\Bu32 &\Rightarrow& \I32X4.\RLANESELECT \\ &&|& + \hex{FD}~~268{:}\Bu32 &\Rightarrow& \I64X2.\RLANESELECT \\ &&|& + \hex{FD}~~269{:}\Bu32 &\Rightarrow& \F32X4.\RMIN \\ &&|& + \hex{FD}~~270{:}\Bu32 &\Rightarrow& \F32X4.\RMAX \\ &&|& + \hex{FD}~~271{:}\Bu32 &\Rightarrow& \F64X2.\RMIN \\ &&|& + \hex{FD}~~272{:}\Bu32 &\Rightarrow& \F64X2.\RMAX \\ &&|& \hex{FD}~~273{:}\Bu32 &\Rightarrow& \I16X8.\RQ15MULRS \\ &&|& - \hex{FD}~~274{:}\Bu32 &\Rightarrow& \I16X8.\K{relaxed\_dot\_i8x16\_i7x16\_s} \\ &&|& - \hex{FD}~~275{:}\Bu32 &\Rightarrow& \I16X8.\K{relaxed\_dot\_i8x16\_i7x16\_add\_s} \\ + \hex{FD}~~274{:}\Bu32 &\Rightarrow& \I16X8.\RDOT\K{\_i8x16\_i7x16\_s} \\ &&|& + \hex{FD}~~275{:}\Bu32 &\Rightarrow& \I16X8.\RDOT\K{\_i8x16\_i7x16\_add\_s} \\ \end{array} diff --git a/document/core/exec/instructions.rst b/document/core/exec/instructions.rst index 51728124a..654dbaeb1 100644 --- a/document/core/exec/instructions.rst +++ b/document/core/exec/instructions.rst @@ -958,7 +958,7 @@ where: .. _exec-vec-rdot: -:math:`\K{i16x8.}\DOT\K{\_i8x16\_i7x16\_s}` +:math:`\K{i16x8.}\RDOT\K{\_i8x16\_i7x16\_s}` ................................................... 1. Assert: due to :ref:`validation `, two values of :ref:`value type ` |V128| are on the top of the stack. @@ -978,7 +978,7 @@ where: .. math:: \begin{array}{l} \begin{array}{llcl@{\qquad}l} - & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i16x8.}\DOT\K{\_i8x16\_i7x16\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ + & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i16x8.}\RDOT\K{\_i8x16\_i7x16\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} @@ -989,7 +989,7 @@ where: \end{array} -:math:`\K{i32x4.}\DOT\K{\_i8x16\_i7x16\_add\_s}` +:math:`\K{i32x4.}\RDOT\K{\_i8x16\_i7x16\_add\_s}` ........................................................ 1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. @@ -1013,7 +1013,7 @@ where: .. math:: \begin{array}{l} \begin{array}{llcl@{\qquad}l} - & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\K{i32x4.}\DOT\K{\_i8x16\_i7x16\_add\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ + & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\K{i32x4.}\RDOT\K{\_i8x16\_i7x16\_add\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} diff --git a/document/core/text/instructions.rst b/document/core/text/instructions.rst index e0ec41e4c..2ec4a83c4 100644 --- a/document/core/text/instructions.rst +++ b/document/core/text/instructions.rst @@ -896,27 +896,27 @@ Vector constant instructions have a mandatory :ref:`shape ` de .. math:: \begin{array}{llclll} - \phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averyveryverylonginstructionnameforvectext} && \phantom{vechasreallyreallyreallylonginstructionnames} \\[-2ex] &&|& + \phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforvectext} && \phantom{vechasreallyreallyreallylonginstructionnames} \\[-2ex] &&|& \text{i16x8.relaxed\_swizzle} &\Rightarrow& \I16X8.\RSWIZZLE \\ &&|& - \text{i32x4.relaxed\_trunc\_f32x4\_s} &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_s} \\ &&|& - \text{i32x4.relaxed\_trunc\_f32x4\_u} &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_u} \\ &&|& - \text{i32x4.relaxed\_trunc\_f32x4\_s\_zero} &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_s\_zero} \\ &&|& - \text{i32x4.relaxed\_trunc\_f32x4\_u\_zero} &\Rightarrow& \I32X4.\RVTRUNC\K{\_f32x4\_u\_zero} \\ &&|& - \text{f32x4.relaxed\_madd} &\Rightarrow& \F32X4.\K{relaxed\_madd} \\ &&|& - \text{f32x4.relaxed\_nmadd} &\Rightarrow& \F32X4.\K{relaxed\_nmadd} \\ &&|& - \text{f64x2.relaxed\_madd} &\Rightarrow& \F64X2.\K{relaxed\_madd} \\ &&|& - \text{f64x2.relaxed\_nmadd} &\Rightarrow& \F64X2.\K{relaxed\_nmadd} \\ &&|& - \text{i8x16.relaxed\_laneselect} &\Rightarrow& \I8X16.\K{relaxed\_laneselect} \\ &&|& - \text{i16x8.relaxed\_laneselect} &\Rightarrow& \I16X8.\K{relaxed\_laneselect} \\ &&|& - \text{i32x4.relaxed\_laneselect} &\Rightarrow& \I32X4.\K{relaxed\_laneselect} \\ &&|& - \text{i64x2.relaxed\_laneselect} &\Rightarrow& \I64X2.\K{relaxed\_laneselect} \\ &&|& - \text{f32x4.relaxed\_min} &\Rightarrow& \F32X4.\K{relaxed\_min} \\ &&|& - \text{f32x4.relaxed\_max} &\Rightarrow& \F32X4.\K{relaxed\_max} \\ &&|& - \text{f64x2.relaxed\_min} &\Rightarrow& \F64X2.\K{relaxed\_min} \\ &&|& - \text{f64x2.relaxed\_max} &\Rightarrow& \F64X2.\K{relaxed\_max} \\ &&|& + \text{i32x4.relaxed\_trunc\_f32x4\_s} &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_s} \\ &&|& + \text{i32x4.relaxed\_trunc\_f32x4\_u} &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_u} \\ &&|& + \text{i32x4.relaxed\_trunc\_f32x4\_s\_zero} &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_s\_zero} \\ &&|& + \text{i32x4.relaxed\_trunc\_f32x4\_u\_zero} &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_u\_zero} \\ &&|& + \text{f32x4.relaxed\_madd} &\Rightarrow& \F32X4.\RMADD \\ &&|& + \text{f32x4.relaxed\_nmadd} &\Rightarrow& \F32X4.\RNMADD \\ &&|& + \text{f64x2.relaxed\_madd} &\Rightarrow& \F64X2.\RMADD \\ &&|& + \text{f64x2.relaxed\_nmadd} &\Rightarrow& \F64X2.\RNMADD \\ &&|& + \text{i8x16.relaxed\_laneselect} &\Rightarrow& \I8X16.\RLANESELECT \\ &&|& + \text{i16x8.relaxed\_laneselect} &\Rightarrow& \I16X8.\RLANESELECT \\ &&|& + \text{i32x4.relaxed\_laneselect} &\Rightarrow& \I32X4.\RLANESELECT \\ &&|& + \text{i64x2.relaxed\_laneselect} &\Rightarrow& \I64X2.\RLANESELECT \\ &&|& + \text{f32x4.relaxed\_min} &\Rightarrow& \F32X4.\RMIN \\ &&|& + \text{f32x4.relaxed\_max} &\Rightarrow& \F32X4.\RMAX \\ &&|& + \text{f64x2.relaxed\_min} &\Rightarrow& \F64X2.\RMIN \\ &&|& + \text{f64x2.relaxed\_max} &\Rightarrow& \F64X2.\RMAX \\ &&|& \text{i16x8.relaxed\_q15mulr\_s} &\Rightarrow& \I16X8.\RQ15MULRS \\ &&|& - \text{i16x8.relaxed\_dot\_i8x16\_i7x16\_s} &\Rightarrow& \I16X8.\K{relaxed\_dot\_i8x16\_i7x16\_s} \\ &&|& - \text{i16x8.relaxed\_dot\_i8x16\_i7x16\_add\_s} &\Rightarrow& \I16X8.\K{relaxed\_dot\_i8x16\_i7x16\_add\_s} + \text{i16x8.relaxed\_dot\_i8x16\_i7x16\_s} &\Rightarrow& \I16X8.\RDOT\K{\_i8x16\_i7x16\_s} \\ &&|& + \text{i16x8.relaxed\_dot\_i8x16\_i7x16\_add\_s} &\Rightarrow& \I16X8.\RDOT\K{\_i8x16\_i7x16\_add\_s} \end{array} diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 7fa5ff0f2..9e213948e 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -507,7 +507,7 @@ .. |RMAX| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_max}} .. |RQ15MULRS| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_q15mulr\_s}} .. |RTRUNC| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_trunc}} -.. |RDOT| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{\_dot}} +.. |RDOT| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_dot}} .. Instructions, non-terminals From f8cac7f3a02826ddbf608abdc19d37d38f9ebbc9 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 09:22:03 -0800 Subject: [PATCH 077/117] Update document/core/exec/numerics.rst Co-authored-by: Andreas Rossberg --- document/core/exec/numerics.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 24d552229..3e48060fe 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2022,7 +2022,7 @@ Relaxed Negative Multiply Add (nmadd) allows for fused or unfused results. :math:`\rswizzle(a^n, s^n)` ........................... -Relaxed swizzle lane is a helper for relaxed swizzle. Result is deterministic +Relaxed swizzle lane is deterministic if the signed interpretation of the index is less than 16 (including negative). :math:`j` is a 8-bit int. From 5e08ffca5ba7eb0073d9ad6e1f592c9137ec34ed Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 09:22:14 -0800 Subject: [PATCH 078/117] Update document/core/exec/numerics.rst Co-authored-by: Andreas Rossberg --- document/core/exec/numerics.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 3e48060fe..9cd0bc033 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2023,7 +2023,7 @@ Relaxed Negative Multiply Add (nmadd) allows for fused or unfused results. ........................... Relaxed swizzle lane is deterministic -if the signed interpretation of the index is less than 16 (including negative). +if the signed interpretation of the index is less than 16 (including negative values). :math:`j` is a 8-bit int. .. math:: From c3f3239721276c6a241776a0a147266b72d5a431 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 09:22:36 -0800 Subject: [PATCH 079/117] Update document/core/exec/numerics.rst Co-authored-by: Andreas Rossberg --- document/core/exec/numerics.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 9cd0bc033..96ee12dab 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2061,8 +2061,8 @@ hardware dependent. :math:`\rtrunc^s_{M,N}(z)` .......................... -Relaxed truncate converts float to int, NaN and out of range values are -hardware dependent. +Relaxed signed truncation converts floating point numbers to integers. +The result for NaN's and out-of-range values is host-dependent. .. math:: \begin{array}{@{}llcll} From ddcc7ed5ca7afffdf65c8f1c6a07aa72f02dd796 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 09:23:05 -0800 Subject: [PATCH 080/117] Update document/core/exec/numerics.rst Co-authored-by: Andreas Rossberg --- document/core/exec/numerics.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 96ee12dab..27380cf10 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2148,7 +2148,7 @@ when either input is a NaN. :math:`\ridotmul_{M,N}(i_1, i_2)` ................................. -Relaxed integer dot product differs from integer dot product when the elements of the input have top bit set. +Relaxed integer dot product differs from regular integer dot product when the elements of the input have their most significant bit set. .. math:: \begin{array}{@{}llcll} From b2fe562dfd79fd78313145c2467a056d5566633f Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 09:23:19 -0800 Subject: [PATCH 081/117] Update document/core/exec/numerics.rst Co-authored-by: Andreas Rossberg --- document/core/exec/numerics.rst | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 27380cf10..a9f298082 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2118,9 +2118,8 @@ when either input is a NaN. :math:`\frmax_N(z_1, z_2)` .......................... -Relaxed max differs from max when inputs are NaNs or different -signs of 0. It allows for implementation to return the first or second input -when either input is a NaN. +Relaxed maximum differs from regular maximum when inputs are NaN's or zeroes with different signs. +It allows for implementations to return the first or second input when either input is a NaN. .. math:: \begin{array}{@{}llcll} From 64bdd028828b7139ba4a9c387df2b6ff874a7f8d Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 09:23:26 -0800 Subject: [PATCH 082/117] Update document/core/exec/numerics.rst Co-authored-by: Andreas Rossberg --- document/core/exec/numerics.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index a9f298082..519396b9e 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2009,7 +2009,7 @@ defined by |IEEE754|_ (Section 5.4.1) as *fusedMultiplyAdd*. :math:`\frnmadd_N(z_1, z_2, z_3)` ................................. -Relaxed Negative Multiply Add (nmadd) allows for fused or unfused results. +Relaxed negative multiply-add allows for fused or unfused results. .. math:: \begin{array}{@{}llcll} From caee90620ad7bc5ee69e3b5aca4ef4b6dca7230b Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 17:35:08 +0000 Subject: [PATCH 083/117] Spell out instruction mnemonic --- .../core/appendix/gen-index-instructions.py | 40 +- document/core/appendix/index-instructions.rst | 1060 ++++++++--------- document/core/binary/instructions.rst | 40 +- document/core/exec/instructions.rst | 30 +- document/core/syntax/instructions.rst | 16 +- document/core/text/instructions.rst | 40 +- document/core/util/macros.def | 18 +- document/core/valid/instructions.rst | 10 +- 8 files changed, 627 insertions(+), 627 deletions(-) diff --git a/document/core/appendix/gen-index-instructions.py b/document/core/appendix/gen-index-instructions.py index b0aba79c2..722c7152c 100755 --- a/document/core/appendix/gen-index-instructions.py +++ b/document/core/appendix/gen-index-instructions.py @@ -575,26 +575,26 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}', r'\hex{FD}~~\hex{FD}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_u'), Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_s}', r'\hex{FD}~~\hex{FE}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_s'), Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_u}', r'\hex{FD}~~\hex{FF}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_u'), - Instruction(r'\I8X16.\RSWIZZLE', r'\hex{FD}~~\hex{80}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vec-rswizzle', r'exec-vec-rswizzle', r'op-rswizzle'), - Instruction(r'\I32X4.\RTRUNC\K{\_f32x4\_s}', r'\hex{FD}~~\hex{81}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_s'), - Instruction(r'\I32X4.\RTRUNC\K{\_f32x4\_u}', r'\hex{FD}~~\hex{82}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_u'), - Instruction(r'\I32X4.\RTRUNC\K{\_f64x2\_s}', r'\hex{FD}~~\hex{83}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_s'), - Instruction(r'\I32X4.\RTRUNC\K{\_f64x2\_u}', r'\hex{FD}~~\hex{84}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_u'), - Instruction(r'\F32X4.\RMADD', r'\hex{FD}~~\hex{85}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frmadd'), - Instruction(r'\F32X4.\RNMADD', r'\hex{FD}~~\hex{86}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frnmadd'), - Instruction(r'\F64X2.\RMADD', r'\hex{FD}~~\hex{87}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frmadd'), - Instruction(r'\F64X2.\RNMADD', r'\hex{FD}~~\hex{88}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frnmadd'), - Instruction(r'\I8X16.\RLANESELECT', r'\hex{FD}~~\hex{89}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), - Instruction(r'\I16X8.\RLANESELECT', r'\hex{FD}~~\hex{8A}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), - Instruction(r'\I32X4.\RLANESELECT', r'\hex{FD}~~\hex{8B}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), - Instruction(r'\I64X2.\RLANESELECT', r'\hex{FD}~~\hex{8C}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), - Instruction(r'\F32X4.\RMIN', r'\hex{FD}~~\hex{8D}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmin'), - Instruction(r'\F32X4.\RMAX', r'\hex{FD}~~\hex{8E}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmax'), - Instruction(r'\F64X2.\RMIN', r'\hex{FD}~~\hex{8F}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmin'), - Instruction(r'\F64X2.\RMAX', r'\hex{FD}~~\hex{90}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmax'), - Instruction(r'\I16X8.\RQ15MULRS', r'\hex{FD}~~\hex{91}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-irq15mulr_s'), - Instruction(r'\I16X8.\RDOT\K{\_i8x16\_i7x16\_s}', r'\hex{FD}~~\hex{92}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vec-rdot', r'exec-vec-rdot', r'op-ridotmul'), - Instruction(r'\I32X4.\RDOT\K{\_i8x16\_i7x16\_add\_s}', r'\hex{FD}~~\hex{93}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vec-rdot', r'exec-vec-rdot', r'op-ridotmul'), + Instruction(r'\I8X16.\RELAXEDSWIZZLE', r'\hex{FD}~~\hex{80}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-relaxed_swizzle', r'exec-relaxed_swizzle', r'op-rswizzle'), + Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f32x4\_s}', r'\hex{FD}~~\hex{81}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_s'), + Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f32x4\_u}', r'\hex{FD}~~\hex{82}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_u'), + Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f64x2\_s}', r'\hex{FD}~~\hex{83}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_s'), + Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f64x2\_u}', r'\hex{FD}~~\hex{84}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_u'), + Instruction(r'\F32X4.\RELAXEDMADD', r'\hex{FD}~~\hex{85}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frmadd'), + Instruction(r'\F32X4.\RELAXEDNMADD', r'\hex{FD}~~\hex{86}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frnmadd'), + Instruction(r'\F64X2.\RELAXEDMADD', r'\hex{FD}~~\hex{87}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frmadd'), + Instruction(r'\F64X2.\RELAXEDNMADD', r'\hex{FD}~~\hex{88}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frnmadd'), + Instruction(r'\I8X16.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{89}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), + Instruction(r'\I16X8.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8A}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), + Instruction(r'\I32X4.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8B}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), + Instruction(r'\I64X2.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8C}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), + Instruction(r'\F32X4.\RELAXEDMIN', r'\hex{FD}~~\hex{8D}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmin'), + Instruction(r'\F32X4.\RELAXEDMAX', r'\hex{FD}~~\hex{8E}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmax'), + Instruction(r'\F64X2.\RELAXEDMIN', r'\hex{FD}~~\hex{8F}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmin'), + Instruction(r'\F64X2.\RELAXEDMAX', r'\hex{FD}~~\hex{90}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmax'), + Instruction(r'\I16X8.\RELAXEDQ15MULRS', r'\hex{FD}~~\hex{91}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-irq15mulr_s'), + Instruction(r'\I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_s}', r'\hex{FD}~~\hex{92}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-relaxed_dot', r'exec-relaxed_dot', r'op-ridotmul'), + Instruction(r'\I32X4.\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s}', r'\hex{FD}~~\hex{93}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_dot', r'exec-relaxed_dot', r'op-ridotmul'), ] diff --git a/document/core/appendix/index-instructions.rst b/document/core/appendix/index-instructions.rst index 502935af0..df2cecd92 100644 --- a/document/core/appendix/index-instructions.rst +++ b/document/core/appendix/index-instructions.rst @@ -6,536 +6,536 @@ Index of Instructions --------------------- -================================================= ==================================== ============================================= ============================================= ===================================================================== -Instruction Binary Opcode Type Validation Execution -================================================= ==================================== ============================================= ============================================= ===================================================================== -:math:`\UNREACHABLE` :math:`\hex{00}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\NOP` :math:`\hex{01}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` -:math:`\BLOCK~\X{bt}` :math:`\hex{02}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\LOOP~\X{bt}` :math:`\hex{03}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\IF~\X{bt}` :math:`\hex{04}` :math:`[t_1^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\ELSE` :math:`\hex{05}` -(reserved) :math:`\hex{06}` -(reserved) :math:`\hex{07}` -(reserved) :math:`\hex{08}` -(reserved) :math:`\hex{09}` -(reserved) :math:`\hex{0A}` -:math:`\END` :math:`\hex{0B}` -:math:`\BR~l` :math:`\hex{0C}` :math:`[t_1^\ast~t^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\BRIF~l` :math:`\hex{0D}` :math:`[t^\ast~\I32] \to [t^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\BRTABLE~l^\ast~l` :math:`\hex{0E}` :math:`[t_1^\ast~t^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\RETURN` :math:`\hex{0F}` :math:`[t_1^\ast~t^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\CALL~x` :math:`\hex{10}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\CALLINDIRECT~x~y` :math:`\hex{11}` :math:`[t_1^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -(reserved) :math:`\hex{12}` -(reserved) :math:`\hex{13}` -(reserved) :math:`\hex{14}` -(reserved) :math:`\hex{15}` -(reserved) :math:`\hex{16}` -(reserved) :math:`\hex{17}` -(reserved) :math:`\hex{18}` -(reserved) :math:`\hex{19}` -:math:`\DROP` :math:`\hex{1A}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` -:math:`\SELECT` :math:`\hex{1B}` :math:`[t~t~\I32] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\SELECT~t` :math:`\hex{1C}` :math:`[t~t~\I32] \to [t]` :ref:`validation ` :ref:`execution ` -(reserved) :math:`\hex{1D}` -(reserved) :math:`\hex{1E}` -(reserved) :math:`\hex{1F}` -:math:`\LOCALGET~x` :math:`\hex{20}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\LOCALSET~x` :math:`\hex{21}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` -:math:`\LOCALTEE~x` :math:`\hex{22}` :math:`[t] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\GLOBALGET~x` :math:`\hex{23}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\GLOBALSET~x` :math:`\hex{24}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` -:math:`\TABLEGET~x` :math:`\hex{25}` :math:`[\I32] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\TABLESET~x` :math:`\hex{26}` :math:`[\I32~t] \to []` :ref:`validation ` :ref:`execution ` -(reserved) :math:`\hex{27}` -:math:`\I32.\LOAD~\memarg` :math:`\hex{28}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD~\memarg` :math:`\hex{29}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\F32.\LOAD~\memarg` :math:`\hex{2A}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution ` -:math:`\F64.\LOAD~\memarg` :math:`\hex{2B}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\LOAD\K{8\_s}~\memarg` :math:`\hex{2C}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\LOAD\K{8\_u}~\memarg` :math:`\hex{2D}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\LOAD\K{16\_s}~\memarg` :math:`\hex{2E}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\LOAD\K{16\_u}~\memarg` :math:`\hex{2F}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{8\_s}~\memarg` :math:`\hex{30}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{8\_u}~\memarg` :math:`\hex{31}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{16\_s}~\memarg` :math:`\hex{32}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{16\_u}~\memarg` :math:`\hex{33}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{32\_s}~\memarg` :math:`\hex{34}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{32\_u}~\memarg` :math:`\hex{35}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\STORE~\memarg` :math:`\hex{36}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I64.\STORE~\memarg` :math:`\hex{37}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\F32.\STORE~\memarg` :math:`\hex{38}` :math:`[\I32~\F32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\F64.\STORE~\memarg` :math:`\hex{39}` :math:`[\I32~\F64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I32.\STORE\K{8}~\memarg` :math:`\hex{3A}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I32.\STORE\K{16}~\memarg` :math:`\hex{3B}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I64.\STORE\K{8}~\memarg` :math:`\hex{3C}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I64.\STORE\K{16}~\memarg` :math:`\hex{3D}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I64.\STORE\K{32}~\memarg` :math:`\hex{3E}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\MEMORYSIZE` :math:`\hex{3F}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\MEMORYGROW` :math:`\hex{40}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\CONST~\i32` :math:`\hex{41}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\CONST~\i64` :math:`\hex{42}` :math:`[] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\F32.\CONST~\f32` :math:`\hex{43}` :math:`[] \to [\F32]` :ref:`validation ` :ref:`execution ` -:math:`\F64.\CONST~\f64` :math:`\hex{44}` :math:`[] \to [\F64]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\EQZ` :math:`\hex{45}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\EQ` :math:`\hex{46}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\NE` :math:`\hex{47}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\LT\K{\_s}` :math:`\hex{48}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\LT\K{\_u}` :math:`\hex{49}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\GT\K{\_s}` :math:`\hex{4A}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\GT\K{\_u}` :math:`\hex{4B}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\LE\K{\_s}` :math:`\hex{4C}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\LE\K{\_u}` :math:`\hex{4D}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\GE\K{\_s}` :math:`\hex{4E}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\GE\K{\_u}` :math:`\hex{4F}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EQZ` :math:`\hex{50}` :math:`[\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EQ` :math:`\hex{51}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\NE` :math:`\hex{52}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\LT\K{\_s}` :math:`\hex{53}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\LT\K{\_u}` :math:`\hex{54}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\GT\K{\_s}` :math:`\hex{55}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\GT\K{\_u}` :math:`\hex{56}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\LE\K{\_s}` :math:`\hex{57}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\LE\K{\_u}` :math:`\hex{58}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\GE\K{\_s}` :math:`\hex{59}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\GE\K{\_u}` :math:`\hex{5A}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\EQ` :math:`\hex{5B}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\NE` :math:`\hex{5C}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\LT` :math:`\hex{5D}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\GT` :math:`\hex{5E}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\LE` :math:`\hex{5F}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\GE` :math:`\hex{60}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\EQ` :math:`\hex{61}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\NE` :math:`\hex{62}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\LT` :math:`\hex{63}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\GT` :math:`\hex{64}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\LE` :math:`\hex{65}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\GE` :math:`\hex{66}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\CLZ` :math:`\hex{67}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\CTZ` :math:`\hex{68}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\POPCNT` :math:`\hex{69}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\ADD` :math:`\hex{6A}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\SUB` :math:`\hex{6B}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\MUL` :math:`\hex{6C}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\DIV\K{\_s}` :math:`\hex{6D}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\DIV\K{\_u}` :math:`\hex{6E}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\REM\K{\_s}` :math:`\hex{6F}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\REM\K{\_u}` :math:`\hex{70}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\AND` :math:`\hex{71}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\OR` :math:`\hex{72}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\XOR` :math:`\hex{73}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\SHL` :math:`\hex{74}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\SHR\K{\_s}` :math:`\hex{75}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\SHR\K{\_u}` :math:`\hex{76}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\ROTL` :math:`\hex{77}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\ROTR` :math:`\hex{78}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\CLZ` :math:`\hex{79}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\CTZ` :math:`\hex{7A}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\POPCNT` :math:`\hex{7B}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\ADD` :math:`\hex{7C}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\SUB` :math:`\hex{7D}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\MUL` :math:`\hex{7E}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\DIV\K{\_s}` :math:`\hex{7F}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\DIV\K{\_u}` :math:`\hex{80}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\REM\K{\_s}` :math:`\hex{81}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\REM\K{\_u}` :math:`\hex{82}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\AND` :math:`\hex{83}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\OR` :math:`\hex{84}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\XOR` :math:`\hex{85}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\SHL` :math:`\hex{86}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\SHR\K{\_s}` :math:`\hex{87}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\SHR\K{\_u}` :math:`\hex{88}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\ROTL` :math:`\hex{89}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\ROTR` :math:`\hex{8A}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\ABS` :math:`\hex{8B}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\NEG` :math:`\hex{8C}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CEIL` :math:`\hex{8D}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\FLOOR` :math:`\hex{8E}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\TRUNC` :math:`\hex{8F}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\NEAREST` :math:`\hex{90}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\SQRT` :math:`\hex{91}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\ADD` :math:`\hex{92}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\SUB` :math:`\hex{93}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\MUL` :math:`\hex{94}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\DIV` :math:`\hex{95}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\FMIN` :math:`\hex{96}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\FMAX` :math:`\hex{97}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\COPYSIGN` :math:`\hex{98}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\ABS` :math:`\hex{99}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\NEG` :math:`\hex{9A}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CEIL` :math:`\hex{9B}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\FLOOR` :math:`\hex{9C}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\TRUNC` :math:`\hex{9D}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\NEAREST` :math:`\hex{9E}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\SQRT` :math:`\hex{9F}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\ADD` :math:`\hex{A0}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\SUB` :math:`\hex{A1}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\MUL` :math:`\hex{A2}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\DIV` :math:`\hex{A3}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\FMIN` :math:`\hex{A4}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\FMAX` :math:`\hex{A5}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\COPYSIGN` :math:`\hex{A6}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\WRAP\K{\_}\I64` :math:`\hex{A7}` :math:`[\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_}\F32\K{\_s}` :math:`\hex{A8}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_}\F32\K{\_u}` :math:`\hex{A9}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_}\F64\K{\_s}` :math:`\hex{AA}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_}\F64\K{\_u}` :math:`\hex{AB}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{\_}\I32\K{\_s}` :math:`\hex{AC}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{\_}\I32\K{\_u}` :math:`\hex{AD}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_}\F32\K{\_s}` :math:`\hex{AE}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_}\F32\K{\_u}` :math:`\hex{AF}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_}\F64\K{\_s}` :math:`\hex{B0}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_}\F64\K{\_u}` :math:`\hex{B1}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CONVERT\K{\_}\I32\K{\_s}` :math:`\hex{B2}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CONVERT\K{\_}\I32\K{\_u}` :math:`\hex{B3}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CONVERT\K{\_}\I64\K{\_s}` :math:`\hex{B4}` :math:`[\I64] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CONVERT\K{\_}\I64\K{\_u}` :math:`\hex{B5}` :math:`[\I64] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\DEMOTE\K{\_}\F64` :math:`\hex{B6}` :math:`[\F64] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CONVERT\K{\_}\I32\K{\_s}` :math:`\hex{B7}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CONVERT\K{\_}\I32\K{\_u}` :math:`\hex{B8}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CONVERT\K{\_}\I64\K{\_s}` :math:`\hex{B9}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CONVERT\K{\_}\I64\K{\_u}` :math:`\hex{BA}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\PROMOTE\K{\_}\F32` :math:`\hex{BB}` :math:`[\F32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\REINTERPRET\K{\_}\F32` :math:`\hex{BC}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\REINTERPRET\K{\_}\F64` :math:`\hex{BD}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\REINTERPRET\K{\_}\I32` :math:`\hex{BE}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\REINTERPRET\K{\_}\I64` :math:`\hex{BF}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\EXTEND\K{8\_s}` :math:`\hex{C0}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\EXTEND\K{16\_s}` :math:`\hex{C1}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{8\_s}` :math:`\hex{C2}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{16\_s}` :math:`\hex{C3}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{32\_s}` :math:`\hex{C4}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -(reserved) :math:`\hex{C5}` -(reserved) :math:`\hex{C6}` -(reserved) :math:`\hex{C7}` -(reserved) :math:`\hex{C8}` -(reserved) :math:`\hex{C9}` -(reserved) :math:`\hex{CA}` -(reserved) :math:`\hex{CB}` -(reserved) :math:`\hex{CC}` -(reserved) :math:`\hex{CD}` -(reserved) :math:`\hex{CE}` -(reserved) :math:`\hex{CF}` -:math:`\REFNULL~t` :math:`\hex{D0}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\REFISNULL` :math:`\hex{D1}` :math:`[t] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\REFFUNC~x` :math:`\hex{D2}` :math:`[] \to [\FUNCREF]` :ref:`validation ` :ref:`execution ` -(reserved) :math:`\hex{D3}` -(reserved) :math:`\hex{D4}` -(reserved) :math:`\hex{D5}` -(reserved) :math:`\hex{D6}` -(reserved) :math:`\hex{D7}` -(reserved) :math:`\hex{D8}` -(reserved) :math:`\hex{D9}` -(reserved) :math:`\hex{DA}` -(reserved) :math:`\hex{DB}` -(reserved) :math:`\hex{DC}` -(reserved) :math:`\hex{DD}` -(reserved) :math:`\hex{DE}` -(reserved) :math:`\hex{DF}` -(reserved) :math:`\hex{E0}` -(reserved) :math:`\hex{E1}` -(reserved) :math:`\hex{E2}` -(reserved) :math:`\hex{E3}` -(reserved) :math:`\hex{E4}` -(reserved) :math:`\hex{E5}` -(reserved) :math:`\hex{E6}` -(reserved) :math:`\hex{E7}` -(reserved) :math:`\hex{E8}` -(reserved) :math:`\hex{E9}` -(reserved) :math:`\hex{EA}` -(reserved) :math:`\hex{EB}` -(reserved) :math:`\hex{EC}` -(reserved) :math:`\hex{ED}` -(reserved) :math:`\hex{EE}` -(reserved) :math:`\hex{EF}` -(reserved) :math:`\hex{F0}` -(reserved) :math:`\hex{F1}` -(reserved) :math:`\hex{F2}` -(reserved) :math:`\hex{F3}` -(reserved) :math:`\hex{F4}` -(reserved) :math:`\hex{F5}` -(reserved) :math:`\hex{F6}` -(reserved) :math:`\hex{F7}` -(reserved) :math:`\hex{F8}` -(reserved) :math:`\hex{F9}` -(reserved) :math:`\hex{FA}` -(reserved) :math:`\hex{FB}` -:math:`\I32.\TRUNC\K{\_sat\_}\F32\K{\_s}` :math:`\hex{FC}~\hex{00}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_sat\_}\F32\K{\_u}` :math:`\hex{FC}~\hex{01}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_sat\_}\F64\K{\_s}` :math:`\hex{FC}~\hex{02}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_sat\_}\F64\K{\_u}` :math:`\hex{FC}~\hex{03}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_sat\_}\F32\K{\_s}` :math:`\hex{FC}~\hex{04}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_sat\_}\F32\K{\_u}` :math:`\hex{FC}~\hex{05}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_sat\_}\F64\K{\_s}` :math:`\hex{FC}~\hex{06}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_sat\_}\F64\K{\_u}` :math:`\hex{FC}~\hex{07}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\MEMORYINIT~x` :math:`\hex{FC}~\hex{08}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\DATADROP~x` :math:`\hex{FC}~\hex{09}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` -:math:`\MEMORYCOPY` :math:`\hex{FC}~\hex{0A}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\MEMORYFILL` :math:`\hex{FC}~\hex{0B}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\TABLEINIT~x~y` :math:`\hex{FC}~\hex{0C}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\ELEMDROP~x` :math:`\hex{FC}~\hex{0D}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` -:math:`\TABLECOPY~x~y` :math:`\hex{FC}~\hex{0E}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\TABLEGROW~x` :math:`\hex{FC}~\hex{0F}` :math:`[t~\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\TABLESIZE~x` :math:`\hex{FC}~\hex{10}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\TABLEFILL~x` :math:`\hex{FC}~\hex{11}` :math:`[\I32~t~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD~\memarg` :math:`\hex{FD}~~\hex{00}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{8x8\_s}~\memarg` :math:`\hex{FD}~~\hex{01}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{8x8\_u}~\memarg` :math:`\hex{FD}~~\hex{02}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{16x4\_s}~\memarg` :math:`\hex{FD}~~\hex{03}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{16x4\_u}~\memarg` :math:`\hex{FD}~~\hex{04}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32x2\_s}~\memarg` :math:`\hex{FD}~~\hex{05}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32x2\_u}~\memarg` :math:`\hex{FD}~~\hex{06}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{8\_splat}~\memarg` :math:`\hex{FD}~~\hex{07}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{16\_splat}~\memarg` :math:`\hex{FD}~~\hex{08}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32\_splat}~\memarg` :math:`\hex{FD}~~\hex{09}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{64\_splat}~\memarg` :math:`\hex{FD}~~\hex{0A}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE~\memarg` :math:`\hex{FD}~~\hex{0B}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\VCONST~\i128` :math:`\hex{FD}~~\hex{0C}` :math:`[] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\SHUFFLE~\laneidx^{16}` :math:`\hex{FD}~~\hex{0D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\SWIZZLE` :math:`\hex{FD}~~\hex{0E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\SPLAT` :math:`\hex{FD}~~\hex{0F}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\SPLAT` :math:`\hex{FD}~~\hex{10}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\SPLAT` :math:`\hex{FD}~~\hex{11}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\SPLAT` :math:`\hex{FD}~~\hex{12}` :math:`[\I64] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\SPLAT` :math:`\hex{FD}~~\hex{13}` :math:`[\F32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F64X2.\SPLAT` :math:`\hex{FD}~~\hex{14}` :math:`[\F64] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\EXTRACTLANE\K{\_s}~\laneidx` :math:`\hex{FD}~~\hex{15}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\EXTRACTLANE\K{\_u}~\laneidx` :math:`\hex{FD}~~\hex{16}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{17}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTRACTLANE\K{\_s}~\laneidx` :math:`\hex{FD}~~\hex{18}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTRACTLANE\K{\_u}~\laneidx` :math:`\hex{FD}~~\hex{19}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1A}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1B}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1C}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1D}` :math:`[\V128] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1E}` :math:`[\V128~\I64] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1F}` :math:`[\V128] \to [\F32]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{20}` :math:`[\V128~\F32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F64X2.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{21}` :math:`[\V128] \to [\F64]` :ref:`validation ` :ref:`execution ` -:math:`\F64X2.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{22}` :math:`[\V128~\F64] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\VEQ` :math:`\hex{FD}~~\hex{23}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VNE` :math:`\hex{FD}~~\hex{24}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{25}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{26}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{27}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{28}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{29}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{2A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{2B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{2C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VEQ` :math:`\hex{FD}~~\hex{2D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VNE` :math:`\hex{FD}~~\hex{2E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{2F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{30}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{31}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{32}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{33}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{34}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{35}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{36}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VEQ` :math:`\hex{FD}~~\hex{37}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VNE` :math:`\hex{FD}~~\hex{38}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{39}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{3A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{3B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{3C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{3D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{3E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{3F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{40}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VEQ` :math:`\hex{FD}~~\hex{41}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VNE` :math:`\hex{FD}~~\hex{42}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VLT` :math:`\hex{FD}~~\hex{43}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VGT` :math:`\hex{FD}~~\hex{44}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VLE` :math:`\hex{FD}~~\hex{45}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VGE` :math:`\hex{FD}~~\hex{46}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VEQ` :math:`\hex{FD}~~\hex{47}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VNE` :math:`\hex{FD}~~\hex{48}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VLT` :math:`\hex{FD}~~\hex{49}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VGT` :math:`\hex{FD}~~\hex{4A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VLE` :math:`\hex{FD}~~\hex{4B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VGE` :math:`\hex{FD}~~\hex{4C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VNOT` :math:`\hex{FD}~~\hex{4D}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VAND` :math:`\hex{FD}~~\hex{4E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VANDNOT` :math:`\hex{FD}~~\hex{4F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VOR` :math:`\hex{FD}~~\hex{50}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VXOR` :math:`\hex{FD}~~\hex{51}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\BITSELECT` :math:`\hex{FD}~~\hex{52}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\ANYTRUE` :math:`\hex{FD}~~\hex{53}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{54}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{55}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{56}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{57}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{58}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{59}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5A}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5B}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5C}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{64\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5D}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\VDEMOTE\K{\_f64x2\_zero}` :math:`\hex{FD}~~\hex{5E}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VPROMOTE\K{\_low\_f32x4}` :math:`\hex{FD}~~\hex{5F}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VABS` :math:`\hex{FD}~~\hex{60}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VNEG` :math:`\hex{FD}~~\hex{61}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VPOPCNT` :math:`\hex{FD}~~\hex{62}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\ALLTRUE` :math:`\hex{FD}~~\hex{63}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\BITMASK` :math:`\hex{FD}~~\hex{64}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\NARROW\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{65}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\NARROW\K{\_i16x8\_u}` :math:`\hex{FD}~~\hex{66}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\VCEIL` :math:`\hex{FD}~~\hex{67}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VFLOOR` :math:`\hex{FD}~~\hex{68}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VTRUNC` :math:`\hex{FD}~~\hex{69}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VNEAREST` :math:`\hex{FD}~~\hex{6A}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSHL` :math:`\hex{FD}~~\hex{6B}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{6C}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{6D}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VADD` :math:`\hex{FD}~~\hex{6E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VADD\K{\_sat\_s}` :math:`\hex{FD}~~\hex{6F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VADD\K{\_sat\_u}` :math:`\hex{FD}~~\hex{70}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSUB` :math:`\hex{FD}~~\hex{71}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~\hex{72}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~\hex{73}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VCEIL` :math:`\hex{FD}~~\hex{74}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VFLOOR` :math:`\hex{FD}~~\hex{75}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{76}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{77}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{78}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{79}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VTRUNC` :math:`\hex{FD}~~\hex{7A}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\AVGR\K{\_u}` :math:`\hex{FD}~~\hex{7B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}` :math:`\hex{FD}~~\hex{7C}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}` :math:`\hex{FD}~~\hex{7D}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{7E}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}` :math:`\hex{FD}~~\hex{7F}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VABS` :math:`\hex{FD}~~\hex{80}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VNEG` :math:`\hex{FD}~~\hex{81}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\Q15MULRSAT\K{\_s}` :math:`\hex{FD}~~\hex{82}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\ALLTRUE` :math:`\hex{FD}~~\hex{83}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\BITMASK` :math:`\hex{FD}~~\hex{84}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\NARROW\K{\_i32x4\_s}` :math:`\hex{FD}~~\hex{85}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\NARROW\K{\_i32x4\_u}` :math:`\hex{FD}~~\hex{86}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~\hex{87}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~\hex{88}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~\hex{89}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~\hex{8A}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VSHL` :math:`\hex{FD}~~\hex{8B}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{8C}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{8D}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VADD` :math:`\hex{FD}~~\hex{8E}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VADD\K{\_sat\_s}` :math:`\hex{FD}~~\hex{8F}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VADD\K{\_sat\_u}` :math:`\hex{FD}~~\hex{90}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSUB` :math:`\hex{FD}~~\hex{91}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~\hex{92}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~\hex{93}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VNEAREST` :math:`\hex{FD}~~\hex{94}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMUL` :math:`\hex{FD}~~\hex{95}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{96}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{97}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{98}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{99}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\AVGR\K{\_u}` :math:`\hex{FD}~~\hex{9B}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~\hex{9C}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~\hex{9D}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~\hex{9E}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~\hex{9F}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VABS` :math:`\hex{FD}~~\hex{A0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VNEG` :math:`\hex{FD}~~\hex{A1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\ALLTRUE` :math:`\hex{FD}~~\hex{A3}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\BITMASK` :math:`\hex{FD}~~\hex{A4}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~\hex{A7}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~\hex{A8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~\hex{A9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~\hex{AA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VSHL` :math:`\hex{FD}~~\hex{AB}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{AC}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{AD}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VADD` :math:`\hex{FD}~~\hex{AE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VSUB` :math:`\hex{FD}~~\hex{B1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMUL` :math:`\hex{FD}~~\hex{B5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{B6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{B7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{B8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{B9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\DOT\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{BA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~\hex{BC}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~\hex{BD}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~\hex{BE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~\hex{BF}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VABS` :math:`\hex{FD}~~\hex{C0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VNEG` :math:`\hex{FD}~~\hex{C1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\ALLTRUE` :math:`\hex{FD}~~\hex{C3}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\BITMASK` :math:`\hex{FD}~~\hex{C4}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{C7}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~\hex{C8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{C9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~\hex{CA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VSHL` :math:`\hex{FD}~~\hex{CB}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{CC}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{CD}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VADD` :math:`\hex{FD}~~\hex{CE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VSUB` :math:`\hex{FD}~~\hex{D1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VMUL` :math:`\hex{FD}~~\hex{D5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VEQ` :math:`\hex{FD}~~\hex{D6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VNE` :math:`\hex{FD}~~\hex{D7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{D8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{D9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{DA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{DB}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{DC}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~\hex{DD}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{DE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~\hex{DF}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\VABS` :math:`\hex{FD}~~\hex{E0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VNEG` :math:`\hex{FD}~~\hex{E1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VSQRT` :math:`\hex{FD}~~\hex{E3}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VADD` :math:`\hex{FD}~~\hex{E4}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VSUB` :math:`\hex{FD}~~\hex{E5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VMUL` :math:`\hex{FD}~~\hex{E6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VDIV` :math:`\hex{FD}~~\hex{E7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VMIN` :math:`\hex{FD}~~\hex{E8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VMAX` :math:`\hex{FD}~~\hex{E9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VPMIN` :math:`\hex{FD}~~\hex{EA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VPMAX` :math:`\hex{FD}~~\hex{EB}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VABS` :math:`\hex{FD}~~\hex{EC}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VNEG` :math:`\hex{FD}~~\hex{ED}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VSQRT` :math:`\hex{FD}~~\hex{EF}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VADD` :math:`\hex{FD}~~\hex{F0}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VSUB` :math:`\hex{FD}~~\hex{F1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VMUL` :math:`\hex{FD}~~\hex{F2}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VDIV` :math:`\hex{FD}~~\hex{F3}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VMIN` :math:`\hex{FD}~~\hex{F4}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VMAX` :math:`\hex{FD}~~\hex{F5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VPMIN` :math:`\hex{FD}~~\hex{F6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VPMAX` :math:`\hex{FD}~~\hex{F7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_s}` :math:`\hex{FD}~~\hex{F8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_u}` :math:`\hex{FD}~~\hex{F9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VCONVERT\K{\_i32x4\_s}` :math:`\hex{FD}~~\hex{FA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VCONVERT\K{\_i32x4\_u}` :math:`\hex{FD}~~\hex{FB}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_s\_zero}` :math:`\hex{FD}~~\hex{FC}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}` :math:`\hex{FD}~~\hex{FD}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{FE}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{FF}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\RSWIZZLE` :math:`\hex{FD}~~\hex{80}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\RTRUNC\K{\_f32x4\_s}` :math:`\hex{FD}~~\hex{81}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\RTRUNC\K{\_f32x4\_u}` :math:`\hex{FD}~~\hex{82}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\RTRUNC\K{\_f64x2\_s}` :math:`\hex{FD}~~\hex{83}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\RTRUNC\K{\_f64x2\_u}` :math:`\hex{FD}~~\hex{84}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\RMADD` :math:`\hex{FD}~~\hex{85}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\RNMADD` :math:`\hex{FD}~~\hex{86}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\RMADD` :math:`\hex{FD}~~\hex{87}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\RNMADD` :math:`\hex{FD}~~\hex{88}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\RLANESELECT` :math:`\hex{FD}~~\hex{89}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\RLANESELECT` :math:`\hex{FD}~~\hex{8A}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\RLANESELECT` :math:`\hex{FD}~~\hex{8B}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\RLANESELECT` :math:`\hex{FD}~~\hex{8C}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\RMIN` :math:`\hex{FD}~~\hex{8D}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\RMAX` :math:`\hex{FD}~~\hex{8E}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\RMIN` :math:`\hex{FD}~~\hex{8F}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\RMAX` :math:`\hex{FD}~~\hex{90}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\RQ15MULRS` :math:`\hex{FD}~~\hex{91}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\RDOT\K{\_i8x16\_i7x16\_s}` :math:`\hex{FD}~~\hex{92}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\RDOT\K{\_i8x16\_i7x16\_add\_s}` :math:`\hex{FD}~~\hex{93}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -================================================= ==================================== ============================================= ============================================= ===================================================================== +==================================================== ==================================== ============================================= ============================================= ====================================================================== +Instruction Binary Opcode Type Validation Execution +==================================================== ==================================== ============================================= ============================================= ====================================================================== +:math:`\UNREACHABLE` :math:`\hex{00}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\NOP` :math:`\hex{01}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` +:math:`\BLOCK~\X{bt}` :math:`\hex{02}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\LOOP~\X{bt}` :math:`\hex{03}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\IF~\X{bt}` :math:`\hex{04}` :math:`[t_1^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\ELSE` :math:`\hex{05}` +(reserved) :math:`\hex{06}` +(reserved) :math:`\hex{07}` +(reserved) :math:`\hex{08}` +(reserved) :math:`\hex{09}` +(reserved) :math:`\hex{0A}` +:math:`\END` :math:`\hex{0B}` +:math:`\BR~l` :math:`\hex{0C}` :math:`[t_1^\ast~t^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\BRIF~l` :math:`\hex{0D}` :math:`[t^\ast~\I32] \to [t^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\BRTABLE~l^\ast~l` :math:`\hex{0E}` :math:`[t_1^\ast~t^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\RETURN` :math:`\hex{0F}` :math:`[t_1^\ast~t^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\CALL~x` :math:`\hex{10}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\CALLINDIRECT~x~y` :math:`\hex{11}` :math:`[t_1^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +(reserved) :math:`\hex{12}` +(reserved) :math:`\hex{13}` +(reserved) :math:`\hex{14}` +(reserved) :math:`\hex{15}` +(reserved) :math:`\hex{16}` +(reserved) :math:`\hex{17}` +(reserved) :math:`\hex{18}` +(reserved) :math:`\hex{19}` +:math:`\DROP` :math:`\hex{1A}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` +:math:`\SELECT` :math:`\hex{1B}` :math:`[t~t~\I32] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\SELECT~t` :math:`\hex{1C}` :math:`[t~t~\I32] \to [t]` :ref:`validation ` :ref:`execution ` +(reserved) :math:`\hex{1D}` +(reserved) :math:`\hex{1E}` +(reserved) :math:`\hex{1F}` +:math:`\LOCALGET~x` :math:`\hex{20}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\LOCALSET~x` :math:`\hex{21}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` +:math:`\LOCALTEE~x` :math:`\hex{22}` :math:`[t] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\GLOBALGET~x` :math:`\hex{23}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\GLOBALSET~x` :math:`\hex{24}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` +:math:`\TABLEGET~x` :math:`\hex{25}` :math:`[\I32] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\TABLESET~x` :math:`\hex{26}` :math:`[\I32~t] \to []` :ref:`validation ` :ref:`execution ` +(reserved) :math:`\hex{27}` +:math:`\I32.\LOAD~\memarg` :math:`\hex{28}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD~\memarg` :math:`\hex{29}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\F32.\LOAD~\memarg` :math:`\hex{2A}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution ` +:math:`\F64.\LOAD~\memarg` :math:`\hex{2B}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\LOAD\K{8\_s}~\memarg` :math:`\hex{2C}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\LOAD\K{8\_u}~\memarg` :math:`\hex{2D}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\LOAD\K{16\_s}~\memarg` :math:`\hex{2E}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\LOAD\K{16\_u}~\memarg` :math:`\hex{2F}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD\K{8\_s}~\memarg` :math:`\hex{30}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD\K{8\_u}~\memarg` :math:`\hex{31}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD\K{16\_s}~\memarg` :math:`\hex{32}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD\K{16\_u}~\memarg` :math:`\hex{33}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD\K{32\_s}~\memarg` :math:`\hex{34}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD\K{32\_u}~\memarg` :math:`\hex{35}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\STORE~\memarg` :math:`\hex{36}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I64.\STORE~\memarg` :math:`\hex{37}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\F32.\STORE~\memarg` :math:`\hex{38}` :math:`[\I32~\F32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\F64.\STORE~\memarg` :math:`\hex{39}` :math:`[\I32~\F64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I32.\STORE\K{8}~\memarg` :math:`\hex{3A}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I32.\STORE\K{16}~\memarg` :math:`\hex{3B}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I64.\STORE\K{8}~\memarg` :math:`\hex{3C}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I64.\STORE\K{16}~\memarg` :math:`\hex{3D}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I64.\STORE\K{32}~\memarg` :math:`\hex{3E}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\MEMORYSIZE` :math:`\hex{3F}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\MEMORYGROW` :math:`\hex{40}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\CONST~\i32` :math:`\hex{41}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\CONST~\i64` :math:`\hex{42}` :math:`[] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\F32.\CONST~\f32` :math:`\hex{43}` :math:`[] \to [\F32]` :ref:`validation ` :ref:`execution ` +:math:`\F64.\CONST~\f64` :math:`\hex{44}` :math:`[] \to [\F64]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\EQZ` :math:`\hex{45}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\EQ` :math:`\hex{46}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\NE` :math:`\hex{47}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\LT\K{\_s}` :math:`\hex{48}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\LT\K{\_u}` :math:`\hex{49}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\GT\K{\_s}` :math:`\hex{4A}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\GT\K{\_u}` :math:`\hex{4B}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\LE\K{\_s}` :math:`\hex{4C}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\LE\K{\_u}` :math:`\hex{4D}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\GE\K{\_s}` :math:`\hex{4E}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\GE\K{\_u}` :math:`\hex{4F}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EQZ` :math:`\hex{50}` :math:`[\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EQ` :math:`\hex{51}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\NE` :math:`\hex{52}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\LT\K{\_s}` :math:`\hex{53}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\LT\K{\_u}` :math:`\hex{54}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\GT\K{\_s}` :math:`\hex{55}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\GT\K{\_u}` :math:`\hex{56}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\LE\K{\_s}` :math:`\hex{57}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\LE\K{\_u}` :math:`\hex{58}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\GE\K{\_s}` :math:`\hex{59}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\GE\K{\_u}` :math:`\hex{5A}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\EQ` :math:`\hex{5B}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\NE` :math:`\hex{5C}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\LT` :math:`\hex{5D}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\GT` :math:`\hex{5E}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\LE` :math:`\hex{5F}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\GE` :math:`\hex{60}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\EQ` :math:`\hex{61}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\NE` :math:`\hex{62}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\LT` :math:`\hex{63}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\GT` :math:`\hex{64}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\LE` :math:`\hex{65}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\GE` :math:`\hex{66}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\CLZ` :math:`\hex{67}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\CTZ` :math:`\hex{68}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\POPCNT` :math:`\hex{69}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\ADD` :math:`\hex{6A}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\SUB` :math:`\hex{6B}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\MUL` :math:`\hex{6C}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\DIV\K{\_s}` :math:`\hex{6D}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\DIV\K{\_u}` :math:`\hex{6E}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\REM\K{\_s}` :math:`\hex{6F}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\REM\K{\_u}` :math:`\hex{70}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\AND` :math:`\hex{71}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\OR` :math:`\hex{72}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\XOR` :math:`\hex{73}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\SHL` :math:`\hex{74}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\SHR\K{\_s}` :math:`\hex{75}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\SHR\K{\_u}` :math:`\hex{76}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\ROTL` :math:`\hex{77}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\ROTR` :math:`\hex{78}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\CLZ` :math:`\hex{79}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\CTZ` :math:`\hex{7A}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\POPCNT` :math:`\hex{7B}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\ADD` :math:`\hex{7C}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\SUB` :math:`\hex{7D}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\MUL` :math:`\hex{7E}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\DIV\K{\_s}` :math:`\hex{7F}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\DIV\K{\_u}` :math:`\hex{80}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\REM\K{\_s}` :math:`\hex{81}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\REM\K{\_u}` :math:`\hex{82}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\AND` :math:`\hex{83}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\OR` :math:`\hex{84}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\XOR` :math:`\hex{85}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\SHL` :math:`\hex{86}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\SHR\K{\_s}` :math:`\hex{87}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\SHR\K{\_u}` :math:`\hex{88}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\ROTL` :math:`\hex{89}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\ROTR` :math:`\hex{8A}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\ABS` :math:`\hex{8B}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\NEG` :math:`\hex{8C}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\CEIL` :math:`\hex{8D}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\FLOOR` :math:`\hex{8E}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\TRUNC` :math:`\hex{8F}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\NEAREST` :math:`\hex{90}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\SQRT` :math:`\hex{91}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\ADD` :math:`\hex{92}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\SUB` :math:`\hex{93}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\MUL` :math:`\hex{94}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\DIV` :math:`\hex{95}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\FMIN` :math:`\hex{96}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\FMAX` :math:`\hex{97}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\COPYSIGN` :math:`\hex{98}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\ABS` :math:`\hex{99}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\NEG` :math:`\hex{9A}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\CEIL` :math:`\hex{9B}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\FLOOR` :math:`\hex{9C}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\TRUNC` :math:`\hex{9D}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\NEAREST` :math:`\hex{9E}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\SQRT` :math:`\hex{9F}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\ADD` :math:`\hex{A0}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\SUB` :math:`\hex{A1}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\MUL` :math:`\hex{A2}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\DIV` :math:`\hex{A3}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\FMIN` :math:`\hex{A4}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\FMAX` :math:`\hex{A5}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\COPYSIGN` :math:`\hex{A6}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\WRAP\K{\_}\I64` :math:`\hex{A7}` :math:`[\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_}\F32\K{\_s}` :math:`\hex{A8}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_}\F32\K{\_u}` :math:`\hex{A9}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_}\F64\K{\_s}` :math:`\hex{AA}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_}\F64\K{\_u}` :math:`\hex{AB}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{\_}\I32\K{\_s}` :math:`\hex{AC}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{\_}\I32\K{\_u}` :math:`\hex{AD}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_}\F32\K{\_s}` :math:`\hex{AE}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_}\F32\K{\_u}` :math:`\hex{AF}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_}\F64\K{\_s}` :math:`\hex{B0}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_}\F64\K{\_u}` :math:`\hex{B1}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\CONVERT\K{\_}\I32\K{\_s}` :math:`\hex{B2}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\CONVERT\K{\_}\I32\K{\_u}` :math:`\hex{B3}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\CONVERT\K{\_}\I64\K{\_s}` :math:`\hex{B4}` :math:`[\I64] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\CONVERT\K{\_}\I64\K{\_u}` :math:`\hex{B5}` :math:`[\I64] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\DEMOTE\K{\_}\F64` :math:`\hex{B6}` :math:`[\F64] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\CONVERT\K{\_}\I32\K{\_s}` :math:`\hex{B7}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\CONVERT\K{\_}\I32\K{\_u}` :math:`\hex{B8}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\CONVERT\K{\_}\I64\K{\_s}` :math:`\hex{B9}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\CONVERT\K{\_}\I64\K{\_u}` :math:`\hex{BA}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\PROMOTE\K{\_}\F32` :math:`\hex{BB}` :math:`[\F32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\REINTERPRET\K{\_}\F32` :math:`\hex{BC}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\REINTERPRET\K{\_}\F64` :math:`\hex{BD}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\REINTERPRET\K{\_}\I32` :math:`\hex{BE}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\REINTERPRET\K{\_}\I64` :math:`\hex{BF}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\EXTEND\K{8\_s}` :math:`\hex{C0}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\EXTEND\K{16\_s}` :math:`\hex{C1}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{8\_s}` :math:`\hex{C2}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{16\_s}` :math:`\hex{C3}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{32\_s}` :math:`\hex{C4}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +(reserved) :math:`\hex{C5}` +(reserved) :math:`\hex{C6}` +(reserved) :math:`\hex{C7}` +(reserved) :math:`\hex{C8}` +(reserved) :math:`\hex{C9}` +(reserved) :math:`\hex{CA}` +(reserved) :math:`\hex{CB}` +(reserved) :math:`\hex{CC}` +(reserved) :math:`\hex{CD}` +(reserved) :math:`\hex{CE}` +(reserved) :math:`\hex{CF}` +:math:`\REFNULL~t` :math:`\hex{D0}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\REFISNULL` :math:`\hex{D1}` :math:`[t] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\REFFUNC~x` :math:`\hex{D2}` :math:`[] \to [\FUNCREF]` :ref:`validation ` :ref:`execution ` +(reserved) :math:`\hex{D3}` +(reserved) :math:`\hex{D4}` +(reserved) :math:`\hex{D5}` +(reserved) :math:`\hex{D6}` +(reserved) :math:`\hex{D7}` +(reserved) :math:`\hex{D8}` +(reserved) :math:`\hex{D9}` +(reserved) :math:`\hex{DA}` +(reserved) :math:`\hex{DB}` +(reserved) :math:`\hex{DC}` +(reserved) :math:`\hex{DD}` +(reserved) :math:`\hex{DE}` +(reserved) :math:`\hex{DF}` +(reserved) :math:`\hex{E0}` +(reserved) :math:`\hex{E1}` +(reserved) :math:`\hex{E2}` +(reserved) :math:`\hex{E3}` +(reserved) :math:`\hex{E4}` +(reserved) :math:`\hex{E5}` +(reserved) :math:`\hex{E6}` +(reserved) :math:`\hex{E7}` +(reserved) :math:`\hex{E8}` +(reserved) :math:`\hex{E9}` +(reserved) :math:`\hex{EA}` +(reserved) :math:`\hex{EB}` +(reserved) :math:`\hex{EC}` +(reserved) :math:`\hex{ED}` +(reserved) :math:`\hex{EE}` +(reserved) :math:`\hex{EF}` +(reserved) :math:`\hex{F0}` +(reserved) :math:`\hex{F1}` +(reserved) :math:`\hex{F2}` +(reserved) :math:`\hex{F3}` +(reserved) :math:`\hex{F4}` +(reserved) :math:`\hex{F5}` +(reserved) :math:`\hex{F6}` +(reserved) :math:`\hex{F7}` +(reserved) :math:`\hex{F8}` +(reserved) :math:`\hex{F9}` +(reserved) :math:`\hex{FA}` +(reserved) :math:`\hex{FB}` +:math:`\I32.\TRUNC\K{\_sat\_}\F32\K{\_s}` :math:`\hex{FC}~\hex{00}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_sat\_}\F32\K{\_u}` :math:`\hex{FC}~\hex{01}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_sat\_}\F64\K{\_s}` :math:`\hex{FC}~\hex{02}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_sat\_}\F64\K{\_u}` :math:`\hex{FC}~\hex{03}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_sat\_}\F32\K{\_s}` :math:`\hex{FC}~\hex{04}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_sat\_}\F32\K{\_u}` :math:`\hex{FC}~\hex{05}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_sat\_}\F64\K{\_s}` :math:`\hex{FC}~\hex{06}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_sat\_}\F64\K{\_u}` :math:`\hex{FC}~\hex{07}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\MEMORYINIT~x` :math:`\hex{FC}~\hex{08}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\DATADROP~x` :math:`\hex{FC}~\hex{09}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` +:math:`\MEMORYCOPY` :math:`\hex{FC}~\hex{0A}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\MEMORYFILL` :math:`\hex{FC}~\hex{0B}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\TABLEINIT~x~y` :math:`\hex{FC}~\hex{0C}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\ELEMDROP~x` :math:`\hex{FC}~\hex{0D}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` +:math:`\TABLECOPY~x~y` :math:`\hex{FC}~\hex{0E}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\TABLEGROW~x` :math:`\hex{FC}~\hex{0F}` :math:`[t~\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\TABLESIZE~x` :math:`\hex{FC}~\hex{10}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\TABLEFILL~x` :math:`\hex{FC}~\hex{11}` :math:`[\I32~t~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD~\memarg` :math:`\hex{FD}~~\hex{00}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{8x8\_s}~\memarg` :math:`\hex{FD}~~\hex{01}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{8x8\_u}~\memarg` :math:`\hex{FD}~~\hex{02}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{16x4\_s}~\memarg` :math:`\hex{FD}~~\hex{03}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{16x4\_u}~\memarg` :math:`\hex{FD}~~\hex{04}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32x2\_s}~\memarg` :math:`\hex{FD}~~\hex{05}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32x2\_u}~\memarg` :math:`\hex{FD}~~\hex{06}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{8\_splat}~\memarg` :math:`\hex{FD}~~\hex{07}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{16\_splat}~\memarg` :math:`\hex{FD}~~\hex{08}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32\_splat}~\memarg` :math:`\hex{FD}~~\hex{09}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{64\_splat}~\memarg` :math:`\hex{FD}~~\hex{0A}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE~\memarg` :math:`\hex{FD}~~\hex{0B}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\VCONST~\i128` :math:`\hex{FD}~~\hex{0C}` :math:`[] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\SHUFFLE~\laneidx^{16}` :math:`\hex{FD}~~\hex{0D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\SWIZZLE` :math:`\hex{FD}~~\hex{0E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\SPLAT` :math:`\hex{FD}~~\hex{0F}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\SPLAT` :math:`\hex{FD}~~\hex{10}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\SPLAT` :math:`\hex{FD}~~\hex{11}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\SPLAT` :math:`\hex{FD}~~\hex{12}` :math:`[\I64] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\SPLAT` :math:`\hex{FD}~~\hex{13}` :math:`[\F32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F64X2.\SPLAT` :math:`\hex{FD}~~\hex{14}` :math:`[\F64] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\EXTRACTLANE\K{\_s}~\laneidx` :math:`\hex{FD}~~\hex{15}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\EXTRACTLANE\K{\_u}~\laneidx` :math:`\hex{FD}~~\hex{16}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{17}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTRACTLANE\K{\_s}~\laneidx` :math:`\hex{FD}~~\hex{18}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTRACTLANE\K{\_u}~\laneidx` :math:`\hex{FD}~~\hex{19}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1A}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1B}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1C}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1D}` :math:`[\V128] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1E}` :math:`[\V128~\I64] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1F}` :math:`[\V128] \to [\F32]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{20}` :math:`[\V128~\F32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F64X2.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{21}` :math:`[\V128] \to [\F64]` :ref:`validation ` :ref:`execution ` +:math:`\F64X2.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{22}` :math:`[\V128~\F64] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\VEQ` :math:`\hex{FD}~~\hex{23}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VNE` :math:`\hex{FD}~~\hex{24}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{25}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{26}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{27}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{28}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{29}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{2A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{2B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{2C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VEQ` :math:`\hex{FD}~~\hex{2D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VNE` :math:`\hex{FD}~~\hex{2E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{2F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{30}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{31}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{32}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{33}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{34}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{35}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{36}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VEQ` :math:`\hex{FD}~~\hex{37}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VNE` :math:`\hex{FD}~~\hex{38}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{39}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{3A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{3B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{3C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{3D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{3E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{3F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{40}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VEQ` :math:`\hex{FD}~~\hex{41}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VNE` :math:`\hex{FD}~~\hex{42}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VLT` :math:`\hex{FD}~~\hex{43}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VGT` :math:`\hex{FD}~~\hex{44}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VLE` :math:`\hex{FD}~~\hex{45}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VGE` :math:`\hex{FD}~~\hex{46}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VEQ` :math:`\hex{FD}~~\hex{47}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VNE` :math:`\hex{FD}~~\hex{48}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VLT` :math:`\hex{FD}~~\hex{49}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VGT` :math:`\hex{FD}~~\hex{4A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VLE` :math:`\hex{FD}~~\hex{4B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VGE` :math:`\hex{FD}~~\hex{4C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VNOT` :math:`\hex{FD}~~\hex{4D}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VAND` :math:`\hex{FD}~~\hex{4E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VANDNOT` :math:`\hex{FD}~~\hex{4F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VOR` :math:`\hex{FD}~~\hex{50}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VXOR` :math:`\hex{FD}~~\hex{51}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\BITSELECT` :math:`\hex{FD}~~\hex{52}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\ANYTRUE` :math:`\hex{FD}~~\hex{53}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{54}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{55}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{56}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{57}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{58}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{59}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5A}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5B}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5C}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{64\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5D}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\VDEMOTE\K{\_f64x2\_zero}` :math:`\hex{FD}~~\hex{5E}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPROMOTE\K{\_low\_f32x4}` :math:`\hex{FD}~~\hex{5F}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VABS` :math:`\hex{FD}~~\hex{60}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VNEG` :math:`\hex{FD}~~\hex{61}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VPOPCNT` :math:`\hex{FD}~~\hex{62}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\ALLTRUE` :math:`\hex{FD}~~\hex{63}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\BITMASK` :math:`\hex{FD}~~\hex{64}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\NARROW\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{65}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\NARROW\K{\_i16x8\_u}` :math:`\hex{FD}~~\hex{66}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\VCEIL` :math:`\hex{FD}~~\hex{67}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VFLOOR` :math:`\hex{FD}~~\hex{68}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VTRUNC` :math:`\hex{FD}~~\hex{69}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VNEAREST` :math:`\hex{FD}~~\hex{6A}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSHL` :math:`\hex{FD}~~\hex{6B}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{6C}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{6D}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VADD` :math:`\hex{FD}~~\hex{6E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VADD\K{\_sat\_s}` :math:`\hex{FD}~~\hex{6F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VADD\K{\_sat\_u}` :math:`\hex{FD}~~\hex{70}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSUB` :math:`\hex{FD}~~\hex{71}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~\hex{72}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~\hex{73}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VCEIL` :math:`\hex{FD}~~\hex{74}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VFLOOR` :math:`\hex{FD}~~\hex{75}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{76}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{77}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{78}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{79}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VTRUNC` :math:`\hex{FD}~~\hex{7A}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\AVGR\K{\_u}` :math:`\hex{FD}~~\hex{7B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}` :math:`\hex{FD}~~\hex{7C}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}` :math:`\hex{FD}~~\hex{7D}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{7E}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}` :math:`\hex{FD}~~\hex{7F}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VABS` :math:`\hex{FD}~~\hex{80}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VNEG` :math:`\hex{FD}~~\hex{81}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\Q15MULRSAT\K{\_s}` :math:`\hex{FD}~~\hex{82}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\ALLTRUE` :math:`\hex{FD}~~\hex{83}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\BITMASK` :math:`\hex{FD}~~\hex{84}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\NARROW\K{\_i32x4\_s}` :math:`\hex{FD}~~\hex{85}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\NARROW\K{\_i32x4\_u}` :math:`\hex{FD}~~\hex{86}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~\hex{87}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~\hex{88}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~\hex{89}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~\hex{8A}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VSHL` :math:`\hex{FD}~~\hex{8B}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{8C}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{8D}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VADD` :math:`\hex{FD}~~\hex{8E}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VADD\K{\_sat\_s}` :math:`\hex{FD}~~\hex{8F}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VADD\K{\_sat\_u}` :math:`\hex{FD}~~\hex{90}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSUB` :math:`\hex{FD}~~\hex{91}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~\hex{92}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~\hex{93}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VNEAREST` :math:`\hex{FD}~~\hex{94}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMUL` :math:`\hex{FD}~~\hex{95}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{96}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{97}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{98}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{99}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\AVGR\K{\_u}` :math:`\hex{FD}~~\hex{9B}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~\hex{9C}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~\hex{9D}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~\hex{9E}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~\hex{9F}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VABS` :math:`\hex{FD}~~\hex{A0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VNEG` :math:`\hex{FD}~~\hex{A1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\ALLTRUE` :math:`\hex{FD}~~\hex{A3}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\BITMASK` :math:`\hex{FD}~~\hex{A4}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~\hex{A7}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~\hex{A8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~\hex{A9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~\hex{AA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VSHL` :math:`\hex{FD}~~\hex{AB}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{AC}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{AD}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VADD` :math:`\hex{FD}~~\hex{AE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VSUB` :math:`\hex{FD}~~\hex{B1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMUL` :math:`\hex{FD}~~\hex{B5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{B6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{B7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{B8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{B9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\DOT\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{BA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~\hex{BC}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~\hex{BD}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~\hex{BE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~\hex{BF}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VABS` :math:`\hex{FD}~~\hex{C0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VNEG` :math:`\hex{FD}~~\hex{C1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\ALLTRUE` :math:`\hex{FD}~~\hex{C3}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\BITMASK` :math:`\hex{FD}~~\hex{C4}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{C7}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~\hex{C8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{C9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~\hex{CA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VSHL` :math:`\hex{FD}~~\hex{CB}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{CC}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{CD}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VADD` :math:`\hex{FD}~~\hex{CE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VSUB` :math:`\hex{FD}~~\hex{D1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VMUL` :math:`\hex{FD}~~\hex{D5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VEQ` :math:`\hex{FD}~~\hex{D6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VNE` :math:`\hex{FD}~~\hex{D7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{D8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{D9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{DA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{DB}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{DC}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~\hex{DD}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{DE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~\hex{DF}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\VABS` :math:`\hex{FD}~~\hex{E0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VNEG` :math:`\hex{FD}~~\hex{E1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VSQRT` :math:`\hex{FD}~~\hex{E3}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VADD` :math:`\hex{FD}~~\hex{E4}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VSUB` :math:`\hex{FD}~~\hex{E5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VMUL` :math:`\hex{FD}~~\hex{E6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VDIV` :math:`\hex{FD}~~\hex{E7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VMIN` :math:`\hex{FD}~~\hex{E8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VMAX` :math:`\hex{FD}~~\hex{E9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VPMIN` :math:`\hex{FD}~~\hex{EA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VPMAX` :math:`\hex{FD}~~\hex{EB}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VABS` :math:`\hex{FD}~~\hex{EC}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VNEG` :math:`\hex{FD}~~\hex{ED}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VSQRT` :math:`\hex{FD}~~\hex{EF}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VADD` :math:`\hex{FD}~~\hex{F0}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VSUB` :math:`\hex{FD}~~\hex{F1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VMUL` :math:`\hex{FD}~~\hex{F2}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VDIV` :math:`\hex{FD}~~\hex{F3}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VMIN` :math:`\hex{FD}~~\hex{F4}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VMAX` :math:`\hex{FD}~~\hex{F5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPMIN` :math:`\hex{FD}~~\hex{F6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPMAX` :math:`\hex{FD}~~\hex{F7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_s}` :math:`\hex{FD}~~\hex{F8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_u}` :math:`\hex{FD}~~\hex{F9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VCONVERT\K{\_i32x4\_s}` :math:`\hex{FD}~~\hex{FA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VCONVERT\K{\_i32x4\_u}` :math:`\hex{FD}~~\hex{FB}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_s\_zero}` :math:`\hex{FD}~~\hex{FC}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}` :math:`\hex{FD}~~\hex{FD}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{FE}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{FF}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\RELAXEDSWIZZLE` :math:`\hex{FD}~~\hex{80}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RELAXEDTRUNC\K{\_f32x4\_s}` :math:`\hex{FD}~~\hex{81}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RELAXEDTRUNC\K{\_f32x4\_u}` :math:`\hex{FD}~~\hex{82}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RELAXEDTRUNC\K{\_f64x2\_s}` :math:`\hex{FD}~~\hex{83}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RELAXEDTRUNC\K{\_f64x2\_u}` :math:`\hex{FD}~~\hex{84}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\RELAXEDMADD` :math:`\hex{FD}~~\hex{85}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\RELAXEDNMADD` :math:`\hex{FD}~~\hex{86}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\RELAXEDMADD` :math:`\hex{FD}~~\hex{87}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\RELAXEDNMADD` :math:`\hex{FD}~~\hex{88}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\RELAXEDLANESELECT` :math:`\hex{FD}~~\hex{89}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\RELAXEDLANESELECT` :math:`\hex{FD}~~\hex{8A}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RELAXEDLANESELECT` :math:`\hex{FD}~~\hex{8B}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\RELAXEDLANESELECT` :math:`\hex{FD}~~\hex{8C}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\RELAXEDMIN` :math:`\hex{FD}~~\hex{8D}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\RELAXEDMAX` :math:`\hex{FD}~~\hex{8E}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\RELAXEDMIN` :math:`\hex{FD}~~\hex{8F}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\RELAXEDMAX` :math:`\hex{FD}~~\hex{90}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\RELAXEDQ15MULRS` :math:`\hex{FD}~~\hex{91}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_s}` :math:`\hex{FD}~~\hex{92}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s}` :math:`\hex{FD}~~\hex{93}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +==================================================== ==================================== ============================================= ============================================= ====================================================================== .. note:: Multi-byte opcodes are given with the shortest possible encoding in the table. diff --git a/document/core/binary/instructions.rst b/document/core/binary/instructions.rst index 9c9bd18b8..e943402f5 100644 --- a/document/core/binary/instructions.rst +++ b/document/core/binary/instructions.rst @@ -841,26 +841,26 @@ All other vector instructions are plain opcodes without any immediates. .. math:: \begin{array}{llclll} \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|& - \hex{FD}~~256{:}\Bu32 &\Rightarrow& \I16X8.\RSWIZZLE \\ &&|& - \hex{FD}~~257{:}\Bu32 &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_s} \\ &&|& - \hex{FD}~~258{:}\Bu32 &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_u} \\ &&|& - \hex{FD}~~259{:}\Bu32 &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_s\_zero} \\ &&|& - \hex{FD}~~260{:}\Bu32 &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_u\_zero} \\ &&|& - \hex{FD}~~261{:}\Bu32 &\Rightarrow& \F32X4.\RMADD \\ &&|& - \hex{FD}~~262{:}\Bu32 &\Rightarrow& \F32X4.\RNMADD \\ &&|& - \hex{FD}~~263{:}\Bu32 &\Rightarrow& \F64X2.\RMADD \\ &&|& - \hex{FD}~~264{:}\Bu32 &\Rightarrow& \F64X2.\RNMADD \\ &&|& - \hex{FD}~~265{:}\Bu32 &\Rightarrow& \I8X16.\RLANESELECT \\ &&|& - \hex{FD}~~266{:}\Bu32 &\Rightarrow& \I16X8.\RLANESELECT \\ &&|& - \hex{FD}~~267{:}\Bu32 &\Rightarrow& \I32X4.\RLANESELECT \\ &&|& - \hex{FD}~~268{:}\Bu32 &\Rightarrow& \I64X2.\RLANESELECT \\ &&|& - \hex{FD}~~269{:}\Bu32 &\Rightarrow& \F32X4.\RMIN \\ &&|& - \hex{FD}~~270{:}\Bu32 &\Rightarrow& \F32X4.\RMAX \\ &&|& - \hex{FD}~~271{:}\Bu32 &\Rightarrow& \F64X2.\RMIN \\ &&|& - \hex{FD}~~272{:}\Bu32 &\Rightarrow& \F64X2.\RMAX \\ &&|& - \hex{FD}~~273{:}\Bu32 &\Rightarrow& \I16X8.\RQ15MULRS \\ &&|& - \hex{FD}~~274{:}\Bu32 &\Rightarrow& \I16X8.\RDOT\K{\_i8x16\_i7x16\_s} \\ &&|& - \hex{FD}~~275{:}\Bu32 &\Rightarrow& \I16X8.\RDOT\K{\_i8x16\_i7x16\_add\_s} \\ + \hex{FD}~~256{:}\Bu32 &\Rightarrow& \I16X8.\RELAXEDSWIZZLE \\ &&|& + \hex{FD}~~257{:}\Bu32 &\Rightarrow& \I32X4.\RELAXEDTRUNC\K{\_f32x4\_s} \\ &&|& + \hex{FD}~~258{:}\Bu32 &\Rightarrow& \I32X4.\RELAXEDTRUNC\K{\_f32x4\_u} \\ &&|& + \hex{FD}~~259{:}\Bu32 &\Rightarrow& \I32X4.\RELAXEDTRUNC\K{\_f32x4\_s\_zero} \\ &&|& + \hex{FD}~~260{:}\Bu32 &\Rightarrow& \I32X4.\RELAXEDTRUNC\K{\_f32x4\_u\_zero} \\ &&|& + \hex{FD}~~261{:}\Bu32 &\Rightarrow& \F32X4.\RELAXEDMADD \\ &&|& + \hex{FD}~~262{:}\Bu32 &\Rightarrow& \F32X4.\RELAXEDNMADD \\ &&|& + \hex{FD}~~263{:}\Bu32 &\Rightarrow& \F64X2.\RELAXEDMADD \\ &&|& + \hex{FD}~~264{:}\Bu32 &\Rightarrow& \F64X2.\RELAXEDNMADD \\ &&|& + \hex{FD}~~265{:}\Bu32 &\Rightarrow& \I8X16.\RELAXEDLANESELECT \\ &&|& + \hex{FD}~~266{:}\Bu32 &\Rightarrow& \I16X8.\RELAXEDLANESELECT \\ &&|& + \hex{FD}~~267{:}\Bu32 &\Rightarrow& \I32X4.\RELAXEDLANESELECT \\ &&|& + \hex{FD}~~268{:}\Bu32 &\Rightarrow& \I64X2.\RELAXEDLANESELECT \\ &&|& + \hex{FD}~~269{:}\Bu32 &\Rightarrow& \F32X4.\RELAXEDMIN \\ &&|& + \hex{FD}~~270{:}\Bu32 &\Rightarrow& \F32X4.\RELAXEDMAX \\ &&|& + \hex{FD}~~271{:}\Bu32 &\Rightarrow& \F64X2.\RELAXEDMIN \\ &&|& + \hex{FD}~~272{:}\Bu32 &\Rightarrow& \F64X2.\RELAXEDMAX \\ &&|& + \hex{FD}~~273{:}\Bu32 &\Rightarrow& \I16X8.\RELAXEDQ15MULRS \\ &&|& + \hex{FD}~~274{:}\Bu32 &\Rightarrow& \I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_s} \\ &&|& + \hex{FD}~~275{:}\Bu32 &\Rightarrow& \I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s} \\ \end{array} diff --git a/document/core/exec/instructions.rst b/document/core/exec/instructions.rst index 654dbaeb1..b96ed4f48 100644 --- a/document/core/exec/instructions.rst +++ b/document/core/exec/instructions.rst @@ -405,10 +405,10 @@ Most vector instructions are defined in terms of generic numeric operators appli \end{array} -.. _exec-vec-rswizzle: +.. _exec-relaxed_swizzle: -:math:`\K{i8x16.}\RSWIZZLE` -........................... +:math:`\K{i8x16.}\RELAXEDSWIZZLE` +................................. 1. Assert: due to :ref:`validation `, two values of :ref:`value type ` |V128| are on the top of the stack. @@ -643,8 +643,8 @@ Most vector instructions are defined in terms of generic numeric operators appli .. _exec-rlaneselect: -:math:`t\K{x}N\K{.}\RLANESELECT` -................................ +:math:`t\K{x}N\K{.}\RELAXEDLANESELECT` +...................................... 1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. @@ -663,7 +663,7 @@ Most vector instructions are defined in terms of generic numeric operators appli .. math:: \begin{array}{l} \begin{array}{lcl@{\qquad}l} - (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\V128\K{.}\RLANESELECT &\stepto& (\V128\K{.}\VCONST~c) & \\ + (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\V128\K{.}\RELAXEDLANESELECT &\stepto& (\V128\K{.}\VCONST~c) & \\ \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} @@ -955,13 +955,13 @@ where: \end{array} -.. _exec-vec-rdot: +.. _exec-relaxed_dot: -:math:`\K{i16x8.}\RDOT\K{\_i8x16\_i7x16\_s}` -................................................... +:math:`\K{i16x8.}\RELAXEDDOT\K{\_i8x16\_i7x16\_s}` +.................................................. -1. Assert: due to :ref:`validation `, two values of :ref:`value type ` |V128| are on the top of the stack. +1. Assert: due to :ref:`validation `, two values of :ref:`value type ` |V128| are on the top of the stack. 2. Pop the value :math:`\V128.\VCONST~c_2` from the stack. @@ -978,7 +978,7 @@ where: .. math:: \begin{array}{l} \begin{array}{llcl@{\qquad}l} - & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i16x8.}\RDOT\K{\_i8x16\_i7x16\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ + & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i16x8.}\RELAXEDDOT\K{\_i8x16\_i7x16\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} @@ -989,10 +989,10 @@ where: \end{array} -:math:`\K{i32x4.}\RDOT\K{\_i8x16\_i7x16\_add\_s}` -........................................................ +:math:`\K{i32x4.}\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s}` +....................................................... -1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. +1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. 2. Pop the value :math:`\V128.\VCONST~c_3` from the stack. @@ -1013,7 +1013,7 @@ where: .. math:: \begin{array}{l} \begin{array}{llcl@{\qquad}l} - & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\K{i32x4.}\RDOT\K{\_i8x16\_i7x16\_add\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ + & (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~(\V128\K{.}\VCONST~c_3)~\K{i32x4.}\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s} &\stepto& (\V128\K{.}\VCONST~c) \\ \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst index 49fd639a7..f5ea8454a 100644 --- a/document/core/syntax/instructions.rst +++ b/document/core/syntax/instructions.rst @@ -276,12 +276,12 @@ Vector instructions (also known as *SIMD* instructions, *single instruction mult \K{f32x4.}\VDEMOTE\K{\_f64x2\_zero} \\&&|& \K{f64x2.}\VCONVERT\K{\_low\_i32x4\_}\sx ~|~ \K{f64x2.}\VPROMOTE\K{\_low\_f32x4} \\ - & &|& \K{i8x16.}\RSWIZZLE \\ - & &|& \K{i16x8.}\RQ15MULRS \\ - & &|& \K{i32x4.}\RTRUNC\K{\_f32x4\_}\sx \\ - & &|& \K{i16x8.}\RDOT\K{\_i8x16\_i7x16\_s} \\ - & &|& \K{i32x4.}\RDOT\K{\_i8x16\_i7x16\_add\_s} \\ - & &|& \ishape\K{.}\RLANESELECT \\ + & &|& \K{i8x16.}\RELAXEDSWIZZLE \\ + & &|& \K{i16x8.}\RELAXEDQ15MULRS \\ + & &|& \K{i32x4.}\RELAXEDTRUNC\K{\_f32x4\_}\sx \\ + & &|& \K{i16x8.}\RELAXEDDOT\K{\_i8x16\_i7x16\_s} \\ + & &|& \K{i32x4.}\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s} \\ + & &|& \ishape\K{.}\RELAXEDLANESELECT \\ & &|& \fshape\K{.}\rvfternop \\ & &|& \fshape\K{.}\rvfbinop \\ & &|& \dots \\ @@ -420,7 +420,7 @@ Occasionally, it is convenient to group operators together according to the foll \VMUL ~|~ \AVGR\K{\_u} ~|~ \Q15MULRSAT\K{\_s} \\&&|& - \RQ15MULRS\K{\_s} \\ + \RELAXEDQ15MULRS\K{\_s} \\ \production{ternary operator} & \vternop &::=& \vvternop ~|~ \rvfternop \\ @@ -434,7 +434,7 @@ Occasionally, it is convenient to group operators together according to the foll \VCONVERT ~|~ \VDEMOTE ~|~ \VPROMOTE ~|~ - \RTRUNC \\ + \RELAXEDTRUNC \\ \end{array} diff --git a/document/core/text/instructions.rst b/document/core/text/instructions.rst index 2ec4a83c4..91db92fc7 100644 --- a/document/core/text/instructions.rst +++ b/document/core/text/instructions.rst @@ -897,26 +897,26 @@ Vector constant instructions have a mandatory :ref:`shape ` de .. math:: \begin{array}{llclll} \phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforvectext} && \phantom{vechasreallyreallyreallylonginstructionnames} \\[-2ex] &&|& - \text{i16x8.relaxed\_swizzle} &\Rightarrow& \I16X8.\RSWIZZLE \\ &&|& - \text{i32x4.relaxed\_trunc\_f32x4\_s} &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_s} \\ &&|& - \text{i32x4.relaxed\_trunc\_f32x4\_u} &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_u} \\ &&|& - \text{i32x4.relaxed\_trunc\_f32x4\_s\_zero} &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_s\_zero} \\ &&|& - \text{i32x4.relaxed\_trunc\_f32x4\_u\_zero} &\Rightarrow& \I32X4.\RTRUNC\K{\_f32x4\_u\_zero} \\ &&|& - \text{f32x4.relaxed\_madd} &\Rightarrow& \F32X4.\RMADD \\ &&|& - \text{f32x4.relaxed\_nmadd} &\Rightarrow& \F32X4.\RNMADD \\ &&|& - \text{f64x2.relaxed\_madd} &\Rightarrow& \F64X2.\RMADD \\ &&|& - \text{f64x2.relaxed\_nmadd} &\Rightarrow& \F64X2.\RNMADD \\ &&|& - \text{i8x16.relaxed\_laneselect} &\Rightarrow& \I8X16.\RLANESELECT \\ &&|& - \text{i16x8.relaxed\_laneselect} &\Rightarrow& \I16X8.\RLANESELECT \\ &&|& - \text{i32x4.relaxed\_laneselect} &\Rightarrow& \I32X4.\RLANESELECT \\ &&|& - \text{i64x2.relaxed\_laneselect} &\Rightarrow& \I64X2.\RLANESELECT \\ &&|& - \text{f32x4.relaxed\_min} &\Rightarrow& \F32X4.\RMIN \\ &&|& - \text{f32x4.relaxed\_max} &\Rightarrow& \F32X4.\RMAX \\ &&|& - \text{f64x2.relaxed\_min} &\Rightarrow& \F64X2.\RMIN \\ &&|& - \text{f64x2.relaxed\_max} &\Rightarrow& \F64X2.\RMAX \\ &&|& - \text{i16x8.relaxed\_q15mulr\_s} &\Rightarrow& \I16X8.\RQ15MULRS \\ &&|& - \text{i16x8.relaxed\_dot\_i8x16\_i7x16\_s} &\Rightarrow& \I16X8.\RDOT\K{\_i8x16\_i7x16\_s} \\ &&|& - \text{i16x8.relaxed\_dot\_i8x16\_i7x16\_add\_s} &\Rightarrow& \I16X8.\RDOT\K{\_i8x16\_i7x16\_add\_s} + \text{i16x8.relaxed\_swizzle} &\Rightarrow& \I16X8.\RELAXEDSWIZZLE \\ &&|& + \text{i32x4.relaxed\_trunc\_f32x4\_s} &\Rightarrow& \I32X4.\RELAXEDTRUNC\K{\_f32x4\_s} \\ &&|& + \text{i32x4.relaxed\_trunc\_f32x4\_u} &\Rightarrow& \I32X4.\RELAXEDTRUNC\K{\_f32x4\_u} \\ &&|& + \text{i32x4.relaxed\_trunc\_f32x4\_s\_zero} &\Rightarrow& \I32X4.\RELAXEDTRUNC\K{\_f32x4\_s\_zero} \\ &&|& + \text{i32x4.relaxed\_trunc\_f32x4\_u\_zero} &\Rightarrow& \I32X4.\RELAXEDTRUNC\K{\_f32x4\_u\_zero} \\ &&|& + \text{f32x4.relaxed\_madd} &\Rightarrow& \F32X4.\RELAXEDMADD \\ &&|& + \text{f32x4.relaxed\_nmadd} &\Rightarrow& \F32X4.\RELAXEDNMADD \\ &&|& + \text{f64x2.relaxed\_madd} &\Rightarrow& \F64X2.\RELAXEDMADD \\ &&|& + \text{f64x2.relaxed\_nmadd} &\Rightarrow& \F64X2.\RELAXEDNMADD \\ &&|& + \text{i8x16.relaxed\_laneselect} &\Rightarrow& \I8X16.\RELAXEDLANESELECT \\ &&|& + \text{i16x8.relaxed\_laneselect} &\Rightarrow& \I16X8.\RELAXEDLANESELECT \\ &&|& + \text{i32x4.relaxed\_laneselect} &\Rightarrow& \I32X4.\RELAXEDLANESELECT \\ &&|& + \text{i64x2.relaxed\_laneselect} &\Rightarrow& \I64X2.\RELAXEDLANESELECT \\ &&|& + \text{f32x4.relaxed\_min} &\Rightarrow& \F32X4.\RELAXEDMIN \\ &&|& + \text{f32x4.relaxed\_max} &\Rightarrow& \F32X4.\RELAXEDMAX \\ &&|& + \text{f64x2.relaxed\_min} &\Rightarrow& \F64X2.\RELAXEDMIN \\ &&|& + \text{f64x2.relaxed\_max} &\Rightarrow& \F64X2.\RELAXEDMAX \\ &&|& + \text{i16x8.relaxed\_q15mulr\_s} &\Rightarrow& \I16X8.\RELAXEDQ15MULRS \\ &&|& + \text{i16x8.relaxed\_dot\_i8x16\_i7x16\_s} &\Rightarrow& \I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_s} \\ &&|& + \text{i16x8.relaxed\_dot\_i8x16\_i7x16\_add\_s} &\Rightarrow& \I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s} \end{array} diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 9e213948e..4aa95e05e 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -499,15 +499,15 @@ .. |EXTADDPAIRWISE| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{extadd\_pairwise}} .. |VDEMOTE| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{demote}} .. |VPROMOTE| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{promote}} -.. |RMADD| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_madd}} -.. |RNMADD| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_nmadd}} -.. |RSWIZZLE| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_swizzle}} -.. |RLANESELECT| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_laneselect}} -.. |RMIN| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_min}} -.. |RMAX| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_max}} -.. |RQ15MULRS| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_q15mulr\_s}} -.. |RTRUNC| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_trunc}} -.. |RDOT| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_dot}} +.. |RELAXEDMADD| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_madd}} +.. |RELAXEDNMADD| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_nmadd}} +.. |RELAXEDSWIZZLE| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_swizzle}} +.. |RELAXEDLANESELECT| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_laneselect}} +.. |RELAXEDMIN| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_min}} +.. |RELAXEDMAX| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_max}} +.. |RELAXEDQ15MULRS| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_q15mulr\_s}} +.. |RELAXEDTRUNC| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_trunc}} +.. |RELAXEDDOT| mathdef:: \xref{syntax/instructions}{syntax-instr-vec}{\K{relaxed\_dot}} .. Instructions, non-terminals diff --git a/document/core/valid/instructions.rst b/document/core/valid/instructions.rst index 33222a3b8..d8e8f2b7d 100644 --- a/document/core/valid/instructions.rst +++ b/document/core/valid/instructions.rst @@ -362,9 +362,9 @@ The following auxiliary function denotes the number of lanes in a vector shape, } -.. _valid-vec-rswizzle: +.. _valid-relaxed_swizzle: -:math:`\K{i8x16.}\RSWIZZLE` +:math:`\K{i8x16.}\RELAXEDSWIZZLE` ................................... * The instruction is valid with type :math:`[\V128~\V128] \to [\V128]`. @@ -372,7 +372,7 @@ The following auxiliary function denotes the number of lanes in a vector shape, .. math:: \frac{ }{ - C \vdashinstr \K{i8x16.}\RSWIZZLE : [\V128~\V128] \to [\V128] + C \vdashinstr \K{i8x16.}\RELAXEDSWIZZLE : [\V128~\V128] \to [\V128] } @@ -489,7 +489,7 @@ The following auxiliary function denotes the number of lanes in a vector shape, .. _valid-rlaneselect: -:math:`\shape\K{.}\RLANESELECT` +:math:`\shape\K{.}\RELAXEDLANESELECT` ............................... * The instruction is valid with type :math:`[\V128~\V128~\V128] \to [\V128]`. @@ -599,7 +599,7 @@ The following auxiliary function denotes the number of lanes in a vector shape, } -.. _valid-vec-rdot: +.. _valid-relaxed_dot: :math:`\ishape_1\K{.}\DOT\K{\_}\ishape_2\_\K{i7x16\_s}` ....................................................... From a1a8a127489a45e987c06f77b594dbb9cdc9b45b Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 17:43:00 +0000 Subject: [PATCH 084/117] Fix text --- document/core/exec/numerics.rst | 21 ++++++++++----------- document/core/valid/instructions.rst | 6 +++--- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 519396b9e..b17e32fd1 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -1994,7 +1994,7 @@ each environment globally chooses a fixed projection for each operator. :math:`\frmadd_N(z_1, z_2, z_3)` ................................ -Relaxed Multiply Add (madd) allows for fused or unfused results. :math:`fma` is +Relaxed multiply-add (madd) allows for fused or unfused results. The function :math:`fma` is defined by |IEEE754|_ (Section 5.4.1) as *fusedMultiplyAdd*. .. math:: @@ -2033,8 +2033,8 @@ if the signed interpretation of the index is less than 16 (including negative va \EXPROFDET & relaxed\_swizzle\_lane(i^n, j) &=& [ 0, i[j \mod n] ] & (\otherwise) \\ & relaxed\_swizzle\_lane(i^n, j) &=& 0 & (\otherwise) \\ \\ - & \rswizzle(a^n, s^n) &=& rsl_0 \dots rsl_{n-1} \\ - & \qquad \where rsl_i &=& relaxed\_swizzle\_lane(a^n, s^n[i]) + & \rswizzle(a^n, s^n) &=& \X{rsl}_0 \dots \X{rsl}_{n-1} \\ + & \qquad \where \X{rsl}_i &=& relaxed\_swizzle\_lane(a^n, s^n[i]) \end{array} @@ -2044,8 +2044,8 @@ if the signed interpretation of the index is less than 16 (including negative va :math:`\rtrunc^u_{M,N}(z)` .......................... -Relaxed truncate converts float to int, NaN and out of range values are -hardware dependent. +Relaxed unsigned truncation converts floating point numbers to integers. +The result for NaN's and out-of-range values is host-dependent. .. math:: \begin{array}{@{}llcll} @@ -2078,9 +2078,9 @@ The result for NaN's and out-of-range values is host-dependent. :math:`\rlaneselect_B(a^n, b^n, c^n)` ..................................... -Relaxed lane select is deterministic where all bits are set or unset in the -mask. Otherwise depending on hardware, either only the top bit is examined, or -all bits are examined (becomes a bitselect). +Relaxed lane selection is deterministic when all bits are set or unset in the +mask. Otherwise depending on the host, either only the top bit is examined, or +all bits are examined (i.e. it becomes a bit select). .. math:: \begin{array}{@{}llcll} @@ -2100,9 +2100,8 @@ all bits are examined (becomes a bitselect). :math:`\frmin_N(z_1, z_2)` .......................... -Relaxed min differs from min when inputs are NaNs or different -signs of 0. It allows for implementation to return the first or second input -when either input is a NaN. +Relaxed minimum differs from regular minimum when inputs are NaN's or zeroes with different signs. +It allows for implementation to return the first or second input when either input is a NaN. .. math:: \begin{array}{@{}llcll} diff --git a/document/core/valid/instructions.rst b/document/core/valid/instructions.rst index d8e8f2b7d..ed09468be 100644 --- a/document/core/valid/instructions.rst +++ b/document/core/valid/instructions.rst @@ -365,7 +365,7 @@ The following auxiliary function denotes the number of lanes in a vector shape, .. _valid-relaxed_swizzle: :math:`\K{i8x16.}\RELAXEDSWIZZLE` -................................... +................................. * The instruction is valid with type :math:`[\V128~\V128] \to [\V128]`. @@ -490,14 +490,14 @@ The following auxiliary function denotes the number of lanes in a vector shape, .. _valid-rlaneselect: :math:`\shape\K{.}\RELAXEDLANESELECT` -............................... +..................................... * The instruction is valid with type :math:`[\V128~\V128~\V128] \to [\V128]`. .. math:: \frac{ }{ - C \vdashinstr \shape\K{.}\vternop : [\V128~\V128~\V128] \to [\V128] + C \vdashinstr \shape\K{.}\RELAXEDLANESELECT : [\V128~\V128~\V128] \to [\V128] } From 2c51978376a065f99b3addf1bcf0ac0a66a3bb06 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 17:46:32 +0000 Subject: [PATCH 085/117] Fix relaxed swizzle lane macro --- document/core/exec/numerics.rst | 10 +++++----- document/core/util/macros.def | 1 + 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index b17e32fd1..6560aefc4 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2028,13 +2028,13 @@ if the signed interpretation of the index is less than 16 (including negative va .. math:: \begin{array}{@{}llcll} - & relaxed\_swizzle\_lane(i^n, j) &=& i[j] & (\iff j < 16) \\ - & relaxed\_swizzle\_lane(i^n, j) &=& 0 & (\iff \signed_8(j) < 0) \\ - \EXPROFDET & relaxed\_swizzle\_lane(i^n, j) &=& [ 0, i[j \mod n] ] & (\otherwise) \\ - & relaxed\_swizzle\_lane(i^n, j) &=& 0 & (\otherwise) \\ + & \rswizzlelane(i^n, j) &=& i[j] & (\iff j < 16) \\ + & \rswizzlelane(i^n, j) &=& 0 & (\iff \signed_8(j) < 0) \\ + \EXPROFDET & \rswizzlelane(i^n, j) &=& [ 0, i[j \mod n] ] & (\otherwise) \\ + & \rswizzlelane(i^n, j) &=& 0 & (\otherwise) \\ \\ & \rswizzle(a^n, s^n) &=& \X{rsl}_0 \dots \X{rsl}_{n-1} \\ - & \qquad \where \X{rsl}_i &=& relaxed\_swizzle\_lane(a^n, s^n[i]) + & \qquad \where \X{rsl}_i &=& \rswizzlelane(a^n, s^n[i]) \end{array} diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 4aa95e05e..77a51e35e 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -1205,6 +1205,7 @@ .. |frmadd| mathdef:: \xref{exec/numerics}{op-frmaddd}{\F{frelaxed\_madd}} .. |frnmadd| mathdef:: \xref{exec/numerics}{op-frnmadd}{\F{frelaxed\_nmadd}} +.. |rswizzlelane| mathdef:: \xref{exec/numerics}{op-rswizzle_lane}{\F{relaxed\_swizzle\_lane}} .. |rswizzle| mathdef:: \xref{exec/numerics}{op-rswizzle}{\F{relaxed\_swizzle}} .. |rtrunc| mathdef:: \xref{exec/numerics}{op-rtrunc}{\F{relaxed\_trunc}} .. |rlaneselect| mathdef:: \xref{exec/numerics}{op-rlaneselect}{\F{relaxed\_laneselect}} From 847b40fef72982b64a2018f73d722fedc7a7c733 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 17:47:50 +0000 Subject: [PATCH 086/117] Fix fma det --- document/core/exec/numerics.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 6560aefc4..92c994397 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2000,7 +2000,7 @@ defined by |IEEE754|_ (Section 5.4.1) as *fusedMultiplyAdd*. .. math:: \begin{array}{@{}llcll} \EXPROFDET & \frmadd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), fma_N(z_1, z_2, z_3) ] \\ - & \frmadd_N(z_1, z_2, z_3) &=& \fadd_N(\fmul_N(z_1, z_2), z_3) \\ + & \frmadd_N(z_1, z_2, z_3) &=& fma_N(z_1, z_2, z_3) \\ \end{array} From ce1d31d15180f99a094489303f8f538578866ae5 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 18:03:58 +0000 Subject: [PATCH 087/117] Fix mnemonics --- .../core/appendix/gen-index-instructions.py | 40 +- document/core/appendix/index-instructions.rst | 1060 ++++++++--------- document/core/exec/instructions.rst | 22 +- document/core/exec/numerics.rst | 135 +-- document/core/util/macros.def | 21 +- document/core/valid/instructions.rst | 2 +- 6 files changed, 641 insertions(+), 639 deletions(-) diff --git a/document/core/appendix/gen-index-instructions.py b/document/core/appendix/gen-index-instructions.py index 722c7152c..f16b5d23f 100755 --- a/document/core/appendix/gen-index-instructions.py +++ b/document/core/appendix/gen-index-instructions.py @@ -575,26 +575,26 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}', r'\hex{FD}~~\hex{FD}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_u'), Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_s}', r'\hex{FD}~~\hex{FE}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_s'), Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_u}', r'\hex{FD}~~\hex{FF}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_u'), - Instruction(r'\I8X16.\RELAXEDSWIZZLE', r'\hex{FD}~~\hex{80}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-relaxed_swizzle', r'exec-relaxed_swizzle', r'op-rswizzle'), - Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f32x4\_s}', r'\hex{FD}~~\hex{81}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_s'), - Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f32x4\_u}', r'\hex{FD}~~\hex{82}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_u'), - Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f64x2\_s}', r'\hex{FD}~~\hex{83}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_s'), - Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f64x2\_u}', r'\hex{FD}~~\hex{84}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-rtrunc_u'), - Instruction(r'\F32X4.\RELAXEDMADD', r'\hex{FD}~~\hex{85}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frmadd'), - Instruction(r'\F32X4.\RELAXEDNMADD', r'\hex{FD}~~\hex{86}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frnmadd'), - Instruction(r'\F64X2.\RELAXEDMADD', r'\hex{FD}~~\hex{87}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frmadd'), - Instruction(r'\F64X2.\RELAXEDNMADD', r'\hex{FD}~~\hex{88}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frnmadd'), - Instruction(r'\I8X16.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{89}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), - Instruction(r'\I16X8.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8A}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), - Instruction(r'\I32X4.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8B}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), - Instruction(r'\I64X2.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8C}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-rlaneselect', r'exec-rlaneselect', r'op-rlaneselect'), - Instruction(r'\F32X4.\RELAXEDMIN', r'\hex{FD}~~\hex{8D}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmin'), - Instruction(r'\F32X4.\RELAXEDMAX', r'\hex{FD}~~\hex{8E}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmax'), - Instruction(r'\F64X2.\RELAXEDMIN', r'\hex{FD}~~\hex{8F}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmin'), - Instruction(r'\F64X2.\RELAXEDMAX', r'\hex{FD}~~\hex{90}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frmax'), - Instruction(r'\I16X8.\RELAXEDQ15MULRS', r'\hex{FD}~~\hex{91}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-irq15mulr_s'), - Instruction(r'\I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_s}', r'\hex{FD}~~\hex{92}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-relaxed_dot', r'exec-relaxed_dot', r'op-ridotmul'), - Instruction(r'\I32X4.\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s}', r'\hex{FD}~~\hex{93}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_dot', r'exec-relaxed_dot', r'op-ridotmul'), + Instruction(r'\I8X16.\RELAXEDSWIZZLE', r'\hex{FD}~~\hex{80}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-relaxed_swizzle', r'exec-relaxed_swizzle', r'op-relaxed_swizzle'), + Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f32x4\_s}', r'\hex{FD}~~\hex{81}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_s'), + Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f32x4\_u}', r'\hex{FD}~~\hex{82}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_u'), + Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f64x2\_s}', r'\hex{FD}~~\hex{83}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_s'), + Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f64x2\_u}', r'\hex{FD}~~\hex{84}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_u'), + Instruction(r'\F32X4.\RELAXEDMADD', r'\hex{FD}~~\hex{85}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-relaxed_madd'), + Instruction(r'\F32X4.\RELAXEDNMADD', r'\hex{FD}~~\hex{86}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-relaxed_nmadd'), + Instruction(r'\F64X2.\RELAXEDMADD', r'\hex{FD}~~\hex{87}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-relaxed_madd'), + Instruction(r'\F64X2.\RELAXEDNMADD', r'\hex{FD}~~\hex{88}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-relaxed_nmadd'), + Instruction(r'\I8X16.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{89}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxedlaneselect', r'exec-relaxedlaneselect', r'op-relaxed_lane_select'), + Instruction(r'\I16X8.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8A}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxedlaneselect', r'exec-relaxedlaneselect', r'op-relaxed_lane_select'), + Instruction(r'\I32X4.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8B}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxedlaneselect', r'exec-relaxedlaneselect', r'op-relaxed_lane_select'), + Instruction(r'\I64X2.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8C}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxedlaneselect', r'exec-relaxedlaneselect', r'op-relaxed_lane_select'), + Instruction(r'\F32X4.\RELAXEDMIN', r'\hex{FD}~~\hex{8D}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-relaxed_min'), + Instruction(r'\F32X4.\RELAXEDMAX', r'\hex{FD}~~\hex{8E}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-relaxed_max'), + Instruction(r'\F64X2.\RELAXEDMIN', r'\hex{FD}~~\hex{8F}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-relaxed_min'), + Instruction(r'\F64X2.\RELAXEDMAX', r'\hex{FD}~~\hex{90}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-relaxed_max'), + Instruction(r'\I16X8.\RELAXEDQ15MULRS', r'\hex{FD}~~\hex{91}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-relaxed_q15mulr_s'), + Instruction(r'\I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_s}', r'\hex{FD}~~\hex{92}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-relaxed_dot', r'exec-relaxed_dot', r'op-relaxed_dot_mul'), + Instruction(r'\I32X4.\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s}', r'\hex{FD}~~\hex{93}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_dot', r'exec-relaxed_dot', r'op-relaxed_dot_mul'), ] diff --git a/document/core/appendix/index-instructions.rst b/document/core/appendix/index-instructions.rst index df2cecd92..934369052 100644 --- a/document/core/appendix/index-instructions.rst +++ b/document/core/appendix/index-instructions.rst @@ -6,536 +6,536 @@ Index of Instructions --------------------- -==================================================== ==================================== ============================================= ============================================= ====================================================================== -Instruction Binary Opcode Type Validation Execution -==================================================== ==================================== ============================================= ============================================= ====================================================================== -:math:`\UNREACHABLE` :math:`\hex{00}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\NOP` :math:`\hex{01}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` -:math:`\BLOCK~\X{bt}` :math:`\hex{02}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\LOOP~\X{bt}` :math:`\hex{03}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\IF~\X{bt}` :math:`\hex{04}` :math:`[t_1^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\ELSE` :math:`\hex{05}` -(reserved) :math:`\hex{06}` -(reserved) :math:`\hex{07}` -(reserved) :math:`\hex{08}` -(reserved) :math:`\hex{09}` -(reserved) :math:`\hex{0A}` -:math:`\END` :math:`\hex{0B}` -:math:`\BR~l` :math:`\hex{0C}` :math:`[t_1^\ast~t^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\BRIF~l` :math:`\hex{0D}` :math:`[t^\ast~\I32] \to [t^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\BRTABLE~l^\ast~l` :math:`\hex{0E}` :math:`[t_1^\ast~t^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\RETURN` :math:`\hex{0F}` :math:`[t_1^\ast~t^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\CALL~x` :math:`\hex{10}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -:math:`\CALLINDIRECT~x~y` :math:`\hex{11}` :math:`[t_1^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` -(reserved) :math:`\hex{12}` -(reserved) :math:`\hex{13}` -(reserved) :math:`\hex{14}` -(reserved) :math:`\hex{15}` -(reserved) :math:`\hex{16}` -(reserved) :math:`\hex{17}` -(reserved) :math:`\hex{18}` -(reserved) :math:`\hex{19}` -:math:`\DROP` :math:`\hex{1A}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` -:math:`\SELECT` :math:`\hex{1B}` :math:`[t~t~\I32] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\SELECT~t` :math:`\hex{1C}` :math:`[t~t~\I32] \to [t]` :ref:`validation ` :ref:`execution ` -(reserved) :math:`\hex{1D}` -(reserved) :math:`\hex{1E}` -(reserved) :math:`\hex{1F}` -:math:`\LOCALGET~x` :math:`\hex{20}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\LOCALSET~x` :math:`\hex{21}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` -:math:`\LOCALTEE~x` :math:`\hex{22}` :math:`[t] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\GLOBALGET~x` :math:`\hex{23}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\GLOBALSET~x` :math:`\hex{24}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` -:math:`\TABLEGET~x` :math:`\hex{25}` :math:`[\I32] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\TABLESET~x` :math:`\hex{26}` :math:`[\I32~t] \to []` :ref:`validation ` :ref:`execution ` -(reserved) :math:`\hex{27}` -:math:`\I32.\LOAD~\memarg` :math:`\hex{28}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD~\memarg` :math:`\hex{29}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\F32.\LOAD~\memarg` :math:`\hex{2A}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution ` -:math:`\F64.\LOAD~\memarg` :math:`\hex{2B}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\LOAD\K{8\_s}~\memarg` :math:`\hex{2C}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\LOAD\K{8\_u}~\memarg` :math:`\hex{2D}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\LOAD\K{16\_s}~\memarg` :math:`\hex{2E}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\LOAD\K{16\_u}~\memarg` :math:`\hex{2F}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{8\_s}~\memarg` :math:`\hex{30}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{8\_u}~\memarg` :math:`\hex{31}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{16\_s}~\memarg` :math:`\hex{32}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{16\_u}~\memarg` :math:`\hex{33}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{32\_s}~\memarg` :math:`\hex{34}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\LOAD\K{32\_u}~\memarg` :math:`\hex{35}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\STORE~\memarg` :math:`\hex{36}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I64.\STORE~\memarg` :math:`\hex{37}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\F32.\STORE~\memarg` :math:`\hex{38}` :math:`[\I32~\F32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\F64.\STORE~\memarg` :math:`\hex{39}` :math:`[\I32~\F64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I32.\STORE\K{8}~\memarg` :math:`\hex{3A}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I32.\STORE\K{16}~\memarg` :math:`\hex{3B}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I64.\STORE\K{8}~\memarg` :math:`\hex{3C}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I64.\STORE\K{16}~\memarg` :math:`\hex{3D}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\I64.\STORE\K{32}~\memarg` :math:`\hex{3E}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` -:math:`\MEMORYSIZE` :math:`\hex{3F}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\MEMORYGROW` :math:`\hex{40}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\CONST~\i32` :math:`\hex{41}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64.\CONST~\i64` :math:`\hex{42}` :math:`[] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\F32.\CONST~\f32` :math:`\hex{43}` :math:`[] \to [\F32]` :ref:`validation ` :ref:`execution ` -:math:`\F64.\CONST~\f64` :math:`\hex{44}` :math:`[] \to [\F64]` :ref:`validation ` :ref:`execution ` -:math:`\I32.\EQZ` :math:`\hex{45}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\EQ` :math:`\hex{46}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\NE` :math:`\hex{47}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\LT\K{\_s}` :math:`\hex{48}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\LT\K{\_u}` :math:`\hex{49}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\GT\K{\_s}` :math:`\hex{4A}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\GT\K{\_u}` :math:`\hex{4B}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\LE\K{\_s}` :math:`\hex{4C}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\LE\K{\_u}` :math:`\hex{4D}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\GE\K{\_s}` :math:`\hex{4E}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\GE\K{\_u}` :math:`\hex{4F}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EQZ` :math:`\hex{50}` :math:`[\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EQ` :math:`\hex{51}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\NE` :math:`\hex{52}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\LT\K{\_s}` :math:`\hex{53}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\LT\K{\_u}` :math:`\hex{54}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\GT\K{\_s}` :math:`\hex{55}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\GT\K{\_u}` :math:`\hex{56}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\LE\K{\_s}` :math:`\hex{57}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\LE\K{\_u}` :math:`\hex{58}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\GE\K{\_s}` :math:`\hex{59}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\GE\K{\_u}` :math:`\hex{5A}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\EQ` :math:`\hex{5B}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\NE` :math:`\hex{5C}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\LT` :math:`\hex{5D}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\GT` :math:`\hex{5E}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\LE` :math:`\hex{5F}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\GE` :math:`\hex{60}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\EQ` :math:`\hex{61}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\NE` :math:`\hex{62}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\LT` :math:`\hex{63}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\GT` :math:`\hex{64}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\LE` :math:`\hex{65}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\GE` :math:`\hex{66}` :math:`[\F64~\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\CLZ` :math:`\hex{67}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\CTZ` :math:`\hex{68}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\POPCNT` :math:`\hex{69}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\ADD` :math:`\hex{6A}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\SUB` :math:`\hex{6B}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\MUL` :math:`\hex{6C}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\DIV\K{\_s}` :math:`\hex{6D}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\DIV\K{\_u}` :math:`\hex{6E}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\REM\K{\_s}` :math:`\hex{6F}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\REM\K{\_u}` :math:`\hex{70}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\AND` :math:`\hex{71}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\OR` :math:`\hex{72}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\XOR` :math:`\hex{73}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\SHL` :math:`\hex{74}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\SHR\K{\_s}` :math:`\hex{75}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\SHR\K{\_u}` :math:`\hex{76}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\ROTL` :math:`\hex{77}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\ROTR` :math:`\hex{78}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\CLZ` :math:`\hex{79}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\CTZ` :math:`\hex{7A}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\POPCNT` :math:`\hex{7B}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\ADD` :math:`\hex{7C}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\SUB` :math:`\hex{7D}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\MUL` :math:`\hex{7E}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\DIV\K{\_s}` :math:`\hex{7F}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\DIV\K{\_u}` :math:`\hex{80}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\REM\K{\_s}` :math:`\hex{81}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\REM\K{\_u}` :math:`\hex{82}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\AND` :math:`\hex{83}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\OR` :math:`\hex{84}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\XOR` :math:`\hex{85}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\SHL` :math:`\hex{86}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\SHR\K{\_s}` :math:`\hex{87}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\SHR\K{\_u}` :math:`\hex{88}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\ROTL` :math:`\hex{89}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\ROTR` :math:`\hex{8A}` :math:`[\I64~\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\ABS` :math:`\hex{8B}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\NEG` :math:`\hex{8C}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CEIL` :math:`\hex{8D}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\FLOOR` :math:`\hex{8E}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\TRUNC` :math:`\hex{8F}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\NEAREST` :math:`\hex{90}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\SQRT` :math:`\hex{91}` :math:`[\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\ADD` :math:`\hex{92}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\SUB` :math:`\hex{93}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\MUL` :math:`\hex{94}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\DIV` :math:`\hex{95}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\FMIN` :math:`\hex{96}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\FMAX` :math:`\hex{97}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\COPYSIGN` :math:`\hex{98}` :math:`[\F32~\F32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\ABS` :math:`\hex{99}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\NEG` :math:`\hex{9A}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CEIL` :math:`\hex{9B}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\FLOOR` :math:`\hex{9C}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\TRUNC` :math:`\hex{9D}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\NEAREST` :math:`\hex{9E}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\SQRT` :math:`\hex{9F}` :math:`[\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\ADD` :math:`\hex{A0}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\SUB` :math:`\hex{A1}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\MUL` :math:`\hex{A2}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\DIV` :math:`\hex{A3}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\FMIN` :math:`\hex{A4}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\FMAX` :math:`\hex{A5}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\COPYSIGN` :math:`\hex{A6}` :math:`[\F64~\F64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\WRAP\K{\_}\I64` :math:`\hex{A7}` :math:`[\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_}\F32\K{\_s}` :math:`\hex{A8}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_}\F32\K{\_u}` :math:`\hex{A9}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_}\F64\K{\_s}` :math:`\hex{AA}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_}\F64\K{\_u}` :math:`\hex{AB}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{\_}\I32\K{\_s}` :math:`\hex{AC}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{\_}\I32\K{\_u}` :math:`\hex{AD}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_}\F32\K{\_s}` :math:`\hex{AE}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_}\F32\K{\_u}` :math:`\hex{AF}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_}\F64\K{\_s}` :math:`\hex{B0}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_}\F64\K{\_u}` :math:`\hex{B1}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CONVERT\K{\_}\I32\K{\_s}` :math:`\hex{B2}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CONVERT\K{\_}\I32\K{\_u}` :math:`\hex{B3}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CONVERT\K{\_}\I64\K{\_s}` :math:`\hex{B4}` :math:`[\I64] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\CONVERT\K{\_}\I64\K{\_u}` :math:`\hex{B5}` :math:`[\I64] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\DEMOTE\K{\_}\F64` :math:`\hex{B6}` :math:`[\F64] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CONVERT\K{\_}\I32\K{\_s}` :math:`\hex{B7}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CONVERT\K{\_}\I32\K{\_u}` :math:`\hex{B8}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CONVERT\K{\_}\I64\K{\_s}` :math:`\hex{B9}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\CONVERT\K{\_}\I64\K{\_u}` :math:`\hex{BA}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\PROMOTE\K{\_}\F32` :math:`\hex{BB}` :math:`[\F32] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\REINTERPRET\K{\_}\F32` :math:`\hex{BC}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\REINTERPRET\K{\_}\F64` :math:`\hex{BD}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32.\REINTERPRET\K{\_}\I32` :math:`\hex{BE}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64.\REINTERPRET\K{\_}\I64` :math:`\hex{BF}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\EXTEND\K{8\_s}` :math:`\hex{C0}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\EXTEND\K{16\_s}` :math:`\hex{C1}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{8\_s}` :math:`\hex{C2}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{16\_s}` :math:`\hex{C3}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\EXTEND\K{32\_s}` :math:`\hex{C4}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -(reserved) :math:`\hex{C5}` -(reserved) :math:`\hex{C6}` -(reserved) :math:`\hex{C7}` -(reserved) :math:`\hex{C8}` -(reserved) :math:`\hex{C9}` -(reserved) :math:`\hex{CA}` -(reserved) :math:`\hex{CB}` -(reserved) :math:`\hex{CC}` -(reserved) :math:`\hex{CD}` -(reserved) :math:`\hex{CE}` -(reserved) :math:`\hex{CF}` -:math:`\REFNULL~t` :math:`\hex{D0}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` -:math:`\REFISNULL` :math:`\hex{D1}` :math:`[t] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\REFFUNC~x` :math:`\hex{D2}` :math:`[] \to [\FUNCREF]` :ref:`validation ` :ref:`execution ` -(reserved) :math:`\hex{D3}` -(reserved) :math:`\hex{D4}` -(reserved) :math:`\hex{D5}` -(reserved) :math:`\hex{D6}` -(reserved) :math:`\hex{D7}` -(reserved) :math:`\hex{D8}` -(reserved) :math:`\hex{D9}` -(reserved) :math:`\hex{DA}` -(reserved) :math:`\hex{DB}` -(reserved) :math:`\hex{DC}` -(reserved) :math:`\hex{DD}` -(reserved) :math:`\hex{DE}` -(reserved) :math:`\hex{DF}` -(reserved) :math:`\hex{E0}` -(reserved) :math:`\hex{E1}` -(reserved) :math:`\hex{E2}` -(reserved) :math:`\hex{E3}` -(reserved) :math:`\hex{E4}` -(reserved) :math:`\hex{E5}` -(reserved) :math:`\hex{E6}` -(reserved) :math:`\hex{E7}` -(reserved) :math:`\hex{E8}` -(reserved) :math:`\hex{E9}` -(reserved) :math:`\hex{EA}` -(reserved) :math:`\hex{EB}` -(reserved) :math:`\hex{EC}` -(reserved) :math:`\hex{ED}` -(reserved) :math:`\hex{EE}` -(reserved) :math:`\hex{EF}` -(reserved) :math:`\hex{F0}` -(reserved) :math:`\hex{F1}` -(reserved) :math:`\hex{F2}` -(reserved) :math:`\hex{F3}` -(reserved) :math:`\hex{F4}` -(reserved) :math:`\hex{F5}` -(reserved) :math:`\hex{F6}` -(reserved) :math:`\hex{F7}` -(reserved) :math:`\hex{F8}` -(reserved) :math:`\hex{F9}` -(reserved) :math:`\hex{FA}` -(reserved) :math:`\hex{FB}` -:math:`\I32.\TRUNC\K{\_sat\_}\F32\K{\_s}` :math:`\hex{FC}~\hex{00}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_sat\_}\F32\K{\_u}` :math:`\hex{FC}~\hex{01}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_sat\_}\F64\K{\_s}` :math:`\hex{FC}~\hex{02}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32.\TRUNC\K{\_sat\_}\F64\K{\_u}` :math:`\hex{FC}~\hex{03}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_sat\_}\F32\K{\_s}` :math:`\hex{FC}~\hex{04}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_sat\_}\F32\K{\_u}` :math:`\hex{FC}~\hex{05}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_sat\_}\F64\K{\_s}` :math:`\hex{FC}~\hex{06}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64.\TRUNC\K{\_sat\_}\F64\K{\_u}` :math:`\hex{FC}~\hex{07}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\MEMORYINIT~x` :math:`\hex{FC}~\hex{08}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\DATADROP~x` :math:`\hex{FC}~\hex{09}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` -:math:`\MEMORYCOPY` :math:`\hex{FC}~\hex{0A}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\MEMORYFILL` :math:`\hex{FC}~\hex{0B}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\TABLEINIT~x~y` :math:`\hex{FC}~\hex{0C}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\ELEMDROP~x` :math:`\hex{FC}~\hex{0D}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` -:math:`\TABLECOPY~x~y` :math:`\hex{FC}~\hex{0E}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\TABLEGROW~x` :math:`\hex{FC}~\hex{0F}` :math:`[t~\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\TABLESIZE~x` :math:`\hex{FC}~\hex{10}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\TABLEFILL~x` :math:`\hex{FC}~\hex{11}` :math:`[\I32~t~\I32] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD~\memarg` :math:`\hex{FD}~~\hex{00}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{8x8\_s}~\memarg` :math:`\hex{FD}~~\hex{01}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{8x8\_u}~\memarg` :math:`\hex{FD}~~\hex{02}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{16x4\_s}~\memarg` :math:`\hex{FD}~~\hex{03}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{16x4\_u}~\memarg` :math:`\hex{FD}~~\hex{04}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32x2\_s}~\memarg` :math:`\hex{FD}~~\hex{05}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32x2\_u}~\memarg` :math:`\hex{FD}~~\hex{06}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{8\_splat}~\memarg` :math:`\hex{FD}~~\hex{07}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{16\_splat}~\memarg` :math:`\hex{FD}~~\hex{08}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32\_splat}~\memarg` :math:`\hex{FD}~~\hex{09}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{64\_splat}~\memarg` :math:`\hex{FD}~~\hex{0A}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE~\memarg` :math:`\hex{FD}~~\hex{0B}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\VCONST~\i128` :math:`\hex{FD}~~\hex{0C}` :math:`[] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\SHUFFLE~\laneidx^{16}` :math:`\hex{FD}~~\hex{0D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\SWIZZLE` :math:`\hex{FD}~~\hex{0E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\SPLAT` :math:`\hex{FD}~~\hex{0F}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\SPLAT` :math:`\hex{FD}~~\hex{10}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\SPLAT` :math:`\hex{FD}~~\hex{11}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\SPLAT` :math:`\hex{FD}~~\hex{12}` :math:`[\I64] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\SPLAT` :math:`\hex{FD}~~\hex{13}` :math:`[\F32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F64X2.\SPLAT` :math:`\hex{FD}~~\hex{14}` :math:`[\F64] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\EXTRACTLANE\K{\_s}~\laneidx` :math:`\hex{FD}~~\hex{15}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\EXTRACTLANE\K{\_u}~\laneidx` :math:`\hex{FD}~~\hex{16}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{17}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTRACTLANE\K{\_s}~\laneidx` :math:`\hex{FD}~~\hex{18}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTRACTLANE\K{\_u}~\laneidx` :math:`\hex{FD}~~\hex{19}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1A}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1B}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1C}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1D}` :math:`[\V128] \to [\I64]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1E}` :math:`[\V128~\I64] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1F}` :math:`[\V128] \to [\F32]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{20}` :math:`[\V128~\F32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F64X2.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{21}` :math:`[\V128] \to [\F64]` :ref:`validation ` :ref:`execution ` -:math:`\F64X2.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{22}` :math:`[\V128~\F64] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\VEQ` :math:`\hex{FD}~~\hex{23}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VNE` :math:`\hex{FD}~~\hex{24}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{25}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{26}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{27}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{28}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{29}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{2A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{2B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{2C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VEQ` :math:`\hex{FD}~~\hex{2D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VNE` :math:`\hex{FD}~~\hex{2E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{2F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{30}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{31}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{32}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{33}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{34}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{35}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{36}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VEQ` :math:`\hex{FD}~~\hex{37}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VNE` :math:`\hex{FD}~~\hex{38}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{39}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{3A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{3B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{3C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{3D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{3E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{3F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{40}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VEQ` :math:`\hex{FD}~~\hex{41}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VNE` :math:`\hex{FD}~~\hex{42}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VLT` :math:`\hex{FD}~~\hex{43}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VGT` :math:`\hex{FD}~~\hex{44}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VLE` :math:`\hex{FD}~~\hex{45}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VGE` :math:`\hex{FD}~~\hex{46}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VEQ` :math:`\hex{FD}~~\hex{47}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VNE` :math:`\hex{FD}~~\hex{48}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VLT` :math:`\hex{FD}~~\hex{49}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VGT` :math:`\hex{FD}~~\hex{4A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VLE` :math:`\hex{FD}~~\hex{4B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VGE` :math:`\hex{FD}~~\hex{4C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VNOT` :math:`\hex{FD}~~\hex{4D}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VAND` :math:`\hex{FD}~~\hex{4E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VANDNOT` :math:`\hex{FD}~~\hex{4F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VOR` :math:`\hex{FD}~~\hex{50}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\VXOR` :math:`\hex{FD}~~\hex{51}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\BITSELECT` :math:`\hex{FD}~~\hex{52}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\V128.\ANYTRUE` :math:`\hex{FD}~~\hex{53}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{54}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{55}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{56}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{57}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{58}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{59}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5A}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\STORE\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5B}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{32\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5C}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\V128.\LOAD\K{64\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5D}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\VDEMOTE\K{\_f64x2\_zero}` :math:`\hex{FD}~~\hex{5E}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VPROMOTE\K{\_low\_f32x4}` :math:`\hex{FD}~~\hex{5F}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VABS` :math:`\hex{FD}~~\hex{60}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VNEG` :math:`\hex{FD}~~\hex{61}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VPOPCNT` :math:`\hex{FD}~~\hex{62}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\ALLTRUE` :math:`\hex{FD}~~\hex{63}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\BITMASK` :math:`\hex{FD}~~\hex{64}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\NARROW\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{65}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I8X16.\NARROW\K{\_i16x8\_u}` :math:`\hex{FD}~~\hex{66}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\VCEIL` :math:`\hex{FD}~~\hex{67}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VFLOOR` :math:`\hex{FD}~~\hex{68}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VTRUNC` :math:`\hex{FD}~~\hex{69}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VNEAREST` :math:`\hex{FD}~~\hex{6A}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSHL` :math:`\hex{FD}~~\hex{6B}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{6C}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{6D}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VADD` :math:`\hex{FD}~~\hex{6E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VADD\K{\_sat\_s}` :math:`\hex{FD}~~\hex{6F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VADD\K{\_sat\_u}` :math:`\hex{FD}~~\hex{70}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSUB` :math:`\hex{FD}~~\hex{71}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~\hex{72}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~\hex{73}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VCEIL` :math:`\hex{FD}~~\hex{74}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VFLOOR` :math:`\hex{FD}~~\hex{75}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{76}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{77}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{78}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{79}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VTRUNC` :math:`\hex{FD}~~\hex{7A}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\AVGR\K{\_u}` :math:`\hex{FD}~~\hex{7B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}` :math:`\hex{FD}~~\hex{7C}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}` :math:`\hex{FD}~~\hex{7D}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{7E}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}` :math:`\hex{FD}~~\hex{7F}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VABS` :math:`\hex{FD}~~\hex{80}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VNEG` :math:`\hex{FD}~~\hex{81}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\Q15MULRSAT\K{\_s}` :math:`\hex{FD}~~\hex{82}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\ALLTRUE` :math:`\hex{FD}~~\hex{83}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\BITMASK` :math:`\hex{FD}~~\hex{84}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\NARROW\K{\_i32x4\_s}` :math:`\hex{FD}~~\hex{85}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\NARROW\K{\_i32x4\_u}` :math:`\hex{FD}~~\hex{86}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~\hex{87}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~\hex{88}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~\hex{89}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~\hex{8A}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\VSHL` :math:`\hex{FD}~~\hex{8B}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{8C}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{8D}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VADD` :math:`\hex{FD}~~\hex{8E}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VADD\K{\_sat\_s}` :math:`\hex{FD}~~\hex{8F}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VADD\K{\_sat\_u}` :math:`\hex{FD}~~\hex{90}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSUB` :math:`\hex{FD}~~\hex{91}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~\hex{92}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~\hex{93}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VNEAREST` :math:`\hex{FD}~~\hex{94}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMUL` :math:`\hex{FD}~~\hex{95}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{96}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{97}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{98}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{99}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\AVGR\K{\_u}` :math:`\hex{FD}~~\hex{9B}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~\hex{9C}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~\hex{9D}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~\hex{9E}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~\hex{9F}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VABS` :math:`\hex{FD}~~\hex{A0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VNEG` :math:`\hex{FD}~~\hex{A1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\ALLTRUE` :math:`\hex{FD}~~\hex{A3}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\BITMASK` :math:`\hex{FD}~~\hex{A4}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~\hex{A7}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~\hex{A8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~\hex{A9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~\hex{AA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\VSHL` :math:`\hex{FD}~~\hex{AB}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{AC}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{AD}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VADD` :math:`\hex{FD}~~\hex{AE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VSUB` :math:`\hex{FD}~~\hex{B1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMUL` :math:`\hex{FD}~~\hex{B5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{B6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{B7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{B8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{B9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\DOT\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{BA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~\hex{BC}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~\hex{BD}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~\hex{BE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~\hex{BF}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VABS` :math:`\hex{FD}~~\hex{C0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VNEG` :math:`\hex{FD}~~\hex{C1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\ALLTRUE` :math:`\hex{FD}~~\hex{C3}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\BITMASK` :math:`\hex{FD}~~\hex{C4}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{C7}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~\hex{C8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{C9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~\hex{CA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\VSHL` :math:`\hex{FD}~~\hex{CB}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{CC}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{CD}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VADD` :math:`\hex{FD}~~\hex{CE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VSUB` :math:`\hex{FD}~~\hex{D1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VMUL` :math:`\hex{FD}~~\hex{D5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VEQ` :math:`\hex{FD}~~\hex{D6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VNE` :math:`\hex{FD}~~\hex{D7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{D8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{D9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{DA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{DB}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{DC}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~\hex{DD}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{DE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~\hex{DF}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` -:math:`\F32X4.\VABS` :math:`\hex{FD}~~\hex{E0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VNEG` :math:`\hex{FD}~~\hex{E1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VSQRT` :math:`\hex{FD}~~\hex{E3}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VADD` :math:`\hex{FD}~~\hex{E4}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VSUB` :math:`\hex{FD}~~\hex{E5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VMUL` :math:`\hex{FD}~~\hex{E6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VDIV` :math:`\hex{FD}~~\hex{E7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VMIN` :math:`\hex{FD}~~\hex{E8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VMAX` :math:`\hex{FD}~~\hex{E9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VPMIN` :math:`\hex{FD}~~\hex{EA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VPMAX` :math:`\hex{FD}~~\hex{EB}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VABS` :math:`\hex{FD}~~\hex{EC}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VNEG` :math:`\hex{FD}~~\hex{ED}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VSQRT` :math:`\hex{FD}~~\hex{EF}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VADD` :math:`\hex{FD}~~\hex{F0}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VSUB` :math:`\hex{FD}~~\hex{F1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VMUL` :math:`\hex{FD}~~\hex{F2}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VDIV` :math:`\hex{FD}~~\hex{F3}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VMIN` :math:`\hex{FD}~~\hex{F4}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VMAX` :math:`\hex{FD}~~\hex{F5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VPMIN` :math:`\hex{FD}~~\hex{F6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VPMAX` :math:`\hex{FD}~~\hex{F7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_s}` :math:`\hex{FD}~~\hex{F8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_u}` :math:`\hex{FD}~~\hex{F9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VCONVERT\K{\_i32x4\_s}` :math:`\hex{FD}~~\hex{FA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\VCONVERT\K{\_i32x4\_u}` :math:`\hex{FD}~~\hex{FB}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_s\_zero}` :math:`\hex{FD}~~\hex{FC}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}` :math:`\hex{FD}~~\hex{FD}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{FE}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{FF}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\RELAXEDSWIZZLE` :math:`\hex{FD}~~\hex{80}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\RELAXEDTRUNC\K{\_f32x4\_s}` :math:`\hex{FD}~~\hex{81}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\RELAXEDTRUNC\K{\_f32x4\_u}` :math:`\hex{FD}~~\hex{82}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\RELAXEDTRUNC\K{\_f64x2\_s}` :math:`\hex{FD}~~\hex{83}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\RELAXEDTRUNC\K{\_f64x2\_u}` :math:`\hex{FD}~~\hex{84}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\RELAXEDMADD` :math:`\hex{FD}~~\hex{85}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\RELAXEDNMADD` :math:`\hex{FD}~~\hex{86}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\RELAXEDMADD` :math:`\hex{FD}~~\hex{87}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\RELAXEDNMADD` :math:`\hex{FD}~~\hex{88}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I8X16.\RELAXEDLANESELECT` :math:`\hex{FD}~~\hex{89}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\RELAXEDLANESELECT` :math:`\hex{FD}~~\hex{8A}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\RELAXEDLANESELECT` :math:`\hex{FD}~~\hex{8B}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I64X2.\RELAXEDLANESELECT` :math:`\hex{FD}~~\hex{8C}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\RELAXEDMIN` :math:`\hex{FD}~~\hex{8D}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F32X4.\RELAXEDMAX` :math:`\hex{FD}~~\hex{8E}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\RELAXEDMIN` :math:`\hex{FD}~~\hex{8F}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\F64X2.\RELAXEDMAX` :math:`\hex{FD}~~\hex{90}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\RELAXEDQ15MULRS` :math:`\hex{FD}~~\hex{91}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_s}` :math:`\hex{FD}~~\hex{92}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -:math:`\I32X4.\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s}` :math:`\hex{FD}~~\hex{93}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` -==================================================== ==================================== ============================================= ============================================= ====================================================================== +==================================================== ==================================== ============================================= ============================================= =================================================================================== +Instruction Binary Opcode Type Validation Execution +==================================================== ==================================== ============================================= ============================================= =================================================================================== +:math:`\UNREACHABLE` :math:`\hex{00}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\NOP` :math:`\hex{01}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` +:math:`\BLOCK~\X{bt}` :math:`\hex{02}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\LOOP~\X{bt}` :math:`\hex{03}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\IF~\X{bt}` :math:`\hex{04}` :math:`[t_1^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\ELSE` :math:`\hex{05}` +(reserved) :math:`\hex{06}` +(reserved) :math:`\hex{07}` +(reserved) :math:`\hex{08}` +(reserved) :math:`\hex{09}` +(reserved) :math:`\hex{0A}` +:math:`\END` :math:`\hex{0B}` +:math:`\BR~l` :math:`\hex{0C}` :math:`[t_1^\ast~t^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\BRIF~l` :math:`\hex{0D}` :math:`[t^\ast~\I32] \to [t^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\BRTABLE~l^\ast~l` :math:`\hex{0E}` :math:`[t_1^\ast~t^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\RETURN` :math:`\hex{0F}` :math:`[t_1^\ast~t^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\CALL~x` :math:`\hex{10}` :math:`[t_1^\ast] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +:math:`\CALLINDIRECT~x~y` :math:`\hex{11}` :math:`[t_1^\ast~\I32] \to [t_2^\ast]` :ref:`validation ` :ref:`execution ` +(reserved) :math:`\hex{12}` +(reserved) :math:`\hex{13}` +(reserved) :math:`\hex{14}` +(reserved) :math:`\hex{15}` +(reserved) :math:`\hex{16}` +(reserved) :math:`\hex{17}` +(reserved) :math:`\hex{18}` +(reserved) :math:`\hex{19}` +:math:`\DROP` :math:`\hex{1A}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` +:math:`\SELECT` :math:`\hex{1B}` :math:`[t~t~\I32] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\SELECT~t` :math:`\hex{1C}` :math:`[t~t~\I32] \to [t]` :ref:`validation ` :ref:`execution ` +(reserved) :math:`\hex{1D}` +(reserved) :math:`\hex{1E}` +(reserved) :math:`\hex{1F}` +:math:`\LOCALGET~x` :math:`\hex{20}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\LOCALSET~x` :math:`\hex{21}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` +:math:`\LOCALTEE~x` :math:`\hex{22}` :math:`[t] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\GLOBALGET~x` :math:`\hex{23}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\GLOBALSET~x` :math:`\hex{24}` :math:`[t] \to []` :ref:`validation ` :ref:`execution ` +:math:`\TABLEGET~x` :math:`\hex{25}` :math:`[\I32] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\TABLESET~x` :math:`\hex{26}` :math:`[\I32~t] \to []` :ref:`validation ` :ref:`execution ` +(reserved) :math:`\hex{27}` +:math:`\I32.\LOAD~\memarg` :math:`\hex{28}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\LOAD~\memarg` :math:`\hex{29}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\F32.\LOAD~\memarg` :math:`\hex{2A}` :math:`[\I32] \to [\F32]` :ref:`validation ` :ref:`execution ` +:math:`\F64.\LOAD~\memarg` :math:`\hex{2B}` :math:`[\I32] \to [\F64]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\LOAD\K{8\_s}~\memarg` :math:`\hex{2C}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\LOAD\K{8\_u}~\memarg` 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:ref:`execution ` +:math:`\I32.\STORE~\memarg` :math:`\hex{36}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I64.\STORE~\memarg` :math:`\hex{37}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\F32.\STORE~\memarg` :math:`\hex{38}` :math:`[\I32~\F32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\F64.\STORE~\memarg` :math:`\hex{39}` :math:`[\I32~\F64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I32.\STORE\K{8}~\memarg` :math:`\hex{3A}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I32.\STORE\K{16}~\memarg` :math:`\hex{3B}` :math:`[\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I64.\STORE\K{8}~\memarg` :math:`\hex{3C}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I64.\STORE\K{16}~\memarg` :math:`\hex{3D}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\I64.\STORE\K{32}~\memarg` :math:`\hex{3E}` :math:`[\I32~\I64] \to []` :ref:`validation ` :ref:`execution ` +:math:`\MEMORYSIZE` :math:`\hex{3F}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\MEMORYGROW` :math:`\hex{40}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\CONST~\i32` :math:`\hex{41}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64.\CONST~\i64` :math:`\hex{42}` :math:`[] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\F32.\CONST~\f32` :math:`\hex{43}` :math:`[] \to [\F32]` :ref:`validation ` :ref:`execution ` +:math:`\F64.\CONST~\f64` :math:`\hex{44}` :math:`[] \to [\F64]` :ref:`validation ` :ref:`execution ` +:math:`\I32.\EQZ` :math:`\hex{45}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\EQ` :math:`\hex{46}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\NE` :math:`\hex{47}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\LT\K{\_s}` :math:`\hex{48}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\LT\K{\_u}` :math:`\hex{49}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\GT\K{\_s}` :math:`\hex{4A}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\GT\K{\_u}` :math:`\hex{4B}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\LE\K{\_s}` :math:`\hex{4C}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\LE\K{\_u}` :math:`\hex{4D}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\GE\K{\_s}` :math:`\hex{4E}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\GE\K{\_u}` :math:`\hex{4F}` :math:`[\I32~\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EQZ` :math:`\hex{50}` :math:`[\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EQ` :math:`\hex{51}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\NE` :math:`\hex{52}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\LT\K{\_s}` :math:`\hex{53}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\LT\K{\_u}` :math:`\hex{54}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\GT\K{\_s}` :math:`\hex{55}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\GT\K{\_u}` :math:`\hex{56}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\LE\K{\_s}` :math:`\hex{57}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\LE\K{\_u}` :math:`\hex{58}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\GE\K{\_s}` :math:`\hex{59}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\GE\K{\_u}` :math:`\hex{5A}` :math:`[\I64~\I64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\EQ` :math:`\hex{5B}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\NE` :math:`\hex{5C}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\LT` :math:`\hex{5D}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\GT` :math:`\hex{5E}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32.\LE` :math:`\hex{5F}` :math:`[\F32~\F32] \to [\I32]` :ref:`validation ` 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` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_}\F32\K{\_u}` :math:`\hex{A9}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_}\F64\K{\_s}` :math:`\hex{AA}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_}\F64\K{\_u}` :math:`\hex{AB}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{\_}\I32\K{\_s}` :math:`\hex{AC}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{\_}\I32\K{\_u}` :math:`\hex{AD}` :math:`[\I32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_}\F32\K{\_s}` :math:`\hex{AE}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_}\F32\K{\_u}` :math:`\hex{AF}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` 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:ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64.\REINTERPRET\K{\_}\I64` :math:`\hex{BF}` :math:`[\I64] \to [\F64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\EXTEND\K{8\_s}` :math:`\hex{C0}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\EXTEND\K{16\_s}` :math:`\hex{C1}` :math:`[\I32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{8\_s}` :math:`\hex{C2}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{16\_s}` :math:`\hex{C3}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\EXTEND\K{32\_s}` :math:`\hex{C4}` :math:`[\I64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +(reserved) :math:`\hex{C5}` +(reserved) :math:`\hex{C6}` +(reserved) :math:`\hex{C7}` +(reserved) :math:`\hex{C8}` +(reserved) :math:`\hex{C9}` +(reserved) :math:`\hex{CA}` +(reserved) :math:`\hex{CB}` +(reserved) :math:`\hex{CC}` +(reserved) :math:`\hex{CD}` +(reserved) :math:`\hex{CE}` +(reserved) :math:`\hex{CF}` +:math:`\REFNULL~t` :math:`\hex{D0}` :math:`[] \to [t]` :ref:`validation ` :ref:`execution ` +:math:`\REFISNULL` :math:`\hex{D1}` :math:`[t] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\REFFUNC~x` :math:`\hex{D2}` :math:`[] \to [\FUNCREF]` :ref:`validation ` :ref:`execution ` +(reserved) :math:`\hex{D3}` +(reserved) :math:`\hex{D4}` +(reserved) :math:`\hex{D5}` +(reserved) :math:`\hex{D6}` +(reserved) :math:`\hex{D7}` +(reserved) :math:`\hex{D8}` +(reserved) :math:`\hex{D9}` +(reserved) :math:`\hex{DA}` +(reserved) :math:`\hex{DB}` +(reserved) :math:`\hex{DC}` +(reserved) :math:`\hex{DD}` +(reserved) :math:`\hex{DE}` +(reserved) :math:`\hex{DF}` +(reserved) :math:`\hex{E0}` +(reserved) :math:`\hex{E1}` +(reserved) :math:`\hex{E2}` +(reserved) :math:`\hex{E3}` +(reserved) :math:`\hex{E4}` +(reserved) :math:`\hex{E5}` +(reserved) :math:`\hex{E6}` +(reserved) :math:`\hex{E7}` +(reserved) :math:`\hex{E8}` +(reserved) :math:`\hex{E9}` +(reserved) :math:`\hex{EA}` +(reserved) :math:`\hex{EB}` +(reserved) :math:`\hex{EC}` +(reserved) :math:`\hex{ED}` +(reserved) :math:`\hex{EE}` +(reserved) :math:`\hex{EF}` +(reserved) :math:`\hex{F0}` +(reserved) :math:`\hex{F1}` +(reserved) :math:`\hex{F2}` +(reserved) :math:`\hex{F3}` +(reserved) :math:`\hex{F4}` +(reserved) :math:`\hex{F5}` +(reserved) :math:`\hex{F6}` +(reserved) :math:`\hex{F7}` +(reserved) :math:`\hex{F8}` +(reserved) :math:`\hex{F9}` +(reserved) :math:`\hex{FA}` +(reserved) :math:`\hex{FB}` +:math:`\I32.\TRUNC\K{\_sat\_}\F32\K{\_s}` :math:`\hex{FC}~\hex{00}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_sat\_}\F32\K{\_u}` :math:`\hex{FC}~\hex{01}` :math:`[\F32] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_sat\_}\F64\K{\_s}` :math:`\hex{FC}~\hex{02}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32.\TRUNC\K{\_sat\_}\F64\K{\_u}` :math:`\hex{FC}~\hex{03}` :math:`[\F64] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_sat\_}\F32\K{\_s}` :math:`\hex{FC}~\hex{04}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_sat\_}\F32\K{\_u}` :math:`\hex{FC}~\hex{05}` :math:`[\F32] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_sat\_}\F64\K{\_s}` :math:`\hex{FC}~\hex{06}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64.\TRUNC\K{\_sat\_}\F64\K{\_u}` :math:`\hex{FC}~\hex{07}` :math:`[\F64] \to [\I64]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\MEMORYINIT~x` :math:`\hex{FC}~\hex{08}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\DATADROP~x` :math:`\hex{FC}~\hex{09}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` +:math:`\MEMORYCOPY` :math:`\hex{FC}~\hex{0A}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\MEMORYFILL` :math:`\hex{FC}~\hex{0B}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\TABLEINIT~x~y` :math:`\hex{FC}~\hex{0C}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\ELEMDROP~x` :math:`\hex{FC}~\hex{0D}` :math:`[] \to []` :ref:`validation ` :ref:`execution ` +:math:`\TABLECOPY~x~y` :math:`\hex{FC}~\hex{0E}` :math:`[\I32~\I32~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\TABLEGROW~x` :math:`\hex{FC}~\hex{0F}` :math:`[t~\I32] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\TABLESIZE~x` :math:`\hex{FC}~\hex{10}` :math:`[] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\TABLEFILL~x` :math:`\hex{FC}~\hex{11}` :math:`[\I32~t~\I32] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD~\memarg` :math:`\hex{FD}~~\hex{00}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{8x8\_s}~\memarg` :math:`\hex{FD}~~\hex{01}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{8x8\_u}~\memarg` :math:`\hex{FD}~~\hex{02}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{16x4\_s}~\memarg` :math:`\hex{FD}~~\hex{03}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{16x4\_u}~\memarg` :math:`\hex{FD}~~\hex{04}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32x2\_s}~\memarg` :math:`\hex{FD}~~\hex{05}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32x2\_u}~\memarg` :math:`\hex{FD}~~\hex{06}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{8\_splat}~\memarg` :math:`\hex{FD}~~\hex{07}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{16\_splat}~\memarg` :math:`\hex{FD}~~\hex{08}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32\_splat}~\memarg` :math:`\hex{FD}~~\hex{09}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{64\_splat}~\memarg` :math:`\hex{FD}~~\hex{0A}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE~\memarg` :math:`\hex{FD}~~\hex{0B}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\VCONST~\i128` :math:`\hex{FD}~~\hex{0C}` :math:`[] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\SHUFFLE~\laneidx^{16}` :math:`\hex{FD}~~\hex{0D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\SWIZZLE` :math:`\hex{FD}~~\hex{0E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\SPLAT` :math:`\hex{FD}~~\hex{0F}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\SPLAT` :math:`\hex{FD}~~\hex{10}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\SPLAT` :math:`\hex{FD}~~\hex{11}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\SPLAT` :math:`\hex{FD}~~\hex{12}` :math:`[\I64] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\SPLAT` :math:`\hex{FD}~~\hex{13}` :math:`[\F32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F64X2.\SPLAT` :math:`\hex{FD}~~\hex{14}` :math:`[\F64] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\EXTRACTLANE\K{\_s}~\laneidx` :math:`\hex{FD}~~\hex{15}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\EXTRACTLANE\K{\_u}~\laneidx` :math:`\hex{FD}~~\hex{16}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{17}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTRACTLANE\K{\_s}~\laneidx` :math:`\hex{FD}~~\hex{18}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTRACTLANE\K{\_u}~\laneidx` :math:`\hex{FD}~~\hex{19}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1A}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1B}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1C}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1D}` :math:`[\V128] \to [\I64]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{1E}` :math:`[\V128~\I64] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{1F}` :math:`[\V128] \to [\F32]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{20}` :math:`[\V128~\F32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F64X2.\EXTRACTLANE~\laneidx` :math:`\hex{FD}~~\hex{21}` :math:`[\V128] \to [\F64]` :ref:`validation ` :ref:`execution ` +:math:`\F64X2.\REPLACELANE~\laneidx` :math:`\hex{FD}~~\hex{22}` :math:`[\V128~\F64] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\VEQ` :math:`\hex{FD}~~\hex{23}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VNE` :math:`\hex{FD}~~\hex{24}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{25}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{26}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{27}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{28}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{29}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{2A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{2B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{2C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VEQ` :math:`\hex{FD}~~\hex{2D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VNE` :math:`\hex{FD}~~\hex{2E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{2F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{30}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{31}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{32}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{33}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{34}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{35}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{36}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VEQ` :math:`\hex{FD}~~\hex{37}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VNE` :math:`\hex{FD}~~\hex{38}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{39}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VLT\K{\_u}` :math:`\hex{FD}~~\hex{3A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{3B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VGT\K{\_u}` :math:`\hex{FD}~~\hex{3C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{3D}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VLE\K{\_u}` :math:`\hex{FD}~~\hex{3E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{3F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VGE\K{\_u}` :math:`\hex{FD}~~\hex{40}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VEQ` :math:`\hex{FD}~~\hex{41}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VNE` :math:`\hex{FD}~~\hex{42}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VLT` :math:`\hex{FD}~~\hex{43}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VGT` :math:`\hex{FD}~~\hex{44}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VLE` :math:`\hex{FD}~~\hex{45}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VGE` :math:`\hex{FD}~~\hex{46}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VEQ` :math:`\hex{FD}~~\hex{47}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VNE` :math:`\hex{FD}~~\hex{48}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VLT` :math:`\hex{FD}~~\hex{49}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VGT` :math:`\hex{FD}~~\hex{4A}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VLE` :math:`\hex{FD}~~\hex{4B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VGE` :math:`\hex{FD}~~\hex{4C}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VNOT` :math:`\hex{FD}~~\hex{4D}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VAND` :math:`\hex{FD}~~\hex{4E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VANDNOT` :math:`\hex{FD}~~\hex{4F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VOR` :math:`\hex{FD}~~\hex{50}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\VXOR` :math:`\hex{FD}~~\hex{51}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\BITSELECT` :math:`\hex{FD}~~\hex{52}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\V128.\ANYTRUE` :math:`\hex{FD}~~\hex{53}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{54}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{55}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{56}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{57}` :math:`[\I32~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{8\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{58}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{16\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{59}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{32\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5A}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\STORE\K{64\_lane}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5B}` :math:`[\I32~\V128] \to []` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{32\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5C}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\V128.\LOAD\K{64\_zero}~\memarg~\laneidx` :math:`\hex{FD}~~\hex{5D}` :math:`[\I32] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\VDEMOTE\K{\_f64x2\_zero}` :math:`\hex{FD}~~\hex{5E}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPROMOTE\K{\_low\_f32x4}` :math:`\hex{FD}~~\hex{5F}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VABS` :math:`\hex{FD}~~\hex{60}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VNEG` :math:`\hex{FD}~~\hex{61}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VPOPCNT` :math:`\hex{FD}~~\hex{62}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\ALLTRUE` :math:`\hex{FD}~~\hex{63}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\BITMASK` :math:`\hex{FD}~~\hex{64}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\NARROW\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{65}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I8X16.\NARROW\K{\_i16x8\_u}` :math:`\hex{FD}~~\hex{66}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\VCEIL` :math:`\hex{FD}~~\hex{67}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VFLOOR` :math:`\hex{FD}~~\hex{68}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VTRUNC` :math:`\hex{FD}~~\hex{69}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VNEAREST` :math:`\hex{FD}~~\hex{6A}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSHL` :math:`\hex{FD}~~\hex{6B}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{6C}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{6D}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VADD` :math:`\hex{FD}~~\hex{6E}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VADD\K{\_sat\_s}` :math:`\hex{FD}~~\hex{6F}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VADD\K{\_sat\_u}` :math:`\hex{FD}~~\hex{70}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSUB` :math:`\hex{FD}~~\hex{71}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~\hex{72}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~\hex{73}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VCEIL` :math:`\hex{FD}~~\hex{74}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VFLOOR` :math:`\hex{FD}~~\hex{75}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{76}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{77}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{78}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{79}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VTRUNC` :math:`\hex{FD}~~\hex{7A}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\AVGR\K{\_u}` :math:`\hex{FD}~~\hex{7B}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}` :math:`\hex{FD}~~\hex{7C}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}` :math:`\hex{FD}~~\hex{7D}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{7E}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}` :math:`\hex{FD}~~\hex{7F}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VABS` :math:`\hex{FD}~~\hex{80}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VNEG` :math:`\hex{FD}~~\hex{81}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\Q15MULRSAT\K{\_s}` :math:`\hex{FD}~~\hex{82}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\ALLTRUE` :math:`\hex{FD}~~\hex{83}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\BITMASK` :math:`\hex{FD}~~\hex{84}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\NARROW\K{\_i32x4\_s}` :math:`\hex{FD}~~\hex{85}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\NARROW\K{\_i32x4\_u}` :math:`\hex{FD}~~\hex{86}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~\hex{87}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~\hex{88}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~\hex{89}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~\hex{8A}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\VSHL` :math:`\hex{FD}~~\hex{8B}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{8C}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{8D}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VADD` :math:`\hex{FD}~~\hex{8E}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VADD\K{\_sat\_s}` :math:`\hex{FD}~~\hex{8F}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VADD\K{\_sat\_u}` :math:`\hex{FD}~~\hex{90}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSUB` :math:`\hex{FD}~~\hex{91}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSUB\K{\_sat\_s}` :math:`\hex{FD}~~\hex{92}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VSUB\K{\_sat\_u}` :math:`\hex{FD}~~\hex{93}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VNEAREST` :math:`\hex{FD}~~\hex{94}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMUL` :math:`\hex{FD}~~\hex{95}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{96}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{97}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{98}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{99}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\AVGR\K{\_u}` :math:`\hex{FD}~~\hex{9B}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~\hex{9C}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~\hex{9D}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTMUL\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~\hex{9E}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I16X8.\EXTMUL\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~\hex{9F}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VABS` :math:`\hex{FD}~~\hex{A0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VNEG` :math:`\hex{FD}~~\hex{A1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\ALLTRUE` :math:`\hex{FD}~~\hex{A3}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\BITMASK` :math:`\hex{FD}~~\hex{A4}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~\hex{A7}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~\hex{A8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~\hex{A9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~\hex{AA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\VSHL` :math:`\hex{FD}~~\hex{AB}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{AC}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{AD}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VADD` :math:`\hex{FD}~~\hex{AE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VSUB` :math:`\hex{FD}~~\hex{B1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMUL` :math:`\hex{FD}~~\hex{B5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMIN\K{\_s}` :math:`\hex{FD}~~\hex{B6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMIN\K{\_u}` :math:`\hex{FD}~~\hex{B7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMAX\K{\_s}` :math:`\hex{FD}~~\hex{B8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VMAX\K{\_u}` :math:`\hex{FD}~~\hex{B9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\DOT\K{\_i16x8\_s}` :math:`\hex{FD}~~\hex{BA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~\hex{BC}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~\hex{BD}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTMUL\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~\hex{BE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I32X4.\EXTMUL\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~\hex{BF}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VABS` :math:`\hex{FD}~~\hex{C0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VNEG` :math:`\hex{FD}~~\hex{C1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\ALLTRUE` :math:`\hex{FD}~~\hex{C3}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\BITMASK` :math:`\hex{FD}~~\hex{C4}~~\hex{01}` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{C7}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~\hex{C8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{C9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~\hex{CA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\VSHL` :math:`\hex{FD}~~\hex{CB}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VSHR\K{\_s}` :math:`\hex{FD}~~\hex{CC}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VSHR\K{\_u}` :math:`\hex{FD}~~\hex{CD}~~\hex{01}` :math:`[\V128~\I32] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VADD` :math:`\hex{FD}~~\hex{CE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VSUB` :math:`\hex{FD}~~\hex{D1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VMUL` :math:`\hex{FD}~~\hex{D5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VEQ` :math:`\hex{FD}~~\hex{D6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VNE` :math:`\hex{FD}~~\hex{D7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VLT\K{\_s}` :math:`\hex{FD}~~\hex{D8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VGT\K{\_s}` :math:`\hex{FD}~~\hex{D9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VLE\K{\_s}` :math:`\hex{FD}~~\hex{DA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\VGE\K{\_s}` :math:`\hex{FD}~~\hex{DB}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{DC}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~\hex{DD}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTMUL\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{DE}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\I64X2.\EXTMUL\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~\hex{DF}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution ` +:math:`\F32X4.\VABS` :math:`\hex{FD}~~\hex{E0}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VNEG` :math:`\hex{FD}~~\hex{E1}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VSQRT` :math:`\hex{FD}~~\hex{E3}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VADD` :math:`\hex{FD}~~\hex{E4}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VSUB` :math:`\hex{FD}~~\hex{E5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VMUL` :math:`\hex{FD}~~\hex{E6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VDIV` :math:`\hex{FD}~~\hex{E7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VMIN` :math:`\hex{FD}~~\hex{E8}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VMAX` :math:`\hex{FD}~~\hex{E9}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VPMIN` :math:`\hex{FD}~~\hex{EA}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VPMAX` :math:`\hex{FD}~~\hex{EB}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VABS` :math:`\hex{FD}~~\hex{EC}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VNEG` :math:`\hex{FD}~~\hex{ED}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VSQRT` :math:`\hex{FD}~~\hex{EF}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VADD` :math:`\hex{FD}~~\hex{F0}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VSUB` :math:`\hex{FD}~~\hex{F1}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VMUL` :math:`\hex{FD}~~\hex{F2}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VDIV` :math:`\hex{FD}~~\hex{F3}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VMIN` :math:`\hex{FD}~~\hex{F4}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VMAX` :math:`\hex{FD}~~\hex{F5}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPMIN` :math:`\hex{FD}~~\hex{F6}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPMAX` :math:`\hex{FD}~~\hex{F7}~~\hex{01}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_s}` :math:`\hex{FD}~~\hex{F8}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_u}` :math:`\hex{FD}~~\hex{F9}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VCONVERT\K{\_i32x4\_s}` :math:`\hex{FD}~~\hex{FA}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VCONVERT\K{\_i32x4\_u}` :math:`\hex{FD}~~\hex{FB}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_s\_zero}` :math:`\hex{FD}~~\hex{FC}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}` :math:`\hex{FD}~~\hex{FD}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~\hex{FE}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VCONVERT\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~\hex{FF}~~\hex{01}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\RELAXEDSWIZZLE` :math:`\hex{FD}~~\hex{80}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RELAXEDTRUNC\K{\_f32x4\_s}` :math:`\hex{FD}~~\hex{81}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RELAXEDTRUNC\K{\_f32x4\_u}` :math:`\hex{FD}~~\hex{82}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RELAXEDTRUNC\K{\_f64x2\_s}` :math:`\hex{FD}~~\hex{83}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RELAXEDTRUNC\K{\_f64x2\_u}` :math:`\hex{FD}~~\hex{84}~~\hex{02}` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\RELAXEDMADD` :math:`\hex{FD}~~\hex{85}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\RELAXEDNMADD` :math:`\hex{FD}~~\hex{86}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\RELAXEDMADD` :math:`\hex{FD}~~\hex{87}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\RELAXEDNMADD` :math:`\hex{FD}~~\hex{88}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I8X16.\RELAXEDLANESELECT` :math:`\hex{FD}~~\hex{89}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\RELAXEDLANESELECT` :math:`\hex{FD}~~\hex{8A}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RELAXEDLANESELECT` :math:`\hex{FD}~~\hex{8B}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I64X2.\RELAXEDLANESELECT` :math:`\hex{FD}~~\hex{8C}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\RELAXEDMIN` :math:`\hex{FD}~~\hex{8D}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\RELAXEDMAX` :math:`\hex{FD}~~\hex{8E}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\RELAXEDMIN` :math:`\hex{FD}~~\hex{8F}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\RELAXEDMAX` :math:`\hex{FD}~~\hex{90}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\RELAXEDQ15MULRS` :math:`\hex{FD}~~\hex{91}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_s}` :math:`\hex{FD}~~\hex{92}~~\hex{02}` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\I32X4.\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s}` :math:`\hex{FD}~~\hex{93}~~\hex{02}` :math:`[\V128~\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +==================================================== ==================================== ============================================= ============================================= =================================================================================== .. note:: Multi-byte opcodes are given with the shortest possible encoding in the table. diff --git a/document/core/exec/instructions.rst b/document/core/exec/instructions.rst index b96ed4f48..91dbcb922 100644 --- a/document/core/exec/instructions.rst +++ b/document/core/exec/instructions.rst @@ -416,18 +416,18 @@ Most vector instructions are defined in terms of generic numeric operators appli 3. Pop the value :math:`\V128.\VCONST~c_1` from the stack. -4. Let :math:`c'` be the result of computing :math:`\lanes^{-1}_{\I8X16}(\rswizzle(\lanes_{i8x16}(c_1), \lanes_{i8x16}(c_2)))`. +4. Let :math:`c'` be the result of computing :math:`\lanes^{-1}_{\I8X16}(\relaxedswizzle(\lanes_{i8x16}(c_1), \lanes_{i8x16}(c_2)))`. 5. Push the value :math:`\V128.\VCONST~c'` onto the stack. .. math:: \begin{array}{l} \begin{array}{lcl@{\qquad}l} - (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i8x16}\K{.}\rswizzle &\stepto& (\V128\K{.}\VCONST~c') + (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i8x16}\K{.}\relaxedswizzle &\stepto& (\V128\K{.}\VCONST~c') \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} - (\iff & c' = \lanes^{-1}_{i8x16}(\rswizzle(\lanes_{i8x16}(c_1), \lanes_{i8x16}(c_2))) + (\iff & c' = \lanes^{-1}_{i8x16}(\relaxedswizzle(\lanes_{i8x16}(c_1), \lanes_{i8x16}(c_2))) \end{array} \end{array} @@ -641,12 +641,12 @@ Most vector instructions are defined in terms of generic numeric operators appli \end{array} -.. _exec-rlaneselect: +.. _exec-relaxedlaneselect: :math:`t\K{x}N\K{.}\RELAXEDLANESELECT` ...................................... -1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. +1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. 2. Pop the value :math:`\V128.\VCONST~c_3` from the stack. @@ -656,7 +656,7 @@ Most vector instructions are defined in terms of generic numeric operators appli 5. Let :math:`B` be the :ref:`bit width ` :math:`|t|` of :ref:`value type ` :math:`t`. -6. Let :math:`c` be the result of computing :math:`\lanes^{-1}_{t\K{x}N}(\rlaneselect_{B}(\lanes_{t\K{x}N}(c_1), \lanes_{t\K{x}N}(c_2), \lanes_{t\K{x}N}(c_3)))`. +6. Let :math:`c` be the result of computing :math:`\lanes^{-1}_{t\K{x}N}(\relaxedlaneselect_{B}(\lanes_{t\K{x}N}(c_1), \lanes_{t\K{x}N}(c_2), \lanes_{t\K{x}N}(c_3)))`. 7. Push the value :math:`\V128.\VCONST~c` to the stack. @@ -667,7 +667,7 @@ Most vector instructions are defined in terms of generic numeric operators appli \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} - (\iff c = \lanes^{-1}_{t\K{x}N}(\rlaneselect_{|t|}(\lanes_{t\K{x}N}(c_1), \lanes_{t\K{x}N}(c_2), \lanes_{t\K{x}N}(c_3)))) \\ + (\iff c = \lanes^{-1}_{t\K{x}N}(\relaxedlaneselect_{|t|}(\lanes_{t\K{x}N}(c_1), \lanes_{t\K{x}N}(c_2), \lanes_{t\K{x}N}(c_3)))) \\ \end{array} \end{array} @@ -967,7 +967,7 @@ where: 3. Pop the value :math:`\V128.\VCONST~c_1` from the stack. -4. Let :math:`(i_1~i_2)^8` be the result of computing :math:`\ridotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` +4. Let :math:`(i_1~i_2)^8` be the result of computing :math:`\relaxeddotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` 5. Let :math:`j^8` be the result of computing :math:`\iadd_{16}(i_1, i_2)^8`. @@ -982,7 +982,7 @@ where: \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} - (\iff & (i_1~i_2)^8 = \ridotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ + (\iff & (i_1~i_2)^8 = \relaxeddotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ \wedge & j^8 = \iadd_{16}(i_1, i_2)^8 \\ \wedge & c = \lanes^{-1}_{\I16X8}(j^8)) \end{array} @@ -1000,7 +1000,7 @@ where: 4. Pop the value :math:`\V128.\VCONST~c_1` from the stack. -5. Let :math:`(i_1~i_2~i_3~i_4)^4` be the result of computing :math:`\ridotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` +5. Let :math:`(i_1~i_2~i_3~i_4)^4` be the result of computing :math:`\relaxeddotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` 6. Let :math:`k^4` be the result of computing :math:`\lanes_{\I32X4}(c_3)`. @@ -1017,7 +1017,7 @@ where: \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} - (\iff & (i_1~i_2~i_3~i_4)^4 = \ridotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ + (\iff & (i_1~i_2~i_3~i_4)^4 = \relaxeddotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ \wedge & k^4 = \lanes_{\I32X4}(c_3) \\ \wedge & j^4 = \iadd_{16}(i_1, i_2, i_3, i_4, k)^4 \\ \wedge & c = \lanes^{-1}_{\I32X4}(j^4)) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 92c994397..c7fbefc19 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -1989,38 +1989,38 @@ each environment globally chooses a fixed projection for each operator. itself can still be non-deterministic or partial. -.. _op-frmadd: +.. _op-relaxed_madd: -:math:`\frmadd_N(z_1, z_2, z_3)` -................................ +:math:`\relaxedmadd_N(z_1, z_2, z_3)` +..................................... Relaxed multiply-add (madd) allows for fused or unfused results. The function :math:`fma` is defined by |IEEE754|_ (Section 5.4.1) as *fusedMultiplyAdd*. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & \frmadd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), fma_N(z_1, z_2, z_3) ] \\ - & \frmadd_N(z_1, z_2, z_3) &=& fma_N(z_1, z_2, z_3) \\ + \EXPROFDET & \relaxedmadd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), fma_N(z_1, z_2, z_3) ] \\ + & \relaxedmadd_N(z_1, z_2, z_3) &=& fma_N(z_1, z_2, z_3) \\ \end{array} -.. _op-frnmadd: +.. _op-relaxed_nmadd: -:math:`\frnmadd_N(z_1, z_2, z_3)` -................................. +:math:`\relaxednmadd_N(z_1, z_2, z_3)` +...................................... Relaxed negative multiply-add allows for fused or unfused results. .. math:: \begin{array}{@{}llcll} - & \frnmadd_N(z_1, z_2, z_3) &=& \frmadd_N(-z_1, z_2, z_3) \\ + & \relaxednmadd_N(z_1, z_2, z_3) &=& \relaxedmadd_N(-z_1, z_2, z_3) \\ \end{array} -.. _op-rswizzle: +.. _op-relaxed_swizzle: -:math:`\rswizzle(a^n, s^n)` -........................... +:math:`\relaxedswizzle(a^n, s^n)` +................................. Relaxed swizzle lane is deterministic if the signed interpretation of the index is less than 16 (including negative values). @@ -2028,55 +2028,56 @@ if the signed interpretation of the index is less than 16 (including negative va .. math:: \begin{array}{@{}llcll} - & \rswizzlelane(i^n, j) &=& i[j] & (\iff j < 16) \\ - & \rswizzlelane(i^n, j) &=& 0 & (\iff \signed_8(j) < 0) \\ - \EXPROFDET & \rswizzlelane(i^n, j) &=& [ 0, i[j \mod n] ] & (\otherwise) \\ - & \rswizzlelane(i^n, j) &=& 0 & (\otherwise) \\ + & \relaxedswizzlelane(i^n, j) &=& i[j] & (\iff j < 16) \\ + & \relaxedswizzlelane(i^n, j) &=& 0 & (\iff \signed_8(j) < 0) \\ + \EXPROFDET & \relaxedswizzlelane(i^n, j) &=& [ 0, i[j \mod n] ] & (\otherwise) \\ + & \relaxedswizzlelane(i^n, j) &=& 0 & (\otherwise) \\ \\ - & \rswizzle(a^n, s^n) &=& \X{rsl}_0 \dots \X{rsl}_{n-1} \\ - & \qquad \where \X{rsl}_i &=& \rswizzlelane(a^n, s^n[i]) + & \relaxedswizzle(a^n, s^n) &=& \X{rsl}_0 \dots \X{rsl}_{n-1} \\ + & \qquad \where \X{rsl}_i &=& \relaxedswizzlelane(a^n, s^n[i]) \end{array} -.. _op-rtrunc: -.. _op-rtrunc_u: +.. _op-relaxed_trunc: +.. _op-relaxed_trunc_u: -:math:`\rtrunc^u_{M,N}(z)` -.......................... +:math:`\relaxedtrunc^u_{M,N}(z)` +................................ Relaxed unsigned truncation converts floating point numbers to integers. The result for NaN's and out-of-range values is host-dependent. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & \rtrunc^u_{M,N}(\pm \NAN(n)) &=& [ 0, 2^{N}-1 ] \\ - \EXPROFDET & \rtrunc^u_{M,N}(\pm q) &=& \truncu_{M,N}(\pm q) & (\iff -1 < \trunc(\pm q) < 2^N) \\ - \EXPROFDET & \rtrunc^u_{M,N}(\pm p) &=& [ \truncsatu_{M,N}(\pm p), 2^{N}-1 ] & (\otherwise) \\ - & \rtrunc^u_{M,N}(\pm p) &=& \truncsatu_{M,N}(\pm p) & (\otherwise) \\ + \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm \NAN(n)) &=& [ 0, 2^{N}-1 ] \\ + \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm q) &=& \truncu_{M,N}(\pm q) & (\iff -1 < \trunc(\pm q) < 2^N) \\ + \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm p) &=& [ \truncsatu_{M,N}(\pm p), 2^{N}-1 ] & (\otherwise) \\ + & \relaxedtrunc^u_{M,N}(\pm p) &=& \truncsatu_{M,N}(\pm p) & (\otherwise) \\ \end{array} -.. _op-rtrunc_s: +.. _op-relaxed_trunc_s: -:math:`\rtrunc^s_{M,N}(z)` -.......................... +:math:`\relaxedtrunc^s_{M,N}(z)` +................................ Relaxed signed truncation converts floating point numbers to integers. The result for NaN's and out-of-range values is host-dependent. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & \rtrunc^s_{M,N}(\pm \NAN(n)) &=& [ 0, -2^{N-1} ] \\ - \EXPROFDET & \rtrunc^s_{M,N}(\pm q) &=& \truncs_{M,N}(\pm q) & (\iff -2^{N-1} - 1 < \trunc(\pm q) < 2^{N-1}) \\ - \EXPROFDET & \rtrunc^s_{M,N}(\pm p) &=& [ \truncsats_{M,N}(\pm p), -2^{N-1} ] & (\otherwise) \\ - & \rtrunc^s_{M,N}(\pm p) &=& \truncsats_{M,N}(\pm p) & (\otherwise) \\ + \EXPROFDET & \relaxedtrunc^s_{M,N}(\pm \NAN(n)) &=& [ 0, -2^{N-1} ] \\ + \EXPROFDET & \relaxedtrunc^s_{M,N}(\pm q) &=& \truncs_{M,N}(\pm q) & (\iff -2^{N-1} - 1 < \trunc(\pm q) < 2^{N-1}) \\ + \EXPROFDET & \relaxedtrunc^s_{M,N}(\pm p) &=& [ \truncsats_{M,N}(\pm p), -2^{N-1} ] & (\otherwise) \\ + & \relaxedtrunc^s_{M,N}(\pm p) &=& \truncsats_{M,N}(\pm p) & (\otherwise) \\ \end{array} -.. _op-rlaneselect: +.. _op-relaxed_lane_select: +.. _op-relaxed_lane: -:math:`\rlaneselect_B(a^n, b^n, c^n)` -..................................... +:math:`\relaxedlaneselect_B(a^n, b^n, c^n)` +........................................... Relaxed lane selection is deterministic when all bits are set or unset in the mask. Otherwise depending on the host, either only the top bit is examined, or @@ -2084,72 +2085,72 @@ all bits are examined (i.e. it becomes a bit select). .. math:: \begin{array}{@{}llcll} - & relaxed\_lane_N(i_1, i_2, 2^N-1) &=& i_1 \\ - & relaxed\_lane_N(i_1, i_2, 0) &=& i_2 \\ - \EXPROFDET & relaxed\_lane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_1 ] & (\iff \signed_N(i_3) < 0) \\ - \EXPROFDET & relaxed\_lane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_2 ] & (\otherwise) \\ - & relaxed\_lane_N(i_1, i_2, i_3) &=& \ibitselect_N(i_1, i_2, i_3) & (\otherwise) \\ + & \relaxedlane_N(i_1, i_2, 2^N-1) &=& i_1 \\ + & \relaxedlane_N(i_1, i_2, 0) &=& i_2 \\ + \EXPROFDET & \relaxedlane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_1 ] & (\iff \signed_N(i_3) < 0) \\ + \EXPROFDET & \relaxedlane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_2 ] & (\otherwise) \\ + & \relaxedlane_N(i_1, i_2, i_3) &=& \ibitselect_N(i_1, i_2, i_3) & (\otherwise) \\ \\ - & \rlaneselect_B(a^n, b^n, c^n) &=& rll_0 \dots rll_{n-1} \\ - & \qquad \where rll_i &=& relaxed\_lane_B(a^n[i], b^n[i], c^n[i]) \\ + & \relaxedlaneselect_B(a^n, b^n, c^n) &=& rll_0 \dots rll_{n-1} \\ + & \qquad \where rll_i &=& \relaxedlane_B(a^n[i], b^n[i], c^n[i]) \\ \end{array} -.. _op-frmin: +.. _op-relaxed_min: -:math:`\frmin_N(z_1, z_2)` -.......................... +:math:`\relaxedmin_N(z_1, z_2)` +............................... Relaxed minimum differs from regular minimum when inputs are NaN's or zeroes with different signs. It allows for implementation to return the first or second input when either input is a NaN. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & \frmin_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ - \EXPROFDET & \frmin_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ - \EXPROFDET & \frmin_N(\pm 0, \mp 0) &=& [ -0, \pm 0, \mp 0, -0 ] \\ - & \frmin_N(z_1, z_2) &=& \fmin_N(z_1, z_2) & (\otherwise) \\ + \EXPROFDET & \relaxedmin_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ + \EXPROFDET & \relaxedmin_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ + \EXPROFDET & \relaxedmin_N(\pm 0, \mp 0) &=& [ -0, \pm 0, \mp 0, -0 ] \\ + & \relaxedmin_N(z_1, z_2) &=& \fmin_N(z_1, z_2) & (\otherwise) \\ \end{array} -.. _op-frmax: +.. _op-relaxed_max: -:math:`\frmax_N(z_1, z_2)` -.......................... +:math:`\relaxedmax_N(z_1, z_2)` +............................... Relaxed maximum differs from regular maximum when inputs are NaN's or zeroes with different signs. It allows for implementations to return the first or second input when either input is a NaN. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & \frmax_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ - \EXPROFDET & \frmax_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ - \EXPROFDET & \frmax_N(\pm 0, \mp 0) &=& [ +0, \pm 0, \mp 0, +0 ] \\ - & \frmax_N(z_1, z_2) &=& \fmax_N(z_1, z_2) & (\otherwise) \\ + \EXPROFDET & \relaxedmax_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ + \EXPROFDET & \relaxedmax_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ + \EXPROFDET & \relaxedmax_N(\pm 0, \mp 0) &=& [ +0, \pm 0, \mp 0, +0 ] \\ + & \relaxedmax_N(z_1, z_2) &=& \fmax_N(z_1, z_2) & (\otherwise) \\ \end{array} -.. _op-irq15mulr_s: +.. _op-relaxed_q15mulr_s: -:math:`\irq15mulrs_N(i_1, i_2)` -............................... +:math:`\relaxedq15mulrs_N(i_1, i_2)` +.................................... .. math:: \begin{array}{@{}llcll} - \EXPROFDET & \irq15mulrs_N(i_1, i_2) &=& [ \sats_N(i), i \mod 2^N ] & (\iff i = \ishrs_N(i_1 \cdot i_2 + 2^{14}, 15)) \\ - & \irq15mulrs_N(i_1, i_2) &=& \iq15mulrsats(i_1, i_2) + \EXPROFDET & \relaxedq15mulrs_N(i_1, i_2) &=& [ \sats_N(i), i \mod 2^N ] & (\iff i = \ishrs_N(i_1 \cdot i_2 + 2^{14}, 15)) \\ + & \relaxedq15mulrs_N(i_1, i_2) &=& \iq15mulrsats(i_1, i_2) \end{array} -.. _op-ridotmul: +.. _op-relaxed_dot_mul: -:math:`\ridotmul_{M,N}(i_1, i_2)` -................................. +:math:`\relaxeddotmul_{M,N}(i_1, i_2)` +...................................... Relaxed integer dot product differs from regular integer dot product when the elements of the input have their most significant bit set. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & \ridotmul_{M,N}(i_1, i_2) &=& [ \imul_N(\signed_M(i_1), i_2), \imul_N(\signed_M(i_1), \signed_M(i_2)) ] \\ - & \ridotmul_{M,N}(i_1, i_2) &=& \imul_N(\extends_{M,N}(i_1), \extends_{M,N}(i_2)) \\ + \EXPROFDET & \relaxeddotmul_{M,N}(i_1, i_2) &=& [ \imul_N(\signed_M(i_1), i_2), \imul_N(\signed_M(i_1), \signed_M(i_2)) ] \\ + & \relaxeddotmul_{M,N}(i_1, i_2) &=& \imul_N(\extends_{M,N}(i_1), \extends_{M,N}(i_2)) \\ \end{array} diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 77a51e35e..0d0c0f3bb 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -1203,16 +1203,17 @@ .. |narrowu| mathdef:: \xref{exec/numerics}{op-narrow_u}{\F{narrow}^{\K{u}}} .. |narrows| mathdef:: \xref{exec/numerics}{op-narrow_s}{\F{narrow}^{\K{s}}} -.. |frmadd| mathdef:: \xref{exec/numerics}{op-frmaddd}{\F{frelaxed\_madd}} -.. |frnmadd| mathdef:: \xref{exec/numerics}{op-frnmadd}{\F{frelaxed\_nmadd}} -.. |rswizzlelane| mathdef:: \xref{exec/numerics}{op-rswizzle_lane}{\F{relaxed\_swizzle\_lane}} -.. |rswizzle| mathdef:: \xref{exec/numerics}{op-rswizzle}{\F{relaxed\_swizzle}} -.. |rtrunc| mathdef:: \xref{exec/numerics}{op-rtrunc}{\F{relaxed\_trunc}} -.. |rlaneselect| mathdef:: \xref{exec/numerics}{op-rlaneselect}{\F{relaxed\_laneselect}} -.. |frmin| mathdef:: \xref{exec/numerics}{op-frmin}{\F{frelaxed\_min}} -.. |frmax| mathdef:: \xref{exec/numerics}{op-frmax}{\F{frelaxed\_max}} -.. |irq15mulrs| mathdef:: \xref{exec/numerics}{op-irq15mulr_s}{\F{irelaxed\_q15mulr\_s}} -.. |ridotmul| mathdef:: \xref{exec/numerics}{op-ridotmul}{\F{relaxed\_dot\_mul}} +.. |relaxedmadd| mathdef:: \xref{exec/numerics}{op-relaxed_madd}{\F{frelaxed\_madd}} +.. |relaxednmadd| mathdef:: \xref{exec/numerics}{op-relaxed_nmadd}{\F{frelaxed\_nmadd}} +.. |relaxedswizzlelane| mathdef:: \xref{exec/numerics}{op-relaxed_swizzle_lane}{\F{relaxed\_swizzle\_lane}} +.. |relaxedswizzle| mathdef:: \xref{exec/numerics}{op-relaxed_swizzle}{\F{relaxed\_swizzle}} +.. |relaxedtrunc| mathdef:: \xref{exec/numerics}{op-relaxed_trunc}{\F{relaxed\_trunc}} +.. |relaxedlane| mathdef:: \xref{exec/numerics}{op-relaxed_lane}{\F{relaxed\_lane}} +.. |relaxedlaneselect| mathdef:: \xref{exec/numerics}{op-relaxed_lane_select}{\F{relaxed\_laneselect}} +.. |relaxedmin| mathdef:: \xref{exec/numerics}{op-relaxed_min}{\F{frelaxed\_min}} +.. |relaxedmax| mathdef:: \xref{exec/numerics}{op-relaxed_max}{\F{frelaxed\_max}} +.. |relaxedq15mulrs| mathdef:: \xref{exec/numerics}{op-relaxed_q15mulr_s}{\F{irelaxed\_q15mulr\_s}} +.. |relaxeddotmul| mathdef:: \xref{exec/numerics}{op-relaxed_dot_mul}{\F{relaxed\_dot\_mul}} .. Numerics, meta functions diff --git a/document/core/valid/instructions.rst b/document/core/valid/instructions.rst index ed09468be..393703cff 100644 --- a/document/core/valid/instructions.rst +++ b/document/core/valid/instructions.rst @@ -487,7 +487,7 @@ The following auxiliary function denotes the number of lanes in a vector shape, } -.. _valid-rlaneselect: +.. _valid-relaxedlaneselect: :math:`\shape\K{.}\RELAXEDLANESELECT` ..................................... From a7d4e96b8d9ee120708193ac429e4541d8939e77 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 14 Feb 2023 18:16:26 +0000 Subject: [PATCH 088/117] Update changes --- document/core/appendix/changes.rst | 18 ++++++++++++++++++ document/core/syntax/instructions.rst | 1 + 2 files changed, 19 insertions(+) diff --git a/document/core/appendix/changes.rst b/document/core/appendix/changes.rst index 339cb25f9..7d66483d8 100644 --- a/document/core/appendix/changes.rst +++ b/document/core/appendix/changes.rst @@ -7,6 +7,24 @@ Change History Since the original release 1.0 of the WebAssembly specification, a number of proposals for extensions have been integrated. The following sections provide an overview of what has changed. +Release 2.1 +~~~~~~~~~~~ + +.. index:: instruction, SIMD + +Relaxed vector instructions +........................... + +Added new relaxed vector instructions, which are vector instructions whose results are host-dependent. + +* New binary :ref:`relaxed vector instruction `: :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_min}`, :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_max}`, :math:`\K{i16x8.relaxed\_q15mulr\_s}`, :math:`\K{i16x8.relaxed\_dot\_i8x16\_i7x16\_s}` + +* New ternary :ref:`relaxed vector instruction `: :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_madd}`, :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_nmadd}`, :math:`\K{i}\!N\!\K{x}\!M\!\K{.relaxed\_laneselect}`, :math:`\K{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s}` + +* New conversion :ref:`relaxed vector instructions `::math:`\K{i32x4.relaxed\_trunc\_f32x4\_}\sx`, :math:`\K{i32x4.relaxed\_trunc\_f64x2\_}\sx\K{\_zero}` + +* New byte reordering :ref:`relaxed vector instruction `: :math:`\K{i8x16.relaxed\_swizzle}` + Release 2.0 ~~~~~~~~~~~ diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst index f5ea8454a..7908d2cd4 100644 --- a/document/core/syntax/instructions.rst +++ b/document/core/syntax/instructions.rst @@ -193,6 +193,7 @@ Occasionally, it is convenient to group operators together according to the foll .. _syntax-rvfbinop: .. _syntax-rvfternop: .. _syntax-instr-vec: +.. _syntax-instr-relaxed: Vector Instructions ~~~~~~~~~~~~~~~~~~~ From 824c9fd0c8e59b611f5b8a1d6b4bdb2fb7fa3cce Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 15 Feb 2023 00:51:30 +0000 Subject: [PATCH 089/117] Text for relaxed q15muls --- document/core/exec/numerics.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index c7fbefc19..06e5a3f14 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2135,6 +2135,9 @@ It allows for implementations to return the first or second input when either in :math:`\relaxedq15mulrs_N(i_1, i_2)` .................................... +Relaxed Q15 multiply differs from regular Q15 multiply when the multiplication results overflows (i.e. when both inputs are -32768). +It allows for implementations to either wrap around or saturate. + .. math:: \begin{array}{@{}llcll} \EXPROFDET & \relaxedq15mulrs_N(i_1, i_2) &=& [ \sats_N(i), i \mod 2^N ] & (\iff i = \ishrs_N(i_1 \cdot i_2 + 2^{14}, 15)) \\ From 61fd687618b0966580a8d13160d58e780960441a Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Wed, 15 Feb 2023 18:29:16 +0000 Subject: [PATCH 090/117] Typo --- document/core/exec/numerics.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 06e5a3f14..e7b893960 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -1973,8 +1973,8 @@ Conversions .. _relaxed-ops: -Relaxed operators -~~~~~~~~~~~~~~~~~ +Relaxed operations +~~~~~~~~~~~~~~~~~~ The result of *relaxed* operators are *host-dependent*, because the set of possible results may depend on properties of the host environment (such as From 70bf915a1329fd525e697abc47a0068e63652d6e Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Mon, 27 Feb 2023 19:14:06 +0000 Subject: [PATCH 091/117] Fix semantics for dot relaxed dot allows the intermediate 16-bit to be saturated (if the underlying host uses signed * unsigned 8 bit, the dot product, 8-bit * 8-bit + 8-bit * -bit) overflows. --- document/core/exec/instructions.rst | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/document/core/exec/instructions.rst b/document/core/exec/instructions.rst index 91dbcb922..1fddba5a9 100644 --- a/document/core/exec/instructions.rst +++ b/document/core/exec/instructions.rst @@ -969,7 +969,7 @@ where: 4. Let :math:`(i_1~i_2)^8` be the result of computing :math:`\relaxeddotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` -5. Let :math:`j^8` be the result of computing :math:`\iadd_{16}(i_1, i_2)^8`. +5. Let :math:`j^8` be the result of computing :math:`\sats_{16}(i_1 + i_2)^8`. 6. Let :math:`c` be the result of computing :math:`\lanes^{-1}_{\I16X8}(j^8)`. @@ -983,7 +983,7 @@ where: \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} (\iff & (i_1~i_2)^8 = \relaxeddotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ - \wedge & j^8 = \iadd_{16}(i_1, i_2)^8 \\ + \wedge & j^8 = \sats_{16}(i_1, i_2)^8 \\ \wedge & c = \lanes^{-1}_{\I16X8}(j^8)) \end{array} \end{array} @@ -1000,15 +1000,19 @@ where: 4. Pop the value :math:`\V128.\VCONST~c_1` from the stack. -5. Let :math:`(i_1~i_2~i_3~i_4)^4` be the result of computing :math:`\relaxeddotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` +5. Let :math:`(i_1~i_2)^8` be the result of computing :math:`\relaxeddotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` -6. Let :math:`k^4` be the result of computing :math:`\lanes_{\I32X4}(c_3)`. +6. Let :math:`(j_1~j_2)^4` be the result of computing :math:`\sats_{16}(i_1 + i_2)^8`. -7. Let :math:`j^4` be the result of computing :math:`\iadd_{32}(i_1, i_2, i_3, i_4, k)^4`. +7. Let :math:`j^4` be the result of computing :math:`\iadd_{32}(\extend^{s}_{16, 32}(j_1), \extend^{s}_{16, 32}(j_2))^4`. -8. Let :math:`c` be the result of computing :math:`\lanes^{-1}_{\I32X4}(j^4)`. +8. Let :math:`k^4` be the result of computing :math:`\lanes_{\I32X4}(c_3)`. -9. Push the value :math:`\V128.\VCONST~c` onto the stack. +9. Let :math:`l^4` be the result of computing :math:`\iadd_{32}(j, k)^4`. + +10. Let :math:`c` be the result of computing :math:`\lanes^{-1}_{\I32X4}(l^4)`. + +11. Push the value :math:`\V128.\VCONST~c` onto the stack. .. math:: \begin{array}{l} @@ -1017,10 +1021,12 @@ where: \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} - (\iff & (i_1~i_2~i_3~i_4)^4 = \relaxeddotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ + (\iff & (i_1~i_2)^8 = \relaxeddotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ + \wedge & (j_1~j_2)^4 = \sats_{16}(i_1 + i_2)^8 \\ + \wedge & j^4 = \iadd_{32}(\extend^{s}_{16, 32}(j_1), \extend^{s}_{16, 32}(j_2))^4 \\ \wedge & k^4 = \lanes_{\I32X4}(c_3) \\ - \wedge & j^4 = \iadd_{16}(i_1, i_2, i_3, i_4, k)^4 \\ - \wedge & c = \lanes^{-1}_{\I32X4}(j^4)) + \wedge & l^4 = \iadd_{32}(j, k)^4 \\ + \wedge & c = \lanes^{-1}_{\I32X4}(l^4)) \end{array} \end{array} From 4073d2731579a3418251548cc3b520c76d70cdc8 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 2 Mar 2023 12:15:01 -0800 Subject: [PATCH 092/117] Update document/core/appendix/changes.rst Co-authored-by: Andreas Rossberg --- document/core/appendix/changes.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/document/core/appendix/changes.rst b/document/core/appendix/changes.rst index 7d66483d8..bcd1e05d6 100644 --- a/document/core/appendix/changes.rst +++ b/document/core/appendix/changes.rst @@ -15,7 +15,7 @@ Release 2.1 Relaxed vector instructions ........................... -Added new relaxed vector instructions, which are vector instructions whose results are host-dependent. +Added new relaxed vector instructions, which are vector instructions whose behaviour is host-dependent. * New binary :ref:`relaxed vector instruction `: :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_min}`, :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_max}`, :math:`\K{i16x8.relaxed\_q15mulr\_s}`, :math:`\K{i16x8.relaxed\_dot\_i8x16\_i7x16\_s}` From 753c77996039b813de2ca267bdae4021b1e3bb2d Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 2 Mar 2023 12:15:15 -0800 Subject: [PATCH 093/117] Update document/core/appendix/changes.rst Co-authored-by: Andreas Rossberg --- document/core/appendix/changes.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/document/core/appendix/changes.rst b/document/core/appendix/changes.rst index bcd1e05d6..9be03e66a 100644 --- a/document/core/appendix/changes.rst +++ b/document/core/appendix/changes.rst @@ -10,7 +10,7 @@ The following sections provide an overview of what has changed. Release 2.1 ~~~~~~~~~~~ -.. index:: instruction, SIMD +.. index:: instruction, vector instruction, SIMD Relaxed vector instructions ........................... From f59b512dae438485363bc13bc37a3754fa18455b Mon Sep 17 00:00:00 2001 From: Zhi An Ng Date: Thu, 2 Mar 2023 12:16:31 -0800 Subject: [PATCH 094/117] Move changes down --- document/core/appendix/changes.rst | 36 +++++++++++++++--------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/document/core/appendix/changes.rst b/document/core/appendix/changes.rst index 9be03e66a..3f806ae08 100644 --- a/document/core/appendix/changes.rst +++ b/document/core/appendix/changes.rst @@ -7,24 +7,6 @@ Change History Since the original release 1.0 of the WebAssembly specification, a number of proposals for extensions have been integrated. The following sections provide an overview of what has changed. -Release 2.1 -~~~~~~~~~~~ - -.. index:: instruction, vector instruction, SIMD - -Relaxed vector instructions -........................... - -Added new relaxed vector instructions, which are vector instructions whose behaviour is host-dependent. - -* New binary :ref:`relaxed vector instruction `: :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_min}`, :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_max}`, :math:`\K{i16x8.relaxed\_q15mulr\_s}`, :math:`\K{i16x8.relaxed\_dot\_i8x16\_i7x16\_s}` - -* New ternary :ref:`relaxed vector instruction `: :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_madd}`, :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_nmadd}`, :math:`\K{i}\!N\!\K{x}\!M\!\K{.relaxed\_laneselect}`, :math:`\K{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s}` - -* New conversion :ref:`relaxed vector instructions `::math:`\K{i32x4.relaxed\_trunc\_f32x4\_}\sx`, :math:`\K{i32x4.relaxed\_trunc\_f64x2\_}\sx\K{\_zero}` - -* New byte reordering :ref:`relaxed vector instruction `: :math:`\K{i8x16.relaxed\_swizzle}` - Release 2.0 ~~~~~~~~~~~ @@ -155,6 +137,24 @@ Added vector type and instructions that manipulate multiple numeric values in pa * New injection/projection :ref:`vector instructions `: :math:`\K{i}\!N\!\K{x}\!M\!\K{.splat}`, :math:`\K{f}\!N\!\K{x}\!M\!\K{.splat}`, :math:`\K{i}\!N\!\K{x}\!M\!\K{.bitmask}` +Release 2.1 +~~~~~~~~~~~ + +.. index:: instruction, vector instruction, SIMD + +Relaxed vector instructions +........................... + +Added new relaxed vector instructions, which are vector instructions whose behaviour is host-dependent. + +* New binary :ref:`relaxed vector instruction `: :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_min}`, :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_max}`, :math:`\K{i16x8.relaxed\_q15mulr\_s}`, :math:`\K{i16x8.relaxed\_dot\_i8x16\_i7x16\_s}` + +* New ternary :ref:`relaxed vector instruction `: :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_madd}`, :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_nmadd}`, :math:`\K{i}\!N\!\K{x}\!M\!\K{.relaxed\_laneselect}`, :math:`\K{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s}` + +* New conversion :ref:`relaxed vector instructions `::math:`\K{i32x4.relaxed\_trunc\_f32x4\_}\sx`, :math:`\K{i32x4.relaxed\_trunc\_f64x2\_}\sx\K{\_zero}` + +* New byte reordering :ref:`relaxed vector instruction `: :math:`\K{i8x16.relaxed\_swizzle}` + .. [#proposal-signext] https://github.com/WebAssembly/spec/tree/main/proposals/sign-extension-ops/ From 8afc0d148937b08023d601e2f226ca761c203572 Mon Sep 17 00:00:00 2001 From: Zhi An Ng Date: Thu, 2 Mar 2023 12:24:07 -0800 Subject: [PATCH 095/117] Add FMA definition --- document/core/exec/numerics.rst | 9 ++++++--- document/core/util/macros.def | 1 + 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index e7b893960..fb062bbcc 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -1990,17 +1990,20 @@ each environment globally chooses a fixed projection for each operator. .. _op-relaxed_madd: +.. _op-fma: :math:`\relaxedmadd_N(z_1, z_2, z_3)` ..................................... -Relaxed multiply-add (madd) allows for fused or unfused results. The function :math:`fma` is +Relaxed multiply-add (madd) allows for fused or unfused results. The function :math:`\fma` is defined by |IEEE754|_ (Section 5.4.1) as *fusedMultiplyAdd*. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & \relaxedmadd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), fma_N(z_1, z_2, z_3) ] \\ - & \relaxedmadd_N(z_1, z_2, z_3) &=& fma_N(z_1, z_2, z_3) \\ + \EXPROFDET & \relaxedmadd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), \fma_N(z_1, z_2, z_3) ] \\ + & \relaxedmadd_N(z_1, z_2, z_3) &=& \fma_N(z_1, z_2, z_3) \\ + \\ + & \fma_N(z_1, z_2, z_3) &=& \ieee_N(z_1 \cdot z_2 + z_3) \\ \end{array} diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 0d0c0f3bb..24b30ac3f 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -1203,6 +1203,7 @@ .. |narrowu| mathdef:: \xref{exec/numerics}{op-narrow_u}{\F{narrow}^{\K{u}}} .. |narrows| mathdef:: \xref{exec/numerics}{op-narrow_s}{\F{narrow}^{\K{s}}} +.. |fma| mathdef:: \xref{exec/numerics}{op-fma}{\F{fma}} .. |relaxedmadd| mathdef:: \xref{exec/numerics}{op-relaxed_madd}{\F{frelaxed\_madd}} .. |relaxednmadd| mathdef:: \xref{exec/numerics}{op-relaxed_nmadd}{\F{frelaxed\_nmadd}} .. |relaxedswizzlelane| mathdef:: \xref{exec/numerics}{op-relaxed_swizzle_lane}{\F{relaxed\_swizzle\_lane}} From 46c9480ac9a158ba39157de042f2dc61141d2cdc Mon Sep 17 00:00:00 2001 From: Zhi An Ng Date: Thu, 2 Mar 2023 12:38:01 -0800 Subject: [PATCH 096/117] Reword fma --- document/core/exec/numerics.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index fb062bbcc..a49d43515 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -1995,8 +1995,8 @@ each environment globally chooses a fixed projection for each operator. :math:`\relaxedmadd_N(z_1, z_2, z_3)` ..................................... -Relaxed multiply-add (madd) allows for fused or unfused results. The function :math:`\fma` is -defined by |IEEE754|_ (Section 5.4.1) as *fusedMultiplyAdd*. +Relaxed multiply-add (madd) allows for fused or unfused results. The function :math:`\fma` +is the same as *fusedMultiplyAdd* defined by |IEEE754|_ (Section 5.4.1). .. math:: \begin{array}{@{}llcll} From a9ef2e447c273919b0fae3e0640852d58828ac0f Mon Sep 17 00:00:00 2001 From: Zhi An Ng Date: Thu, 2 Mar 2023 12:38:58 -0800 Subject: [PATCH 097/117] Remove parens --- document/core/exec/numerics.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index a49d43515..9804630af 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -1995,7 +1995,7 @@ each environment globally chooses a fixed projection for each operator. :math:`\relaxedmadd_N(z_1, z_2, z_3)` ..................................... -Relaxed multiply-add (madd) allows for fused or unfused results. The function :math:`\fma` +Relaxed multiply-add allows for fused or unfused results. The function :math:`\fma` is the same as *fusedMultiplyAdd* defined by |IEEE754|_ (Section 5.4.1). .. math:: From b00d45163a8535a59b1d2947abcd1fa0550ff49a Mon Sep 17 00:00:00 2001 From: Deepti Gandluri Date: Mon, 6 Mar 2023 23:04:23 -0800 Subject: [PATCH 098/117] Add entropy.md to discuss fingerprinting, and compat concerns (#83) --- proposals/relaxed-simd/entropy.md | 57 +++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 proposals/relaxed-simd/entropy.md diff --git a/proposals/relaxed-simd/entropy.md b/proposals/relaxed-simd/entropy.md new file mode 100644 index 000000000..52898e233 --- /dev/null +++ b/proposals/relaxed-simd/entropy.md @@ -0,0 +1,57 @@ +# Entropy, Compat and Usage patterns + +The Relaxed SIMD proposal adds new operations that take advantage of the underlying hardware for accelerated performance by loosening the portability constraints of fixed-width SIMD, or adding new instructions that introduce local non-determinisim. This introduces a few potential risks specifically for browser engine implementations, though it’s possible that one or more of these might be applicable to other environments: +* Identifying underlying characteristics of the device (processor information if the engine that implements this proposal used the most optimal lowerings) +* Possibly identifying information about the browser currently in use (i.e. if a sufficiently motivated user writes a hand tuned Wasm function when engines use different lowerings for instructions) +* Compatibility risks, i.e. if code compiled for one browser works differently on a different browser (This is specific to observable behavior changes, and not performance differences) + +This document is an attempt to collate information that is already available in the issues filed for each of the operations on fingerprinting risk, quantify the risk for fingerprinting/compat issues and provide some information about usage patterns. + +## Instruction summary + +* **relaxed i8x16.swizzle**
+ *Entropy exposed:* Differences between x86/ARM
+ *Deterministic lowering:* Available
+ *Compat risk:* Low, as the differences exposed are for out of range indices
+ [*Issue link*](https://github.com/WebAssembly/relaxed-simd/issues/22) +* **relaxed i32x4.trunc_{f32x4, f64x2} operations**
+ *Entropy exposed:* Differences between x86/ARM
+ *Deterministic lowering:* Available
+ *Compat risk:* Low, as the differing behavior is for out of range values, and NaNs
+ [*Issue link*](https://github.com/WebAssembly/relaxed-simd/issues/21)
+* **qfma, qfmns**
+ *Entropy exposed:* Differences between hardware that has native FMA support, and hardware that does not.
+ *Deterministic lowering:* Not available, but depending on underlying hardware, the results can only be fused, or unfused.
+ *Compat risk:* Potentially divergent behavior based on hardware FMA support
+ *Mitigating reasons to include:* Most modern hardware do have native FMA support, performance wins are significant, operations are difficult to emulate
+ [*Issue link*](https://github.com/WebAssembly/simd/pull/79)
+* **{i8x16, i16x8, i32x4, i64x2}.laneselect**
+ *Entropy exposed:* x86/ARM
+ *Deterministic lowering:* Available
+ *Compat risk:* Medium, architectures vary on which bit is used for lane selection
+ [*Issue link*](https://github.com/WebAssembly/relaxed-simd/issues/17)
+* **{f32x4, f64x2}.{min,max}**
+ *Entropy exposed:* x86/ARM
+ *Deterministic lowering:* Available
+ *Compat risk:* Low, varying outputs when one of the inputs is NaN, or +0, -0
+ [*Issue link*](https://github.com/WebAssembly/relaxed-simd/issues/33)
+* **I16x8.relaxed_q15mulr_s**
+ *Entropy exposed:* x86/ARM
+ *Deterministic lowering:* Available
+ *Compat risk:* Low, different behaviors only in the overflow case
+ [*Issue link*](https://github.com/WebAssembly/relaxed-simd/issues/40)
+* **Dot product instructions**
+ *Entropy exposed:* x86/ARM, and whether the Dot product extension is supported in the most optimal codegen
+ *Deterministic lowering:* Available, but only when not using the most optimal codegen
+ *Compat risk:* Medium for architectures that support the Dot product extensions as they vary in saturating/wrapping behavior of intermediate results
*Mitigating reasons to include:* [Performance](https://docs.google.com/presentation/d/1xlyO1ly2Fbo2Up5ZuV_BTSwiNpCwPygag09XQRjclSA/edit#slide=id.g1fee95a4c4f_0_0)
+ [*Issue link*](https://github.com/WebAssembly/relaxed-simd/issues/52) + +## Usage patterns + +One of the things to note here, for compat especially, is to lay out the usage patterns, or specifically when these instructions are generated. As the proposal is still in the experimental state, the only way to currently experiment with these instructions are to call the clang built-ins directly, and experiment with them on an engine that has these instructions available as a prototype. + +In the future, these can be invoked using: + * Wasm Intrinsic header files + * Possibly in the autovectorizer, but only when flags like `-ffast-math` are used, that assume inputs and/or results are not NaNs or +-Infs. + +The thing to note here is that by either explicitly calling the intrinsics, or using specific compiler flags is a high enough threshold that this type of local non-determinism is not something a user would encounter by default, i.e. these instructions can only be used deliberately, and the proposal assumes a specialized usage. From 4afd146464237d411e7d1ff587bf1194c3c2eea1 Mon Sep 17 00:00:00 2001 From: Deepti Gandluri Date: Mon, 6 Mar 2023 23:05:19 -0800 Subject: [PATCH 099/117] Rename entropy.md to Entropy.md --- proposals/relaxed-simd/{entropy.md => Entropy.md} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename proposals/relaxed-simd/{entropy.md => Entropy.md} (100%) diff --git a/proposals/relaxed-simd/entropy.md b/proposals/relaxed-simd/Entropy.md similarity index 100% rename from proposals/relaxed-simd/entropy.md rename to proposals/relaxed-simd/Entropy.md From c4c9ddaf0d8b086f64531ed80604b44e6f19efec Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Fri, 3 Mar 2023 21:37:04 +0000 Subject: [PATCH 100/117] Add prose for exec numerics and fma --- document/core/exec/numerics.rst | 175 ++++++++++++++++++++++++++++---- 1 file changed, 153 insertions(+), 22 deletions(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 9804630af..ba9171a97 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -1989,21 +1989,70 @@ each environment globally chooses a fixed projection for each operator. itself can still be non-deterministic or partial. -.. _op-relaxed_madd: .. _op-fma: +:math:`\fma(z_1, z_2, z_3)` +........................... + +The function :math:`\fma` is the same as *fusedMultiplyAdd* defined by |IEEE754|_ (Section 5.4.1). +It computes :math:`(z_1 \cdot z_2) + z_3` as if with unbounded range and precision, rounding only once for the final result. + +* If either :math:`z_1` or :math:`z_2` or :math:`z_3` is a NaN, return an element of :math:`\nans_N{z_1, z_2, z_3}`. + +* Else if either :math:`z_1` or :math:`z_2` is a zero and the other is an infinity, then return an element of :math:`\nans_N\{\}`. + +* Else if both :math:`z_1` or :math:`z_2` are infinities of equal sign, and :math:`z_3` is a negative infinity, then return an element of :math:`\nans_N\{\}`. + +* Else if both :math:`z_1` or :math:`z_2` are infinities of opposite sign, and :math:`z_3` is a positive infinity, then return an element of :math:`\nans_N\{\}`. + +* Else if either :math:`z_1` or :math:`z_2` is an infinity and the other is a value of the same sign, and :math:`z_3` is a negative infinity, then return an element of :math:`\nans_N\{\}`. + +* Else if either :math:`z_1` or :math:`z_2` is an infinity and the other is a value of the opposite sign, and :math:`z_3` is a positive infinity, then return an element of :math:`\nans_N\{\}`. + +* Else if both :math:`z_1` and :math:`z_2` are zeroes of the same sign and :math:`z_3` is a zero, then return positive zero. + +* Else if both :math:`z_1` and :math:`z_2` are zeroes of the opposite sign and :math:`z_3` is a positive zero, then return positive zero. + +* Else if both :math:`z_1` and :math:`z_2` are zeroes of the opposite sign and :math:`z_3` is a negative zero, then return negative zero. + +* Else return the result of multiplying :math:`z_1` and :math:`z_2`, adding :math:`z_3` to the intermediate, and the final result ref:`rounded ` to the nearest representable value. + +.. math:: + \begin{array}{@{}llcll} + & \fma_N(\pm \NAN(n), z_2, z_3) &=& \nans_N\{\pm \NAN(n), z_2, z_3\} \\ + & \fma_N(z_1, \pm \NAN(n), z_3) &=& \nans_N\{\pm \NAN(n), z_1, z_3\} \\ + & \fma_N(z_1, z_2, \pm \NAN(n)) &=& \nans_N\{\pm \NAN(n), z_1, z_2\} \\ + & \fma_N(\pm \infty, \pm 0, z_3) &=& \nans_N\{\} \\ + & \fma_N(\pm \infty, \mp 0, z_3) &=& \nans_N\{\} \\ + & \fma_N(\pm \infty, \pm \infty, - \infty) &=& \nans_N\{\} \\ + & \fma_N(\pm \infty, \mp \infty, + \infty) &=& \nans_N\{\} \\ + & \fma_N(\pm q_1, \pm \infty, - \infty) &=& \nans_N\{\} \\ + & \fma_N(\pm q_1, \mp \infty, + \infty) &=& \nans_N\{\} \\ + & \fma_N(\pm \infty, \pm q_1, - \infty) &=& \nans_N\{\} \\ + & \fma_N(\mp \infty, \pm q_1, + \infty) &=& \nans_N\{\} \\ + & \fma_N(\pm 0, \pm 0, \mp 0) &=& + 0 \\ + & \fma_N(\pm 0, \pm 0, \pm 0) &=& + 0 \\ + & \fma_N(\pm 0, \mp 0, + 0) &=& + 0 \\ + & \fma_N(\pm 0, \mp 0, - 0) &=& - 0 \\ + & \fma_N(z_1, z_2, z_3) &=& \ieee_N(z_1 \cdot z_2 + z_3) \\ + \end{array} + + +.. _op-relaxed_madd: + :math:`\relaxedmadd_N(z_1, z_2, z_3)` ..................................... -Relaxed multiply-add allows for fused or unfused results. The function :math:`\fma` -is the same as *fusedMultiplyAdd* defined by |IEEE754|_ (Section 5.4.1). +Relaxed multiply-add allows for fused or unfused results. + +* :math:`\EXPROFDET` Return either :math:`\fadd_N(\fmul_N(z_1, z_2), z_3)` or :math:`\fma_N(z_1, z_2, z_3)` + +* Return :math:`\fma_N(z_1, z_2, z_3)` .. math:: \begin{array}{@{}llcll} \EXPROFDET & \relaxedmadd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), \fma_N(z_1, z_2, z_3) ] \\ & \relaxedmadd_N(z_1, z_2, z_3) &=& \fma_N(z_1, z_2, z_3) \\ - \\ - & \fma_N(z_1, z_2, z_3) &=& \ieee_N(z_1 \cdot z_2 + z_3) \\ \end{array} @@ -2014,20 +2063,28 @@ is the same as *fusedMultiplyAdd* defined by |IEEE754|_ (Section 5.4.1). Relaxed negative multiply-add allows for fused or unfused results. +* Return :math:`\relaxedmadd(-z_1, z_2, z_3)`. + .. math:: \begin{array}{@{}llcll} & \relaxednmadd_N(z_1, z_2, z_3) &=& \relaxedmadd_N(-z_1, z_2, z_3) \\ \end{array} -.. _op-relaxed_swizzle: +.. _op-relaxed_swizzle_lane: -:math:`\relaxedswizzle(a^n, s^n)` -................................. +:math:`\relaxedswizzlelane(i^n, j)` +................................... -Relaxed swizzle lane is deterministic -if the signed interpretation of the index is less than 16 (including negative values). -:math:`j` is a 8-bit int. +* Let :math:`k` be the :ref:`signed interpretation ` of :math:`j`. + +* If :math:`j` is less than :math:`16`, return :math:`i[j]`. + +* If :math:`k` is less than :math:`0`, return :math:`0`. + +* :math:`\EXPROFDET` Otherwise, return either :math:`0` or :math:`i[j \mod n]`. + +* Otherwise, return :math:`0`. .. math:: \begin{array}{@{}llcll} @@ -2035,7 +2092,21 @@ if the signed interpretation of the index is less than 16 (including negative va & \relaxedswizzlelane(i^n, j) &=& 0 & (\iff \signed_8(j) < 0) \\ \EXPROFDET & \relaxedswizzlelane(i^n, j) &=& [ 0, i[j \mod n] ] & (\otherwise) \\ & \relaxedswizzlelane(i^n, j) &=& 0 & (\otherwise) \\ - \\ + \end{array} + + +.. _op-relaxed_swizzle: + +:math:`\relaxedswizzle(a^n, s^n)` +................................. + +Relaxed swizzle lane is deterministic if the signed interpretation of the index is less than 16 (including negative values). +:math:`j` is a 8-bit int. + +* Return :math:`\X{rsl}_0 \dots \X{rsl}_{n-1}` where :math:`\X{rsl}_i = \relaxedswizzlelane(a^n, s^n[i])` + +.. math:: + \begin{array}{@{}llcll} & \relaxedswizzle(a^n, s^n) &=& \X{rsl}_0 \dots \X{rsl}_{n-1} \\ & \qquad \where \X{rsl}_i &=& \relaxedswizzlelane(a^n, s^n[i]) \end{array} @@ -2050,12 +2121,20 @@ if the signed interpretation of the index is less than 16 (including negative va Relaxed unsigned truncation converts floating point numbers to integers. The result for NaN's and out-of-range values is host-dependent. +* :math:`\EXPROFDET` If :math:`z` is a NaN, return either :math:`0` or :math:`2^N-1`. + +* :math:`\EXPROFDET` Else if :math:`\trunc(z)` is positive and less than :math:`2^N`, return :math:`\truncu_{M,N}(z)`. + +* :math:`\EXPROFDET` Else return either :math:`\truncsatu_{M,N}(z)` or :math:`2^N-1`. + +* Return :math:`\truncsatu_{M,N}(z)`. + .. math:: \begin{array}{@{}llcll} \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm \NAN(n)) &=& [ 0, 2^{N}-1 ] \\ \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm q) &=& \truncu_{M,N}(\pm q) & (\iff -1 < \trunc(\pm q) < 2^N) \\ \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm p) &=& [ \truncsatu_{M,N}(\pm p), 2^{N}-1 ] & (\otherwise) \\ - & \relaxedtrunc^u_{M,N}(\pm p) &=& \truncsatu_{M,N}(\pm p) & (\otherwise) \\ + & \relaxedtrunc^u_{M,N}(z) &=& \truncsatu_{M,N}(z) & \\ \end{array} @@ -2067,24 +2146,37 @@ The result for NaN's and out-of-range values is host-dependent. Relaxed signed truncation converts floating point numbers to integers. The result for NaN's and out-of-range values is host-dependent. +* :math:`\EXPROFDET` If :math:`z` is a NaN, return either :math:`0` or :math:`-2^{N-1}`. + +* :math:`\EXPROFDET` Else if :math:`\trunc(z)` is larger than :math:`-2^{N-1}-1` and less than :math:`2^{N-1}`, return :math:`\truncs_{M,N}(z)`. + +* :math:`\EXPROFDET` Else return either :math:`\truncsats_{M,N}(z)` or :math:`-2^{N-1}`. + +* Return :math:`\truncsats_{M,N}(z)`. + .. math:: \begin{array}{@{}llcll} \EXPROFDET & \relaxedtrunc^s_{M,N}(\pm \NAN(n)) &=& [ 0, -2^{N-1} ] \\ \EXPROFDET & \relaxedtrunc^s_{M,N}(\pm q) &=& \truncs_{M,N}(\pm q) & (\iff -2^{N-1} - 1 < \trunc(\pm q) < 2^{N-1}) \\ \EXPROFDET & \relaxedtrunc^s_{M,N}(\pm p) &=& [ \truncsats_{M,N}(\pm p), -2^{N-1} ] & (\otherwise) \\ - & \relaxedtrunc^s_{M,N}(\pm p) &=& \truncsats_{M,N}(\pm p) & (\otherwise) \\ + & \relaxedtrunc^s_{M,N}(z) &=& \truncsats_{M,N}(z) & \\ \end{array} -.. _op-relaxed_lane_select: .. _op-relaxed_lane: -:math:`\relaxedlaneselect_B(a^n, b^n, c^n)` -........................................... +:math:`\relaxedlane_N(i_1, i_2, i_3)` +..................................... -Relaxed lane selection is deterministic when all bits are set or unset in the -mask. Otherwise depending on the host, either only the top bit is examined, or -all bits are examined (i.e. it becomes a bit select). +* If :math:`i_3` is :math:`2^N - 1`, return :math:`i_1`. + +* Else if :math:`i_3` is :math:`0`, return :math:`i_2`. + +* :math:`\EXPROFDET` Else if :math:`\signed_n(i_3)` is less than :math:`0`, return either :math:`\ibitselect_n(i_1, i_2, i_3)` or :math:`i_1`. + +* :math:`\EXPROFDET` Otherwise return either :math:`\ibitselect_n(i_1, i_2, i_3)` or :math:`i_2`. + +* Otherwise return :math:`\ibitselect_n(i_1, i_2, i_3)`. .. math:: \begin{array}{@{}llcll} @@ -2093,7 +2185,22 @@ all bits are examined (i.e. it becomes a bit select). \EXPROFDET & \relaxedlane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_1 ] & (\iff \signed_N(i_3) < 0) \\ \EXPROFDET & \relaxedlane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_2 ] & (\otherwise) \\ & \relaxedlane_N(i_1, i_2, i_3) &=& \ibitselect_N(i_1, i_2, i_3) & (\otherwise) \\ - \\ + \end{array} + + +.. _op-relaxed_lane_select: + +:math:`\relaxedlaneselect_B(a^n, b^n, c^n)` +........................................... + +Relaxed lane selection is deterministic when all bits are set or unset in the +mask. Otherwise depending on the host, either only the top bit is examined, or +all bits are examined (i.e. it becomes a bit select). + +* Return :math:`rll_0 \dots rll_{n-1}` where :math:`rll_i = \relaxedlane_B(a^n[i], b^n[i], c^n[i])`. + +.. math:: + \begin{array}{@{}llcll} & \relaxedlaneselect_B(a^n, b^n, c^n) &=& rll_0 \dots rll_{n-1} \\ & \qquad \where rll_i &=& \relaxedlane_B(a^n[i], b^n[i], c^n[i]) \\ \end{array} @@ -2107,6 +2214,14 @@ all bits are examined (i.e. it becomes a bit select). Relaxed minimum differs from regular minimum when inputs are NaN's or zeroes with different signs. It allows for implementation to return the first or second input when either input is a NaN. +* :math:`\EXPROFDET` If :math:`z_1` is a NaN, return either an element of :math:`\nans_N\{z_1, z_2\}`, :math:`\NAN(n)`, or :math:`z_2` + +* :math:`\EXPROFDET` If :math:`z_2` is a NaN, return either an element of :math:`\nans_N\{z_1, z_2\}`, :math:`\NAN(n)`, or :math:`z_1` + +* :math:`\EXPROFDET` If both :math:`z_1` and :math:`z_2` are zeroes of opposite sign, return either :math:`+ 0` or :math:`- 0`. + +* Return :math:`\fmin_N(z_1, z_2)`. + .. math:: \begin{array}{@{}llcll} \EXPROFDET & \relaxedmin_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ @@ -2124,6 +2239,14 @@ It allows for implementation to return the first or second input when either inp Relaxed maximum differs from regular maximum when inputs are NaN's or zeroes with different signs. It allows for implementations to return the first or second input when either input is a NaN. +* :math:`\EXPROFDET` If :math:`z_1` is a NaN, return either an element of :math:`\nans_N\{z_1, z_2\}`, :math:`\NAN(n)`, or :math:`z_2` + +* :math:`\EXPROFDET` If :math:`z_2` is a NaN, return either an element of :math:`\nans_N\{z_1, z_2\}`, :math:`\NAN(n)`, or :math:`z_1` + +* :math:`\EXPROFDET` If both :math:`z_1` and :math:`z_2` are zeroes of opposite sign, return either :math:`+ 0` or :math:`- 0`. + +* Return :math:`\fmax_N(z_1, z_2)`. + .. math:: \begin{array}{@{}llcll} \EXPROFDET & \relaxedmax_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ @@ -2141,9 +2264,13 @@ It allows for implementations to return the first or second input when either in Relaxed Q15 multiply differs from regular Q15 multiply when the multiplication results overflows (i.e. when both inputs are -32768). It allows for implementations to either wrap around or saturate. +* :math:`\EXPROFDET` If both :math:`z_1` and :math:`z_2` are :math:`-2^{N-1}`, return either :math:`2^{N-1} - 1` or :math:`-2^{N-1}`. + +* Return :math:`\iq15mulrsats(i_1, i_2)` + .. math:: \begin{array}{@{}llcll} - \EXPROFDET & \relaxedq15mulrs_N(i_1, i_2) &=& [ \sats_N(i), i \mod 2^N ] & (\iff i = \ishrs_N(i_1 \cdot i_2 + 2^{14}, 15)) \\ + \EXPROFDET & \relaxedq15mulrs_N(-2^{N-1}, -2^{N-1}) &=& [ 2^{N-1}-1, -2^{N-1}] & \\ & \relaxedq15mulrs_N(i_1, i_2) &=& \iq15mulrsats(i_1, i_2) \end{array} @@ -2155,6 +2282,10 @@ It allows for implementations to either wrap around or saturate. Relaxed integer dot product differs from regular integer dot product when the elements of the input have their most significant bit set. +* :math:`\EXPROFDET` Return either :math:`\imul_N(\signed_M(i_1), i_2), \imul_N(\signed_M(i_1), \signed_M(i_2))`. + +* Return :math:`\imul_N(\extends_{M,N}(i_1), \extends_{M,N}(i_2))`. + .. math:: \begin{array}{@{}llcll} \EXPROFDET & \relaxeddotmul_{M,N}(i_1, i_2) &=& [ \imul_N(\signed_M(i_1), i_2), \imul_N(\signed_M(i_1), \signed_M(i_2)) ] \\ From 70f8687ad1791ab925044c45f47aef5e3ea74fc9 Mon Sep 17 00:00:00 2001 From: Zhi An Ng Date: Mon, 5 Jun 2023 13:33:55 -0700 Subject: [PATCH 101/117] Add more allowed return values for relaxed trunc unsigned --- document/core/exec/numerics.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index ba9171a97..b16fdad59 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2121,19 +2121,19 @@ Relaxed swizzle lane is deterministic if the signed interpretation of the index Relaxed unsigned truncation converts floating point numbers to integers. The result for NaN's and out-of-range values is host-dependent. -* :math:`\EXPROFDET` If :math:`z` is a NaN, return either :math:`0` or :math:`2^N-1`. +* :math:`\EXPROFDET` If :math:`z` is a NaN, return either :math:`0` or :math:`2^N-1` or :math:`2^N-2` or :math:`2^(N-1)`. * :math:`\EXPROFDET` Else if :math:`\trunc(z)` is positive and less than :math:`2^N`, return :math:`\truncu_{M,N}(z)`. -* :math:`\EXPROFDET` Else return either :math:`\truncsatu_{M,N}(z)` or :math:`2^N-1`. +* :math:`\EXPROFDET` Else return either :math:`\truncsatu_{M,N}(z)` or :math:`2^N-1` or :math:`2^N-2` or :math:`2^(N-1)`. * Return :math:`\truncsatu_{M,N}(z)`. .. math:: \begin{array}{@{}llcll} - \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm \NAN(n)) &=& [ 0, 2^{N}-1 ] \\ + \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm \NAN(n)) &=& [ 0, 2^{N}-1, 2^{N}-2, 2^{N-1}] \\ \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm q) &=& \truncu_{M,N}(\pm q) & (\iff -1 < \trunc(\pm q) < 2^N) \\ - \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm p) &=& [ \truncsatu_{M,N}(\pm p), 2^{N}-1 ] & (\otherwise) \\ + \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm p) &=& [ \truncsatu_{M,N}(\pm p), 2^{N}-1, 2^{N}-2, 2^{N-1}] & (\otherwise) \\ & \relaxedtrunc^u_{M,N}(z) &=& \truncsatu_{M,N}(z) & \\ \end{array} From d879d67b2b779d87490b75cc9880479c1ad62c8d Mon Sep 17 00:00:00 2001 From: Zhi An Ng Date: Fri, 30 Jun 2023 13:45:55 +0800 Subject: [PATCH 102/117] Document that "either" comes from threads proposal --- test/core/relaxed-simd/i16x8_relaxed_q15mulr_s.wast | 2 ++ test/core/relaxed-simd/i32x4_relaxed_trunc.wast | 1 + test/core/relaxed-simd/i8x16_relaxed_swizzle.wast | 1 + test/core/relaxed-simd/relaxed_dot_product.wast | 1 + test/core/relaxed-simd/relaxed_laneselect.wast | 1 + test/core/relaxed-simd/relaxed_madd_nmadd.wast | 1 + test/core/relaxed-simd/relaxed_min_max.wast | 1 + 7 files changed, 8 insertions(+) diff --git a/test/core/relaxed-simd/i16x8_relaxed_q15mulr_s.wast b/test/core/relaxed-simd/i16x8_relaxed_q15mulr_s.wast index 265d99160..00f901cbc 100644 --- a/test/core/relaxed-simd/i16x8_relaxed_q15mulr_s.wast +++ b/test/core/relaxed-simd/i16x8_relaxed_q15mulr_s.wast @@ -1,4 +1,6 @@ ;; Tests for i16x8.relaxed_q15mulr_s. +;; `either` comes from https://github.com/WebAssembly/threads. + (module (func (export "i16x8.relaxed_q15mulr_s") (param v128 v128) (result v128) (i16x8.relaxed_q15mulr_s (local.get 0) (local.get 1))) diff --git a/test/core/relaxed-simd/i32x4_relaxed_trunc.wast b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast index 889542c6a..cca3ecb95 100644 --- a/test/core/relaxed-simd/i32x4_relaxed_trunc.wast +++ b/test/core/relaxed-simd/i32x4_relaxed_trunc.wast @@ -1,4 +1,5 @@ ;; Tests for i32x4.relaxed_trunc_f32x4_s, i32x4.relaxed_trunc_f32x4_u, i32x4.relaxed_trunc_f64x2_s_zero, and i32x4.relaxed_trunc_f64x2_u_zero. +;; `either` comes from https://github.com/WebAssembly/threads. (module (func (export "i32x4.relaxed_trunc_f32x4_s") (param v128) (result v128) (i32x4.relaxed_trunc_f32x4_s (local.get 0))) diff --git a/test/core/relaxed-simd/i8x16_relaxed_swizzle.wast b/test/core/relaxed-simd/i8x16_relaxed_swizzle.wast index 1b20668d3..f1bcb4552 100644 --- a/test/core/relaxed-simd/i8x16_relaxed_swizzle.wast +++ b/test/core/relaxed-simd/i8x16_relaxed_swizzle.wast @@ -1,4 +1,5 @@ ;; Tests for relaxed i8x16 swizzle. +;; `either` comes from https://github.com/WebAssembly/threads. (module (func (export "i8x16.relaxed_swizzle") (param v128 v128) (result v128) (i8x16.relaxed_swizzle (local.get 0) (local.get 1))) diff --git a/test/core/relaxed-simd/relaxed_dot_product.wast b/test/core/relaxed-simd/relaxed_dot_product.wast index 41dee0afc..48714b87b 100644 --- a/test/core/relaxed-simd/relaxed_dot_product.wast +++ b/test/core/relaxed-simd/relaxed_dot_product.wast @@ -1,4 +1,5 @@ ;; Tests for relaxed dot products. +;; `either` comes from https://github.com/WebAssembly/threads. (module (func (export "i16x8.relaxed_dot_i8x16_i7x16_s") (param v128 v128) (result v128) (i16x8.relaxed_dot_i8x16_i7x16_s (local.get 0) (local.get 1))) diff --git a/test/core/relaxed-simd/relaxed_laneselect.wast b/test/core/relaxed-simd/relaxed_laneselect.wast index 4ea6eb818..c43acb5e7 100644 --- a/test/core/relaxed-simd/relaxed_laneselect.wast +++ b/test/core/relaxed-simd/relaxed_laneselect.wast @@ -1,4 +1,5 @@ ;; Tests for i8x16.relaxed_laneselect, i16x8.relaxed_laneselect, i32x4.relaxed_laneselect, and i64x2.relaxed_laneselect. +;; `either` comes from https://github.com/WebAssembly/threads. (module (func (export "i8x16.relaxed_laneselect") (param v128 v128 v128) (result v128) (i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))) diff --git a/test/core/relaxed-simd/relaxed_madd_nmadd.wast b/test/core/relaxed-simd/relaxed_madd_nmadd.wast index d3f76f810..40ce0ed3e 100644 --- a/test/core/relaxed-simd/relaxed_madd_nmadd.wast +++ b/test/core/relaxed-simd/relaxed_madd_nmadd.wast @@ -1,4 +1,5 @@ ;; Tests for f32x4.relaxed_madd, f32x4.relaxed_nmadd, f64x2.relaxed_madd, and f64x2.relaxed_nmadd. +;; `either` comes from https://github.com/WebAssembly/threads. (module (func (export "f32x4.relaxed_madd") (param v128 v128 v128) (result v128) (f32x4.relaxed_madd (local.get 0) (local.get 1) (local.get 2))) diff --git a/test/core/relaxed-simd/relaxed_min_max.wast b/test/core/relaxed-simd/relaxed_min_max.wast index d8a04ba4d..ac3ebb07c 100644 --- a/test/core/relaxed-simd/relaxed_min_max.wast +++ b/test/core/relaxed-simd/relaxed_min_max.wast @@ -1,4 +1,5 @@ ;; Tests for f32x4.min, f32x4.max, f64x2.min, and f64x2.max. +;; `either` comes from https://github.com/WebAssembly/threads. (module (func (export "f32x4.relaxed_min") (param v128 v128) (result v128) (f32x4.relaxed_min (local.get 0) (local.get 1))) From f7e861c4ed1ca862edfbcd4c1ab4b85112b63c0d Mon Sep 17 00:00:00 2001 From: Zhi An Ng Date: Mon, 5 Jun 2023 17:01:08 -0700 Subject: [PATCH 103/117] Fix relaxed laneselect to allow looking at top bit of byte This allows using pblendvb for i16x8 lane select. See #125. --- document/core/exec/numerics.rst | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index b16fdad59..d48f480a7 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2168,25 +2168,33 @@ The result for NaN's and out-of-range values is host-dependent. :math:`\relaxedlane_N(i_1, i_2, i_3)` ..................................... -* If :math:`i_3` is :math:`2^N - 1`, return :math:`i_1`. +* :math:`\EXPROFDET` If :math:`i_3` is :math:`2^N - 1`, return :math:`i_1`. -* Else if :math:`i_3` is :math:`0`, return :math:`i_2`. +* :math:`\EXPROFDET` Else if :math:`i_3` is :math:`0`, return :math:`i_2`. -* :math:`\EXPROFDET` Else if :math:`\signed_n(i_3)` is less than :math:`0`, return either :math:`\ibitselect_n(i_1, i_2, i_3)` or :math:`i_1`. +* :math:`\EXPROFDET` Otherwise return either :math:`\ibitselect_n(i_1, i_2, i_3)` or :math:`i_1` or :math:`i_2` or :math:`\F{top\_bit\_byteselect_N}(i_1, i_2, i_3)`. -* :math:`\EXPROFDET` Otherwise return either :math:`\ibitselect_n(i_1, i_2, i_3)` or :math:`i_2`. - -* Otherwise return :math:`\ibitselect_n(i_1, i_2, i_3)`. +* Return :math:`\ibitselect_n(i_1, i_2, i_3)`. .. math:: \begin{array}{@{}llcll} - & \relaxedlane_N(i_1, i_2, 2^N-1) &=& i_1 \\ - & \relaxedlane_N(i_1, i_2, 0) &=& i_2 \\ - \EXPROFDET & \relaxedlane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_1 ] & (\iff \signed_N(i_3) < 0) \\ - \EXPROFDET & \relaxedlane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_2 ] & (\otherwise) \\ + \EXPROFDET & \relaxedlane_N(i_1, i_2, 2^N-1) &=& i_1 \\ + \EXPROFDET & \relaxedlane_N(i_1, i_2, 0) &=& i_2 \\ + \EXPROFDET & \relaxedlane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_2, i_3, \\ + & & & \qquad \F{top\_bit\_byteselect}(i_1, i_2, i_3)] & (\otherwise) \\ & \relaxedlane_N(i_1, i_2, i_3) &=& \ibitselect_N(i_1, i_2, i_3) & (\otherwise) \\ \end{array} +where: + +.. math:: + \begin{array}{@{}llcll} + & \F{top\_bit\_byteselect}_N(i_1, i_2, i_3) &=& tbb_0 ... tbb_{N/8 - 1} \\ + & \F{tbb_j} &=& \F{byteselect}(\bytes_8(i_1)[j], \bytes_8(i_2)[j], \bytes_8(i_3)[j]) \\ + & \F{byteselect}(a, b, 0~c^7) &=& a \\ + & \F{byteselect}(a, b, c) &=& b \\ + \end{array} + .. _op-relaxed_lane_select: @@ -2195,7 +2203,8 @@ The result for NaN's and out-of-range values is host-dependent. Relaxed lane selection is deterministic when all bits are set or unset in the mask. Otherwise depending on the host, either only the top bit is examined, or -all bits are examined (i.e. it becomes a bit select). +all bits are examined (i.e. it becomes a bit select), or the top bit of each +byte in the lane is examined. * Return :math:`rll_0 \dots rll_{n-1}` where :math:`rll_i = \relaxedlane_B(a^n[i], b^n[i], c^n[i])`. From cd9c447623cc80f708023426b3fda85194602e11 Mon Sep 17 00:00:00 2001 From: Zhi An Ng Date: Mon, 26 Jun 2023 02:52:39 +0000 Subject: [PATCH 104/117] Add special test case for i16x8.relaxed_laneselect --- test/core/relaxed-simd/relaxed_laneselect.wast | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/test/core/relaxed-simd/relaxed_laneselect.wast b/test/core/relaxed-simd/relaxed_laneselect.wast index c43acb5e7..10913816b 100644 --- a/test/core/relaxed-simd/relaxed_laneselect.wast +++ b/test/core/relaxed-simd/relaxed_laneselect.wast @@ -39,6 +39,16 @@ (either (v128.const i16x8 0 9 0x1278 0x5634 12 13 14 15) (v128.const i16x8 0 9 0x1234 0x5678 12 13 14 15))) +;; special case for i16x8 to allow pblendvb +(assert_return (invoke "i16x8.relaxed_laneselect" + (v128.const i16x8 0 1 0x1234 0x1234 4 5 6 7) + (v128.const i16x8 8 9 0x5678 0x5678 12 13 14 15) + (v128.const i16x8 0xffff 0 0xff00 0x0080 0 0 0 0)) ;; 0x0080 is the special case + (either (v128.const i16x8 0 9 0x1278 0x5678 12 13 14 15) ;; bitselect + (v128.const i16x8 0 9 0x1234 0x5678 12 13 14 15) ;; top bit of i16 lane examined + (v128.const i16x8 0 9 0x1278 0x5634 12 13 14 15) ;; top bit of each byte + )) + (assert_return (invoke "i32x4.relaxed_laneselect" (v128.const i32x4 0 1 0x12341234 0x12341234) (v128.const i32x4 4 5 0x56785678 0x56785678) From 22257c57ba60f59d2b81a267635c5eba28719c0e Mon Sep 17 00:00:00 2001 From: Thibaud Michaud Date: Tue, 3 Oct 2023 10:24:55 +0200 Subject: [PATCH 105/117] Fix relaxed trunc pseudocode in Overview --- proposals/relaxed-simd/Overview.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/proposals/relaxed-simd/Overview.md b/proposals/relaxed-simd/Overview.md index 1c627e7b8..8fe79bfec 100644 --- a/proposals/relaxed-simd/Overview.md +++ b/proposals/relaxed-simd/Overview.md @@ -115,6 +115,7 @@ def relaxed_i32x4_trunc_f32x4_s(a : f32x4) -> i32x4: for i in range(4): if isnan(a[i]): result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MIN) + continue r = truncate(a[i]) if r < INT32_MIN: result[i] = INT32_MIN @@ -128,6 +129,7 @@ def relaxed_i32x4_trunc_f32x4_u(a : f32x4) -> i32x4: for i in range(4): if isnan(a[i]): result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, UINT32_MAX) + continue r = truncate(a[i]) if r < UINT32_MIN: result[i] = IMPLEMENTATION_DEFINED_ONE_OF(UINT32_MIN, UINT32_MAX) @@ -141,6 +143,7 @@ def relaxed_i32x4_trunc_f64x2_zero_s(a : f64x2) -> i32x4: for i in range(2): if isnan(a[i]): result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, INT32_MIN) + continue r = truncate(a[i]) if r < INT32_MIN: result[i] = INT32_MIN @@ -154,6 +157,7 @@ def relaxed_i32x4_trunc_f64x2_zero_u(a : f64x2) -> i32x4: for i in range(2): if isnan(a[i]): result[i] = IMPLEMENTATION_DEFINED_ONE_OF(0, UINT32_MAX) + continue r = truncate(a[i]) if r < UINT32_MIN: result[i] = IMPLEMENTATION_DEFINED_ONE_OF(UINT32_MIN, UINT32_MAX) From 95dc80e422eea3720f0c12543f99899b63907c8e Mon Sep 17 00:00:00 2001 From: Deepti Gandluri Date: Fri, 10 May 2024 00:26:54 -0700 Subject: [PATCH 106/117] Update ImplementationStatus.md --- proposals/relaxed-simd/ImplementationStatus.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/proposals/relaxed-simd/ImplementationStatus.md b/proposals/relaxed-simd/ImplementationStatus.md index e621fcf19..9a1273103 100644 --- a/proposals/relaxed-simd/ImplementationStatus.md +++ b/proposals/relaxed-simd/ImplementationStatus.md @@ -19,9 +19,9 @@ | `f32x4.relaxed_max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | | `f64x2.relaxed_min` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | | `f64x2.relaxed_max` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | -| `i16x8.relaxed_q15mulr_s` | -mrelaxed-simd | | | -| `i16x8.relaxed_dot_i8x16_i7x16_s` | -mrelaxed-simd | | | -| `i32x4.relaxed_dot_i8x16_i7x16_add_s` | -mrelaxed-simd | | | +| `i16x8.relaxed_q15mulr_s` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i16x8.relaxed_dot_i8x16_i7x16_s` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | +| `i32x4.relaxed_dot_i8x16_i7x16_add_s` | -mrelaxed-simd | :heavy_check_mark: | :heavy_check_mark: | [1] Tip of tree LLVM as of 2021-10-28 From e9c9a9b72dd05cee7a5df881d90b9b40b6ba7090 Mon Sep 17 00:00:00 2001 From: Nick Fitzgerald Date: Thu, 18 Jul 2024 10:58:09 -0700 Subject: [PATCH 107/117] Add a smoke test for consistent nondeterminism Fixes https://github.com/WebAssembly/relaxed-simd/issues/155 --- .../core/relaxed-simd/relaxed_madd_nmadd.wast | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/test/core/relaxed-simd/relaxed_madd_nmadd.wast b/test/core/relaxed-simd/relaxed_madd_nmadd.wast index 40ce0ed3e..187b71d5a 100644 --- a/test/core/relaxed-simd/relaxed_madd_nmadd.wast +++ b/test/core/relaxed-simd/relaxed_madd_nmadd.wast @@ -189,3 +189,36 @@ (v128.const f64x2 -0x1.000002p+0 -0x1.000002p+0) (v128.const f64x2 -0x1.00000204p+0 -0x1.00000204p+0)) (v128.const i64x2 -1 -1)) + +;; Test that the non-deterministic choice of fusing and then rounding or +;; rounding multiple times in `relaxed_madd` is consistent throughout a +;; program's execution. +;; +;; This property is impossible to test exhaustively, so this is just a simple +;; smoke test for when the operands to a `relaxed_madd` are known statically +;; versus when they are dynamically supplied. This should, at least, catch +;; illegal constant-folding and -propagation by the compiler that leads to +;; inconsistent rounding behavior at compile time versus at run time. +;; +;; FLT_MAX == 0x1.fffffep+127 +;; FLT_MAX * 2 - FLT_MAX == +;; FLT_MAX (if fma) +;; 0 (if no fma) +;; from https://www.vinc17.net/software/fma-tests.c +(module + (func (export "test-consistent-nondeterminism") (param v128 v128 v128) (result v128) + (f32x4.eq + (f32x4.relaxed_madd (v128.const f32x4 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 ) + (v128.const f32x4 2.0 2.0 2.0 2.0) + (v128.const f32x4 -0x1.fffffep+127 -0x1.fffffep+127 -0x1.fffffep+127 -0x1.fffffep+127)) + (f32x4.relaxed_madd (local.get 0) + (local.get 1) + (local.get 2)) + ) + ) +) +(assert_return (invoke "test-consistent-nondeterminism" + (v128.const f32x4 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 0x1.fffffep+127 ) + (v128.const f32x4 2.0 2.0 2.0 2.0) + (v128.const f32x4 -0x1.fffffep+127 -0x1.fffffep+127 -0x1.fffffep+127 -0x1.fffffep+127)) + (v128.const i32x4 -1 -1 -1 -1)) From 9d740b06f1062e18524df6fe56ccfd92d72bede2 Mon Sep 17 00:00:00 2001 From: Andreas Rossberg Date: Wed, 4 Sep 2024 16:57:32 +0200 Subject: [PATCH 108/117] Minor edits --- .github/workflows/ci-interpreter.yml | 2 +- document/core/appendix/profiles.rst | 20 +++++++++++--------- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/.github/workflows/ci-interpreter.yml b/.github/workflows/ci-interpreter.yml index 91a5fc423..6c09ffc0f 100644 --- a/.github/workflows/ci-interpreter.yml +++ b/.github/workflows/ci-interpreter.yml @@ -27,7 +27,7 @@ jobs: - name: Setup Node.js uses: actions/setup-node@v2 with: - node-version: 19.x + node-version: 20.x - name: Build interpreter run: cd interpreter && opam exec make - name: Run tests diff --git a/document/core/appendix/profiles.rst b/document/core/appendix/profiles.rst index 8d360834d..ea32797d9 100644 --- a/document/core/appendix/profiles.rst +++ b/document/core/appendix/profiles.rst @@ -11,7 +11,7 @@ A host platform can thereby decide to support the language only under a restrict Conventions ~~~~~~~~~~~ -A profile modification is specified by decorating selected rules in the main body of this specification with a *profile annotation* that defines them as "conditional" on the choice of profile. +A profile modification is specified by decorating selected rules in the main body of this specification with a *profile annotation* that defines them as conditional on the choice of profile. For that purpose, every profile defines a *profile marker*, an alphanumeric short-hand like :math:`\profilename{ABC}`. A profile annotation of the form :math:`\exprofiles{\profile{ABC}~\profile{XYZ}}` on a rule indicates that this rule is *excluded* for either of the profiles whose marker is :math:`\profilename{ABC}` or :math:`\profilename{XYZ}`. @@ -46,7 +46,7 @@ The overall effect is that the respective construct is no longer part of the lan & &|& \UNREACHABLE \\ \end{array} - A rule may be annotated by multiple markers, which might be the case if a construct is in the intersection of multiple features. + A rule may be annotated by multiple markers, which could be the case if a construct is in the intersection of multiple features. Semantics Annotations @@ -54,22 +54,22 @@ Semantics Annotations To restrict certain behaviours in a profile, individual :ref:`validation ` or :ref:`reduction ` rules or auxiliary definitions are annotated with an associated marker. -This has the simple consequence that the respective rule is no longer applicable under the given profile. +This has the consequence that the respective rule is no longer applicable under the given profile. .. note:: For example, an "infinite" profile marked :math:`\profilename{INF}` could define that growing memory never fails: .. math:: \begin{array}{llcl@{\qquad}l} - & S; F; (\I32.\CONST~n)~\MEMORYGROW &\stepto& S'; F; (\I32.\CONST~\X{sz}) + & S; F; (\I32.\CONST~n)~\MEMORYGROW~x &\stepto& S'; F; (\I32.\CONST~\X{sz}) \\&&& \begin{array}[t]{@{}r@{~}l@{}} - (\iff & F.\AMODULE.\MIMEMS[0] = a \\ + (\iff & F.\AMODULE.\MIMEMS[x] = a \\ \wedge & \X{sz} = |S.\SMEMS[a].\MIDATA|/64\,\F{Ki} \\ \wedge & S' = S \with \SMEMS[a] = \growmem(S.\SMEMS[a], n)) \\[1ex] \end{array} \\[1ex] - \exprofiles{\profile{INF}} & S; F; (\I32.\CONST~n)~\MEMORYGROW &\stepto& S; F; (\I32.\CONST~\signed_{32}^{-1}(-1)) + \exprofiles{\profile{INF}} & S; F; (\I32.\CONST~n)~\MEMORYGROW~x &\stepto& S; F; (\I32.\CONST~\signed_{32}^{-1}(-1)) \end{array} @@ -80,15 +80,15 @@ All profiles are defined such that the following properties are preserved: * All profiles represent syntactic and semantic subsets of the :ref:`full profile `, i.e., they do not *add* syntax or *alter* behaviour. -* All profiles are mutually compatible, i.e., no two profiles subset semantic behaviour in inconsistent ways, and any intersection of profiles preserves the properties described here. +* All profiles are mutually compatible, i.e., no two profiles subset semantic behaviour in inconsistent or ambiguous ways, and any intersection of profiles preserves the properties described here. -* Profiles that restrict execution do not violate :ref:`soundness `, i.e., all :ref:`configurations ` valid under that profile still have well-defined execution behaviour. +* Profiles do not violate :ref:`soundness `, i.e., all :ref:`configurations ` valid under that profile still have well-defined execution behaviour. .. note:: Tools are generally expected to handle and produce code for the full profile by default. In particular, producers should not generate code that *depends* on specific profiles. Instead, all code should preserve correctness when executed under the full profile. - Moreover, profiles should be considered static and fixed for a given platform or ecosystem. Runtime conditioning on the "current" profile should especially be avoided. + Moreover, profiles should be considered static and fixed for a given platform or ecosystem. Runtime conditioning on the "current" profile is not intended and should be avoided. @@ -123,6 +123,8 @@ It defines a sub-language that does not exhibit any incidental non-deterministic * All :ref:`NaN ` values :ref:`generated ` by :ref:`floating-point instructions ` are canonical and positive. +* All :ref:`relaxed vector instructions ` have a fixed behaviour that does not depend on the implementation. + Even under this profile, the |MEMORYGROW| and |TABLEGROW| instructions technically remain :ref:`non-deterministic `, in order to be able to indicate resource exhaustion. .. note:: From acb599c4a01d320e39908213c8caa68a2aa3481e Mon Sep 17 00:00:00 2001 From: Andreas Rossberg Date: Wed, 4 Sep 2024 16:58:35 +0200 Subject: [PATCH 109/117] Refactor relaxed ops spec --- document/core/appendix/index-instructions.py | 32 +- document/core/exec/instructions.rst | 30 +- document/core/exec/numerics.rst | 429 +++++++++---------- document/core/util/macros.def | 23 +- document/core/valid/instructions.rst | 2 +- 5 files changed, 258 insertions(+), 258 deletions(-) diff --git a/document/core/appendix/index-instructions.py b/document/core/appendix/index-instructions.py index 882049d8a..c39fc4a90 100755 --- a/document/core/appendix/index-instructions.py +++ b/document/core/appendix/index-instructions.py @@ -633,26 +633,26 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\I32X4.\VTRUNC\K{\_sat\_f64x2\_u\_zero}', r'\hex{FD}~~\hex{FD}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-trunc_sat_u'), Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_s}', r'\hex{FD}~~\hex{FE}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_s'), Instruction(r'\F64X2.\VCONVERT\K{\_low\_i32x4\_u}', r'\hex{FD}~~\hex{FF}~~\hex{01}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-convert_u'), - Instruction(r'\I8X16.\RELAXEDSWIZZLE', r'\hex{FD}~~\hex{80}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-relaxed_swizzle', r'exec-relaxed_swizzle', r'op-relaxed_swizzle'), + Instruction(r'\I8X16.\RELAXEDSWIZZLE', r'\hex{FD}~~\hex{80}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-relaxed_swizzle', r'exec-relaxed_swizzle', r'op-irelaxed_swizzle'), Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f32x4\_s}', r'\hex{FD}~~\hex{81}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_s'), Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f32x4\_u}', r'\hex{FD}~~\hex{82}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_u'), Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f64x2\_s}', r'\hex{FD}~~\hex{83}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_s'), Instruction(r'\I32X4.\RELAXEDTRUNC\K{\_f64x2\_u}', r'\hex{FD}~~\hex{84}~~\hex{02}', r'[\V128] \to [\V128]', r'valid-vcvtop', r'exec-vcvtop', r'op-relaxed_trunc_u'), - Instruction(r'\F32X4.\RELAXEDMADD', r'\hex{FD}~~\hex{85}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-relaxed_madd'), - Instruction(r'\F32X4.\RELAXEDNMADD', r'\hex{FD}~~\hex{86}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-relaxed_nmadd'), - Instruction(r'\F64X2.\RELAXEDMADD', r'\hex{FD}~~\hex{87}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-relaxed_madd'), - Instruction(r'\F64X2.\RELAXEDNMADD', r'\hex{FD}~~\hex{88}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-relaxed_nmadd'), - Instruction(r'\I8X16.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{89}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxedlaneselect', r'exec-relaxedlaneselect', r'op-relaxed_lane_select'), - Instruction(r'\I16X8.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8A}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxedlaneselect', r'exec-relaxedlaneselect', r'op-relaxed_lane_select'), - Instruction(r'\I32X4.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8B}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxedlaneselect', r'exec-relaxedlaneselect', r'op-relaxed_lane_select'), - Instruction(r'\I64X2.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8C}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxedlaneselect', r'exec-relaxedlaneselect', r'op-relaxed_lane_select'), - Instruction(r'\F32X4.\RELAXEDMIN', r'\hex{FD}~~\hex{8D}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-relaxed_min'), - Instruction(r'\F32X4.\RELAXEDMAX', r'\hex{FD}~~\hex{8E}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-relaxed_max'), - Instruction(r'\F64X2.\RELAXEDMIN', r'\hex{FD}~~\hex{8F}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-relaxed_min'), - Instruction(r'\F64X2.\RELAXEDMAX', r'\hex{FD}~~\hex{90}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-relaxed_max'), - Instruction(r'\I16X8.\RELAXEDQ15MULRS', r'\hex{FD}~~\hex{91}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-relaxed_q15mulr_s'), - Instruction(r'\I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_s}', r'\hex{FD}~~\hex{92}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-relaxed_dot', r'exec-relaxed_dot', r'op-relaxed_dot_mul'), - Instruction(r'\I32X4.\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s}', r'\hex{FD}~~\hex{93}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_dot', r'exec-relaxed_dot', r'op-relaxed_dot_mul'), + Instruction(r'\F32X4.\RELAXEDMADD', r'\hex{FD}~~\hex{85}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frelaxed_madd'), + Instruction(r'\F32X4.\RELAXEDNMADD', r'\hex{FD}~~\hex{86}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frelaxed_nmadd'), + Instruction(r'\F64X2.\RELAXEDMADD', r'\hex{FD}~~\hex{87}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frelaxed_madd'), + Instruction(r'\F64X2.\RELAXEDNMADD', r'\hex{FD}~~\hex{88}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-vternop', r'exec-vternop', r'op-frelaxed_nmadd'), + Instruction(r'\I8X16.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{89}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_laneselect', r'exec-relaxed_laneselect', r'op-irelaxed_laneselect'), + Instruction(r'\I16X8.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8A}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_laneselect', r'exec-relaxed_laneselect', r'op-irelaxed_laneselect'), + Instruction(r'\I32X4.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8B}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_laneselect', r'exec-relaxed_laneselect', r'op-irelaxed_laneselect'), + Instruction(r'\I64X2.\RELAXEDLANESELECT', r'\hex{FD}~~\hex{8C}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_laneselect', r'exec-relaxed_laneselect', r'op-irelaxed_laneselect'), + Instruction(r'\F32X4.\RELAXEDMIN', r'\hex{FD}~~\hex{8D}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frelaxed_min'), + Instruction(r'\F32X4.\RELAXEDMAX', r'\hex{FD}~~\hex{8E}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frelaxed_max'), + Instruction(r'\F64X2.\RELAXEDMIN', r'\hex{FD}~~\hex{8F}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frelaxed_min'), + Instruction(r'\F64X2.\RELAXEDMAX', r'\hex{FD}~~\hex{90}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-frelaxed_max'), + Instruction(r'\I16X8.\RELAXEDQ15MULRS', r'\hex{FD}~~\hex{91}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-irelaxed_q15mulr_s'), + Instruction(r'\I16X8.\RELAXEDDOT\K{\_i8x16\_i7x16\_s}', r'\hex{FD}~~\hex{92}~~\hex{02}', r'[\V128~\V128] \to [\V128]', r'valid-relaxed_dot', r'exec-relaxed_dot'), + Instruction(r'\I32X4.\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s}', r'\hex{FD}~~\hex{93}~~\hex{02}', r'[\V128~\V128~\V128] \to [\V128]', r'valid-relaxed_dot', r'exec-relaxed_dot'), Instruction(None, r'\hex{FE}'), Instruction(None, r'\hex{FF}'), ] diff --git a/document/core/exec/instructions.rst b/document/core/exec/instructions.rst index 4fb28a528..35bb4cb46 100644 --- a/document/core/exec/instructions.rst +++ b/document/core/exec/instructions.rst @@ -1740,24 +1740,26 @@ Most other vector instructions are defined in terms of numeric operators that ar :math:`\K{i8x16.}\RELAXEDSWIZZLE` ................................. +.. todo: align the implementation of swizzle and relaxed_swizzle + 1. Assert: due to :ref:`validation `, two values of :ref:`value type ` |V128| are on the top of the stack. 2. Pop the value :math:`\V128.\VCONST~c_2` from the stack. 3. Pop the value :math:`\V128.\VCONST~c_1` from the stack. -4. Let :math:`c'` be the result of computing :math:`\lanes^{-1}_{\I8X16}(\relaxedswizzle(\lanes_{i8x16}(c_1), \lanes_{i8x16}(c_2)))`. +4. Let :math:`c'` be the result of computing :math:`\lanes^{-1}_{\I8X16}(\irelaxedswizzle(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)))`. 5. Push the value :math:`\V128.\VCONST~c'` onto the stack. .. math:: \begin{array}{l} \begin{array}{lcl@{\qquad}l} - (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\K{i8x16}\K{.}\relaxedswizzle &\stepto& (\V128\K{.}\VCONST~c') + (\V128\K{.}\VCONST~c_1)~(\V128\K{.}\VCONST~c_2)~\I8X16\K{.}\irelaxedswizzle &\stepto& (\V128\K{.}\VCONST~c') \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} - (\iff & c' = \lanes^{-1}_{i8x16}(\relaxedswizzle(\lanes_{i8x16}(c_1), \lanes_{i8x16}(c_2))) + (\iff & c' = \lanes^{-1}_{\I8X16}(\irelaxedswizzle(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))) \end{array} \end{array} @@ -1971,12 +1973,12 @@ Most other vector instructions are defined in terms of numeric operators that ar \end{array} -.. _exec-relaxedlaneselect: +.. _exec-relaxed_laneselect: :math:`t\K{x}N\K{.}\RELAXEDLANESELECT` ...................................... -1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. +1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. 2. Pop the value :math:`\V128.\VCONST~c_3` from the stack. @@ -1984,9 +1986,9 @@ Most other vector instructions are defined in terms of numeric operators that ar 4. Pop the value :math:`\V128.\VCONST~c_1` from the stack. -5. Let :math:`B` be the :ref:`bit width ` :math:`|t|` of :ref:`value type ` :math:`t`. +5. Let :math:`N` be the :ref:`bit width ` :math:`|t|` of :ref:`value type ` :math:`t`. -6. Let :math:`c` be the result of computing :math:`\lanes^{-1}_{t\K{x}N}(\relaxedlaneselect_{B}(\lanes_{t\K{x}N}(c_1), \lanes_{t\K{x}N}(c_2), \lanes_{t\K{x}N}(c_3)))`. +6. Let :math:`c` be the result of computing :math:`\irelaxedlaneselect_{t\K{x}N}(c_1, c_2, c_3)`. 7. Push the value :math:`\V128.\VCONST~c` to the stack. @@ -1997,7 +1999,7 @@ Most other vector instructions are defined in terms of numeric operators that ar \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} - (\iff c = \lanes^{-1}_{t\K{x}N}(\relaxedlaneselect_{|t|}(\lanes_{t\K{x}N}(c_1), \lanes_{t\K{x}N}(c_2), \lanes_{t\K{x}N}(c_3)))) \\ + (\iff c = \irelaxedlaneselect_{t\K{x}N}(c_1, c_2, c_3)^\ast \\ \end{array} \end{array} @@ -2325,13 +2327,15 @@ where: :math:`\K{i16x8.}\RELAXEDDOT\K{\_i8x16\_i7x16\_s}` .................................................. +.. todo: move more of this to numerics + 1. Assert: due to :ref:`validation `, two values of :ref:`value type ` |V128| are on the top of the stack. 2. Pop the value :math:`\V128.\VCONST~c_2` from the stack. 3. Pop the value :math:`\V128.\VCONST~c_1` from the stack. -4. Let :math:`(i_1~i_2)^8` be the result of computing :math:`\relaxeddotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` +4. Let :math:`(i_1~i_2)^8` be the result of computing :math:`\irelaxeddotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` 5. Let :math:`j^8` be the result of computing :math:`\sats_{16}(i_1 + i_2)^8`. @@ -2346,7 +2350,7 @@ where: \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} - (\iff & (i_1~i_2)^8 = \relaxeddotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ + (\iff & (i_1~i_2)^8 = \irelaxeddotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ \wedge & j^8 = \sats_{16}(i_1, i_2)^8 \\ \wedge & c = \lanes^{-1}_{\I16X8}(j^8)) \end{array} @@ -2356,6 +2360,8 @@ where: :math:`\K{i32x4.}\RELAXEDDOT\K{\_i8x16\_i7x16\_add\_s}` ....................................................... +.. todo: move more of this to numerics + 1. Assert: due to :ref:`validation `, three values of :ref:`value type ` |V128| are on the top of the stack. 2. Pop the value :math:`\V128.\VCONST~c_3` from the stack. @@ -2364,7 +2370,7 @@ where: 4. Pop the value :math:`\V128.\VCONST~c_1` from the stack. -5. Let :math:`(i_1~i_2)^8` be the result of computing :math:`\relaxeddotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` +5. Let :math:`(i_1~i_2)^8` be the result of computing :math:`\irelaxeddotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` 6. Let :math:`(j_1~j_2)^4` be the result of computing :math:`\sats_{16}(i_1 + i_2)^8`. @@ -2385,7 +2391,7 @@ where: \end{array} \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} - (\iff & (i_1~i_2)^8 = \relaxeddotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ + (\iff & (i_1~i_2)^8 = \irelaxeddotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ \wedge & (j_1~j_2)^4 = \sats_{16}(i_1 + i_2)^8 \\ \wedge & j^4 = \iadd_{32}(\extend^{s}_{16, 32}(j_1), \extend^{s}_{16, 32}(j_2))^4 \\ \wedge & k^4 = \lanes_{\I32X4}(c_3) \\ diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 3348a8367..a32ff11b7 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -1054,9 +1054,9 @@ The non-deterministic result is expressed by the following auxiliary function pr \begin{array}{llcl@{\qquad}l} & \nans_N\{z^\ast\} &=& \{ + \NAN(\canon_N) \} \\ \exprofiles{\PROFDET} & \nans_N\{z^\ast\} &=& \{ + \NAN(n), - \NAN(n) ~|~ n = \canon_N \} - & (\iff \forall \,{\pm \NAN(n)} \in z^\ast,~ n = \canon_N) \\ + & (\iff \{z^\ast\} \subseteq \{ + \NAN(\canon_N), - \NAN(\canon_N) \} \\ \exprofiles{\PROFDET} & \nans_N\{z^\ast\} &=& \{ + \NAN(n), - \NAN(n) ~|~ n \geq \canon_N \} - & (\iff \exists \,{\pm \NAN(n)} \in z^\ast,~ n \neq \canon_N) \\ + & (\iff \{z^\ast\} \not\subseteq \{ + \NAN(\canon_N), - \NAN(\canon_N) \} \\ \end{array} @@ -1239,6 +1239,55 @@ The non-deterministic result is expressed by the following auxiliary function pr \end{array} +.. _op-fma: + +:math:`\fma_N(z_1, z_2, z_3)` +............................. + +The function :math:`\fma` is the same as *fusedMultiplyAdd* defined by |IEEE754|_ (Section 5.4.1). +It computes :math:`(z_1 \cdot z_2) + z_3` as if with unbounded range and precision, rounding only once for the final result. + +* If either :math:`z_1` or :math:`z_2` or :math:`z_3` is a NaN, return an element of :math:`\nans_N{z_1, z_2, z_3}`. + +* Else if either :math:`z_1` or :math:`z_2` is a zero and the other is an infinity, then return an element of :math:`\nans_N\{\}`. + +* Else if both :math:`z_1` or :math:`z_2` are infinities of equal sign, and :math:`z_3` is a negative infinity, then return an element of :math:`\nans_N\{\}`. + +* Else if both :math:`z_1` or :math:`z_2` are infinities of opposite sign, and :math:`z_3` is a positive infinity, then return an element of :math:`\nans_N\{\}`. + +* Else if either :math:`z_1` or :math:`z_2` is an infinity and the other is a value of the same sign, and :math:`z_3` is a negative infinity, then return an element of :math:`\nans_N\{\}`. + +* Else if either :math:`z_1` or :math:`z_2` is an infinity and the other is a value of the opposite sign, and :math:`z_3` is a positive infinity, then return an element of :math:`\nans_N\{\}`. + +* Else if both :math:`z_1` and :math:`z_2` are zeroes of the same sign and :math:`z_3` is a zero, then return positive zero. + +* Else if both :math:`z_1` and :math:`z_2` are zeroes of the opposite sign and :math:`z_3` is a positive zero, then return positive zero. + +* Else if both :math:`z_1` and :math:`z_2` are zeroes of the opposite sign and :math:`z_3` is a negative zero, then return negative zero. + +* Else return the result of multiplying :math:`z_1` and :math:`z_2`, adding :math:`z_3` to the intermediate, and the final result ref:`rounded ` to the nearest representable value. + +.. math:: + \begin{array}{@{}llcll} + & \fma_N(\pm \NAN(n), z_2, z_3) &=& \nans_N\{\pm \NAN(n), z_2, z_3\} \\ + & \fma_N(z_1, \pm \NAN(n), z_3) &=& \nans_N\{\pm \NAN(n), z_1, z_3\} \\ + & \fma_N(z_1, z_2, \pm \NAN(n)) &=& \nans_N\{\pm \NAN(n), z_1, z_2\} \\ + & \fma_N(\pm \infty, \pm 0, z_3) &=& \nans_N\{\} \\ + & \fma_N(\pm \infty, \mp 0, z_3) &=& \nans_N\{\} \\ + & \fma_N(\pm \infty, \pm \infty, - \infty) &=& \nans_N\{\} \\ + & \fma_N(\pm \infty, \mp \infty, + \infty) &=& \nans_N\{\} \\ + & \fma_N(\pm q_1, \pm \infty, - \infty) &=& \nans_N\{\} \\ + & \fma_N(\pm q_1, \mp \infty, + \infty) &=& \nans_N\{\} \\ + & \fma_N(\pm \infty, \pm q_1, - \infty) &=& \nans_N\{\} \\ + & \fma_N(\mp \infty, \pm q_1, + \infty) &=& \nans_N\{\} \\ + & \fma_N(\pm 0, \pm 0, \mp 0) &=& + 0 \\ + & \fma_N(\pm 0, \pm 0, \pm 0) &=& + 0 \\ + & \fma_N(\pm 0, \mp 0, + 0) &=& + 0 \\ + & \fma_N(\pm 0, \mp 0, - 0) &=& - 0 \\ + & \fma_N(z_1, z_2, z_3) &=& \ieee_N(z_1 \cdot z_2 + z_3) \\ + \end{array} + + .. _op-fmin: :math:`\fmin_N(z_1, z_2)` @@ -1979,332 +2028,276 @@ Conversions \narrowu_{M,N}(i) &=& \satu_N(\signed_M(i)) \end{array} + .. _relaxed-ops: +.. _aux-relaxed: -Relaxed operations +Relaxed Operations ~~~~~~~~~~~~~~~~~~ -The result of *relaxed* operators are *host-dependent*, because the set of -possible results may depend on properties of the host environment (such as -hardware). Technically, each such operator produces a fixed-size *list of sets* -of allowed values. For each execution of the operator in the same environment, -only values from the set at the same position in the list are returned, i.e., -each environment globally chooses a fixed projection for each operator. - -.. note:: - Each operator can be thought of as a family of operations that is fixed to - one particular choice by the execution environment. The fixed operation - itself can still be non-deterministic or partial. - - -.. _op-fma: - -:math:`\fma(z_1, z_2, z_3)` -........................... +The result of *relaxed* operators are *implementation-dependent*, because the set of possible results may depend on properties of the host environment, such as its hardware. +Technically, their behaviour is controlled by a set of *global parameters* to the semantics that an implementation can instantiate in different ways. +These choices are fixed, that is, parameters are constant during the execution of any given program. -The function :math:`\fma` is the same as *fusedMultiplyAdd* defined by |IEEE754|_ (Section 5.4.1). -It computes :math:`(z_1 \cdot z_2) + z_3` as if with unbounded range and precision, rounding only once for the final result. - -* If either :math:`z_1` or :math:`z_2` or :math:`z_3` is a NaN, return an element of :math:`\nans_N{z_1, z_2, z_3}`. - -* Else if either :math:`z_1` or :math:`z_2` is a zero and the other is an infinity, then return an element of :math:`\nans_N\{\}`. - -* Else if both :math:`z_1` or :math:`z_2` are infinities of equal sign, and :math:`z_3` is a negative infinity, then return an element of :math:`\nans_N\{\}`. - -* Else if both :math:`z_1` or :math:`z_2` are infinities of opposite sign, and :math:`z_3` is a positive infinity, then return an element of :math:`\nans_N\{\}`. - -* Else if either :math:`z_1` or :math:`z_2` is an infinity and the other is a value of the same sign, and :math:`z_3` is a negative infinity, then return an element of :math:`\nans_N\{\}`. - -* Else if either :math:`z_1` or :math:`z_2` is an infinity and the other is a value of the opposite sign, and :math:`z_3` is a positive infinity, then return an element of :math:`\nans_N\{\}`. - -* Else if both :math:`z_1` and :math:`z_2` are zeroes of the same sign and :math:`z_3` is a zero, then return positive zero. - -* Else if both :math:`z_1` and :math:`z_2` are zeroes of the opposite sign and :math:`z_3` is a positive zero, then return positive zero. - -* Else if both :math:`z_1` and :math:`z_2` are zeroes of the opposite sign and :math:`z_3` is a negative zero, then return negative zero. - -* Else return the result of multiplying :math:`z_1` and :math:`z_2`, adding :math:`z_3` to the intermediate, and the final result ref:`rounded ` to the nearest representable value. +Every such parameter is an index into a sequence of possible sets of results and must be instantiated to a defined index. +In the :ref:`deterministic profile `, every parameter is prescribed to be 0. +This behaviour is expressed by the following auxiliary function, +where :math:`R` is a global parameter selecting one of the allowed outcomes: .. math:: - \begin{array}{@{}llcll} - & \fma_N(\pm \NAN(n), z_2, z_3) &=& \nans_N\{\pm \NAN(n), z_2, z_3\} \\ - & \fma_N(z_1, \pm \NAN(n), z_3) &=& \nans_N\{\pm \NAN(n), z_1, z_3\} \\ - & \fma_N(z_1, z_2, \pm \NAN(n)) &=& \nans_N\{\pm \NAN(n), z_1, z_2\} \\ - & \fma_N(\pm \infty, \pm 0, z_3) &=& \nans_N\{\} \\ - & \fma_N(\pm \infty, \mp 0, z_3) &=& \nans_N\{\} \\ - & \fma_N(\pm \infty, \pm \infty, - \infty) &=& \nans_N\{\} \\ - & \fma_N(\pm \infty, \mp \infty, + \infty) &=& \nans_N\{\} \\ - & \fma_N(\pm q_1, \pm \infty, - \infty) &=& \nans_N\{\} \\ - & \fma_N(\pm q_1, \mp \infty, + \infty) &=& \nans_N\{\} \\ - & \fma_N(\pm \infty, \pm q_1, - \infty) &=& \nans_N\{\} \\ - & \fma_N(\mp \infty, \pm q_1, + \infty) &=& \nans_N\{\} \\ - & \fma_N(\pm 0, \pm 0, \mp 0) &=& + 0 \\ - & \fma_N(\pm 0, \pm 0, \pm 0) &=& + 0 \\ - & \fma_N(\pm 0, \mp 0, + 0) &=& + 0 \\ - & \fma_N(\pm 0, \mp 0, - 0) &=& - 0 \\ - & \fma_N(z_1, z_2, z_3) &=& \ieee_N(z_1 \cdot z_2 + z_3) \\ + \begin{array}{@{}lcll} + \EXPROFDET & \relaxed(R)[ A_0, \dots, A_n ] = A_R \\ + & \relaxed(R)[ A_0, \dots, A_n ] = A_0 \\ \end{array} +.. note:: + Each parameter can be thought of as inducing a family of operations + that is fixed to one particular choice by the execution environment. + The fixed operation itself can still be non-deterministic or partial. -.. _op-relaxed_madd: -:math:`\relaxedmadd_N(z_1, z_2, z_3)` -..................................... +.. _op-frelaxed_madd: -Relaxed multiply-add allows for fused or unfused results. +:math:`\frelaxedmadd_N(z_1, z_2, z_3)` +...................................... -* :math:`\EXPROFDET` Return either :math:`\fadd_N(\fmul_N(z_1, z_2), z_3)` or :math:`\fma_N(z_1, z_2, z_3)` +The implementation-specific behaviour of this operation is determined by the global parameter :math:`R_{\F{fmadd}} \in \{0, 1\}`. -* Return :math:`\fma_N(z_1, z_2, z_3)` +* Return :math:`\relaxed(R_{\F{fmadd}})[\fadd_N(\fmul_N(z_1, z_2), z_3)` or :math:`\fma_N(z_1, z_2, z_3)]`. .. math:: - \begin{array}{@{}llcll} - \EXPROFDET & \relaxedmadd_N(z_1, z_2, z_3) &=& [ \fadd_N(\fmul_N(z_1, z_2), z_3), \fma_N(z_1, z_2, z_3) ] \\ - & \relaxedmadd_N(z_1, z_2, z_3) &=& \fma_N(z_1, z_2, z_3) \\ + \begin{array}{@{}lcll} + \frelaxedmadd_N(z_1, z_2, z_3) &=& \relaxed(R_{\F{fmadd}})[ \fadd_N(\fmul_N(z_1, z_2), z_3), \fma_N(z_1, z_2, z_3) ] \\ \end{array} +.. note:: + Relaxed multiply-add allows for fused or unfused results, + which leads to implementation-dependent rounding behaviour. + In the :ref:`deterministic profile `, + the unfused behaviour is used. -.. _op-relaxed_nmadd: -:math:`\relaxednmadd_N(z_1, z_2, z_3)` -...................................... +.. _op-frelaxed_nmadd: -Relaxed negative multiply-add allows for fused or unfused results. +:math:`\frelaxednmadd_N(z_1, z_2, z_3)` +....................................... -* Return :math:`\relaxedmadd(-z_1, z_2, z_3)`. +* Return :math:`\frelaxedmadd(-z_1, z_2, z_3)`. .. math:: - \begin{array}{@{}llcll} - & \relaxednmadd_N(z_1, z_2, z_3) &=& \relaxedmadd_N(-z_1, z_2, z_3) \\ + \begin{array}{@{}lcll} + \frelaxednmadd_N(z_1, z_2, z_3) &=& \frelaxedmadd_N(-z_1, z_2, z_3) \\ \end{array} +.. note:: + This operation is implementation-dependent because :math:`\frelaxedmadd` is implementation-dependent. -.. _op-relaxed_swizzle_lane: - -:math:`\relaxedswizzlelane(i^n, j)` -................................... - -* Let :math:`k` be the :ref:`signed interpretation ` of :math:`j`. - -* If :math:`j` is less than :math:`16`, return :math:`i[j]`. - -* If :math:`k` is less than :math:`0`, return :math:`0`. - -* :math:`\EXPROFDET` Otherwise, return either :math:`0` or :math:`i[j \mod n]`. -* Otherwise, return :math:`0`. +.. _op-frelaxed_min: -.. math:: - \begin{array}{@{}llcll} - & \relaxedswizzlelane(i^n, j) &=& i[j] & (\iff j < 16) \\ - & \relaxedswizzlelane(i^n, j) &=& 0 & (\iff \signed_8(j) < 0) \\ - \EXPROFDET & \relaxedswizzlelane(i^n, j) &=& [ 0, i[j \mod n] ] & (\otherwise) \\ - & \relaxedswizzlelane(i^n, j) &=& 0 & (\otherwise) \\ - \end{array} +:math:`\frelaxedmin_N(z_1, z_2)` +................................ +The implementation-specific behaviour of this operation is determined by the global parameter :math:`R_{\F{fmin}} \in \{0, 1, 2, 3\}`. -.. _op-relaxed_swizzle: +* If :math:`z_1` is a NaN, then return :math:`\relaxed(R_{\F{fmin}})[ \fmin_N(z_1, z_2)`, \NAN(n), z_2, z_2 ]`. -:math:`\relaxedswizzle(a^n, s^n)` -................................. +* If :math:`z_2` is a NaN, then return :math:`\relaxed(R_{\F{fmin}})[ \fmin_N(z_1, z_2)`, z_1, \NAN(n), z_1 ]`. -Relaxed swizzle lane is deterministic if the signed interpretation of the index is less than 16 (including negative values). -:math:`j` is a 8-bit int. +* If both :math:`z_1` and :math:`z_2` are zeroes of opposite sign, then return :math:`\relaxed(R_{\F{fmin}})[ \fmin_N(z_1, z_2)`, \pm 0, \mp 0, -0 ]`. -* Return :math:`\X{rsl}_0 \dots \X{rsl}_{n-1}` where :math:`\X{rsl}_i = \relaxedswizzlelane(a^n, s^n[i])` +* Return :math:`\fmin_N(z_1, z_2)`. .. math:: - \begin{array}{@{}llcll} - & \relaxedswizzle(a^n, s^n) &=& \X{rsl}_0 \dots \X{rsl}_{n-1} \\ - & \qquad \where \X{rsl}_i &=& \relaxedswizzlelane(a^n, s^n[i]) + \begin{array}{@{}lcll} + \frelaxedmin_N(\pm \NAN(n), z_2) &=& \relaxed(R_{\F{fmin}})[ \fmin_N(\pm \NAN(n), z_2), \NAN(n), z_2, z_2 ] \\ + \frelaxedmin_N(z_1, \pm \NAN(n)) &=& \relaxed(R_{\F{fmin}})[ \fmin_N(z_1, \pm \NAN(n)), z_1, \NAN(n), z_1 ] \\ + \frelaxedmin_N(\pm 0, \mp 0) &=& \relaxed(R_{\F{fmin}})[ \fmin_N(\pm 0, \mp 0), \pm 0, \mp 0, -0 ] \\ + \frelaxedmin_N(z_1, z_2) &=& \fmin_N(z_1, z_2) & (\otherwise) \\ \end{array} +.. note:: + Relaxed minimum is implementation-dependent for NaNs and for zeroes with different signs. + In the :ref:`deterministic profile `, + it behaves like regular :math:`\fmin`. -.. _op-relaxed_trunc: -.. _op-relaxed_trunc_u: -:math:`\relaxedtrunc^u_{M,N}(z)` +.. _op-frelaxed_max: + +:math:`\frelaxedmax_N(z_1, z_2)` ................................ -Relaxed unsigned truncation converts floating point numbers to integers. -The result for NaN's and out-of-range values is host-dependent. +The implementation-specific behaviour of this operation is determined by the global parameter :math:`R_{\F{fmax}} \in \{0, 1, 2, 3\}`. -* :math:`\EXPROFDET` If :math:`z` is a NaN, return either :math:`0` or :math:`2^N-1` or :math:`2^N-2` or :math:`2^(N-1)`. +* If :math:`z_1` is a NaN, then return :math:`\relaxed(R_{\F{fmax}})[ \fmax_N(z_1, z_2)`, \NAN(n), z_2, z_2 ]`. -* :math:`\EXPROFDET` Else if :math:`\trunc(z)` is positive and less than :math:`2^N`, return :math:`\truncu_{M,N}(z)`. +* If :math:`z_2` is a NaN, then return :math:`\relaxed(R_{\F{fmax}})[ \fmax_N(z_1, z_2)`, z_1, \NAN(n), z_1 ]`. -* :math:`\EXPROFDET` Else return either :math:`\truncsatu_{M,N}(z)` or :math:`2^N-1` or :math:`2^N-2` or :math:`2^(N-1)`. +* If both :math:`z_1` and :math:`z_2` are zeroes of opposite sign, then return :math:`\relaxed(R_{\F{fmax}})[ \fmax_N(z_1, z_2)`, \pm 0, \mp 0, +0 ]`. -* Return :math:`\truncsatu_{M,N}(z)`. +* Return :math:`\fmax_N(z_1, z_2)`. .. math:: - \begin{array}{@{}llcll} - \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm \NAN(n)) &=& [ 0, 2^{N}-1, 2^{N}-2, 2^{N-1}] \\ - \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm q) &=& \truncu_{M,N}(\pm q) & (\iff -1 < \trunc(\pm q) < 2^N) \\ - \EXPROFDET & \relaxedtrunc^u_{M,N}(\pm p) &=& [ \truncsatu_{M,N}(\pm p), 2^{N}-1, 2^{N}-2, 2^{N-1}] & (\otherwise) \\ - & \relaxedtrunc^u_{M,N}(z) &=& \truncsatu_{M,N}(z) & \\ + \begin{array}{@{}lcll} + \frelaxedmax_N(\pm \NAN(n), z_2) &=& \relaxed(R_{\F{fmax}})[ \fmax_N(\pm \NAN(n), z_2), \NAN(n), z_2, z_2 ] \\ + \frelaxedmax_N(z_1, \pm \NAN(n)) &=& \relaxed(R_{\F{fmax}})[ \fmax_N(z_1, \pm \NAN(n)), z_1, \NAN(n), z_1 ] \\ + \frelaxedmax_N(\pm 0, \mp 0) &=& \relaxed(R_{\F{fmax}})[ \fmax_N(\pm 0, \mp 0), \pm 0, \mp 0, +0 ] \\ + \frelaxedmax_N(z_1, z_2) &=& \fmax_N(z_1, z_2) & (\otherwise) \\ \end{array} +.. note:: + Relaxed maximum is implementation-dependent for NaNs and for zeroes with different signs. + In the :ref:`deterministic profile `, + it behaves like regular :math:`\fmax`. -.. _op-relaxed_trunc_s: -:math:`\relaxedtrunc^s_{M,N}(z)` -................................ - -Relaxed signed truncation converts floating point numbers to integers. -The result for NaN's and out-of-range values is host-dependent. +.. _op-irelaxed_dot_mul: -* :math:`\EXPROFDET` If :math:`z` is a NaN, return either :math:`0` or :math:`-2^{N-1}`. +:math:`\irelaxeddotmul_{M,N}(i_1, i_2)` +....................................... -* :math:`\EXPROFDET` Else if :math:`\trunc(z)` is larger than :math:`-2^{N-1}-1` and less than :math:`2^{N-1}`, return :math:`\truncs_{M,N}(z)`. +This is an auxiliary operator for the specification of |RELAXEDDOT|. -* :math:`\EXPROFDET` Else return either :math:`\truncsats_{M,N}(z)` or :math:`-2^{N-1}`. +The implementation-specific behaviour of this operation is determined by the global parameter :math:`R_{\F{idot}} \in \{0, 1\}`. -* Return :math:`\truncsats_{M,N}(z)`. +* Return :math:`\relaxed(R_{\F{idot}})[ \imul_N(\extends_{M,N}(i_1), extends_{M,N}), \imul_N(\extends_{M,N}(i_1), \extendu_{M,N}(i_2)) ]`. .. math:: - \begin{array}{@{}llcll} - \EXPROFDET & \relaxedtrunc^s_{M,N}(\pm \NAN(n)) &=& [ 0, -2^{N-1} ] \\ - \EXPROFDET & \relaxedtrunc^s_{M,N}(\pm q) &=& \truncs_{M,N}(\pm q) & (\iff -2^{N-1} - 1 < \trunc(\pm q) < 2^{N-1}) \\ - \EXPROFDET & \relaxedtrunc^s_{M,N}(\pm p) &=& [ \truncsats_{M,N}(\pm p), -2^{N-1} ] & (\otherwise) \\ - & \relaxedtrunc^s_{M,N}(z) &=& \truncsats_{M,N}(z) & \\ + \begin{array}{@{}lcll} + \irelaxeddotmul_{M,N}(i_1, i_2) &=& \relaxed(R_{\F{idot}})[ \imul_N(\extends_{M,N}(i_1), extends_{M,N}), \imul_N(\extends_{M,N}(i_1), \extendu_{M,N}(i_2)) ] \\ \end{array} +.. note:: + Relaxed dot product is implementation-dependent when the second operand is negative in a signed intepretation. + In the :ref:`deterministic profile `, + it behaves like signed dot product. + -.. _op-relaxed_lane: +.. _op-irelaxed_q15mulr_s: -:math:`\relaxedlane_N(i_1, i_2, i_3)` +:math:`\irelaxedq15mulrs_N(i_1, i_2)` ..................................... -* :math:`\EXPROFDET` If :math:`i_3` is :math:`2^N - 1`, return :math:`i_1`. - -* :math:`\EXPROFDET` Else if :math:`i_3` is :math:`0`, return :math:`i_2`. +The implementation-specific behaviour of this operation is determined by the global parameter :math:`R_{\F{iq15mulr}} \in \{0, 1\}`. -* :math:`\EXPROFDET` Otherwise return either :math:`\ibitselect_n(i_1, i_2, i_3)` or :math:`i_1` or :math:`i_2` or :math:`\F{top\_bit\_byteselect_N}(i_1, i_2, i_3)`. +* If both :math:`i_1` and :math:`i_2` equal :math:`(\signed^{-1}_N(-2^{N-1})`, then return :math:`\relaxed(R_{\F{iq15mulr}})[ 2^{N-1}-1, \signed^{-1}_N(-2^{N-1}) ]`. -* Return :math:`\ibitselect_n(i_1, i_2, i_3)`. +* Return :math:`\iq15mulrsats(i_1, i_2)` .. math:: - \begin{array}{@{}llcll} - \EXPROFDET & \relaxedlane_N(i_1, i_2, 2^N-1) &=& i_1 \\ - \EXPROFDET & \relaxedlane_N(i_1, i_2, 0) &=& i_2 \\ - \EXPROFDET & \relaxedlane_N(i_1, i_2, i_3) &=& [ \ibitselect_N(i_1, i_2, i_3), i_2, i_3, \\ - & & & \qquad \F{top\_bit\_byteselect}(i_1, i_2, i_3)] & (\otherwise) \\ - & \relaxedlane_N(i_1, i_2, i_3) &=& \ibitselect_N(i_1, i_2, i_3) & (\otherwise) \\ + \begin{array}{@{}lcll} + \irelaxedq15mulrs_N(\signed^{-1}_N(-2^{N-1}), \signed^{-1}_N(-2^{N-1})) &=& \relaxed(R_{\F{iq15mulr}})[ 2^{N-1}-1, \signed^{-1}_N(-2^{N-1}) ] & \\ + \irelaxedq15mulrs_N(i_1, i_2) &=& \iq15mulrsats(i_1, i_2) \end{array} -where: +.. note:: + Relaxed Q15 multiplication is implementation-dependent when the result overflows. + In the :ref:`deterministic profile `, + it behaves like regular :math:`\iq15mulrsats`. -.. math:: - \begin{array}{@{}llcll} - & \F{top\_bit\_byteselect}_N(i_1, i_2, i_3) &=& tbb_0 ... tbb_{N/8 - 1} \\ - & \F{tbb_j} &=& \F{byteselect}(\bytes_8(i_1)[j], \bytes_8(i_2)[j], \bytes_8(i_3)[j]) \\ - & \F{byteselect}(a, b, 0~c^7) &=& a \\ - & \F{byteselect}(a, b, c) &=& b \\ - \end{array} +.. _op-relaxed_trunc: +.. _op-relaxed_trunc_u: -.. _op-relaxed_lane_select: +:math:`\relaxedtrunc^u_{M,N}(z)` +................................ -:math:`\relaxedlaneselect_B(a^n, b^n, c^n)` -........................................... +The implementation-specific behaviour of this operation is determined by the global parameter :math:`R_{\F{trunc\_u}} \in \{0, 1, 2, 3\}`. -Relaxed lane selection is deterministic when all bits are set or unset in the -mask. Otherwise depending on the host, either only the top bit is examined, or -all bits are examined (i.e. it becomes a bit select), or the top bit of each -byte in the lane is examined. +* If :math:`z` is normal or subnormal and :math:`\trunc(z)` is non-negative and less than :math:`2^N`, then return :math:`\truncu_{M,N}(z)`. -* Return :math:`rll_0 \dots rll_{n-1}` where :math:`rll_i = \relaxedlane_B(a^n[i], b^n[i], c^n[i])`. +* Else, return :math:`\relaxed(R_{\F{trunc\_u}})[ \truncsatu_{M,N}(z), 2^N-1, 2^N-2, 2^(N-1) ]`. .. math:: - \begin{array}{@{}llcll} - & \relaxedlaneselect_B(a^n, b^n, c^n) &=& rll_0 \dots rll_{n-1} \\ - & \qquad \where rll_i &=& \relaxedlane_B(a^n[i], b^n[i], c^n[i]) \\ + \begin{array}{@{}lcll} + \relaxedtrunc^u_{M,N}(\pm q) &=& \truncu_{M,N}(\pm q) & (\iff 0 \leq \trunc(\pm q) < 2^N) \\ + \relaxedtrunc^u_{M,N}(z) &=& \relaxed(R_{\F{trunc\_u}})[ \truncsatu_{M,N}(z), 2^{N}-1, 2^{N}-2, 2^{N-1}] & (\otherwise) \\ \end{array} +.. note:: + Relaxed unsigned truncation is implementation-dependent for NaNs and out-of-range values. + In the :ref:`deterministic profile `, + it behaves like regular :math:`\truncu`. -.. _op-relaxed_min: - -:math:`\relaxedmin_N(z_1, z_2)` -............................... -Relaxed minimum differs from regular minimum when inputs are NaN's or zeroes with different signs. -It allows for implementation to return the first or second input when either input is a NaN. +.. _op-relaxed_trunc_s: -* :math:`\EXPROFDET` If :math:`z_1` is a NaN, return either an element of :math:`\nans_N\{z_1, z_2\}`, :math:`\NAN(n)`, or :math:`z_2` +:math:`\relaxedtrunc^s_{M,N}(z)` +................................ -* :math:`\EXPROFDET` If :math:`z_2` is a NaN, return either an element of :math:`\nans_N\{z_1, z_2\}`, :math:`\NAN(n)`, or :math:`z_1` +The implementation-specific behaviour of this operation is determined by the global parameter :math:`R_{\F{trunc\_s}} \in \{0, 1\}`. -* :math:`\EXPROFDET` If both :math:`z_1` and :math:`z_2` are zeroes of opposite sign, return either :math:`+ 0` or :math:`- 0`. +* If :math:`z` is normal or subnormal and :math:`\trunc(z)` is greater than or equal to :math:`-2^{N-1}` and less than :math:`2^{N-1}`, then return :math:`\truncs_{M,N}(z)`. -* Return :math:`\fmin_N(z_1, z_2)`. +* Else, return :math:`\relaxed(R_{\F{trunc\_s}})[ \truncsats_{M,N}(z), 2^N-1, 2^N-2, 2^(N-1) ]`. .. math:: - \begin{array}{@{}llcll} - \EXPROFDET & \relaxedmin_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ - \EXPROFDET & \relaxedmin_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ - \EXPROFDET & \relaxedmin_N(\pm 0, \mp 0) &=& [ -0, \pm 0, \mp 0, -0 ] \\ - & \relaxedmin_N(z_1, z_2) &=& \fmin_N(z_1, z_2) & (\otherwise) \\ + \begin{array}{@{}lcll} + \relaxedtrunc^s_{M,N}(\pm q) &=& \truncs_{M,N}(\pm q) & (\iff -2^{N-1} \leq \trunc(\pm q) < 2^{N-1}) \\ + \relaxedtrunc^s_{M,N}(z) &=& \relaxed(R_{\F{trunc\_s}})[ \truncsats_{M,N}(z), \signed^{-1}_N(-2^{N-1})] & (\otherwise) \\ \end{array} +.. note:: + Relaxed signed truncation is implementation-dependent for NaNs and out-of-range values. + In the :ref:`deterministic profile `, + it behaves like regular :math:`\truncs`. -.. _op-relaxed_max: -:math:`\relaxedmax_N(z_1, z_2)` -............................... +.. _op-irelaxed_swizzle: +.. _op-irelaxed_swizzle_lane: -Relaxed maximum differs from regular maximum when inputs are NaN's or zeroes with different signs. -It allows for implementations to return the first or second input when either input is a NaN. +:math:`\irelaxedswizzle(i^n, j^n)` +.................................. -* :math:`\EXPROFDET` If :math:`z_1` is a NaN, return either an element of :math:`\nans_N\{z_1, z_2\}`, :math:`\NAN(n)`, or :math:`z_2` +The implementation-specific behaviour of this operation is determined by the global parameter :math:`R_{\F{swizzle}} \in \{0, 1\}`. -* :math:`\EXPROFDET` If :math:`z_2` is a NaN, return either an element of :math:`\nans_N\{z_1, z_2\}`, :math:`\NAN(n)`, or :math:`z_1` +* For each :math:`j_k` in :math:`j^n`, let :math:`r_k` be the value :math:`\irelaxedswizzlelane(i^n, j_k)`. -* :math:`\EXPROFDET` If both :math:`z_1` and :math:`z_2` are zeroes of opposite sign, return either :math:`+ 0` or :math:`- 0`. +* Let :math:`r^n` be the concatenation of all :math:`r_k`. -* Return :math:`\fmax_N(z_1, z_2)`. +* Return :math:`r^n`. .. math:: - \begin{array}{@{}llcll} - \EXPROFDET & \relaxedmax_N(\pm \NAN(n), z_2) &=& [ \nans_N\{\pm \NAN(n), z_2\}, \NAN(n), z_2, z_2 ] \\ - \EXPROFDET & \relaxedmax_N(z_1, \pm \NAN(n)) &=& [ \nans_N\{\pm \NAN(n), z_1\}, z_1, \NAN(n), z_1 ] \\ - \EXPROFDET & \relaxedmax_N(\pm 0, \mp 0) &=& [ +0, \pm 0, \mp 0, +0 ] \\ - & \relaxedmax_N(z_1, z_2) &=& \fmax_N(z_1, z_2) & (\otherwise) \\ + \begin{array}{@{}lcl} + \irelaxedswizzle(i^n, j^n) &=& \irelaxedswizzlelane(i^n, j)^n \\ \end{array} - -.. _op-relaxed_q15mulr_s: - -:math:`\relaxedq15mulrs_N(i_1, i_2)` -.................................... - -Relaxed Q15 multiply differs from regular Q15 multiply when the multiplication results overflows (i.e. when both inputs are -32768). -It allows for implementations to either wrap around or saturate. - -* :math:`\EXPROFDET` If both :math:`z_1` and :math:`z_2` are :math:`-2^{N-1}`, return either :math:`2^{N-1} - 1` or :math:`-2^{N-1}`. - -* Return :math:`\iq15mulrsats(i_1, i_2)` +where: .. math:: - \begin{array}{@{}llcll} - \EXPROFDET & \relaxedq15mulrs_N(-2^{N-1}, -2^{N-1}) &=& [ 2^{N-1}-1, -2^{N-1}] & \\ - & \relaxedq15mulrs_N(i_1, i_2) &=& \iq15mulrsats(i_1, i_2) + \begin{array}{@{}lcll} + \irelaxedswizzlelane(i^n, j) &=& i[j] & (\iff j < 16) \\ + \irelaxedswizzlelane(i^n, j) &=& 0 & (\iff \signed_8(j) < 0) \\ + \irelaxedswizzlelane(i^n, j) &=& \relaxed(R_{\F{swizzle}})[ 0, i[j \mod n] ] & (\otherwise) \\ \end{array} +.. note:: + Relaxed swizzle is implementation-dependent + if the signed interpretation of any of the 8-bit indices in :math:`j^n` is larger than or equal to 16. + In the :ref:`deterministic profile `, + it behaves like regular :math:`\SWIZZLE`. -.. _op-relaxed_dot_mul: -:math:`\relaxeddotmul_{M,N}(i_1, i_2)` -...................................... +.. _op-irelaxed_laneselect: + +:math:`\irelaxedlaneselect_N(i_1, i_2, i_3)` +............................................ -Relaxed integer dot product differs from regular integer dot product when the elements of the input have their most significant bit set. +The implementation-specific behaviour of this operation is determined by the global parameter :math:`R_{\F{laneselect}} \in \{0, 1\}`. -* :math:`\EXPROFDET` Return either :math:`\imul_N(\signed_M(i_1), i_2), \imul_N(\signed_M(i_1), \signed_M(i_2))`. +* If :math:`i_3` is smaller than :math:`2^{N-1}`, then let :math:`i'_3` be the value :math:`0`, otherwise :math:`2^N-1`. -* Return :math:`\imul_N(\extends_{M,N}(i_1), \extends_{M,N}(i_2))`. +* Let :math:`i''_3` be :math:`\relaxed(R_{\F{laneselect}})[i_3, i'_3]`. + +* Return :math:`\ibitselect_N(i_1, i_2, i''_3)`. .. math:: - \begin{array}{@{}llcll} - \EXPROFDET & \relaxeddotmul_{M,N}(i_1, i_2) &=& [ \imul_N(\signed_M(i_1), i_2), \imul_N(\signed_M(i_1), \signed_M(i_2)) ] \\ - & \relaxeddotmul_{M,N}(i_1, i_2) &=& \imul_N(\extends_{M,N}(i_1), \extends_{M,N}(i_2)) \\ + \begin{array}{@{}lcll} + \irelaxedlaneselect_N(i_1, i_2, i_3) &=& \ibitselect_N(i_1, i_2, \relaxed(R_{\F{laneselect}})[ i_3, \extends_{1,N}(\ishru_N(i_3, N-1)) ]) \\ \end{array} + +.. note:: + Relaxed lane selection is non-deterministic when the mask mixes set and cleared bits, + since the value of the high bit may or may not be expanded to all bits. + In the :ref:`deterministic profile `, + it behaves like :math:`\ibitselect`. diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 2adae94f9..82d731fbf 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -1487,6 +1487,7 @@ .. |fsub| mathdef:: \xref{exec/numerics}{op-fsub}{\F{fsub}} .. |fmul| mathdef:: \xref{exec/numerics}{op-fmul}{\F{fmul}} .. |fdiv| mathdef:: \xref{exec/numerics}{op-fdiv}{\F{fdiv}} +.. |fma| mathdef:: \xref{exec/numerics}{op-fma}{\F{fma}} .. |fmin| mathdef:: \xref{exec/numerics}{op-fmin}{\F{fmin}} .. |fmax| mathdef:: \xref{exec/numerics}{op-fmax}{\F{fmax}} .. |fcopysign| mathdef:: \xref{exec/numerics}{op-fcopysign}{\F{fcopysign}} @@ -1523,18 +1524,16 @@ .. |narrowu| mathdef:: \xref{exec/numerics}{op-narrow_u}{\F{narrow}^{\K{u}}} .. |narrows| mathdef:: \xref{exec/numerics}{op-narrow_s}{\F{narrow}^{\K{s}}} -.. |fma| mathdef:: \xref{exec/numerics}{op-fma}{\F{fma}} -.. |relaxedmadd| mathdef:: \xref{exec/numerics}{op-relaxed_madd}{\F{frelaxed\_madd}} -.. |relaxednmadd| mathdef:: \xref{exec/numerics}{op-relaxed_nmadd}{\F{frelaxed\_nmadd}} -.. |relaxedswizzlelane| mathdef:: \xref{exec/numerics}{op-relaxed_swizzle_lane}{\F{relaxed\_swizzle\_lane}} -.. |relaxedswizzle| mathdef:: \xref{exec/numerics}{op-relaxed_swizzle}{\F{relaxed\_swizzle}} +.. |frelaxedmadd| mathdef:: \xref{exec/numerics}{op-frelaxed_madd}{\F{frelaxed\_madd}} +.. |frelaxednmadd| mathdef:: \xref{exec/numerics}{op-frelaxed_nmadd}{\F{frelaxed\_nmadd}} +.. |irelaxedswizzlelane| mathdef:: \xref{exec/numerics}{op-irelaxed_swizzle_lane}{\F{frelaxed\_swizzle\_lane}} +.. |irelaxedswizzle| mathdef:: \xref{exec/numerics}{op-irelaxed_swizzle}{\F{frelaxed\_swizzle}} .. |relaxedtrunc| mathdef:: \xref{exec/numerics}{op-relaxed_trunc}{\F{relaxed\_trunc}} -.. |relaxedlane| mathdef:: \xref{exec/numerics}{op-relaxed_lane}{\F{relaxed\_lane}} -.. |relaxedlaneselect| mathdef:: \xref{exec/numerics}{op-relaxed_lane_select}{\F{relaxed\_laneselect}} -.. |relaxedmin| mathdef:: \xref{exec/numerics}{op-relaxed_min}{\F{frelaxed\_min}} -.. |relaxedmax| mathdef:: \xref{exec/numerics}{op-relaxed_max}{\F{frelaxed\_max}} -.. |relaxedq15mulrs| mathdef:: \xref{exec/numerics}{op-relaxed_q15mulr_s}{\F{irelaxed\_q15mulr\_s}} -.. |relaxeddotmul| mathdef:: \xref{exec/numerics}{op-relaxed_dot_mul}{\F{relaxed\_dot\_mul}} +.. |irelaxedlaneselect| mathdef:: \xref{exec/numerics}{op-irelaxed_laneselect}{\F{irelaxed\_laneselect}} +.. |frelaxedmin| mathdef:: \xref{exec/numerics}{op-frelaxed_min}{\F{frelaxed\_min}} +.. |frelaxedmax| mathdef:: \xref{exec/numerics}{op-frelaxed_max}{\F{frelaxed\_max}} +.. |irelaxedq15mulrs| mathdef:: \xref{exec/numerics}{op-irelaxed_q15mulr_s}{\F{irelaxed\_q15mulr\_s}} +.. |irelaxeddotmul| mathdef:: \xref{exec/numerics}{op-irelaxed_dot_mul}{\F{irelaxed\_dot\_mul}} .. Numerics, meta functions @@ -1557,6 +1556,8 @@ .. |lanes| mathdef:: \xref{exec/numerics}{aux-lanes}{\F{lanes}} +.. |relaxed| mathdef:: \xref{exec/numerics}{aux-relaxed}{\F{relaxed}} + .. Other meta functions diff --git a/document/core/valid/instructions.rst b/document/core/valid/instructions.rst index f0a57b49c..d3f3577dd 100644 --- a/document/core/valid/instructions.rst +++ b/document/core/valid/instructions.rst @@ -1038,7 +1038,7 @@ The following auxiliary function denotes the number of lanes in a vector shape, } -.. _valid-relaxedlaneselect: +.. _valid-relaxed_laneselect: :math:`\shape\K{.}\RELAXEDLANESELECT` ..................................... From bc87071c03c7850fc12f336c8168764f2f8ceb2c Mon Sep 17 00:00:00 2001 From: Andreas Rossberg Date: Fri, 6 Sep 2024 09:36:51 +0200 Subject: [PATCH 110/117] Implementation note --- document/core/exec/numerics.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index a32ff11b7..cfbe1ae7b 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2052,9 +2052,12 @@ where :math:`R` is a global parameter selecting one of the allowed outcomes: .. note:: Each parameter can be thought of as inducing a family of operations - that is fixed to one particular choice by the execution environment. + that is fixed to one particular choice by an implementation. The fixed operation itself can still be non-deterministic or partial. + Implementations are expexted to either choose the behaviour that is the most efficient on the underlying hardware, + or the behaviour of the deterministic profile. + .. _op-frelaxed_madd: From a315401ada94e5bf3a3c04424410b9d9237aad06 Mon Sep 17 00:00:00 2001 From: Clemens Backes Date: Tue, 24 Sep 2024 17:29:55 +0200 Subject: [PATCH 111/117] [test] Fix left-over use of kWasmStmt in wasm-module-builder (#1812) This was renamed to kWasmVoid in https://github.com/WebAssembly/memory64/commit/2f5a7c524fdc4dec280c6a53bc3cc800b6ad1c11. --- test/js-api/wasm-module-builder.js | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/js-api/wasm-module-builder.js b/test/js-api/wasm-module-builder.js index 4b5abcfbe..04f19b278 100644 --- a/test/js-api/wasm-module-builder.js +++ b/test/js-api/wasm-module-builder.js @@ -934,7 +934,7 @@ class WasmModuleBuilder { addTable(type, initial_size, max_size = undefined, init_expr = undefined) { if (type == kWasmI32 || type == kWasmI64 || type == kWasmF32 || - type == kWasmF64 || type == kWasmS128 || type == kWasmStmt) { + type == kWasmF64 || type == kWasmS128 || type == kWasmVoid) { throw new Error('Tables must be of a reference type'); } if (init_expr != undefined) checkExpr(init_expr); From 09cc6c67df9839fce619ccfe7ae2155c9d62c6b5 Mon Sep 17 00:00:00 2001 From: Andreas Rossberg Date: Thu, 26 Sep 2024 07:59:15 +0200 Subject: [PATCH 112/117] Adapt changes --- document/core/appendix/changes.rst | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/document/core/appendix/changes.rst b/document/core/appendix/changes.rst index f0f2a808e..009abb363 100644 --- a/document/core/appendix/changes.rst +++ b/document/core/appendix/changes.rst @@ -525,13 +525,28 @@ Relaxed Vector Instructions Added new *relaxed* vector instructions, which are vector instructions whose behaviour is non-deterministic and implementation-dependent. [#proposal-relaxed]_ -* New binary :ref:`vector instruction `: :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_min}`, :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_max}`, :math:`\K{i16x8.relaxed\_q15mulr\_s}`, :math:`\K{i16x8.relaxed\_dot\_i8x16\_i7x16\_s}` +* New binary :ref:`vector instruction `: -* New ternary :ref:`vector instruction `: :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_madd}`, :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_nmadd}`, :math:`\K{i}\!N\!\K{x}\!M\!\K{.relaxed\_laneselect}`, :math:`\K{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s}` + - :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_min}` + - :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_max}` + - :math:`\K{i16x8.relaxed\_q15mulr\_s}` + - :math:`\K{i16x8.relaxed\_dot\_i8x16\_i7x16\_s}` -* New conversion :ref:`vector instructions `::math:`\K{i32x4.relaxed\_trunc\_f32x4\_}\sx`, :math:`\K{i32x4.relaxed\_trunc\_f64x2\_}\sx\K{\_zero}` +* New ternary :ref:`vector instruction `: -* New byte reordering :ref:`vector instruction `: :math:`\K{i8x16.relaxed\_swizzle}` + - :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_madd}` + - :math:`\K{f}\!N\!\K{x}\!M\!\K{.relaxed\_nmadd}` + - :math:`\K{i}\!N\!\K{x}\!M\!\K{.relaxed\_laneselect}` + - :math:`\K{i32x4.relaxed\_dot\_i8x16\_i7x16\_add\_s}` + +* New conversion :ref:`vector instructions `: + + - :math:`\K{i32x4.relaxed\_trunc\_f32x4\_}\sx` + - :math:`\K{i32x4.relaxed\_trunc\_f64x2\_}\sx\K{\_zero}` + +* New byte reordering :ref:`vector instruction `: + + - :math:`\K{i8x16.relaxed\_swizzle}` .. index:: determinism, non-determinism, profiles From 8dadd74b8b8938813fc5212aec30e81b696c0ed8 Mon Sep 17 00:00:00 2001 From: Andreas Rossberg Date: Thu, 26 Sep 2024 08:07:54 +0200 Subject: [PATCH 113/117] Eps --- document/core/appendix/changes.rst | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/document/core/appendix/changes.rst b/document/core/appendix/changes.rst index 009abb363..352bc504a 100644 --- a/document/core/appendix/changes.rst +++ b/document/core/appendix/changes.rst @@ -523,7 +523,8 @@ Added managed reference types. [#proposal-gc]_ Relaxed Vector Instructions ........................... -Added new *relaxed* vector instructions, which are vector instructions whose behaviour is non-deterministic and implementation-dependent. [#proposal-relaxed]_ +Added new *relaxed* vector instructions, +whose behaviour is non-deterministic and implementation-dependent. [#proposal-relaxed]_ * New binary :ref:`vector instruction `: @@ -554,7 +555,7 @@ Added new *relaxed* vector instructions, which are vector instructions whose beh Profiles ........ -Added the notion of :ref:`profile ` for specifying language subsets. +Introduced the concept of :ref:`profile ` for specifying language subsets. * A new profile defining a :ref:`deterministic ` mode of execution. From e9cbf1a88a2877a2c73c4651c712beb36f72b80b Mon Sep 17 00:00:00 2001 From: Andreas Rossberg Date: Tue, 1 Oct 2024 15:15:41 +0200 Subject: [PATCH 114/117] [spec] Fix typo in relaxed formula --- document/core/exec/numerics.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index cfbe1ae7b..38b254491 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -2163,11 +2163,11 @@ This is an auxiliary operator for the specification of |RELAXEDDOT|. The implementation-specific behaviour of this operation is determined by the global parameter :math:`R_{\F{idot}} \in \{0, 1\}`. -* Return :math:`\relaxed(R_{\F{idot}})[ \imul_N(\extends_{M,N}(i_1), extends_{M,N}), \imul_N(\extends_{M,N}(i_1), \extendu_{M,N}(i_2)) ]`. +* Return :math:`\relaxed(R_{\F{idot}})[ \imul_N(\extends_{M,N}(i_1), \extends_{M,N}(i_2)), \imul_N(\extends_{M,N}(i_1), \extendu_{M,N}(i_2)) ]`. .. math:: \begin{array}{@{}lcll} - \irelaxeddotmul_{M,N}(i_1, i_2) &=& \relaxed(R_{\F{idot}})[ \imul_N(\extends_{M,N}(i_1), extends_{M,N}), \imul_N(\extends_{M,N}(i_1), \extendu_{M,N}(i_2)) ] \\ + \irelaxeddotmul_{M,N}(i_1, i_2) &=& \relaxed(R_{\F{idot}})[ \imul_N(\extends_{M,N}(i_1), \extends_{M,N}(i_2)), \imul_N(\extends_{M,N}(i_1), \extendu_{M,N}(i_2)) ] \\ \end{array} .. note:: From 8e5f4eeaa1aaf407a21cf0f1268519dba8ee6b4e Mon Sep 17 00:00:00 2001 From: Andreas Rossberg Date: Thu, 3 Oct 2024 10:51:18 +0200 Subject: [PATCH 115/117] [spec] Various fixes to SIMD stuff --- document/core/exec/instructions.rst | 31 +++++++++++++++++++++-------- document/core/exec/numerics.rst | 30 ++++++++++++++-------------- 2 files changed, 38 insertions(+), 23 deletions(-) diff --git a/document/core/exec/instructions.rst b/document/core/exec/instructions.rst index e52977425..24d73e24b 100644 --- a/document/core/exec/instructions.rst +++ b/document/core/exec/instructions.rst @@ -1601,6 +1601,21 @@ Most other vector instructions are defined in terms of numeric operators that ar :math:`\lanes_{\K{i32x4}}(v_1)` and :math:`\lanes_{\K{i32x4}}(v_2)` respectively. +For non-deterministic operators this definition is generalized to sets: + +.. math:: + \begin{array}{lll} + \X{op}_{t\K{x}N}(n_1,\dots,n_k) &=& + \{ \lanes^{-1}_{t\K{x}N}(i^\ast) ~|~ i^\ast \in \Large\times\xref{Step_pure/instructions}{exec-instr-numeric}{\X{op}}_t(i_1,\dots,i_k)^\ast \land i_1^\ast = \lanes_{t\K{x}N}(n_1) \land \dots \land i_k^\ast = \lanes_{t\K{x}N}(n_k) \} \\ + \end{array} + +where :math:`\Large\times \{x^\ast\}^N` transforms a sequence of :math:`N` sets of values into a set of sequences of :math:`N` values by computing the set product: + +.. math:: + \begin{array}{lll} + \Large\times (S_1 \dots S_N) &=& \{ x_1 \dots x_N ~|~ x_1 \in S_1 \land \dots \land x_N \in S_N \} + \end{array} + .. _exec-vconst: @@ -2335,9 +2350,9 @@ where: 3. Pop the value :math:`\V128.\VCONST~c_1` from the stack. -4. Let :math:`(i_1~i_2)^8` be the result of computing :math:`\irelaxeddotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` +4. Let :math:`(i_1~i_2)^8` be the result of computing :math:`\irelaxeddotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` -5. Let :math:`j^8` be the result of computing :math:`\sats_{16}(i_1 + i_2)^8`. +5. Let :math:`j^8` be the result of computing :math:`\iaddsats_{16}(i_1, i_2)^8`. 6. Let :math:`c` be the result of computing :math:`\lanes^{-1}_{\I16X8}(j^8)`. @@ -2351,7 +2366,7 @@ where: \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} (\iff & (i_1~i_2)^8 = \irelaxeddotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ - \wedge & j^8 = \sats_{16}(i_1, i_2)^8 \\ + \wedge & j^8 = \iaddsats_{16}(i_1, i_2)^8 \\ \wedge & c = \lanes^{-1}_{\I16X8}(j^8)) \end{array} \end{array} @@ -2370,11 +2385,11 @@ where: 4. Pop the value :math:`\V128.\VCONST~c_1` from the stack. -5. Let :math:`(i_1~i_2)^8` be the result of computing :math:`\irelaxeddotmul_{8, 16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` +5. Let :math:`(i_1~i_2)^8` be the result of computing :math:`\irelaxeddotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2))` -6. Let :math:`(j_1~j_2)^4` be the result of computing :math:`\sats_{16}(i_1 + i_2)^8`. +6. Let :math:`(j_1~j_2)^4` be the result of computing :math:`\iaddsats_{16}(i_1, i_2)^8`. -7. Let :math:`j^4` be the result of computing :math:`\iadd_{32}(\extend^{s}_{16, 32}(j_1), \extend^{s}_{16, 32}(j_2))^4`. +7. Let :math:`j^4` be the result of computing :math:`\iadd_{32}(\extends_{16,32}(j_1), \extends_{16,32}(j_2))^4`. 8. Let :math:`k^4` be the result of computing :math:`\lanes_{\I32X4}(c_3)`. @@ -2392,8 +2407,8 @@ where: \\ \qquad \begin{array}[t]{@{}r@{~}l@{}} (\iff & (i_1~i_2)^8 = \irelaxeddotmul_{8,16}(\lanes_{\I8X16}(c_1), \lanes_{\I8X16}(c_2)) \\ - \wedge & (j_1~j_2)^4 = \sats_{16}(i_1 + i_2)^8 \\ - \wedge & j^4 = \iadd_{32}(\extend^{s}_{16, 32}(j_1), \extend^{s}_{16, 32}(j_2))^4 \\ + \wedge & (j_1~j_2)^4 = \iaddsats_{16}(i_1, i_2)^8 \\ + \wedge & j^4 = \iadd_{32}(\extends_{16,32}(j_1), \extends_{16,32}(j_2))^4 \\ \wedge & k^4 = \lanes_{\I32X4}(c_3) \\ \wedge & l^4 = \iadd_{32}(j, k)^4 \\ \wedge & c = \lanes^{-1}_{\I32X4}(l^4)) diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 38b254491..44f823eef 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -88,8 +88,8 @@ Conventions: .. math:: \begin{array}{lll@{\qquad}l} - \satu_N(i) &=& 2^N-1 & (\iff i > 2^N-1)\\ \satu_N(i) &=& 0 & (\iff i < 0) \\ + \satu_N(i) &=& 2^N-1 & (\iff i > 2^N-1)\\ \satu_N(i) &=& i & (\otherwise) \\ \end{array} @@ -97,8 +97,8 @@ Conventions: .. math:: \begin{array}{lll@{\qquad}l} - \sats_N(i) &=& \signed_N^{-1}(-2^{N-1}) & (\iff i < -2^{N-1})\\ - \sats_N(i) &=& \signed_N^{-1}(2^{N-1}-1) & (\iff i > 2^{N-1}-1)\\ + \sats_N(i) &=& -2^{N-1} & (\iff i < -2^{N-1})\\ + \sats_N(i) &=& 2^{N-1}-1 & (\iff i > 2^{N-1}-1)\\ \sats_N(i) &=& i & (\otherwise) \end{array} @@ -860,11 +860,11 @@ The integer result of predicates -- i.e., :ref:`tests ` and :ref: * Let :math:`j` be the result of adding :math:`j_1` and :math:`j_2`. -* Return :math:`\sats_N(j)`. +* Return the value whose signed interpretation is :math:`\sats_N(j)`. .. math:: \begin{array}{lll@{\qquad}l} - \iaddsats_N(i_1, i_2) &=& \sats_N(\signed_N(i_1) + \signed_N(i_2)) + \iaddsats_N(i_1, i_2) &=& \signed_N^{-1}(\sats_N(\signed_N(i_1) + \signed_N(i_2))) \end{array} @@ -894,11 +894,11 @@ The integer result of predicates -- i.e., :ref:`tests ` and :ref: * Let :math:`j` be the result of subtracting :math:`j_2` from :math:`j_1`. -* Return :math:`\sats_N(j)`. +* Return the value whose signed interpretation is :math:`\sats_N(j)`. .. math:: \begin{array}{lll@{\qquad}l} - \isubsats_N(i_1, i_2) &=& \sats_N(\signed_N(i_1) - \signed_N(i_2)) + \isubsats_N(i_1, i_2) &=& \signed_N^{-1}(\sats_N(\signed_N(i_1) - \signed_N(i_2))) \end{array} @@ -922,11 +922,11 @@ The integer result of predicates -- i.e., :ref:`tests ` and :ref: :math:`\iq15mulrsats_N(i_1, i_2)` ................................. -* Return the result of :math:`\sats_N(\ishrs_N(i_1 \cdot i_2 + 2^{14}, 15))`. +* Return the whose signed interpretation is the result of :math:`\sats_N(\ishrs_N(i_1 \cdot i_2 + 2^{14}, 15))`. .. math:: \begin{array}{lll@{\qquad}l} - \iq15mulrsats_N(i_1, i_2) &=& \sats_N(\ishrs_N(i_1 \cdot i_2 + 2^{14}, 15)) + \iq15mulrsats_N(i_1, i_2) &=& \signed_N^{-1}(\sats_N(\ishrs_N(i_1 \cdot i_2 + 2^{14}, 15))) \end{array} @@ -1901,14 +1901,14 @@ Conversions * Else if :math:`z` is positive infinity, then return :math:`2^{N-1} - 1`. -* Else, return :math:`\sats_N(\trunc(z))`. +* Else, return the value whose signed interpretation is :math:`\sats_N(\trunc(z))`. .. math:: \begin{array}{lll@{\qquad}l} \truncsats_{M,N}(\pm \NAN(n)) &=& 0 \\ \truncsats_{M,N}(- \infty) &=& -2^{N-1} \\ \truncsats_{M,N}(+ \infty) &=& 2^{N-1}-1 \\ - \truncsats_{M,N}(z) &=& \sats_N(\trunc(z)) \\ + \truncsats_{M,N}(z) &=& \signed_N^{-1}(\sats_N(\trunc(z))) \\ \end{array} @@ -2006,11 +2006,11 @@ Conversions * Let :math:`j` be the :ref:`signed interpretation ` of :math:`i` of size :math:`M`. -* Return :math:`\sats_N(j)`. +* Return the value whose signed interpretation is :math:`\sats_N(j)`. .. math:: \begin{array}{lll@{\qquad}l} - \narrows_{M,N}(i) &=& \sats_N(\signed_M(i)) + \narrows_{M,N}(i) &=& \signed_N^{-1}(\sats_N(\signed_M(i))) \end{array} @@ -2220,7 +2220,7 @@ The implementation-specific behaviour of this operation is determined by the glo .. note:: Relaxed unsigned truncation is implementation-dependent for NaNs and out-of-range values. In the :ref:`deterministic profile `, - it behaves like regular :math:`\truncu`. + it behaves like regular :math:`\truncsatu`. .. _op-relaxed_trunc_s: @@ -2243,7 +2243,7 @@ The implementation-specific behaviour of this operation is determined by the glo .. note:: Relaxed signed truncation is implementation-dependent for NaNs and out-of-range values. In the :ref:`deterministic profile `, - it behaves like regular :math:`\truncs`. + it behaves like regular :math:`\truncsats`. .. _op-irelaxed_swizzle: From 2a30893e2868adbe0831af3c277728203bc70e8d Mon Sep 17 00:00:00 2001 From: Andreas Rossberg Date: Tue, 8 Oct 2024 11:45:33 +0200 Subject: [PATCH 116/117] [interpreter] Fix JS module invocation (#1829) --- interpreter/script/js.ml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/interpreter/script/js.ml b/interpreter/script/js.ml index ca25ac3eb..2e796f7e7 100644 --- a/interpreter/script/js.ml +++ b/interpreter/script/js.ml @@ -614,13 +614,16 @@ let rec of_result res = | EitherResult ress -> "[" ^ String.concat ", " (List.map of_result ress) ^ "]" +let of_module bs = + "module(" ^ of_bytes bs ^ ")" + let rec of_definition def = match def.it with - | Textual (m, _) -> of_bytes (Encode.encode m) - | Encoded (_, bs) -> of_bytes bs.it + | Textual (m, _) -> of_module (Encode.encode m) + | Encoded (_, bs) -> of_module bs.it | Quoted (_, s) -> try of_definition (snd (Parse.Module.parse_string ~offset:s.at s.it)) - with Parse.Syntax _ | Custom.Syntax _ -> of_bytes "" + with Parse.Syntax _ | Custom.Syntax _ -> of_module "" let of_instance env x_opt = "instance(" ^ of_mod_opt env x_opt ^ ")" @@ -628,7 +631,7 @@ let of_instance env x_opt = let of_wrapper env x_opt name wrap_action wrap_assertion at = let x = of_inst_opt env x_opt in let bs = wrap name wrap_action wrap_assertion at in - "call(instance(module(" ^ of_bytes bs ^ "), " ^ + "call(instance(" ^ of_module bs ^ ", " ^ "exports(" ^ x ^ ")), " ^ " \"run\", [])" let of_action env act = From 29b1fd4d3771b08d6a505fdce4bb2b3373dd7d61 Mon Sep 17 00:00:00 2001 From: Andreas Rossberg Date: Tue, 8 Oct 2024 15:41:38 +0200 Subject: [PATCH 117/117] [interpreter] Proper fix for JS conversion (#1832) --- interpreter/script/js.ml | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/interpreter/script/js.ml b/interpreter/script/js.ml index 2e796f7e7..adc072cb1 100644 --- a/interpreter/script/js.ml +++ b/interpreter/script/js.ml @@ -236,7 +236,7 @@ let env () : env = let current_mod (env : env) = "$$" ^ string_of_int env.current_mod let of_mod_opt (env : env) = function | None -> current_mod env - | Some x -> x.it + | Some x -> "$" ^ x.it let current_inst (env : env) = "$" ^ string_of_int env.current_inst let of_inst_opt (env : env) = function @@ -614,24 +614,18 @@ let rec of_result res = | EitherResult ress -> "[" ^ String.concat ", " (List.map of_result ress) ^ "]" -let of_module bs = - "module(" ^ of_bytes bs ^ ")" - let rec of_definition def = match def.it with - | Textual (m, _) -> of_module (Encode.encode m) - | Encoded (_, bs) -> of_module bs.it + | Textual (m, _) -> of_bytes (Encode.encode m) + | Encoded (_, bs) -> of_bytes bs.it | Quoted (_, s) -> try of_definition (snd (Parse.Module.parse_string ~offset:s.at s.it)) - with Parse.Syntax _ | Custom.Syntax _ -> of_module "" - -let of_instance env x_opt = - "instance(" ^ of_mod_opt env x_opt ^ ")" + with Parse.Syntax _ | Custom.Syntax _ -> of_bytes "" let of_wrapper env x_opt name wrap_action wrap_assertion at = let x = of_inst_opt env x_opt in let bs = wrap name wrap_action wrap_assertion at in - "call(instance(" ^ of_module bs ^ ", " ^ + "call(instance(module(" ^ of_bytes bs ^ "), " ^ "exports(" ^ x ^ ")), " ^ " \"run\", [])" let of_action env act = @@ -680,9 +674,9 @@ let of_assertion env ass = | AssertInvalidCustom (def, _) -> "assert_invalid_custom(" ^ of_definition def ^ ");" | AssertUnlinkable (x_opt, _) -> - "assert_unlinkable(" ^ of_instance env x_opt ^ ");" + "assert_unlinkable(" ^ of_mod_opt env x_opt ^ ");" | AssertUninstantiable (x_opt, _) -> - "assert_uninstantiable(" ^ of_instance env x_opt ^ ");" + "assert_uninstantiable(" ^ of_mod_opt env x_opt ^ ");" | AssertReturn (act, ress) -> of_assertion' env act "assert_return" (List.map of_result ress) (Some (assert_return ress)) @@ -705,7 +699,7 @@ let of_command env cmd = | Quoted (_, s) -> unquote (snd (Parse.Module.parse_string ~offset:s.at s.it)) in bind_mod env x_opt (unquote def); - "let " ^ current_mod env ^ " = " ^ of_definition def ^ ";\n" ^ + "let " ^ current_mod env ^ " = module(" ^ of_definition def ^ ");\n" ^ (if x_opt = None then "" else "let " ^ of_mod_opt env x_opt ^ " = " ^ current_mod env ^ ";\n") | Instance (x1_opt, x2_opt) ->