diff --git a/.github/workflows/gds.yaml b/.github/workflows/gds.yaml index cb22e455..f41c860d 100644 --- a/.github/workflows/gds.yaml +++ b/.github/workflows/gds.yaml @@ -25,18 +25,6 @@ jobs: - name: Run Tiny Tapeout Precheck uses: TinyTapeout/tt-gds-action/precheck@tt09 - gl_test: - needs: gds - runs-on: ubuntu-latest - steps: - - name: checkout repo - uses: actions/checkout@v4 - with: - submodules: recursive - - - name: GL test - uses: TinyTapeout/tt-gds-action/gl_test@tt09 - viewer: needs: gds runs-on: ubuntu-latest diff --git a/.github/workflows/test.yaml b/.github/workflows/wokwi_test.yaml similarity index 61% rename from .github/workflows/test.yaml rename to .github/workflows/wokwi_test.yaml index 8b1efcbf..93eb472b 100644 --- a/.github/workflows/test.yaml +++ b/.github/workflows/wokwi_test.yaml @@ -1,7 +1,7 @@ -name: test +name: wokwi_test on: [push, workflow_dispatch] jobs: - test: + wokwi_test: runs-on: ubuntu-latest steps: - name: Checkout repo @@ -9,6 +9,13 @@ jobs: with: submodules: recursive + - name: Checkout tt-support-tools repo + uses: actions/checkout@v4 + with: + repository: TinyTapeout/tt-support-tools + path: tt + ref: tt09 + - name: Install iverilog shell: bash run: sudo apt-get update && sudo apt-get install -y iverilog @@ -21,9 +28,21 @@ jobs: - name: Install Python packages shell: bash - run: pip install -r test/requirements.txt + run: | + pip install -r test/requirements.txt + pip install -r tt/requirements.txt + + - name: Fetch the truth table + run: ./tt/tt_tool.py --create-user-config + + - name: Check for truth table existence + id: check_files + uses: andstor/file-existence-action@v3 + with: + files: "test/truthtable.md" - name: Run tests + if: steps.check_files.outputs.files_exists == 'true' run: | cd test make clean @@ -43,5 +62,5 @@ jobs: with: name: test-vcd path: | - test/tb.vcd + test/*.vcd test/results.xml diff --git a/README.md b/README.md index 68ba6ed4..4269f8f9 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ -![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) ![](../../workflows/fpga/badge.svg) +![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/wokwi_test/badge.svg) ![](../../workflows/fpga/badge.svg) -# Tiny Tapeout Verilog Project Template +# Tiny Tapeout Wokwi Project Template - [Read the documentation for project](docs/info.md) @@ -10,14 +10,11 @@ Tiny Tapeout is an educational project that aims to make it easier and cheaper t To learn more and get started, visit https://tinytapeout.com. -## Set up your Verilog project +## Wokwi Projects -1. Add your Verilog files to the `src` folder. -2. Edit the [info.yaml](info.yaml) and update information about your project, paying special attention to the `source_files` and `top_module` properties. If you are upgrading an existing Tiny Tapeout project, check out our [online info.yaml migration tool](https://tinytapeout.github.io/tt-yaml-upgrade-tool/). -3. Edit [docs/info.md](docs/info.md) and add a description of your project. -4. Adapt the testbench to your design. See [test/README.md](test/README.md) for more information. +Edit the [info.yaml](info.yaml) and change the `wokwi_id` to the ID of your Wokwi project. You can find the ID in the URL of your project, it's the big number after `wokwi.com/projects/`. -The GitHub action will automatically build the ASIC files using [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/). +The GitHub action will automatically fetch the digital netlist from Wokwi and build the ASIC files. ## Enable GitHub actions to build the results page diff --git a/info.yaml b/info.yaml index 50bb751a..f6c3071f 100644 --- a/info.yaml +++ b/info.yaml @@ -1,23 +1,16 @@ -# Tiny Tapeout project information +# Tiny Tapeout project information (Wokwi project) project: + wokwi_id: 0 # Set this to the ID of your Wokwi project (the number from the project's URL) title: "" # Project title author: "" # Your name discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) description: "" # One line description of what your project does - language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc + language: "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable) # How many tiles your design occupies? A single tile is about 167x108 uM. tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2 - # Your top module name must start with "tt_um_". Make it unique by including your github username: - top_module: "tt_um_example" - - # List your project's source files here. - # Source files must be in ./src and you must list each source file separately, one per line. - # Don't forget to also update `PROJECT_SOURCES` in test/Makefile. - source_files: - - "project.v" # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. pinout: diff --git a/src/cells.v b/src/cells.v new file mode 100644 index 00000000..920f0d42 --- /dev/null +++ b/src/cells.v @@ -0,0 +1,102 @@ +/* +This file provides the mapping from the Wokwi modules to Verilog HDL. + +It's only needed for Wokwi designs. +*/ + +`define default_netname none + +module buffer_cell ( + input wire in, + output wire out + ); + assign out = in; +endmodule + +module and_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a & b; +endmodule + +module or_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a | b; +endmodule + +module xor_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = a ^ b; +endmodule + +module nand_cell ( + input wire a, + input wire b, + output wire out + ); + + assign out = !(a&b); +endmodule + +module not_cell ( + input wire in, + output wire out + ); + + assign out = !in; +endmodule + +module mux_cell ( + input wire a, + input wire b, + input wire sel, + output wire out + ); + + assign out = sel ? b : a; +endmodule + +module dff_cell ( + input wire clk, + input wire d, + output reg q, + output wire notq + ); + + assign notq = !q; + always @(posedge clk) + q <= d; + +endmodule + +module dffsr_cell ( + input wire clk, + input wire d, + input wire s, + input wire r, + output reg q, + output wire notq + ); + + assign notq = !q; + + always @(posedge clk or posedge s or posedge r) begin + if (r) + q <= 0; + else if (s) + q <= 1; + else + q <= d; + end +endmodule diff --git a/src/project.v b/src/project.v deleted file mode 100644 index cd6f7406..00000000 --- a/src/project.v +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2024 Your Name - * SPDX-License-Identifier: Apache-2.0 - */ - -`default_nettype none - -module tt_um_example ( - input wire [7:0] ui_in, // Dedicated inputs - output wire [7:0] uo_out, // Dedicated outputs - input wire [7:0] uio_in, // IOs: Input path - output wire [7:0] uio_out, // IOs: Output path - output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) - input wire ena, // always 1 when the design is powered, so you can ignore it - input wire clk, // clock - input wire rst_n // reset_n - low to reset -); - - // All output pins must be assigned. If not used, assign to 0. - assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in - assign uio_out = 0; - assign uio_oe = 0; - - // List all unused inputs to prevent warnings - wire _unused = &{ena, clk, rst_n, 1'b0}; - -endmodule diff --git a/test/README.md b/test/README.md deleted file mode 100644 index 172327f0..00000000 --- a/test/README.md +++ /dev/null @@ -1,31 +0,0 @@ -# Sample testbench for a Tiny Tapeout project - -This is a sample testbench for a Tiny Tapeout project. It uses [cocotb](https://docs.cocotb.org/en/stable/) to drive the DUT and check the outputs. -See below to get started or for more information, check the [website](https://tinytapeout.com/hdl/testing/). - -## Setting up - -1. Edit [Makefile](Makefile) and modify `PROJECT_SOURCES` to point to your Verilog files. -2. Edit [tb.v](tb.v) and replace `tt_um_example` with your module name. - -## How to run - -To run the RTL simulation: - -```sh -make -B -``` - -To run gatelevel simulation, first harden your project and copy `../runs/wokwi/results/final/verilog/gl/{your_module_name}.v` to `gate_level_netlist.v`. - -Then run: - -```sh -make -B GATES=yes -``` - -## How to view the VCD file - -```sh -gtkwave tb.vcd tb.gtkw -``` diff --git a/test/tb.gtkw b/test/tb.gtkw deleted file mode 100644 index c92ca3ce..00000000 --- a/test/tb.gtkw +++ /dev/null @@ -1,39 +0,0 @@ -[*] -[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Mon Nov 20 16:00:28 2023 -[*] -[dumpfile] "/home/uri/p/tt-new-template-proto/test/tb.vcd" -[dumpfile_mtime] "Mon Nov 20 15:58:34 2023" -[dumpfile_size] 1110 -[savefile] "/home/uri/p/tt-new-template-proto/test/tb.gtkw" -[timestart] 0 -[size] 1376 600 -[pos] -1 -1 -*-24.534533 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] tb. -[sst_width] 297 -[signals_width] 230 -[sst_expanded] 1 -[sst_vpaned_height] 158 -@28 -tb.user_project.ena -@29 -tb.user_project.clk -@28 -tb.user_project.rst_n -@200 --Inputs -@22 -tb.user_project.ui_in[7:0] -@200 --Bidirectional Pins -@22 -tb.user_project.uio_in[7:0] -tb.user_project.uio_oe[7:0] -tb.user_project.uio_out[7:0] -@200 --Output Pins -@22 -tb.user_project.uo_out[7:0] -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/test/tb.v b/test/tb.v deleted file mode 100644 index 2fc848c6..00000000 --- a/test/tb.v +++ /dev/null @@ -1,45 +0,0 @@ -`default_nettype none -`timescale 1ns / 1ps - -/* This testbench just instantiates the module and makes some convenient wires - that can be driven / tested by the cocotb test.py. -*/ -module tb (); - - // Dump the signals to a VCD file. You can view it with gtkwave. - initial begin - $dumpfile("tb.vcd"); - $dumpvars(0, tb); - #1; - end - - // Wire up the inputs and outputs: - reg clk; - reg rst_n; - reg ena; - reg [7:0] ui_in; - reg [7:0] uio_in; - wire [7:0] uo_out; - wire [7:0] uio_out; - wire [7:0] uio_oe; - - // Replace tt_um_example with your module name: - tt_um_example user_project ( - - // Include power ports for the Gate Level test: -`ifdef GL_TEST - .VPWR(1'b1), - .VGND(1'b0), -`endif - - .ui_in (ui_in), // Dedicated inputs - .uo_out (uo_out), // Dedicated outputs - .uio_in (uio_in), // IOs: Input path - .uio_out(uio_out), // IOs: Output path - .uio_oe (uio_oe), // IOs: Enable path (active high: 0=input, 1=output) - .ena (ena), // enable - goes high when design is selected - .clk (clk), // clock - .rst_n (rst_n) // not reset - ); - -endmodule diff --git a/test/test.py b/test/test.py deleted file mode 100644 index fa7f92c8..00000000 --- a/test/test.py +++ /dev/null @@ -1,40 +0,0 @@ -# SPDX-FileCopyrightText: © 2024 Tiny Tapeout -# SPDX-License-Identifier: Apache-2.0 - -import cocotb -from cocotb.clock import Clock -from cocotb.triggers import ClockCycles - - -@cocotb.test() -async def test_project(dut): - dut._log.info("Start") - - # Set the clock period to 10 us (100 KHz) - clock = Clock(dut.clk, 10, units="us") - cocotb.start_soon(clock.start()) - - # Reset - dut._log.info("Reset") - dut.ena.value = 1 - dut.ui_in.value = 0 - dut.uio_in.value = 0 - dut.rst_n.value = 0 - await ClockCycles(dut.clk, 10) - dut.rst_n.value = 1 - - dut._log.info("Test project behavior") - - # Set the input values you want to test - dut.ui_in.value = 20 - dut.uio_in.value = 30 - - # Wait for one clock cycle to see the output values - await ClockCycles(dut.clk, 1) - - # The following assersion is just an example of how to check the output values. - # Change it to match the actual expected output of your module: - assert dut.uo_out.value == 50 - - # Keep testing the module by changing the input values, waiting for - # one or more clock cycles, and asserting the expected output values.