From 0e16c6a0e201e1a491f092c510cf348ad728454a Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 6 Feb 2023 16:02:04 +0100 Subject: [PATCH 1/9] [VPTOOL] Use Ruamel Yaml to handle Yaml I/O. Set up infra for Yaml output. * tools/vptool/vptool/vp.py (toplevel): Import Ruamel Yaml instead of the PyYaml flavor. Add skeleton of support for *existing* DVplan object classes. (MyMain.save_db): Update the Git SHA1 signatures on all IPs, not only on those currently unlocked (all IPs are manipulated by the current VPTOOL version, whether saved or not.) Update Pickle protocol version to v4 (default in Python 3.6+). Add stubs/comments for Yaml output. (MyMain.load_db_quiet): Add stubs/comments for Yaml input. (MyMain.lock_ip): Use Pickle protocol v4. (MyMain.lock_all_ip): Ditto. (MyMain.save_personalization): Ditto. (toplevel): Use Ruamel Yaml engine to load configuration file using the safe loader. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp.py | 71 ++++++++++++++++++++++++++++----------- 1 file changed, 52 insertions(+), 19 deletions(-) diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index a782de3eec..a4a1e70983 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -20,18 +20,25 @@ import pickle from collections import OrderedDict +# Use Ruamel YAML support +from ruamel.yaml import YAML, yaml_object +# global db_yaml_engine +# db_yaml_engine = YAML(typ='rt') + # import cPickle as pickle # Configuration (env + Python + Yaml) is imported indirectly via vp_pack. from vp_pack import * + +# db_yaml_engine.register_class(Item) +# db_yaml_engine.register_class(Prop) +# db_yaml_engine.register_class(Ip) + import os, sys, pwd, glob, subprocess from optparse import OptionParser, Option from PIL import Image, ImageTk import shutil import hashlib -# PyYAML import: Use C backend (libyaml) if available. -from yaml import load, dump - try: from yaml import CLoader as Loader, CDumper as Dumper except ImportError: @@ -1953,16 +1960,16 @@ def save_db(self, save_as="no"): save_dir = os.path.dirname(vp_config.SAVED_DB_LOCATION) saved_ip_str = "" for ip_elt in pickle_ip_list: + # Sign the IP with the current SHA1 of VPTOOL. + ip_elt[1].vptool_gitrev = self.vptool_gitrev + ip_elt[1].io_fmt_gitrev = vp_config.io_fmt_gitrev + ip_elt[1].config_gitrev = vp_config.config_gitrev + ip_elt[1].ymlcfg_gitrev = vp_config.yaml_config[ + "yaml_cfg_gitrev" + ] # Save individual IPs only if locked by user. if self.is_locked_by_user(current_ip_name=ip_elt[1].name): saved_ip_str += "\n " + ip_elt[1].name - # Sign the IP with the current SHA1 of VPTOOL. - ip_elt[1].vptool_gitrev = self.vptool_gitrev - ip_elt[1].io_fmt_gitrev = vp_config.io_fmt_gitrev - ip_elt[1].config_gitrev = vp_config.config_gitrev - ip_elt[1].ymlcfg_gitrev = vp_config.yaml_config[ - "yaml_cfg_gitrev" - ] with open( save_dir + "/VP_IP" @@ -1970,7 +1977,21 @@ def save_db(self, save_as="no"): + ".pck", "wb", ) as output: - pickle.dump(ip_elt, output, 0) + pickle.dump(ip_elt, output, 4) + # TODO: Add translation of pickle_ip_list to new-gen + # types *HERE*, after emitting Pickle. + # Emit the Yaml output from the fixed structures, + # skipping pickled ones. + # Write yaml output + #with open( + # save_dir + # + "/VP_IP" + # + str(ip_elt[1].ip_num).zfill(3) + # + ".yml", + # "wb", + #) as output: + # db_yaml_engine.dump(ip_elt[1], output) + if saved_ip_str: tkinter.messagebox.showinfo( "Info", @@ -1987,10 +2008,11 @@ def save_db(self, save_as="no"): % vp_config.yaml_config["gui"]["ip"]["label"].lower(), ) else: + # ZC FIXME Add support for Yaml in non-split-save mode. with open(vp_config.SAVED_DB_LOCATION, "wb") as output: - pickle.dump(len(pickle_ip_list), output, 0) + pickle.dump(len(pickle_ip_list), output, 4) for ip_elt in pickle_ip_list: - pickle.dump(ip_elt, output, 0) + pickle.dump(ip_elt, output, 4) self.prep_db_import() # update_ip_widget() self.update_all_item_target_list() @@ -2058,6 +2080,9 @@ def load_db_quiet(self): # print("---INFO: Loading "+filename) with open(filename, "rb") as input: pickle_ip_list.append(pickle.load(input)) + #for filename in glob.glob(dir_to_load + "/VP_IP*yml"): + # with open(filename, "rb") as input: + # pickle_ip_list.append(db_yaml_engine.load(input)) if pickle_ip_list: # Find the lowest ip_num that can be used for newly created IPs. # It has to be higher than the highest existing ip_num. @@ -2065,6 +2090,7 @@ def load_db_quiet(self): ip_num_next = 1 + max( [ (lambda e: e if isinstance(e, int) else int(e, base=10))( + #elt.ip_num # Yaml !!omap mode: list of objects elt[1].ip_num ) for elt in pickle_ip_list @@ -2083,6 +2109,12 @@ def load_db_quiet(self): for dummy in range(ip_num_next): pickle_ip_list.append(pickle.load(input)) # change list to dict + # Yaml mode: !!omap produced a list of elts + #for ip_elt in pickle_ip_list: + # self.ip_list[ip_elt.name] = ip_elt + # # Seems pickle doesn't restore class attribute. Done manually here for IP + # self.ip_list[ip_elt.name].__class__._ip_count = ip_num_next + # Pickle mode: list of objects is a list of mappings for ip_key, ip_elt in pickle_ip_list: self.ip_list[ip_key] = ip_elt # Seems pickle doesn't restore class attribute. Done manually here for IP @@ -2145,7 +2177,7 @@ def lock_ip(self): LOCKED_IP_DICT[current_ip_name] = pwd.getpwuid(os.getuid()).pw_name try: with open(vp_config.LOCKED_IP_LOCATION, "wb") as output: - pickle.dump(LOCKED_IP_DICT, output, 0) + pickle.dump(LOCKED_IP_DICT, output, 4) self.update_ip_widget() except Exception as e: print( @@ -2168,7 +2200,7 @@ def lock_all_ip(self): LOCKED_IP_DICT[current_ip_name] = pwd.getpwuid(os.getuid()).pw_name try: with open(vp_config.LOCKED_IP_LOCATION, "wb") as output: - pickle.dump(LOCKED_IP_DICT, output, 0) + pickle.dump(LOCKED_IP_DICT, output, 4) self.update_ip_widget() except Exception as e: print( @@ -2247,9 +2279,9 @@ def save_personalization(self): if os.path.exists(sys.argv[0]): preference_file = os.path.dirname(sys.argv[0]) + "/" + PERSO_FILE with open(preference_file, "wb") as output: - pickle.dump(BG_COLOR, output, 0) - pickle.dump(EDITOR, output, 0) - pickle.dump(self.verif_menu.enable_image_panel.get(), output, 0) + pickle.dump(BG_COLOR, output, 4) + pickle.dump(EDITOR, output, 4) + pickle.dump(self.verif_menu.enable_image_panel.get(), output, 4) def change_gui_color(self): global BG_COLOR @@ -2455,7 +2487,8 @@ def __generate_option_parser(): # Load YAML configuration if available. try: with open(os.path.join(os.path.dirname(__file__), YAML_CONFIG_FILE), "r") as f: - vp_config.init_yaml_config(load(f, Loader=Loader)) + config_yaml_engine = YAML(typ='safe') + vp_config.init_yaml_config(config_yaml_engine.load(f)) # print("YAML config = \n" + dump(vp_config.yaml_config, Dumper=Dumper)) except Exception as e: print( From 64c0fe5b249794ef41042e1805bb27905ef24a45 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Tue, 7 Feb 2023 12:31:44 +0100 Subject: [PATCH 2/9] [VPTOOL] Add transcoding of legacy structures. Output new structs as Yaml. * tools/vptool/vptool/vp.py (db_yaml_engine): New global object. Register VerifItem, Subfeature and Feature as Yaml-supported classes. (MyMain.save_db): Dump new-style data structures as Yaml for all Ip objects. (MyMain.load_db_quiet): Update Yaml-relaed comments. * tools/vptool/vptool/vp_pack.py (toplevel): Import OrderedDict. (VerifItem): New class. (Item.to_VerifItem): Add translation method legacy->new for verif items. (Subfeature): New class. (Prop.to_Subfeature): Add translation method legacy->new for subfeatures. (Feature): New class. (Ip.to_Feature): Add translation method legacy->new for features. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp.py | 28 ++--- tools/vptool/vptool/vp_pack.py | 202 +++++++++++++++++++++++++++++++++ 2 files changed, 216 insertions(+), 14 deletions(-) diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index a4a1e70983..900ed0905e 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -22,16 +22,16 @@ # Use Ruamel YAML support from ruamel.yaml import YAML, yaml_object -# global db_yaml_engine -# db_yaml_engine = YAML(typ='rt') +global db_yaml_engine +db_yaml_engine = YAML(typ='rt') # import cPickle as pickle # Configuration (env + Python + Yaml) is imported indirectly via vp_pack. from vp_pack import * -# db_yaml_engine.register_class(Item) -# db_yaml_engine.register_class(Prop) -# db_yaml_engine.register_class(Ip) +db_yaml_engine.register_class(VerifItem) +db_yaml_engine.register_class(Subfeature) +db_yaml_engine.register_class(Feature) import os, sys, pwd, glob, subprocess from optparse import OptionParser, Option @@ -1983,14 +1983,14 @@ def save_db(self, save_as="no"): # Emit the Yaml output from the fixed structures, # skipping pickled ones. # Write yaml output - #with open( - # save_dir - # + "/VP_IP" - # + str(ip_elt[1].ip_num).zfill(3) - # + ".yml", - # "wb", - #) as output: - # db_yaml_engine.dump(ip_elt[1], output) + with open( + save_dir + + "/VP_IP" + + str(ip_elt[1].ip_num).zfill(3) + + "_new_types.yml", + "wb", + ) as output: + db_yaml_engine.dump(ip_elt[1].to_Feature(), output) if saved_ip_str: tkinter.messagebox.showinfo( @@ -2109,7 +2109,7 @@ def load_db_quiet(self): for dummy in range(ip_num_next): pickle_ip_list.append(pickle.load(input)) # change list to dict - # Yaml mode: !!omap produced a list of elts + # Yaml mode: !!omap yields a list of elts when loaded. #for ip_elt in pickle_ip_list: # self.ip_list[ip_elt.name] = ip_elt # # Seems pickle doesn't restore class attribute. Done manually here for IP diff --git a/tools/vptool/vptool/vp_pack.py b/tools/vptool/vptool/vp_pack.py index 2f6f9e7bc8..afcf27b5e9 100755 --- a/tools/vptool/vptool/vp_pack.py +++ b/tools/vptool/vptool/vp_pack.py @@ -10,6 +10,7 @@ import sys, os from datetime import datetime +from collections import OrderedDict import re # Load the configuration associated with the current platform @@ -47,6 +48,61 @@ def normalize_tag(l): ##################################### ##### Class Definition + +class VerifItem: + """ + A Verification Item captures a specific aspect of a design that + can be individually verified. + Verification Items are intended to be instantiated in a Subfeature + class which groups Verification Items related to a given property of + the design, e.g. to one instruction of an Instruction Set. + """ + # Class variable: Names of Python attributes of a Verification Item that + # can be free-form strings and have default cue strings defined. + attr_names = [ + "description", + "reqt_doc", # Note the 'd' in '_doc'... + "verif_goals", + "coverage_loc", + "comments" + ] + # Class variable: Matching names in Yaml-based GUI configuration + gui_fields = [ + "feature_descr", + "requirement_loc", + "verif_goals", + "coverage_loc", + "comments", + ] + + def __init__(self, name=0, tag="", description=""): + # Identifier of the Item, used in display lists. + self.name = name + # Unique tag of the Verificataion Item (never to be reused). + self.tag = tag + # Description of the property to be verified. + self.description = description + # Document containing the corresponding requirement + self.reqt_doc = "" + # Pointers into the document + self.ref_mode = "page" + self.ref_page = "" + self.ref_section = "" + self.ref_viewer = "firefox" + # Goals of verification + self.verif_goals = "" + # Pointer to coverage data + self.coverage_loc = "" + # Pass/fail criteria + self.pfc = -1 # None selected, must choose + # Test type + self.test_type = -1 # None selected, must choose + # Coverage method + self.cov_method = -1 # None selected, must choose + # Applicable cores + self.cores = -1 # By default, a new Verif Item is applicable to all cores. + self.comments = "" + class Item: """ An item defines a specific case to test depending on its parent property @@ -95,6 +151,27 @@ def __init__(self, item_ref_name=0, tag="", description="", purpose=""): self.rfu_dict = {} # used as lock. will be updated with class update self.rfu_dict["lock_status"] = 0 + def to_VerifItem(self): + """ + Convert an Item to a VerifItem. Keep only the information that's needed. + """ + result = VerifItem(self.name, self.tag, self.description) + result.reqt_doc = self.purpose + # These attributes may be missing on objects coming from older VPTOOL versions. + for attr in ["ref_mode", "ref_page", "ref_section", "ref_viewer"]: + if hasattr(self, attr): + setattr(result, attr, getattr(self, attr)) + else: + setattr(result, attr, "") + result.verif_goals = self.verif_goals + result.pfc = self.pfc + result.test_type = self.test_type + result.cov_method = self.cov_method + result.cores = self.cores + result.coverage_loc = self.coverage_loc + result.comments = self.comments + return result + def attrval2str(self, attr): if attr == "cores" and "cores" in vp_config.yaml_config: # 'cores' are at toplevel of the Yaml config and the attr value is a bitmap. @@ -198,6 +275,43 @@ def prep_to_save(self): self.tag = normalize_tag(self.tag) +class Subfeature: + """ + A Subfeature is a subset of a major design feature that is characterized + by a distinctive property. Therefore, the verification items related to + that property are closely related and are grouped together into a list + associated with the Subfeature. + """ + def __init__(self, name="", tag=""): + # Name of the subfeature + self.name = name + # Tag of the subfeature: Must be unique across all subfeatures. + self.tag = tag + # Index of the next item to be added (MUST INCREASE ON EVERY ADDITION!) + self.next_elt_id = 0 + # List of Verification Items in this feature: an OrderedDict. + self.items = OrderedDict() + + def __str__(self): + return format("### Sub-feature: %s\n\n" % (self.name)) + + def add_item(self, tag, description=""): # adds a Verification Item to subfeature + new_item = VerifItem( + str(self.next_elt_id).zfill(3), + tag=tag + "_I" + str(self.next_elt_id).zfill(3), + description=description, + ) + self.items[str(self.next_elt_id).zfill(3)] = new_item + self.next_elt_id += 1 + # Return a ref to the newly created item. + return new_item + + def del_item(self, index): # remove a verification item from the subfeature + del self.items[index] + + def get_item_names(self): + return [item.name for item in self.items.values()] + class Prop: """ A Property defines a specific behaviour or an IP section, to be tested/verified @@ -219,6 +333,24 @@ def __init__(self, name="", tag="", wid_order=0): self.rfu_list_2 = [] self.rfu_dict = {} + def to_Subfeature(self): + """ + Convert a legacy Prop to a Subfeature, transfer only the fields that are required. + """ + result = Subfeature(self.name, self.tag) + # 'next_elt_id' needs extra care as 'item_count' assumes a contiguous + # numbering of Items in Prop and will be inconsistent if items are removed. + # Computing the max of item IDs is not reliable either in case the last + # item was removed. + result.next_elt_id = self.item_count + max_item_id = max([int(elt[1].name) for elt in (self.item_list if self.item_list else self.rfu_list)]) + if max_item_id >= self.item_count: + raise ValueError((self.item_count, max_item_id)) + result.next_elt_id = 1 + max_item_id + translated_items = [[elt[0], elt[1].to_VerifItem()] for elt in (self.item_list if self.item_list else self.rfu_list)] + result.items = OrderedDict(translated_items) + return result + def __str__(self): return format("### Sub-feature: %s\n\n" % (self.name)) @@ -315,6 +447,64 @@ def lock_items(self): for item in list(self.item_list.values()): item.lock() +class Feature: + """ + A Feature is a major group of design properties, for example + a class of instructions or an operation mode of an interface. + """ + # Class variable: highest Feature ID seen so far. + _highest_id = -1 + + def __init__(self, name="", id=0): + # Index of next subfeature to add (MUST ALWAYS GROW upon adding subfeatures!) + self.next_elt_id = 0 + # Name of the Feature + self.name = name + # Numerical ID of the Feature: Use the highest known value PLUS ONE + # unless explicitly given (e.g., when converting Ip objects). + if id != 0: + if id > self.__class__._highest_id: + self.__class__._highest_id = id + self.id = id + else: + raise ValueError((id, self.__class__._highest_id)) + else: + self.__class__._highest_id += 1 + self.id = self.__class__._highest_id + # Index of the Feature (for display ordering) + #self.index = index + # List of subfeatures + self.subfeatures = OrderedDict() + + def __str__(self): + return format("## Feature: %s\n\n" % (self.name)) + + def add_subfeature(self, name, tag=""): + """ + Add a subfeature of the current feature. + """ + if name in self.subfeatures.keys(): + print("Subfeature '%s' already exists in Feature '%s'!" % (name, self.name)) + feedback = 0 + else: + name = remove_non_ascii(name) + subfeature_name = str(self.next_elt_id).zfill(3) + "_" + str(name) + self.next_elt_id += 1 + self.subfeatures[name] = Subfeature( + subfeature_name, + tag="VP_" + + vp_config.PROJECT_IDENT + + "_F" + + str(self.ip_num).zfill(3) + + "_S" + + str(self.prop_count).zfill(3), + ) + feedback = self.subfeatures[subfeature_name].tag + self._count += 1 + return (feedback, subfeature_name) + + def del_subfeature(self, name): + del self.subfeatures[str(name)] class Ip: """ @@ -341,6 +531,18 @@ def __init__(self, name="", index=""): self.rfu_list_0 = [] self.rfu_list_1 = [] + def to_Feature(self): + """ + Convert an Ip to a Feature. + """ + result = Feature(self.name, self.ip_num) + # Next_elf_it needs extra care as it is derived from the length of the list + # of Properties / Subfeatures. + result.next_elt_id = self.prop_count + translated_subfeatures = [[elt[0], elt[1].to_Subfeature()] for elt in (self.prop_list if self.prop_list else self.rfu_list)] + result.subfeatures = OrderedDict(translated_subfeatures) + return result + def __str__(self): return format("## Feature: %s\n\n" % (self.name)) From 364fd25fd40fdfb10cc337792d65d0749612369c Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Tue, 7 Feb 2023 17:30:47 +0100 Subject: [PATCH 3/9] [VPTOOL] Save Git SHA1s in Yaml data. Add Yaml->legacy translation path. * tools/vptool/vptool/vp_pack.py (VerifItem.__init__): Reorder attribs to better match GUI layout. Update comments. (VerifItem.to_Item): New. (Item.to_VerifItem): Factorize identical attribute assignment. (Subfeature.__init__): Add 'display_order' attrib. (Subfeature.to_Prop): New. (Prop.to_Subfeature): Propagage 'wid_order' attrib as 'display_order'. (Feature.__init__): Add 'display_order' and VPTOOL Git SHA1 attribs. (Feature.to_Ip): New. (Ip.__init__): Add VPTOOL Git SHA1 attribs. (Ip.to_Feature): Copy Git SHA1 attribs. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp_pack.py | 72 ++++++++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 13 deletions(-) diff --git a/tools/vptool/vptool/vp_pack.py b/tools/vptool/vptool/vp_pack.py index afcf27b5e9..d9d5324a10 100755 --- a/tools/vptool/vptool/vp_pack.py +++ b/tools/vptool/vptool/vp_pack.py @@ -82,17 +82,15 @@ def __init__(self, name=0, tag="", description=""): self.tag = tag # Description of the property to be verified. self.description = description - # Document containing the corresponding requirement + # Document containing the corresponding requirement or design spec. self.reqt_doc = "" - # Pointers into the document + # Viewing information for the requirement/design document. self.ref_mode = "page" self.ref_page = "" self.ref_section = "" self.ref_viewer = "firefox" # Goals of verification self.verif_goals = "" - # Pointer to coverage data - self.coverage_loc = "" # Pass/fail criteria self.pfc = -1 # None selected, must choose # Test type @@ -101,8 +99,24 @@ def __init__(self, name=0, tag="", description=""): self.cov_method = -1 # None selected, must choose # Applicable cores self.cores = -1 # By default, a new Verif Item is applicable to all cores. + # Pointer to coverage data + self.coverage_loc = "" + # User comments for the verification item self.comments = "" + def to_Item(self): + """ + Convert a VerifItem to a legacy-style Item object. + """ + result = Item(self.name, self.tag, self.description, self.reqt_doc) + # These attributes are a 1-to-1 match. + for attr in [ + "ref_mode", "ref_page", "ref_section", "ref_viewer", "verif_goals", + "pfc", "test_type", "cov_method", "cores", "coverage_loc", "comments", + ]: + setattr(result, attr, getattr(self, attr)) + return result + class Item: """ An item defines a specific case to test depending on its parent property @@ -163,13 +177,12 @@ def to_VerifItem(self): setattr(result, attr, getattr(self, attr)) else: setattr(result, attr, "") - result.verif_goals = self.verif_goals - result.pfc = self.pfc - result.test_type = self.test_type - result.cov_method = self.cov_method - result.cores = self.cores - result.coverage_loc = self.coverage_loc - result.comments = self.comments + # The following attributes were already mandatory in older RISC-V VPTOOL versions. + for attr in [ + "verif_goals", + "pfc", "test_type", "cov_method", "cores", "coverage_loc", "comments", + ]: + setattr(result, attr, getattr(self, attr)) return result def attrval2str(self, attr): @@ -289,6 +302,8 @@ def __init__(self, name="", tag=""): self.tag = tag # Index of the next item to be added (MUST INCREASE ON EVERY ADDITION!) self.next_elt_id = 0 + # Display order of the Subfeature + self.display_order = 0 # List of Verification Items in this feature: an OrderedDict. self.items = OrderedDict() @@ -312,6 +327,14 @@ def del_item(self, index): # remove a verification item from the subfeature def get_item_names(self): return [item.name for item in self.items.values()] + def to_Prop(self): + """ + Convert a Subfeature into legacy-stype Prop object. + """ + result = Prop(self.name, self.tag, self.display_order) + result.list_of_items = [[elt[0], elt[1].to_Item()] for elt in self.items.items()] + return result + class Prop: """ A Property defines a specific behaviour or an IP section, to be tested/verified @@ -347,6 +370,7 @@ def to_Subfeature(self): if max_item_id >= self.item_count: raise ValueError((self.item_count, max_item_id)) result.next_elt_id = 1 + max_item_id + result.display_order = self.wid_order translated_items = [[elt[0], elt[1].to_VerifItem()] for elt in (self.item_list if self.item_list else self.rfu_list)] result.items = OrderedDict(translated_items) return result @@ -471,10 +495,14 @@ def __init__(self, name="", id=0): else: self.__class__._highest_id += 1 self.id = self.__class__._highest_id - # Index of the Feature (for display ordering) - #self.index = index + # Display order of the Feature + self.display_order = self.id # List of subfeatures self.subfeatures = OrderedDict() + self.vptool_gitrev = '' + self.io_fmt_gitrev = '' + self.config_gitrev = '' + self.ymlcfg_gitrev = '' def __str__(self): return format("## Feature: %s\n\n" % (self.name)) @@ -506,6 +534,17 @@ def add_subfeature(self, name, tag=""): def del_subfeature(self, name): del self.subfeatures[str(name)] + def to_Ip(self): + """ + Convert a Feature to a legacy-stype Ip. + """ + result = Ip(self.name) + result.wid_order = self.display_order + result.prop_list = [[elt[0], elt[1].toSubfeature()] for elt in self.subfeatures.items()] + for attr in ["vptool_gitrev", "io_fmt_gitrev", "config_gitrev", "ymlcfg_gitrev"]: + setattr(result, attr, getattr(self, attr)) + return result + class Ip: """ An IP defines a bloc instantiated at chip top level, or more generally, a design specification chapter @@ -530,6 +569,10 @@ def __init__(self, name="", index=""): self.rfu_list = [] self.rfu_list_0 = [] self.rfu_list_1 = [] + self.vptool_gitrev = '' + self.io_fmt_gitrev = '' + self.config_gitrev = '' + self.ymlcfg_gitrev = '' def to_Feature(self): """ @@ -539,8 +582,11 @@ def to_Feature(self): # Next_elf_it needs extra care as it is derived from the length of the list # of Properties / Subfeatures. result.next_elt_id = self.prop_count + result.display_order = self.wid_order translated_subfeatures = [[elt[0], elt[1].to_Subfeature()] for elt in (self.prop_list if self.prop_list else self.rfu_list)] result.subfeatures = OrderedDict(translated_subfeatures) + for attr in ["vptool_gitrev", "io_fmt_gitrev", "config_gitrev", "ymlcfg_gitrev"]: + setattr(result, attr, getattr(self, attr)) return result def __str__(self): From f9e7cfcdbeefd70d60584a3f5847185e4cd94b41 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Thu, 9 Feb 2023 10:19:17 +0100 Subject: [PATCH 4/9] VPTOOL: Revert Pickle output to protocol 0. Add stable roundtrip Yaml I/O. * tooos/vptool/vptool/vp.py (MyMain.save_db): Revert to human-readable version of Pickle protocol. Change default Yaml files to 'VP_IPnnn.yml'. (MyMain.load_db_quiet): Add arg 'use_yaml_input' to switch between Pickle and Yaml input. Change default Yaml files to 'VP_IPnnn.yml'. Process input according to chosen input mode (Pickle/Yaml). (MyMain.lock_all_ip): Revert to human-readable version of Pickle protocol. (MyMain.create_gui): Add arg 'use_yaml_input' to select load mode. (toplevel): Add '-y'/'--yaml' option to cmdline options. Pass choice to GUI creation. * tools/vptool/vptool/vp_pack.py (Subfeature.to_Prop): Set item_count. Populate rfu_list. Fix name of list of items. (Prop.to_Subfeature): Add debug message (commented out). Accept item count as is. (Feature._highest_id): Rename to '_feature_count'. Start from 0, not -1. (Feature.__init__): Set default value of 'id' arg to "" and check for default ID accordingly, so 0 becomes a valid non-default ID. (Feature.to_Ip): Map id to ip_num. Correctly populate the rfu_list and the prop_list attributes. (Ip.__init__): Check for default index by comparing against default value instead of checking for falseness. Add debug message (commented out). (Ip.to_Feature): Add comment. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp.py | 78 ++++++++++++++++++++-------------- tools/vptool/vptool/vp_pack.py | 37 ++++++++-------- 2 files changed, 64 insertions(+), 51 deletions(-) diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index 900ed0905e..755afe774c 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -1977,7 +1977,7 @@ def save_db(self, save_as="no"): + ".pck", "wb", ) as output: - pickle.dump(ip_elt, output, 4) + pickle.dump(ip_elt, output, 0) # TODO: Add translation of pickle_ip_list to new-gen # types *HERE*, after emitting Pickle. # Emit the Yaml output from the fixed structures, @@ -1987,7 +1987,7 @@ def save_db(self, save_as="no"): save_dir + "/VP_IP" + str(ip_elt[1].ip_num).zfill(3) - + "_new_types.yml", + + ".yml", "wb", ) as output: db_yaml_engine.dump(ip_elt[1].to_Feature(), output) @@ -2010,9 +2010,9 @@ def save_db(self, save_as="no"): else: # ZC FIXME Add support for Yaml in non-split-save mode. with open(vp_config.SAVED_DB_LOCATION, "wb") as output: - pickle.dump(len(pickle_ip_list), output, 4) + pickle.dump(len(pickle_ip_list), output, 0) for ip_elt in pickle_ip_list: - pickle.dump(ip_elt, output, 4) + pickle.dump(ip_elt, output, 0) self.prep_db_import() # update_ip_widget() self.update_all_item_target_list() @@ -2057,7 +2057,7 @@ def load_db( tkinter.messagebox.showwarning("Warning", "No DB Loaded!") return need_to_load - def load_db_quiet(self): + def load_db_quiet(self, use_yaml_input=False): pickle_ip_list = [] ip_num_next = 0 if self.split_save: @@ -2073,16 +2073,18 @@ def load_db_quiet(self): else "" ) + ")", - os.path.join(dir_to_load, "VP_IP*.pck"), + os.path.join(dir_to_load, "VP_IP[0-9][0-9][0-9].pck"), ) ) - for filename in glob.glob(dir_to_load + "/VP_IP*pck"): - # print("---INFO: Loading "+filename) - with open(filename, "rb") as input: - pickle_ip_list.append(pickle.load(input)) - #for filename in glob.glob(dir_to_load + "/VP_IP*yml"): - # with open(filename, "rb") as input: - # pickle_ip_list.append(db_yaml_engine.load(input)) + if not use_yaml_input: + for filename in glob.glob(dir_to_load + "/VP_IP*pck"): + # print("---INFO: Loading "+filename) + with open(filename, "rb") as input: + pickle_ip_list.append(pickle.load(input)) + else: + for filename in glob.glob(dir_to_load + "/VP_IP[0-9][0-9][0-9].yml"): + with open(filename, "rb") as input: + pickle_ip_list.append(db_yaml_engine.load(input)) if pickle_ip_list: # Find the lowest ip_num that can be used for newly created IPs. # It has to be higher than the highest existing ip_num. @@ -2090,8 +2092,8 @@ def load_db_quiet(self): ip_num_next = 1 + max( [ (lambda e: e if isinstance(e, int) else int(e, base=10))( - #elt.ip_num # Yaml !!omap mode: list of objects - elt[1].ip_num + elt.id if use_yaml_input # Yaml !!omap mode: list of objects + else elt[1].ip_num ) for elt in pickle_ip_list ] @@ -2109,16 +2111,18 @@ def load_db_quiet(self): for dummy in range(ip_num_next): pickle_ip_list.append(pickle.load(input)) # change list to dict - # Yaml mode: !!omap yields a list of elts when loaded. - #for ip_elt in pickle_ip_list: - # self.ip_list[ip_elt.name] = ip_elt - # # Seems pickle doesn't restore class attribute. Done manually here for IP - # self.ip_list[ip_elt.name].__class__._ip_count = ip_num_next - # Pickle mode: list of objects is a list of mappings - for ip_key, ip_elt in pickle_ip_list: - self.ip_list[ip_key] = ip_elt - # Seems pickle doesn't restore class attribute. Done manually here for IP - self.ip_list[ip_key].__class__._ip_count = ip_num_next + if use_yaml_input: + # Yaml mode: !!omap yields a list of elts when loaded. + for ip_elt in pickle_ip_list: + self.ip_list[ip_elt.name] = ip_elt.to_Ip() + # Seems pickle doesn't restore class attribute. Done manually here for IP + self.ip_list[ip_elt.name].__class__._ip_count = ip_num_next + else: + # Pickle mode: list of objects is a list of mappings as 2-elt lists + for ip_key, ip_elt in pickle_ip_list: + self.ip_list[ip_key] = ip_elt + # Seems pickle doesn't restore class attribute. Done manually here for IP + self.ip_list[ip_key].__class__._ip_count = ip_num_next self.prep_db_import() self.update_all_item_target_list() self.db_git_rev = self.get_db_gitrev() @@ -2177,7 +2181,7 @@ def lock_ip(self): LOCKED_IP_DICT[current_ip_name] = pwd.getpwuid(os.getuid()).pw_name try: with open(vp_config.LOCKED_IP_LOCATION, "wb") as output: - pickle.dump(LOCKED_IP_DICT, output, 4) + pickle.dump(LOCKED_IP_DICT, output, 0) self.update_ip_widget() except Exception as e: print( @@ -2200,7 +2204,7 @@ def lock_all_ip(self): LOCKED_IP_DICT[current_ip_name] = pwd.getpwuid(os.getuid()).pw_name try: with open(vp_config.LOCKED_IP_LOCATION, "wb") as output: - pickle.dump(LOCKED_IP_DICT, output, 4) + pickle.dump(LOCKED_IP_DICT, output, 0) self.update_ip_widget() except Exception as e: print( @@ -2279,9 +2283,9 @@ def save_personalization(self): if os.path.exists(sys.argv[0]): preference_file = os.path.dirname(sys.argv[0]) + "/" + PERSO_FILE with open(preference_file, "wb") as output: - pickle.dump(BG_COLOR, output, 4) - pickle.dump(EDITOR, output, 4) - pickle.dump(self.verif_menu.enable_image_panel.get(), output, 4) + pickle.dump(BG_COLOR, output, 0) + pickle.dump(EDITOR, output, 0) + pickle.dump(self.verif_menu.enable_image_panel.get(), output, 0) def change_gui_color(self): global BG_COLOR @@ -2342,7 +2346,7 @@ def get_spin_vip_config(self): ##### DB INTERACTIION FUNCTIONS ##### Main GUI Creation - def create_gui(self, theme): + def create_gui(self, theme, use_yaml_input): self.personalization() # TOP Widget @@ -2450,7 +2454,7 @@ def create_gui(self, theme): self.desc_widget.text1.bind("", self.im_up_des_ctrl_lock) self.desc_widget.text.bind("", self.im_up_des_tip_disp) self.item_widget.wlist.bind("<>", self.im_up_item) - self.load_db_quiet() + self.load_db_quiet(use_yaml_input) self.load_lock_ip() self.update_ip_widget() self.top.bind("", self.main_exit_handler) @@ -2481,6 +2485,14 @@ def __generate_option_parser(): help="Select a GUI theme for this session", default=vp_config.yaml_config["gui"]["theme"], ) + parser.add_option( + "-y", + "--yaml", + action="store_true", + dest="use_yaml_input", + help="Read database in Yaml format", + default=False, + ) return parser @@ -2507,4 +2519,4 @@ def __generate_option_parser(): SAVED_DB_LOCATION = os.path.realpath(options.dataBase) print(SAVED_DB_LOCATION) -top_gui.create_gui(options.theme) +top_gui.create_gui(options.theme, options.use_yaml_input) diff --git a/tools/vptool/vptool/vp_pack.py b/tools/vptool/vptool/vp_pack.py index d9d5324a10..baf6c35c33 100755 --- a/tools/vptool/vptool/vp_pack.py +++ b/tools/vptool/vptool/vp_pack.py @@ -332,7 +332,9 @@ def to_Prop(self): Convert a Subfeature into legacy-stype Prop object. """ result = Prop(self.name, self.tag, self.display_order) - result.list_of_items = [[elt[0], elt[1].to_Item()] for elt in self.items.items()] + result.item_count = self.next_elt_id + result.rfu_list = [[elt[0], elt[1].to_Item()] for elt in self.items.items()] + result.item_list = dict(result.rfu_list) return result class Prop: @@ -365,11 +367,8 @@ def to_Subfeature(self): # numbering of Items in Prop and will be inconsistent if items are removed. # Computing the max of item IDs is not reliable either in case the last # item was removed. + 3print("### Prop.to_Subfeature(tag='%s'): item_count = %d" % (self.tag, self.item_count)) result.next_elt_id = self.item_count - max_item_id = max([int(elt[1].name) for elt in (self.item_list if self.item_list else self.rfu_list)]) - if max_item_id >= self.item_count: - raise ValueError((self.item_count, max_item_id)) - result.next_elt_id = 1 + max_item_id result.display_order = self.wid_order translated_items = [[elt[0], elt[1].to_VerifItem()] for elt in (self.item_list if self.item_list else self.rfu_list)] result.items = OrderedDict(translated_items) @@ -477,24 +476,20 @@ class Feature: a class of instructions or an operation mode of an interface. """ # Class variable: highest Feature ID seen so far. - _highest_id = -1 + _feature_count = 0 - def __init__(self, name="", id=0): + def __init__(self, name="", id=""): # Index of next subfeature to add (MUST ALWAYS GROW upon adding subfeatures!) self.next_elt_id = 0 # Name of the Feature self.name = name # Numerical ID of the Feature: Use the highest known value PLUS ONE # unless explicitly given (e.g., when converting Ip objects). - if id != 0: - if id > self.__class__._highest_id: - self.__class__._highest_id = id - self.id = id - else: - raise ValueError((id, self.__class__._highest_id)) + if id != "": + self.id = int(id) else: - self.__class__._highest_id += 1 - self.id = self.__class__._highest_id + self.id = self.__class__._feature_count + self.__class__._feature_count += 1 # Display order of the Feature self.display_order = self.id # List of subfeatures @@ -538,9 +533,13 @@ def to_Ip(self): """ Convert a Feature to a legacy-stype Ip. """ - result = Ip(self.name) + # Map Feature.id to Ip.ip_num. + #print("### Feature.to_Ip(name='%s', id='%d')" % (self.name, self.id)) + result = Ip(self.name, self.id) + result.prop_count = self.next_elt_id result.wid_order = self.display_order - result.prop_list = [[elt[0], elt[1].toSubfeature()] for elt in self.subfeatures.items()] + result.rfu_list = [[elt[0], elt[1].to_Prop()] for elt in self.subfeatures.items()] + result.prop_list = dict(result.rfu_list) for attr in ["vptool_gitrev", "io_fmt_gitrev", "config_gitrev", "ymlcfg_gitrev"]: setattr(result, attr, getattr(self, attr)) return result @@ -558,10 +557,11 @@ def __init__(self, name="", index=""): self.prop_count = 0 # determine how many prop have been created for a given IP self.name = name self.prop_list = {} - if index: + if index != "": self.ip_num = index ## Store number creation else: self.ip_num = self.__class__._ip_count + #print("### Created Ip(name='%s', index='%d')" % (self.name, self.ip_num)) self.__class__._ip_count += 1 self.wid_order = self.ip_num # rfu for future dev @@ -578,6 +578,7 @@ def to_Feature(self): """ Convert an Ip to a Feature. """ + # Map Ip.ip_num to Feature.id. result = Feature(self.name, self.ip_num) # Next_elf_it needs extra care as it is derived from the length of the list # of Properties / Subfeatures. From 16bf162879eb5590480bf9ed06db7c6c54b03e0d Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Thu, 9 Feb 2023 12:40:27 +0100 Subject: [PATCH 5/9] VPTOOL HOTFIX: Fix breaker typo. * tools/vptool/vptool/vp_pack.py (Prop.to_Subfeature): Fix typo commenting out the diagnostic message. Signed-off-by: Zbigniew Chamski --- tools/vptool/vptool/vp_pack.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/vptool/vptool/vp_pack.py b/tools/vptool/vptool/vp_pack.py index baf6c35c33..7ee5d68801 100755 --- a/tools/vptool/vptool/vp_pack.py +++ b/tools/vptool/vptool/vp_pack.py @@ -367,7 +367,7 @@ def to_Subfeature(self): # numbering of Items in Prop and will be inconsistent if items are removed. # Computing the max of item IDs is not reliable either in case the last # item was removed. - 3print("### Prop.to_Subfeature(tag='%s'): item_count = %d" % (self.tag, self.item_count)) + #print("### Prop.to_Subfeature(tag='%s'): item_count = %d" % (self.tag, self.item_count)) result.next_elt_id = self.item_count result.display_order = self.wid_order translated_items = [[elt[0], elt[1].to_VerifItem()] for elt in (self.item_list if self.item_list else self.rfu_list)] From 3e2b547217f320e5997f9a8a6b6927c737df5e51 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 13 Feb 2023 10:23:40 +0100 Subject: [PATCH 6/9] VPTOOL: Switch to Yaml storage. Prepare to switch DVplans to Yaml form. * cva6/docs/VerifPlans/FRONTEND/runme.sh: Pass cmdline options to VPTOOL. * cva6/docs/VerifPlans/ISA_RV32/runme.sh: Ditto. * tools/vptool/vptool/vp.py (MyMain.save_db): Save databases as Yaml. (MyMain.load_db_quiet): By default, load DB from the Yaml files. Use "yml" extension in window title when using Yaml DB files. (__generate_option_parser): Add option to select Pickle input. Set defaults to Yaml for both Yaml and Pickle format option. Signed-off-by: Zbigniew Chamski --- cva6/docs/VerifPlans/FRONTEND/runme.sh | 2 +- cva6/docs/VerifPlans/ISA_RV32/runme.sh | 2 +- tools/vptool/vptool/vp.py | 38 ++++++++++++++++---------- 3 files changed, 26 insertions(+), 16 deletions(-) diff --git a/cva6/docs/VerifPlans/FRONTEND/runme.sh b/cva6/docs/VerifPlans/FRONTEND/runme.sh index 3a79359e96..fb0023f982 100644 --- a/cva6/docs/VerifPlans/FRONTEND/runme.sh +++ b/cva6/docs/VerifPlans/FRONTEND/runme.sh @@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` # FIXME: Introduce a suitably named shell variable that points to the root # directory of the tool set (TOOL_TOP etc.) # FORNOW use a hardcoded relative path. -python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py -t winxpblue +python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py $* diff --git a/cva6/docs/VerifPlans/ISA_RV32/runme.sh b/cva6/docs/VerifPlans/ISA_RV32/runme.sh index 8cc952c8a2..b301c78503 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/runme.sh +++ b/cva6/docs/VerifPlans/ISA_RV32/runme.sh @@ -31,4 +31,4 @@ export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` # FIXME: Introduce a suitably named shell variable that points to the root # directory of the tool set (TOOL_TOP etc.) # FORNOW use a hardcoded relative path. -python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py -t winxpblue +python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py $* diff --git a/tools/vptool/vptool/vp.py b/tools/vptool/vptool/vp.py index 755afe774c..03047594b4 100755 --- a/tools/vptool/vptool/vp.py +++ b/tools/vptool/vptool/vp.py @@ -1968,20 +1968,21 @@ def save_db(self, save_as="no"): "yaml_cfg_gitrev" ] # Save individual IPs only if locked by user. - if self.is_locked_by_user(current_ip_name=ip_elt[1].name): - saved_ip_str += "\n " + ip_elt[1].name - with open( - save_dir - + "/VP_IP" - + str(ip_elt[1].ip_num).zfill(3) - + ".pck", - "wb", - ) as output: - pickle.dump(ip_elt, output, 0) + #if self.is_locked_by_user(current_ip_name=ip_elt[1].name): + # saved_ip_str += "\n " + ip_elt[1].name + # with open( + # save_dir + # + "/VP_IP" + # + str(ip_elt[1].ip_num).zfill(3) + # + ".pck", + # "wb", + # ) as output: + # pickle.dump(ip_elt, output, 0) # TODO: Add translation of pickle_ip_list to new-gen # types *HERE*, after emitting Pickle. # Emit the Yaml output from the fixed structures, # skipping pickled ones. + saved_ip_str += "\n " + ip_elt[1].name # Write yaml output with open( save_dir @@ -2057,7 +2058,7 @@ def load_db( tkinter.messagebox.showwarning("Warning", "No DB Loaded!") return need_to_load - def load_db_quiet(self, use_yaml_input=False): + def load_db_quiet(self, use_yaml_input=True): pickle_ip_list = [] ip_num_next = 0 if self.split_save: @@ -2073,11 +2074,11 @@ def load_db_quiet(self, use_yaml_input=False): else "" ) + ")", - os.path.join(dir_to_load, "VP_IP[0-9][0-9][0-9].pck"), + os.path.join(dir_to_load, "VP_IP[0-9][0-9][0-9].%s" % ("yml" if use_yaml_input else "pck")), ) ) if not use_yaml_input: - for filename in glob.glob(dir_to_load + "/VP_IP*pck"): + for filename in glob.glob(dir_to_load + "/VP_IP[0-9][0-9][0-9].pck"): # print("---INFO: Loading "+filename) with open(filename, "rb") as input: pickle_ip_list.append(pickle.load(input)) @@ -2491,8 +2492,17 @@ def __generate_option_parser(): action="store_true", dest="use_yaml_input", help="Read database in Yaml format", - default=False, + default=True, ) + parser.add_option( + "-p", + "--pickle", + action="store_false", + dest="use_yaml_input", + help="Read database in Pickle format", + default=True, + ) + return parser From c34e480faf5ff39e1017f3fe0bdb06cb280e5eb5 Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 13 Feb 2023 11:29:24 +0100 Subject: [PATCH 7/9] DV plans: Switch FRONTEND DV plan to Yaml format. * cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml: New. * cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck: Delete. * cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck: Ditto. * cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck: Ditto. Signed-off-by: Zbigniew Chamski --- cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck | 1198 -------------------- cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml | 422 +++++++ cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck | 384 ------- cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml | 104 ++ cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck | 508 --------- cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml | 152 +++ cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck | 384 ------- cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml | 104 ++ cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck | 232 ---- cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml | 66 ++ cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck | 308 ----- cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml | 80 ++ cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck | 59 - cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml | 10 + cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck | 376 ------ cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml | 114 ++ 16 files changed, 1052 insertions(+), 3449 deletions(-) delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml delete mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck create mode 100644 cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck deleted file mode 100644 index a5d1c48614..0000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP003.pck +++ /dev/null @@ -1,1198 +0,0 @@ -(VPC generation stage -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I10 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I3 -sVwid_order -p12 -I3 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V001_BTB -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I6 -sg8 -g17 -sVtag -p23 -VVP_IP003_P001 -p24 -sVitem_list -p25 -(dp26 -sg12 -I1 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F003_S001_I000 -p34 -sVdescription -p35 -VIf instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB. Else JALR is not considered as a control flow instruction, which will generate a mispredict. -p36 -sVpurpose -p37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p38 -sVverif_goals -p39 -VExecute a JALR instruction with a valid address in BTB which is not a misprediction. Check that instruction queue is not flushed. -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I4 -sVtest_type -p44 -I0 -sVcov_method -p45 -I1 -sVcores -p46 -I16 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_FRONTEND_F003_S001_I001 -p62 -sg35 -VIf instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB. Else JALR is not considered as a control flow instruction, which will generate a mispredict. -p63 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p64 -sg39 -VExecute a JALR instruction with a valid address in BTB which is a misprediction. -p65 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -a(V002 -p71 -g1 -(g29 -g3 -Ntp72 -Rp73 -(dp74 -g8 -V002 -p75 -sg23 -VVP_FRONTEND_F003_S001_I002 -p76 -sg35 -VIf instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB.\u000a\u000aElse JALR is not considered as a control flow instruction, which will generate a mispredict. -p77 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p78 -sg39 -VExecute test with JALR instructions. Functional cov: JALR is executed and BTB output is not valid. -p79 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp80 -sg15 -(lp81 -sg52 -(lp82 -sg13 -(dp83 -g55 -I0 -ssbtp84 -asVrfu_list_1 -p85 -(lp86 -sg52 -(lp87 -sg13 -(dp88 -sbtp89 -a(V002_BHT -p90 -g1 -(g18 -g3 -Ntp91 -Rp92 -(dp93 -g22 -I4 -sg8 -g90 -sg23 -VVP_IP003_P002 -p94 -sg25 -(dp95 -sg12 -I2 -sg15 -(lp96 -(V000 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V000 -p101 -sg23 -VVP_FRONTEND_F003_S002_I000 -p102 -sg35 -VIf instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken. -p103 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p104 -sg39 -VExecute a BRANCH instruction with a valid address in BHT which is not a misprediction. Check that instruction queue is not flushed. -p105 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -Vlock_status -p110 -I0 -ssbtp111 -a(V001 -p112 -g1 -(g29 -g3 -Ntp113 -Rp114 -(dp115 -g8 -V001 -p116 -sg23 -VVP_FRONTEND_F003_S002_I001 -p117 -sg35 -VIf instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken. -p118 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p119 -sg39 -VExecute a BRANCH instruction with a valid address in BHT which is a misprediction. -p120 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp121 -sg15 -(lp122 -sg52 -(lp123 -sg13 -(dp124 -Vlock_status -p125 -I0 -ssbtp126 -a(V002 -p127 -g1 -(g29 -g3 -Ntp128 -Rp129 -(dp130 -g8 -V002 -p131 -sg23 -VVP_FRONTEND_F003_S002_I002 -p132 -sg35 -VIf instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken. -p133 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p134 -sg39 -VExecute test with BRANCH instructions. Functional cov: a BRANCH is executed, BTB output is not valid and the branch is taken. -p135 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp136 -sg15 -(lp137 -sg52 -(lp138 -sg13 -(dp139 -g125 -I0 -ssbtp140 -asg85 -(lp141 -sg52 -(lp142 -sg13 -(dp143 -sbtp144 -a(V003_RAS -p145 -g1 -(g18 -g3 -Ntp146 -Rp147 -(dp148 -g22 -I4 -sg8 -g145 -sg23 -VVP_IP003_P003 -p149 -sg25 -(dp150 -sg12 -I3 -sg15 -(lp151 -(V000 -p152 -g1 -(g29 -g3 -Ntp153 -Rp154 -(dp155 -g8 -V000 -p156 -sg23 -VVP_FRONTEND_F003_S003_I000 -p157 -sg35 -VIf instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated. -p158 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p159 -sg39 -VExecute a RET instruction with a valid address in RAS. Check that instruction queue is not flushed. -p160 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp161 -sg15 -(lp162 -sg52 -(lp163 -sg13 -(dp164 -g125 -I0 -ssbtp165 -a(V001 -p166 -g1 -(g29 -g3 -Ntp167 -Rp168 -(dp169 -g8 -V001 -p170 -sg23 -VVP_FRONTEND_F003_S003_I001 -p171 -sg35 -VIf instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated. -p172 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p173 -sg39 -VExecute a RET instruction with a valid address in RAS which is a misprediction. -p174 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp175 -sg15 -(lp176 -sg52 -(lp177 -sg13 -(dp178 -g125 -I0 -ssbtp179 -a(V002 -p180 -g1 -(g29 -g3 -Ntp181 -Rp182 -(dp183 -g8 -V002 -p184 -sg23 -VVP_FRONTEND_F003_S003_I002 -p185 -sg35 -VIf instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated. -p186 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Branch Predict -p187 -sg39 -VExecute test with RET instructions. Functional cov: RET is executed and RAS output is not valid. -p188 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp189 -sg15 -(lp190 -sg52 -(lp191 -sg13 -(dp192 -g125 -I0 -ssbtp193 -asg85 -(lp194 -sg52 -(lp195 -sg13 -(dp196 -sbtp197 -a(V004_Return from environment call -p198 -g1 -(g18 -g3 -Ntp199 -Rp200 -(dp201 -g22 -I2 -sg8 -g198 -sg23 -VVP_IP003_P004 -p202 -sg25 -(dp203 -sg12 -I4 -sg15 -(lp204 -(V000 -p205 -g1 -(g29 -g3 -Ntp206 -Rp207 -(dp208 -g8 -V000 -p209 -sg23 -VVP_FRONTEND_F003_S004_I000 -p210 -sg35 -VWhen CSR asks a return from an environment call, the PC is assigned to the successive PC to the one stored in the CSR [m-s]epc register. -p211 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Return from env call -p212 -sg39 -VSet two different addresses for mepc and sepc in CSR registers. Use a arc_test returning from machine env call.\u000a\u000a* Check by assertion that when machine return occurs the mepc address is fetched.\u000a* Functional cov: execute a machine return. -p213 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp214 -sg15 -(lp215 -sg52 -(lp216 -sg13 -(dp217 -g125 -I0 -ssbtp218 -a(V001 -p219 -g1 -(g29 -g3 -Ntp220 -Rp221 -(dp222 -g8 -V001 -p223 -sg23 -VVP_FRONTEND_F003_S004_I001 -p224 -sg35 -VWhen CSR asks a return from an environment call, the PC is assigned to the successive PC to the one stored in the CSR [m-s]epc register. -p225 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Return from env call -p226 -sg39 -VSet two different addresses for mepc and sepc in CSR registers. Use a returning from supervisor env call.\u000a\u000a* Check by assertion that when supervisor return occurs the sepc address is fetched.\u000a* Functional cov: execute a supervisor return. -p227 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I24 -sg47 -g42 -sg48 -g42 -sg49 -(lp228 -sg15 -(lp229 -sg52 -(lp230 -sg13 -(dp231 -g125 -I0 -ssbtp232 -asg85 -(lp233 -sg52 -(lp234 -sg13 -(dp235 -sbtp236 -a(V005_Exception/Interrupt -p237 -g1 -(g18 -g3 -Ntp238 -Rp239 -(dp240 -g22 -I2 -sg8 -g237 -sg23 -VVP_IP003_P005 -p241 -sg25 -(dp242 -sg12 -I5 -sg15 -(lp243 -(V000 -p244 -g1 -(g29 -g3 -Ntp245 -Rp246 -(dp247 -g8 -V000 -p248 -sg23 -VVP_FRONTEND_F003_S005_I000 -p249 -sg35 -VIf an exception (or interrupt, which is in the context of RISC-V systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned to the CSR trap vector base address. The trap vector base address can be different depending on whether the exception traps to S-Mode or M-Mode (user mode exceptions are currently not supported) -p250 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Exception -p251 -sg39 -VSet two different addresses for machine and supervisor handlers in CSR registers. Use a test which executes in machine mode and generates a machine exception by UVM. Check by assertion that when machine exception occurs the machine address is fetched. Functional cov: exception occurs in machine mode. -p252 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp253 -sg15 -(lp254 -sg52 -(lp255 -sg13 -(dp256 -g125 -I0 -ssbtp257 -a(V001 -p258 -g1 -(g29 -g3 -Ntp259 -Rp260 -(dp261 -g8 -V001 -p262 -sg23 -VVP_FRONTEND_F003_S005_I001 -p263 -sg35 -VIf an exception (or interrupt, which is in the context of RISC-V systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned to the CSR trap vector base address. The trap vector base address can be different depending on whether the exception traps to S-Mode or M-Mode (user mode exceptions are currently not supported) -p264 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Exception -p265 -sg39 -VSet two different addresses for machine and supervisor handlers in CSR registers. Use a test which executes in supervisor mode and generates a supervisor exception by UVM. Check by assertion that when supervisor exception occurs the supervisor address is fetched. functional cov: exception occurs in supervisor mode. -p266 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp267 -sg15 -(lp268 -sg52 -(lp269 -sg13 -(dp270 -g125 -I0 -ssbtp271 -asg85 -(lp272 -sg52 -(lp273 -sg13 -(dp274 -sbtp275 -a(V006_Pipeline flush -p276 -g1 -(g18 -g3 -Ntp277 -Rp278 -(dp279 -g22 -I2 -sg8 -g276 -sg23 -VVP_IP003_P006 -p280 -sg25 -(dp281 -sg12 -I6 -sg15 -(lp282 -(V000 -p283 -g1 -(g29 -g3 -Ntp284 -Rp285 -(dp286 -g8 -V000 -p287 -sg23 -VVP_FRONTEND_F003_S006_I000 -p288 -sg35 -VFRONTEND starts fetching from the next instruction again in order to take the up-dated information into account -p289 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Pipeline flush -p290 -sg39 -V[no need to verify this point] -p291 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp292 -sg15 -(lp293 -sg52 -(lp294 -sg13 -(dp295 -g125 -I0 -ssbtp296 -asg85 -(lp297 -sg52 -(lp298 -sg13 -(dp299 -sbtp300 -a(V007_Debug -p301 -g1 -(g18 -g3 -Ntp302 -Rp303 -(dp304 -g22 -I1 -sg8 -g301 -sg23 -VVP_IP003_P007 -p305 -sg25 -(dp306 -sg12 -I7 -sg15 -(lp307 -(V000 -p308 -g1 -(g29 -g3 -Ntp309 -Rp310 -(dp311 -g8 -V000 -p312 -sg23 -VVP_FRONTEND_F003_S007_I000 -p313 -sg35 -VThe debug jump is requested by CSR. The address to be jumped into is HW coded. -p314 -sg37 -VFRONTEND sub-system/functionality/PC generation stage/Debug -p315 -sg39 -VUVM generates a debug request to jump into debug handler. Check by assertion that the HW coded debug address is fetched. Functional cov: debug mode occurs -p316 -sg41 -g42 -sg43 -I4 -sg44 -I0 -sg45 -I1 -sg46 -I32 -sg47 -g42 -sg48 -g42 -sg49 -(lp317 -sg15 -(lp318 -sg52 -(lp319 -sg13 -(dp320 -g125 -I0 -ssbtp321 -asg85 -(lp322 -sg52 -(lp323 -sg13 -(dp324 -sbtp325 -a(V008_Address mapping change -p326 -g1 -(g18 -g3 -Ntp327 -Rp328 -(dp329 -g22 -I1 -sg8 -g326 -sg23 -VVP_IP003_P008 -p330 -sg25 -(dp331 -sg12 -I8 -sg15 -(lp332 -(V000 -p333 -g1 -(g29 -g3 -Ntp334 -Rp335 -(dp336 -g8 -V000 -p337 -sg23 -VVP_FRONTEND_F003_S008_I000 -p338 -sg35 -VAll program counters are logical addressed. If the logical to physical mapping changes a fence.vm instruction should used to flush the pipeline and TLBs -p339 -sg37 -VFRONTEND sub-system/functionality/PC generation stage -p340 -sg39 -VExecute a address mapping change, then execute a fence.vm instruction, and continue the execution. -p341 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp342 -sg15 -(lp343 -sg52 -(lp344 -sg13 -(dp345 -g125 -I0 -ssbtp346 -asg85 -(lp347 -sg52 -(lp348 -sg13 -(dp349 -sbtp350 -a(V009_Pc gen priority -p351 -g1 -(g18 -g3 -Ntp352 -Rp353 -(dp354 -g22 -I3 -sg8 -g351 -sg23 -VVP_IP003_P009 -p355 -sg25 -(dp356 -sg12 -I9 -sg15 -(lp357 -(V000 -p358 -g1 -(g29 -g3 -Ntp359 -Rp360 -(dp361 -g8 -V000 -p362 -sg23 -VVP_FRONTEND_F003_S009_I000 -p363 -sg35 -VThe next PC can originate from the following sources (listed in order of precedence) -p364 -sg37 -VFRONTEND sub-system/functionality/PC generation stage -p365 -sg39 -VUse arc_test executing return from env call and generate Exceptions by UVM during reset, Branch predict, default, mispredict, replay and return from env call. Functional cov: monitor the 6 events -p366 -sg41 -g42 -sg43 -I3 -sg44 -I0 -sg45 -I1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp367 -sg15 -(lp368 -sg52 -(lp369 -sg13 -(dp370 -g125 -I0 -ssbtp371 -a(V002 -p372 -g1 -(g29 -g3 -Ntp373 -Rp374 -(dp375 -g8 -V002 -p376 -sg23 -VVP_FRONTEND_F003_S009_I002 -p377 -sg35 -VThe next PC can originate from the following sources (listed in order of precedence) -p378 -sg37 -VFRONTEND sub-system/functionality/PC generation stage -p379 -sg39 -V[other cases to be elaborated] -p380 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp381 -sg15 -(lp382 -sg52 -(lp383 -sg13 -(dp384 -g125 -I0 -ssbtp385 -asg85 -(lp386 -sg52 -(lp387 -sg13 -(dp388 -sbtp389 -asVrfu_list_0 -p390 -(lp391 -sg85 -(lp392 -sVvptool_gitrev -p393 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p394 -sVio_fmt_gitrev -p395 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p396 -sVconfig_gitrev -p397 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p398 -sVymlcfg_gitrev -p399 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p400 -sbtp401 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml new file mode 100644 index 0000000000..83439bc394 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP003.yml @@ -0,0 +1,422 @@ +!Feature +next_elt_id: 10 +name: PC generation stage +id: 3 +display_order: 3 +subfeatures: !!omap +- 001_BTB: !Subfeature + name: 001_BTB + tag: VP_IP003_P001 + next_elt_id: 6 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S001_I000 + description: If instruction is a JALR and BTB (Branch Target Buffer) returns + a valid address, next PC is predicted by BTB. Else JALR is not considered + as a control flow instruction, which will generate a mispredict. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a JALR instruction with a valid address in BTB which + is not a misprediction. Check that instruction queue is not flushed. + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S001_I001 + description: If instruction is a JALR and BTB (Branch Target Buffer) returns + a valid address, next PC is predicted by BTB. Else JALR is not considered + as a control flow instruction, which will generate a mispredict. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a JALR instruction with a valid address in BTB which + is a misprediction. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S001_I002 + description: "If instruction is a JALR and BTB (Branch Target Buffer) returns\ + \ a valid address, next PC is predicted by BTB.\n\nElse JALR is not considered\ + \ as a control flow instruction, which will generate a mispredict." + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute test with JALR instructions. Functional cov: JALR is + executed and BTB output is not valid.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' +- 002_BHT: !Subfeature + name: 002_BHT + tag: VP_IP003_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S002_I000 + description: If instruction is a branch and BTH (Branch History table) returns + a valid address, next PC is predicted by BHT. Else branch is not considered + as an control flow instruction, which will generate a mispredict when branch + is taken. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a BRANCH instruction with a valid address in BHT which + is not a misprediction. Check that instruction queue is not flushed. + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S002_I001 + description: If instruction is a branch and BTH (Branch History table) returns + a valid address, next PC is predicted by BHT. Else branch is not considered + as an control flow instruction, which will generate a mispredict when branch + is taken. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a BRANCH instruction with a valid address in BHT which + is a misprediction. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S002_I002 + description: If instruction is a branch and BTH (Branch History table) returns + a valid address, next PC is predicted by BHT. Else branch is not considered + as an control flow instruction, which will generate a mispredict when branch + is taken. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute test with BRANCH instructions. Functional cov: a BRANCH + is executed, BTB output is not valid and the branch is taken.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' +- 003_RAS: !Subfeature + name: 003_RAS + tag: VP_IP003_P003 + next_elt_id: 4 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S003_I000 + description: If instruction is a RET and RAS (Return Address Stack) returns + a valid address and RET has already been consummed by instruction queue. + Else RET is considered as a control flow instruction but next PC is not + predicted. A mispredict wil be generated. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a RET instruction with a valid address in RAS. Check + that instruction queue is not flushed. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S003_I001 + description: If instruction is a RET and RAS (Return Address Stack) returns + a valid address and RET has already been consummed by instruction queue. + Else RET is considered as a control flow instruction but next PC is not + predicted. A mispredict wil be generated. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a RET instruction with a valid address in RAS which is + a misprediction. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S003_I002 + description: If instruction is a RET and RAS (Return Address Stack) returns + a valid address and RET has already been consummed by instruction queue. + Else RET is considered as a control flow instruction but next PC is not + predicted. A mispredict wil be generated. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute test with RET instructions. Functional cov: RET is executed + and RAS output is not valid.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' +- 004_Return from environment call: !Subfeature + name: 004_Return from environment call + tag: VP_IP003_P004 + next_elt_id: 2 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S004_I000 + description: When CSR asks a return from an environment call, the PC is assigned + to the successive PC to the one stored in the CSR [m-s]epc register. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Return from + env call + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Set two different addresses for mepc and sepc in CSR registers.\ + \ Use a arc_test returning from machine env call.\n\n* Check by assertion\ + \ that when machine return occurs the mepc address is fetched.\n* Functional\ + \ cov: execute a machine return." + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S004_I001 + description: When CSR asks a return from an environment call, the PC is assigned + to the successive PC to the one stored in the CSR [m-s]epc register. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Return from + env call + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Set two different addresses for mepc and sepc in CSR registers.\ + \ Use a returning from supervisor env call.\n\n* Check by assertion that\ + \ when supervisor return occurs the sepc address is fetched.\n* Functional\ + \ cov: execute a supervisor return." + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 24 + coverage_loc: '' + comments: '' +- 005_Exception/Interrupt: !Subfeature + name: 005_Exception/Interrupt + tag: VP_IP003_P005 + next_elt_id: 2 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S005_I000 + description: If an exception (or interrupt, which is in the context of RISC-V + systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned + to the CSR trap vector base address. The trap vector base address can be + different depending on whether the exception traps to S-Mode or M-Mode (user + mode exceptions are currently not supported) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Exception + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Set two different addresses for machine and supervisor handlers + in CSR registers. Use a test which executes in machine mode and generates + a machine exception by UVM. Check by assertion that when machine exception + occurs the machine address is fetched. Functional cov: exception occurs + in machine mode.' + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S005_I001 + description: If an exception (or interrupt, which is in the context of RISC-V + systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned + to the CSR trap vector base address. The trap vector base address can be + different depending on whether the exception traps to S-Mode or M-Mode (user + mode exceptions are currently not supported) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Exception + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Set two different addresses for machine and supervisor handlers + in CSR registers. Use a test which executes in supervisor mode and generates + a supervisor exception by UVM. Check by assertion that when supervisor exception + occurs the supervisor address is fetched. functional cov: exception occurs + in supervisor mode.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' +- 006_Pipeline flush: !Subfeature + name: 006_Pipeline flush + tag: VP_IP003_P006 + next_elt_id: 2 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S006_I000 + description: FRONTEND starts fetching from the next instruction again in order + to take the up-dated information into account + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Pipeline flush + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[no need to verify this point]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' +- 007_Debug: !Subfeature + name: 007_Debug + tag: VP_IP003_P007 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S007_I000 + description: The debug jump is requested by CSR. The address to be jumped + into is HW coded. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Debug + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'UVM generates a debug request to jump into debug handler. Check + by assertion that the HW coded debug address is fetched. Functional cov: + debug mode occurs' + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 32 + coverage_loc: '' + comments: '' +- 008_Address mapping change: !Subfeature + name: 008_Address mapping change + tag: VP_IP003_P008 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S008_I000 + description: All program counters are logical addressed. If the logical to + physical mapping changes a fence.vm instruction should used to flush the + pipeline and TLBs + reqt_doc: FRONTEND sub-system/functionality/PC generation stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a address mapping change, then execute a fence.vm instruction, + and continue the execution. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 009_Pc gen priority: !Subfeature + name: 009_Pc gen priority + tag: VP_IP003_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S009_I000 + description: The next PC can originate from the following sources (listed + in order of precedence) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Use arc_test executing return from env call and generate Exceptions + by UVM during reset, Branch predict, default, mispredict, replay and return + from env call. Functional cov: monitor the 6 events' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S009_I002 + description: The next PC can originate from the following sources (listed + in order of precedence) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[other cases to be elaborated]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck deleted file mode 100644 index 7af6e80e48..0000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP004.pck +++ /dev/null @@ -1,384 +0,0 @@ -(VBTB -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I4 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I4 -sVwid_order -p12 -I4 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_flush -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP004_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F004_S000_I000 -p34 -sVdescription -p35 -VThe BTB is never flushed. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/BTB -p38 -sVverif_goals -p39 -VNA\u000a\u000a[Does it make sense?] -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I0 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_table depth -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP004_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F004_S001_I000 -p74 -sg35 -VThe information is stored in a 8 entry table. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/BTB -p76 -sg39 -VConfirm that the best configuration for BTB entry number is 8 by monitoring the Coremark performance and silicon footprint, the configuration without BTB is to be challenged too. -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -a(V002_Table update -p87 -g1 -(g18 -g3 -Ntp88 -Rp89 -(dp90 -g22 -I1 -sg8 -g87 -sg23 -VVP_IP004_P002 -p91 -sg25 -(dp92 -sg12 -I2 -sg15 -(lp93 -(V000 -p94 -g1 -(g29 -g3 -Ntp95 -Rp96 -(dp97 -g8 -V000 -p98 -sg23 -VVP_FRONTEND_F004_S002_I000 -p99 -sg35 -VWhen a unconditional jumps to a register (JALR instruction) is mispredicted by the EXECUTE, the relative information is stored into the BTB, that is to say the JALR PC and the target address. -p100 -sg37 -VFRONTEND sub-system/Architecture and Modules/BTB -p101 -sg39 -VWhen a mis predict occurs caused by JALR, check that info is stored in BTB -p102 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp103 -sg15 -(lp104 -sg52 -(lp105 -sg13 -(dp106 -g55 -I0 -ssbtp107 -asg57 -(lp108 -sg52 -(lp109 -sg13 -(dp110 -sbtp111 -a(V003_debug is not intrusive -p112 -g1 -(g18 -g3 -Ntp113 -Rp114 -(dp115 -g22 -I1 -sg8 -g112 -sg23 -VVP_IP004_P003 -p116 -sg25 -(dp117 -sg12 -I3 -sg15 -(lp118 -(V000 -p119 -g1 -(g29 -g3 -Ntp120 -Rp121 -(dp122 -g8 -V000 -p123 -sg23 -VVP_FRONTEND_F004_S003_I000 -p124 -sg35 -VThe BTB is not updated if processor is in debug mode. -p125 -sg37 -VFRONTEND sub-system/Architecture and Modules/BTB -p126 -sg39 -VExecute a debug session, check that the table content is not modified -p127 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I32 -sg47 -g42 -sg48 -g42 -sg49 -(lp128 -sg15 -(lp129 -sg52 -(lp130 -sg13 -(dp131 -g55 -I0 -ssbtp132 -asg57 -(lp133 -sg52 -(lp134 -sg13 -(dp135 -sbtp136 -asVrfu_list_0 -p137 -(lp138 -sg57 -(lp139 -sVvptool_gitrev -p140 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p141 -sVio_fmt_gitrev -p142 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p143 -sVconfig_gitrev -p144 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p145 -sVymlcfg_gitrev -p146 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p147 -sbtp148 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml new file mode 100644 index 0000000000..9b39ea709e --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP004.yml @@ -0,0 +1,104 @@ +!Feature +next_elt_id: 4 +name: BTB +id: 4 +display_order: 4 +subfeatures: !!omap +- 000_flush: !Subfeature + name: 000_flush + tag: VP_IP004_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S000_I000 + description: The BTB is never flushed. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "NA\n\n[Does it make sense?]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 001_table depth: !Subfeature + name: 001_table depth + tag: VP_IP004_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S001_I000 + description: The information is stored in a 8 entry table. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for BTB entry number is 8 + by monitoring the Coremark performance and silicon footprint, the configuration + without BTB is to be challenged too. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Table update: !Subfeature + name: 002_Table update + tag: VP_IP004_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S002_I000 + description: When a unconditional jumps to a register (JALR instruction) is + mispredicted by the EXECUTE, the relative information is stored into the + BTB, that is to say the JALR PC and the target address. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: When a mis predict occurs caused by JALR, check that info is + stored in BTB + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 003_debug is not intrusive: !Subfeature + name: 003_debug is not intrusive + tag: VP_IP004_P003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S003_I000 + description: The BTB is not updated if processor is in debug mode. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a debug session, check that the table content is not + modified + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 32 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck deleted file mode 100644 index 56b70c2b1b..0000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP005.pck +++ /dev/null @@ -1,508 +0,0 @@ -(VBHT -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I6 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I5 -sVwid_order -p12 -I5 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_flush -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP005_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F005_S000_I000 -p34 -sVdescription -p35 -VThe BTB is never flushed. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/BHT -p38 -sVverif_goals -p39 -VNA\u000a\u000a[Does it make sense?] -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I0 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V002_table update -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP005_P002 -p66 -sg25 -(dp67 -sg12 -I2 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F005_S002_I000 -p74 -sg35 -VWhen a branch instruction is resolved by the EXECUTE, the relative information is stored in the Branch History Table. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p76 -sg39 -VWhen a mis predict occurs caused by BRANCH, check that info is stored in BHT -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -a(V003_saturation -p87 -g1 -(g18 -g3 -Ntp88 -Rp89 -(dp90 -g22 -I2 -sg8 -g87 -sg23 -VVP_IP005_P003 -p91 -sg25 -(dp92 -sg12 -I3 -sg15 -(lp93 -(V000 -p94 -g1 -(g29 -g3 -Ntp95 -Rp96 -(dp97 -g8 -V000 -p98 -sg23 -VVP_FRONTEND_F005_S003_I000 -p99 -sg35 -VThe Branch History table is a two-bit saturation counter that takes the virtual address of the current fetched instruction by the CACHE. It states whether the current branch request should be taken or not. The two bit counter is updated by the successive execution of the current instructions as shown in the following figure. -p100 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p101 -sg39 -VExecute a serie of taken and not taken branch to check the saturation mechanism -p102 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I-1 -sg47 -g42 -sg48 -g42 -sg49 -(lp103 -sg15 -(lp104 -sg52 -(lp105 -sg13 -(dp106 -g55 -I0 -ssbtp107 -a(V001 -p108 -g1 -(g29 -g3 -Ntp109 -Rp110 -(dp111 -g8 -V001 -p112 -sg23 -VVP_FRONTEND_F005_S003_I001 -p113 -sg35 -VThe Branch History table is a two-bit saturation counter that takes the virtual address of the current fetched instruction by the CACHE. It states whether the current branch request should be taken or not. The two bit counter is updated by the successive execution of the current instructions as shown in the following figure. -p114 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p115 -sg39 -VVerify the saturation mechnism is optimal. Modify the saturation mechanism by removing/adding one stage, and check the Coremark performance evolution -p116 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp117 -sg15 -(lp118 -sg52 -(lp119 -sg13 -(dp120 -g55 -I0 -ssbtp121 -asg57 -(lp122 -sg52 -(lp123 -sg13 -(dp124 -sbtp125 -a(V004_Table depth -p126 -g1 -(g18 -g3 -Ntp127 -Rp128 -(dp129 -g22 -I1 -sg8 -g126 -sg23 -VVP_IP005_P004 -p130 -sg25 -(dp131 -sg12 -I4 -sg15 -(lp132 -(V000 -p133 -g1 -(g29 -g3 -Ntp134 -Rp135 -(dp136 -g8 -V000 -p137 -sg23 -VVP_FRONTEND_F005_S004_I000 -p138 -sg35 -VThe information is stored in a 1024 entry table. -p139 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p140 -sg39 -VConfirm that the best configuration for BHT entry number is 1024 by monitoring the Coremark performance and silicon footprint, the configuration without BHT is to be challenged too. -p141 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp142 -sg15 -(lp143 -sg52 -(lp144 -sg13 -(dp145 -g55 -I0 -ssbtp146 -asg57 -(lp147 -sg52 -(lp148 -sg13 -(dp149 -sbtp150 -a(V005_Debug is not intrusive -p151 -g1 -(g18 -g3 -Ntp152 -Rp153 -(dp154 -g22 -I1 -sg8 -g151 -sg23 -VVP_IP005_P005 -p155 -sg25 -(dp156 -sg12 -I5 -sg15 -(lp157 -(V000 -p158 -g1 -(g29 -g3 -Ntp159 -Rp160 -(dp161 -g8 -V000 -p162 -sg23 -VVP_FRONTEND_F005_S005_I000 -p163 -sg35 -VThe BHT is not updated if processor is in debug mode. -p164 -sg37 -VFRONTEND sub-system/Architecture and Modules/BHT -p165 -sg39 -VExecute a debug session, check that the table content is not modified -p166 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I32 -sg47 -g42 -sg48 -g42 -sg49 -(lp167 -sg15 -(lp168 -sg52 -(lp169 -sg13 -(dp170 -g55 -I0 -ssbtp171 -asg57 -(lp172 -sg52 -(lp173 -sg13 -(dp174 -sbtp175 -asVrfu_list_0 -p176 -(lp177 -sg57 -(lp178 -sVvptool_gitrev -p179 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p180 -sVio_fmt_gitrev -p181 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p182 -sVconfig_gitrev -p183 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p184 -sVymlcfg_gitrev -p185 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p186 -sbtp187 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml new file mode 100644 index 0000000000..df4babd4dd --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP005.yml @@ -0,0 +1,152 @@ +!Feature +next_elt_id: 6 +name: BHT +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_flush: !Subfeature + name: 000_flush + tag: VP_IP005_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S000_I000 + description: The BTB is never flushed. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "NA\n\n[Does it make sense?]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 002_table update: !Subfeature + name: 002_table update + tag: VP_IP005_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S002_I000 + description: When a branch instruction is resolved by the EXECUTE, the relative + information is stored in the Branch History Table. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: When a mis predict occurs caused by BRANCH, check that info is + stored in BHT + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 003_saturation: !Subfeature + name: 003_saturation + tag: VP_IP005_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S003_I000 + description: The Branch History table is a two-bit saturation counter that + takes the virtual address of the current fetched instruction by the CACHE. + It states whether the current branch request should be taken or not. The + two bit counter is updated by the successive execution of the current instructions + as shown in the following figure. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a serie of taken and not taken branch to check the saturation + mechanism + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F005_S003_I001 + description: The Branch History table is a two-bit saturation counter that + takes the virtual address of the current fetched instruction by the CACHE. + It states whether the current branch request should be taken or not. The + two bit counter is updated by the successive execution of the current instructions + as shown in the following figure. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Verify the saturation mechnism is optimal. Modify the saturation + mechanism by removing/adding one stage, and check the Coremark performance + evolution + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 004_Table depth: !Subfeature + name: 004_Table depth + tag: VP_IP005_P004 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S004_I000 + description: The information is stored in a 1024 entry table. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for BHT entry number is 1024 + by monitoring the Coremark performance and silicon footprint, the configuration + without BHT is to be challenged too. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 005_Debug is not intrusive: !Subfeature + name: 005_Debug is not intrusive + tag: VP_IP005_P005 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S005_I000 + description: The BHT is not updated if processor is in debug mode. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a debug session, check that the table content is not + modified + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 32 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck deleted file mode 100644 index 2fdde8008f..0000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP006.pck +++ /dev/null @@ -1,384 +0,0 @@ -(VRAS -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I4 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I6 -sVwid_order -p12 -I6 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_flush -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP006_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F006_S000_I000 -p34 -sVdescription -p35 -VThe RAS is never flushed. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/RAS -p38 -sVverif_goals -p39 -VNA\u000a\u000a[Does it make sense?] -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I0 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_table depth -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP006_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F006_S001_I000 -p74 -sg35 -VThe RAS FIFO depth is 2. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/RAS -p76 -sg39 -VConfirm that the best configuration for RAS entry number is 2 by monitoring the Coremark performance and silicon footprint, the configuration without RAS is to be challenged too. -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -a(V002_Table update -p87 -g1 -(g18 -g3 -Ntp88 -Rp89 -(dp90 -g22 -I1 -sg8 -g87 -sg23 -VVP_IP006_P002 -p91 -sg25 -(dp92 -sg12 -I2 -sg15 -(lp93 -(V000 -p94 -g1 -(g29 -g3 -Ntp95 -Rp96 -(dp97 -g8 -V000 -p98 -sg23 -VVP_FRONTEND_F006_S002_I000 -p99 -sg35 -VWhen an unconditional jumps to a known target address (JAL instruction) is consummed by the instr_queue, the next pc after the JAL instruction and the return address are stored into a FIFO. -p100 -sg37 -VFRONTEND sub-system/Architecture and Modules/RAS -p101 -sg39 -VWhen a JAL instruction is executed, check that info is stored in RAS -p102 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp103 -sg15 -(lp104 -sg52 -(lp105 -sg13 -(dp106 -g55 -I0 -ssbtp107 -asg57 -(lp108 -sg52 -(lp109 -sg13 -(dp110 -sbtp111 -a(V003_Debug is not intrusive -p112 -g1 -(g18 -g3 -Ntp113 -Rp114 -(dp115 -g22 -I1 -sg8 -g112 -sg23 -VVP_IP006_P003 -p116 -sg25 -(dp117 -sg12 -I3 -sg15 -(lp118 -(V000 -p119 -g1 -(g29 -g3 -Ntp120 -Rp121 -(dp122 -g8 -V000 -p123 -sg23 -VVP_FRONTEND_F006_S003_I000 -p124 -sg35 -VNo dedicated specification -p125 -sg37 -VFRONTEND sub-system/Architecture and Modules/RAS -p126 -sg39 -VExecute a debug session, check that the table content is not modified -p127 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I32 -sg47 -g42 -sg48 -g42 -sg49 -(lp128 -sg15 -(lp129 -sg52 -(lp130 -sg13 -(dp131 -g55 -I0 -ssbtp132 -asg57 -(lp133 -sg52 -(lp134 -sg13 -(dp135 -sbtp136 -asVrfu_list_0 -p137 -(lp138 -sg57 -(lp139 -sVvptool_gitrev -p140 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p141 -sVio_fmt_gitrev -p142 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p143 -sVconfig_gitrev -p144 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p145 -sVymlcfg_gitrev -p146 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p147 -sbtp148 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml new file mode 100644 index 0000000000..76b06d4982 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP006.yml @@ -0,0 +1,104 @@ +!Feature +next_elt_id: 4 +name: RAS +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_flush: !Subfeature + name: 000_flush + tag: VP_IP006_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S000_I000 + description: The RAS is never flushed. + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "NA\n\n[Does it make sense?]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 001_table depth: !Subfeature + name: 001_table depth + tag: VP_IP006_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S001_I000 + description: The RAS FIFO depth is 2. + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for RAS entry number is 2 + by monitoring the Coremark performance and silicon footprint, the configuration + without RAS is to be challenged too. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Table update: !Subfeature + name: 002_Table update + tag: VP_IP006_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S002_I000 + description: When an unconditional jumps to a known target address (JAL instruction) + is consummed by the instr_queue, the next pc after the JAL instruction and + the return address are stored into a FIFO. + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: When a JAL instruction is executed, check that info is stored + in RAS + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 003_Debug is not intrusive: !Subfeature + name: 003_Debug is not intrusive + tag: VP_IP006_P003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S003_I000 + description: No dedicated specification + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a debug session, check that the table content is not + modified + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 32 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck deleted file mode 100644 index 92ea004222..0000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP007.pck +++ /dev/null @@ -1,232 +0,0 @@ -(VInstr_realign -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I2 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I7 -sVwid_order -p12 -I7 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_C extension -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP007_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F007_S000_I000 -p34 -sVdescription -p35 -VThe 32-bit aligned block coming from the CACHE sub-system enters the instr_realign module. This module extracts the instructions from the 32-bit blocks, up to two instructions because it is possible to fetch two instructions when C extension is used. If the instructions are not compressed, it is possible that the instruction is not aligned on the block size but rather interleaved with two cache blocks. In that case, two cache accesses are needed. The instr_realign module provides at maximum one instruction per cycle. Not complete instruction is stored in instr_realign module before being provided in the next cycles. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/Instr_realign -p38 -sVverif_goals -p39 -VExecute program compiled with C extension. Cover the case when 2 instructions are fetched in the same cache block and when an instruction is interleaved with two cache block\u000a\u000a[NO NEED TO VERIFY THIS CASE] -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I0 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_Flush -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP007_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F007_S001_I000 -p74 -sg35 -VIn case of mispredict, flush, replay or branch predict, the instr_realign is re-initialized, the internal register storing the instruction alignment state is reset. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/Instr_realign -p76 -sg39 -V[NO NEED TO VERIFY THIS CASE] -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I0 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -asVrfu_list_0 -p87 -(lp88 -sg57 -(lp89 -sVvptool_gitrev -p90 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p91 -sVio_fmt_gitrev -p92 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p93 -sVconfig_gitrev -p94 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p95 -sVymlcfg_gitrev -p96 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p97 -sbtp98 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml new file mode 100644 index 0000000000..365f818e39 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP007.yml @@ -0,0 +1,66 @@ +!Feature +next_elt_id: 2 +name: Instr_realign +id: 7 +display_order: 7 +subfeatures: !!omap +- 000_C extension: !Subfeature + name: 000_C extension + tag: VP_IP007_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F007_S000_I000 + description: The 32-bit aligned block coming from the CACHE sub-system enters + the instr_realign module. This module extracts the instructions from the + 32-bit blocks, up to two instructions because it is possible to fetch two + instructions when C extension is used. If the instructions are not compressed, + it is possible that the instruction is not aligned on the block size but + rather interleaved with two cache blocks. In that case, two cache accesses + are needed. The instr_realign module provides at maximum one instruction + per cycle. Not complete instruction is stored in instr_realign module before + being provided in the next cycles. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_realign + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Execute program compiled with C extension. Cover the case when\ + \ 2 instructions are fetched in the same cache block and when an instruction\ + \ is interleaved with two cache block\n\n[NO NEED TO VERIFY THIS CASE]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 001_Flush: !Subfeature + name: 001_Flush + tag: VP_IP007_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F007_S001_I000 + description: In case of mispredict, flush, replay or branch predict, the instr_realign + is re-initialized, the internal register storing the instruction alignment + state is reset. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_realign + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[NO NEED TO VERIFY THIS CASE]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck deleted file mode 100644 index dc4ea8eef4..0000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP008.pck +++ /dev/null @@ -1,308 +0,0 @@ -(VInstr_queue -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I3 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I8 -sVwid_order -p12 -I8 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_FIFO depth -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP008_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F008_S000_I000 -p34 -sVdescription -p35 -VThe instruction queue contains max 4 instructions. -p36 -sVpurpose -p37 -VFRONTEND sub-system/Architecture and Modules/Instr_queue -p38 -sVverif_goals -p39 -VConfirm that the best configuration for instruction queue entry number is 4 by monitoring the Coremark performance and silicon footprint -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I11 -sVtest_type -p44 -I10 -sVcov_method -p45 -I10 -sVcores -p46 -I8 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_Page fault exception -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I1 -sg8 -g62 -sg23 -VVP_IP008_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_FRONTEND_F008_S001_I000 -p74 -sg35 -VIn instruction queue, exception can only correspond to page-fault exception. -p75 -sg37 -VFRONTEND sub-system/Architecture and Modules/Instr_queue -p76 -sg39 -VExecute following exception and check that only page-fault can be stored in instruction queue: bus errors, invalid accesses or instruction page faults. -p77 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -asg57 -(lp83 -sg52 -(lp84 -sg13 -(dp85 -sbtp86 -a(V002_Flush -p87 -g1 -(g18 -g3 -Ntp88 -Rp89 -(dp90 -g22 -I1 -sg8 -g87 -sg23 -VVP_IP008_P002 -p91 -sg25 -(dp92 -sg12 -I2 -sg15 -(lp93 -(V000 -p94 -g1 -(g29 -g3 -Ntp95 -Rp96 -(dp97 -g8 -V000 -p98 -sg23 -VVP_FRONTEND_F008_S002_I000 -p99 -sg35 -VThe instruction queue can be flushed by CONTROLLER. -p100 -sg37 -VFRONTEND sub-system/Architecture and Modules/Instr_queue -p101 -sg39 -V[NO NEED TO VERIFY THIS CASE] -p102 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I0 -sg47 -g42 -sg48 -g42 -sg49 -(lp103 -sg15 -(lp104 -sg52 -(lp105 -sg13 -(dp106 -g55 -I0 -ssbtp107 -asg57 -(lp108 -sg52 -(lp109 -sg13 -(dp110 -sbtp111 -asVrfu_list_0 -p112 -(lp113 -sg57 -(lp114 -sVvptool_gitrev -p115 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p116 -sVio_fmt_gitrev -p117 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p118 -sVconfig_gitrev -p119 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p120 -sVymlcfg_gitrev -p121 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p122 -sbtp123 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml new file mode 100644 index 0000000000..0559c2d9d1 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP008.yml @@ -0,0 +1,80 @@ +!Feature +next_elt_id: 3 +name: Instr_queue +id: 8 +display_order: 8 +subfeatures: !!omap +- 000_FIFO depth: !Subfeature + name: 000_FIFO depth + tag: VP_IP008_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F008_S000_I000 + description: The instruction queue contains max 4 instructions. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for instruction queue entry + number is 4 by monitoring the Coremark performance and silicon footprint + pfc: 11 + test_type: 10 + cov_method: 10 + cores: 8 + coverage_loc: '' + comments: '' +- 001_Page fault exception: !Subfeature + name: 001_Page fault exception + tag: VP_IP008_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F008_S001_I000 + description: In instruction queue, exception can only correspond to page-fault + exception. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute following exception and check that only page-fault can + be stored in instruction queue: bus errors, invalid accesses or instruction + page faults.' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Flush: !Subfeature + name: 002_Flush + tag: VP_IP008_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F008_S002_I000 + description: The instruction queue can be flushed by CONTROLLER. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[NO NEED TO VERIFY THIS CASE]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck deleted file mode 100644 index ac1287a8b7..0000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP009.pck +++ /dev/null @@ -1,59 +0,0 @@ -(VInstr_scan -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I0 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I9 -sVwid_order -p12 -I9 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -sVrfu_list_0 -p17 -(lp18 -sVrfu_list_1 -p19 -(lp20 -sVvptool_gitrev -p21 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p22 -sVio_fmt_gitrev -p23 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p24 -sVconfig_gitrev -p25 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p26 -sVymlcfg_gitrev -p27 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p28 -sbtp29 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml new file mode 100644 index 0000000000..6ec7a33b7e --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP009.yml @@ -0,0 +1,10 @@ +!Feature +next_elt_id: 0 +name: Instr_scan +id: 9 +display_order: 9 +subfeatures: !!omap [] +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck b/cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck deleted file mode 100644 index db23b5ab5b..0000000000 --- a/cva6/docs/VerifPlans/FRONTEND/VP_IP010.pck +++ /dev/null @@ -1,376 +0,0 @@ -(VFetch stage -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I3 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I10 -sVwid_order -p12 -I10 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V001_MMU translation -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I2 -sg8 -g17 -sVtag -p23 -VVP_IP010_P001 -p24 -sVitem_list -p25 -(dp26 -sg12 -I1 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_FRONTEND_F010_S001_I000 -p34 -sVdescription -p35 -VThe Fetch stage asks the MMU to translate the requested address. -p36 -sVpurpose -p37 -VFRONTEND sub-system/functionality/Fetch stage -p38 -sVverif_goals -p39 -VExecute a program with virtual PC -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I-1 -sVtest_type -p44 -I-1 -sVcov_method -p45 -I-1 -sVcores -p46 -I16 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_FRONTEND_F010_S001_I001 -p62 -sg35 -VThe Fetch stage asks the MMU to translate the requested address. -p63 -sg37 -VFRONTEND sub-system/functionality/Fetch stage -p64 -sg39 -VCheck the translation does not impact execution time by executing Coremark in pphysical and virtual modes. -p65 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -asVrfu_list_1 -p71 -(lp72 -sg52 -(lp73 -sg13 -(dp74 -sbtp75 -a(V002_Exceptions -p76 -g1 -(g18 -g3 -Ntp77 -Rp78 -(dp79 -g22 -I4 -sg8 -g76 -sg23 -VVP_IP010_P002 -p80 -sg25 -(dp81 -sg12 -I2 -sg15 -(lp82 -(V000 -p83 -g1 -(g29 -g3 -Ntp84 -Rp85 -(dp86 -g8 -V000 -p87 -sg23 -VVP_FRONTEND_F010_S002_I000 -p88 -sg35 -VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults. -p89 -sg37 -VFRONTEND sub-system/functionality/Fetch stage -p90 -sg39 -VGenerate a bus error exception by UVM or by test (to be decided) and check that the exception address is fetched. Functional cov: a bus error exception occurs. -p91 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp92 -sg15 -(lp93 -sg52 -(lp94 -sg13 -(dp95 -g55 -I0 -ssbtp96 -a(V002 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V002 -p101 -sg23 -VVP_FRONTEND_F010_S002_I002 -p102 -sg35 -VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults. -p103 -sg37 -VFRONTEND sub-system/functionality/Fetch stage -p104 -sg39 -VGenerate an invalid access exception by UVM or by test (to be decided) and check that the exception address is fetched. Functional cov: an invalid access exception occurs. -p105 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I8 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -g55 -I0 -ssbtp110 -a(V003 -p111 -g1 -(g29 -g3 -Ntp112 -Rp113 -(dp114 -g8 -V003 -p115 -sg23 -VVP_FRONTEND_F010_S002_I003 -p116 -sg35 -VMemory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults. -p117 -sg37 -VFRONTEND sub-system/functionality/Fetch stage -p118 -sg39 -VGenerate an instruction page faults and check that the exception is triggered -p119 -sg41 -g42 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I16 -sg47 -g42 -sg48 -g42 -sg49 -(lp120 -sg15 -(lp121 -sg52 -(lp122 -sg13 -(dp123 -g55 -I0 -ssbtp124 -asg71 -(lp125 -sg52 -(lp126 -sg13 -(dp127 -sbtp128 -asVrfu_list_0 -p129 -(lp130 -sg71 -(lp131 -sVvptool_gitrev -p132 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p133 -sVio_fmt_gitrev -p134 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p135 -sVconfig_gitrev -p136 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p137 -sVymlcfg_gitrev -p138 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p139 -sbtp140 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml b/cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml new file mode 100644 index 0000000000..fe95149ac9 --- /dev/null +++ b/cva6/docs/VerifPlans/FRONTEND/VP_IP010.yml @@ -0,0 +1,114 @@ +!Feature +next_elt_id: 3 +name: Fetch stage +id: 10 +display_order: 10 +subfeatures: !!omap +- 001_MMU translation: !Subfeature + name: 001_MMU translation + tag: VP_IP010_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F010_S001_I000 + description: The Fetch stage asks the MMU to translate the requested address. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a program with virtual PC + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F010_S001_I001 + description: The Fetch stage asks the MMU to translate the requested address. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Check the translation does not impact execution time by executing + Coremark in pphysical and virtual modes. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Exceptions: !Subfeature + name: 002_Exceptions + tag: VP_IP010_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F010_S002_I000 + description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback + potential exceptions generated by the memory fetch request. They can be + bus errors, invalid accesses or instruction page faults. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Generate a bus error exception by UVM or by test (to be decided) + and check that the exception address is fetched. Functional cov: a bus error + exception occurs.' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F010_S002_I002 + description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback + potential exceptions generated by the memory fetch request. They can be + bus errors, invalid accesses or instruction page faults. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Generate an invalid access exception by UVM or by test (to be + decided) and check that the exception address is fetched. Functional cov: + an invalid access exception occurs.' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_FRONTEND_F010_S002_I003 + description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback + potential exceptions generated by the memory fetch request. They can be + bus errors, invalid accesses or instruction page faults. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Generate an instruction page faults and check that the exception + is triggered + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' From e03c76bacd37d858b08a04426952e50c7f383c5e Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 13 Feb 2023 11:34:12 +0100 Subject: [PATCH 8/9] DV plans: Switch ISA_RV32 DV plan to Yaml format. * cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml: New. * cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck: Delete. * cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck: Ditto. Signed-off-by: Zbigniew Chamski --- cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck | 1999 --------------- cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml | 697 ++++++ cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck | 1828 -------------- cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml | 665 +++++ cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck | 1478 ----------- cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml | 498 ++++ cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck | 1333 ---------- cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml | 454 ++++ cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck | 157 -- cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml | 33 + cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck | 284 --- cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml | 70 + cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck | 780 ------ cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml | 275 +++ cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck | 976 -------- cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml | 350 +++ cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck | 520 ---- cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml | 179 ++ cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck | 2059 ---------------- cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml | 788 ++++++ cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck | 2592 -------------------- cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml | 868 +++++++ cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck | 920 ------- cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml | 286 +++ cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck | 672 ----- cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml | 218 ++ cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck | 824 ------- cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml | 263 ++ cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck | 157 -- cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml | 32 + 30 files changed, 5676 insertions(+), 16579 deletions(-) delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml delete mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck create mode 100644 cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck deleted file mode 100644 index 01fe8aacb0..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.pck +++ /dev/null @@ -1,1999 +0,0 @@ -(VRV32I Register-Immediate Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I11 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I0 -sVwid_order -p12 -I0 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_ADDI -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP011_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F011_S000_I000 -p34 -sVdescription -p35 -Vaddi rd, rs1, imm[11:0]\u000ard = rs1 + Sext(imm[11:0])\u000aArithmetic overflow is lost and ignored -p36 -sVpurpose -p37 -VISA\u000aChapter 2.4 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32i_addi_cg.cp_rs1\u000aisacov.rv32i_addi_cg.cp_rd\u000aisacov.rv32i_addi_cg.cp_rd_rs1_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F011_S000_I001 -p63 -sg35 -Vaddi rd, rs1, imm[11:0]\u000ard = rs1 + Sext(imm[11:0])\u000aArithmetic overflow is lost and ignored -p64 -sg37 -VISA\u000aChapter 2.4 -p65 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p66 -sg41 -Visacov.rv32i_addi_cg.cp_rs1_value\u000aisacov.rv32i_addi_cg.cp_immi_value\u000aisacov.rv32i_addi_cg.cross_rs1_immi_value\u000aisacov.rv32i_addi_cg.cp_rs1_toggle\u000aisacov.rv32i_addi_cg.cp_immi_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F011_S000_I002 -p78 -sg35 -Vaddi rd, rs1, imm[11:0]\u000ard = rs1 + Sext(imm[11:0])\u000aArithmetic overflow is lost and ignored -p79 -sg37 -VISA\u000aChapter 2.4 -p80 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32i_addi_cg.cp_rd_value\u000aisacov.rv32i_addi_cg.cp_rd_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -asVrfu_list_1 -p88 -(lp89 -sg53 -(lp90 -sg13 -(dp91 -sbtp92 -a(V001_XORI -p93 -g1 -(g18 -g3 -Ntp94 -Rp95 -(dp96 -g22 -I5 -sg8 -g93 -sg23 -VVP_IP011_P001 -p97 -sg25 -(dp98 -sg12 -I1 -sg15 -(lp99 -(V000 -p100 -g1 -(g29 -g3 -Ntp101 -Rp102 -(dp103 -g8 -V000 -p104 -sg23 -VVP_ISA_F011_S001_I000 -p105 -sg35 -Vxori rd, rs1, imm[11:0]\u000ard = rs1 ^ Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p106 -sg37 -VISA\u000aChapter 2.4 -p107 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p108 -sg41 -Visacov.rv32i_xori_cg.cp_rs1\u000aisacov.rv32i_xori_cg.cp_rd\u000aisacov.rv32i_xori_cg.cp_rd_rs1_hazard -p109 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp110 -sg15 -(lp111 -sg53 -(lp112 -sg13 -(dp113 -g56 -I0 -ssbtp114 -a(V001 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -g115 -sg23 -VVP_ISA_F011_S001_I001 -p119 -sg35 -Vxori rd, rs1, imm[11:0]\u000ard = rs1 ^ Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p120 -sg37 -VISA\u000aChapter 2.4 -p121 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p122 -sg41 -Visacov.rv32i_xori_cg.cp_rs1_value\u000aisacov.rv32i_xori_cg.cp_immi_value\u000aisacov.rv32i_xori_cg.cross_rs1_immi_value\u000aisacov.rv32i_xori_cg.cp_rs1_toggle\u000aisacov.rv32i_xori_cg.cp_immi_toggle -p123 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp124 -sg15 -(lp125 -sg53 -(lp126 -sg13 -(dp127 -g56 -I0 -ssbtp128 -a(V002 -p129 -g1 -(g29 -g3 -Ntp130 -Rp131 -(dp132 -g8 -g129 -sg23 -VVP_ISA_F011_S001_I002 -p133 -sg35 -Vxori rd, rs1, imm[11:0]\u000ard = rs1 ^ Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p134 -sg37 -VISA\u000aChapter 2.4 -p135 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p136 -sg41 -Visacov.rv32i_xori_cg.cp_rd_value\u000aisacov.rv32i_xori_cg.cp_rd_toggle -p137 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp138 -sg15 -(lp139 -sg53 -(lp140 -sg13 -(dp141 -g56 -I0 -ssbtp142 -asg88 -(lp143 -sg53 -(lp144 -sg13 -(dp145 -sbtp146 -a(V002_ORI -p147 -g1 -(g18 -g3 -Ntp148 -Rp149 -(dp150 -g22 -I4 -sg8 -g147 -sg23 -VVP_IP011_P002 -p151 -sg25 -(dp152 -sg12 -I2 -sg15 -(lp153 -(V000 -p154 -g1 -(g29 -g3 -Ntp155 -Rp156 -(dp157 -g8 -V000 -p158 -sg23 -VVP_ISA_F011_S002_I000 -p159 -sg35 -Vori rd, rs1, imm[11:0]\u000ard = rs1 | Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p160 -sg37 -VISA\u000aChapter 2.4 -p161 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p162 -sg41 -Visacov.rv32i_ori_cg.cp_rs1\u000aisacov.rv32i_ori_cg.cp_rd\u000aisacov.rv32i_ori_cg.cp_rd_rs1_hazard -p163 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp164 -sg15 -(lp165 -sg53 -(lp166 -sg13 -(dp167 -g56 -I0 -ssbtp168 -a(V001 -p169 -g1 -(g29 -g3 -Ntp170 -Rp171 -(dp172 -g8 -g169 -sg23 -VVP_ISA_F011_S002_I001 -p173 -sg35 -Vori rd, rs1, imm[11:0]\u000ard = rs1 | Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p174 -sg37 -VISA\u000aChapter 2.4 -p175 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p176 -sg41 -Visacov.rv32i_ori_cg.cp_rs1_value\u000aisacov.rv32i_ori_cg.cp_immi_value\u000aisacov.rv32i_ori_cg.cross_rs1_immi_value\u000aisacov.rv32i_ori_cg.cp_rs1_toggle\u000aisacov.rv32i_ori_cg.cp_immi_toggle -p177 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp178 -sg15 -(lp179 -sg53 -(lp180 -sg13 -(dp181 -g56 -I0 -ssbtp182 -a(V002 -p183 -g1 -(g29 -g3 -Ntp184 -Rp185 -(dp186 -g8 -g183 -sg23 -VVP_ISA_F011_S002_I002 -p187 -sg35 -Vori rd, rs1, imm[11:0]\u000ard = rs1 | Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p188 -sg37 -VISA\u000aChapter 2.4 -p189 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p190 -sg41 -Visacov.rv32i_ori_cg.cp_rd_value\u000aisacov.rv32i_ori_cg.cp_rd_toggle -p191 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp192 -sg15 -(lp193 -sg53 -(lp194 -sg13 -(dp195 -g56 -I0 -ssbtp196 -asg88 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -sbtp200 -a(V003_ANDI -p201 -g1 -(g18 -g3 -Ntp202 -Rp203 -(dp204 -g22 -I3 -sg8 -g201 -sg23 -VVP_IP011_P003 -p205 -sg25 -(dp206 -sg12 -I3 -sg15 -(lp207 -(V000 -p208 -g1 -(g29 -g3 -Ntp209 -Rp210 -(dp211 -g8 -V000 -p212 -sg23 -VVP_ISA_F011_S003_I000 -p213 -sg35 -Vandi rd, rs1, imm[11:0]\u000ard = rs1 & Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p214 -sg37 -VISA\u000aChapter 2.4 -p215 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p216 -sg41 -Visacov.rv32i_andi_cg.cp_rs1\u000aisacov.rv32i_andi_cg.cp_rd\u000aisacov.rv32i_andi_cg.cp_rd_rs1_hazard -p217 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp218 -sg15 -(lp219 -sg53 -(lp220 -sg13 -(dp221 -g56 -I0 -ssbtp222 -a(V001 -p223 -g1 -(g29 -g3 -Ntp224 -Rp225 -(dp226 -g8 -V001 -p227 -sg23 -VVP_ISA_F011_S003_I001 -p228 -sg35 -Vandi rd, rs1, imm[11:0]\u000ard = rs1 & Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p229 -sg37 -VISA\u000aChapter 2.4 -p230 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p231 -sg41 -Visacov.rv32i_andi_cg.cp_rs1_value\u000aisacov.rv32i_andi_cg.cp_immi_value\u000aisacov.rv32i_andi_cg.cross_rs1_immi_value\u000aisacov.rv32i_andi_cg.cp_rs1_toggle\u000aisacov.rv32i_andi_cg.cp_immi_toggle -p232 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp233 -sg15 -(lp234 -sg53 -(lp235 -sg13 -(dp236 -g56 -I0 -ssbtp237 -a(V002 -p238 -g1 -(g29 -g3 -Ntp239 -Rp240 -(dp241 -g8 -V002 -p242 -sg23 -VVP_ISA_F011_S003_I002 -p243 -sg35 -Vandi rd, rs1, imm[11:0]\u000ard = rs1 & Sext(imm[11:0])\u000aNote: this is a bitwise, not logical operation -p244 -sg37 -VISA\u000aChapter 2.4 -p245 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p246 -sg41 -Visacov.rv32i_andi_cg.cp_rd_value\u000aisacov.rv32i_andi_cg.cp_rd_toggle -p247 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp248 -sg15 -(lp249 -sg53 -(lp250 -sg13 -(dp251 -g56 -I0 -ssbtp252 -asg88 -(lp253 -sg53 -(lp254 -sg13 -(dp255 -sbtp256 -a(V004_SLTI -p257 -g1 -(g18 -g3 -Ntp258 -Rp259 -(dp260 -g22 -I3 -sg8 -g257 -sg23 -VVP_IP011_P004 -p261 -sg25 -(dp262 -sg12 -I4 -sg15 -(lp263 -(V000 -p264 -g1 -(g29 -g3 -Ntp265 -Rp266 -(dp267 -g8 -V000 -p268 -sg23 -VVP_ISA_F011_S004_I000 -p269 -sg35 -Vslti rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as signed numbers -p270 -sg37 -VISA\u000aChapter 2.4 -p271 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p272 -sg41 -Visacov.rv32i_slti_cg.cp_rs1\u000aisacov.rv32i_slti_cg.cp_rd\u000aisacov.rv32i_slti_cg.cp_rd_rs1_hazard -p273 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp274 -sg15 -(lp275 -sg53 -(lp276 -sg13 -(dp277 -g56 -I0 -ssbtp278 -a(V001 -p279 -g1 -(g29 -g3 -Ntp280 -Rp281 -(dp282 -g8 -V001 -p283 -sg23 -VVP_ISA_F011_S004_I001 -p284 -sg35 -Vslti rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as signed numbers -p285 -sg37 -VISA\u000aChapter 2.4 -p286 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p287 -sg41 -Visacov.rv32i_slti_cg.cp_rs1_value\u000aisacov.rv32i_slti_cg.cp_immi_value\u000aisacov.rv32i_slti_cg.cross_rs1_immi_value\u000aisacov.rv32i_slti_cg.cp_rs1_toggle\u000aisacov.rv32i_slti_cg.cp_immi_toggle -p288 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp289 -sg15 -(lp290 -sg53 -(lp291 -sg13 -(dp292 -g56 -I0 -ssbtp293 -a(V002 -p294 -g1 -(g29 -g3 -Ntp295 -Rp296 -(dp297 -g8 -V002 -p298 -sg23 -VVP_ISA_F011_S004_I002 -p299 -sg35 -Vslti rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as signed numbers -p300 -sg37 -VISA\u000aChapter 2.4 -p301 -sg39 -VOutput result:\u000a\u000ard value is in [0,1] -p302 -sg41 -Visacov.rv32i_slti_cg.cp_rd_value -p303 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp304 -sg15 -(lp305 -sg53 -(lp306 -sg13 -(dp307 -g56 -I0 -ssbtp308 -asg88 -(lp309 -sg53 -(lp310 -sg13 -(dp311 -sbtp312 -a(V005_SLTIU -p313 -g1 -(g18 -g3 -Ntp314 -Rp315 -(dp316 -g22 -I3 -sg8 -g313 -sg23 -VVP_IP011_P005 -p317 -sg25 -(dp318 -sg12 -I5 -sg15 -(lp319 -(V000 -p320 -g1 -(g29 -g3 -Ntp321 -Rp322 -(dp323 -g8 -V000 -p324 -sg23 -VVP_ISA_F011_S005_I000 -p325 -sg35 -Vsltiu rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as unsigned numbers -p326 -sg37 -VISA\u000aChapter 2.4 -p327 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p328 -sg41 -Visacov.rv32i_sltiu_cg.cp_rs1\u000aisacov.rv32i_sltiu_cg.cp_rd\u000aisacov.rv32i_sltiu_cg.cp_rd_rs1_hazard -p329 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp330 -sg15 -(lp331 -sg53 -(lp332 -sg13 -(dp333 -g56 -I0 -ssbtp334 -a(V001 -p335 -g1 -(g29 -g3 -Ntp336 -Rp337 -(dp338 -g8 -V001 -p339 -sg23 -VVP_ISA_F011_S005_I001 -p340 -sg35 -Vsltiu rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as unsigned numbers -p341 -sg37 -VISA\u000aChapter 2.4 -p342 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p343 -sg41 -Visacov.rv32i_sltiu_cg.cp_rs1_value\u000aisacov.rv32i_sltiu_cg.cp_immi_value\u000aisacov.rv32i_sltiu_cg.cross_rs1_immi_value\u000aisacov.rv32i_sltiu_cg.cp_rs1_toggle\u000aisacov.rv32i_sltiu_cg.cp_immi_toggle -p344 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp345 -sg15 -(lp346 -sg53 -(lp347 -sg13 -(dp348 -g56 -I0 -ssbtp349 -a(V002 -p350 -g1 -(g29 -g3 -Ntp351 -Rp352 -(dp353 -g8 -V002 -p354 -sg23 -VVP_ISA_F011_S005_I002 -p355 -sg35 -Vsltiu rd, rs1, imm[11:0]\u000ard = (rs1 < Sext(imm[11:0]) ? 1 : 0\u000aBoth imm and rs1 treated as unsigned numbers -p356 -sg37 -VISA\u000aChapter 2.4 -p357 -sg39 -VOutput result:\u000a\u000ard value is in [0,1] -p358 -sg41 -Visacov.rv32i_sltiu_cg.cp_rd_value -p359 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp360 -sg15 -(lp361 -sg53 -(lp362 -sg13 -(dp363 -g56 -I0 -ssbtp364 -asg88 -(lp365 -sg53 -(lp366 -sg13 -(dp367 -sbtp368 -a(V006_SLLI -p369 -g1 -(g18 -g3 -Ntp370 -Rp371 -(dp372 -g22 -I3 -sg8 -g369 -sg23 -VVP_IP011_P006 -p373 -sg25 -(dp374 -sg12 -I6 -sg15 -(lp375 -(V000 -p376 -g1 -(g29 -g3 -Ntp377 -Rp378 -(dp379 -g8 -V000 -p380 -sg23 -VVP_ISA_F011_S006_I000 -p381 -sg35 -Vslli rd, rs, imm[4:0]\u000ard = rs << imm[4:0]\u000aZeros are shirfted into lower bits -p382 -sg37 -VISA\u000aChapter 2.4 -p383 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p384 -sg41 -Visacov.rv32i_slli_cg.cp_rs1\u000aisacov.rv32i_slli_cg.cp_rd\u000aisacov.rv32i_slli_cg.cp_rd_rs1_hazard -p385 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp386 -sg15 -(lp387 -sg53 -(lp388 -sg13 -(dp389 -g56 -I0 -ssbtp390 -a(V001 -p391 -g1 -(g29 -g3 -Ntp392 -Rp393 -(dp394 -g8 -V001 -p395 -sg23 -VVP_ISA_F011_S006_I001 -p396 -sg35 -Vslli rd, rs, imm[4:0]\u000ard = rs << imm[4:0]\u000aZeros are shirfted into lower bits -p397 -sg37 -VISA\u000aChapter 2.4 -p398 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate shamt value is [0,31]\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled -p399 -sg41 -Visacov.rv32i_slli_cg.cp_rs1_value\u000aisacov.rv32i_slli_cg.cp_immi_value\u000aisacov.rv32i_slli_cg.cross_rs1_immi_value\u000aisacov.rv32i_slli_cg.cp_rs1_toggle -p400 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp401 -sg15 -(lp402 -sg53 -(lp403 -sg13 -(dp404 -g56 -I0 -ssbtp405 -a(V002 -p406 -g1 -(g29 -g3 -Ntp407 -Rp408 -(dp409 -g8 -V002 -p410 -sg23 -VVP_ISA_F011_S006_I002 -p411 -sg35 -Vslli rd, rs, imm[4:0]\u000ard = rs << imm[4:0]\u000aZeros are shirfted into lower bits -p412 -sg37 -VISA\u000aChapter 2.4 -p413 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p414 -sg41 -Visacov.rv32i_slli_cg.cp_rd_value\u000aisacov.rv32i_slli_cg.cp_rd_toggle -p415 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp416 -sg15 -(lp417 -sg53 -(lp418 -sg13 -(dp419 -g56 -I0 -ssbtp420 -asg88 -(lp421 -sg53 -(lp422 -sg13 -(dp423 -sbtp424 -a(V007_SRLI -p425 -g1 -(g18 -g3 -Ntp426 -Rp427 -(dp428 -g22 -I4 -sg8 -g425 -sg23 -VVP_IP011_P007 -p429 -sg25 -(dp430 -sg12 -I7 -sg15 -(lp431 -(V000 -p432 -g1 -(g29 -g3 -Ntp433 -Rp434 -(dp435 -g8 -V000 -p436 -sg23 -VVP_ISA_F011_S007_I000 -p437 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits -p438 -sg37 -VISA\u000aChapter 2.4 -p439 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p440 -sg41 -Visacov.rv32i_srli_cg.cp_rs1\u000aisacov.rv32i_srli_cg.cp_rd\u000aisacov.rv32i_srli_cg.cp_rd_rs1_hazard -p441 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp442 -sg15 -(lp443 -sg53 -(lp444 -sg13 -(dp445 -g56 -I0 -ssbtp446 -a(V001 -p447 -g1 -(g29 -g3 -Ntp448 -Rp449 -(dp450 -g8 -g447 -sg23 -VVP_ISA_F011_S007_I001 -p451 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits -p452 -sg37 -VISA\u000aChapter 2.4 -p453 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate shamt value is [0,31]\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled -p454 -sg41 -Visacov.rv32i_srli_cg.cp_rs1_value\u000aisacov.rv32i_srli_cg.cp_immi_value\u000aisacov.rv32i_srli_cg.cross_rs1_immi_value\u000aisacov.rv32i_srli_cg.cp_rs1_toggle -p455 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp456 -sg15 -(lp457 -sg53 -(lp458 -sg13 -(dp459 -g56 -I0 -ssbtp460 -a(V002 -p461 -g1 -(g29 -g3 -Ntp462 -Rp463 -(dp464 -g8 -g461 -sg23 -VVP_ISA_F011_S007_I002 -p465 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits -p466 -sg37 -VISA\u000aChapter 2.4 -p467 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p468 -sg41 -Visacov.rv32i_srli_cg.cp_rd_value\u000aisacov.rv32i_srli_cg.cp_rd_toggle -p469 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp470 -sg15 -(lp471 -sg53 -(lp472 -sg13 -(dp473 -g56 -I0 -ssbtp474 -asg88 -(lp475 -sg53 -(lp476 -sg13 -(dp477 -sbtp478 -a(V008_SRAI -p479 -g1 -(g18 -g3 -Ntp480 -Rp481 -(dp482 -g22 -I3 -sg8 -g479 -sg23 -VVP_IP011_P008 -p483 -sg25 -(dp484 -sg12 -I8 -sg15 -(lp485 -(V000 -p486 -g1 -(g29 -g3 -Ntp487 -Rp488 -(dp489 -g8 -V000 -p490 -sg23 -VVP_ISA_F011_S008_I000 -p491 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aThe original sign bit is copied into the vacated upper bits -p492 -sg37 -VISA\u000aChapter 2.4 -p493 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p494 -sg41 -Visacov.rv32i_srai_cg.cp_rs1\u000aisacov.rv32i_srai_cg.cp_rd\u000aisacov.rv32i_srai_cg.cp_rd_rs1_hazard -p495 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp496 -sg15 -(lp497 -sg53 -(lp498 -sg13 -(dp499 -g56 -I0 -ssbtp500 -a(V001 -p501 -g1 -(g29 -g3 -Ntp502 -Rp503 -(dp504 -g8 -V001 -p505 -sg23 -VVP_ISA_F011_S008_I001 -p506 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aThe original sign bit is copied into the vacated upper bits -p507 -sg37 -VISA\u000aChapter 2.4 -p508 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate shamt value is [0,31]\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled -p509 -sg41 -Visacov.rv32i_srai_cg.cp_rs1_value\u000aisacov.rv32i_srai_cg.cp_immi_value\u000aisacov.rv32i_srai_cg.cross_rs1_immi_value\u000aisacov.rv32i_srai_cg.cp_rs1_toggle -p510 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp511 -sg15 -(lp512 -sg53 -(lp513 -sg13 -(dp514 -g56 -I0 -ssbtp515 -a(V002 -p516 -g1 -(g29 -g3 -Ntp517 -Rp518 -(dp519 -g8 -V002 -p520 -sg23 -VVP_ISA_F011_S008_I002 -p521 -sg35 -Vsrli rd, rs, imm[4:0]\u000ard = rs >> imm[4:0]\u000aZeros are shirfted into upper bits -p522 -sg37 -VISA\u000aChapter 2.4 -p523 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p524 -sg41 -Visacov.rv32i_srai_cg.cp_rd_value\u000aisacov.rv32i_srai_cg.cp_rd_toggle -p525 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp526 -sg15 -(lp527 -sg53 -(lp528 -sg13 -(dp529 -g56 -I0 -ssbtp530 -asg88 -(lp531 -sg53 -(lp532 -sg13 -(dp533 -sbtp534 -a(V009_LUI -p535 -g1 -(g18 -g3 -Ntp536 -Rp537 -(dp538 -g22 -I3 -sg8 -g535 -sg23 -VVP_IP011_P009 -p539 -sg25 -(dp540 -sg12 -I9 -sg15 -(lp541 -(V000 -p542 -g1 -(g29 -g3 -Ntp543 -Rp544 -(dp545 -g8 -V000 -p546 -sg23 -VVP_ISA_F011_S009_I000 -p547 -sg35 -Vlui rd, imm[19:0]\u000ard = imm[19:0] << 12\u000ard[11:0] is zero-filled. -p548 -sg37 -VISA\u000aChapter 2.4 -p549 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p550 -sg41 -Visacov.rv32i_lui_cg.cp_rd -p551 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp552 -sg15 -(lp553 -sg53 -(lp554 -sg13 -(dp555 -g56 -I0 -ssbtp556 -a(V001 -p557 -g1 -(g29 -g3 -Ntp558 -Rp559 -(dp560 -g8 -V001 -p561 -sg23 -VVP_ISA_F011_S009_I001 -p562 -sg35 -Vlui rd, imm[19:0]\u000ard = imm[19:0] << 12\u000ard[11:0] is zero-filled. -p563 -sg37 -VISA\u000aChapter 2.4 -p564 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate value is zero and non-zero\u000aAll bits of immu are toggled -p565 -sg41 -Visacov.rv32i_lui_cg.cp_immu_value\u000aisacov.rv32i_lui_cg.cp_immu_toggle -p566 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp567 -sg15 -(lp568 -sg53 -(lp569 -sg13 -(dp570 -g56 -I0 -ssbtp571 -a(V002 -p572 -g1 -(g29 -g3 -Ntp573 -Rp574 -(dp575 -g8 -V002 -p576 -sg23 -VVP_ISA_F011_S009_I002 -p577 -sg35 -Vlui rd, imm[19:0]\u000ard = imm[19:0] << 12\u000ard[11:0] is zero-filled. -p578 -sg37 -VISA\u000aChapter 2.4 -p579 -sg39 -VOutput result:\u000a\u000ard value is zero and non-zero\u000aAll bits of rd[31:12] are toggled (11:0 are deposited with 0) -p580 -sg41 -Visacov.rv32i_lui_cg.cp_rd_value\u000aisacov.rv32i_lui_cg.cp_rd_toggle -p581 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp582 -sg15 -(lp583 -sg53 -(lp584 -sg13 -(dp585 -g56 -I0 -ssbtp586 -asg88 -(lp587 -sg53 -(lp588 -sg13 -(dp589 -sbtp590 -a(V010_AUIPC -p591 -g1 -(g18 -g3 -Ntp592 -Rp593 -(dp594 -g22 -I3 -sg8 -g591 -sg23 -VVP_IP011_P010 -p595 -sg25 -(dp596 -sg12 -I10 -sg15 -(lp597 -(V000 -p598 -g1 -(g29 -g3 -Ntp599 -Rp600 -(dp601 -g8 -V000 -p602 -sg23 -VVP_ISA_F011_S010_I000 -p603 -sg35 -Vauipc rd, imm[19:0]\u000ard = pc + (imm[19:0] << 12)\u000apc is address of auipc instruction\u000a\u000aAssumption: arithmetic overflow is lost and ignored. -p604 -sg37 -VISA\u000aChapter 2.4 -p605 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p606 -sg41 -Visacov.rv32i_auipc_cg.cp_rd -p607 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp608 -sg15 -(lp609 -sg53 -(lp610 -sg13 -(dp611 -g56 -I0 -ssbtp612 -a(V001 -p613 -g1 -(g29 -g3 -Ntp614 -Rp615 -(dp616 -g8 -V001 -p617 -sg23 -VVP_ISA_F011_S010_I001 -p618 -sg35 -Vauipc rd, imm[19:0]\u000ard = pc + (imm[19:0] << 12)\u000apc is address of auipc instruction\u000a\u000aAssumption: arithmetic overflow is lost and ignored. -p619 -sg37 -VISA\u000aChapter 2.4 -p620 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000aimmediate value is zero and non-zero\u000aAll bits of immu are toggled -p621 -sg41 -Visacov.rv32i_auipc_cg.cp_immu_value\u000aisacov.rv32i_auipc_cg.cp_immu_toggle -p622 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp623 -sg15 -(lp624 -sg53 -(lp625 -sg13 -(dp626 -g56 -I0 -ssbtp627 -a(V002 -p628 -g1 -(g29 -g3 -Ntp629 -Rp630 -(dp631 -g8 -V002 -p632 -sg23 -VVP_ISA_F011_S010_I002 -p633 -sg35 -Vauipc rd, imm[19:0]\u000ard = pc + (imm[19:0] << 12)\u000apc is address of auipc instruction\u000a\u000aAssumption: arithmetic overflow is lost and ignored. -p634 -sg37 -VISA\u000aChapter 2.4 -p635 -sg39 -VOutput result:\u000a\u000ard value is zero and non-zero\u000aAll bits of rd[31:12] are toggled (11:0 are deposited with 0) -p636 -sg41 -Visacov.rv32i_auipc_cg.cp_rd_value\u000aisacov.rv32i_auipc_cg.cp_rd_toggle -p637 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp638 -sg15 -(lp639 -sg53 -(lp640 -sg13 -(dp641 -g56 -I0 -ssbtp642 -asg88 -(lp643 -sg53 -(lp644 -sg13 -(dp645 -sbtp646 -asVrfu_list_0 -p647 -(lp648 -sg88 -(lp649 -sVvptool_gitrev -p650 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p651 -sVio_fmt_gitrev -p652 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p653 -sVconfig_gitrev -p654 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p655 -sVymlcfg_gitrev -p656 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p657 -sbtp658 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml new file mode 100644 index 0000000000..70b22805da --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml @@ -0,0 +1,697 @@ +!Feature +next_elt_id: 11 +name: RV32I Register-Immediate Instructions +id: 0 +display_order: 0 +subfeatures: !!omap +- 000_ADDI: !Subfeature + name: 000_ADDI + tag: VP_IP011_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S000_I000 + description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ + \ overflow is lost and ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_addi_cg.cp_rs1\nisacov.rv32i_addi_cg.cp_rd\nisacov.rv32i_addi_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S000_I001 + description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ + \ overflow is lost and ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_addi_cg.cp_rs1_value\nisacov.rv32i_addi_cg.cp_immi_value\n\ + isacov.rv32i_addi_cg.cross_rs1_immi_value\nisacov.rv32i_addi_cg.cp_rs1_toggle\n\ + isacov.rv32i_addi_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S000_I002 + description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ + \ overflow is lost and ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_addi_cg.cp_rd_value\nisacov.rv32i_addi_cg.cp_rd_toggle" + comments: '' +- 001_XORI: !Subfeature + name: 001_XORI + tag: VP_IP011_P001 + next_elt_id: 5 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S001_I000 + description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xori_cg.cp_rs1\nisacov.rv32i_xori_cg.cp_rd\nisacov.rv32i_xori_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S001_I001 + description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xori_cg.cp_rs1_value\nisacov.rv32i_xori_cg.cp_immi_value\n\ + isacov.rv32i_xori_cg.cross_rs1_immi_value\nisacov.rv32i_xori_cg.cp_rs1_toggle\n\ + isacov.rv32i_xori_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S001_I002 + description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xori_cg.cp_rd_value\nisacov.rv32i_xori_cg.cp_rd_toggle" + comments: '' +- 002_ORI: !Subfeature + name: 002_ORI + tag: VP_IP011_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S002_I000 + description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_ori_cg.cp_rs1\nisacov.rv32i_ori_cg.cp_rd\nisacov.rv32i_ori_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S002_I001 + description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_ori_cg.cp_rs1_value\nisacov.rv32i_ori_cg.cp_immi_value\n\ + isacov.rv32i_ori_cg.cross_rs1_immi_value\nisacov.rv32i_ori_cg.cp_rs1_toggle\n\ + isacov.rv32i_ori_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S002_I002 + description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_ori_cg.cp_rd_value\nisacov.rv32i_ori_cg.cp_rd_toggle" + comments: '' +- 003_ANDI: !Subfeature + name: 003_ANDI + tag: VP_IP011_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S003_I000 + description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ + \ this is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_andi_cg.cp_rs1\nisacov.rv32i_andi_cg.cp_rd\nisacov.rv32i_andi_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S003_I001 + description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ + \ this is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_andi_cg.cp_rs1_value\nisacov.rv32i_andi_cg.cp_immi_value\n\ + isacov.rv32i_andi_cg.cross_rs1_immi_value\nisacov.rv32i_andi_cg.cp_rs1_toggle\n\ + isacov.rv32i_andi_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S003_I002 + description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ + \ this is a bitwise, not logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_andi_cg.cp_rd_value\nisacov.rv32i_andi_cg.cp_rd_toggle" + comments: '' +- 004_SLTI: !Subfeature + name: 004_SLTI + tag: VP_IP011_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S004_I000 + description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ + Both imm and rs1 treated as signed numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slti_cg.cp_rs1\nisacov.rv32i_slti_cg.cp_rd\nisacov.rv32i_slti_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S004_I001 + description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ + Both imm and rs1 treated as signed numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slti_cg.cp_rs1_value\nisacov.rv32i_slti_cg.cp_immi_value\n\ + isacov.rv32i_slti_cg.cross_rs1_immi_value\nisacov.rv32i_slti_cg.cp_rs1_toggle\n\ + isacov.rv32i_slti_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S004_I002 + description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ + Both imm and rs1 treated as signed numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is in [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_slti_cg.cp_rd_value + comments: '' +- 005_SLTIU: !Subfeature + name: 005_SLTIU + tag: VP_IP011_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S005_I000 + description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ + \ 0\nBoth imm and rs1 treated as unsigned numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltiu_cg.cp_rs1\nisacov.rv32i_sltiu_cg.cp_rd\n\ + isacov.rv32i_sltiu_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S005_I001 + description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ + \ 0\nBoth imm and rs1 treated as unsigned numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltiu_cg.cp_rs1_value\nisacov.rv32i_sltiu_cg.cp_immi_value\n\ + isacov.rv32i_sltiu_cg.cross_rs1_immi_value\nisacov.rv32i_sltiu_cg.cp_rs1_toggle\n\ + isacov.rv32i_sltiu_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S005_I002 + description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ + \ 0\nBoth imm and rs1 treated as unsigned numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is in [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_sltiu_cg.cp_rd_value + comments: '' +- 006_SLLI: !Subfeature + name: 006_SLLI + tag: VP_IP011_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S006_I000 + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + \ into lower bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slli_cg.cp_rs1\nisacov.rv32i_slli_cg.cp_rd\nisacov.rv32i_slli_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S006_I001 + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + \ into lower bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\ + \ zero values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slli_cg.cp_rs1_value\nisacov.rv32i_slli_cg.cp_immi_value\n\ + isacov.rv32i_slli_cg.cross_rs1_immi_value\nisacov.rv32i_slli_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S006_I002 + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + \ into lower bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slli_cg.cp_rd_value\nisacov.rv32i_slli_cg.cp_rd_toggle" + comments: '' +- 007_SRLI: !Subfeature + name: 007_SRLI + tag: VP_IP011_P007 + next_elt_id: 4 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S007_I000 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srli_cg.cp_rs1\nisacov.rv32i_srli_cg.cp_rd\nisacov.rv32i_srli_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S007_I001 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\ + \ zero values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srli_cg.cp_rs1_value\nisacov.rv32i_srli_cg.cp_immi_value\n\ + isacov.rv32i_srli_cg.cross_rs1_immi_value\nisacov.rv32i_srli_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S007_I002 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srli_cg.cp_rd_value\nisacov.rv32i_srli_cg.cp_rd_toggle" + comments: '' +- 008_SRAI: !Subfeature + name: 008_SRAI + tag: VP_IP011_P008 + next_elt_id: 3 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S008_I000 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\ + \ bit is copied into the vacated upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srai_cg.cp_rs1\nisacov.rv32i_srai_cg.cp_rd\nisacov.rv32i_srai_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S008_I001 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\ + \ bit is copied into the vacated upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\ + \ zero values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srai_cg.cp_rs1_value\nisacov.rv32i_srai_cg.cp_immi_value\n\ + isacov.rv32i_srai_cg.cross_rs1_immi_value\nisacov.rv32i_srai_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S008_I002 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srai_cg.cp_rd_value\nisacov.rv32i_srai_cg.cp_rd_toggle" + comments: '' +- 009_LUI: !Subfeature + name: 009_LUI + tag: VP_IP011_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S009_I000 + description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_lui_cg.cp_rd + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S009_I001 + description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ value is zero and non-zero\nAll bits of immu are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lui_cg.cp_immu_value\nisacov.rv32i_lui_cg.cp_immu_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S009_I002 + description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is zero and non-zero\nAll bits of\ + \ rd[31:12] are toggled (11:0 are deposited with 0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lui_cg.cp_rd_value\nisacov.rv32i_lui_cg.cp_rd_toggle" + comments: '' +- 010_AUIPC: !Subfeature + name: 010_AUIPC + tag: VP_IP011_P010 + next_elt_id: 3 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F011_S010_I000 + description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ + \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_auipc_cg.cp_rd + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F011_S010_I001 + description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ + \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ value is zero and non-zero\nAll bits of immu are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_auipc_cg.cp_immu_value\nisacov.rv32i_auipc_cg.cp_immu_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F011_S010_I002 + description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ + \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is zero and non-zero\nAll bits of\ + \ rd[31:12] are toggled (11:0 are deposited with 0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_auipc_cg.cp_rd_value\nisacov.rv32i_auipc_cg.cp_rd_toggle" + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck deleted file mode 100644 index 4c356dddb2..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.pck +++ /dev/null @@ -1,1828 +0,0 @@ -(VRV32I Register-Register Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I10 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I1 -sVwid_order -p12 -I1 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_ADD -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I4 -sg8 -g17 -sVtag -p23 -VVP_IP001_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F001_S000_I000 -p34 -sVdescription -p35 -Vadd rd, rs1, rs2\u000ard = rs1 + rs2\u000aArithmetic overflow is lost and ignored -p36 -sVpurpose -p37 -VISA\u000aChapter 2.4 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32i_add_cg.cp_rs1\u000aisacov.rv32i_add_cg.cp_rs2\u000aisacov.rv32i_add_cg.cp_rd\u000aisacov.rv32i_add_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_add_cg.cp_rd_rs2_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -g58 -sg23 -VVP_ISA_F001_S000_I001 -p62 -sg35 -Vadd rd, rs1, rs2\u000ard = rs1 + rs2\u000aArithmetic overflow is lost and ignored -p63 -sg37 -VISA\u000aChapter 2.4 -p64 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p65 -sg41 -Visacov.rv32i_add_cg.cp_rs1_value\u000aisacov.rv32i_add_cg.cp_rs2_value\u000aisacov.rv32i_add_cg.cross_rs1_rs2_value\u000aisacov.rv32i_add_cg.cp_rs1_toggle\u000aisacov.rv32i_add_cg.cp_rs2_toggle -p66 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp67 -sg15 -(lp68 -sg53 -(lp69 -sg13 -(dp70 -g56 -I0 -ssbtp71 -a(V002 -p72 -g1 -(g29 -g3 -Ntp73 -Rp74 -(dp75 -g8 -g72 -sg23 -VVP_ISA_F001_S000_I002 -p76 -sg35 -Vadd rd, rs1, rs2\u000ard = rs1 + rs2\u000aArithmetic overflow is lost and ignored -p77 -sg37 -VISA\u000aChapter 2.4 -p78 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p79 -sg41 -Visacov.rv32i_add_cg.cp_rd_value\u000aisacov.rv32i_add_cg.cp_rd_toggle -p80 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp81 -sg15 -(lp82 -sg53 -(lp83 -sg13 -(dp84 -g56 -I0 -ssbtp85 -asVrfu_list_1 -p86 -(lp87 -sg53 -(lp88 -sg13 -(dp89 -sbtp90 -a(V001_SUB -p91 -g1 -(g18 -g3 -Ntp92 -Rp93 -(dp94 -g22 -I3 -sg8 -g91 -sg23 -VVP_IP001_P001 -p95 -sg25 -(dp96 -sg12 -I1 -sg15 -(lp97 -(V000 -p98 -g1 -(g29 -g3 -Ntp99 -Rp100 -(dp101 -g8 -V000 -p102 -sg23 -VVP_ISA_F001_S001_I000 -p103 -sg35 -Vsub rd, rs1, rs2\u000ard = rs1 - rs2\u000aArithmetic underflow is ignored -p104 -sg37 -VISA\u000aChapter 2.4 -p105 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p106 -sg41 -Visacov.rv32i_sub_cg.cp_rs1\u000aisacov.rv32i_sub_cg.cp_rs2\u000aisacov.rv32i_sub_cg.cp_rd\u000aisacov.rv32i_sub_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_sub_cg.cp_rd_rs2_hazard -p107 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp108 -sg15 -(lp109 -sg53 -(lp110 -sg13 -(dp111 -g56 -I0 -ssbtp112 -a(V001 -p113 -g1 -(g29 -g3 -Ntp114 -Rp115 -(dp116 -g8 -V001 -p117 -sg23 -VVP_ISA_F001_S001_I001 -p118 -sg35 -Vsub rd, rs1, rs2\u000ard = rs1 - rs2\u000aArithmetic underflow is ignored -p119 -sg37 -VISA\u000aChapter 2.4 -p120 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p121 -sg41 -Visacov.rv32i_sub_cg.cp_rs1_value\u000aisacov.rv32i_sub_cg.cp_rs2_value\u000aisacov.rv32i_sub_cg.cross_rs1_rs2_value\u000aisacov.rv32i_sub_cg.cp_rs1_toggle\u000aisacov.rv32i_sub_cg.cp_rs2_toggle -p122 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp123 -sg15 -(lp124 -sg53 -(lp125 -sg13 -(dp126 -g56 -I0 -ssbtp127 -a(V002 -p128 -g1 -(g29 -g3 -Ntp129 -Rp130 -(dp131 -g8 -V002 -p132 -sg23 -VVP_ISA_F001_S001_I002 -p133 -sg35 -Vsub rd, rs1, rs2\u000ard = rs1 - rs2\u000aArithmetic underflow is ignored -p134 -sg37 -VISA\u000aChapter 2.4 -p135 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p136 -sg41 -Visacov.rv32i_sub_cg.cp_rd_value\u000aisacov.rv32i_sub_cg.cp_rd_toggle -p137 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp138 -sg15 -(lp139 -sg53 -(lp140 -sg13 -(dp141 -g56 -I0 -ssbtp142 -asg86 -(lp143 -sg53 -(lp144 -sg13 -(dp145 -sbtp146 -a(V002_AND -p147 -g1 -(g18 -g3 -Ntp148 -Rp149 -(dp150 -g22 -I3 -sg8 -g147 -sg23 -VVP_IP001_P002 -p151 -sg25 -(dp152 -sg12 -I2 -sg15 -(lp153 -(V000 -p154 -g1 -(g29 -g3 -Ntp155 -Rp156 -(dp157 -g8 -V000 -p158 -sg23 -VVP_ISA_F001_S002_I000 -p159 -sg35 -Vand rd, rs1, rs2\u000ard = rs1 & rs2\u000aNote: this is a bitwise, not logical operation -p160 -sg37 -VISA\u000aChapter 2.4 -p161 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p162 -sg41 -Visacov.rv32i_and_cg.cp_rs1\u000aisacov.rv32i_and_cg.cp_rs2\u000aisacov.rv32i_and_cg.cp_rd\u000aisacov.rv32i_and_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_and_cg.cp_rd_rs2_hazard\u000aisacov.rv32i_and_cg.cp_rs1\u000aisacov.rv32i_and_cg.cp_rs2\u000aisacov.rv32i_and_cg.cp_rd\u000aisacov.rv32i_and_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_and_cg.cp_rd_rs2_hazard -p163 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp164 -sg15 -(lp165 -sg53 -(lp166 -sg13 -(dp167 -g56 -I0 -ssbtp168 -a(V001 -p169 -g1 -(g29 -g3 -Ntp170 -Rp171 -(dp172 -g8 -V001 -p173 -sg23 -VVP_ISA_F001_S002_I001 -p174 -sg35 -Vand rd, rs1, rs2\u000ard = rs1 & rs2\u000aNote: this is a bitwise, not logical operation -p175 -sg37 -VISA\u000aChapter 2.4 -p176 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p177 -sg41 -Visacov.rv32i_and_cg.cp_rs1_value\u000aisacov.rv32i_and_cg.cp_rs2_value\u000aisacov.rv32i_and_cg.cross_rs1_rs2_value\u000aisacov.rv32i_and_cg.cp_rs1_toggle\u000aisacov.rv32i_and_cg.cp_rs2_toggle -p178 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp179 -sg15 -(lp180 -sg53 -(lp181 -sg13 -(dp182 -g56 -I0 -ssbtp183 -a(V002 -p184 -g1 -(g29 -g3 -Ntp185 -Rp186 -(dp187 -g8 -V002 -p188 -sg23 -VVP_ISA_F001_S002_I002 -p189 -sg35 -Vand rd, rs1, rs2\u000ard = rs1 & rs2\u000aNote: this is a bitwise, not logical operation -p190 -sg37 -VISA\u000aChapter 2.4 -p191 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p192 -sg41 -Visacov.rv32i_and_cg.cp_rd_value\u000aisacov.rv32i_and_cg.cp_rd_toggle -p193 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp194 -sg15 -(lp195 -sg53 -(lp196 -sg13 -(dp197 -g56 -I0 -ssbtp198 -asg86 -(lp199 -sg53 -(lp200 -sg13 -(dp201 -sbtp202 -a(V003_OR -p203 -g1 -(g18 -g3 -Ntp204 -Rp205 -(dp206 -g22 -I3 -sg8 -g203 -sg23 -VVP_IP001_P003 -p207 -sg25 -(dp208 -sg12 -I3 -sg15 -(lp209 -(V000 -p210 -g1 -(g29 -g3 -Ntp211 -Rp212 -(dp213 -g8 -V000 -p214 -sg23 -VVP_ISA_F001_S003_I000 -p215 -sg35 -Vor rd, rs1, rs2\u000ard = rs1 | rs2\u000aNote: this is a bitwise, not logical operation -p216 -sg37 -VISA\u000aChapter 2.4 -p217 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p218 -sg41 -Visacov.rv32i_or_cg.cp_rs1\u000aisacov.rv32i_or_cg.cp_rs2\u000aisacov.rv32i_or_cg.cp_rd\u000aisacov.rv32i_or_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_or_cg.cp_rd_rs2_hazard -p219 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp220 -sg15 -(lp221 -sg53 -(lp222 -sg13 -(dp223 -g56 -I0 -ssbtp224 -a(V001 -p225 -g1 -(g29 -g3 -Ntp226 -Rp227 -(dp228 -g8 -V001 -p229 -sg23 -VVP_ISA_F001_S003_I001 -p230 -sg35 -Vor rd, rs1, rs2\u000ard = rs1 | rs2\u000aNote: this is a bitwise, not logical operation -p231 -sg37 -VISA\u000aChapter 2.4 -p232 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p233 -sg41 -Visacov.rv32i_or_cg.cp_rs1_value\u000aisacov.rv32i_or_cg.cp_rs2_value\u000aisacov.rv32i_or_cg.cross_rs1_rs2_value\u000aisacov.rv32i_or_cg.cp_rs1_toggle\u000aisacov.rv32i_or_cg.cp_rs2_toggle -p234 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp235 -sg15 -(lp236 -sg53 -(lp237 -sg13 -(dp238 -g56 -I0 -ssbtp239 -a(V002 -p240 -g1 -(g29 -g3 -Ntp241 -Rp242 -(dp243 -g8 -V002 -p244 -sg23 -VVP_ISA_F001_S003_I002 -p245 -sg35 -Vor rd, rs1, rs2\u000ard = rs1 | rs2\u000aNote: this is a bitwise, not logical operation -p246 -sg37 -VISA\u000aChapter 2.4 -p247 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p248 -sg41 -Visacov.rv32i_or_cg.cp_rd_value\u000aisacov.rv32i_or_cg.cp_rd_toggle -p249 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp250 -sg15 -(lp251 -sg53 -(lp252 -sg13 -(dp253 -g56 -I0 -ssbtp254 -asg86 -(lp255 -sg53 -(lp256 -sg13 -(dp257 -sbtp258 -a(V004_XOR -p259 -g1 -(g18 -g3 -Ntp260 -Rp261 -(dp262 -g22 -I3 -sg8 -g259 -sg23 -VVP_IP001_P004 -p263 -sg25 -(dp264 -sg12 -I4 -sg15 -(lp265 -(V000 -p266 -g1 -(g29 -g3 -Ntp267 -Rp268 -(dp269 -g8 -V000 -p270 -sg23 -VVP_ISA_F001_S004_I000 -p271 -sg35 -Vxor rd, rs1, rs2\u000ard = rs1 ^ rs2\u000aNote: this is a bitwise, not logical operation -p272 -sg37 -VISA\u000aChapter 2.4 -p273 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p274 -sg41 -Visacov.rv32i_xor_cg.cp_rs1\u000aisacov.rv32i_xor_cg.cp_rs2\u000aisacov.rv32i_xor_cg.cp_rd\u000aisacov.rv32i_xor_cg.rd_rs1_hazard\u000aisacov.rv32i_xor_cg.rd_rs2_hazard -p275 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp276 -sg15 -(lp277 -sg53 -(lp278 -sg13 -(dp279 -g56 -I0 -ssbtp280 -a(V001 -p281 -g1 -(g29 -g3 -Ntp282 -Rp283 -(dp284 -g8 -V001 -p285 -sg23 -VVP_ISA_F001_S004_I001 -p286 -sg35 -Vxor rd, rs1, rs2\u000ard = rs1 ^ rs2\u000aNote: this is a bitwise, not logical operation -p287 -sg37 -VISA\u000aChapter 2.4 -p288 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p289 -sg41 -Visacov.rv32i_xor_cg.cp_rs1_value\u000aisacov.rv32i_xor_cg.cp_rs2_value\u000aisacov.rv32i_xor_cg.cross_rs1_rs2_value\u000aisacov.rv32i_xor_cg.cp_rs1_toggle\u000aisacov.rv32i_xor_cg.cp_rs2_toggle -p290 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp291 -sg15 -(lp292 -sg53 -(lp293 -sg13 -(dp294 -g56 -I0 -ssbtp295 -a(V002 -p296 -g1 -(g29 -g3 -Ntp297 -Rp298 -(dp299 -g8 -V002 -p300 -sg23 -VVP_ISA_F001_S004_I002 -p301 -sg35 -Vxor rd, rs1, rs2\u000ard = rs1 ^ rs2\u000aNote: this is a bitwise, not logical operation -p302 -sg37 -VISA\u000aChapter 2.4 -p303 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p304 -sg41 -Visacov.rv32i_xor_cg.cp_rd_value\u000aisacov.rv32i_xor_cg.cp_rd_toggle -p305 -sg43 -I-1 -sg44 -I-1 -sg45 -I-1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp306 -sg15 -(lp307 -sg53 -(lp308 -sg13 -(dp309 -g56 -I0 -ssbtp310 -asg86 -(lp311 -sg53 -(lp312 -sg13 -(dp313 -sbtp314 -a(V005_SLT -p315 -g1 -(g18 -g3 -Ntp316 -Rp317 -(dp318 -g22 -I3 -sg8 -g315 -sg23 -VVP_IP001_P005 -p319 -sg25 -(dp320 -sg12 -I5 -sg15 -(lp321 -(V000 -p322 -g1 -(g29 -g3 -Ntp323 -Rp324 -(dp325 -g8 -V000 -p326 -sg23 -VVP_ISA_F001_S005_I000 -p327 -sg35 -Vslt rd, rs1, rs2\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 ad rs2 treated as signed numbers -p328 -sg37 -VISA\u000aChapter 2.4 -p329 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p330 -sg41 -Visacov.rv32i_slt_cg.cp_rs1\u000aisacov.rv32i_slt_cg.cp_rs2\u000aisacov.rv32i_slt_cg.cp_rd\u000aisacov.rv32i_slt_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_slt_cg.cp_rd_rs2_hazard -p331 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp332 -sg15 -(lp333 -sg53 -(lp334 -sg13 -(dp335 -g56 -I0 -ssbtp336 -a(V001 -p337 -g1 -(g29 -g3 -Ntp338 -Rp339 -(dp340 -g8 -V001 -p341 -sg23 -VVP_ISA_F001_S005_I001 -p342 -sg35 -Vslt rd, rs1, rs2\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 ad rs2 treated as signed numbers -p343 -sg37 -VISA\u000aChapter 2.4 -p344 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p345 -sg41 -Visacov.rv32i_slt_cg.cp_rs1_value\u000aisacov.rv32i_slt_cg.cp_rs2_value\u000aisacov.rv32i_slt_cg.cross_rs1_rs2_value\u000aisacov.rv32i_slt_cg.cp_rs1_toggle\u000aisacov.rv32i_slt_cg.cp_rs2_toggle -p346 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp347 -sg15 -(lp348 -sg53 -(lp349 -sg13 -(dp350 -g56 -I0 -ssbtp351 -a(V002 -p352 -g1 -(g29 -g3 -Ntp353 -Rp354 -(dp355 -g8 -V002 -p356 -sg23 -VVP_ISA_F001_S005_I002 -p357 -sg35 -Vslt rd, rs1, rs2\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 ad rs2 treated as signed numbers -p358 -sg37 -VISA\u000aChapter 2.4 -p359 -sg39 -VOutput result:\u000a\u000ard value is [0,1] -p360 -sg41 -Visacov.rv32i_slt_cg.cp_rd_value -p361 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp362 -sg15 -(lp363 -sg53 -(lp364 -sg13 -(dp365 -g56 -I0 -ssbtp366 -asg86 -(lp367 -sg53 -(lp368 -sg13 -(dp369 -sbtp370 -a(V006_SLTU -p371 -g1 -(g18 -g3 -Ntp372 -Rp373 -(dp374 -g22 -I3 -sg8 -g371 -sg23 -VVP_IP001_P006 -p375 -sg25 -(dp376 -sg12 -I6 -sg15 -(lp377 -(V000 -p378 -g1 -(g29 -g3 -Ntp379 -Rp380 -(dp381 -g8 -V000 -p382 -sg23 -VVP_ISA_F001_S006_I000 -p383 -sg35 -Vsltu rd, rs1, imm[11:0]\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 and rs2 treated as unsigned numbers -p384 -sg37 -VISA\u000aChapter 2.4 -p385 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p386 -sg41 -Visacov.rv32i_sltu_cg.cp_rs1\u000aisacov.rv32i_sltu_cg.cp_rs2\u000aisacov.rv32i_sltu_cg.cp_rd\u000aisacov.rv32i_sltu_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_sltu_cg.cp_rd_rs2_hazard -p387 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp388 -sg15 -(lp389 -sg53 -(lp390 -sg13 -(dp391 -g56 -I0 -ssbtp392 -a(V001 -p393 -g1 -(g29 -g3 -Ntp394 -Rp395 -(dp396 -g8 -V001 -p397 -sg23 -VVP_ISA_F001_S006_I001 -p398 -sg35 -Vsltu rd, rs1, imm[11:0]\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 and rs2 treated as unsigned numbers -p399 -sg37 -VISA\u000aChapter 2.4 -p400 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p401 -sg41 -Visacov.rv32i_sltu_cg.cp_rs1_value\u000aisacov.rv32i_sltu_cg.cp_rs2_value\u000aisacov.rv32i_sltu_cg.cross_rs1_rs2_value\u000aisacov.rv32i_sltu_cg.cp_rs1_toggle\u000aisacov.rv32i_sltu_cg.cp_rs2_toggle -p402 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp403 -sg15 -(lp404 -sg53 -(lp405 -sg13 -(dp406 -g56 -I0 -ssbtp407 -a(V002 -p408 -g1 -(g29 -g3 -Ntp409 -Rp410 -(dp411 -g8 -V002 -p412 -sg23 -VVP_ISA_F001_S006_I002 -p413 -sg35 -Vsltu rd, rs1, imm[11:0]\u000ard = (rs1 < rs2) ? 1 : 0\u000aBoth rs1 and rs2 treated as unsigned numbers -p414 -sg37 -VISA\u000aChapter 2.4 -p415 -sg39 -VOutput result:\u000a\u000ard value is [0,1] -p416 -sg41 -Visacov.rv32i_sltu_cg.cp_rd_value -p417 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp418 -sg15 -(lp419 -sg53 -(lp420 -sg13 -(dp421 -g56 -I0 -ssbtp422 -asg86 -(lp423 -sg53 -(lp424 -sg13 -(dp425 -sbtp426 -a(V007_SLL -p427 -g1 -(g18 -g3 -Ntp428 -Rp429 -(dp430 -g22 -I3 -sg8 -g427 -sg23 -VVP_IP001_P007 -p431 -sg25 -(dp432 -sg12 -I7 -sg15 -(lp433 -(V000 -p434 -g1 -(g29 -g3 -Ntp435 -Rp436 -(dp437 -g8 -V000 -p438 -sg23 -VVP_ISA_F001_S007_I000 -p439 -sg35 -Vsll rd, rs1, rs2\u000ard = rs1 << rs2[4:0]\u000aZeros are shirfted into lower bits -p440 -sg37 -VISA\u000aChapter 2.4 -p441 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p442 -sg41 -Visacov.rv32i_sll_cg.cp_rs1\u000aisacov.rv32i_sll_cg.cp_rs2\u000aisacov.rv32i_sll_cg.cp_rd\u000aisacov.rv32i_sll_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_sll_cg.cp_rd_rs2_hazard -p443 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp444 -sg15 -(lp445 -sg53 -(lp446 -sg13 -(dp447 -g56 -I0 -ssbtp448 -a(V001 -p449 -g1 -(g29 -g3 -Ntp450 -Rp451 -(dp452 -g8 -V001 -p453 -sg23 -VVP_ISA_F001_S007_I001 -p454 -sg35 -Vsll rd, rs1, rs2\u000ard = rs1 << rs2[4:0]\u000aZeros are shirfted into lower bits -p455 -sg37 -VISA\u000aChapter 2.4 -p456 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is tested from [0,31]\u000aAll combinations of rs1 and rs2 non-zero and zero values with all shift values are used\u000aAll bits of rs1 are toggled -p457 -sg41 -Visacov.rv32i_sll_cg.cp_rs1_value\u000aisacov.rv32i_sll_cg.cp_rs2_value\u000aisacov.rv32i_sll_cg.cross_rs1_rs2_value\u000aisacov.rv32i_sll_cg.cp_rs1_toggle -p458 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp459 -sg15 -(lp460 -sg53 -(lp461 -sg13 -(dp462 -g56 -I0 -ssbtp463 -a(V002 -p464 -g1 -(g29 -g3 -Ntp465 -Rp466 -(dp467 -g8 -V002 -p468 -sg23 -VVP_ISA_F001_S007_I002 -p469 -sg35 -Vsll rd, rs1, rs2\u000ard = rs1 << rs2[4:0]\u000aZeros are shirfted into lower bits -p470 -sg37 -VISA\u000aChapter 2.4 -p471 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero.\u000aAll bits of rd are toggled -p472 -sg41 -Visacov.rv32i_sll_cg.cp_rd_value\u000aisacov.rv32i_sll_cg.cp_rd_toggle\u000aisacov.rv32i_sll_cg.cp_rd_value\u000aisacov.rv32i_sll_cg.cp_rd_toggle -p473 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp474 -sg15 -(lp475 -sg53 -(lp476 -sg13 -(dp477 -g56 -I0 -ssbtp478 -asg86 -(lp479 -sg53 -(lp480 -sg13 -(dp481 -sbtp482 -a(V008_SRL -p483 -g1 -(g18 -g3 -Ntp484 -Rp485 -(dp486 -g22 -I3 -sg8 -g483 -sg23 -VVP_IP001_P008 -p487 -sg25 -(dp488 -sg12 -I8 -sg15 -(lp489 -(V000 -p490 -g1 -(g29 -g3 -Ntp491 -Rp492 -(dp493 -g8 -V000 -p494 -sg23 -VVP_ISA_F001_S008_I000 -p495 -sg35 -Vsrl rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aZeros are shirfted into upper bits -p496 -sg37 -VISA\u000aChapter 2.4 -p497 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p498 -sg41 -Visacov.rv32i_srl_cg.cp_rs1\u000aisacov.rv32i_srl_cg.cp_rs2\u000aisacov.rv32i_srl_cg.cp_rd\u000aisacov.rv32i_srl_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_srl_cg.cp_rd_rs2_hazard -p499 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp500 -sg15 -(lp501 -sg53 -(lp502 -sg13 -(dp503 -g56 -I0 -ssbtp504 -a(V001 -p505 -g1 -(g29 -g3 -Ntp506 -Rp507 -(dp508 -g8 -V001 -p509 -sg23 -VVP_ISA_F001_S008_I001 -p510 -sg35 -Vsrl rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aZeros are shirfted into upper bits -p511 -sg37 -VISA\u000aChapter 2.4 -p512 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is tested from [0,31]\u000aAll combinations of rs1 and rs2 non-zero and zero values with all shift values are used\u000aAll bits of rs1 are toggled -p513 -sg41 -Visacov.rv32i_srl_cg.cp_rs1_value\u000aisacov.rv32i_srl_cg.cp_rs2_value\u000aisacov.rv32i_srl_cg.cross_rs1_rs2_value\u000aisacov.rv32i_srl_cg.cp_rs1_toggle -p514 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp515 -sg15 -(lp516 -sg53 -(lp517 -sg13 -(dp518 -g56 -I0 -ssbtp519 -a(V002 -p520 -g1 -(g29 -g3 -Ntp521 -Rp522 -(dp523 -g8 -V002 -p524 -sg23 -VVP_ISA_F001_S008_I002 -p525 -sg35 -Vsrl rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aZeros are shirfted into upper bits -p526 -sg37 -VISA\u000aChapter 2.4 -p527 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero.\u000aAll bits of rd are toggled -p528 -sg41 -Visacov.rv32i_srl_cg.cp_rd_value\u000aisacov.rv32i_srl_cg.cp_rd_toggle -p529 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp530 -sg15 -(lp531 -sg53 -(lp532 -sg13 -(dp533 -g56 -I0 -ssbtp534 -asg86 -(lp535 -sg53 -(lp536 -sg13 -(dp537 -sbtp538 -a(V009_SRA -p539 -g1 -(g18 -g3 -Ntp540 -Rp541 -(dp542 -g22 -I3 -sg8 -g539 -sg23 -VVP_IP001_P009 -p543 -sg25 -(dp544 -sg12 -I9 -sg15 -(lp545 -(V000 -p546 -g1 -(g29 -g3 -Ntp547 -Rp548 -(dp549 -g8 -V000 -p550 -sg23 -VVP_ISA_F001_S009_I000 -p551 -sg35 -Vsra rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aThe original sign bit is copied into the vacated upper bits -p552 -sg37 -VISA\u000aChapter 2.4 -p553 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p554 -sg41 -Visacov.rv32i_sra_cg.cp_rs1\u000aisacov.rv32i_sra_cg.cp_rs2\u000aisacov.rv32i_sra_cg.cp_rd\u000aisacov.rv32i_sra_cg.cp_rd_rs1_hazard\u000aisacov.rv32i_sra_cg.cp_rd_rs2_hazard -p555 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp556 -sg15 -(lp557 -sg53 -(lp558 -sg13 -(dp559 -g56 -I0 -ssbtp560 -a(V001 -p561 -g1 -(g29 -g3 -Ntp562 -Rp563 -(dp564 -g8 -V001 -p565 -sg23 -VVP_ISA_F001_S009_I001 -p566 -sg35 -Vsra rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aThe original sign bit is copied into the vacated upper bits -p567 -sg37 -VISA\u000aChapter 2.4 -p568 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve, and zero\u000ars2 value is tested from [0,31]\u000aAll combinations of rs1 and rs2 +ve, -ve and zero values with all shift values are used\u000aAll bits of rs1 are toggled -p569 -sg41 -Visacov.rv32i_sra_cg.cp_rs1_value\u000aisacov.rv32i_sra_cg.cp_rs2_value\u000aisacov.rv32i_sra_cg.cross_rs1_rs2_value\u000aisacov.rv32i_sra_cg.cp_rs1_toggle -p570 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp571 -sg15 -(lp572 -sg53 -(lp573 -sg13 -(dp574 -g56 -I0 -ssbtp575 -a(V002 -p576 -g1 -(g29 -g3 -Ntp577 -Rp578 -(dp579 -g8 -V002 -p580 -sg23 -VVP_ISA_F001_S009_I002 -p581 -sg35 -Vsra rd, rs1, rs2\u000ard = rs1 >> rs2[4:0]\u000aZeros are shirfted into upper bits -p582 -sg37 -VISA\u000aChapter 2.4 -p583 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve, and zero.\u000aAll bits of rd are toggled -p584 -sg41 -Visacov.rv32i_sra_cg.cp_rd_value\u000aisacov.rv32i_sra_cg.cp_rd_toggle -p585 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp586 -sg15 -(lp587 -sg53 -(lp588 -sg13 -(dp589 -g56 -I0 -ssbtp590 -asg86 -(lp591 -sg53 -(lp592 -sg13 -(dp593 -sbtp594 -asVrfu_list_0 -p595 -(lp596 -sg86 -(lp597 -sVvptool_gitrev -p598 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p599 -sVio_fmt_gitrev -p600 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p601 -sVconfig_gitrev -p602 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p603 -sVymlcfg_gitrev -p604 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p605 -sbtp606 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml new file mode 100644 index 0000000000..81184060b9 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml @@ -0,0 +1,665 @@ +!Feature +next_elt_id: 10 +name: RV32I Register-Register Instructions +id: 1 +display_order: 1 +subfeatures: !!omap +- 000_ADD: !Subfeature + name: 000_ADD + tag: VP_IP001_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S000_I000 + description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ + \ and ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_add_cg.cp_rs1\nisacov.rv32i_add_cg.cp_rs2\nisacov.rv32i_add_cg.cp_rd\n\ + isacov.rv32i_add_cg.cp_rd_rs1_hazard\nisacov.rv32i_add_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S000_I001 + description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ + \ and ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_add_cg.cp_rs1_value\nisacov.rv32i_add_cg.cp_rs2_value\n\ + isacov.rv32i_add_cg.cross_rs1_rs2_value\nisacov.rv32i_add_cg.cp_rs1_toggle\n\ + isacov.rv32i_add_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S000_I002 + description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ + \ and ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_add_cg.cp_rd_value\nisacov.rv32i_add_cg.cp_rd_toggle" + comments: '' +- 001_SUB: !Subfeature + name: 001_SUB + tag: VP_IP001_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S001_I000 + description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sub_cg.cp_rs1\nisacov.rv32i_sub_cg.cp_rs2\nisacov.rv32i_sub_cg.cp_rd\n\ + isacov.rv32i_sub_cg.cp_rd_rs1_hazard\nisacov.rv32i_sub_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S001_I001 + description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sub_cg.cp_rs1_value\nisacov.rv32i_sub_cg.cp_rs2_value\n\ + isacov.rv32i_sub_cg.cross_rs1_rs2_value\nisacov.rv32i_sub_cg.cp_rs1_toggle\n\ + isacov.rv32i_sub_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S001_I002 + description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sub_cg.cp_rd_value\nisacov.rv32i_sub_cg.cp_rd_toggle" + comments: '' +- 002_AND: !Subfeature + name: 002_AND + tag: VP_IP001_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S002_I000 + description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_and_cg.cp_rs1\nisacov.rv32i_and_cg.cp_rs2\nisacov.rv32i_and_cg.cp_rd\n\ + isacov.rv32i_and_cg.cp_rd_rs1_hazard\nisacov.rv32i_and_cg.cp_rd_rs2_hazard\n\ + isacov.rv32i_and_cg.cp_rs1\nisacov.rv32i_and_cg.cp_rs2\nisacov.rv32i_and_cg.cp_rd\n\ + isacov.rv32i_and_cg.cp_rd_rs1_hazard\nisacov.rv32i_and_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S002_I001 + description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_and_cg.cp_rs1_value\nisacov.rv32i_and_cg.cp_rs2_value\n\ + isacov.rv32i_and_cg.cross_rs1_rs2_value\nisacov.rv32i_and_cg.cp_rs1_toggle\n\ + isacov.rv32i_and_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S002_I002 + description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_and_cg.cp_rd_value\nisacov.rv32i_and_cg.cp_rd_toggle" + comments: '' +- 003_OR: !Subfeature + name: 003_OR + tag: VP_IP001_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S003_I000 + description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_or_cg.cp_rs1\nisacov.rv32i_or_cg.cp_rs2\nisacov.rv32i_or_cg.cp_rd\n\ + isacov.rv32i_or_cg.cp_rd_rs1_hazard\nisacov.rv32i_or_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S003_I001 + description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_or_cg.cp_rs1_value\nisacov.rv32i_or_cg.cp_rs2_value\n\ + isacov.rv32i_or_cg.cross_rs1_rs2_value\nisacov.rv32i_or_cg.cp_rs1_toggle\n\ + isacov.rv32i_or_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S003_I002 + description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_or_cg.cp_rd_value\nisacov.rv32i_or_cg.cp_rd_toggle" + comments: '' +- 004_XOR: !Subfeature + name: 004_XOR + tag: VP_IP001_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S004_I000 + description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xor_cg.cp_rs1\nisacov.rv32i_xor_cg.cp_rs2\nisacov.rv32i_xor_cg.cp_rd\n\ + isacov.rv32i_xor_cg.rd_rs1_hazard\nisacov.rv32i_xor_cg.rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S004_I001 + description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xor_cg.cp_rs1_value\nisacov.rv32i_xor_cg.cp_rs2_value\n\ + isacov.rv32i_xor_cg.cross_rs1_rs2_value\nisacov.rv32i_xor_cg.cp_rs1_toggle\n\ + isacov.rv32i_xor_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S004_I002 + description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: "isacov.rv32i_xor_cg.cp_rd_value\nisacov.rv32i_xor_cg.cp_rd_toggle" + comments: '' +- 005_SLT: !Subfeature + name: 005_SLT + tag: VP_IP001_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S005_I000 + description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ + \ treated as signed numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slt_cg.cp_rs1\nisacov.rv32i_slt_cg.cp_rs2\nisacov.rv32i_slt_cg.cp_rd\n\ + isacov.rv32i_slt_cg.cp_rd_rs1_hazard\nisacov.rv32i_slt_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S005_I001 + description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ + \ treated as signed numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slt_cg.cp_rs1_value\nisacov.rv32i_slt_cg.cp_rs2_value\n\ + isacov.rv32i_slt_cg.cross_rs1_rs2_value\nisacov.rv32i_slt_cg.cp_rs1_toggle\n\ + isacov.rv32i_slt_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S005_I002 + description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ + \ treated as signed numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_slt_cg.cp_rd_value + comments: '' +- 006_SLTU: !Subfeature + name: 006_SLTU + tag: VP_IP001_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S006_I000 + description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ + \ and rs2 treated as unsigned numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltu_cg.cp_rs1\nisacov.rv32i_sltu_cg.cp_rs2\n\ + isacov.rv32i_sltu_cg.cp_rd\nisacov.rv32i_sltu_cg.cp_rd_rs1_hazard\nisacov.rv32i_sltu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S006_I001 + description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ + \ and rs2 treated as unsigned numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltu_cg.cp_rs1_value\nisacov.rv32i_sltu_cg.cp_rs2_value\n\ + isacov.rv32i_sltu_cg.cross_rs1_rs2_value\nisacov.rv32i_sltu_cg.cp_rs1_toggle\n\ + isacov.rv32i_sltu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S006_I002 + description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ + \ and rs2 treated as unsigned numbers" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_sltu_cg.cp_rd_value + comments: '' +- 007_SLL: !Subfeature + name: 007_SLL + tag: VP_IP001_P007 + next_elt_id: 3 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S007_I000 + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + \ lower bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sll_cg.cp_rs1\nisacov.rv32i_sll_cg.cp_rs2\nisacov.rv32i_sll_cg.cp_rd\n\ + isacov.rv32i_sll_cg.cp_rd_rs1_hazard\nisacov.rv32i_sll_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S007_I001 + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + \ lower bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is tested from [0,31]\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values with all shift values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sll_cg.cp_rs1_value\nisacov.rv32i_sll_cg.cp_rs2_value\n\ + isacov.rv32i_sll_cg.cross_rs1_rs2_value\nisacov.rv32i_sll_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S007_I002 + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + \ lower bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero.\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sll_cg.cp_rd_value\nisacov.rv32i_sll_cg.cp_rd_toggle\n\ + isacov.rv32i_sll_cg.cp_rd_value\nisacov.rv32i_sll_cg.cp_rd_toggle" + comments: '' +- 008_SRL: !Subfeature + name: 008_SRL + tag: VP_IP001_P008 + next_elt_id: 3 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S008_I000 + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srl_cg.cp_rs1\nisacov.rv32i_srl_cg.cp_rs2\nisacov.rv32i_srl_cg.cp_rd\n\ + isacov.rv32i_srl_cg.cp_rd_rs1_hazard\nisacov.rv32i_srl_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S008_I001 + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is tested from [0,31]\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values with all shift values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srl_cg.cp_rs1_value\nisacov.rv32i_srl_cg.cp_rs2_value\n\ + isacov.rv32i_srl_cg.cross_rs1_rs2_value\nisacov.rv32i_srl_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S008_I002 + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero.\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srl_cg.cp_rd_value\nisacov.rv32i_srl_cg.cp_rd_toggle" + comments: '' +- 009_SRA: !Subfeature + name: 009_SRA + tag: VP_IP001_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F001_S009_I000 + description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\ + \ is copied into the vacated upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sra_cg.cp_rs1\nisacov.rv32i_sra_cg.cp_rs2\nisacov.rv32i_sra_cg.cp_rd\n\ + isacov.rv32i_sra_cg.cp_rd_rs1_hazard\nisacov.rv32i_sra_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F001_S009_I001 + description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\ + \ is copied into the vacated upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve, and zero\nrs2 value\ + \ is tested from [0,31]\nAll combinations of rs1 and rs2 +ve, -ve and zero\ + \ values with all shift values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sra_cg.cp_rs1_value\nisacov.rv32i_sra_cg.cp_rs2_value\n\ + isacov.rv32i_sra_cg.cross_rs1_rs2_value\nisacov.rv32i_sra_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F001_S009_I002 + description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: "ISA\nChapter 2.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve, and zero.\nAll bits\ + \ of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sra_cg.cp_rd_value\nisacov.rv32i_sra_cg.cp_rd_toggle" + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck deleted file mode 100644 index e2b333919a..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.pck +++ /dev/null @@ -1,1478 +0,0 @@ -(VRV32I Control Transfer Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I8 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I2 -sVwid_order -p12 -I2 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_JAL -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP002_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F002_S000_I000 -p34 -sVdescription -p35 -Vjal rd, imm[20:1]\u000ard = pc+4; pc += Sext({imm[20:1], 1\u2019b0})\u000apc is calculated using signed arithmetic\u000a\u000ajal x0, imm[20:1] (special case: unconditional jump)\u000apc += Sext({imm[20:1], 1\u2019b0}) -p36 -sVpurpose -p37 -VISA\u000aChapter 2.5 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p40 -sVcoverage_loc -p41 -Visacov.rv32i_jal_cg.cp_rd -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F002_S000_I001 -p63 -sg35 -Vjal rd, imm[20:1]\u000ard = pc+4; pc += Sext({imm[20:1], 1\u2019b0})\u000apc is calculated using signed arithmetic\u000a\u000ajal x0, imm[20:1] (special case: unconditional jump)\u000apc += Sext({imm[20:1], 1\u2019b0}) -p64 -sg37 -VISA\u000aChapter 2.5 -p65 -sg39 -VInput operands:\u000a\u000aimmj value is +ve, -ve, and zero\u000aAll bits of immj are toggled -p66 -sg41 -Visacov.rv32i_jal_cg.cp_immj_value\u000aisacov.rv32i_jal_cg.cp_immj_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F002_S000_I002 -p78 -sg35 -Vjal rd, imm[20:1]\u000ard = pc+4; pc += Sext({imm[20:1], 1\u2019b0})\u000apc is calculated using signed arithmetic\u000a\u000ajal x0, imm[20:1] (special case: unconditional jump)\u000apc += Sext({imm[20:1], 1\u2019b0}) -p79 -sg37 -VISA\u000aChapter 2.5 -p80 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32i_jal_cg.cp_rd_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -asVrfu_list_1 -p88 -(lp89 -sg53 -(lp90 -sg13 -(dp91 -sbtp92 -a(V001_JALR -p93 -g1 -(g18 -g3 -Ntp94 -Rp95 -(dp96 -g22 -I3 -sg8 -g93 -sg23 -VVP_IP002_P001 -p97 -sg25 -(dp98 -sg12 -I1 -sg15 -(lp99 -(V000 -p100 -g1 -(g29 -g3 -Ntp101 -Rp102 -(dp103 -g8 -V000 -p104 -sg23 -VVP_ISA_F002_S001_I000 -p105 -sg35 -Vjalr rd, rs1, imm[11:0]\u000ard = pc+4; pc = rs1 + Sext(imm[11:0])\u000apc is calculated using signed arithmetic -p106 -sg37 -VISA\u000aChapter 2.5 -p107 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p108 -sg41 -Visacov.rv32i_jalr_cg.cp_rs1\u000aisacov.rv32i_jalr_cg.cp_rd\u000aisacov.rv32i_jalr_cg.cp_rd_rs1_hazard -p109 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp110 -sg15 -(lp111 -sg53 -(lp112 -sg13 -(dp113 -g56 -I0 -ssbtp114 -a(V001 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -V001 -p119 -sg23 -VVP_ISA_F002_S001_I001 -p120 -sg35 -Vjalr rd, rs1, imm[11:0]\u000ard = pc+4; pc = rs1 + Sext(imm[11:0])\u000apc is calculated using signed arithmetic -p121 -sg37 -VISA\u000aChapter 2.5 -p122 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve, and zero\u000aAll bits of immi are toggled\u000aAll bits of rs1 are toggled -p123 -sg41 -Visacov.rv32i_jalr_cg.cp_immi_value\u000aisacov.rv32i_jalr_cg.cp_immi_toggle\u000aisacov.rv32i_jalr_cg.cp_rs1_toggle -p124 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp125 -sg15 -(lp126 -sg53 -(lp127 -sg13 -(dp128 -g56 -I0 -ssbtp129 -a(V002 -p130 -g1 -(g29 -g3 -Ntp131 -Rp132 -(dp133 -g8 -V002 -p134 -sg23 -VVP_ISA_F002_S001_I002 -p135 -sg35 -Vjalr rd, rs1, imm[11:0]\u000ard = pc+4; pc = rs1 + Sext(imm[11:0])\u000apc is calculated using signed arithmetic -p136 -sg37 -VISA\u000aChapter 2.5 -p137 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p138 -sg41 -Visacov.rv32i_jalr_cg.cp_rd_toggle -p139 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp140 -sg15 -(lp141 -sg53 -(lp142 -sg13 -(dp143 -g56 -I0 -ssbtp144 -asg88 -(lp145 -sg53 -(lp146 -sg13 -(dp147 -sbtp148 -a(V002_BEQ -p149 -g1 -(g18 -g3 -Ntp150 -Rp151 -(dp152 -g22 -I3 -sg8 -g149 -sg23 -VVP_IP002_P002 -p153 -sg25 -(dp154 -sg12 -I2 -sg15 -(lp155 -(V000 -p156 -g1 -(g29 -g3 -Ntp157 -Rp158 -(dp159 -g8 -V000 -p160 -sg23 -VVP_ISA_F002_S002_I000 -p161 -sg35 -Vbeq rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1==rs2) else pc += 4\u000apc is calculated using signed arithmetic -p162 -sg37 -VISA\u000aChapter 2.5 -p163 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p164 -sg41 -Visacov.rv32i_beq_cg.cp_rs1\u000aisacov.rv32i_beq_cg.cp_rs2 -p165 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp166 -sg15 -(lp167 -sg53 -(lp168 -sg13 -(dp169 -g56 -I0 -ssbtp170 -a(V001 -p171 -g1 -(g29 -g3 -Ntp172 -Rp173 -(dp174 -g8 -V001 -p175 -sg23 -VVP_ISA_F002_S002_I001 -p176 -sg35 -Vbeq rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1==rs2) else pc += 4\u000apc is calculated using signed arithmetic -p177 -sg37 -VISA\u000aChapter 2.5 -p178 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p179 -sg41 -Visacov.rv32i_beq_cg.cp_immb_value\u000aisacov.rv32i_beq_cg.cp_rs1_toggle\u000aisacov.rv32i_beq_cg.cp_rs2_toggle -p180 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp181 -sg15 -(lp182 -sg53 -(lp183 -sg13 -(dp184 -g56 -I0 -ssbtp185 -a(V002 -p186 -g1 -(g29 -g3 -Ntp187 -Rp188 -(dp189 -g8 -V002 -p190 -sg23 -VVP_ISA_F002_S002_I002 -p191 -sg35 -Vbeq rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1==rs2) else pc += 4\u000apc is calculated using signed arithmetic -p192 -sg37 -VISA\u000aChapter 2.5 -p193 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p194 -sg41 -Visacov.rv32i_beq_cg.cp_branch_taken -p195 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp196 -sg15 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -g56 -I0 -ssbtp200 -asg88 -(lp201 -sg53 -(lp202 -sg13 -(dp203 -sbtp204 -a(V003_BNE -p205 -g1 -(g18 -g3 -Ntp206 -Rp207 -(dp208 -g22 -I3 -sg8 -g205 -sg23 -VVP_IP002_P003 -p209 -sg25 -(dp210 -sg12 -I3 -sg15 -(lp211 -(V000 -p212 -g1 -(g29 -g3 -Ntp213 -Rp214 -(dp215 -g8 -V000 -p216 -sg23 -VVP_ISA_F002_S003_I000 -p217 -sg35 -Vbne rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1!=rs2) else pc += 4\u000apc is calculated using signed arithmetic -p218 -sg37 -VISA\u000aChapter 2.5 -p219 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p220 -sg41 -Visacov.rv32i_bne_cg.cp_rs1\u000aisacov.rv32i_bne_cg.cp_rs2 -p221 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp222 -sg15 -(lp223 -sg53 -(lp224 -sg13 -(dp225 -g56 -I0 -ssbtp226 -a(V001 -p227 -g1 -(g29 -g3 -Ntp228 -Rp229 -(dp230 -g8 -V001 -p231 -sg23 -VVP_ISA_F002_S003_I001 -p232 -sg35 -Vbne rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1!=rs2) else pc += 4\u000apc is calculated using signed arithmetic -p233 -sg37 -VISA\u000aChapter 2.5 -p234 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p235 -sg41 -Visacov.rv32i_bne_cg.cp_immb_value\u000aisacov.rv32i_bne_cg.cp_rs1_toggle\u000aisacov.rv32i_bne_cg.cp_rs2_toggle -p236 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp237 -sg15 -(lp238 -sg53 -(lp239 -sg13 -(dp240 -g56 -I0 -ssbtp241 -a(V002 -p242 -g1 -(g29 -g3 -Ntp243 -Rp244 -(dp245 -g8 -V002 -p246 -sg23 -VVP_ISA_F002_S003_I002 -p247 -sg35 -Vbne rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1!=rs2) else pc += 4\u000apc is calculated using signed arithmetic -p248 -sg37 -VISA\u000aChapter 2.5 -p249 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p250 -sg41 -Visacov.rv32i_bne_cg.cp_branch_taken -p251 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp252 -sg15 -(lp253 -sg53 -(lp254 -sg13 -(dp255 -g56 -I0 -ssbtp256 -asg88 -(lp257 -sg53 -(lp258 -sg13 -(dp259 -sbtp260 -a(V004_BLT -p261 -g1 -(g18 -g3 -Ntp262 -Rp263 -(dp264 -g22 -I3 -sg8 -g261 -sg23 -VVP_IP002_P004 -p265 -sg25 -(dp266 -sg12 -I4 -sg15 -(lp267 -(V000 -p268 -g1 -(g29 -g3 -Ntp269 -Rp270 -(dp271 -g8 -V000 -p272 -sg23 -VVP_ISA_F002_S004_I000 -p273 -sg35 -Vblt rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using signed arithmetic -p274 -sg37 -VISA\u000aChapter 2.5 -p275 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p276 -sg41 -Visacov.rv32i_blt_cg.cp_rs1\u000aisacov.rv32i_blt_cg.cp_rs2 -p277 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp278 -sg15 -(lp279 -sg53 -(lp280 -sg13 -(dp281 -g56 -I0 -ssbtp282 -a(V001 -p283 -g1 -(g29 -g3 -Ntp284 -Rp285 -(dp286 -g8 -V001 -p287 -sg23 -VVP_ISA_F002_S004_I001 -p288 -sg35 -Vblt rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using signed arithmetic -p289 -sg37 -VISA\u000aChapter 2.5 -p290 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p291 -sg41 -Visacov.rv32i_blt_cg.cp_immb_value\u000aisacov.rv32i_blt_cg.cp_rs1_toggle\u000aisacov.rv32i_blt_cg.cp_rs2_toggle -p292 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp293 -sg15 -(lp294 -sg53 -(lp295 -sg13 -(dp296 -g56 -I0 -ssbtp297 -a(V002 -p298 -g1 -(g29 -g3 -Ntp299 -Rp300 -(dp301 -g8 -V002 -p302 -sg23 -VVP_ISA_F002_S004_I002 -p303 -sg35 -Vblt rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using signed arithmetic -p304 -sg37 -VISA\u000aChapter 2.5 -p305 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p306 -sg41 -Visacov.rv32i_blt_cg.cp_branch_taken -p307 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp308 -sg15 -(lp309 -sg53 -(lp310 -sg13 -(dp311 -g56 -I0 -ssbtp312 -asg88 -(lp313 -sg53 -(lp314 -sg13 -(dp315 -sbtp316 -a(V005_BGE -p317 -g1 -(g18 -g3 -Ntp318 -Rp319 -(dp320 -g22 -I6 -sg8 -g317 -sg23 -VVP_IP002_P005 -p321 -sg25 -(dp322 -sg12 -I5 -sg15 -(lp323 -(V000 -p324 -g1 -(g29 -g3 -Ntp325 -Rp326 -(dp327 -g8 -V000 -p328 -sg23 -VVP_ISA_F002_S005_I000 -p329 -sg35 -Vbge rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using signed arithmetic -p330 -sg37 -VISA\u000aChapter 2.5 -p331 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p332 -sg41 -Visacov.rv32i_bge_cg.cp_rs1\u000aisacov.rv32i_bge_cg.cp_rs2 -p333 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp334 -sg15 -(lp335 -sg53 -(lp336 -sg13 -(dp337 -g56 -I0 -ssbtp338 -a(V001 -p339 -g1 -(g29 -g3 -Ntp340 -Rp341 -(dp342 -g8 -g339 -sg23 -VVP_ISA_F002_S005_I001 -p343 -sg35 -Vbge rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using signed arithmetic -p344 -sg37 -VISA\u000aChapter 2.5 -p345 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p346 -sg41 -Visacov.rv32i_bge_cg.cp_immb_value\u000aisacov.rv32i_bge_cg.cp_rs1_toggle\u000aisacov.rv32i_bge_cg.cp_rs2_toggle -p347 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp348 -sg15 -(lp349 -sg53 -(lp350 -sg13 -(dp351 -g56 -I0 -ssbtp352 -a(V002 -p353 -g1 -(g29 -g3 -Ntp354 -Rp355 -(dp356 -g8 -g353 -sg23 -VVP_ISA_F002_S005_I002 -p357 -sg35 -Vbge rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using signed arithmetic -p358 -sg37 -VISA\u000aChapter 2.5 -p359 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p360 -sg41 -Visacov.rv32i_bge_cg.cp_branch_taken -p361 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp362 -sg15 -(lp363 -sg53 -(lp364 -sg13 -(dp365 -g56 -I0 -ssbtp366 -asg88 -(lp367 -sg53 -(lp368 -sg13 -(dp369 -sbtp370 -a(V006_BLTU -p371 -g1 -(g18 -g3 -Ntp372 -Rp373 -(dp374 -g22 -I3 -sg8 -g371 -sg23 -VVP_IP002_P006 -p375 -sg25 -(dp376 -sg12 -I6 -sg15 -(lp377 -(V000 -p378 -g1 -(g29 -g3 -Ntp379 -Rp380 -(dp381 -g8 -V000 -p382 -sg23 -VVP_ISA_F002_S006_I000 -p383 -sg35 -Vbltu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p384 -sg37 -VISA\u000aChapter 2.5 -p385 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p386 -sg41 -Visacov.rv32i_bltu_cg.cp_rs1\u000aisacov.rv32i_bltu_cg.cp_rs2 -p387 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp388 -sg15 -(lp389 -sg53 -(lp390 -sg13 -(dp391 -g56 -I0 -ssbtp392 -a(V001 -p393 -g1 -(g29 -g3 -Ntp394 -Rp395 -(dp396 -g8 -V001 -p397 -sg23 -VVP_ISA_F002_S006_I001 -p398 -sg35 -Vbltu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p399 -sg37 -VISA\u000aChapter 2.5 -p400 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p401 -sg41 -Visacov.rv32i_bltu_cg.cp_immb_value\u000aisacov.rv32i_bltu_cg.cp_rs1_toggle\u000aisacov.rv32i_bltu_cg.cp_rs2_toggle -p402 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp403 -sg15 -(lp404 -sg53 -(lp405 -sg13 -(dp406 -g56 -I0 -ssbtp407 -a(V002 -p408 -g1 -(g29 -g3 -Ntp409 -Rp410 -(dp411 -g8 -V002 -p412 -sg23 -VVP_ISA_F002_S006_I002 -p413 -sg35 -Vbltu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 < rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p414 -sg37 -VISA\u000aChapter 2.5 -p415 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p416 -sg41 -Visacov.rv32i_bltu_cg.cp_branch_taken -p417 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp418 -sg15 -(lp419 -sg53 -(lp420 -sg13 -(dp421 -g56 -I0 -ssbtp422 -asg88 -(lp423 -sg53 -(lp424 -sg13 -(dp425 -sbtp426 -a(V007_BGEU -p427 -g1 -(g18 -g3 -Ntp428 -Rp429 -(dp430 -g22 -I3 -sg8 -g427 -sg23 -VVP_IP002_P007 -p431 -sg25 -(dp432 -sg12 -I7 -sg15 -(lp433 -(V000 -p434 -g1 -(g29 -g3 -Ntp435 -Rp436 -(dp437 -g8 -V000 -p438 -sg23 -VVP_ISA_F002_S007_I000 -p439 -sg35 -Vbgeu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p440 -sg37 -VISA\u000aChapter 2.5 -p441 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p442 -sg41 -Visacov.rv32i_bgeu_cg.cp_rs1\u000aisacov.rv32i_bgeu_cg.cp_rs2 -p443 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp444 -sg15 -(lp445 -sg53 -(lp446 -sg13 -(dp447 -g56 -I0 -ssbtp448 -a(V001 -p449 -g1 -(g29 -g3 -Ntp450 -Rp451 -(dp452 -g8 -V001 -p453 -sg23 -VVP_ISA_F002_S007_I001 -p454 -sg35 -Vbgeu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p455 -sg37 -VISA\u000aChapter 2.5 -p456 -sg39 -VInput operands:\u000a\u000aimmb value is +ve, -ve, and zero\u000aAll bits of immb are toggled\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p457 -sg41 -Visacov.rv32i_bgeu_cg.cp_immb_value\u000aisacov.rv32i_bgeu_cg.cp_rs1_toggle\u000aisacov.rv32i_bgeu_cg.cp_rs2_toggle -p458 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp459 -sg15 -(lp460 -sg53 -(lp461 -sg13 -(dp462 -g56 -I0 -ssbtp463 -a(V002 -p464 -g1 -(g29 -g3 -Ntp465 -Rp466 -(dp467 -g8 -V002 -p468 -sg23 -VVP_ISA_F002_S007_I002 -p469 -sg35 -Vbgeu rs1, rs2, imm[12:1]\u000apc += Sext({imm[12:1], 1\u2019b0}) if (rs1 >= rs2) else pc += 4\u000apc is calculated using unsigned arithmetic -p470 -sg37 -VISA\u000aChapter 2.5 -p471 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p472 -sg41 -Visacov.rv32i_bgeu_cg.cp_branch_taken -p473 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp474 -sg15 -(lp475 -sg53 -(lp476 -sg13 -(dp477 -g56 -I0 -ssbtp478 -asg88 -(lp479 -sg53 -(lp480 -sg13 -(dp481 -sbtp482 -asVrfu_list_0 -p483 -(lp484 -sg88 -(lp485 -sVvptool_gitrev -p486 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p487 -sVio_fmt_gitrev -p488 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p489 -sVconfig_gitrev -p490 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p491 -sVymlcfg_gitrev -p492 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p493 -sbtp494 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml new file mode 100644 index 0000000000..a6903df290 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml @@ -0,0 +1,498 @@ +!Feature +next_elt_id: 8 +name: RV32I Control Transfer Instructions +id: 2 +display_order: 2 +subfeatures: !!omap +- 000_JAL: !Subfeature + name: 000_JAL + tag: VP_IP002_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S000_I000 + description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ + pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ + \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_jal_cg.cp_rd + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S000_I001 + description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ + pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ + \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmj value is +ve, -ve, and zero\nAll bits\ + \ of immj are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_jal_cg.cp_immj_value\nisacov.rv32i_jal_cg.cp_immj_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S000_I002 + description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ + pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ + \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_jal_cg.cp_rd_toggle + comments: '' +- 001_JALR: !Subfeature + name: 001_JALR + tag: VP_IP002_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S001_I000 + description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ + pc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_jalr_cg.cp_rs1\nisacov.rv32i_jalr_cg.cp_rd\nisacov.rv32i_jalr_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S001_I001 + description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ + pc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmi value is +ve, -ve, and zero\nAll bits\ + \ of immi are toggled\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_jalr_cg.cp_immi_value\nisacov.rv32i_jalr_cg.cp_immi_toggle\n\ + isacov.rv32i_jalr_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S001_I002 + description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ + pc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_jalr_cg.cp_rd_toggle + comments: '' +- 002_BEQ: !Subfeature + name: 002_BEQ + tag: VP_IP002_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S002_I000 + description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_beq_cg.cp_rs1\nisacov.rv32i_beq_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S002_I001 + description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_beq_cg.cp_immb_value\nisacov.rv32i_beq_cg.cp_rs1_toggle\n\ + isacov.rv32i_beq_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S002_I002 + description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_beq_cg.cp_branch_taken + comments: '' +- 003_BNE: !Subfeature + name: 003_BNE + tag: VP_IP002_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S003_I000 + description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bne_cg.cp_rs1\nisacov.rv32i_bne_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S003_I001 + description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bne_cg.cp_immb_value\nisacov.rv32i_bne_cg.cp_rs1_toggle\n\ + isacov.rv32i_bne_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S003_I002 + description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bne_cg.cp_branch_taken + comments: '' +- 004_BLT: !Subfeature + name: 004_BLT + tag: VP_IP002_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S004_I000 + description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_blt_cg.cp_rs1\nisacov.rv32i_blt_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S004_I001 + description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_blt_cg.cp_immb_value\nisacov.rv32i_blt_cg.cp_rs1_toggle\n\ + isacov.rv32i_blt_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S004_I002 + description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_blt_cg.cp_branch_taken + comments: '' +- 005_BGE: !Subfeature + name: 005_BGE + tag: VP_IP002_P005 + next_elt_id: 6 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S005_I000 + description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bge_cg.cp_rs1\nisacov.rv32i_bge_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S005_I001 + description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bge_cg.cp_immb_value\nisacov.rv32i_bge_cg.cp_rs1_toggle\n\ + isacov.rv32i_bge_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S005_I002 + description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bge_cg.cp_branch_taken + comments: '' +- 006_BLTU: !Subfeature + name: 006_BLTU + tag: VP_IP002_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S006_I000 + description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bltu_cg.cp_rs1\nisacov.rv32i_bltu_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S006_I001 + description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bltu_cg.cp_immb_value\nisacov.rv32i_bltu_cg.cp_rs1_toggle\n\ + isacov.rv32i_bltu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S006_I002 + description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bltu_cg.cp_branch_taken + comments: '' +- 007_BGEU: !Subfeature + name: 007_BGEU + tag: VP_IP002_P007 + next_elt_id: 3 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F002_S007_I000 + description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bgeu_cg.cp_rs1\nisacov.rv32i_bgeu_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F002_S007_I001 + description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bgeu_cg.cp_immb_value\nisacov.rv32i_bgeu_cg.cp_rs1_toggle\n\ + isacov.rv32i_bgeu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F002_S007_I002 + description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bgeu_cg.cp_branch_taken + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck deleted file mode 100644 index bcd79324f6..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.pck +++ /dev/null @@ -1,1333 +0,0 @@ -(VRV32I Load and Store Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I8 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I3 -sVwid_order -p12 -I3 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_LB -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP003_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F003_S000_I000 -p34 -sVdescription -p35 -Vlb rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:7])\u000ard is calculated using signed arithmetic -p36 -sVpurpose -p37 -VISA\u000aChapter 2.6 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32i_lb_cg.cp_rs1\u000aisacov.rv32i_lb_cg.cp_rd\u000aisacov.rv32i_lb_cg.cp_rd_rs1_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F003_S000_I001 -p63 -sg35 -Vlb rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:7])\u000ard is calculated using signed arithmetic -p64 -sg37 -VISA\u000aChapter 2.6 -p65 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p66 -sg41 -Visacov.rv32i_lb_cg.cp_immi_value\u000aisacov.rv32i_lb_cg.cp_rs1_toggle\u000aisacov.rv32i_lb_cg.cp_immi_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F003_S000_I002 -p78 -sg35 -Vlb rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:7])\u000ard is calculated using signed arithmetic -p79 -sg37 -VISA\u000aChapter 2.6 -p80 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32i_lb_cg.cp_rd_value\u000aisacov.rv32i_lb_cg.cp_rd_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -asVrfu_list_1 -p88 -(lp89 -sg53 -(lp90 -sg13 -(dp91 -sbtp92 -a(V001_LH -p93 -g1 -(g18 -g3 -Ntp94 -Rp95 -(dp96 -g22 -I3 -sg8 -g93 -sg23 -VVP_IP003_P001 -p97 -sg25 -(dp98 -sg12 -I1 -sg15 -(lp99 -(V000 -p100 -g1 -(g29 -g3 -Ntp101 -Rp102 -(dp103 -g8 -V000 -p104 -sg23 -VVP_ISA_F003_S001_I000 -p105 -sg35 -Vlh rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:15])\u000ard is calculated using signed arithmetic -p106 -sg37 -VISA\u000aChapter 2.6 -p107 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p108 -sg41 -Visacov.rv32i_lh_cg.cp_rs1\u000aisacov.rv32i_lh_cg.cp_rd\u000aisacov.rv32i_lh_cg.cp_rd_rs1_hazard -p109 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp110 -sg15 -(lp111 -sg53 -(lp112 -sg13 -(dp113 -g56 -I0 -ssbtp114 -a(V001 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -V001 -p119 -sg23 -VVP_ISA_F003_S001_I001 -p120 -sg35 -Vlh rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:15])\u000ard is calculated using signed arithmetic -p121 -sg37 -VISA\u000aChapter 2.6 -p122 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled\u000aUnaligned and aligned accesses from memory -p123 -sg41 -Visacov.rv32i_lh_cg.cp_immi_value\u000aisacov.rv32i_lh_cg.cp_rs1_toggle\u000aisacov.rv32i_lh_cg.cp_immi_toggle\u000aisacov.rv32i_lh_cg.cp_aligned -p124 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp125 -sg15 -(lp126 -sg53 -(lp127 -sg13 -(dp128 -g56 -I0 -ssbtp129 -a(V002 -p130 -g1 -(g29 -g3 -Ntp131 -Rp132 -(dp133 -g8 -V002 -p134 -sg23 -VVP_ISA_F003_S001_I002 -p135 -sg35 -Vlh rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:15])\u000ard is calculated using signed arithmetic -p136 -sg37 -VISA\u000aChapter 2.6 -p137 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p138 -sg41 -Visacov.rv32i_lh_cg.cp_rd_value\u000aisacov.rv32i_lh_cg.cp_rd_toggle -p139 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp140 -sg15 -(lp141 -sg53 -(lp142 -sg13 -(dp143 -g56 -I0 -ssbtp144 -asg88 -(lp145 -sg53 -(lp146 -sg13 -(dp147 -sbtp148 -a(V002_LW -p149 -g1 -(g18 -g3 -Ntp150 -Rp151 -(dp152 -g22 -I3 -sg8 -g149 -sg23 -VVP_IP003_P002 -p153 -sg25 -(dp154 -sg12 -I2 -sg15 -(lp155 -(V000 -p156 -g1 -(g29 -g3 -Ntp157 -Rp158 -(dp159 -g8 -V000 -p160 -sg23 -VVP_ISA_F003_S002_I000 -p161 -sg35 -Vlw rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:31])\u000ard is calculated using signed arithmetic -p162 -sg37 -VISA\u000aChapter 2.6 -p163 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p164 -sg41 -Visacov.rv32i_lw_cg.cp_rs1\u000aisacov.rv32i_lw_cg.cp_rd\u000aisacov.rv32i_lw_cg.cp_rd_rs1_hazard -p165 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp166 -sg15 -(lp167 -sg53 -(lp168 -sg13 -(dp169 -g56 -I0 -ssbtp170 -a(V001 -p171 -g1 -(g29 -g3 -Ntp172 -Rp173 -(dp174 -g8 -V001 -p175 -sg23 -VVP_ISA_F003_S002_I001 -p176 -sg35 -Vlw rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:31])\u000ard is calculated using signed arithmetic -p177 -sg37 -VISA\u000aChapter 2.6 -p178 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled\u000aUnaligned and aligned accesses from memory -p179 -sg41 -Visacov.rv32i_lw_cg.cp_immi_value\u000aisacov.rv32i_lw_cg.cp_rs1_toggle\u000aisacov.rv32i_lw_cg.cp_immi_toggle\u000aisacov.rv32i_lw_cg.cp_aligned -p180 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp181 -sg15 -(lp182 -sg53 -(lp183 -sg13 -(dp184 -g56 -I0 -ssbtp185 -a(V002 -p186 -g1 -(g29 -g3 -Ntp187 -Rp188 -(dp189 -g8 -V002 -p190 -sg23 -VVP_ISA_F003_S002_I002 -p191 -sg35 -Vlw rd, rs1, imm\u000ard = Sext(M[rs1+imm][0:31])\u000ard is calculated using signed arithmetic -p192 -sg37 -VISA\u000aChapter 2.6 -p193 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p194 -sg41 -Visacov.rv32i_lw_cg.cp_rd_value\u000aisacov.rv32i_lw_cg.cp_rd_toggle -p195 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp196 -sg15 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -g56 -I0 -ssbtp200 -asg88 -(lp201 -sg53 -(lp202 -sg13 -(dp203 -sbtp204 -a(V003_LBU -p205 -g1 -(g18 -g3 -Ntp206 -Rp207 -(dp208 -g22 -I3 -sg8 -g205 -sg23 -VVP_IP003_P003 -p209 -sg25 -(dp210 -sg12 -I3 -sg15 -(lp211 -(V000 -p212 -g1 -(g29 -g3 -Ntp213 -Rp214 -(dp215 -g8 -V000 -p216 -sg23 -VVP_ISA_F003_S003_I000 -p217 -sg35 -Vlbu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:7])\u000ard is calculated using unsigned arithmetic -p218 -sg37 -VISA\u000aChapter 2.6 -p219 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p220 -sg41 -Visacov.rv32i_lbu_cg.cp_rs1\u000aisacov.rv32i_lbu_cg.cp_rd\u000aisacov.rv32i_lbu_cg.cp_rd_rs1_hazard -p221 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp222 -sg15 -(lp223 -sg53 -(lp224 -sg13 -(dp225 -g56 -I0 -ssbtp226 -a(V001 -p227 -g1 -(g29 -g3 -Ntp228 -Rp229 -(dp230 -g8 -V001 -p231 -sg23 -VVP_ISA_F003_S003_I001 -p232 -sg35 -Vlbu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:7])\u000ard is calculated using unsigned arithmetic -p233 -sg37 -VISA\u000aChapter 2.6 -p234 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled -p235 -sg41 -Visacov.rv32i_lbu_cg.cp_immi_value\u000aisacov.rv32i_lbu_cg.cp_rs1_toggle\u000aisacov.rv32i_lbu_cg.cp_immi_toggle -p236 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp237 -sg15 -(lp238 -sg53 -(lp239 -sg13 -(dp240 -g56 -I0 -ssbtp241 -a(V002 -p242 -g1 -(g29 -g3 -Ntp243 -Rp244 -(dp245 -g8 -V002 -p246 -sg23 -VVP_ISA_F003_S003_I002 -p247 -sg35 -Vlbu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:7])\u000ard is calculated using unsigned arithmetic -p248 -sg37 -VISA\u000aChapter 2.6 -p249 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd[7:0] are toggled -p250 -sg41 -Visacov.rv32i_lbu_cg.cp_rd_value\u000aisacov.rv32i_lbu_cg.cp_rd_toggle -p251 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp252 -sg15 -(lp253 -sg53 -(lp254 -sg13 -(dp255 -g56 -I0 -ssbtp256 -asg88 -(lp257 -sg53 -(lp258 -sg13 -(dp259 -sbtp260 -a(V004_LHU -p261 -g1 -(g18 -g3 -Ntp262 -Rp263 -(dp264 -g22 -I3 -sg8 -g261 -sg23 -VVP_IP003_P004 -p265 -sg25 -(dp266 -sg12 -I4 -sg15 -(lp267 -(V000 -p268 -g1 -(g29 -g3 -Ntp269 -Rp270 -(dp271 -g8 -V000 -p272 -sg23 -VVP_ISA_F003_S004_I000 -p273 -sg35 -Vlhu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:15])\u000ard is calculated using unsigned arithmetic -p274 -sg37 -VISA\u000aChapter 2.6 -p275 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p276 -sg41 -Visacov.rv32i_lhu_cg.cp_rs1\u000aisacov.rv32i_lhu_cg.cp_rd\u000aisacov.rv32i_lhu_cg.cp_rd_rs1_hazard -p277 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp278 -sg15 -(lp279 -sg53 -(lp280 -sg13 -(dp281 -g56 -I0 -ssbtp282 -a(V001 -p283 -g1 -(g29 -g3 -Ntp284 -Rp285 -(dp286 -g8 -V001 -p287 -sg23 -VVP_ISA_F003_S004_I001 -p288 -sg35 -Vlhu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:15])\u000ard is calculated using unsigned arithmetic -p289 -sg37 -VISA\u000aChapter 2.6 -p290 -sg39 -VInput operands:\u000a\u000aimmi value is +ve, -ve and zero\u000aAll combinations of rs1 and immi +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of immi are toggled\u000aUnaligned and aligned accesses from memory -p291 -sg41 -Visacov.rv32i_lhu_cg.cp_immi_value\u000aisacov.rv32i_lhu_cg.cp_rs1_toggle\u000aisacov.rv32i_lhu_cg.cp_immi_toggle\u000aisacov.rv32i_lhu_cg.cp_aligned -p292 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp293 -sg15 -(lp294 -sg53 -(lp295 -sg13 -(dp296 -g56 -I0 -ssbtp297 -a(V002 -p298 -g1 -(g29 -g3 -Ntp299 -Rp300 -(dp301 -g8 -V002 -p302 -sg23 -VVP_ISA_F003_S004_I002 -p303 -sg35 -Vlhu rd, rs1, imm\u000ard = Zext(M[rs1+imm][0:15])\u000ard is calculated using unsigned arithmetic -p304 -sg37 -VISA\u000aChapter 2.6 -p305 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd[15:0] are toggled -p306 -sg41 -Visacov.rv32i_lhu_cg.cp_rd_value\u000aisacov.rv32i_lhu_cg.cp_rd_toggle -p307 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp308 -sg15 -(lp309 -sg53 -(lp310 -sg13 -(dp311 -g56 -I0 -ssbtp312 -asg88 -(lp313 -sg53 -(lp314 -sg13 -(dp315 -sbtp316 -a(V005_SB -p317 -g1 -(g18 -g3 -Ntp318 -Rp319 -(dp320 -g22 -I3 -sg8 -g317 -sg23 -VVP_IP003_P005 -p321 -sg25 -(dp322 -sg12 -I5 -sg15 -(lp323 -(V000 -p324 -g1 -(g29 -g3 -Ntp325 -Rp326 -(dp327 -g8 -V000 -p328 -sg23 -VVP_ISA_F003_S005_I000 -p329 -sg35 -Vsb rs1, rs2, imm\u000aM[rs1+imm][0:7] = rs2[0:7] -p330 -sg37 -VISA\u000aChapter 2.6 -p331 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p332 -sg41 -Visacov.rv32i_sb_cg.cp_rs1\u000aisacov.rv32i_sb_cg.cp_rs2 -p333 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp334 -sg15 -(lp335 -sg53 -(lp336 -sg13 -(dp337 -g56 -I0 -ssbtp338 -a(V001 -p339 -g1 -(g29 -g3 -Ntp340 -Rp341 -(dp342 -g8 -V001 -p343 -sg23 -VVP_ISA_F003_S005_I001 -p344 -sg35 -Vsb rs1, rs2, imm\u000aM[rs1+imm][0:7] = rs2[0:7] -p345 -sg37 -VISA\u000aChapter 2.6 -p346 -sg39 -VInput operands:\u000a\u000aimms value is +ve, -ve and zero\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aAll bits of imms are toggled -p347 -sg41 -Visacov.rv32i_sb_cg.cp_imms_value\u000aisacov.rv32i_sb_cg.cp_rs1_toggle\u000aisacov.rv32i_sb_cg.cp_rs2_toggle\u000aisacov.rv32i_sb_cg.cp_imms_toggle -p348 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp349 -sg15 -(lp350 -sg53 -(lp351 -sg13 -(dp352 -g56 -I0 -ssbtp353 -asg88 -(lp354 -sg53 -(lp355 -sg13 -(dp356 -sbtp357 -a(V006_SH -p358 -g1 -(g18 -g3 -Ntp359 -Rp360 -(dp361 -g22 -I2 -sg8 -g358 -sg23 -VVP_IP003_P006 -p362 -sg25 -(dp363 -sg12 -I6 -sg15 -(lp364 -(V000 -p365 -g1 -(g29 -g3 -Ntp366 -Rp367 -(dp368 -g8 -V000 -p369 -sg23 -VVP_ISA_F003_S006_I000 -p370 -sg35 -Vsh rs1, rs2, imm\u000aM[rs1+imm][0:15] = rs2[0:15] -p371 -sg37 -VISA\u000aChapter 2.6 -p372 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p373 -sg41 -Visacov.rv32i_sh_cg.cp_rs1\u000aisacov.rv32i_sh_cg.cp_rs2 -p374 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp375 -sg15 -(lp376 -sg53 -(lp377 -sg13 -(dp378 -g56 -I0 -ssbtp379 -a(V001 -p380 -g1 -(g29 -g3 -Ntp381 -Rp382 -(dp383 -g8 -V001 -p384 -sg23 -VVP_ISA_F003_S006_I001 -p385 -sg35 -Vsh rs1, rs2, imm\u000aM[rs1+imm][0:15] = rs2[0:15] -p386 -sg37 -VISA\u000aChapter 2.6 -p387 -sg39 -VInput operands:\u000a\u000aimms value is +ve, -ve and zero\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aAll bits of imms are toggled\u000aUnaligned and aligned accesses to memory -p388 -sg41 -Visacov.rv32i_sh_cg.cp_imms_value\u000aisacov.rv32i_sh_cg.cp_rs1_toggle\u000aisacov.rv32i_sh_cg.cp_rs2_toggle\u000aisacov.rv32i_sh_cg.cp_imms_toggle\u000aisacov.rv32i_sh_cg.cp_aligned -p389 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp390 -sg15 -(lp391 -sg53 -(lp392 -sg13 -(dp393 -g56 -I0 -ssbtp394 -asg88 -(lp395 -sg53 -(lp396 -sg13 -(dp397 -sbtp398 -a(V007_SW -p399 -g1 -(g18 -g3 -Ntp400 -Rp401 -(dp402 -g22 -I2 -sg8 -g399 -sg23 -VVP_IP003_P007 -p403 -sg25 -(dp404 -sg12 -I7 -sg15 -(lp405 -(V000 -p406 -g1 -(g29 -g3 -Ntp407 -Rp408 -(dp409 -g8 -V000 -p410 -sg23 -VVP_ISA_F003_S007_I000 -p411 -sg35 -Vsw rs1, rs2, imm\u000aM[rs1+imm][0:31] = rs2[0:31] -p412 -sg37 -VISA\u000aChapter 2.6 -p413 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used. -p414 -sg41 -Visacov.rv32i_sw_cg.cp_rs1\u000aisacov.rv32i_sw_cg.cp_rs2 -p415 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp416 -sg15 -(lp417 -sg53 -(lp418 -sg13 -(dp419 -g56 -I0 -ssbtp420 -a(V001 -p421 -g1 -(g29 -g3 -Ntp422 -Rp423 -(dp424 -g8 -V001 -p425 -sg23 -VVP_ISA_F003_S007_I001 -p426 -sg35 -Vsw rs1, rs2, imm\u000aM[rs1+imm][0:31] = rs2[0:31] -p427 -sg37 -VISA\u000aChapter 2.6 -p428 -sg39 -VInput operands:\u000a\u000aimms value is +ve, -ve and zero\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aAll bits of imms are toggled\u000aUnaligned and aligned accesses to memory -p429 -sg41 -Visacov.rv32i_sw_cg.cp_imms_value\u000aisacov.rv32i_sw_cg.cp_rs1_toggle\u000aisacov.rv32i_sw_cg.cp_rs2_toggle\u000aisacov.rv32i_sw_cg.cp_imms_toggle\u000aisacov.rv32i_sw_cg.cp_aligned -p430 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp431 -sg15 -(lp432 -sg53 -(lp433 -sg13 -(dp434 -g56 -I0 -ssbtp435 -asg88 -(lp436 -sg53 -(lp437 -sg13 -(dp438 -sbtp439 -asVrfu_list_0 -p440 -(lp441 -sg88 -(lp442 -sVvptool_gitrev -p443 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p444 -sVio_fmt_gitrev -p445 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p446 -sVconfig_gitrev -p447 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p448 -sVymlcfg_gitrev -p449 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p450 -sbtp451 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml new file mode 100644 index 0000000000..cf67b09c1e --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml @@ -0,0 +1,454 @@ +!Feature +next_elt_id: 8 +name: RV32I Load and Store Instructions +id: 3 +display_order: 3 +subfeatures: !!omap +- 000_LB: !Subfeature + name: 000_LB + tag: VP_IP003_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S000_I000 + description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lb_cg.cp_rs1\nisacov.rv32i_lb_cg.cp_rd\nisacov.rv32i_lb_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S000_I001 + description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lb_cg.cp_immi_value\nisacov.rv32i_lb_cg.cp_rs1_toggle\n\ + isacov.rv32i_lb_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F003_S000_I002 + description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lb_cg.cp_rd_value\nisacov.rv32i_lb_cg.cp_rd_toggle" + comments: '' +- 001_LH: !Subfeature + name: 001_LH + tag: VP_IP003_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S001_I000 + description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lh_cg.cp_rs1\nisacov.rv32i_lh_cg.cp_rd\nisacov.rv32i_lh_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S001_I001 + description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\ + \ from memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lh_cg.cp_immi_value\nisacov.rv32i_lh_cg.cp_rs1_toggle\n\ + isacov.rv32i_lh_cg.cp_immi_toggle\nisacov.rv32i_lh_cg.cp_aligned" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F003_S001_I002 + description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lh_cg.cp_rd_value\nisacov.rv32i_lh_cg.cp_rd_toggle" + comments: '' +- 002_LW: !Subfeature + name: 002_LW + tag: VP_IP003_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S002_I000 + description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lw_cg.cp_rs1\nisacov.rv32i_lw_cg.cp_rd\nisacov.rv32i_lw_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S002_I001 + description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\ + \ from memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lw_cg.cp_immi_value\nisacov.rv32i_lw_cg.cp_rs1_toggle\n\ + isacov.rv32i_lw_cg.cp_immi_toggle\nisacov.rv32i_lw_cg.cp_aligned" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F003_S002_I002 + description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lw_cg.cp_rd_value\nisacov.rv32i_lw_cg.cp_rd_toggle" + comments: '' +- 003_LBU: !Subfeature + name: 003_LBU + tag: VP_IP003_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S003_I000 + description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lbu_cg.cp_rs1\nisacov.rv32i_lbu_cg.cp_rd\nisacov.rv32i_lbu_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S003_I001 + description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lbu_cg.cp_immi_value\nisacov.rv32i_lbu_cg.cp_rs1_toggle\n\ + isacov.rv32i_lbu_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F003_S003_I002 + description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd[7:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lbu_cg.cp_rd_value\nisacov.rv32i_lbu_cg.cp_rd_toggle" + comments: '' +- 004_LHU: !Subfeature + name: 004_LHU + tag: VP_IP003_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S004_I000 + description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lhu_cg.cp_rs1\nisacov.rv32i_lhu_cg.cp_rd\nisacov.rv32i_lhu_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S004_I001 + description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\ + \ from memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lhu_cg.cp_immi_value\nisacov.rv32i_lhu_cg.cp_rs1_toggle\n\ + isacov.rv32i_lhu_cg.cp_immi_toggle\nisacov.rv32i_lhu_cg.cp_aligned" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F003_S004_I002 + description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd[15:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lhu_cg.cp_rd_value\nisacov.rv32i_lhu_cg.cp_rd_toggle" + comments: '' +- 005_SB: !Subfeature + name: 005_SB + tag: VP_IP003_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S005_I000 + description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sb_cg.cp_rs1\nisacov.rv32i_sb_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S005_I001 + description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\ + \ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sb_cg.cp_imms_value\nisacov.rv32i_sb_cg.cp_rs1_toggle\n\ + isacov.rv32i_sb_cg.cp_rs2_toggle\nisacov.rv32i_sb_cg.cp_imms_toggle" + comments: '' +- 006_SH: !Subfeature + name: 006_SH + tag: VP_IP003_P006 + next_elt_id: 2 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S006_I000 + description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sh_cg.cp_rs1\nisacov.rv32i_sh_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S006_I001 + description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\ + \ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\ + \ toggled\nUnaligned and aligned accesses to memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sh_cg.cp_imms_value\nisacov.rv32i_sh_cg.cp_rs1_toggle\n\ + isacov.rv32i_sh_cg.cp_rs2_toggle\nisacov.rv32i_sh_cg.cp_imms_toggle\nisacov.rv32i_sh_cg.cp_aligned" + comments: '' +- 007_SW: !Subfeature + name: 007_SW + tag: VP_IP003_P007 + next_elt_id: 2 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F003_S007_I000 + description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sw_cg.cp_rs1\nisacov.rv32i_sw_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F003_S007_I001 + description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]" + reqt_doc: "ISA\nChapter 2.6" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\ + \ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\ + \ toggled\nUnaligned and aligned accesses to memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sw_cg.cp_imms_value\nisacov.rv32i_sw_cg.cp_rs1_toggle\n\ + isacov.rv32i_sw_cg.cp_rs2_toggle\nisacov.rv32i_sw_cg.cp_imms_toggle\nisacov.rv32i_sw_cg.cp_aligned" + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck deleted file mode 100644 index bd77b2b90b..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.pck +++ /dev/null @@ -1,157 +0,0 @@ -(VRV32I Memory Ordering Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I1 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I4 -sVwid_order -p12 -I4 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_FENCE -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP004_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F004_S000_I000 -p34 -sVdescription -p35 -VFence operation executed\u000aImplementation is microarchitecture specific -p36 -sVpurpose -p37 -VISA\u000aChapter 2.7 -p38 -sVverif_goals -p39 -VInstruction executed -p40 -sVcoverage_loc -p41 -Visacov.rv32i_fence.cp_fixed -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -asVrfu_list_1 -p58 -(lp59 -sg53 -(lp60 -sg13 -(dp61 -sbtp62 -asVrfu_list_0 -p63 -(lp64 -sg58 -(lp65 -sVvptool_gitrev -p66 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p67 -sVio_fmt_gitrev -p68 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p69 -sVconfig_gitrev -p70 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p71 -sVymlcfg_gitrev -p72 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p73 -sbtp74 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml new file mode 100644 index 0000000000..01a61498b7 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml @@ -0,0 +1,33 @@ +!Feature +next_elt_id: 1 +name: RV32I Memory Ordering Instructions +id: 4 +display_order: 4 +subfeatures: !!omap +- 000_FENCE: !Subfeature + name: 000_FENCE + tag: VP_IP004_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F004_S000_I000 + description: "Fence operation executed\nImplementation is microarchitecture\ + \ specific" + reqt_doc: "ISA\nChapter 2.7" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_fence.cp_fixed + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck deleted file mode 100644 index f17fd3ee40..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.pck +++ /dev/null @@ -1,284 +0,0 @@ -(VRV32I Environment Call and Breakpoints -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I2 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I5 -sVwid_order -p12 -I5 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_ECALL -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I2 -sg8 -g17 -sVtag -p23 -VVP_IP005_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F005_S000_I000 -p34 -sVdescription -p35 -VSoftware exception vector entered -p36 -sVpurpose -p37 -VISA\u000aChapter 2.8 -p38 -sVverif_goals -p39 -VInstruction executed -p40 -sVcoverage_loc -p41 -Visacov.rv32i_ecall.cp_fixed -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F005_S000_I001 -p63 -sg35 -VReturn control to a debugger -p64 -sg37 -VISA\u000aChapter 2.8 -p65 -sg39 -VInstruction executed -p66 -sg41 -Visacov.rv32i_ebreak.cp_fixed -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -asVrfu_list_1 -p73 -(lp74 -sg53 -(lp75 -sg13 -(dp76 -sbtp77 -a(V001_EBREAK -p78 -g1 -(g18 -g3 -Ntp79 -Rp80 -(dp81 -g22 -I1 -sg8 -g78 -sg23 -VVP_IP005_P001 -p82 -sg25 -(dp83 -sg12 -I1 -sg15 -(lp84 -(V000 -p85 -g1 -(g29 -g3 -Ntp86 -Rp87 -(dp88 -g8 -V000 -p89 -sg23 -VVP_ISA_F005_S001_I000 -p90 -sg35 -VReturn control to a debugger -p91 -sg37 -VISA\u000aChapter 2.8 -p92 -sg39 -VInstruction executed -p93 -sg41 -Visacov.rv32i_ebreak.cp_fixed -p94 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp95 -sg15 -(lp96 -sg53 -(lp97 -sg13 -(dp98 -Vlock_status -p99 -I0 -ssbtp100 -asg73 -(lp101 -sg53 -(lp102 -sg13 -(dp103 -sbtp104 -asVrfu_list_0 -p105 -(lp106 -sg73 -(lp107 -sVvptool_gitrev -p108 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p109 -sVio_fmt_gitrev -p110 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p111 -sVconfig_gitrev -p112 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p113 -sVymlcfg_gitrev -p114 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p115 -sbtp116 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml new file mode 100644 index 0000000000..85fd2a35ce --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml @@ -0,0 +1,70 @@ +!Feature +next_elt_id: 2 +name: RV32I Environment Call and Breakpoints +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_ECALL: !Subfeature + name: 000_ECALL + tag: VP_IP005_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F005_S000_I000 + description: Software exception vector entered + reqt_doc: "ISA\nChapter 2.8" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_ecall.cp_fixed + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F005_S000_I001 + description: Return control to a debugger + reqt_doc: "ISA\nChapter 2.8" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_ebreak.cp_fixed + comments: '' +- 001_EBREAK: !Subfeature + name: 001_EBREAK + tag: VP_IP005_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F005_S001_I000 + description: Return control to a debugger + reqt_doc: "ISA\nChapter 2.8" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_ebreak.cp_fixed + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck deleted file mode 100644 index 540f7f4954..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.pck +++ /dev/null @@ -1,780 +0,0 @@ -(VRV32M Multiplication Operations -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I7 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I6 -sVwid_order -p12 -I6 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_MUL -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP000_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F000_S000_I000 -p34 -sVdescription -p35 -Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored. -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 7.1 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32m_mul_cg.cp_rs1\u000aisacov.rv32m_mul_cg.cp_rs2\u000aisacov.rv32m_mul_cg.cp_rd\u000aisacov.rv32m_mul_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mul_cg.cp_rd_rs2_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F000_S000_I001 -p63 -sg35 -Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored. -p64 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p65 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p66 -sg41 -Visacov.rv32m_mul_cg.cp_rs1_value\u000aisacov.rv32m_mul_cg.cp_rs2_value\u000aisacov.rv32m_mul_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mul_cg.cp_rs1_toggle \u000aisacov.rv32m_mul_cg.cp_rs2_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F000_S000_I002 -p78 -sg35 -Vmul rd, rs1, rs2\u000ax[rd] = x[rs1] * x[rs2]\u000aArithmetic overflow is ignored. -p79 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p80 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32m_mul_cg.cp_rd_value\u000aisacov.rv32m_mul_cg.cp_rd_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -asVrfu_list_1 -p88 -(lp89 -sg53 -(lp90 -sg13 -(dp91 -sbtp92 -a(V001_MULH -p93 -g1 -(g18 -g3 -Ntp94 -Rp95 -(dp96 -g22 -I3 -sg8 -g93 -sg23 -VVP_IP000_P001 -p97 -sg25 -(dp98 -sg12 -I1 -sg15 -(lp99 -(V000 -p100 -g1 -(g29 -g3 -Ntp101 -Rp102 -(dp103 -g8 -V000 -p104 -sg23 -VVP_ISA_F000_S001_I000 -p105 -sg35 -Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers -p106 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p107 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p108 -sg41 -Visacov.rv32m_mulh_cg.cp_rs1\u000aisacov.rv32m_mulh_cg.cp_rs2\u000aisacov.rv32m_mulh_cg.cp_rd\u000aisacov.rv32m_mulh_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulh_cg.cp_rd_rs2_hazard -p109 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I32 -sg47 -g48 -sg49 -g48 -sg50 -(lp110 -sg15 -(lp111 -sg53 -(lp112 -sg13 -(dp113 -g56 -I0 -ssbtp114 -a(V001 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -V001 -p119 -sg23 -VVP_ISA_F000_S001_I001 -p120 -sg35 -Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers -p121 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p122 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p123 -sg41 -Visacov.rv32m_mulh_cg.cp_rs1_value\u000aisacov.rv32m_mulh_cg.cp_rs2_value\u000aisacov.rv32m_mulh_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulh_cg.cp_rs1_toggle \u000aisacov.rv32m_mulh_cg.cp_rs2_toggle -p124 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I32 -sg47 -g48 -sg49 -g48 -sg50 -(lp125 -sg15 -(lp126 -sg53 -(lp127 -sg13 -(dp128 -g56 -I0 -ssbtp129 -a(V002 -p130 -g1 -(g29 -g3 -Ntp131 -Rp132 -(dp133 -g8 -V002 -p134 -sg23 -VVP_ISA_F000_S001_I002 -p135 -sg35 -Vmulh rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000aBoth rs1 and rs2 treated as signed numbers -p136 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p137 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p138 -sg41 -Visacov.rv32m_mulh_cg.cp_rd_value\u000aisacov.rv32m_mulh_cg.cp_rd_toggle -p139 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp140 -sg15 -(lp141 -sg53 -(lp142 -sg13 -(dp143 -g56 -I0 -ssbtp144 -asg88 -(lp145 -sg53 -(lp146 -sg13 -(dp147 -sbtp148 -a(V002_MULHU -p149 -g1 -(g18 -g3 -Ntp150 -Rp151 -(dp152 -g22 -I3 -sg8 -g149 -sg23 -VVP_IP000_P002 -p153 -sg25 -(dp154 -sg12 -I2 -sg15 -(lp155 -(V000 -p156 -g1 -(g29 -g3 -Ntp157 -Rp158 -(dp159 -g8 -V000 -p160 -sg23 -VVP_ISA_F000_S002_I000 -p161 -sg35 -Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers -p162 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p163 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p164 -sg41 -Visacov.rv32m_mulhu_cg.cp_rs1\u000aisacov.rv32m_mulhu_cg.cp_rs2\u000aisacov.rv32m_mulhu_cg.cp_rd\u000aisacov.rv32m_mulhu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulhu_cg.cp_rd_rs2_hazard -p165 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp166 -sg15 -(lp167 -sg53 -(lp168 -sg13 -(dp169 -g56 -I0 -ssbtp170 -a(V001 -p171 -g1 -(g29 -g3 -Ntp172 -Rp173 -(dp174 -g8 -V001 -p175 -sg23 -VVP_ISA_F000_S002_I001 -p176 -sg35 -Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers -p177 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p178 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p179 -sg41 -Visacov.rv32m_mulhu_cg.cp_rs1_value\u000aisacov.rv32m_mulhu_cg.cp_rs2_value\u000aisacov.rv32m_mulhu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulhu_cg.cp_rs1_toggle \u000aisacov.rv32m_mulhu_cg.cp_rs2_toggle -p180 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp181 -sg15 -(lp182 -sg53 -(lp183 -sg13 -(dp184 -g56 -I0 -ssbtp185 -a(V002 -p186 -g1 -(g29 -g3 -Ntp187 -Rp188 -(dp189 -g8 -V002 -p190 -sg23 -VVP_ISA_F000_S002_I002 -p191 -sg35 -Vmulhu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >> XLEN\u000aBoth rs1 and rs2 treated as unsigned numbers -p192 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p193 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p194 -sg41 -Visacov.rv32m_mulhu_cg.cp_rd_value\u000aisacov.rv32m_mulhu_cg.cp_rd_toggle -p195 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp196 -sg15 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -g56 -I0 -ssbtp200 -asg88 -(lp201 -sg53 -(lp202 -sg13 -(dp203 -sbtp204 -a(V003_MULHSU -p205 -g1 -(g18 -g3 -Ntp206 -Rp207 -(dp208 -g22 -I3 -sg8 -g205 -sg23 -VVP_IP000_P003 -p209 -sg25 -(dp210 -sg12 -I3 -sg15 -(lp211 -(V000 -p212 -g1 -(g29 -g3 -Ntp213 -Rp214 -(dp215 -g8 -V000 -p216 -sg23 -VVP_ISA_F000_S003_I000 -p217 -sg35 -Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number -p218 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p219 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p220 -sg41 -Visacov.rv32m_mulhsu_cg.cp_rs1\u000aisacov.rv32m_mulhsu_cg.cp_rs2\u000aisacov.rv32m_mulhsu_cg.cp_rd\u000aisacov.rv32m_mulhsu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_mulhsu_cg.cp_rd_rs2_hazard -p221 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp222 -sg15 -(lp223 -sg53 -(lp224 -sg13 -(dp225 -g56 -I0 -ssbtp226 -a(V001 -p227 -g1 -(g29 -g3 -Ntp228 -Rp229 -(dp230 -g8 -V001 -p231 -sg23 -VVP_ISA_F000_S003_I001 -p232 -sg35 -Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number -p233 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p234 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p235 -sg41 -Visacov.rv32m_mulhsu_cg.cp_rs1_value\u000aisacov.rv32m_mulhsu_cg.cp_rs2_value\u000aisacov.rv32m_mulhsu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_mulhsu_cg.cp_rs1_toggle \u000aisacov.rv32m_mulhsu_cg.cp_rs2_toggle -p236 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp237 -sg15 -(lp238 -sg53 -(lp239 -sg13 -(dp240 -g56 -I0 -ssbtp241 -a(V002 -p242 -g1 -(g29 -g3 -Ntp243 -Rp244 -(dp245 -g8 -V002 -p246 -sg23 -VVP_ISA_F000_S003_I002 -p247 -sg35 -Vmulhsu rd, rs1, rs2\u000ax[rd] = (x[rs1] * x[rs2]) >>s XLEN\u000ars1 treated as signed number, rs2 treated as unsigned number -p248 -sg37 -VUnprivileged ISA\u000aChapter 7.1 -p249 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p250 -sg41 -Visacov.rv32m_mulhsu_cg.cp_rd_value\u000aisacov.rv32m_mulhsu_cg.cp_rd_toggle -p251 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp252 -sg15 -(lp253 -sg53 -(lp254 -sg13 -(dp255 -g56 -I0 -ssbtp256 -asg88 -(lp257 -sg53 -(lp258 -sg13 -(dp259 -sbtp260 -asVrfu_list_0 -p261 -(lp262 -sg88 -(lp263 -sVvptool_gitrev -p264 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p265 -sVio_fmt_gitrev -p266 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p267 -sVconfig_gitrev -p268 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p269 -sVymlcfg_gitrev -p270 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p271 -sbtp272 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml new file mode 100644 index 0000000000..fa7e671901 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml @@ -0,0 +1,275 @@ +!Feature +next_elt_id: 7 +name: RV32M Multiplication Operations +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_MUL: !Subfeature + name: 000_MUL + tag: VP_IP000_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F000_S000_I000 + description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ + \ is ignored." + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mul_cg.cp_rs1\nisacov.rv32m_mul_cg.cp_rs2\nisacov.rv32m_mul_cg.cp_rd\n\ + isacov.rv32m_mul_cg.cp_rd_rs1_hazard\nisacov.rv32m_mul_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F000_S000_I001 + description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ + \ is ignored." + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mul_cg.cp_rs1_value\nisacov.rv32m_mul_cg.cp_rs2_value\n\ + isacov.rv32m_mul_cg.cross_rs1_rs2_value\nisacov.rv32m_mul_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mul_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F000_S000_I002 + description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ + \ is ignored." + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mul_cg.cp_rd_value\nisacov.rv32m_mul_cg.cp_rd_toggle" + comments: '' +- 001_MULH: !Subfeature + name: 001_MULH + tag: VP_IP000_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F000_S001_I000 + description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ + \ rs1 and rs2 treated as signed numbers" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 32 + coverage_loc: "isacov.rv32m_mulh_cg.cp_rs1\nisacov.rv32m_mulh_cg.cp_rs2\n\ + isacov.rv32m_mulh_cg.cp_rd\nisacov.rv32m_mulh_cg.cp_rd_rs1_hazard\nisacov.rv32m_mulh_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F000_S001_I001 + description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ + \ rs1 and rs2 treated as signed numbers" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 32 + coverage_loc: "isacov.rv32m_mulh_cg.cp_rs1_value\nisacov.rv32m_mulh_cg.cp_rs2_value\n\ + isacov.rv32m_mulh_cg.cross_rs1_rs2_value\nisacov.rv32m_mulh_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mulh_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F000_S001_I002 + description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ + \ rs1 and rs2 treated as signed numbers" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulh_cg.cp_rd_value\nisacov.rv32m_mulh_cg.cp_rd_toggle" + comments: '' +- 002_MULHU: !Subfeature + name: 002_MULHU + tag: VP_IP000_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F000_S002_I000 + description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ + \ rs1 and rs2 treated as unsigned numbers" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhu_cg.cp_rs1\nisacov.rv32m_mulhu_cg.cp_rs2\n\ + isacov.rv32m_mulhu_cg.cp_rd\nisacov.rv32m_mulhu_cg.cp_rd_rs1_hazard\nisacov.rv32m_mulhu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F000_S002_I001 + description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ + \ rs1 and rs2 treated as unsigned numbers" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhu_cg.cp_rs1_value\nisacov.rv32m_mulhu_cg.cp_rs2_value\n\ + isacov.rv32m_mulhu_cg.cross_rs1_rs2_value\nisacov.rv32m_mulhu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mulhu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F000_S002_I002 + description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ + \ rs1 and rs2 treated as unsigned numbers" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhu_cg.cp_rd_value\nisacov.rv32m_mulhu_cg.cp_rd_toggle" + comments: '' +- 003_MULHSU: !Subfeature + name: 003_MULHSU + tag: VP_IP000_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F000_S003_I000 + description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ + \ treated as signed number, rs2 treated as unsigned number" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rs1\nisacov.rv32m_mulhsu_cg.cp_rs2\n\ + isacov.rv32m_mulhsu_cg.cp_rd\nisacov.rv32m_mulhsu_cg.cp_rd_rs1_hazard\n\ + isacov.rv32m_mulhsu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F000_S003_I001 + description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ + \ treated as signed number, rs2 treated as unsigned number" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rs1_value\nisacov.rv32m_mulhsu_cg.cp_rs2_value\n\ + isacov.rv32m_mulhsu_cg.cross_rs1_rs2_value\nisacov.rv32m_mulhsu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mulhsu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F000_S003_I002 + description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ + \ treated as signed number, rs2 treated as unsigned number" + reqt_doc: "Unprivileged ISA\nChapter 7.1" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rd_value\nisacov.rv32m_mulhsu_cg.cp_rd_toggle" + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck deleted file mode 100644 index 057f15b89b..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.pck +++ /dev/null @@ -1,976 +0,0 @@ -(VRV32M Division Operations -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I4 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I7 -sVwid_order -p12 -I7 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_DIV -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I4 -sg8 -g17 -sVtag -p23 -VVP_IP007_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F007_S000_I000 -p34 -sVdescription -p35 -Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 7.2 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p40 -sVcoverage_loc -p41 -Visacov.rv32m_div_cg.cp_rs1\u000aisacov.rv32m_div_cg.cp_rs2\u000aisacov.rv32m_div_cg.cp_rd\u000aisacov.rv32m_div_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_div_cg.cp_rd_rs2_hazard -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -a(V001 -p58 -g1 -(g29 -g3 -Ntp59 -Rp60 -(dp61 -g8 -V001 -p62 -sg23 -VVP_ISA_F007_S000_I001 -p63 -sg35 -Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero -p64 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p65 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p66 -sg41 -Visacov.rv32m_div_cg.cp_rs1_value\u000aisacov.rv32m_div_cg.cp_rs2_value\u000aisacov.rv32m_div_cg.cross_rs1_rs2_value\u000aisacov.rv32m_div_cg.cp_rs1_toggle \u000aisacov.rv32m_div_cg.cp_rs2_toggle -p67 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp68 -sg15 -(lp69 -sg53 -(lp70 -sg13 -(dp71 -g56 -I0 -ssbtp72 -a(V002 -p73 -g1 -(g29 -g3 -Ntp74 -Rp75 -(dp76 -g8 -V002 -p77 -sg23 -VVP_ISA_F007_S000_I002 -p78 -sg35 -Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero -p79 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p80 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p81 -sg41 -Visacov.rv32m_div_cg.cp_rs1_value\u000aisacov.rv32m_div_cg.cp_rs2_value\u000aisacov.rv32m_div_cg.cross_rs1_rs2_value\u000aisacov.rv32m_div_cg.cp_rs1_toggle \u000aisacov.rv32m_div_cg.cp_rs2_toggle -p82 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp83 -sg15 -(lp84 -sg53 -(lp85 -sg13 -(dp86 -g56 -I0 -ssbtp87 -a(V003 -p88 -g1 -(g29 -g3 -Ntp89 -Rp90 -(dp91 -g8 -V003 -p92 -sg23 -VVP_ISA_F007_S000_I003 -p93 -sg35 -Vdiv rd, rs1, rs2\u000ax[rd] = x[rs1] / x[rs2]\u000ard is calculated using signed arithmetic; rounding towards zero -p94 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p95 -sg39 -VExercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns rd = -2^31).\u000aExercise division by zero (returns -1 ; all bits set) -p96 -sg41 -Visacov.rv32m_div_results_cg.cp_div_special_results\u000aisacov.rv32m_div_results_cg.cp_div_arithmetic_overflow -p97 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp98 -sg15 -(lp99 -sg53 -(lp100 -sg13 -(dp101 -g56 -I0 -ssbtp102 -asVrfu_list_1 -p103 -(lp104 -sg53 -(lp105 -sg13 -(dp106 -sbtp107 -a(V001_REM -p108 -g1 -(g18 -g3 -Ntp109 -Rp110 -(dp111 -g22 -I4 -sg8 -g108 -sg23 -VVP_IP007_P001 -p112 -sg25 -(dp113 -sg12 -I1 -sg15 -(lp114 -(V000 -p115 -g1 -(g29 -g3 -Ntp116 -Rp117 -(dp118 -g8 -V000 -p119 -sg23 -VVP_ISA_F007_S001_I000 -p120 -sg35 -Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) -p121 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p122 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p123 -sg41 -Visacov.rv32m_rem_cg.cp_rs1\u000aisacov.rv32m_rem_cg.cp_rs2\u000aisacov.rv32m_rem_cg.cp_rd\u000aisacov.rv32m_rem_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_rem_cg.cp_rd_rs2_hazard -p124 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp125 -sg15 -(lp126 -sg53 -(lp127 -sg13 -(dp128 -g56 -I0 -ssbtp129 -a(V001 -p130 -g1 -(g29 -g3 -Ntp131 -Rp132 -(dp133 -g8 -V001 -p134 -sg23 -VVP_ISA_F007_S001_I001 -p135 -sg35 -Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) -p136 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p137 -sg39 -VInput operands:\u000a\u000ars1 value is +ve, -ve and zero\u000ars2 value is +ve, -ve and zero\u000aAll combinations of rs1 and rs2 +ve, -ve, and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p138 -sg41 -Visacov.rv32m_rem_cg.cp_rs1_value\u000aisacov.rv32m_rem_cg.cp_rs2_value\u000aisacov.rv32m_rem_cg.cross_rs1_rs2_value\u000aisacov.rv32m_rem_cg.cp_rs1_toggle \u000aisacov.rv32m_rem_cg.cp_rs2_toggle -p139 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp140 -sg15 -(lp141 -sg53 -(lp142 -sg13 -(dp143 -g56 -I0 -ssbtp144 -a(V002 -p145 -g1 -(g29 -g3 -Ntp146 -Rp147 -(dp148 -g8 -V002 -p149 -sg23 -VVP_ISA_F007_S001_I002 -p150 -sg35 -Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) -p151 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p152 -sg39 -VOutput result:\u000a\u000ard value is +ve, -ve and zero\u000aAll bits of rd are toggled -p153 -sg41 -Visacov.rv32m_rem_cg.cp_rd_value\u000aisacov.rv32m_rem_cg.cp_rd_toggle -p154 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp155 -sg15 -(lp156 -sg53 -(lp157 -sg13 -(dp158 -g56 -I0 -ssbtp159 -a(V003 -p160 -g1 -(g29 -g3 -Ntp161 -Rp162 -(dp163 -g8 -V003 -p164 -sg23 -VVP_ISA_F007_S001_I003 -p165 -sg35 -Vrem rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) -p166 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p167 -sg39 -VExercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns rd = 0).\u000aExercise division by zero (returns rs1) -p168 -sg41 -Visacov.rv32m_rem_results_cg.cp_div_zero\u000aisacov.rv32m_rem_results_cg.cp_div_arithmetic_overflow -p169 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp170 -sg15 -(lp171 -sg53 -(lp172 -sg13 -(dp173 -g56 -I0 -ssbtp174 -asg103 -(lp175 -sg53 -(lp176 -sg13 -(dp177 -sbtp178 -a(V002_DIVU -p179 -g1 -(g18 -g3 -Ntp180 -Rp181 -(dp182 -g22 -I4 -sg8 -g179 -sg23 -VVP_IP007_P002 -p183 -sg25 -(dp184 -sg12 -I2 -sg15 -(lp185 -(V000 -p186 -g1 -(g29 -g3 -Ntp187 -Rp188 -(dp189 -g8 -V000 -p190 -sg23 -VVP_ISA_F007_S002_I000 -p191 -sg35 -Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero -p192 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p193 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p194 -sg41 -Visacov.rv32m_divu_cg.cp_rs1\u000aisacov.rv32m_divu_cg.cp_rs2\u000aisacov.rv32m_divu_cg.cp_rd\u000aisacov.rv32m_divu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_divu_cg.cp_rd_rs2_hazard -p195 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp196 -sg15 -(lp197 -sg53 -(lp198 -sg13 -(dp199 -g56 -I0 -ssbtp200 -a(V001 -p201 -g1 -(g29 -g3 -Ntp202 -Rp203 -(dp204 -g8 -V001 -p205 -sg23 -VVP_ISA_F007_S002_I001 -p206 -sg35 -Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero -p207 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p208 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p209 -sg41 -Visacov.rv32m_divu_cg.cp_rs1_value\u000aisacov.rv32m_divu_cg.cp_rs2_value\u000aisacov.rv32m_divu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_divu_cg.cp_rs1_toggle \u000aisacov.rv32m_divu_cg.cp_rs2_toggle -p210 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp211 -sg15 -(lp212 -sg53 -(lp213 -sg13 -(dp214 -g56 -I0 -ssbtp215 -a(V002 -p216 -g1 -(g29 -g3 -Ntp217 -Rp218 -(dp219 -g8 -V002 -p220 -sg23 -VVP_ISA_F007_S002_I002 -p221 -sg35 -Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero -p222 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p223 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p224 -sg41 -Visacov.rv32m_divu_cg.cp_rd_value\u000aisacov.rv32m_divu_cg.cp_rd_toggle -p225 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp226 -sg15 -(lp227 -sg53 -(lp228 -sg13 -(dp229 -g56 -I0 -ssbtp230 -a(V003 -p231 -g1 -(g29 -g3 -Ntp232 -Rp233 -(dp234 -g8 -V003 -p235 -sg23 -VVP_ISA_F007_S002_I003 -p236 -sg35 -Vdivu rd, rs1, rs2\u000ax[rd] = x[rs1] u/ x[rs2]\u000ard is calculated using unsigned arithmetic; rounding towards zero -p237 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p238 -sg39 -VExercise division by zero (returns 2^32-1 ; all bits set) -p239 -sg41 -Visacov.rv32m_divu_results_cg.cp_div_zero -p240 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp241 -sg15 -(lp242 -sg53 -(lp243 -sg13 -(dp244 -g56 -I0 -ssbtp245 -asg103 -(lp246 -sg53 -(lp247 -sg13 -(dp248 -sbtp249 -a(V003_REMU -p250 -g1 -(g18 -g3 -Ntp251 -Rp252 -(dp253 -g22 -I4 -sg8 -g250 -sg23 -VVP_IP007_P003 -p254 -sg25 -(dp255 -sg12 -I3 -sg15 -(lp256 -(V000 -p257 -g1 -(g29 -g3 -Ntp258 -Rp259 -(dp260 -g8 -V000 -p261 -sg23 -VVP_ISA_F007_S003_I000 -p262 -sg35 -Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU -p263 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p264 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p265 -sg41 -Visacov.rv32m_remu_cg.cp_rs1\u000aisacov.rv32m_remu_cg.cp_rs2\u000aisacov.rv32m_remu_cg.cp_rd\u000aisacov.rv32m_remu_cg.cp_rd_rs1_hazard\u000aisacov.rv32m_remu_cg.cp_rd_rs2_hazard -p266 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp267 -sg15 -(lp268 -sg53 -(lp269 -sg13 -(dp270 -g56 -I0 -ssbtp271 -a(V001 -p272 -g1 -(g29 -g3 -Ntp273 -Rp274 -(dp275 -g8 -V001 -p276 -sg23 -VVP_ISA_F007_S003_I001 -p277 -sg35 -Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU -p278 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p279 -sg39 -VInput operands:\u000a\u000ars1 value is non-zero and zero\u000ars2 value is non-zero and zero\u000aAll combinations of rs1 and rs2 non-zero and zero values are used\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p280 -sg41 -Visacov.rv32m_remu_cg.cp_rs1_value\u000aisacov.rv32m_remu_cg.cp_rs2_value\u000aisacov.rv32m_remu_cg.cross_rs1_rs2_value\u000aisacov.rv32m_remu_cg.cp_rs1_toggle \u000aisacov.rv32m_remu_cg.cp_rs2_toggle -p281 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp282 -sg15 -(lp283 -sg53 -(lp284 -sg13 -(dp285 -g56 -I0 -ssbtp286 -a(V002 -p287 -g1 -(g29 -g3 -Ntp288 -Rp289 -(dp290 -g8 -V002 -p291 -sg23 -VVP_ISA_F007_S003_I002 -p292 -sg35 -Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU -p293 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p294 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p295 -sg41 -Visacov.rv32m_remu_cg.cp_rd_value\u000aisacov.rv32m_remu_cg.cp_rd_toggle -p296 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp297 -sg15 -(lp298 -sg53 -(lp299 -sg13 -(dp300 -g56 -I0 -ssbtp301 -a(V003 -p302 -g1 -(g29 -g3 -Ntp303 -Rp304 -(dp305 -g8 -V003 -p306 -sg23 -VVP_ISA_F007_S003_I003 -p307 -sg35 -Vremu rd, rs1, rs2\u000ax[rd] = x[rs1] % x[rs2]\u000ard is calculated using unsigned arithmetic; remainder from the same division than DIVU -p308 -sg37 -VUnprivileged ISA\u000aChapter 7.2 -p309 -sg39 -VExercise division by zero (returns rs1) -p310 -sg41 -Visacov.rv32m_remu_results_cg.cp_div_zero -p311 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g48 -sg49 -g48 -sg50 -(lp312 -sg15 -(lp313 -sg53 -(lp314 -sg13 -(dp315 -g56 -I0 -ssbtp316 -asg103 -(lp317 -sg53 -(lp318 -sg13 -(dp319 -sbtp320 -asVrfu_list_0 -p321 -(lp322 -sg103 -(lp323 -sVvptool_gitrev -p324 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p325 -sVio_fmt_gitrev -p326 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p327 -sVconfig_gitrev -p328 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p329 -sVymlcfg_gitrev -p330 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p331 -sbtp332 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml new file mode 100644 index 0000000000..bb6964c430 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml @@ -0,0 +1,350 @@ +!Feature +next_elt_id: 4 +name: RV32M Division Operations +id: 7 +display_order: 7 +subfeatures: !!omap +- 000_DIV: !Subfeature + name: 000_DIV + tag: VP_IP007_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S000_I000 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_cg.cp_rs1\nisacov.rv32m_div_cg.cp_rs2\nisacov.rv32m_div_cg.cp_rd\n\ + isacov.rv32m_div_cg.cp_rd_rs1_hazard\nisacov.rv32m_div_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S000_I001 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_cg.cp_rs1_value\nisacov.rv32m_div_cg.cp_rs2_value\n\ + isacov.rv32m_div_cg.cross_rs1_rs2_value\nisacov.rv32m_div_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_div_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F007_S000_I002 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_cg.cp_rs1_value\nisacov.rv32m_div_cg.cp_rs2_value\n\ + isacov.rv32m_div_cg.cross_rs1_rs2_value\nisacov.rv32m_div_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_div_cg.cp_rs2_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F007_S000_I003 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns\ + \ rd = -2^31).\nExercise division by zero (returns -1 ; all bits set)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_results_cg.cp_div_special_results\nisacov.rv32m_div_results_cg.cp_div_arithmetic_overflow" + comments: '' +- 001_REM: !Subfeature + name: 001_REM + tag: VP_IP007_P001 + next_elt_id: 4 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S001_I000 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_cg.cp_rs1\nisacov.rv32m_rem_cg.cp_rs2\nisacov.rv32m_rem_cg.cp_rd\n\ + isacov.rv32m_rem_cg.cp_rd_rs1_hazard\nisacov.rv32m_rem_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S001_I001 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_cg.cp_rs1_value\nisacov.rv32m_rem_cg.cp_rs2_value\n\ + isacov.rv32m_rem_cg.cross_rs1_rs2_value\nisacov.rv32m_rem_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_rem_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F007_S001_I002 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_cg.cp_rd_value\nisacov.rv32m_rem_cg.cp_rd_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F007_S001_I003 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns\ + \ rd = 0).\nExercise division by zero (returns rs1)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_results_cg.cp_div_zero\nisacov.rv32m_rem_results_cg.cp_div_arithmetic_overflow" + comments: '' +- 002_DIVU: !Subfeature + name: 002_DIVU + tag: VP_IP007_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S002_I000 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_divu_cg.cp_rs1\nisacov.rv32m_divu_cg.cp_rs2\n\ + isacov.rv32m_divu_cg.cp_rd\nisacov.rv32m_divu_cg.cp_rd_rs1_hazard\nisacov.rv32m_divu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S002_I001 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_divu_cg.cp_rs1_value\nisacov.rv32m_divu_cg.cp_rs2_value\n\ + isacov.rv32m_divu_cg.cross_rs1_rs2_value\nisacov.rv32m_divu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_divu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F007_S002_I002 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_divu_cg.cp_rd_value\nisacov.rv32m_divu_cg.cp_rd_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F007_S002_I003 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Exercise division by zero (returns 2^32-1 ; all bits set) + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32m_divu_results_cg.cp_div_zero + comments: '' +- 003_REMU: !Subfeature + name: 003_REMU + tag: VP_IP007_P003 + next_elt_id: 4 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S003_I000 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_remu_cg.cp_rs1\nisacov.rv32m_remu_cg.cp_rs2\n\ + isacov.rv32m_remu_cg.cp_rd\nisacov.rv32m_remu_cg.cp_rd_rs1_hazard\nisacov.rv32m_remu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S003_I001 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_remu_cg.cp_rs1_value\nisacov.rv32m_remu_cg.cp_rs2_value\n\ + isacov.rv32m_remu_cg.cross_rs1_rs2_value\nisacov.rv32m_remu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_remu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F007_S003_I002 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_remu_cg.cp_rd_value\nisacov.rv32m_remu_cg.cp_rd_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F007_S003_I003 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Exercise division by zero (returns rs1) + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32m_remu_results_cg.cp_div_zero + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck deleted file mode 100644 index 2844a13db8..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.pck +++ /dev/null @@ -1,520 +0,0 @@ -(VRV32A Load-Reserved/Store-Conditional Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I2 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I8 -sVwid_order -p12 -I8 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_LR.W -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I4 -sg8 -g17 -sVtag -p23 -VVP_IP008_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F008_S000_I000 -p34 -sVdescription -p35 -Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 8.2 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F008_S000_I001 -p62 -sg35 -Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception -p63 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p64 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -a(V002 -p71 -g1 -(g29 -g3 -Ntp72 -Rp73 -(dp74 -g8 -V002 -p75 -sg23 -VVP_ISA_F008_S000_I002 -p76 -sg35 -Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception -p77 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p78 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p79 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp80 -sg15 -(lp81 -sg52 -(lp82 -sg13 -(dp83 -g55 -I0 -ssbtp84 -a(V003 -p85 -g1 -(g29 -g3 -Ntp86 -Rp87 -(dp88 -g8 -V003 -p89 -sg23 -VVP_ISA_F008_S000_I003 -p90 -sg35 -Vlr.w rd, (rs1)\u000ard = [rs1]\u000aA load occurs to address at rs1 with the results loaded to rd.\u000aMisaligned address should cause an exception -p91 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p92 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exceptio -p93 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp94 -sg15 -(lp95 -sg52 -(lp96 -sg13 -(dp97 -g55 -I0 -ssbtp98 -asVrfu_list_1 -p99 -(lp100 -sg52 -(lp101 -sg13 -(dp102 -sbtp103 -a(V001_SC.W -p104 -g1 -(g18 -g3 -Ntp105 -Rp106 -(dp107 -g22 -I4 -sg8 -g104 -sg23 -VVP_IP008_P001 -p108 -sg25 -(dp109 -sg12 -I1 -sg15 -(lp110 -(V000 -p111 -g1 -(g29 -g3 -Ntp112 -Rp113 -(dp114 -g8 -V000 -p115 -sg23 -VVP_ISA_F008_S001_I000 -p116 -sg35 -Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds. -p117 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p118 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p119 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp120 -sg15 -(lp121 -sg52 -(lp122 -sg13 -(dp123 -g55 -I0 -ssbtp124 -a(V001 -p125 -g1 -(g29 -g3 -Ntp126 -Rp127 -(dp128 -g8 -V001 -p129 -sg23 -VVP_ISA_F008_S001_I001 -p130 -sg35 -Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds. -p131 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p132 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p133 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp134 -sg15 -(lp135 -sg52 -(lp136 -sg13 -(dp137 -g55 -I0 -ssbtp138 -a(V002 -p139 -g1 -(g29 -g3 -Ntp140 -Rp141 -(dp142 -g8 -V002 -p143 -sg23 -VVP_ISA_F008_S001_I002 -p144 -sg35 -Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds. -p145 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p146 -sg39 -VOutput result:\u000a\u000ard is either zero or non-zero to indicate success or failure, respectively -p147 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp148 -sg15 -(lp149 -sg52 -(lp150 -sg13 -(dp151 -g55 -I0 -ssbtp152 -a(V003 -p153 -g1 -(g29 -g3 -Ntp154 -Rp155 -(dp156 -g8 -V003 -p157 -sg23 -VVP_ISA_F008_S001_I003 -p158 -sg35 -Vsc.w rd, rs2, (rs1)\u000a[rs1] = rs2\u000ard = exokay ? 0 : 1\u000aA store occurs to address at rs1 with data from rs2.\u000aIf the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur.\u000aIf the reservation set passes, then rd is set to a zero-value and the store succeeds. -p159 -sg37 -VUnprivileged ISA\u000aChapter 8.2 -p160 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p161 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp162 -sg15 -(lp163 -sg52 -(lp164 -sg13 -(dp165 -g55 -I0 -ssbtp166 -asg99 -(lp167 -sg52 -(lp168 -sg13 -(dp169 -sbtp170 -asVrfu_list_0 -p171 -(lp172 -sg99 -(lp173 -sVvptool_gitrev -p174 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p175 -sVio_fmt_gitrev -p176 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p177 -sVconfig_gitrev -p178 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p179 -sVymlcfg_gitrev -p180 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p181 -sbtp182 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml new file mode 100644 index 0000000000..9677eec744 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml @@ -0,0 +1,179 @@ +!Feature +next_elt_id: 2 +name: RV32A Load-Reserved/Store-Conditional Instructions +id: 8 +display_order: 8 +subfeatures: !!omap +- 000_LR.W: !Subfeature + name: 000_LR.W + tag: VP_IP008_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S000_I000 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S000_I001 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S000_I002 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F008_S000_I003 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exceptio" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_SC.W: !Subfeature + name: 001_SC.W + tag: VP_IP008_P001 + next_elt_id: 4 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S001_I000 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used\nAll possible register combinations where rs2\ + \ == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S001_I001 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S001_I002 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd is either zero or non-zero to indicate\ + \ success or failure, respectively" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F008_S001_I003 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: "Unprivileged ISA\nChapter 8.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck deleted file mode 100644 index 09577a56f1..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.pck +++ /dev/null @@ -1,2059 +0,0 @@ -(VRV32A Atomic Memory Operations -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I9 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I9 -sVwid_order -p12 -I9 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_AMOSWAP.W -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I4 -sg8 -g17 -sVtag -p23 -VVP_IP009_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F009_S000_I000 -p34 -sVdescription -p35 -Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1) -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 8.4 -p38 -sVverif_goals -p39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F009_S000_I001 -p62 -sg35 -Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1) -p63 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p64 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -a(V002 -p71 -g1 -(g29 -g3 -Ntp72 -Rp73 -(dp74 -g8 -V002 -p75 -sg23 -VVP_ISA_F009_S000_I002 -p76 -sg35 -Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1) -p77 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p78 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p79 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp80 -sg15 -(lp81 -sg52 -(lp82 -sg13 -(dp83 -g55 -I0 -ssbtp84 -a(V003 -p85 -g1 -(g29 -g3 -Ntp86 -Rp87 -(dp88 -g8 -V003 -p89 -sg23 -VVP_ISA_F009_S000_I003 -p90 -sg35 -Vamoswap.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2\u000aA load occurs from the address at rs1 into rd.\u000aThe value at rs2 is then written back to the address at (rs1) -p91 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p92 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p93 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp94 -sg15 -(lp95 -sg52 -(lp96 -sg13 -(dp97 -g55 -I0 -ssbtp98 -asVrfu_list_1 -p99 -(lp100 -sg52 -(lp101 -sg13 -(dp102 -sbtp103 -a(V001_AMOADD.W -p104 -g1 -(g18 -g3 -Ntp105 -Rp106 -(dp107 -g22 -I4 -sg8 -g104 -sg23 -VVP_IP009_P001 -p108 -sg25 -(dp109 -sg12 -I1 -sg15 -(lp110 -(V000 -p111 -g1 -(g29 -g3 -Ntp112 -Rp113 -(dp114 -g8 -V000 -p115 -sg23 -VVP_ISA_F009_S001_I000 -p116 -sg35 -Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) -p117 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p118 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p119 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp120 -sg15 -(lp121 -sg52 -(lp122 -sg13 -(dp123 -g55 -I0 -ssbtp124 -a(V001 -p125 -g1 -(g29 -g3 -Ntp126 -Rp127 -(dp128 -g8 -V001 -p129 -sg23 -VVP_ISA_F009_S001_I001 -p130 -sg35 -Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) -p131 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p132 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000a+ve, -ve and zero values of rs2 are used -p133 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp134 -sg15 -(lp135 -sg52 -(lp136 -sg13 -(dp137 -g55 -I0 -ssbtp138 -a(V002 -p139 -g1 -(g29 -g3 -Ntp140 -Rp141 -(dp142 -g8 -V002 -p143 -sg23 -VVP_ISA_F009_S001_I002 -p144 -sg35 -Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) -p145 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p146 -sg39 -VOutput result: \u000a\u000a+ve, -ve and zero values of rd are used\u000aAll bits of rd are toggled -p147 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp148 -sg15 -(lp149 -sg52 -(lp150 -sg13 -(dp151 -g55 -I0 -ssbtp152 -a(V003 -p153 -g1 -(g29 -g3 -Ntp154 -Rp155 -(dp156 -g8 -V003 -p157 -sg23 -VVP_ISA_F009_S001_I003 -p158 -sg35 -Vamoadd.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 + [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) -p159 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p160 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p161 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp162 -sg15 -(lp163 -sg52 -(lp164 -sg13 -(dp165 -g55 -I0 -ssbtp166 -asg99 -(lp167 -sg52 -(lp168 -sg13 -(dp169 -sbtp170 -a(V002_AMOAND.W -p171 -g1 -(g18 -g3 -Ntp172 -Rp173 -(dp174 -g22 -I4 -sg8 -g171 -sg23 -VVP_IP009_P002 -p175 -sg25 -(dp176 -sg12 -I2 -sg15 -(lp177 -(V000 -p178 -g1 -(g29 -g3 -Ntp179 -Rp180 -(dp181 -g8 -V000 -p182 -sg23 -VVP_ISA_F009_S002_I000 -p183 -sg35 -Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) -p184 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p185 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p186 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp187 -sg15 -(lp188 -sg52 -(lp189 -sg13 -(dp190 -g55 -I0 -ssbtp191 -a(V001 -p192 -g1 -(g29 -g3 -Ntp193 -Rp194 -(dp195 -g8 -V001 -p196 -sg23 -VVP_ISA_F009_S002_I001 -p197 -sg35 -Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) -p198 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p199 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used -p200 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp201 -sg15 -(lp202 -sg52 -(lp203 -sg13 -(dp204 -g55 -I0 -ssbtp205 -a(V002 -p206 -g1 -(g29 -g3 -Ntp207 -Rp208 -(dp209 -g8 -V002 -p210 -sg23 -VVP_ISA_F009_S002_I002 -p211 -sg35 -Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) -p212 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p213 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p214 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp215 -sg15 -(lp216 -sg52 -(lp217 -sg13 -(dp218 -g55 -I0 -ssbtp219 -a(V003 -p220 -g1 -(g29 -g3 -Ntp221 -Rp222 -(dp223 -g8 -V003 -p224 -sg23 -VVP_ISA_F009_S002_I003 -p225 -sg35 -Vamoand.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 & rs[1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) -p226 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p227 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p228 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp229 -sg15 -(lp230 -sg52 -(lp231 -sg13 -(dp232 -g55 -I0 -ssbtp233 -asg99 -(lp234 -sg52 -(lp235 -sg13 -(dp236 -sbtp237 -a(V003_AMOOR.W -p238 -g1 -(g18 -g3 -Ntp239 -Rp240 -(dp241 -g22 -I4 -sg8 -g238 -sg23 -VVP_IP009_P003 -p242 -sg25 -(dp243 -sg12 -I3 -sg15 -(lp244 -(V000 -p245 -g1 -(g29 -g3 -Ntp246 -Rp247 -(dp248 -g8 -V000 -p249 -sg23 -VVP_ISA_F009_S003_I000 -p250 -sg35 -Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) -p251 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p252 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p253 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp254 -sg15 -(lp255 -sg52 -(lp256 -sg13 -(dp257 -g55 -I0 -ssbtp258 -a(V001 -p259 -g1 -(g29 -g3 -Ntp260 -Rp261 -(dp262 -g8 -V001 -p263 -sg23 -VVP_ISA_F009_S003_I001 -p264 -sg35 -Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) -p265 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p266 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used -p267 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp268 -sg15 -(lp269 -sg52 -(lp270 -sg13 -(dp271 -g55 -I0 -ssbtp272 -a(V002 -p273 -g1 -(g29 -g3 -Ntp274 -Rp275 -(dp276 -g8 -V002 -p277 -sg23 -VVP_ISA_F009_S003_I002 -p278 -sg35 -Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) -p279 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p280 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p281 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp282 -sg15 -(lp283 -sg52 -(lp284 -sg13 -(dp285 -g55 -I0 -ssbtp286 -a(V003 -p287 -g1 -(g29 -g3 -Ntp288 -Rp289 -(dp290 -g8 -V003 -p291 -sg23 -VVP_ISA_F009_S003_I003 -p292 -sg35 -Vamoor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 | [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) -p293 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p294 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p295 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp296 -sg15 -(lp297 -sg52 -(lp298 -sg13 -(dp299 -g55 -I0 -ssbtp300 -asg99 -(lp301 -sg52 -(lp302 -sg13 -(dp303 -sbtp304 -a(V004_AMOXOR.W -p305 -g1 -(g18 -g3 -Ntp306 -Rp307 -(dp308 -g22 -I4 -sg8 -g305 -sg23 -VVP_IP009_P004 -p309 -sg25 -(dp310 -sg12 -I4 -sg15 -(lp311 -(V000 -p312 -g1 -(g29 -g3 -Ntp313 -Rp314 -(dp315 -g8 -V000 -p316 -sg23 -VVP_ISA_F009_S004_I000 -p317 -sg35 -Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) -p318 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p319 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p320 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp321 -sg15 -(lp322 -sg52 -(lp323 -sg13 -(dp324 -g55 -I0 -ssbtp325 -a(V001 -p326 -g1 -(g29 -g3 -Ntp327 -Rp328 -(dp329 -g8 -V001 -p330 -sg23 -VVP_ISA_F009_S004_I001 -p331 -sg35 -Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) -p332 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p333 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000aZero and non-zero values of rs2 are used -p334 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp335 -sg15 -(lp336 -sg52 -(lp337 -sg13 -(dp338 -g55 -I0 -ssbtp339 -a(V002 -p340 -g1 -(g29 -g3 -Ntp341 -Rp342 -(dp343 -g8 -V002 -p344 -sg23 -VVP_ISA_F009_S004_I002 -p345 -sg35 -Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) -p346 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p347 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p348 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp349 -sg15 -(lp350 -sg52 -(lp351 -sg13 -(dp352 -g55 -I0 -ssbtp353 -a(V003 -p354 -g1 -(g29 -g3 -Ntp355 -Rp356 -(dp357 -g8 -V003 -p358 -sg23 -VVP_ISA_F009_S004_I003 -p359 -sg35 -Vamoxor.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = rs2 ^ [rs1]\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) -p360 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p361 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p362 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp363 -sg15 -(lp364 -sg52 -(lp365 -sg13 -(dp366 -g55 -I0 -ssbtp367 -asg99 -(lp368 -sg52 -(lp369 -sg13 -(dp370 -sbtp371 -a(V005_AMOMAX.W -p372 -g1 -(g18 -g3 -Ntp373 -Rp374 -(dp375 -g22 -I4 -sg8 -g372 -sg23 -VVP_IP009_P005 -p376 -sg25 -(dp377 -sg12 -I5 -sg15 -(lp378 -(V000 -p379 -g1 -(g29 -g3 -Ntp380 -Rp381 -(dp382 -g8 -V000 -p383 -sg23 -VVP_ISA_F009_S005_I000 -p384 -sg35 -Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) -p385 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p386 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p387 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp388 -sg15 -(lp389 -sg52 -(lp390 -sg13 -(dp391 -g55 -I0 -ssbtp392 -a(V001 -p393 -g1 -(g29 -g3 -Ntp394 -Rp395 -(dp396 -g8 -V001 -p397 -sg23 -VVP_ISA_F009_S005_I001 -p398 -sg35 -Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) -p399 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p400 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled\u000a+ve, -ve and zero values of rs2 are used -p401 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp402 -sg15 -(lp403 -sg52 -(lp404 -sg13 -(dp405 -g55 -I0 -ssbtp406 -a(V002 -p407 -g1 -(g29 -g3 -Ntp408 -Rp409 -(dp410 -g8 -g407 -sg23 -VVP_ISA_F009_S005_I002 -p411 -sg35 -Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) -p412 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p413 -sg39 -VOutput result: \u000a\u000a+ve, -ve and zero values of rd are used\u000aAll bits of rd are toggled -p414 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp415 -sg15 -(lp416 -sg52 -(lp417 -sg13 -(dp418 -g55 -I0 -ssbtp419 -a(V003 -p420 -g1 -(g29 -g3 -Ntp421 -Rp422 -(dp423 -g8 -V003 -p424 -sg23 -VVP_ISA_F009_S005_I003 -p425 -sg35 -Vamomax.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) -p426 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p427 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p428 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp429 -sg15 -(lp430 -sg52 -(lp431 -sg13 -(dp432 -g55 -I0 -ssbtp433 -asg99 -(lp434 -sg52 -(lp435 -sg13 -(dp436 -sbtp437 -a(V006_AMOMAXU.W -p438 -g1 -(g18 -g3 -Ntp439 -Rp440 -(dp441 -g22 -I4 -sg8 -g438 -sg23 -VVP_IP009_P006 -p442 -sg25 -(dp443 -sg12 -I6 -sg15 -(lp444 -(V000 -p445 -g1 -(g29 -g3 -Ntp446 -Rp447 -(dp448 -g8 -V000 -p449 -sg23 -VVP_ISA_F009_S006_I000 -p450 -sg35 -Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) -p451 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p452 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p453 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp454 -sg15 -(lp455 -sg52 -(lp456 -sg13 -(dp457 -g55 -I0 -ssbtp458 -a(V001 -p459 -g1 -(g29 -g3 -Ntp460 -Rp461 -(dp462 -g8 -V001 -p463 -sg23 -VVP_ISA_F009_S006_I001 -p464 -sg35 -Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) -p465 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p466 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p467 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp468 -sg15 -(lp469 -sg52 -(lp470 -sg13 -(dp471 -g55 -I0 -ssbtp472 -a(V002 -p473 -g1 -(g29 -g3 -Ntp474 -Rp475 -(dp476 -g8 -V002 -p477 -sg23 -VVP_ISA_F009_S006_I002 -p478 -sg35 -Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) -p479 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p480 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p481 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp482 -sg15 -(lp483 -sg52 -(lp484 -sg13 -(dp485 -g55 -I0 -ssbtp486 -a(V003 -p487 -g1 -(g29 -g3 -Ntp488 -Rp489 -(dp490 -g8 -V003 -p491 -sg23 -VVP_ISA_F009_S006_I003 -p492 -sg35 -Vamomaxu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = max_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) -p493 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p494 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p495 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp496 -sg15 -(lp497 -sg52 -(lp498 -sg13 -(dp499 -g55 -I0 -ssbtp500 -asg99 -(lp501 -sg52 -(lp502 -sg13 -(dp503 -sbtp504 -a(V007_AMOMIN.W -p505 -g1 -(g18 -g3 -Ntp506 -Rp507 -(dp508 -g22 -I4 -sg8 -g505 -sg23 -VVP_IP009_P007 -p509 -sg25 -(dp510 -sg12 -I7 -sg15 -(lp511 -(V000 -p512 -g1 -(g29 -g3 -Ntp513 -Rp514 -(dp515 -g8 -V000 -p516 -sg23 -VVP_ISA_F009_S007_I000 -p517 -sg35 -Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) -p518 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p519 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p520 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp521 -sg15 -(lp522 -sg52 -(lp523 -sg13 -(dp524 -g55 -I0 -ssbtp525 -a(V001 -p526 -g1 -(g29 -g3 -Ntp527 -Rp528 -(dp529 -g8 -V001 -p530 -sg23 -VVP_ISA_F009_S007_I001 -p531 -sg35 -Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) -p532 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p533 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p534 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp535 -sg15 -(lp536 -sg52 -(lp537 -sg13 -(dp538 -g55 -I0 -ssbtp539 -a(V002 -p540 -g1 -(g29 -g3 -Ntp541 -Rp542 -(dp543 -g8 -V002 -p544 -sg23 -VVP_ISA_F009_S007_I002 -p545 -sg35 -Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) -p546 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p547 -sg39 -VOutput result: \u000a\u000a+ve, -ve and zero values of rd are used\u000aAll bits of rd are toggled -p548 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp549 -sg15 -(lp550 -sg52 -(lp551 -sg13 -(dp552 -g55 -I0 -ssbtp553 -a(V003 -p554 -g1 -(g29 -g3 -Ntp555 -Rp556 -(dp557 -g8 -V003 -p558 -sg23 -VVP_ISA_F009_S007_I003 -p559 -sg35 -Vamomin.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_signed(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) -p560 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p561 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p562 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp563 -sg15 -(lp564 -sg52 -(lp565 -sg13 -(dp566 -g55 -I0 -ssbtp567 -asg99 -(lp568 -sg52 -(lp569 -sg13 -(dp570 -sbtp571 -a(V008_AMOMINU.W -p572 -g1 -(g18 -g3 -Ntp573 -Rp574 -(dp575 -g22 -I4 -sg8 -g572 -sg23 -VVP_IP009_P008 -p576 -sg25 -(dp577 -sg12 -I8 -sg15 -(lp578 -(V000 -p579 -g1 -(g29 -g3 -Ntp580 -Rp581 -(dp582 -g8 -V000 -p583 -sg23 -VVP_ISA_F009_S008_I000 -p584 -sg35 -Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) -p585 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p586 -sg39 -VInput operands:\u000a\u000aAll possible rs1 registers are used.\u000aAll possible rs2 registers are used.\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs1 == rd are used\u000aAll possible register combinations where rs2 == rd are used -p587 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp588 -sg15 -(lp589 -sg52 -(lp590 -sg13 -(dp591 -g55 -I0 -ssbtp592 -a(V001 -p593 -g1 -(g29 -g3 -Ntp594 -Rp595 -(dp596 -g8 -V001 -p597 -sg23 -VVP_ISA_F009_S008_I001 -p598 -sg35 -Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) -p599 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p600 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled\u000aAll bits of rs2 are toggled -p601 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp602 -sg15 -(lp603 -sg52 -(lp604 -sg13 -(dp605 -g55 -I0 -ssbtp606 -a(V002 -p607 -g1 -(g29 -g3 -Ntp608 -Rp609 -(dp610 -g8 -V002 -p611 -sg23 -VVP_ISA_F009_S008_I002 -p612 -sg35 -Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) -p613 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p614 -sg39 -VOutput result: \u000a\u000aAll bits of rd are toggled -p615 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp616 -sg15 -(lp617 -sg52 -(lp618 -sg13 -(dp619 -g55 -I0 -ssbtp620 -a(V003 -p621 -g1 -(g29 -g3 -Ntp622 -Rp623 -(dp624 -g8 -V003 -p625 -sg23 -VVP_ISA_F009_S008_I003 -p626 -sg35 -Vamominu.w rd, rs2, (rs1)\u000ard = [rs1]\u000a[rs1] = min_unsigned(rs2, [rs1])\u000aA load occurs from the address at rs1 into rd.\u000aThe values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) -p627 -sg37 -VUnprivileged ISA\u000aChapter 8.4 -p628 -sg39 -VException:\u000a\u000aMisaligned address (non-32-bit aligned) will always cause exception -p629 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp630 -sg15 -(lp631 -sg52 -(lp632 -sg13 -(dp633 -g55 -I0 -ssbtp634 -asg99 -(lp635 -sg52 -(lp636 -sg13 -(dp637 -sbtp638 -asVrfu_list_0 -p639 -(lp640 -sg99 -(lp641 -sVvptool_gitrev -p642 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p643 -sVio_fmt_gitrev -p644 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p645 -sVconfig_gitrev -p646 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p647 -sVymlcfg_gitrev -p648 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p649 -sbtp650 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml new file mode 100644 index 0000000000..3c1a267e4f --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml @@ -0,0 +1,788 @@ +!Feature +next_elt_id: 9 +name: RV32A Atomic Memory Operations +id: 9 +display_order: 9 +subfeatures: !!omap +- 000_AMOSWAP.W: !Subfeature + name: 000_AMOSWAP.W + tag: VP_IP009_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S000_I000 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S000_I001 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S000_I002 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S000_I003 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_AMOADD.W: !Subfeature + name: 001_AMOADD.W + tag: VP_IP009_P001 + next_elt_id: 4 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S001_I000 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S001_I001 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\n+ve, -ve and zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S001_I002 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\ + All bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S001_I003 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_AMOAND.W: !Subfeature + name: 002_AMOAND.W + tag: VP_IP009_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S002_I000 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S002_I001 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S002_I002 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S002_I003 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_AMOOR.W: !Subfeature + name: 003_AMOOR.W + tag: VP_IP009_P003 + next_elt_id: 4 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S003_I000 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S003_I001 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S003_I002 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S003_I003 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_AMOXOR.W: !Subfeature + name: 004_AMOXOR.W + tag: VP_IP009_P004 + next_elt_id: 4 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S004_I000 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S004_I001 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S004_I002 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S004_I003 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_AMOMAX.W: !Subfeature + name: 005_AMOMAX.W + tag: VP_IP009_P005 + next_elt_id: 4 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S005_I000 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S005_I001 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\n+ve, -ve and zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S005_I002 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\ + All bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S005_I003 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 006_AMOMAXU.W: !Subfeature + name: 006_AMOMAXU.W + tag: VP_IP009_P006 + next_elt_id: 4 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S006_I000 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S006_I001 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S006_I002 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S006_I003 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 007_AMOMIN.W: !Subfeature + name: 007_AMOMIN.W + tag: VP_IP009_P007 + next_elt_id: 4 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S007_I000 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S007_I001 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S007_I002 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\ + All bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S007_I003 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 008_AMOMINU.W: !Subfeature + name: 008_AMOMINU.W + tag: VP_IP009_P008 + next_elt_id: 4 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S008_I000 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S008_I001 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S008_I002 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_F009_S008_I003 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: "Unprivileged ISA\nChapter 8.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck deleted file mode 100644 index 997752667d..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.pck +++ /dev/null @@ -1,2592 +0,0 @@ -(VRV32C Integer Computational Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I16 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I10 -sVwid_order -p12 -I10 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_C.LI -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I2 -sg8 -g17 -sVtag -p23 -VVP_IP008_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F008_S000_I000 -p34 -sVdescription -p35 -Vc.li rd, imm[5:0]\u000ax[rd] = sext(imm)\u000aExpands to addi rd, x0, imm[5:0]. Invalid when rd=x0.\u000ard is calculated using signed arithmetic -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 16.5 -p38 -sVverif_goals -p39 -VInput operands:\u000a\u000aAll bits of imm[5:0] are toggled -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F008_S000_I001 -p62 -sg35 -Vc.li rd, imm[5:0]\u000ax[rd] = sext(imm)\u000aExpands to addi rd, x0, imm[5:0]. Invalid when rd=x0.\u000ard is calculated using signed arithmetic -p63 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p64 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -asVrfu_list_1 -p71 -(lp72 -sg52 -(lp73 -sg13 -(dp74 -sbtp75 -a(V001_C.LUI -p76 -g1 -(g18 -g3 -Ntp77 -Rp78 -(dp79 -g22 -I2 -sg8 -g76 -sg23 -VVP_IP008_P001 -p80 -sg25 -(dp81 -sg12 -I1 -sg15 -(lp82 -(V000 -p83 -g1 -(g29 -g3 -Ntp84 -Rp85 -(dp86 -g8 -V000 -p87 -sg23 -VVP_ISA_F008_S001_I000 -p88 -sg35 -Vc.lui rd, nzimm[17:12]\u000ax[rd] = sext(nzimm[17:12] << 12)\u000aExpands to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\u000ard is calculated using signed arithmetic. -p89 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p90 -sg39 -VInput operands:\u000a\u000aAll bits of imm[17:12] are toggled -p91 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp92 -sg15 -(lp93 -sg52 -(lp94 -sg13 -(dp95 -g55 -I0 -ssbtp96 -a(V001 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V001 -p101 -sg23 -VVP_ISA_F008_S001_I001 -p102 -sg35 -Vc.lui rd, nzimm[17:12]\u000ax[rd] = sext(nzimm[17:12] << 12)\u000aExpands to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\u000ard is calculated using signed arithmetic. -p103 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p104 -sg39 -VOutput result:\u000a\u000aAll bits of rd[31:12] are toggled -p105 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -g55 -I0 -ssbtp110 -asg71 -(lp111 -sg52 -(lp112 -sg13 -(dp113 -sbtp114 -a(V002_C.ADDI -p115 -g1 -(g18 -g3 -Ntp116 -Rp117 -(dp118 -g22 -I3 -sg8 -g115 -sg23 -VVP_IP008_P002 -p119 -sg25 -(dp120 -sg12 -I2 -sg15 -(lp121 -(V000 -p122 -g1 -(g29 -g3 -Ntp123 -Rp124 -(dp125 -g8 -V000 -p126 -sg23 -VVP_ISA_F008_S002_I000 -p127 -sg35 -Vc.addi rd, nzimm[5:0]\u000ax[rd] = x[rd] + sext(nzimm[5:0])\u000aExpands to addi rd, rd, nzimm[5:0].\u000aInvalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored.\u000ard is calculated using signed arithmetic. -p128 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p129 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p130 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp131 -sg15 -(lp132 -sg52 -(lp133 -sg13 -(dp134 -g55 -I0 -ssbtp135 -a(V001 -p136 -g1 -(g29 -g3 -Ntp137 -Rp138 -(dp139 -g8 -V001 -p140 -sg23 -VVP_ISA_F008_S002_I001 -p141 -sg35 -Vc.addi rd, nzimm[5:0]\u000ax[rd] = x[rd] + sext(nzimm[5:0])\u000aExpands to addi rd, rd, nzimm[5:0].\u000aInvalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored.\u000ard is calculated using signed arithmetic. -p142 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p143 -sg39 -VInput operands:\u000a\u000aAll inputs bits of rd before instruction execution are toggled\u000aAll bits of nzimm are toggled -p144 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp145 -sg15 -(lp146 -sg52 -(lp147 -sg13 -(dp148 -g55 -I0 -ssbtp149 -a(V002 -p150 -g1 -(g29 -g3 -Ntp151 -Rp152 -(dp153 -g8 -V002 -p154 -sg23 -VVP_ISA_F008_S002_I002 -p155 -sg35 -Vc.addi rd, nzimm[5:0]\u000ax[rd] = x[rd] + sext(nzimm[5:0])\u000aExpands to addi rd, rd, nzimm[5:0].\u000aInvalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored.\u000ard is calculated using signed arithmetic. -p156 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p157 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p158 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp159 -sg15 -(lp160 -sg52 -(lp161 -sg13 -(dp162 -g55 -I0 -ssbtp163 -asg71 -(lp164 -sg52 -(lp165 -sg13 -(dp166 -sbtp167 -a(V003_C.ADDI16SP -p168 -g1 -(g18 -g3 -Ntp169 -Rp170 -(dp171 -g22 -I3 -sg8 -g168 -sg23 -VVP_IP008_P003 -p172 -sg25 -(dp173 -sg12 -I3 -sg15 -(lp174 -(V000 -p175 -g1 -(g29 -g3 -Ntp176 -Rp177 -(dp178 -g8 -V000 -p179 -sg23 -VVP_ISA_F008_S003_I000 -p180 -sg35 -Vc.addi16sp nzimm[9:4]\u000ax[2] = x[2] + sext(nzimm[9:4])\u000aExpands to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\u000ard is calculated using signed arithmetic. -p181 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p182 -sg39 -VInput operands:\u000a\u000a+ve and -ve values of nzimm are used\u000aAll bits of nzimm[9:4] are toggled\u000aAll bits of x2 before instruction execution are toggled -p183 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp184 -sg15 -(lp185 -sg52 -(lp186 -sg13 -(dp187 -g55 -I0 -ssbtp188 -a(V001 -p189 -g1 -(g29 -g3 -Ntp190 -Rp191 -(dp192 -g8 -V001 -p193 -sg23 -VVP_ISA_F008_S003_I001 -p194 -sg35 -Vc.addi16sp nzimm[9:4]\u000ax[2] = x[2] + sext(nzimm[9:4])\u000aExpands to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\u000ard is calculated using signed arithmetic. -p195 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p196 -sg39 -VOutput result:\u000a\u000aAll bits of x2 are toggled -p197 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp198 -sg15 -(lp199 -sg52 -(lp200 -sg13 -(dp201 -g55 -I0 -ssbtp202 -asg71 -(lp203 -sg52 -(lp204 -sg13 -(dp205 -sbtp206 -a(V004_C.ADDI4SPN -p207 -g1 -(g18 -g3 -Ntp208 -Rp209 -(dp210 -g22 -I3 -sg8 -g207 -sg23 -VVP_IP008_P004 -p211 -sg25 -(dp212 -sg12 -I4 -sg15 -(lp213 -(V000 -p214 -g1 -(g29 -g3 -Ntp215 -Rp216 -(dp217 -g8 -V000 -p218 -sg23 -VVP_ISA_F008_S004_I000 -p219 -sg35 -Vc.addi4spn rd', nzuimm[9:2]\u000ax[8+rd'] = x[2] + nzuimm[9:2]\u000aExpands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\u000ard is calculated using signed arithmetic. -p220 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p221 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p222 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp223 -sg15 -(lp224 -sg52 -(lp225 -sg13 -(dp226 -g55 -I0 -ssbtp227 -a(V001 -p228 -g1 -(g29 -g3 -Ntp229 -Rp230 -(dp231 -g8 -V001 -p232 -sg23 -VVP_ISA_F008_S004_I001 -p233 -sg35 -Vc.addi4spn rd', nzuimm[9:2]\u000ax[8+rd'] = x[2] + nzuimm[9:2]\u000aExpands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\u000ard is calculated using signed arithmetic. -p234 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p235 -sg39 -VInput operands:\u000a\u000aAll bits of nzuimm[9:2] are toggled\u000aAll bits of x2 before instruction execution are toggled -p236 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp237 -sg15 -(lp238 -sg52 -(lp239 -sg13 -(dp240 -g55 -I0 -ssbtp241 -a(V002 -p242 -g1 -(g29 -g3 -Ntp243 -Rp244 -(dp245 -g8 -V002 -p246 -sg23 -VVP_ISA_F008_S004_I002 -p247 -sg35 -Vc.addi4spn rd', nzuimm[9:2]\u000ax[8+rd'] = x[2] + nzuimm[9:2]\u000aExpands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\u000ard is calculated using signed arithmetic. -p248 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p249 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p250 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp251 -sg15 -(lp252 -sg52 -(lp253 -sg13 -(dp254 -g55 -I0 -ssbtp255 -asg71 -(lp256 -sg52 -(lp257 -sg13 -(dp258 -sbtp259 -a(V005_C.SLLI -p260 -g1 -(g18 -g3 -Ntp261 -Rp262 -(dp263 -g22 -I3 -sg8 -g260 -sg23 -VVP_IP008_P005 -p264 -sg25 -(dp265 -sg12 -I5 -sg15 -(lp266 -(V000 -p267 -g1 -(g29 -g3 -Ntp268 -Rp269 -(dp270 -g8 -V000 -p271 -sg23 -VVP_ISA_F008_S005_I000 -p272 -sg35 -Vc.slli rd, uimm[5:0]\u000ax[rd] = x[rd] << uimm[5:0]\u000aExpands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0. -p273 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p274 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p275 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp276 -sg15 -(lp277 -sg52 -(lp278 -sg13 -(dp279 -g55 -I0 -ssbtp280 -a(V001 -p281 -g1 -(g29 -g3 -Ntp282 -Rp283 -(dp284 -g8 -V001 -p285 -sg23 -VVP_ISA_F008_S005_I001 -p286 -sg35 -Vc.slli rd, uimm[5:0]\u000ax[rd] = x[rd] << uimm[5:0]\u000aExpands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0. -p287 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p288 -sg39 -VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000aAll bits of rd before instruction execution are toggled -p289 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp290 -sg15 -(lp291 -sg52 -(lp292 -sg13 -(dp293 -g55 -I0 -ssbtp294 -a(V002 -p295 -g1 -(g29 -g3 -Ntp296 -Rp297 -(dp298 -g8 -V002 -p299 -sg23 -VVP_ISA_F008_S005_I002 -p300 -sg35 -Vc.slli rd, uimm[5:0]\u000ax[rd] = x[rd] << uimm[5:0]\u000aExpands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0. -p301 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p302 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p303 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp304 -sg15 -(lp305 -sg52 -(lp306 -sg13 -(dp307 -g55 -I0 -ssbtp308 -asg71 -(lp309 -sg52 -(lp310 -sg13 -(dp311 -sbtp312 -a(V006_C.SRLI -p313 -g1 -(g18 -g3 -Ntp314 -Rp315 -(dp316 -g22 -I3 -sg8 -g313 -sg23 -VVP_IP008_P006 -p317 -sg25 -(dp318 -sg12 -I6 -sg15 -(lp319 -(V000 -p320 -g1 -(g29 -g3 -Ntp321 -Rp322 -(dp323 -g8 -V000 -p324 -sg23 -VVP_ISA_F008_S006_I000 -p325 -sg35 -Vc.srli rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >>u uimm[5:0]\u000aExpands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, -p326 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p327 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p328 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp329 -sg15 -(lp330 -sg52 -(lp331 -sg13 -(dp332 -g55 -I0 -ssbtp333 -a(V001 -p334 -g1 -(g29 -g3 -Ntp335 -Rp336 -(dp337 -g8 -V001 -p338 -sg23 -VVP_ISA_F008_S006_I001 -p339 -sg35 -Vc.srli rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >>u uimm[5:0]\u000aExpands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, -p340 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p341 -sg39 -VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000aAll bits of rd before instruction execution are toggled -p342 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp343 -sg15 -(lp344 -sg52 -(lp345 -sg13 -(dp346 -g55 -I0 -ssbtp347 -a(V002 -p348 -g1 -(g29 -g3 -Ntp349 -Rp350 -(dp351 -g8 -V002 -p352 -sg23 -VVP_ISA_F008_S006_I002 -p353 -sg35 -Vc.srli rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >>u uimm[5:0]\u000aExpands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, -p354 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p355 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p356 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp357 -sg15 -(lp358 -sg52 -(lp359 -sg13 -(dp360 -g55 -I0 -ssbtp361 -asg71 -(lp362 -sg52 -(lp363 -sg13 -(dp364 -sbtp365 -a(V007_C.SRAI -p366 -g1 -(g18 -g3 -Ntp367 -Rp368 -(dp369 -g22 -I3 -sg8 -g366 -sg23 -VVP_IP008_P007 -p370 -sg25 -(dp371 -sg12 -I7 -sg15 -(lp372 -(V000 -p373 -g1 -(g29 -g3 -Ntp374 -Rp375 -(dp376 -g8 -V000 -p377 -sg23 -VVP_ISA_F008_S007_I000 -p378 -sg35 -Vc.srai rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >> uimm[5:0]\u000aExpands to srai rd', rd', uimm[5:0]. -p379 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p380 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p381 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp382 -sg15 -(lp383 -sg52 -(lp384 -sg13 -(dp385 -g55 -I0 -ssbtp386 -a(V001 -p387 -g1 -(g29 -g3 -Ntp388 -Rp389 -(dp390 -g8 -V001 -p391 -sg23 -VVP_ISA_F008_S007_I001 -p392 -sg35 -Vc.srai rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >> uimm[5:0]\u000aExpands to srai rd', rd', uimm[5:0]. -p393 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p394 -sg39 -VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000a+ve, -ve and zero values of rd` are used\u000aAll bits of rd` before instruction execution are toggled -p395 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp396 -sg15 -(lp397 -sg52 -(lp398 -sg13 -(dp399 -g55 -I0 -ssbtp400 -a(V002 -p401 -g1 -(g29 -g3 -Ntp402 -Rp403 -(dp404 -g8 -V002 -p405 -sg23 -VVP_ISA_F008_S007_I002 -p406 -sg35 -Vc.srai rd', uimm[5:0]\u000ax[8+rd'] = x[8+rd'] >> uimm[5:0]\u000aExpands to srai rd', rd', uimm[5:0]. -p407 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p408 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p409 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp410 -sg15 -(lp411 -sg52 -(lp412 -sg13 -(dp413 -g55 -I0 -ssbtp414 -asg71 -(lp415 -sg52 -(lp416 -sg13 -(dp417 -sbtp418 -a(V008_C.ANDI -p419 -g1 -(g18 -g3 -Ntp420 -Rp421 -(dp422 -g22 -I3 -sg8 -g419 -sg23 -VVP_IP008_P008 -p423 -sg25 -(dp424 -sg12 -I8 -sg15 -(lp425 -(V000 -p426 -g1 -(g29 -g3 -Ntp427 -Rp428 -(dp429 -g8 -V000 -p430 -sg23 -VVP_ISA_F008_S008_I000 -p431 -sg35 -Vc.andi rd', imm[5:0]\u000ax[8+rd'] = x[8+rd'] & sext(imm[5:0])\u000aExpands to andi rd', rd', imm[5:0].\u000aimm treated as signed number -p432 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p433 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p434 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp435 -sg15 -(lp436 -sg52 -(lp437 -sg13 -(dp438 -g55 -I0 -ssbtp439 -a(V001 -p440 -g1 -(g29 -g3 -Ntp441 -Rp442 -(dp443 -g8 -V001 -p444 -sg23 -VVP_ISA_F008_S008_I001 -p445 -sg35 -Vc.andi rd', imm[5:0]\u000ax[8+rd'] = x[8+rd'] & sext(imm[5:0])\u000aExpands to andi rd', rd', imm[5:0].\u000aimm treated as signed number -p446 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p447 -sg39 -VInput operands:\u000a\u000aAll shift amounts from [0:31] are used\u000a+ve, -ve and zero values of imm are used\u000aAll bits of rd` before instruction execution are toggled -p448 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp449 -sg15 -(lp450 -sg52 -(lp451 -sg13 -(dp452 -g55 -I0 -ssbtp453 -a(V002 -p454 -g1 -(g29 -g3 -Ntp455 -Rp456 -(dp457 -g8 -V002 -p458 -sg23 -VVP_ISA_F008_S008_I002 -p459 -sg35 -Vc.andi rd', imm[5:0]\u000ax[8+rd'] = x[8+rd'] & sext(imm[5:0])\u000aExpands to andi rd', rd', imm[5:0].\u000aimm treated as signed number -p460 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p461 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p462 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp463 -sg15 -(lp464 -sg52 -(lp465 -sg13 -(dp466 -g55 -I0 -ssbtp467 -asg71 -(lp468 -sg52 -(lp469 -sg13 -(dp470 -sbtp471 -a(V009_C.MV -p472 -g1 -(g18 -g3 -Ntp473 -Rp474 -(dp475 -g22 -I3 -sg8 -g472 -sg23 -VVP_IP008_P009 -p476 -sg25 -(dp477 -sg12 -I9 -sg15 -(lp478 -(V000 -p479 -g1 -(g29 -g3 -Ntp480 -Rp481 -(dp482 -g8 -V000 -p483 -sg23 -VVP_ISA_F008_S009_I000 -p484 -sg35 -Vc.mv rd, rs2\u000ax[rd] = x[rs2]\u000aExpands to add rd, x0, rs2\u000aInvalid when rs2=x0 or rd=x0. -p485 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p486 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used.\u000aAll possible register combinations where rs2 == rd are used -p487 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp488 -sg15 -(lp489 -sg52 -(lp490 -sg13 -(dp491 -g55 -I0 -ssbtp492 -a(V001 -p493 -g1 -(g29 -g3 -Ntp494 -Rp495 -(dp496 -g8 -V001 -p497 -sg23 -VVP_ISA_F008_S009_I001 -p498 -sg35 -Vc.mv rd, rs2\u000ax[rd] = x[rs2]\u000aExpands to add rd, x0, rs2\u000aInvalid when rs2=x0 or rd=x0. -p499 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p500 -sg39 -VInput operands:\u000a\u000aAll bits of rs2 are toggled -p501 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp502 -sg15 -(lp503 -sg52 -(lp504 -sg13 -(dp505 -g55 -I0 -ssbtp506 -a(V002 -p507 -g1 -(g29 -g3 -Ntp508 -Rp509 -(dp510 -g8 -V002 -p511 -sg23 -VVP_ISA_F008_S009_I002 -p512 -sg35 -Vc.mv rd, rs2\u000ax[rd] = x[rs2]\u000aExpands to add rd, x0, rs2\u000aInvalid when rs2=x0 or rd=x0. -p513 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p514 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled -p515 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp516 -sg15 -(lp517 -sg52 -(lp518 -sg13 -(dp519 -g55 -I0 -ssbtp520 -asg71 -(lp521 -sg52 -(lp522 -sg13 -(dp523 -sbtp524 -a(V010_C.ADD -p525 -g1 -(g18 -g3 -Ntp526 -Rp527 -(dp528 -g22 -I3 -sg8 -g525 -sg23 -VVP_IP008_P010 -p529 -sg25 -(dp530 -sg12 -I10 -sg15 -(lp531 -(V000 -p532 -g1 -(g29 -g3 -Ntp533 -Rp534 -(dp535 -g8 -V000 -p536 -sg23 -VVP_ISA_F008_S010_I000 -p537 -sg35 -Vc.add rd, rs2\u000ax[rd] = x[rd] + x[rs2]\u000aExpands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0.\u000aArithmetic overflow is lost and ignored -p538 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p539 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p540 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp541 -sg15 -(lp542 -sg52 -(lp543 -sg13 -(dp544 -g55 -I0 -ssbtp545 -a(V001 -p546 -g1 -(g29 -g3 -Ntp547 -Rp548 -(dp549 -g8 -V001 -p550 -sg23 -VVP_ISA_F008_S010_I001 -p551 -sg35 -Vc.add rd, rs2\u000ax[rd] = x[rd] + x[rs2]\u000aExpands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0.\u000aArithmetic overflow is lost and ignored -p552 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p553 -sg39 -VInput operands:\u000a\u000a+ve,-ve and zero values of rs2 are used\u000a+ve,-ve, and zero values of rdrs1 are used\u000aAll bits of rs2 are toggled\u000aAll bits of rd before instruction execution are toggled -p554 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp555 -sg15 -(lp556 -sg52 -(lp557 -sg13 -(dp558 -g55 -I0 -ssbtp559 -a(V002 -p560 -g1 -(g29 -g3 -Ntp561 -Rp562 -(dp563 -g8 -V002 -p564 -sg23 -VVP_ISA_F008_S010_I002 -p565 -sg35 -Vc.add rd, rs2\u000ax[rd] = x[rd] + x[rs2]\u000aExpands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0.\u000aArithmetic overflow is lost and ignored -p566 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p567 -sg39 -VOutput result:\u000a\u000aAll bits of rd are toggled\u000a+ve,-ve and zero values of rd are used -p568 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp569 -sg15 -(lp570 -sg52 -(lp571 -sg13 -(dp572 -g55 -I0 -ssbtp573 -asg71 -(lp574 -sg52 -(lp575 -sg13 -(dp576 -sbtp577 -a(V011_C.AND -p578 -g1 -(g18 -g3 -Ntp579 -Rp580 -(dp581 -g22 -I3 -sg8 -g578 -sg23 -VVP_IP008_P011 -p582 -sg25 -(dp583 -sg12 -I11 -sg15 -(lp584 -(V000 -p585 -g1 -(g29 -g3 -Ntp586 -Rp587 -(dp588 -g8 -V000 -p589 -sg23 -VVP_ISA_F008_S011_I000 -p590 -sg35 -Vc.and rd', rs2'\u000ax[8+rd'] = x[8+rd'] & x[8+rs2']\u000aExpands to and rd', rd', rs2'. -p591 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p592 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p593 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp594 -sg15 -(lp595 -sg52 -(lp596 -sg13 -(dp597 -g55 -I0 -ssbtp598 -a(V001 -p599 -g1 -(g29 -g3 -Ntp600 -Rp601 -(dp602 -g8 -V001 -p603 -sg23 -VVP_ISA_F008_S011_I001 -p604 -sg35 -Vc.and rd', rs2'\u000ax[8+rd'] = x[8+rd'] & x[8+rs2']\u000aExpands to and rd', rd', rs2'. -p605 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p606 -sg39 -VInput operands:\u000a\u000aNon-zero and zero values of rs2` are used\u000aNon-zero and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled -p607 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp608 -sg15 -(lp609 -sg52 -(lp610 -sg13 -(dp611 -g55 -I0 -ssbtp612 -a(V002 -p613 -g1 -(g29 -g3 -Ntp614 -Rp615 -(dp616 -g8 -V002 -p617 -sg23 -VVP_ISA_F008_S011_I002 -p618 -sg35 -Vc.and rd', rs2'\u000ax[8+rd'] = x[8+rd'] & x[8+rs2']\u000aExpands to and rd', rd', rs2'. -p619 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p620 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p621 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp622 -sg15 -(lp623 -sg52 -(lp624 -sg13 -(dp625 -g55 -I0 -ssbtp626 -asg71 -(lp627 -sg52 -(lp628 -sg13 -(dp629 -sbtp630 -a(V012_C.OR -p631 -g1 -(g18 -g3 -Ntp632 -Rp633 -(dp634 -g22 -I3 -sg8 -g631 -sg23 -VVP_IP008_P012 -p635 -sg25 -(dp636 -sg12 -I12 -sg15 -(lp637 -(V000 -p638 -g1 -(g29 -g3 -Ntp639 -Rp640 -(dp641 -g8 -V000 -p642 -sg23 -VVP_ISA_F008_S012_I000 -p643 -sg35 -Vc.or rd', rs2'\u000ax[8+rd'] = x[8+rd'] | x[8+rs2']\u000aExpands to or rd', rd', rs2'. -p644 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p645 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p646 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp647 -sg15 -(lp648 -sg52 -(lp649 -sg13 -(dp650 -g55 -I0 -ssbtp651 -a(V001 -p652 -g1 -(g29 -g3 -Ntp653 -Rp654 -(dp655 -g8 -V001 -p656 -sg23 -VVP_ISA_F008_S012_I001 -p657 -sg35 -Vc.or rd', rs2'\u000ax[8+rd'] = x[8+rd'] | x[8+rs2']\u000aExpands to or rd', rd', rs2'. -p658 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p659 -sg39 -VInput operands:\u000a\u000aNon-zero and zero values of rs2` are used\u000aNon-zero and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled -p660 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp661 -sg15 -(lp662 -sg52 -(lp663 -sg13 -(dp664 -g55 -I0 -ssbtp665 -a(V002 -p666 -g1 -(g29 -g3 -Ntp667 -Rp668 -(dp669 -g8 -V002 -p670 -sg23 -VVP_ISA_F008_S012_I002 -p671 -sg35 -Vc.or rd', rs2'\u000ax[8+rd'] = x[8+rd'] | x[8+rs2']\u000aExpands to or rd', rd', rs2'. -p672 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p673 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p674 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp675 -sg15 -(lp676 -sg52 -(lp677 -sg13 -(dp678 -g55 -I0 -ssbtp679 -asg71 -(lp680 -sg52 -(lp681 -sg13 -(dp682 -sbtp683 -a(V013_C.XOR -p684 -g1 -(g18 -g3 -Ntp685 -Rp686 -(dp687 -g22 -I3 -sg8 -g684 -sg23 -VVP_IP008_P013 -p688 -sg25 -(dp689 -sg12 -I13 -sg15 -(lp690 -(V000 -p691 -g1 -(g29 -g3 -Ntp692 -Rp693 -(dp694 -g8 -V000 -p695 -sg23 -VVP_ISA_F008_S013_I000 -p696 -sg35 -Vc.xor rd', rs2'\u000ax[8+rd'] = x[8+rd'] ^ x[8+rs2']\u000aExpands to xor rd', rd', rs2'. -p697 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p698 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p699 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp700 -sg15 -(lp701 -sg52 -(lp702 -sg13 -(dp703 -g55 -I0 -ssbtp704 -a(V001 -p705 -g1 -(g29 -g3 -Ntp706 -Rp707 -(dp708 -g8 -V001 -p709 -sg23 -VVP_ISA_F008_S013_I001 -p710 -sg35 -Vc.xor rd', rs2'\u000ax[8+rd'] = x[8+rd'] ^ x[8+rs2']\u000aExpands to xor rd', rd', rs2'. -p711 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p712 -sg39 -VInput operands:\u000a\u000aNon-zero and zero values of rs2` are used\u000aNon-zero and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled -p713 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp714 -sg15 -(lp715 -sg52 -(lp716 -sg13 -(dp717 -g55 -I0 -ssbtp718 -a(V002 -p719 -g1 -(g29 -g3 -Ntp720 -Rp721 -(dp722 -g8 -V002 -p723 -sg23 -VVP_ISA_F008_S013_I002 -p724 -sg35 -Vc.xor rd', rs2'\u000ax[8+rd'] = x[8+rd'] ^ x[8+rs2']\u000aExpands to xor rd', rd', rs2'. -p725 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p726 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p727 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp728 -sg15 -(lp729 -sg52 -(lp730 -sg13 -(dp731 -g55 -I0 -ssbtp732 -asg71 -(lp733 -sg52 -(lp734 -sg13 -(dp735 -sbtp736 -a(V014_C.SUB -p737 -g1 -(g18 -g3 -Ntp738 -Rp739 -(dp740 -g22 -I3 -sg8 -g737 -sg23 -VVP_IP008_P014 -p741 -sg25 -(dp742 -sg12 -I14 -sg15 -(lp743 -(V000 -p744 -g1 -(g29 -g3 -Ntp745 -Rp746 -(dp747 -g8 -V000 -p748 -sg23 -VVP_ISA_F008_S014_I000 -p749 -sg35 -Vc.sub rd', rs2'\u000ax[8+rd'] = x[8+rd'] - x[8+rs2']\u000aExpands to sub rd', rd', rs2'. Arithmetic underflow is ignored -p750 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p751 -sg39 -VRegister operands:\u000a\u000aAll possible rd` registers are used. -p752 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp753 -sg15 -(lp754 -sg52 -(lp755 -sg13 -(dp756 -g55 -I0 -ssbtp757 -a(V001 -p758 -g1 -(g29 -g3 -Ntp759 -Rp760 -(dp761 -g8 -V001 -p762 -sg23 -VVP_ISA_F008_S014_I001 -p763 -sg35 -Vc.sub rd', rs2'\u000ax[8+rd'] = x[8+rd'] - x[8+rs2']\u000aExpands to sub rd', rd', rs2'. Arithmetic underflow is ignored -p764 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p765 -sg39 -VInput operands:\u000a\u000a+ve,-ve and zero values of rs2` are used\u000a+ve, -ve, and zero values of rd` are used\u000aAll bits of rs2` are toggled\u000aAll bits of rd` before instruction execution are toggled -p766 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp767 -sg15 -(lp768 -sg52 -(lp769 -sg13 -(dp770 -g55 -I0 -ssbtp771 -a(V002 -p772 -g1 -(g29 -g3 -Ntp773 -Rp774 -(dp775 -g8 -V002 -p776 -sg23 -VVP_ISA_F008_S014_I002 -p777 -sg35 -Vc.sub rd', rs2'\u000ax[8+rd'] = x[8+rd'] - x[8+rs2']\u000aExpands to sub rd', rd', rs2'. Arithmetic underflow is ignored -p778 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p779 -sg39 -VOutput result:\u000a\u000aAll bits of rd` are toggled -p780 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp781 -sg15 -(lp782 -sg52 -(lp783 -sg13 -(dp784 -g55 -I0 -ssbtp785 -asg71 -(lp786 -sg52 -(lp787 -sg13 -(dp788 -sbtp789 -a(V015_C.EBREAK -p790 -g1 -(g18 -g3 -Ntp791 -Rp792 -(dp793 -g22 -I1 -sg8 -g790 -sg23 -VVP_IP008_P015 -p794 -sg25 -(dp795 -sg12 -I15 -sg15 -(lp796 -(V000 -p797 -g1 -(g29 -g3 -Ntp798 -Rp799 -(dp800 -g8 -V000 -p801 -sg23 -VVP_ISA_F008_S015_I000 -p802 -sg35 -Vc.ebreak\u000aRaiseException(Breakpoint)\u000aExpands to ebreak. -p803 -sg37 -VUnprivileged ISA\u000aChapter 16.5 -p804 -sg39 -VInstruction executed -p805 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp806 -sg15 -(lp807 -sg52 -(lp808 -sg13 -(dp809 -g55 -I0 -ssbtp810 -asg71 -(lp811 -sg52 -(lp812 -sg13 -(dp813 -sbtp814 -asVrfu_list_0 -p815 -(lp816 -sg71 -(lp817 -sVvptool_gitrev -p818 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p819 -sVio_fmt_gitrev -p820 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p821 -sVconfig_gitrev -p822 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p823 -sVymlcfg_gitrev -p824 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p825 -sbtp826 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml new file mode 100644 index 0000000000..21eb1d64e9 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml @@ -0,0 +1,868 @@ +!Feature +next_elt_id: 16 +name: RV32C Integer Computational Instructions +id: 10 +display_order: 10 +subfeatures: !!omap +- 000_C.LI: !Subfeature + name: 000_C.LI + tag: VP_IP008_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S000_I000 + description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\ + \ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of imm[5:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S000_I001 + description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\ + \ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_C.LUI: !Subfeature + name: 001_C.LUI + tag: VP_IP008_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S001_I000 + description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\ + \ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\ + \ calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of imm[17:12] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S001_I001 + description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\ + \ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\ + \ calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd[31:12] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_C.ADDI: !Subfeature + name: 002_C.ADDI + tag: VP_IP008_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S002_I000 + description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ + \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ + \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S002_I001 + description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ + \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ + \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll inputs bits of rd before instruction\ + \ execution are toggled\nAll bits of nzimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S002_I002 + description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ + \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ + \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_C.ADDI16SP: !Subfeature + name: 003_C.ADDI16SP + tag: VP_IP008_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S003_I000 + description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\ + \ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\ + \ signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\n+ve and -ve values of nzimm are used\nAll\ + \ bits of nzimm[9:4] are toggled\nAll bits of x2 before instruction execution\ + \ are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S003_I001 + description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\ + \ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\ + \ signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of x2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_C.ADDI4SPN: !Subfeature + name: 004_C.ADDI4SPN + tag: VP_IP008_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S004_I000 + description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ + \ using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S004_I001 + description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ + \ using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of nzuimm[9:2] are toggled\nAll\ + \ bits of x2 before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S004_I002 + description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ + \ using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_C.SLLI: !Subfeature + name: 005_C.SLLI + tag: VP_IP008_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S005_I000 + description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ + \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S005_I001 + description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ + \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + All bits of rd before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S005_I002 + description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ + \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 006_C.SRLI: !Subfeature + name: 006_C.SRLI + tag: VP_IP008_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S006_I000 + description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ + \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S006_I001 + description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ + \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + All bits of rd before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S006_I002 + description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ + \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 007_C.SRAI: !Subfeature + name: 007_C.SRAI + tag: VP_IP008_P007 + next_elt_id: 3 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S007_I000 + description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ + \ to srai rd', rd', uimm[5:0]." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S007_I001 + description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ + \ to srai rd', rd', uimm[5:0]." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + +ve, -ve and zero values of rd` are used\nAll bits of rd` before instruction\ + \ execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S007_I002 + description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ + \ to srai rd', rd', uimm[5:0]." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 008_C.ANDI: !Subfeature + name: 008_C.ANDI + tag: VP_IP008_P008 + next_elt_id: 3 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S008_I000 + description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ + Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S008_I001 + description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ + Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + +ve, -ve and zero values of imm are used\nAll bits of rd` before instruction\ + \ execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S008_I002 + description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ + Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 009_C.MV: !Subfeature + name: 009_C.MV + tag: VP_IP008_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S009_I000 + description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ + \ when rs2=x0 or rd=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used.\n\ + All possible register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S009_I001 + description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ + \ when rs2=x0 or rd=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S009_I002 + description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ + \ when rs2=x0 or rd=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 010_C.ADD: !Subfeature + name: 010_C.ADD + tag: VP_IP008_P010 + next_elt_id: 3 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S010_I000 + description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ + \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S010_I001 + description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ + \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\n+ve,-ve and zero values of rs2 are used\n\ + +ve,-ve, and zero values of rdrs1 are used\nAll bits of rs2 are toggled\n\ + All bits of rd before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S010_I002 + description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ + \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd are toggled\n+ve,-ve and zero\ + \ values of rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 011_C.AND: !Subfeature + name: 011_C.AND + tag: VP_IP008_P011 + next_elt_id: 3 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S011_I000 + description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ + \ and rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S011_I001 + description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ + \ and rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\ + Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S011_I002 + description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ + \ and rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 012_C.OR: !Subfeature + name: 012_C.OR + tag: VP_IP008_P012 + next_elt_id: 3 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S012_I000 + description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ + \ or rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S012_I001 + description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ + \ or rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\ + Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S012_I002 + description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ + \ or rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 013_C.XOR: !Subfeature + name: 013_C.XOR + tag: VP_IP008_P013 + next_elt_id: 3 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S013_I000 + description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ + \ xor rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S013_I001 + description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ + \ xor rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\ + Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S013_I002 + description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ + \ xor rd', rd', rs2'." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 014_C.SUB: !Subfeature + name: 014_C.SUB + tag: VP_IP008_P014 + next_elt_id: 3 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S014_I000 + description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ + \ sub rd', rd', rs2'. Arithmetic underflow is ignored" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F008_S014_I001 + description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ + \ sub rd', rd', rs2'. Arithmetic underflow is ignored" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\n+ve,-ve and zero values of rs2` are used\n\ + +ve, -ve, and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F008_S014_I002 + description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ + \ sub rd', rd', rs2'. Arithmetic underflow is ignored" + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 015_C.EBREAK: !Subfeature + name: 015_C.EBREAK + tag: VP_IP008_P015 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F008_S015_I000 + description: "c.ebreak\nRaiseException(Breakpoint)\nExpands to ebreak." + reqt_doc: "Unprivileged ISA\nChapter 16.5" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck deleted file mode 100644 index e8ad3e4119..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.pck +++ /dev/null @@ -1,920 +0,0 @@ -(VRV32C Control Transfer Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I6 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I11 -sVwid_order -p12 -I11 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_C.J -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP010_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F010_S000_I000 -p34 -sVdescription -p35 -Vc.j imm[11:1]\u000apc += sext(imm)\u000apc is calculated using signed arithmetic\u000aExpands to jal x0, imm[11:1]. -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 16.4 -p38 -sVverif_goals -p39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -asVrfu_list_1 -p57 -(lp58 -sg52 -(lp59 -sg13 -(dp60 -sbtp61 -a(V001_C.JAL -p62 -g1 -(g18 -g3 -Ntp63 -Rp64 -(dp65 -g22 -I2 -sg8 -g62 -sg23 -VVP_IP010_P001 -p66 -sg25 -(dp67 -sg12 -I1 -sg15 -(lp68 -(V000 -p69 -g1 -(g29 -g3 -Ntp70 -Rp71 -(dp72 -g8 -V000 -p73 -sg23 -VVP_ISA_F010_S001_I000 -p74 -sg35 -Vc.jal imm[11:1]\u000ax[1] = pc+2; pc += sext(imm)\u000apc is calculated using signed arithmetic. -p75 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p76 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled -p77 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp78 -sg15 -(lp79 -sg52 -(lp80 -sg13 -(dp81 -g55 -I0 -ssbtp82 -a(V001 -p83 -g1 -(g29 -g3 -Ntp84 -Rp85 -(dp86 -g8 -V001 -p87 -sg23 -VVP_ISA_F010_S001_I001 -p88 -sg35 -Vc.jal imm[11:1]\u000ax[1] = pc+2; pc += sext(imm)\u000apc is calculated using signed arithmetic. -p89 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p90 -sg39 -VOutput result:\u000a\u000aAll bits of x1 are toggled -p91 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp92 -sg15 -(lp93 -sg52 -(lp94 -sg13 -(dp95 -g55 -I0 -ssbtp96 -asg57 -(lp97 -sg52 -(lp98 -sg13 -(dp99 -sbtp100 -a(V002_C.JR -p101 -g1 -(g18 -g3 -Ntp102 -Rp103 -(dp104 -g22 -I2 -sg8 -g101 -sg23 -VVP_IP010_P002 -p105 -sg25 -(dp106 -sg12 -I2 -sg15 -(lp107 -(V000 -p108 -g1 -(g29 -g3 -Ntp109 -Rp110 -(dp111 -g8 -V000 -p112 -sg23 -VVP_ISA_F010_S002_I000 -p113 -sg35 -Vc.jr rs1\u000apc = x[rs1]\u000aExpands to jalr x0, 0(rs1). \u000aInvalid when rs1=x0. -p114 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p115 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used. -p116 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp117 -sg15 -(lp118 -sg52 -(lp119 -sg13 -(dp120 -g55 -I0 -ssbtp121 -a(V001 -p122 -g1 -(g29 -g3 -Ntp123 -Rp124 -(dp125 -g8 -V001 -p126 -sg23 -VVP_ISA_F010_S002_I001 -p127 -sg35 -Vc.jr rs1\u000apc = x[rs1]\u000aExpands to jalr x0, 0(rs1). \u000aInvalid when rs1=x0. -p128 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p129 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled -p130 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp131 -sg15 -(lp132 -sg52 -(lp133 -sg13 -(dp134 -g55 -I0 -ssbtp135 -asg57 -(lp136 -sg52 -(lp137 -sg13 -(dp138 -sbtp139 -a(V003_C.JALR -p140 -g1 -(g18 -g3 -Ntp141 -Rp142 -(dp143 -g22 -I3 -sg8 -g140 -sg23 -VVP_IP010_P003 -p144 -sg25 -(dp145 -sg12 -I3 -sg15 -(lp146 -(V000 -p147 -g1 -(g29 -g3 -Ntp148 -Rp149 -(dp150 -g8 -V000 -p151 -sg23 -VVP_ISA_F010_S003_I000 -p152 -sg35 -Vc.jalr rs1\u000at = pc + 2; pc = x[rs1]; x[1] = t\u000aExpands to jalr x1, 0(rs1). \u000aInvalid when rs1=x0. -p153 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p154 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used. -p155 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp156 -sg15 -(lp157 -sg52 -(lp158 -sg13 -(dp159 -g55 -I0 -ssbtp160 -a(V001 -p161 -g1 -(g29 -g3 -Ntp162 -Rp163 -(dp164 -g8 -V001 -p165 -sg23 -VVP_ISA_F010_S003_I001 -p166 -sg35 -Vc.jalr rs1\u000at = pc + 2; pc = x[rs1]; x[1] = t\u000aExpands to jalr x1, 0(rs1). \u000aInvalid when rs1=x0. -p167 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p168 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled -p169 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp170 -sg15 -(lp171 -sg52 -(lp172 -sg13 -(dp173 -g55 -I0 -ssbtp174 -a(V002 -p175 -g1 -(g29 -g3 -Ntp176 -Rp177 -(dp178 -g8 -V002 -p179 -sg23 -VVP_ISA_F010_S003_I002 -p180 -sg35 -Vc.jalr rs1\u000at = pc + 2; pc = x[rs1]; x[1] = t\u000aExpands to jalr x1, 0(rs1). \u000aInvalid when rs1=x0. -p181 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p182 -sg39 -VOutput result:\u000a\u000aAll bits of x1 are toggled -p183 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp184 -sg15 -(lp185 -sg52 -(lp186 -sg13 -(dp187 -g55 -I0 -ssbtp188 -asg57 -(lp189 -sg52 -(lp190 -sg13 -(dp191 -sbtp192 -a(V004_C.BEQZ -p193 -g1 -(g18 -g3 -Ntp194 -Rp195 -(dp196 -g22 -I3 -sg8 -g193 -sg23 -VVP_IP010_P004 -p197 -sg25 -(dp198 -sg12 -I4 -sg15 -(lp199 -(V000 -p200 -g1 -(g29 -g3 -Ntp201 -Rp202 -(dp203 -g8 -V000 -p204 -sg23 -VVP_ISA_F010_S004_I000 -p205 -sg35 -Vc.beqz rs1', imm[8:1]\u000aif (x[8+rs1'] == 0) pc += sext(imm)\u000aExpands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p206 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p207 -sg39 -VRegister operands:\u000a\u000aAll possible rs1` registers are used. -p208 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp209 -sg15 -(lp210 -sg52 -(lp211 -sg13 -(dp212 -g55 -I0 -ssbtp213 -a(V001 -p214 -g1 -(g29 -g3 -Ntp215 -Rp216 -(dp217 -g8 -V001 -p218 -sg23 -VVP_ISA_F010_S004_I001 -p219 -sg35 -Vc.beqz rs1', imm[8:1]\u000aif (x[8+rs1'] == 0) pc += sext(imm)\u000aExpands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p220 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p221 -sg39 -VInput operands:\u000a\u000aAll bits of rs1` are toggled -p222 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp223 -sg15 -(lp224 -sg52 -(lp225 -sg13 -(dp226 -g55 -I0 -ssbtp227 -a(V002 -p228 -g1 -(g29 -g3 -Ntp229 -Rp230 -(dp231 -g8 -V002 -p232 -sg23 -VVP_ISA_F010_S004_I002 -p233 -sg35 -Vc.beqz rs1', imm[8:1]\u000aif (x[8+rs1'] == 0) pc += sext(imm)\u000aExpands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p234 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p235 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p236 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp237 -sg15 -(lp238 -sg52 -(lp239 -sg13 -(dp240 -g55 -I0 -ssbtp241 -asg57 -(lp242 -sg52 -(lp243 -sg13 -(dp244 -sbtp245 -a(V005_C.BNEZ -p246 -g1 -(g18 -g3 -Ntp247 -Rp248 -(dp249 -g22 -I3 -sg8 -g246 -sg23 -VVP_IP010_P005 -p250 -sg25 -(dp251 -sg12 -I5 -sg15 -(lp252 -(V000 -p253 -g1 -(g29 -g3 -Ntp254 -Rp255 -(dp256 -g8 -V000 -p257 -sg23 -VVP_ISA_F010_S005_I000 -p258 -sg35 -Vc.bnez rs1', imm[8:1]\u000aif (x[8+rs1'] \u2260 0) pc += sext(imm)\u000aExpands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p259 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p260 -sg39 -VRegister operands:\u000a\u000aAll possible rs1` registers are used. -p261 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp262 -sg15 -(lp263 -sg52 -(lp264 -sg13 -(dp265 -g55 -I0 -ssbtp266 -a(V001 -p267 -g1 -(g29 -g3 -Ntp268 -Rp269 -(dp270 -g8 -V001 -p271 -sg23 -VVP_ISA_F010_S005_I001 -p272 -sg35 -Vc.bnez rs1', imm[8:1]\u000aif (x[8+rs1'] \u2260 0) pc += sext(imm)\u000aExpands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p273 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p274 -sg39 -VInput operands:\u000a\u000aAll bits of rs1 are toggled -p275 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp276 -sg15 -(lp277 -sg52 -(lp278 -sg13 -(dp279 -g55 -I0 -ssbtp280 -a(V002 -p281 -g1 -(g29 -g3 -Ntp282 -Rp283 -(dp284 -g8 -V002 -p285 -sg23 -VVP_ISA_F010_S005_I002 -p286 -sg35 -Vc.bnez rs1', imm[8:1]\u000aif (x[8+rs1'] \u2260 0) pc += sext(imm)\u000aExpands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. -p287 -sg37 -VUnprivileged ISA\u000aChapter 16.4 -p288 -sg39 -VOutput result:\u000a\u000aBranch taken or not-taken -p289 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp290 -sg15 -(lp291 -sg52 -(lp292 -sg13 -(dp293 -g55 -I0 -ssbtp294 -asg57 -(lp295 -sg52 -(lp296 -sg13 -(dp297 -sbtp298 -asVrfu_list_0 -p299 -(lp300 -sg57 -(lp301 -sVvptool_gitrev -p302 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p303 -sVio_fmt_gitrev -p304 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p305 -sVconfig_gitrev -p306 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p307 -sVymlcfg_gitrev -p308 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p309 -sbtp310 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml new file mode 100644 index 0000000000..c95e043323 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml @@ -0,0 +1,286 @@ +!Feature +next_elt_id: 6 +name: RV32C Control Transfer Instructions +id: 11 +display_order: 11 +subfeatures: !!omap +- 000_C.J: !Subfeature + name: 000_C.J + tag: VP_IP010_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F010_S000_I000 + description: "c.j imm[11:1]\npc += sext(imm)\npc is calculated using signed\ + \ arithmetic\nExpands to jal x0, imm[11:1]." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_C.JAL: !Subfeature + name: 001_C.JAL + tag: VP_IP010_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F010_S001_I000 + description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\ + \ using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F010_S001_I001 + description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\ + \ using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of x1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_C.JR: !Subfeature + name: 002_C.JR + tag: VP_IP010_P002 + next_elt_id: 2 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F010_S002_I000 + description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\ + \ when rs1=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F010_S002_I001 + description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\ + \ when rs1=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_C.JALR: !Subfeature + name: 003_C.JALR + tag: VP_IP010_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F010_S003_I000 + description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ + \ x1, 0(rs1). \nInvalid when rs1=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F010_S003_I001 + description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ + \ x1, 0(rs1). \nInvalid when rs1=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F010_S003_I002 + description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ + \ x1, 0(rs1). \nInvalid when rs1=x0." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nAll bits of x1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_C.BEQZ: !Subfeature + name: 004_C.BEQZ + tag: VP_IP010_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F010_S004_I000 + description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F010_S004_I001 + description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F010_S004_I002 + description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_C.BNEZ: !Subfeature + name: 005_C.BNEZ + tag: VP_IP010_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F010_S005_I000 + description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F010_S005_I001 + description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F010_S005_I002 + description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: "Unprivileged ISA\nChapter 16.4" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck deleted file mode 100644 index 73c3f301f4..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.pck +++ /dev/null @@ -1,672 +0,0 @@ -(VRV32C Load and Store Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I4 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I12 -sVwid_order -p12 -I12 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_C.LWSP -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I3 -sg8 -g17 -sVtag -p23 -VVP_IP009_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F009_S000_I000 -p34 -sVdescription -p35 -Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 16.3 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rd registers are used. -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F009_S000_I001 -p62 -sg35 -Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number -p63 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p64 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -a(V002 -p71 -g1 -(g29 -g3 -Ntp72 -Rp73 -(dp74 -g8 -V002 -p75 -sg23 -VVP_ISA_F009_S000_I002 -p76 -sg35 -Vc.lwsp rd, uimm(x2)\u000ax[rd] = sext(M[x[2] + uimm][0:31])\u000aExpands to lw rd, uimm[7:2](x2). \u000aInvalid when rd=x0.\u000auimm treated as unsigned number -p77 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p78 -sg39 -VOutput result:\u000a\u000ard value is non-zero and zero\u000aAll bits of rd are toggled -p79 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp80 -sg15 -(lp81 -sg52 -(lp82 -sg13 -(dp83 -g55 -I0 -ssbtp84 -asVrfu_list_1 -p85 -(lp86 -sg52 -(lp87 -sg13 -(dp88 -sbtp89 -a(V001_C.SWSP -p90 -g1 -(g18 -g3 -Ntp91 -Rp92 -(dp93 -g22 -I2 -sg8 -g90 -sg23 -VVP_IP009_P001 -p94 -sg25 -(dp95 -sg12 -I1 -sg15 -(lp96 -(V000 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V000 -p101 -sg23 -VVP_ISA_F009_S001_I000 -p102 -sg35 -Vc.swsp rs2, uimm(x2)\u000aM[x[2] + uimm][0:31] = x[rs2]\u000aExpands to sw rs2, uimm[7:2](x2).\u000auimm treated as unsigned number -p103 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p104 -sg39 -VRegister operands:\u000a\u000aAll possible rs2 registers are used. -p105 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -g55 -I0 -ssbtp110 -a(V001 -p111 -g1 -(g29 -g3 -Ntp112 -Rp113 -(dp114 -g8 -V001 -p115 -sg23 -VVP_ISA_F009_S001_I001 -p116 -sg35 -Vc.swsp rs2, uimm(x2)\u000aM[x[2] + uimm][0:31] = x[rs2]\u000aExpands to sw rs2, uimm[7:2](x2).\u000auimm treated as unsigned number -p117 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p118 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled -p119 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp120 -sg15 -(lp121 -sg52 -(lp122 -sg13 -(dp123 -g55 -I0 -ssbtp124 -asg85 -(lp125 -sg52 -(lp126 -sg13 -(dp127 -sbtp128 -a(V002_C.LW -p129 -g1 -(g18 -g3 -Ntp130 -Rp131 -(dp132 -g22 -I3 -sg8 -g129 -sg23 -VVP_IP009_P002 -p133 -sg25 -(dp134 -sg12 -I2 -sg15 -(lp135 -(V000 -p136 -g1 -(g29 -g3 -Ntp137 -Rp138 -(dp139 -g8 -V000 -p140 -sg23 -VVP_ISA_F009_S002_I000 -p141 -sg35 -Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1') -p142 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p143 -sg39 -VRegister operands:\u000a\u000aAll possible rs1` registers are used.\u000aAll possible rd` registers are used.\u000aAll possible register combinations where rs1` == rd` are used -p144 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp145 -sg15 -(lp146 -sg52 -(lp147 -sg13 -(dp148 -g55 -I0 -ssbtp149 -a(V001 -p150 -g1 -(g29 -g3 -Ntp151 -Rp152 -(dp153 -g8 -V001 -p154 -sg23 -VVP_ISA_F009_S002_I001 -p155 -sg35 -Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1') -p156 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p157 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled\u000aAll bits of rs1` are toggled -p158 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp159 -sg15 -(lp160 -sg52 -(lp161 -sg13 -(dp162 -g55 -I0 -ssbtp163 -a(V002 -p164 -g1 -(g29 -g3 -Ntp165 -Rp166 -(dp167 -g8 -V002 -p168 -sg23 -VVP_ISA_F009_S002_I002 -p169 -sg35 -Vc.lw rd', uimm(rs1')\u000ax[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1'\u000aExpands to lw rd', uimm[6:2](rs1') -p170 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p171 -sg39 -VOutput result:\u000a\u000ard` value is non-zero and zero\u000aAll bits of rd are toggled -p172 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp173 -sg15 -(lp174 -sg52 -(lp175 -sg13 -(dp176 -g55 -I0 -ssbtp177 -asg85 -(lp178 -sg52 -(lp179 -sg13 -(dp180 -sbtp181 -a(V003_C.SW -p182 -g1 -(g18 -g3 -Ntp183 -Rp184 -(dp185 -g22 -I2 -sg8 -g182 -sg23 -VVP_IP009_P003 -p186 -sg25 -(dp187 -sg12 -I3 -sg15 -(lp188 -(V000 -p189 -g1 -(g29 -g3 -Ntp190 -Rp191 -(dp192 -g8 -V000 -p193 -sg23 -VVP_ISA_F009_S003_I000 -p194 -sg35 -Vc.sw rs2', uimm(rs1')\u000aM[x[rs1] + uimm][0:31] = x[rs2], where rs2=8+rs2' and rs1=8+rs1'\u000aExpands to sw rs2', uimm[6:2](rs1'). -p195 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p196 -sg39 -VRegister operands:\u000a\u000aAll possible rs1` registers are used.\u000aAll possible rd` registers are used.\u000aAll possible register combinations where rs1` == rd` are used -p197 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp198 -sg15 -(lp199 -sg52 -(lp200 -sg13 -(dp201 -g55 -I0 -ssbtp202 -a(V001 -p203 -g1 -(g29 -g3 -Ntp204 -Rp205 -(dp206 -g8 -V001 -p207 -sg23 -VVP_ISA_F009_S003_I001 -p208 -sg35 -Vc.sw rs2', uimm(rs1')\u000aM[x[rs1] + uimm][0:31] = x[rs2], where rs2=8+rs2' and rs1=8+rs1'\u000aExpands to sw rs2', uimm[6:2](rs1'). -p209 -sg37 -VUnprivileged ISA\u000aChapter 16.3 -p210 -sg39 -VInput operands:\u000a\u000auimm value is non-zero and zero\u000aAll bits of uimm are toggled\u000aAll bits of rs1` are toggled\u000aAll bits of rs2` are toggled -p211 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp212 -sg15 -(lp213 -sg52 -(lp214 -sg13 -(dp215 -g55 -I0 -ssbtp216 -asg85 -(lp217 -sg52 -(lp218 -sg13 -(dp219 -sbtp220 -asVrfu_list_0 -p221 -(lp222 -sg85 -(lp223 -sVvptool_gitrev -p224 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p225 -sVio_fmt_gitrev -p226 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p227 -sVconfig_gitrev -p228 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p229 -sVymlcfg_gitrev -p230 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p231 -sbtp232 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml new file mode 100644 index 0000000000..7fe21ee0d1 --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml @@ -0,0 +1,218 @@ +!Feature +next_elt_id: 4 +name: RV32C Load and Store Instructions +id: 12 +display_order: 12 +subfeatures: !!omap +- 000_C.LWSP: !Subfeature + name: 000_C.LWSP + tag: VP_IP009_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S000_I000 + description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ + \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ + \ number" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S000_I001 + description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ + \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ + \ number" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S000_I002 + description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ + \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ + \ number" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_C.SWSP: !Subfeature + name: 001_C.SWSP + tag: VP_IP009_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S001_I000 + description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\ + \ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S001_I001 + description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\ + \ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_C.LW: !Subfeature + name: 002_C.LW + tag: VP_IP009_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S002_I000 + description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ + \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1` registers are used.\n\ + All possible rd` registers are used.\nAll possible register combinations\ + \ where rs1` == rd` are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S002_I001 + description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ + \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled\nAll bits of rs1` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_F009_S002_I002 + description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ + \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd` value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_C.SW: !Subfeature + name: 003_C.SW + tag: VP_IP009_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F009_S003_I000 + description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\ + \ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')." + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1` registers are used.\n\ + All possible rd` registers are used.\nAll possible register combinations\ + \ where rs1` == rd` are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F009_S003_I001 + description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\ + \ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')." + reqt_doc: "Unprivileged ISA\nChapter 16.3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled\nAll bits of rs1` are toggled\nAll bits of rs2` are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck deleted file mode 100644 index acac417644..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.pck +++ /dev/null @@ -1,824 +0,0 @@ -(VRV32Zicsr Control and Status Register (CSR) Instructions -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I6 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I13 -sVwid_order -p12 -I13 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_CSRRW -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I2 -sg8 -g17 -sVtag -p23 -VVP_IP007_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F007_S000_I000 -p34 -sVdescription -p35 -Vcsrrw rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] -p36 -sVpurpose -p37 -VISA Chapter 9 -p38 -sVverif_goals -p39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used -p40 -sVcoverage_loc -p41 -V -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -g42 -sVstatus -p48 -g42 -sVsimu_target_list -p49 -(lp50 -sg15 -(lp51 -sVrfu_list_2 -p52 -(lp53 -sg13 -(dp54 -Vlock_status -p55 -I0 -ssbtp56 -a(V001 -p57 -g1 -(g29 -g3 -Ntp58 -Rp59 -(dp60 -g8 -V001 -p61 -sg23 -VVP_ISA_F007_S000_I001 -p62 -sg35 -Vcsrrw rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] -p63 -sg37 -VISA Chapter 9 -p64 -sg39 -VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0) -p65 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp66 -sg15 -(lp67 -sg52 -(lp68 -sg13 -(dp69 -g55 -I0 -ssbtp70 -asVrfu_list_1 -p71 -(lp72 -sg52 -(lp73 -sg13 -(dp74 -sbtp75 -a(V001_CSRRS -p76 -g1 -(g18 -g3 -Ntp77 -Rp78 -(dp79 -g22 -I2 -sg8 -g76 -sg23 -VVP_IP007_P001 -p80 -sg25 -(dp81 -sg12 -I1 -sg15 -(lp82 -(V000 -p83 -g1 -(g29 -g3 -Ntp84 -Rp85 -(dp86 -g8 -V000 -p87 -sg23 -VVP_ISA_F007_S001_I000 -p88 -sg35 -Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] | csr\u000aNote that not all bits of csr will be writable. -p89 -sg37 -VISA Chapter 9 -p90 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used -p91 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp92 -sg15 -(lp93 -sg52 -(lp94 -sg13 -(dp95 -g55 -I0 -ssbtp96 -a(V001 -p97 -g1 -(g29 -g3 -Ntp98 -Rp99 -(dp100 -g8 -V001 -p101 -sg23 -VVP_ISA_F007_S001_I001 -p102 -sg35 -Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] | csr\u000aNote that not all bits of csr will be writable. -p103 -sg37 -VISA Chapter 9 -p104 -sg39 -VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0) -p105 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp106 -sg15 -(lp107 -sg52 -(lp108 -sg13 -(dp109 -g55 -I0 -ssbtp110 -asg71 -(lp111 -sg52 -(lp112 -sg13 -(dp113 -sbtp114 -a(V002_CSRRC -p115 -g1 -(g18 -g3 -Ntp116 -Rp117 -(dp118 -g22 -I2 -sg8 -g115 -sg23 -VVP_IP007_P002 -p119 -sg25 -(dp120 -sg12 -I2 -sg15 -(lp121 -(V000 -p122 -g1 -(g29 -g3 -Ntp123 -Rp124 -(dp125 -g8 -V000 -p126 -sg23 -VVP_ISA_F007_S002_I000 -p127 -sg35 -Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = ~[rs1] | csr\u000aNote that not all bits of csr will be writable. -p128 -sg37 -VISA Chapter 9 -p129 -sg39 -VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used -p130 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp131 -sg15 -(lp132 -sg52 -(lp133 -sg13 -(dp134 -g55 -I0 -ssbtp135 -a(V001 -p136 -g1 -(g29 -g3 -Ntp137 -Rp138 -(dp139 -g8 -V001 -p140 -sg23 -VVP_ISA_F007_S002_I001 -p141 -sg35 -Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = ~[rs1] | csr\u000aNote that not all bits of csr will be writable. -p142 -sg37 -VISA Chapter 9 -p143 -sg39 -VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0) -p144 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp145 -sg15 -(lp146 -sg52 -(lp147 -sg13 -(dp148 -g55 -I0 -ssbtp149 -asg71 -(lp150 -sg52 -(lp151 -sg13 -(dp152 -sbtp153 -a(V003_CSRRWI -p154 -g1 -(g18 -g3 -Ntp155 -Rp156 -(dp157 -g22 -I2 -sg8 -g154 -sg23 -VVP_IP007_P003 -p158 -sg25 -(dp159 -sg12 -I3 -sg15 -(lp160 -(V000 -p161 -g1 -(g29 -g3 -Ntp162 -Rp163 -(dp164 -g8 -V000 -p165 -sg23 -VVP_ISA_F007_S003_I000 -p166 -sg35 -Vcsrrwi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0])\u000aIf rd == x0 then CSR is not read. -p167 -sg37 -VISA Chapter 9 -p168 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used -p169 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp170 -sg15 -(lp171 -sg52 -(lp172 -sg13 -(dp173 -g55 -I0 -ssbtp174 -a(V001 -p175 -g1 -(g29 -g3 -Ntp176 -Rp177 -(dp178 -g8 -V001 -p179 -sg23 -VVP_ISA_F007_S003_I001 -p180 -sg35 -Vcsrrwi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0])\u000aIf rd == x0 then CSR is not read. -p181 -sg37 -VISA Chapter 9 -p182 -sg39 -VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled -p183 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp184 -sg15 -(lp185 -sg52 -(lp186 -sg13 -(dp187 -g55 -I0 -ssbtp188 -asg71 -(lp189 -sg52 -(lp190 -sg13 -(dp191 -sbtp192 -a(V004_CSRRSI -p193 -g1 -(g18 -g3 -Ntp194 -Rp195 -(dp196 -g22 -I2 -sg8 -g193 -sg23 -VVP_IP007_P004 -p197 -sg25 -(dp198 -sg12 -I4 -sg15 -(lp199 -(V000 -p200 -g1 -(g29 -g3 -Ntp201 -Rp202 -(dp203 -g8 -V000 -p204 -sg23 -VVP_ISA_F007_S004_I000 -p205 -sg35 -Vcsrrsi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0]) | csr\u000aNote that not all bits of csr will be writable. -p206 -sg37 -VISA Chapter 9 -p207 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used -p208 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp209 -sg15 -(lp210 -sg52 -(lp211 -sg13 -(dp212 -g55 -I0 -ssbtp213 -a(V001 -p214 -g1 -(g29 -g3 -Ntp215 -Rp216 -(dp217 -g8 -V001 -p218 -sg23 -VVP_ISA_F007_S004_I001 -p219 -sg35 -Vcsrrsi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0]) | csr\u000aNote that not all bits of csr will be writable. -p220 -sg37 -VISA Chapter 9 -p221 -sg39 -VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled -p222 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp223 -sg15 -(lp224 -sg52 -(lp225 -sg13 -(dp226 -g55 -I0 -ssbtp227 -asg71 -(lp228 -sg52 -(lp229 -sg13 -(dp230 -sbtp231 -a(V005_CSRRCI -p232 -g1 -(g18 -g3 -Ntp233 -Rp234 -(dp235 -g22 -I2 -sg8 -g232 -sg23 -VVP_IP007_P005 -p236 -sg25 -(dp237 -sg12 -I5 -sg15 -(lp238 -(V000 -p239 -g1 -(g29 -g3 -Ntp240 -Rp241 -(dp242 -g8 -V000 -p243 -sg23 -VVP_ISA_F007_S005_I000 -p244 -sg35 -Vcsrrs rd, imm[4:0], csr\u000ard = Zext([csr]); csr = ~(Zext(imm[4:0])) | csr\u000aNote that not all bits of csr will be writable. -p245 -sg37 -VISA Chapter 9 -p246 -sg39 -VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used -p247 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp248 -sg15 -(lp249 -sg52 -(lp250 -sg13 -(dp251 -g55 -I0 -ssbtp252 -a(V001 -p253 -g1 -(g29 -g3 -Ntp254 -Rp255 -(dp256 -g8 -V001 -p257 -sg23 -VVP_ISA_F007_S005_I001 -p258 -sg35 -Vcsrrs rd, imm[4:0], csr\u000ard = Zext([csr]); csr = ~(Zext(imm[4:0])) | csr\u000aNote that not all bits of csr will be writable. -p259 -sg37 -VISA Chapter 9 -p260 -sg39 -VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled -p261 -sg41 -g42 -sg43 -I3 -sg44 -I3 -sg45 -I1 -sg46 -I56 -sg47 -g42 -sg48 -g42 -sg49 -(lp262 -sg15 -(lp263 -sg52 -(lp264 -sg13 -(dp265 -g55 -I0 -ssbtp266 -asg71 -(lp267 -sg52 -(lp268 -sg13 -(dp269 -sbtp270 -asVrfu_list_0 -p271 -(lp272 -sg71 -(lp273 -sVvptool_gitrev -p274 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p275 -sVio_fmt_gitrev -p276 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p277 -sVconfig_gitrev -p278 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p279 -sVymlcfg_gitrev -p280 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p281 -sbtp282 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml new file mode 100644 index 0000000000..b13e60860e --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml @@ -0,0 +1,263 @@ +!Feature +next_elt_id: 6 +name: RV32Zicsr Control and Status Register (CSR) Instructions +id: 13 +display_order: 13 +subfeatures: !!omap +- 000_CSRRW: !Subfeature + name: 000_CSRRW + tag: VP_IP007_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S000_I000 + description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]" + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\ + All possible rd registers are used\nAll supported CSRs are used\nAll possible\ + \ register combinations where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S000_I001 + description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]" + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\ + \ rs1 != x0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_CSRRS: !Subfeature + name: 001_CSRRS + tag: VP_IP007_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S001_I000 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\ + All possible rd registers are used\nAll supported CSRs are used\nAll possible\ + \ register combinations where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S001_I001 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\ + \ rs1 != x0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_CSRRC: !Subfeature + name: 002_CSRRC + tag: VP_IP007_P002 + next_elt_id: 2 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S002_I000 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\ + All possible rd registers are used\nAll supported CSRs are used\nAll possible\ + \ register combinations where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S002_I001 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\ + \ rs1 != x0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_CSRRWI: !Subfeature + name: 003_CSRRWI + tag: VP_IP007_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S003_I000 + description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\ + If rd == x0 then CSR is not read." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\ + \ supported CSRs are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S003_I001 + description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\ + If rd == x0 then CSR is not read." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\ + All bits of imm[4:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_CSRRSI: !Subfeature + name: 004_CSRRSI + tag: VP_IP007_P004 + next_elt_id: 2 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S004_I000 + description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\ + \ supported CSRs are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S004_I001 + description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\ + All bits of imm[4:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_CSRRCI: !Subfeature + name: 005_CSRRCI + tag: VP_IP007_P005 + next_elt_id: 2 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F007_S005_I000 + description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\ + \ supported CSRs are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_F007_S005_I001 + description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ISA Chapter 9 + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\ + All bits of imm[4:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck b/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck deleted file mode 100644 index d3b9272ec0..0000000000 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.pck +++ /dev/null @@ -1,157 +0,0 @@ -(VRV32Zifencei Instruction-Fetch Fence -p0 -ccopy_reg -_reconstructor -p1 -(cvp_pack -Ip -p2 -c__builtin__ -object -p3 -Ntp4 -Rp5 -(dp6 -Vprop_count -p7 -I1 -sVname -p8 -g0 -sVprop_list -p9 -(dp10 -sVip_num -p11 -I14 -sVwid_order -p12 -I14 -sVrfu_dict -p13 -(dp14 -sVrfu_list -p15 -(lp16 -(V000_FENCE.I -p17 -g1 -(cvp_pack -Prop -p18 -g3 -Ntp19 -Rp20 -(dp21 -Vitem_count -p22 -I1 -sg8 -g17 -sVtag -p23 -VVP_IP006_P000 -p24 -sVitem_list -p25 -(dp26 -sg12 -I0 -sg15 -(lp27 -(V000 -p28 -g1 -(cvp_pack -Item -p29 -g3 -Ntp30 -Rp31 -(dp32 -g8 -V000 -p33 -sg23 -VVP_ISA_F006_S000_I000 -p34 -sVdescription -p35 -VFence.I instruction executed\u000aImplementation is core-specific -p36 -sVpurpose -p37 -VUnprivileged ISA\u000aChapter 3 -p38 -sVverif_goals -p39 -VFence.I instruction is executed -p40 -sVcoverage_loc -p41 -Visacov.rv32zifencei_fence_i_cg -p42 -sVpfc -p43 -I3 -sVtest_type -p44 -I3 -sVcov_method -p45 -I1 -sVcores -p46 -I56 -sVcomments -p47 -V -p48 -sVstatus -p49 -g48 -sVsimu_target_list -p50 -(lp51 -sg15 -(lp52 -sVrfu_list_2 -p53 -(lp54 -sg13 -(dp55 -Vlock_status -p56 -I0 -ssbtp57 -asVrfu_list_1 -p58 -(lp59 -sg53 -(lp60 -sg13 -(dp61 -sbtp62 -asVrfu_list_0 -p63 -(lp64 -sg58 -(lp65 -sVvptool_gitrev -p66 -V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $ -p67 -sVio_fmt_gitrev -p68 -V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $ -p69 -sVconfig_gitrev -p70 -V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $ -p71 -sVymlcfg_gitrev -p72 -V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $ -p73 -sbtp74 -. \ No newline at end of file diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml new file mode 100644 index 0000000000..b12d713c9c --- /dev/null +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml @@ -0,0 +1,32 @@ +!Feature +next_elt_id: 1 +name: RV32Zifencei Instruction-Fetch Fence +id: 14 +display_order: 14 +subfeatures: !!omap +- 000_FENCE.I: !Subfeature + name: 000_FENCE.I + tag: VP_IP006_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_F006_S000_I000 + description: "Fence.I instruction executed\nImplementation is core-specific" + reqt_doc: "Unprivileged ISA\nChapter 3" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Fence.I instruction is executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32zifencei_fence_i_cg + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' From 33d8a6499706639d0f9cfffe1ccf683a545e34dc Mon Sep 17 00:00:00 2001 From: Zbigniew Chamski Date: Mon, 13 Feb 2023 17:59:30 +0100 Subject: [PATCH 9/9] DV plans: Update ISA_RV32 item tags: match feature order, remove duplicates. * cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml: Name tags after feature number used in DB file name. Use 'ISA_RV32' in tag names to match project name. * cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml: Ditto. * cva6/docs/VerifPlans/ISA_RV32/runme.sh (PROJECT_NAME): USe more explicit printable name. (PROJECT_IDENT): Use same name as in directory naming to prevent future ambiguity with 64b ISA. Signed-off-by: Zbigniew Chamski --- cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml | 66 ++++++++--------- cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml | 60 +++++++-------- cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml | 48 ++++++------ cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml | 42 +++++------ cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml | 2 +- cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml | 6 +- cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml | 24 +++--- cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml | 32 ++++---- cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml | 16 ++-- cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml | 72 +++++++++--------- cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml | 86 +++++++++++----------- cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml | 28 +++---- cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml | 20 ++--- cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml | 24 +++--- cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml | 2 +- cva6/docs/VerifPlans/ISA_RV32/runme.sh | 4 +- 16 files changed, 266 insertions(+), 266 deletions(-) diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml index 70b22805da..4fa8fffdf5 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP000.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S000_I000 + tag: VP_ISA_RV32_F000_S000_I000 description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ \ overflow is lost and ignored" reqt_doc: "ISA\nChapter 2.4" @@ -31,7 +31,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S000_I001 + tag: VP_ISA_RV32_F000_S000_I001 description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ \ overflow is lost and ignored" reqt_doc: "ISA\nChapter 2.4" @@ -52,7 +52,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S000_I002 + tag: VP_ISA_RV32_F000_S000_I002 description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ \ overflow is lost and ignored" reqt_doc: "ISA\nChapter 2.4" @@ -76,7 +76,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S001_I000 + tag: VP_ISA_RV32_F000_S001_I000 description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ \ is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -95,7 +95,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S001_I001 + tag: VP_ISA_RV32_F000_S001_I001 description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ \ is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -116,7 +116,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S001_I002 + tag: VP_ISA_RV32_F000_S001_I002 description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ \ is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -140,7 +140,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S002_I000 + tag: VP_ISA_RV32_F000_S002_I000 description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ \ is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -159,7 +159,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S002_I001 + tag: VP_ISA_RV32_F000_S002_I001 description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ \ is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -180,7 +180,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S002_I002 + tag: VP_ISA_RV32_F000_S002_I002 description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ \ is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -204,7 +204,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S003_I000 + tag: VP_ISA_RV32_F000_S003_I000 description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ \ this is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -223,7 +223,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S003_I001 + tag: VP_ISA_RV32_F000_S003_I001 description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ \ this is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -244,7 +244,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S003_I002 + tag: VP_ISA_RV32_F000_S003_I002 description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ \ this is a bitwise, not logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -268,7 +268,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S004_I000 + tag: VP_ISA_RV32_F000_S004_I000 description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ Both imm and rs1 treated as signed numbers" reqt_doc: "ISA\nChapter 2.4" @@ -287,7 +287,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S004_I001 + tag: VP_ISA_RV32_F000_S004_I001 description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ Both imm and rs1 treated as signed numbers" reqt_doc: "ISA\nChapter 2.4" @@ -308,7 +308,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S004_I002 + tag: VP_ISA_RV32_F000_S004_I002 description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ Both imm and rs1 treated as signed numbers" reqt_doc: "ISA\nChapter 2.4" @@ -331,7 +331,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S005_I000 + tag: VP_ISA_RV32_F000_S005_I000 description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ \ 0\nBoth imm and rs1 treated as unsigned numbers" reqt_doc: "ISA\nChapter 2.4" @@ -351,7 +351,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S005_I001 + tag: VP_ISA_RV32_F000_S005_I001 description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ \ 0\nBoth imm and rs1 treated as unsigned numbers" reqt_doc: "ISA\nChapter 2.4" @@ -372,7 +372,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S005_I002 + tag: VP_ISA_RV32_F000_S005_I002 description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ \ 0\nBoth imm and rs1 treated as unsigned numbers" reqt_doc: "ISA\nChapter 2.4" @@ -395,7 +395,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S006_I000 + tag: VP_ISA_RV32_F000_S006_I000 description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ \ into lower bits" reqt_doc: "ISA\nChapter 2.4" @@ -414,7 +414,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S006_I001 + tag: VP_ISA_RV32_F000_S006_I001 description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ \ into lower bits" reqt_doc: "ISA\nChapter 2.4" @@ -434,7 +434,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S006_I002 + tag: VP_ISA_RV32_F000_S006_I002 description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ \ into lower bits" reqt_doc: "ISA\nChapter 2.4" @@ -458,7 +458,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S007_I000 + tag: VP_ISA_RV32_F000_S007_I000 description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ \ into upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -477,7 +477,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S007_I001 + tag: VP_ISA_RV32_F000_S007_I001 description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ \ into upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -497,7 +497,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S007_I002 + tag: VP_ISA_RV32_F000_S007_I002 description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ \ into upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -521,7 +521,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S008_I000 + tag: VP_ISA_RV32_F000_S008_I000 description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\ \ bit is copied into the vacated upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -540,7 +540,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S008_I001 + tag: VP_ISA_RV32_F000_S008_I001 description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\ \ bit is copied into the vacated upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -560,7 +560,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S008_I002 + tag: VP_ISA_RV32_F000_S008_I002 description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ \ into upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -584,7 +584,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S009_I000 + tag: VP_ISA_RV32_F000_S009_I000 description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." reqt_doc: "ISA\nChapter 2.4" ref_mode: '' @@ -600,7 +600,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S009_I001 + tag: VP_ISA_RV32_F000_S009_I001 description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." reqt_doc: "ISA\nChapter 2.4" ref_mode: '' @@ -617,7 +617,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S009_I002 + tag: VP_ISA_RV32_F000_S009_I002 description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." reqt_doc: "ISA\nChapter 2.4" ref_mode: '' @@ -640,7 +640,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F011_S010_I000 + tag: VP_ISA_RV32_F000_S010_I000 description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." reqt_doc: "ISA\nChapter 2.4" @@ -657,7 +657,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F011_S010_I001 + tag: VP_ISA_RV32_F000_S010_I001 description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." reqt_doc: "ISA\nChapter 2.4" @@ -675,7 +675,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F011_S010_I002 + tag: VP_ISA_RV32_F000_S010_I002 description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." reqt_doc: "ISA\nChapter 2.4" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml index 81184060b9..3c9c818463 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP001.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S000_I000 + tag: VP_ISA_RV32_F001_S000_I000 description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ \ and ignored" reqt_doc: "ISA\nChapter 2.4" @@ -33,7 +33,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S000_I001 + tag: VP_ISA_RV32_F001_S000_I001 description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ \ and ignored" reqt_doc: "ISA\nChapter 2.4" @@ -54,7 +54,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S000_I002 + tag: VP_ISA_RV32_F001_S000_I002 description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ \ and ignored" reqt_doc: "ISA\nChapter 2.4" @@ -78,7 +78,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S001_I000 + tag: VP_ISA_RV32_F001_S001_I000 description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" reqt_doc: "ISA\nChapter 2.4" ref_mode: '' @@ -98,7 +98,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S001_I001 + tag: VP_ISA_RV32_F001_S001_I001 description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" reqt_doc: "ISA\nChapter 2.4" ref_mode: '' @@ -118,7 +118,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S001_I002 + tag: VP_ISA_RV32_F001_S001_I002 description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" reqt_doc: "ISA\nChapter 2.4" ref_mode: '' @@ -141,7 +141,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S002_I000 + tag: VP_ISA_RV32_F001_S002_I000 description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -164,7 +164,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S002_I001 + tag: VP_ISA_RV32_F001_S002_I001 description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -185,7 +185,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S002_I002 + tag: VP_ISA_RV32_F001_S002_I002 description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -209,7 +209,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S003_I000 + tag: VP_ISA_RV32_F001_S003_I000 description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -230,7 +230,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S003_I001 + tag: VP_ISA_RV32_F001_S003_I001 description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -251,7 +251,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S003_I002 + tag: VP_ISA_RV32_F001_S003_I002 description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -275,7 +275,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S004_I000 + tag: VP_ISA_RV32_F001_S004_I000 description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -296,7 +296,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S004_I001 + tag: VP_ISA_RV32_F001_S004_I001 description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -317,7 +317,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S004_I002 + tag: VP_ISA_RV32_F001_S004_I002 description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ \ logical operation" reqt_doc: "ISA\nChapter 2.4" @@ -341,7 +341,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S005_I000 + tag: VP_ISA_RV32_F001_S005_I000 description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ \ treated as signed numbers" reqt_doc: "ISA\nChapter 2.4" @@ -362,7 +362,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S005_I001 + tag: VP_ISA_RV32_F001_S005_I001 description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ \ treated as signed numbers" reqt_doc: "ISA\nChapter 2.4" @@ -383,7 +383,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S005_I002 + tag: VP_ISA_RV32_F001_S005_I002 description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ \ treated as signed numbers" reqt_doc: "ISA\nChapter 2.4" @@ -406,7 +406,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S006_I000 + tag: VP_ISA_RV32_F001_S006_I000 description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ \ and rs2 treated as unsigned numbers" reqt_doc: "ISA\nChapter 2.4" @@ -427,7 +427,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S006_I001 + tag: VP_ISA_RV32_F001_S006_I001 description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ \ and rs2 treated as unsigned numbers" reqt_doc: "ISA\nChapter 2.4" @@ -448,7 +448,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S006_I002 + tag: VP_ISA_RV32_F001_S006_I002 description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ \ and rs2 treated as unsigned numbers" reqt_doc: "ISA\nChapter 2.4" @@ -471,7 +471,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S007_I000 + tag: VP_ISA_RV32_F001_S007_I000 description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ \ lower bits" reqt_doc: "ISA\nChapter 2.4" @@ -492,7 +492,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S007_I001 + tag: VP_ISA_RV32_F001_S007_I001 description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ \ lower bits" reqt_doc: "ISA\nChapter 2.4" @@ -512,7 +512,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S007_I002 + tag: VP_ISA_RV32_F001_S007_I002 description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ \ lower bits" reqt_doc: "ISA\nChapter 2.4" @@ -537,7 +537,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S008_I000 + tag: VP_ISA_RV32_F001_S008_I000 description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ \ upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -558,7 +558,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S008_I001 + tag: VP_ISA_RV32_F001_S008_I001 description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ \ upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -578,7 +578,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S008_I002 + tag: VP_ISA_RV32_F001_S008_I002 description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ \ upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -602,7 +602,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F001_S009_I000 + tag: VP_ISA_RV32_F001_S009_I000 description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\ \ is copied into the vacated upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -623,7 +623,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F001_S009_I001 + tag: VP_ISA_RV32_F001_S009_I001 description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\ \ is copied into the vacated upper bits" reqt_doc: "ISA\nChapter 2.4" @@ -643,7 +643,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F001_S009_I002 + tag: VP_ISA_RV32_F001_S009_I002 description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ \ upper bits" reqt_doc: "ISA\nChapter 2.4" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml index a6903df290..1e96260727 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP002.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S000_I000 + tag: VP_ISA_RV32_F002_S000_I000 description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" @@ -30,7 +30,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S000_I001 + tag: VP_ISA_RV32_F002_S000_I001 description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" @@ -49,7 +49,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S000_I002 + tag: VP_ISA_RV32_F002_S000_I002 description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" @@ -73,7 +73,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S001_I000 + tag: VP_ISA_RV32_F002_S001_I000 description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ pc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -92,7 +92,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S001_I001 + tag: VP_ISA_RV32_F002_S001_I001 description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ pc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -111,7 +111,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S001_I002 + tag: VP_ISA_RV32_F002_S001_I002 description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ pc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -134,7 +134,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S002_I000 + tag: VP_ISA_RV32_F002_S002_I000 description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ \ else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -152,7 +152,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S002_I001 + tag: VP_ISA_RV32_F002_S002_I001 description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ \ else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -172,7 +172,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S002_I002 + tag: VP_ISA_RV32_F002_S002_I002 description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ \ else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -195,7 +195,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S003_I000 + tag: VP_ISA_RV32_F002_S003_I000 description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ \ else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -213,7 +213,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S003_I001 + tag: VP_ISA_RV32_F002_S003_I001 description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ \ else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -233,7 +233,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S003_I002 + tag: VP_ISA_RV32_F002_S003_I002 description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ \ else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -256,7 +256,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S004_I000 + tag: VP_ISA_RV32_F002_S004_I000 description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ < rs2) else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -274,7 +274,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S004_I001 + tag: VP_ISA_RV32_F002_S004_I001 description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ < rs2) else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -294,7 +294,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S004_I002 + tag: VP_ISA_RV32_F002_S004_I002 description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ < rs2) else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -317,7 +317,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S005_I000 + tag: VP_ISA_RV32_F002_S005_I000 description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -335,7 +335,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S005_I001 + tag: VP_ISA_RV32_F002_S005_I001 description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -355,7 +355,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S005_I002 + tag: VP_ISA_RV32_F002_S005_I002 description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -378,7 +378,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S006_I000 + tag: VP_ISA_RV32_F002_S006_I000 description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -396,7 +396,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S006_I001 + tag: VP_ISA_RV32_F002_S006_I001 description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -416,7 +416,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S006_I002 + tag: VP_ISA_RV32_F002_S006_I002 description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -439,7 +439,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F002_S007_I000 + tag: VP_ISA_RV32_F002_S007_I000 description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -457,7 +457,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F002_S007_I001 + tag: VP_ISA_RV32_F002_S007_I001 description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.5" @@ -477,7 +477,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F002_S007_I002 + tag: VP_ISA_RV32_F002_S007_I002 description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.5" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml index cf67b09c1e..0fdce09e68 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP003.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S000_I000 + tag: VP_ISA_RV32_F003_S000_I000 description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -31,7 +31,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S000_I001 + tag: VP_ISA_RV32_F003_S000_I001 description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -51,7 +51,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F003_S000_I002 + tag: VP_ISA_RV32_F003_S000_I002 description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -75,7 +75,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S001_I000 + tag: VP_ISA_RV32_F003_S001_I000 description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -94,7 +94,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S001_I001 + tag: VP_ISA_RV32_F003_S001_I001 description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -115,7 +115,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F003_S001_I002 + tag: VP_ISA_RV32_F003_S001_I002 description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -139,7 +139,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S002_I000 + tag: VP_ISA_RV32_F003_S002_I000 description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -158,7 +158,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S002_I001 + tag: VP_ISA_RV32_F003_S002_I001 description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -179,7 +179,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F003_S002_I002 + tag: VP_ISA_RV32_F003_S002_I002 description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ \ using signed arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -203,7 +203,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S003_I000 + tag: VP_ISA_RV32_F003_S003_I000 description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ \ using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -222,7 +222,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S003_I001 + tag: VP_ISA_RV32_F003_S003_I001 description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ \ using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -242,7 +242,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F003_S003_I002 + tag: VP_ISA_RV32_F003_S003_I002 description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ \ using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -266,7 +266,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S004_I000 + tag: VP_ISA_RV32_F003_S004_I000 description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ \ using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -285,7 +285,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S004_I001 + tag: VP_ISA_RV32_F003_S004_I001 description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ \ using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -306,7 +306,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F003_S004_I002 + tag: VP_ISA_RV32_F003_S004_I002 description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ \ using unsigned arithmetic" reqt_doc: "ISA\nChapter 2.6" @@ -330,7 +330,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S005_I000 + tag: VP_ISA_RV32_F003_S005_I000 description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]" reqt_doc: "ISA\nChapter 2.6" ref_mode: '' @@ -347,7 +347,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S005_I001 + tag: VP_ISA_RV32_F003_S005_I001 description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]" reqt_doc: "ISA\nChapter 2.6" ref_mode: '' @@ -372,7 +372,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S006_I000 + tag: VP_ISA_RV32_F003_S006_I000 description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]" reqt_doc: "ISA\nChapter 2.6" ref_mode: '' @@ -389,7 +389,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S006_I001 + tag: VP_ISA_RV32_F003_S006_I001 description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]" reqt_doc: "ISA\nChapter 2.6" ref_mode: '' @@ -414,7 +414,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F003_S007_I000 + tag: VP_ISA_RV32_F003_S007_I000 description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]" reqt_doc: "ISA\nChapter 2.6" ref_mode: '' @@ -431,7 +431,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F003_S007_I001 + tag: VP_ISA_RV32_F003_S007_I001 description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]" reqt_doc: "ISA\nChapter 2.6" ref_mode: '' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml index 01a61498b7..13e0301358 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP004.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F004_S000_I000 + tag: VP_ISA_RV32_F004_S000_I000 description: "Fence operation executed\nImplementation is microarchitecture\ \ specific" reqt_doc: "ISA\nChapter 2.7" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml index 85fd2a35ce..7de113c115 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP005.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F005_S000_I000 + tag: VP_ISA_RV32_F005_S000_I000 description: Software exception vector entered reqt_doc: "ISA\nChapter 2.8" ref_mode: '' @@ -28,7 +28,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F005_S000_I001 + tag: VP_ISA_RV32_F005_S000_I001 description: Return control to a debugger reqt_doc: "ISA\nChapter 2.8" ref_mode: '' @@ -50,7 +50,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F005_S001_I000 + tag: VP_ISA_RV32_F005_S001_I000 description: Return control to a debugger reqt_doc: "ISA\nChapter 2.8" ref_mode: '' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml index fa7e671901..ad8ffc9a42 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP006.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F000_S000_I000 + tag: VP_ISA_RV32_F006_S000_I000 description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ \ is ignored." reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -33,7 +33,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F000_S000_I001 + tag: VP_ISA_RV32_F006_S000_I001 description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ \ is ignored." reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -54,7 +54,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F000_S000_I002 + tag: VP_ISA_RV32_F006_S000_I002 description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ \ is ignored." reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -78,7 +78,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F000_S001_I000 + tag: VP_ISA_RV32_F006_S001_I000 description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ \ rs1 and rs2 treated as signed numbers" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -99,7 +99,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F000_S001_I001 + tag: VP_ISA_RV32_F006_S001_I001 description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ \ rs1 and rs2 treated as signed numbers" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -120,7 +120,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F000_S001_I002 + tag: VP_ISA_RV32_F006_S001_I002 description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ \ rs1 and rs2 treated as signed numbers" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -144,7 +144,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F000_S002_I000 + tag: VP_ISA_RV32_F006_S002_I000 description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ \ rs1 and rs2 treated as unsigned numbers" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -165,7 +165,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F000_S002_I001 + tag: VP_ISA_RV32_F006_S002_I001 description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ \ rs1 and rs2 treated as unsigned numbers" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -186,7 +186,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F000_S002_I002 + tag: VP_ISA_RV32_F006_S002_I002 description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ \ rs1 and rs2 treated as unsigned numbers" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -210,7 +210,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F000_S003_I000 + tag: VP_ISA_RV32_F006_S003_I000 description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ \ treated as signed number, rs2 treated as unsigned number" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -232,7 +232,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F000_S003_I001 + tag: VP_ISA_RV32_F006_S003_I001 description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ \ treated as signed number, rs2 treated as unsigned number" reqt_doc: "Unprivileged ISA\nChapter 7.1" @@ -253,7 +253,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F000_S003_I002 + tag: VP_ISA_RV32_F006_S003_I002 description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ \ treated as signed number, rs2 treated as unsigned number" reqt_doc: "Unprivileged ISA\nChapter 7.1" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml index bb6964c430..729b10f137 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP007.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S000_I000 + tag: VP_ISA_RV32_F007_S000_I000 description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ \ using signed arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -33,7 +33,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S000_I001 + tag: VP_ISA_RV32_F007_S000_I001 description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ \ using signed arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -54,7 +54,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F007_S000_I002 + tag: VP_ISA_RV32_F007_S000_I002 description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ \ using signed arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -74,7 +74,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F007_S000_I003 + tag: VP_ISA_RV32_F007_S000_I003 description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ \ using signed arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -98,7 +98,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S001_I000 + tag: VP_ISA_RV32_F007_S001_I000 description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using signed arithmetic; remainder from the same division than DIV (the\ \ sign of rd equals the sign of rs1)" @@ -120,7 +120,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S001_I001 + tag: VP_ISA_RV32_F007_S001_I001 description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using signed arithmetic; remainder from the same division than DIV (the\ \ sign of rd equals the sign of rs1)" @@ -142,7 +142,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F007_S001_I002 + tag: VP_ISA_RV32_F007_S001_I002 description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using signed arithmetic; remainder from the same division than DIV (the\ \ sign of rd equals the sign of rs1)" @@ -161,7 +161,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F007_S001_I003 + tag: VP_ISA_RV32_F007_S001_I003 description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using signed arithmetic; remainder from the same division than DIV (the\ \ sign of rd equals the sign of rs1)" @@ -186,7 +186,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S002_I000 + tag: VP_ISA_RV32_F007_S002_I000 description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ \ using unsigned arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -207,7 +207,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S002_I001 + tag: VP_ISA_RV32_F007_S002_I001 description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ \ using unsigned arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -228,7 +228,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F007_S002_I002 + tag: VP_ISA_RV32_F007_S002_I002 description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ \ using unsigned arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -246,7 +246,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F007_S002_I003 + tag: VP_ISA_RV32_F007_S002_I003 description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ \ using unsigned arithmetic; rounding towards zero" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -269,7 +269,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S003_I000 + tag: VP_ISA_RV32_F007_S003_I000 description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using unsigned arithmetic; remainder from the same division than DIVU" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -290,7 +290,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S003_I001 + tag: VP_ISA_RV32_F007_S003_I001 description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using unsigned arithmetic; remainder from the same division than DIVU" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -311,7 +311,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F007_S003_I002 + tag: VP_ISA_RV32_F007_S003_I002 description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using unsigned arithmetic; remainder from the same division than DIVU" reqt_doc: "Unprivileged ISA\nChapter 7.2" @@ -329,7 +329,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F007_S003_I003 + tag: VP_ISA_RV32_F007_S003_I003 description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ \ using unsigned arithmetic; remainder from the same division than DIVU" reqt_doc: "Unprivileged ISA\nChapter 7.2" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml index 9677eec744..4c817cebf6 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP008.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S000_I000 + tag: VP_ISA_RV32_F008_S000_I000 description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ \ with the results loaded to rd.\nMisaligned address should cause an exception" reqt_doc: "Unprivileged ISA\nChapter 8.2" @@ -31,7 +31,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S000_I001 + tag: VP_ISA_RV32_F008_S000_I001 description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ \ with the results loaded to rd.\nMisaligned address should cause an exception" reqt_doc: "Unprivileged ISA\nChapter 8.2" @@ -48,7 +48,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S000_I002 + tag: VP_ISA_RV32_F008_S000_I002 description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ \ with the results loaded to rd.\nMisaligned address should cause an exception" reqt_doc: "Unprivileged ISA\nChapter 8.2" @@ -65,7 +65,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F008_S000_I003 + tag: VP_ISA_RV32_F008_S000_I003 description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ \ with the results loaded to rd.\nMisaligned address should cause an exception" reqt_doc: "Unprivileged ISA\nChapter 8.2" @@ -89,7 +89,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S001_I000 + tag: VP_ISA_RV32_F008_S001_I000 description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ \ from a previous LR.W fails, then rd is set to a non-zero value and the\ @@ -112,7 +112,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S001_I001 + tag: VP_ISA_RV32_F008_S001_I001 description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ \ from a previous LR.W fails, then rd is set to a non-zero value and the\ @@ -133,7 +133,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S001_I002 + tag: VP_ISA_RV32_F008_S001_I002 description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ \ from a previous LR.W fails, then rd is set to a non-zero value and the\ @@ -154,7 +154,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F008_S001_I003 + tag: VP_ISA_RV32_F008_S001_I003 description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ \ from a previous LR.W fails, then rd is set to a non-zero value and the\ diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml index 3c1a267e4f..75717fbf13 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP009.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S000_I000 + tag: VP_ISA_RV32_F009_S000_I000 description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ \ to the address at (rs1)" @@ -33,7 +33,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S000_I001 + tag: VP_ISA_RV32_F009_S000_I001 description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ \ to the address at (rs1)" @@ -52,7 +52,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S000_I002 + tag: VP_ISA_RV32_F009_S000_I002 description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ \ to the address at (rs1)" @@ -70,7 +70,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S000_I003 + tag: VP_ISA_RV32_F009_S000_I003 description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ \ to the address at (rs1)" @@ -95,7 +95,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S001_I000 + tag: VP_ISA_RV32_F009_S001_I000 description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and added using signed arithmetic and the result iis then written back\ @@ -117,7 +117,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S001_I001 + tag: VP_ISA_RV32_F009_S001_I001 description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and added using signed arithmetic and the result iis then written back\ @@ -137,7 +137,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S001_I002 + tag: VP_ISA_RV32_F009_S001_I002 description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and added using signed arithmetic and the result iis then written back\ @@ -157,7 +157,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S001_I003 + tag: VP_ISA_RV32_F009_S001_I003 description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and added using signed arithmetic and the result iis then written back\ @@ -183,7 +183,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S002_I000 + tag: VP_ISA_RV32_F009_S002_I000 description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise ANDed and the result iis then written back to the address\ @@ -205,7 +205,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S002_I001 + tag: VP_ISA_RV32_F009_S002_I001 description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise ANDed and the result iis then written back to the address\ @@ -225,7 +225,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S002_I002 + tag: VP_ISA_RV32_F009_S002_I002 description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise ANDed and the result iis then written back to the address\ @@ -244,7 +244,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S002_I003 + tag: VP_ISA_RV32_F009_S002_I003 description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise ANDed and the result iis then written back to the address\ @@ -270,7 +270,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S003_I000 + tag: VP_ISA_RV32_F009_S003_I000 description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ \ bit-wise ORed and the result iis then written back to the address at (rs1)" @@ -291,7 +291,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S003_I001 + tag: VP_ISA_RV32_F009_S003_I001 description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ \ bit-wise ORed and the result iis then written back to the address at (rs1)" @@ -310,7 +310,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S003_I002 + tag: VP_ISA_RV32_F009_S003_I002 description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ \ bit-wise ORed and the result iis then written back to the address at (rs1)" @@ -328,7 +328,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S003_I003 + tag: VP_ISA_RV32_F009_S003_I003 description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ \ bit-wise ORed and the result iis then written back to the address at (rs1)" @@ -353,7 +353,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S004_I000 + tag: VP_ISA_RV32_F009_S004_I000 description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise XORRed and the result iis then written back to the address\ @@ -375,7 +375,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S004_I001 + tag: VP_ISA_RV32_F009_S004_I001 description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise XORRed and the result iis then written back to the address\ @@ -395,7 +395,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S004_I002 + tag: VP_ISA_RV32_F009_S004_I002 description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise XORRed and the result iis then written back to the address\ @@ -414,7 +414,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S004_I003 + tag: VP_ISA_RV32_F009_S004_I003 description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ \ and bit-wise XORRed and the result iis then written back to the address\ @@ -440,7 +440,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S005_I000 + tag: VP_ISA_RV32_F009_S005_I000 description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the largest value\ @@ -462,7 +462,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S005_I001 + tag: VP_ISA_RV32_F009_S005_I001 description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the largest value\ @@ -482,7 +482,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S005_I002 + tag: VP_ISA_RV32_F009_S005_I002 description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the largest value\ @@ -502,7 +502,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S005_I003 + tag: VP_ISA_RV32_F009_S005_I003 description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the largest value\ @@ -528,7 +528,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S006_I000 + tag: VP_ISA_RV32_F009_S006_I000 description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the largest value\ @@ -550,7 +550,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S006_I001 + tag: VP_ISA_RV32_F009_S006_I001 description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the largest value\ @@ -570,7 +570,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S006_I002 + tag: VP_ISA_RV32_F009_S006_I002 description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the largest value\ @@ -589,7 +589,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S006_I003 + tag: VP_ISA_RV32_F009_S006_I003 description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the largest value\ @@ -615,7 +615,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S007_I000 + tag: VP_ISA_RV32_F009_S007_I000 description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the smaller value\ @@ -637,7 +637,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S007_I001 + tag: VP_ISA_RV32_F009_S007_I001 description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the smaller value\ @@ -657,7 +657,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S007_I002 + tag: VP_ISA_RV32_F009_S007_I002 description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the smaller value\ @@ -677,7 +677,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S007_I003 + tag: VP_ISA_RV32_F009_S007_I003 description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming signed numbers and the smaller value\ @@ -703,7 +703,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S008_I000 + tag: VP_ISA_RV32_F009_S008_I000 description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ @@ -725,7 +725,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S008_I001 + tag: VP_ISA_RV32_F009_S008_I001 description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ @@ -745,7 +745,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S008_I002 + tag: VP_ISA_RV32_F009_S008_I002 description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ @@ -764,7 +764,7 @@ subfeatures: !!omap comments: '' - '003': !VerifItem name: '003' - tag: VP_ISA_F009_S008_I003 + tag: VP_ISA_RV32_F009_S008_I003 description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml index 21eb1d64e9..eb4420529d 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP010.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S000_I000 + tag: VP_ISA_RV32_F010_S000_I000 description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\ \ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -29,7 +29,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S000_I001 + tag: VP_ISA_RV32_F010_S000_I001 description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\ \ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -52,7 +52,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S001_I000 + tag: VP_ISA_RV32_F010_S001_I000 description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\ \ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\ \ calculated using signed arithmetic." @@ -70,7 +70,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S001_I001 + tag: VP_ISA_RV32_F010_S001_I001 description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\ \ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\ \ calculated using signed arithmetic." @@ -94,7 +94,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S002_I000 + tag: VP_ISA_RV32_F010_S002_I000 description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." @@ -112,7 +112,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S002_I001 + tag: VP_ISA_RV32_F010_S002_I001 description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." @@ -131,7 +131,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S002_I002 + tag: VP_ISA_RV32_F010_S002_I002 description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." @@ -155,7 +155,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S003_I000 + tag: VP_ISA_RV32_F010_S003_I000 description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\ \ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\ \ signed arithmetic." @@ -175,7 +175,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S003_I001 + tag: VP_ISA_RV32_F010_S003_I001 description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\ \ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\ \ signed arithmetic." @@ -199,7 +199,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S004_I000 + tag: VP_ISA_RV32_F010_S004_I000 description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ \ using signed arithmetic." @@ -217,7 +217,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S004_I001 + tag: VP_ISA_RV32_F010_S004_I001 description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ \ using signed arithmetic." @@ -236,7 +236,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S004_I002 + tag: VP_ISA_RV32_F010_S004_I002 description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ \ using signed arithmetic." @@ -260,7 +260,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S005_I000 + tag: VP_ISA_RV32_F010_S005_I000 description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -277,7 +277,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S005_I001 + tag: VP_ISA_RV32_F010_S005_I001 description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -295,7 +295,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S005_I002 + tag: VP_ISA_RV32_F010_S005_I002 description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -318,7 +318,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S006_I000 + tag: VP_ISA_RV32_F010_S006_I000 description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -335,7 +335,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S006_I001 + tag: VP_ISA_RV32_F010_S006_I001 description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -353,7 +353,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S006_I002 + tag: VP_ISA_RV32_F010_S006_I002 description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -376,7 +376,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S007_I000 + tag: VP_ISA_RV32_F010_S007_I000 description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ \ to srai rd', rd', uimm[5:0]." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -393,7 +393,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S007_I001 + tag: VP_ISA_RV32_F010_S007_I001 description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ \ to srai rd', rd', uimm[5:0]." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -412,7 +412,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S007_I002 + tag: VP_ISA_RV32_F010_S007_I002 description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ \ to srai rd', rd', uimm[5:0]." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -435,7 +435,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S008_I000 + tag: VP_ISA_RV32_F010_S008_I000 description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -452,7 +452,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S008_I001 + tag: VP_ISA_RV32_F010_S008_I001 description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -471,7 +471,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S008_I002 + tag: VP_ISA_RV32_F010_S008_I002 description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -494,7 +494,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S009_I000 + tag: VP_ISA_RV32_F010_S009_I000 description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ \ when rs2=x0 or rd=x0." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -512,7 +512,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S009_I001 + tag: VP_ISA_RV32_F010_S009_I001 description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ \ when rs2=x0 or rd=x0." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -529,7 +529,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S009_I002 + tag: VP_ISA_RV32_F010_S009_I002 description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ \ when rs2=x0 or rd=x0." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -552,7 +552,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S010_I000 + tag: VP_ISA_RV32_F010_S010_I000 description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -569,7 +569,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S010_I001 + tag: VP_ISA_RV32_F010_S010_I001 description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -588,7 +588,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S010_I002 + tag: VP_ISA_RV32_F010_S010_I002 description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -612,7 +612,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S011_I000 + tag: VP_ISA_RV32_F010_S011_I000 description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ \ and rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -629,7 +629,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S011_I001 + tag: VP_ISA_RV32_F010_S011_I001 description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ \ and rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -648,7 +648,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S011_I002 + tag: VP_ISA_RV32_F010_S011_I002 description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ \ and rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -671,7 +671,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S012_I000 + tag: VP_ISA_RV32_F010_S012_I000 description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ \ or rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -688,7 +688,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S012_I001 + tag: VP_ISA_RV32_F010_S012_I001 description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ \ or rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -707,7 +707,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S012_I002 + tag: VP_ISA_RV32_F010_S012_I002 description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ \ or rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -730,7 +730,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S013_I000 + tag: VP_ISA_RV32_F010_S013_I000 description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ \ xor rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -747,7 +747,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S013_I001 + tag: VP_ISA_RV32_F010_S013_I001 description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ \ xor rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -766,7 +766,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S013_I002 + tag: VP_ISA_RV32_F010_S013_I002 description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ \ xor rd', rd', rs2'." reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -789,7 +789,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S014_I000 + tag: VP_ISA_RV32_F010_S014_I000 description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ \ sub rd', rd', rs2'. Arithmetic underflow is ignored" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -806,7 +806,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F008_S014_I001 + tag: VP_ISA_RV32_F010_S014_I001 description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ \ sub rd', rd', rs2'. Arithmetic underflow is ignored" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -825,7 +825,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F008_S014_I002 + tag: VP_ISA_RV32_F010_S014_I002 description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ \ sub rd', rd', rs2'. Arithmetic underflow is ignored" reqt_doc: "Unprivileged ISA\nChapter 16.5" @@ -848,7 +848,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F008_S015_I000 + tag: VP_ISA_RV32_F010_S015_I000 description: "c.ebreak\nRaiseException(Breakpoint)\nExpands to ebreak." reqt_doc: "Unprivileged ISA\nChapter 16.5" ref_mode: '' diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml index c95e043323..38e84fc44e 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP011.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F010_S000_I000 + tag: VP_ISA_RV32_F011_S000_I000 description: "c.j imm[11:1]\npc += sext(imm)\npc is calculated using signed\ \ arithmetic\nExpands to jal x0, imm[11:1]." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -36,7 +36,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F010_S001_I000 + tag: VP_ISA_RV32_F011_S001_I000 description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\ \ using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -54,7 +54,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F010_S001_I001 + tag: VP_ISA_RV32_F011_S001_I001 description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\ \ using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -77,7 +77,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F010_S002_I000 + tag: VP_ISA_RV32_F011_S002_I000 description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\ \ when rs1=x0." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -94,7 +94,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F010_S002_I001 + tag: VP_ISA_RV32_F011_S002_I001 description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\ \ when rs1=x0." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -117,7 +117,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F010_S003_I000 + tag: VP_ISA_RV32_F011_S003_I000 description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ \ x1, 0(rs1). \nInvalid when rs1=x0." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -134,7 +134,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F010_S003_I001 + tag: VP_ISA_RV32_F011_S003_I001 description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ \ x1, 0(rs1). \nInvalid when rs1=x0." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -151,7 +151,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F010_S003_I002 + tag: VP_ISA_RV32_F011_S003_I002 description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ \ x1, 0(rs1). \nInvalid when rs1=x0." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -174,7 +174,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F010_S004_I000 + tag: VP_ISA_RV32_F011_S004_I000 description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -191,7 +191,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F010_S004_I001 + tag: VP_ISA_RV32_F011_S004_I001 description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -208,7 +208,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F010_S004_I002 + tag: VP_ISA_RV32_F011_S004_I002 description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -231,7 +231,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F010_S005_I000 + tag: VP_ISA_RV32_F011_S005_I000 description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -248,7 +248,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F010_S005_I001 + tag: VP_ISA_RV32_F011_S005_I001 description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" @@ -265,7 +265,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F010_S005_I002 + tag: VP_ISA_RV32_F011_S005_I002 description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." reqt_doc: "Unprivileged ISA\nChapter 16.4" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml index 7fe21ee0d1..776d2d4657 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP012.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S000_I000 + tag: VP_ISA_RV32_F012_S000_I000 description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ \ number" @@ -30,7 +30,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S000_I001 + tag: VP_ISA_RV32_F012_S000_I001 description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ \ number" @@ -49,7 +49,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S000_I002 + tag: VP_ISA_RV32_F012_S000_I002 description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ \ number" @@ -74,7 +74,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S001_I000 + tag: VP_ISA_RV32_F012_S001_I000 description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\ \ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number" reqt_doc: "Unprivileged ISA\nChapter 16.3" @@ -91,7 +91,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S001_I001 + tag: VP_ISA_RV32_F012_S001_I001 description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\ \ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number" reqt_doc: "Unprivileged ISA\nChapter 16.3" @@ -115,7 +115,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S002_I000 + tag: VP_ISA_RV32_F012_S002_I000 description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" reqt_doc: "Unprivileged ISA\nChapter 16.3" @@ -134,7 +134,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S002_I001 + tag: VP_ISA_RV32_F012_S002_I001 description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" reqt_doc: "Unprivileged ISA\nChapter 16.3" @@ -152,7 +152,7 @@ subfeatures: !!omap comments: '' - '002': !VerifItem name: '002' - tag: VP_ISA_F009_S002_I002 + tag: VP_ISA_RV32_F012_S002_I002 description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" reqt_doc: "Unprivileged ISA\nChapter 16.3" @@ -176,7 +176,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F009_S003_I000 + tag: VP_ISA_RV32_F012_S003_I000 description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\ \ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')." reqt_doc: "Unprivileged ISA\nChapter 16.3" @@ -195,7 +195,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F009_S003_I001 + tag: VP_ISA_RV32_F012_S003_I001 description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\ \ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')." reqt_doc: "Unprivileged ISA\nChapter 16.3" diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml index b13e60860e..2cd64fbfcd 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP013.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S000_I000 + tag: VP_ISA_RV32_F013_S000_I000 description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]" reqt_doc: ISA Chapter 9 ref_mode: '' @@ -30,7 +30,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S000_I001 + tag: VP_ISA_RV32_F013_S000_I001 description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]" reqt_doc: ISA Chapter 9 ref_mode: '' @@ -53,7 +53,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S001_I000 + tag: VP_ISA_RV32_F013_S001_I000 description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\ \ that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -72,7 +72,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S001_I001 + tag: VP_ISA_RV32_F013_S001_I001 description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\ \ that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -96,7 +96,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S002_I000 + tag: VP_ISA_RV32_F013_S002_I000 description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\ \ that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -115,7 +115,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S002_I001 + tag: VP_ISA_RV32_F013_S002_I001 description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\ \ that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -139,7 +139,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S003_I000 + tag: VP_ISA_RV32_F013_S003_I000 description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\ If rd == x0 then CSR is not read." reqt_doc: ISA Chapter 9 @@ -157,7 +157,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S003_I001 + tag: VP_ISA_RV32_F013_S003_I001 description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\ If rd == x0 then CSR is not read." reqt_doc: ISA Chapter 9 @@ -181,7 +181,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S004_I000 + tag: VP_ISA_RV32_F013_S004_I000 description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\ \ | csr\nNote that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -199,7 +199,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S004_I001 + tag: VP_ISA_RV32_F013_S004_I001 description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\ \ | csr\nNote that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -223,7 +223,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F007_S005_I000 + tag: VP_ISA_RV32_F013_S005_I000 description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\ \ | csr\nNote that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 @@ -241,7 +241,7 @@ subfeatures: !!omap comments: '' - '001': !VerifItem name: '001' - tag: VP_ISA_F007_S005_I001 + tag: VP_ISA_RV32_F013_S005_I001 description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\ \ | csr\nNote that not all bits of csr will be writable." reqt_doc: ISA Chapter 9 diff --git a/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml b/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml index b12d713c9c..b4fbf21f97 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml +++ b/cva6/docs/VerifPlans/ISA_RV32/VP_IP014.yml @@ -12,7 +12,7 @@ subfeatures: !!omap items: !!omap - '000': !VerifItem name: '000' - tag: VP_ISA_F006_S000_I000 + tag: VP_ISA_RV32_F014_S000_I000 description: "Fence.I instruction executed\nImplementation is core-specific" reqt_doc: "Unprivileged ISA\nChapter 3" ref_mode: '' diff --git a/cva6/docs/VerifPlans/ISA_RV32/runme.sh b/cva6/docs/VerifPlans/ISA_RV32/runme.sh index b301c78503..0af7efb8db 100644 --- a/cva6/docs/VerifPlans/ISA_RV32/runme.sh +++ b/cva6/docs/VerifPlans/ISA_RV32/runme.sh @@ -17,11 +17,11 @@ export PLATFORM_TOP_DIR="$ROOTDIR" # Set the printable name for the project that will be used # in the human-readable documentation. -export PROJECT_NAME="ISA" +export PROJECT_NAME="ISA RISC-V 32b" # Set the alphanumerical identifier of the project that # will be used to construct file names etc. -export PROJECT_IDENT="ISA" +export PROJECT_IDENT="ISA_RV32" # Set the destination directory of Markdown files for this project. # Since it will be used by VPTOOL, it shall NOT be a relative path.