diff --git a/core/cva6.sv b/core/cva6.sv index b2cade53a6..fdae5afe79 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -33,12 +33,12 @@ module cva6 // branchpredict scoreboard entry // this is the struct which we will inject into the pipeline to guide the various // units towards the correct branch decision and resolve - parameter type branchpredict_sbe_t = struct packed { + localparam type branchpredict_sbe_t = struct packed { cf_t cf; // type of control flow prediction logic [riscv::VLEN-1:0] predict_address; // target address at which to jump, or not }, - parameter type exception_t = struct packed { + localparam type exception_t = struct packed { logic [riscv::XLEN-1:0] cause; // cause of exception logic [riscv::XLEN-1:0] tval; // additional information of causing exception (e.g.: instruction causing it), // address of LD/ST fault @@ -47,25 +47,25 @@ module cva6 // cache request ports // I$ address translation requests - parameter type icache_areq_t = struct packed { + localparam type icache_areq_t = struct packed { logic fetch_valid; // address translation valid logic [riscv::PLEN-1:0] fetch_paddr; // physical address in exception_t fetch_exception; // exception occurred during fetch }, - parameter type icache_arsp_t = struct packed { + localparam type icache_arsp_t = struct packed { logic fetch_req; // address translation request logic [riscv::VLEN-1:0] fetch_vaddr; // virtual address out }, // I$ data requests - parameter type icache_dreq_t = struct packed { + localparam type icache_dreq_t = struct packed { logic req; // we request a new word logic kill_s1; // kill the current request logic kill_s2; // kill the last request logic spec; // request is speculative logic [riscv::VLEN-1:0] vaddr; // 1st cycle: 12 bit index is taken for lookup }, - parameter type icache_drsp_t = struct packed { + localparam type icache_drsp_t = struct packed { logic ready; // icache is ready logic valid; // signals a valid read logic [ariane_pkg::FETCH_WIDTH-1:0] data; // 2+ cycle out: tag @@ -76,7 +76,7 @@ module cva6 // IF/ID Stage // store the decompressed instruction - parameter type fetch_entry_t = struct packed { + localparam type fetch_entry_t = struct packed { logic [riscv::VLEN-1:0] address; // the address of the instructions from below logic [31:0] instruction; // instruction word branchpredict_sbe_t branch_predict; // this field contains branch prediction information regarding the forward branch path @@ -84,7 +84,7 @@ module cva6 }, // ID/EX/WB Stage - parameter type scoreboard_entry_t = struct packed { + localparam type scoreboard_entry_t = struct packed { logic [riscv::VLEN-1:0] pc; // PC of instruction logic [TRANS_ID_BITS-1:0] trans_id; // this can potentially be simplified, we could index the scoreboard entry // with the transaction id in any case make the width more generic @@ -112,7 +112,7 @@ module cva6 // this is the struct we get back from ex stage and we will use it to update // all the necessary data structures // bp_resolve_t - parameter type bp_resolve_t = struct packed { + localparam type bp_resolve_t = struct packed { logic valid; // prediction with all its values is valid logic [riscv::VLEN-1:0] pc; // PC of predict or mis-predict logic [riscv::VLEN-1:0] target_address; // target address at which to jump, or not @@ -123,7 +123,7 @@ module cva6 // All information needed to determine whether we need to associate an interrupt // with the corresponding instruction or not. - parameter type irq_ctrl_t = struct packed { + localparam type irq_ctrl_t = struct packed { logic [riscv::XLEN-1:0] mie; logic [riscv::XLEN-1:0] mip; logic [riscv::XLEN-1:0] mideleg; @@ -131,7 +131,7 @@ module cva6 logic global_enable; }, - parameter type lsu_ctrl_t = struct packed { + localparam type lsu_ctrl_t = struct packed { logic valid; logic [riscv::VLEN-1:0] vaddr; logic overflow; @@ -142,7 +142,7 @@ module cva6 logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id; }, - parameter type fu_data_t = struct packed { + localparam type fu_data_t = struct packed { fu_t fu; fu_op operation; logic [riscv::XLEN-1:0] operand_a; @@ -151,13 +151,13 @@ module cva6 logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id; }, - parameter type icache_req_t = struct packed { + localparam type icache_req_t = struct packed { logic [$clog2(ariane_pkg::ICACHE_SET_ASSOC)-1:0] way; // way to replace logic [riscv::PLEN-1:0] paddr; // physical address logic nc; // noncacheable logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) }, - parameter type icache_rtrn_t = struct packed { + localparam type icache_rtrn_t = struct packed { wt_cache_pkg::icache_in_t rtype; // see definitions above logic [ariane_pkg::ICACHE_LINE_WIDTH-1:0] data; // full cache line width logic [ariane_pkg::ICACHE_USER_LINE_WIDTH-1:0] user; // user bits @@ -171,7 +171,7 @@ module cva6 }, // D$ data requests - parameter type dcache_req_i_t = struct packed { + localparam type dcache_req_i_t = struct packed { logic [DCACHE_INDEX_WIDTH-1:0] address_index; logic [DCACHE_TAG_WIDTH-1:0] address_tag; logic [riscv::XLEN-1:0] data_wdata; @@ -185,7 +185,7 @@ module cva6 logic tag_valid; }, - parameter type dcache_req_o_t = struct packed { + localparam type dcache_req_o_t = struct packed { logic data_gnt; logic data_rvalid; logic [DCACHE_TID_WIDTH-1:0] data_rid;