diff --git a/prj_config_default.teros b/prj_config_default.teros index 21d74a64..ca46fb30 100644 --- a/prj_config_default.teros +++ b/prj_config_default.teros @@ -59,7 +59,7 @@ { "vivado":{ "installation_path":"", - "part":"XC7Z010", + "part":"xc7z010clg400-1", "pnr":"vivado" } }, @@ -83,8 +83,8 @@ "quartus":{ "installation_path":"", "board_device_index":"", - "family":"", - "device":"", + "family":"Cyclone V", + "device":"5CSXFC6D6F31C8ES", "quartus_options":"", "dse_options":"" } diff --git a/resources/project_manager/examples/quartus/blinky.v b/resources/project_manager/examples/quartus/blinky.v new file mode 100644 index 00000000..2a1c67d9 --- /dev/null +++ b/resources/project_manager/examples/quartus/blinky.v @@ -0,0 +1,16 @@ +module blinky + #(parameter clk_freq_hz = 0) + (input clk, + output reg q = 1'b0); + + reg [$clog2(clk_freq_hz)-1:0] count = 0; + + always @(posedge clk) begin + count <= count + 1; + if (count == clk_freq_hz-1) begin + q <= !q; + count <= 0; + end + end + +endmodule diff --git a/resources/project_manager/examples/quartus/de1_soc_revF.sdc b/resources/project_manager/examples/quartus/de1_soc_revF.sdc new file mode 100644 index 00000000..ca22ae22 --- /dev/null +++ b/resources/project_manager/examples/quartus/de1_soc_revF.sdc @@ -0,0 +1,8 @@ +# Main system clock (50 Mhz) +create_clock -name "clk" -period 20.000ns [get_ports {clk}] + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty diff --git a/resources/project_manager/examples/quartus/pinmap.tcl b/resources/project_manager/examples/quartus/pinmap.tcl new file mode 100644 index 00000000..31e93e13 --- /dev/null +++ b/resources/project_manager/examples/quartus/pinmap.tcl @@ -0,0 +1,11 @@ +# +# Clock +# +set_location_assignment PIN_AF14 -to clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk + +# +# LEDR0 +# +set_location_assignment PIN_V16 -to q +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q diff --git a/resources/project_manager/examples/quartus/project.yml b/resources/project_manager/examples/quartus/project.yml new file mode 100644 index 00000000..96d3a9d3 --- /dev/null +++ b/resources/project_manager/examples/quartus/project.yml @@ -0,0 +1,26 @@ +toplevel: blinky +name: project_quartus +files: + - name: "pinmap.tcl" + file_type: tclSource + is_include_file: false + include_path: "" + logical_name: "" + - name: "de1_soc_revF.sdc" + file_type: SDC + is_include_file: false + include_path: "" + logical_name: "" + - name: "blinky.v" + file_type: "verilogSource-2005" + is_include_file: false + include_path: "" + logical_name: "" +tool_options: + quartus: + installation_path: "" + board_device_index: "" + family: "Cyclone\x20V" + device: 5CSXFC6D6F31C8ES + quartus_options: "" + dse_options: "" \ No newline at end of file diff --git a/resources/release_notes/group_ports.png b/resources/release_notes/group_ports.png deleted file mode 100644 index 506fd7c0..00000000 Binary files a/resources/release_notes/group_ports.png and /dev/null differ diff --git a/resources/release_notes/release-notes.html b/resources/release_notes/release-notes.html index 7f64b243..1761cc85 100644 --- a/resources/release_notes/release-notes.html +++ b/resources/release_notes/release-notes.html @@ -7,18 +7,35 @@ -

Release notes 0.1.4

+

Release notes 0.2.0

+ +

Documentation

+

Take a look at the documentation + https://terostechnology.github.io/terosHDLdoc/

+

+
+ + +

Project manager

+

+

+

+

Editor


@@ -27,13 +44,21 @@

Editor

Documenter


-image + + +

User examples

+

Take a look at the documentation + https://github.com/TerosTechnology/teroshdl-examples

+

+

Other improvements

@@ -41,24 +66,11 @@

Other improvements


-

Small bugs fixed

-

-

-

-
- -

Documentation

-

Take a look at the documentation - https://terostechnology.github.io/terosHDLdoc/

-

-
+ diff --git a/src/lib/project_manager/tools/edalize.ts b/src/lib/project_manager/tools/edalize.ts index 5ebae771..85c97a27 100644 --- a/src/lib/project_manager/tools/edalize.ts +++ b/src/lib/project_manager/tools/edalize.ts @@ -79,9 +79,21 @@ export class Edalize extends tool_base.Tool_base{ } set_builds(simulator_name, project_name, top_level){ - if (simulator_name !== 'vivado'){ - return []; + let builds; + switch (simulator_name) { + case 'vivado': + builds = this.vivado_builds( project_name, top_level); + break; + case 'quartus': + builds = this.quartus_builds( project_name, top_level); + break; + default: + builds = []; } + return builds; + } + + vivado_builds( project_name, top_level){ const homedir = require('os').homedir(); let runs_folder = `${project_name}.runs`; let synt_file = `${top_level}_utilization_synth.rpt`; @@ -90,7 +102,7 @@ export class Edalize extends tool_base.Tool_base{ let synt_path = path_lib.join(homedir, '.teroshdl', 'build', runs_folder, 'synth_1', synt_file); let imp_path = path_lib.join(homedir, '.teroshdl', 'build', runs_folder, 'impl_1', imp_file); let time_path = path_lib.join(homedir, '.teroshdl', 'build', runs_folder, 'impl_1', time_file); - + let builds = [ { name: 'Synthesis utilization design information', @@ -107,7 +119,33 @@ export class Edalize extends tool_base.Tool_base{ ]; return builds; } + + quartus_builds( project_name, top_level){ + const homedir = require('os').homedir(); + let synt_file = `${top_level}.map.summary`; + let imp_file = `${top_level}.fit.summary`; + let time_file = `${top_level}.sta.summary`; + let synt_path = path_lib.join(homedir, '.teroshdl', 'build', synt_file); + let imp_path = path_lib.join(homedir, '.teroshdl', 'build', imp_file); + let time_path = path_lib.join(homedir, '.teroshdl', 'build', time_file); + let builds = [ + { + name: 'Synthesis design information', + location: synt_path + }, + { + name: 'Place & route design information', + location: imp_path + }, + { + name: 'Timming report', + location: time_path + } + ]; + return builds; + } + open_waveform_gtkwave(){ let shell = require('shelljs'); let command = `gtkwave ${this.complete_waveform_path}`;